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[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29 #include "vi.h"
30 #include "vid.h"
31
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
41
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44
45 #include "tonga_sdma_pkt_open.h"
46
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
63
64
65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
66 {
67 SDMA0_REGISTER_OFFSET,
68 SDMA1_REGISTER_OFFSET
69 };
70
71 static const u32 golden_settings_tonga_a11[] =
72 {
73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
83 };
84
85 static const u32 tonga_mgcg_cgcg_init[] =
86 {
87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
89 };
90
91 static const u32 golden_settings_fiji_a10[] =
92 {
93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
101 };
102
103 static const u32 fiji_mgcg_cgcg_init[] =
104 {
105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
107 };
108
109 static const u32 golden_settings_polaris11_a11[] =
110 {
111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
121 };
122
123 static const u32 golden_settings_polaris10_a11[] =
124 {
125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135 };
136
137 static const u32 cz_golden_settings_a11[] =
138 {
139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
151 };
152
153 static const u32 cz_mgcg_cgcg_init[] =
154 {
155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
157 };
158
159 static const u32 stoney_golden_settings_a11[] =
160 {
161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
165 };
166
167 static const u32 stoney_mgcg_cgcg_init[] =
168 {
169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
170 };
171
172 /*
173 * sDMA - System DMA
174 * Starting with CIK, the GPU has new asynchronous
175 * DMA engines. These engines are used for compute
176 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 * and each one supports 1 ring buffer used for gfx
178 * and 2 queues used for compute.
179 *
180 * The programming model is very similar to the CP
181 * (ring buffer, IBs, etc.), but sDMA has it's own
182 * packet format that is different from the PM4 format
183 * used by the CP. sDMA supports copying data, writing
184 * embedded data, solid fills, and a number of other
185 * things. It also has support for tiling/detiling of
186 * buffers.
187 */
188
189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
190 {
191 switch (adev->asic_type) {
192 case CHIP_FIJI:
193 amdgpu_program_register_sequence(adev,
194 fiji_mgcg_cgcg_init,
195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
196 amdgpu_program_register_sequence(adev,
197 golden_settings_fiji_a10,
198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
199 break;
200 case CHIP_TONGA:
201 amdgpu_program_register_sequence(adev,
202 tonga_mgcg_cgcg_init,
203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
204 amdgpu_program_register_sequence(adev,
205 golden_settings_tonga_a11,
206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
207 break;
208 case CHIP_POLARIS11:
209 amdgpu_program_register_sequence(adev,
210 golden_settings_polaris11_a11,
211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
212 break;
213 case CHIP_POLARIS10:
214 amdgpu_program_register_sequence(adev,
215 golden_settings_polaris10_a11,
216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
217 break;
218 case CHIP_CARRIZO:
219 amdgpu_program_register_sequence(adev,
220 cz_mgcg_cgcg_init,
221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
222 amdgpu_program_register_sequence(adev,
223 cz_golden_settings_a11,
224 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
225 break;
226 case CHIP_STONEY:
227 amdgpu_program_register_sequence(adev,
228 stoney_mgcg_cgcg_init,
229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
230 amdgpu_program_register_sequence(adev,
231 stoney_golden_settings_a11,
232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
233 break;
234 default:
235 break;
236 }
237 }
238
239 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
240 {
241 int i;
242 for (i = 0; i < adev->sdma.num_instances; i++) {
243 release_firmware(adev->sdma.instance[i].fw);
244 adev->sdma.instance[i].fw = NULL;
245 }
246 }
247
248 /**
249 * sdma_v3_0_init_microcode - load ucode images from disk
250 *
251 * @adev: amdgpu_device pointer
252 *
253 * Use the firmware interface to load the ucode images into
254 * the driver (not loaded into hw).
255 * Returns 0 on success, error on failure.
256 */
257 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
258 {
259 const char *chip_name;
260 char fw_name[30];
261 int err = 0, i;
262 struct amdgpu_firmware_info *info = NULL;
263 const struct common_firmware_header *header = NULL;
264 const struct sdma_firmware_header_v1_0 *hdr;
265
266 DRM_DEBUG("\n");
267
268 switch (adev->asic_type) {
269 case CHIP_TONGA:
270 chip_name = "tonga";
271 break;
272 case CHIP_FIJI:
273 chip_name = "fiji";
274 break;
275 case CHIP_POLARIS11:
276 chip_name = "polaris11";
277 break;
278 case CHIP_POLARIS10:
279 chip_name = "polaris10";
280 break;
281 case CHIP_CARRIZO:
282 chip_name = "carrizo";
283 break;
284 case CHIP_STONEY:
285 chip_name = "stoney";
286 break;
287 default: BUG();
288 }
289
290 for (i = 0; i < adev->sdma.num_instances; i++) {
291 if (i == 0)
292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
293 else
294 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
295 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
296 if (err)
297 goto out;
298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
299 if (err)
300 goto out;
301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
304 if (adev->sdma.instance[i].feature_version >= 20)
305 adev->sdma.instance[i].burst_nop = true;
306
307 if (adev->firmware.smu_load) {
308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
310 info->fw = adev->sdma.instance[i].fw;
311 header = (const struct common_firmware_header *)info->fw->data;
312 adev->firmware.fw_size +=
313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
314 }
315 }
316 out:
317 if (err) {
318 printk(KERN_ERR
319 "sdma_v3_0: Failed to load firmware \"%s\"\n",
320 fw_name);
321 for (i = 0; i < adev->sdma.num_instances; i++) {
322 release_firmware(adev->sdma.instance[i].fw);
323 adev->sdma.instance[i].fw = NULL;
324 }
325 }
326 return err;
327 }
328
329 /**
330 * sdma_v3_0_ring_get_rptr - get the current read pointer
331 *
332 * @ring: amdgpu ring pointer
333 *
334 * Get the current rptr from the hardware (VI+).
335 */
336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
337 {
338 u32 rptr;
339
340 /* XXX check if swapping is necessary on BE */
341 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
342
343 return rptr;
344 }
345
346 /**
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
348 *
349 * @ring: amdgpu ring pointer
350 *
351 * Get the current wptr from the hardware (VI+).
352 */
353 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
354 {
355 struct amdgpu_device *adev = ring->adev;
356 u32 wptr;
357
358 if (ring->use_doorbell) {
359 /* XXX check if swapping is necessary on BE */
360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
361 } else {
362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
363
364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
365 }
366
367 return wptr;
368 }
369
370 /**
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
372 *
373 * @ring: amdgpu ring pointer
374 *
375 * Write the wptr back to the hardware (VI+).
376 */
377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
378 {
379 struct amdgpu_device *adev = ring->adev;
380
381 if (ring->use_doorbell) {
382 /* XXX check if swapping is necessary on BE */
383 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
384 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
385 } else {
386 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
387
388 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
389 }
390 }
391
392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
393 {
394 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
395 int i;
396
397 for (i = 0; i < count; i++)
398 if (sdma && sdma->burst_nop && (i == 0))
399 amdgpu_ring_write(ring, ring->nop |
400 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
401 else
402 amdgpu_ring_write(ring, ring->nop);
403 }
404
405 /**
406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
407 *
408 * @ring: amdgpu ring pointer
409 * @ib: IB object to schedule
410 *
411 * Schedule an IB in the DMA ring (VI).
412 */
413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
414 struct amdgpu_ib *ib,
415 unsigned vm_id, bool ctx_switch)
416 {
417 u32 vmid = vm_id & 0xf;
418
419 /* IB packet must end on a 8 DW boundary */
420 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
421
422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
424 /* base must be 32 byte aligned */
425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
427 amdgpu_ring_write(ring, ib->length_dw);
428 amdgpu_ring_write(ring, 0);
429 amdgpu_ring_write(ring, 0);
430
431 }
432
433 /**
434 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
435 *
436 * @ring: amdgpu ring pointer
437 *
438 * Emit an hdp flush packet on the requested DMA ring.
439 */
440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
441 {
442 u32 ref_and_mask = 0;
443
444 if (ring == &ring->adev->sdma.instance[0].ring)
445 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
446 else
447 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
448
449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
450 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
451 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
452 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
453 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
454 amdgpu_ring_write(ring, ref_and_mask); /* reference */
455 amdgpu_ring_write(ring, ref_and_mask); /* mask */
456 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
457 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
458 }
459
460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
461 {
462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
463 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
464 amdgpu_ring_write(ring, mmHDP_DEBUG0);
465 amdgpu_ring_write(ring, 1);
466 }
467
468 /**
469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
470 *
471 * @ring: amdgpu ring pointer
472 * @fence: amdgpu fence object
473 *
474 * Add a DMA fence packet to the ring to write
475 * the fence seq number and DMA trap packet to generate
476 * an interrupt if needed (VI).
477 */
478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
479 unsigned flags)
480 {
481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
482 /* write the fence */
483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
484 amdgpu_ring_write(ring, lower_32_bits(addr));
485 amdgpu_ring_write(ring, upper_32_bits(addr));
486 amdgpu_ring_write(ring, lower_32_bits(seq));
487
488 /* optionally write high bits as well */
489 if (write64bit) {
490 addr += 4;
491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
492 amdgpu_ring_write(ring, lower_32_bits(addr));
493 amdgpu_ring_write(ring, upper_32_bits(addr));
494 amdgpu_ring_write(ring, upper_32_bits(seq));
495 }
496
497 /* generate an interrupt */
498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
499 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
500 }
501
502 unsigned init_cond_exec(struct amdgpu_ring *ring)
503 {
504 unsigned ret;
505 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
506 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
507 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
508 amdgpu_ring_write(ring, 1);
509 ret = ring->wptr;/* this is the offset we need patch later */
510 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
511 return ret;
512 }
513
514 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
515 {
516 unsigned cur;
517 BUG_ON(ring->ring[offset] != 0x55aa55aa);
518
519 cur = ring->wptr - 1;
520 if (likely(cur > offset))
521 ring->ring[offset] = cur - offset;
522 else
523 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
524 }
525
526
527 /**
528 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
529 *
530 * @adev: amdgpu_device pointer
531 *
532 * Stop the gfx async dma ring buffers (VI).
533 */
534 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
535 {
536 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
537 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
538 u32 rb_cntl, ib_cntl;
539 int i;
540
541 if ((adev->mman.buffer_funcs_ring == sdma0) ||
542 (adev->mman.buffer_funcs_ring == sdma1))
543 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
544
545 for (i = 0; i < adev->sdma.num_instances; i++) {
546 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
547 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
548 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
549 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
550 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
551 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
552 }
553 sdma0->ready = false;
554 sdma1->ready = false;
555 }
556
557 /**
558 * sdma_v3_0_rlc_stop - stop the compute async dma engines
559 *
560 * @adev: amdgpu_device pointer
561 *
562 * Stop the compute async dma queues (VI).
563 */
564 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
565 {
566 /* XXX todo */
567 }
568
569 /**
570 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
571 *
572 * @adev: amdgpu_device pointer
573 * @enable: enable/disable the DMA MEs context switch.
574 *
575 * Halt or unhalt the async dma engines context switch (VI).
576 */
577 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
578 {
579 u32 f32_cntl;
580 int i;
581
582 for (i = 0; i < adev->sdma.num_instances; i++) {
583 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
584 if (enable)
585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
586 AUTO_CTXSW_ENABLE, 1);
587 else
588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
589 AUTO_CTXSW_ENABLE, 0);
590 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
591 }
592 }
593
594 /**
595 * sdma_v3_0_enable - stop the async dma engines
596 *
597 * @adev: amdgpu_device pointer
598 * @enable: enable/disable the DMA MEs.
599 *
600 * Halt or unhalt the async dma engines (VI).
601 */
602 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
603 {
604 u32 f32_cntl;
605 int i;
606
607 if (!enable) {
608 sdma_v3_0_gfx_stop(adev);
609 sdma_v3_0_rlc_stop(adev);
610 }
611
612 for (i = 0; i < adev->sdma.num_instances; i++) {
613 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
614 if (enable)
615 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
616 else
617 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
618 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
619 }
620 }
621
622 /**
623 * sdma_v3_0_gfx_resume - setup and start the async dma engines
624 *
625 * @adev: amdgpu_device pointer
626 *
627 * Set up the gfx DMA ring buffers and enable them (VI).
628 * Returns 0 for success, error for failure.
629 */
630 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
631 {
632 struct amdgpu_ring *ring;
633 u32 rb_cntl, ib_cntl;
634 u32 rb_bufsz;
635 u32 wb_offset;
636 u32 doorbell;
637 int i, j, r;
638
639 for (i = 0; i < adev->sdma.num_instances; i++) {
640 ring = &adev->sdma.instance[i].ring;
641 wb_offset = (ring->rptr_offs * 4);
642
643 mutex_lock(&adev->srbm_mutex);
644 for (j = 0; j < 16; j++) {
645 vi_srbm_select(adev, 0, 0, 0, j);
646 /* SDMA GFX */
647 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
648 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
649 }
650 vi_srbm_select(adev, 0, 0, 0, 0);
651 mutex_unlock(&adev->srbm_mutex);
652
653 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
654 adev->gfx.config.gb_addr_config & 0x70);
655
656 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
657
658 /* Set ring buffer size in dwords */
659 rb_bufsz = order_base_2(ring->ring_size / 4);
660 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
662 #ifdef __BIG_ENDIAN
663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
665 RPTR_WRITEBACK_SWAP_ENABLE, 1);
666 #endif
667 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
668
669 /* Initialize the ring buffer's read and write pointers */
670 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
671 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
672 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
673 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
674
675 /* set the wb address whether it's enabled or not */
676 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
677 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
678 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
679 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
680
681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
682
683 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
684 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
685
686 ring->wptr = 0;
687 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
688
689 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
690
691 if (ring->use_doorbell) {
692 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
693 OFFSET, ring->doorbell_index);
694 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
695 } else {
696 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
697 }
698 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
699
700 /* enable DMA RB */
701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
702 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
703
704 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
705 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
706 #ifdef __BIG_ENDIAN
707 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
708 #endif
709 /* enable DMA IBs */
710 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
711
712 ring->ready = true;
713 }
714
715 /* unhalt the MEs */
716 sdma_v3_0_enable(adev, true);
717 /* enable sdma ring preemption */
718 sdma_v3_0_ctx_switch_enable(adev, true);
719
720 for (i = 0; i < adev->sdma.num_instances; i++) {
721 ring = &adev->sdma.instance[i].ring;
722 r = amdgpu_ring_test_ring(ring);
723 if (r) {
724 ring->ready = false;
725 return r;
726 }
727
728 if (adev->mman.buffer_funcs_ring == ring)
729 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
730 }
731
732 return 0;
733 }
734
735 /**
736 * sdma_v3_0_rlc_resume - setup and start the async dma engines
737 *
738 * @adev: amdgpu_device pointer
739 *
740 * Set up the compute DMA queues and enable them (VI).
741 * Returns 0 for success, error for failure.
742 */
743 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
744 {
745 /* XXX todo */
746 return 0;
747 }
748
749 /**
750 * sdma_v3_0_load_microcode - load the sDMA ME ucode
751 *
752 * @adev: amdgpu_device pointer
753 *
754 * Loads the sDMA0/1 ucode.
755 * Returns 0 for success, -EINVAL if the ucode is not available.
756 */
757 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
758 {
759 const struct sdma_firmware_header_v1_0 *hdr;
760 const __le32 *fw_data;
761 u32 fw_size;
762 int i, j;
763
764 /* halt the MEs */
765 sdma_v3_0_enable(adev, false);
766
767 for (i = 0; i < adev->sdma.num_instances; i++) {
768 if (!adev->sdma.instance[i].fw)
769 return -EINVAL;
770 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
771 amdgpu_ucode_print_sdma_hdr(&hdr->header);
772 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
773 fw_data = (const __le32 *)
774 (adev->sdma.instance[i].fw->data +
775 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
776 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
777 for (j = 0; j < fw_size; j++)
778 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
779 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
780 }
781
782 return 0;
783 }
784
785 /**
786 * sdma_v3_0_start - setup and start the async dma engines
787 *
788 * @adev: amdgpu_device pointer
789 *
790 * Set up the DMA engines and enable them (VI).
791 * Returns 0 for success, error for failure.
792 */
793 static int sdma_v3_0_start(struct amdgpu_device *adev)
794 {
795 int r, i;
796
797 if (!adev->pp_enabled) {
798 if (!adev->firmware.smu_load) {
799 r = sdma_v3_0_load_microcode(adev);
800 if (r)
801 return r;
802 } else {
803 for (i = 0; i < adev->sdma.num_instances; i++) {
804 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
805 (i == 0) ?
806 AMDGPU_UCODE_ID_SDMA0 :
807 AMDGPU_UCODE_ID_SDMA1);
808 if (r)
809 return -EINVAL;
810 }
811 }
812 }
813
814 /* disble sdma engine before programing it */
815 sdma_v3_0_ctx_switch_enable(adev, false);
816 sdma_v3_0_enable(adev, false);
817
818 /* start the gfx rings and rlc compute queues */
819 r = sdma_v3_0_gfx_resume(adev);
820 if (r)
821 return r;
822 r = sdma_v3_0_rlc_resume(adev);
823 if (r)
824 return r;
825
826 return 0;
827 }
828
829 /**
830 * sdma_v3_0_ring_test_ring - simple async dma engine test
831 *
832 * @ring: amdgpu_ring structure holding ring information
833 *
834 * Test the DMA engine by writing using it to write an
835 * value to memory. (VI).
836 * Returns 0 for success, error for failure.
837 */
838 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
839 {
840 struct amdgpu_device *adev = ring->adev;
841 unsigned i;
842 unsigned index;
843 int r;
844 u32 tmp;
845 u64 gpu_addr;
846
847 r = amdgpu_wb_get(adev, &index);
848 if (r) {
849 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
850 return r;
851 }
852
853 gpu_addr = adev->wb.gpu_addr + (index * 4);
854 tmp = 0xCAFEDEAD;
855 adev->wb.wb[index] = cpu_to_le32(tmp);
856
857 r = amdgpu_ring_alloc(ring, 5);
858 if (r) {
859 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
860 amdgpu_wb_free(adev, index);
861 return r;
862 }
863
864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
865 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
866 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
867 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
868 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
869 amdgpu_ring_write(ring, 0xDEADBEEF);
870 amdgpu_ring_commit(ring);
871
872 for (i = 0; i < adev->usec_timeout; i++) {
873 tmp = le32_to_cpu(adev->wb.wb[index]);
874 if (tmp == 0xDEADBEEF)
875 break;
876 DRM_UDELAY(1);
877 }
878
879 if (i < adev->usec_timeout) {
880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
881 } else {
882 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
883 ring->idx, tmp);
884 r = -EINVAL;
885 }
886 amdgpu_wb_free(adev, index);
887
888 return r;
889 }
890
891 /**
892 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
893 *
894 * @ring: amdgpu_ring structure holding ring information
895 *
896 * Test a simple IB in the DMA ring (VI).
897 * Returns 0 on success, error on failure.
898 */
899 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
900 {
901 struct amdgpu_device *adev = ring->adev;
902 struct amdgpu_ib ib;
903 struct fence *f = NULL;
904 unsigned index;
905 u32 tmp = 0;
906 u64 gpu_addr;
907 long r;
908
909 r = amdgpu_wb_get(adev, &index);
910 if (r) {
911 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
912 return r;
913 }
914
915 gpu_addr = adev->wb.gpu_addr + (index * 4);
916 tmp = 0xCAFEDEAD;
917 adev->wb.wb[index] = cpu_to_le32(tmp);
918 memset(&ib, 0, sizeof(ib));
919 r = amdgpu_ib_get(adev, NULL, 256, &ib);
920 if (r) {
921 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
922 goto err0;
923 }
924
925 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
926 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
927 ib.ptr[1] = lower_32_bits(gpu_addr);
928 ib.ptr[2] = upper_32_bits(gpu_addr);
929 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
930 ib.ptr[4] = 0xDEADBEEF;
931 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
932 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
933 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
934 ib.length_dw = 8;
935
936 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
937 if (r)
938 goto err1;
939
940 r = fence_wait_timeout(f, false, timeout);
941 if (r == 0) {
942 DRM_ERROR("amdgpu: IB test timed out\n");
943 r = -ETIMEDOUT;
944 goto err1;
945 } else if (r < 0) {
946 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
947 goto err1;
948 }
949 tmp = le32_to_cpu(adev->wb.wb[index]);
950 if (tmp == 0xDEADBEEF) {
951 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
952 r = 0;
953 } else {
954 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
955 r = -EINVAL;
956 }
957 err1:
958 amdgpu_ib_free(adev, &ib, NULL);
959 fence_put(f);
960 err0:
961 amdgpu_wb_free(adev, index);
962 return r;
963 }
964
965 /**
966 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
967 *
968 * @ib: indirect buffer to fill with commands
969 * @pe: addr of the page entry
970 * @src: src addr to copy from
971 * @count: number of page entries to update
972 *
973 * Update PTEs by copying them from the GART using sDMA (CIK).
974 */
975 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
976 uint64_t pe, uint64_t src,
977 unsigned count)
978 {
979 unsigned bytes = count * 8;
980
981 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
982 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
983 ib->ptr[ib->length_dw++] = bytes;
984 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
985 ib->ptr[ib->length_dw++] = lower_32_bits(src);
986 ib->ptr[ib->length_dw++] = upper_32_bits(src);
987 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
988 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
989 }
990
991 /**
992 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
993 *
994 * @ib: indirect buffer to fill with commands
995 * @pe: addr of the page entry
996 * @value: dst addr to write into pe
997 * @count: number of page entries to update
998 * @incr: increase next addr by incr bytes
999 *
1000 * Update PTEs by writing them manually using sDMA (CIK).
1001 */
1002 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1003 uint64_t value, unsigned count,
1004 uint32_t incr)
1005 {
1006 unsigned ndw = count * 2;
1007
1008 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1009 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1010 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1011 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1012 ib->ptr[ib->length_dw++] = ndw;
1013 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1014 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1015 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1016 value += incr;
1017 }
1018 }
1019
1020 /**
1021 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1022 *
1023 * @ib: indirect buffer to fill with commands
1024 * @pe: addr of the page entry
1025 * @addr: dst addr to write into pe
1026 * @count: number of page entries to update
1027 * @incr: increase next addr by incr bytes
1028 * @flags: access flags
1029 *
1030 * Update the page tables using sDMA (CIK).
1031 */
1032 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1033 uint64_t addr, unsigned count,
1034 uint32_t incr, uint32_t flags)
1035 {
1036 /* for physically contiguous pages (vram) */
1037 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1038 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1039 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1040 ib->ptr[ib->length_dw++] = flags; /* mask */
1041 ib->ptr[ib->length_dw++] = 0;
1042 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1043 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1044 ib->ptr[ib->length_dw++] = incr; /* increment size */
1045 ib->ptr[ib->length_dw++] = 0;
1046 ib->ptr[ib->length_dw++] = count; /* number of entries */
1047 }
1048
1049 /**
1050 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1051 *
1052 * @ib: indirect buffer to fill with padding
1053 *
1054 */
1055 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1056 {
1057 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1058 u32 pad_count;
1059 int i;
1060
1061 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1062 for (i = 0; i < pad_count; i++)
1063 if (sdma && sdma->burst_nop && (i == 0))
1064 ib->ptr[ib->length_dw++] =
1065 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1066 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1067 else
1068 ib->ptr[ib->length_dw++] =
1069 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1070 }
1071
1072 /**
1073 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1074 *
1075 * @ring: amdgpu_ring pointer
1076 *
1077 * Make sure all previous operations are completed (CIK).
1078 */
1079 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1080 {
1081 uint32_t seq = ring->fence_drv.sync_seq;
1082 uint64_t addr = ring->fence_drv.gpu_addr;
1083
1084 /* wait for idle */
1085 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1086 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1087 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1088 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1089 amdgpu_ring_write(ring, addr & 0xfffffffc);
1090 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1091 amdgpu_ring_write(ring, seq); /* reference */
1092 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1093 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1094 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1095 }
1096
1097 /**
1098 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1099 *
1100 * @ring: amdgpu_ring pointer
1101 * @vm: amdgpu_vm pointer
1102 *
1103 * Update the page table base and flush the VM TLB
1104 * using sDMA (VI).
1105 */
1106 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1107 unsigned vm_id, uint64_t pd_addr)
1108 {
1109 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1110 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1111 if (vm_id < 8) {
1112 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1113 } else {
1114 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1115 }
1116 amdgpu_ring_write(ring, pd_addr >> 12);
1117
1118 /* flush TLB */
1119 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1120 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1121 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1122 amdgpu_ring_write(ring, 1 << vm_id);
1123
1124 /* wait for flush */
1125 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1126 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1127 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1128 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1129 amdgpu_ring_write(ring, 0);
1130 amdgpu_ring_write(ring, 0); /* reference */
1131 amdgpu_ring_write(ring, 0); /* mask */
1132 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1133 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1134 }
1135
1136 static int sdma_v3_0_early_init(void *handle)
1137 {
1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140 switch (adev->asic_type) {
1141 case CHIP_STONEY:
1142 adev->sdma.num_instances = 1;
1143 break;
1144 default:
1145 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1146 break;
1147 }
1148
1149 sdma_v3_0_set_ring_funcs(adev);
1150 sdma_v3_0_set_buffer_funcs(adev);
1151 sdma_v3_0_set_vm_pte_funcs(adev);
1152 sdma_v3_0_set_irq_funcs(adev);
1153
1154 return 0;
1155 }
1156
1157 static int sdma_v3_0_sw_init(void *handle)
1158 {
1159 struct amdgpu_ring *ring;
1160 int r, i;
1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1162
1163 /* SDMA trap event */
1164 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1165 if (r)
1166 return r;
1167
1168 /* SDMA Privileged inst */
1169 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1170 if (r)
1171 return r;
1172
1173 /* SDMA Privileged inst */
1174 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1175 if (r)
1176 return r;
1177
1178 r = sdma_v3_0_init_microcode(adev);
1179 if (r) {
1180 DRM_ERROR("Failed to load sdma firmware!\n");
1181 return r;
1182 }
1183
1184 for (i = 0; i < adev->sdma.num_instances; i++) {
1185 ring = &adev->sdma.instance[i].ring;
1186 ring->ring_obj = NULL;
1187 ring->use_doorbell = true;
1188 ring->doorbell_index = (i == 0) ?
1189 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1190
1191 sprintf(ring->name, "sdma%d", i);
1192 r = amdgpu_ring_init(adev, ring, 1024,
1193 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1194 &adev->sdma.trap_irq,
1195 (i == 0) ?
1196 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1197 AMDGPU_RING_TYPE_SDMA);
1198 if (r)
1199 return r;
1200 }
1201
1202 return r;
1203 }
1204
1205 static int sdma_v3_0_sw_fini(void *handle)
1206 {
1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208 int i;
1209
1210 for (i = 0; i < adev->sdma.num_instances; i++)
1211 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1212
1213 sdma_v3_0_free_microcode(adev);
1214 return 0;
1215 }
1216
1217 static int sdma_v3_0_hw_init(void *handle)
1218 {
1219 int r;
1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221
1222 sdma_v3_0_init_golden_registers(adev);
1223
1224 r = sdma_v3_0_start(adev);
1225 if (r)
1226 return r;
1227
1228 return r;
1229 }
1230
1231 static int sdma_v3_0_hw_fini(void *handle)
1232 {
1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235 sdma_v3_0_ctx_switch_enable(adev, false);
1236 sdma_v3_0_enable(adev, false);
1237
1238 return 0;
1239 }
1240
1241 static int sdma_v3_0_suspend(void *handle)
1242 {
1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245 return sdma_v3_0_hw_fini(adev);
1246 }
1247
1248 static int sdma_v3_0_resume(void *handle)
1249 {
1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1251
1252 return sdma_v3_0_hw_init(adev);
1253 }
1254
1255 static bool sdma_v3_0_is_idle(void *handle)
1256 {
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258 u32 tmp = RREG32(mmSRBM_STATUS2);
1259
1260 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1261 SRBM_STATUS2__SDMA1_BUSY_MASK))
1262 return false;
1263
1264 return true;
1265 }
1266
1267 static int sdma_v3_0_wait_for_idle(void *handle)
1268 {
1269 unsigned i;
1270 u32 tmp;
1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273 for (i = 0; i < adev->usec_timeout; i++) {
1274 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1275 SRBM_STATUS2__SDMA1_BUSY_MASK);
1276
1277 if (!tmp)
1278 return 0;
1279 udelay(1);
1280 }
1281 return -ETIMEDOUT;
1282 }
1283
1284 static int sdma_v3_0_check_soft_reset(void *handle)
1285 {
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 u32 srbm_soft_reset = 0;
1288 u32 tmp = RREG32(mmSRBM_STATUS2);
1289
1290 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1291 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1292 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1293 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1294 }
1295
1296 if (srbm_soft_reset) {
1297 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = true;
1298 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1299 } else {
1300 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = false;
1301 adev->sdma.srbm_soft_reset = 0;
1302 }
1303
1304 return 0;
1305 }
1306
1307 static int sdma_v3_0_pre_soft_reset(void *handle)
1308 {
1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310 u32 srbm_soft_reset = 0;
1311
1312 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1313 return 0;
1314
1315 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1316
1317 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1318 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1319 sdma_v3_0_ctx_switch_enable(adev, false);
1320 sdma_v3_0_enable(adev, false);
1321 }
1322
1323 return 0;
1324 }
1325
1326 static int sdma_v3_0_post_soft_reset(void *handle)
1327 {
1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329 u32 srbm_soft_reset = 0;
1330
1331 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1332 return 0;
1333
1334 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1335
1336 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1337 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1338 sdma_v3_0_gfx_resume(adev);
1339 sdma_v3_0_rlc_resume(adev);
1340 }
1341
1342 return 0;
1343 }
1344
1345 static int sdma_v3_0_soft_reset(void *handle)
1346 {
1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1348 u32 srbm_soft_reset = 0;
1349 u32 tmp;
1350
1351 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1352 return 0;
1353
1354 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1355
1356 if (srbm_soft_reset) {
1357 tmp = RREG32(mmSRBM_SOFT_RESET);
1358 tmp |= srbm_soft_reset;
1359 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1360 WREG32(mmSRBM_SOFT_RESET, tmp);
1361 tmp = RREG32(mmSRBM_SOFT_RESET);
1362
1363 udelay(50);
1364
1365 tmp &= ~srbm_soft_reset;
1366 WREG32(mmSRBM_SOFT_RESET, tmp);
1367 tmp = RREG32(mmSRBM_SOFT_RESET);
1368
1369 /* Wait a little for things to settle down */
1370 udelay(50);
1371 }
1372
1373 return 0;
1374 }
1375
1376 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1377 struct amdgpu_irq_src *source,
1378 unsigned type,
1379 enum amdgpu_interrupt_state state)
1380 {
1381 u32 sdma_cntl;
1382
1383 switch (type) {
1384 case AMDGPU_SDMA_IRQ_TRAP0:
1385 switch (state) {
1386 case AMDGPU_IRQ_STATE_DISABLE:
1387 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1388 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1389 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1390 break;
1391 case AMDGPU_IRQ_STATE_ENABLE:
1392 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1393 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1394 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1395 break;
1396 default:
1397 break;
1398 }
1399 break;
1400 case AMDGPU_SDMA_IRQ_TRAP1:
1401 switch (state) {
1402 case AMDGPU_IRQ_STATE_DISABLE:
1403 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1404 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1405 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1406 break;
1407 case AMDGPU_IRQ_STATE_ENABLE:
1408 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1409 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1410 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1411 break;
1412 default:
1413 break;
1414 }
1415 break;
1416 default:
1417 break;
1418 }
1419 return 0;
1420 }
1421
1422 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1423 struct amdgpu_irq_src *source,
1424 struct amdgpu_iv_entry *entry)
1425 {
1426 u8 instance_id, queue_id;
1427
1428 instance_id = (entry->ring_id & 0x3) >> 0;
1429 queue_id = (entry->ring_id & 0xc) >> 2;
1430 DRM_DEBUG("IH: SDMA trap\n");
1431 switch (instance_id) {
1432 case 0:
1433 switch (queue_id) {
1434 case 0:
1435 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1436 break;
1437 case 1:
1438 /* XXX compute */
1439 break;
1440 case 2:
1441 /* XXX compute */
1442 break;
1443 }
1444 break;
1445 case 1:
1446 switch (queue_id) {
1447 case 0:
1448 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1449 break;
1450 case 1:
1451 /* XXX compute */
1452 break;
1453 case 2:
1454 /* XXX compute */
1455 break;
1456 }
1457 break;
1458 }
1459 return 0;
1460 }
1461
1462 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1463 struct amdgpu_irq_src *source,
1464 struct amdgpu_iv_entry *entry)
1465 {
1466 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1467 schedule_work(&adev->reset_work);
1468 return 0;
1469 }
1470
1471 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1472 struct amdgpu_device *adev,
1473 bool enable)
1474 {
1475 uint32_t temp, data;
1476 int i;
1477
1478 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1479 for (i = 0; i < adev->sdma.num_instances; i++) {
1480 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1481 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1489 if (data != temp)
1490 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1491 }
1492 } else {
1493 for (i = 0; i < adev->sdma.num_instances; i++) {
1494 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1495 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1496 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1497 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1498 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1499 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1500 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1501 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1502 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1503
1504 if (data != temp)
1505 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1506 }
1507 }
1508 }
1509
1510 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1511 struct amdgpu_device *adev,
1512 bool enable)
1513 {
1514 uint32_t temp, data;
1515 int i;
1516
1517 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1518 for (i = 0; i < adev->sdma.num_instances; i++) {
1519 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1520 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1521
1522 if (temp != data)
1523 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1524 }
1525 } else {
1526 for (i = 0; i < adev->sdma.num_instances; i++) {
1527 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1528 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1529
1530 if (temp != data)
1531 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1532 }
1533 }
1534 }
1535
1536 static int sdma_v3_0_set_clockgating_state(void *handle,
1537 enum amd_clockgating_state state)
1538 {
1539 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1540
1541 switch (adev->asic_type) {
1542 case CHIP_FIJI:
1543 case CHIP_CARRIZO:
1544 case CHIP_STONEY:
1545 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1546 state == AMD_CG_STATE_GATE ? true : false);
1547 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1548 state == AMD_CG_STATE_GATE ? true : false);
1549 break;
1550 default:
1551 break;
1552 }
1553 return 0;
1554 }
1555
1556 static int sdma_v3_0_set_powergating_state(void *handle,
1557 enum amd_powergating_state state)
1558 {
1559 return 0;
1560 }
1561
1562 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1563 .name = "sdma_v3_0",
1564 .early_init = sdma_v3_0_early_init,
1565 .late_init = NULL,
1566 .sw_init = sdma_v3_0_sw_init,
1567 .sw_fini = sdma_v3_0_sw_fini,
1568 .hw_init = sdma_v3_0_hw_init,
1569 .hw_fini = sdma_v3_0_hw_fini,
1570 .suspend = sdma_v3_0_suspend,
1571 .resume = sdma_v3_0_resume,
1572 .is_idle = sdma_v3_0_is_idle,
1573 .wait_for_idle = sdma_v3_0_wait_for_idle,
1574 .check_soft_reset = sdma_v3_0_check_soft_reset,
1575 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1576 .post_soft_reset = sdma_v3_0_post_soft_reset,
1577 .soft_reset = sdma_v3_0_soft_reset,
1578 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1579 .set_powergating_state = sdma_v3_0_set_powergating_state,
1580 };
1581
1582 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1583 .get_rptr = sdma_v3_0_ring_get_rptr,
1584 .get_wptr = sdma_v3_0_ring_get_wptr,
1585 .set_wptr = sdma_v3_0_ring_set_wptr,
1586 .parse_cs = NULL,
1587 .emit_ib = sdma_v3_0_ring_emit_ib,
1588 .emit_fence = sdma_v3_0_ring_emit_fence,
1589 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1590 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1591 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1592 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1593 .test_ring = sdma_v3_0_ring_test_ring,
1594 .test_ib = sdma_v3_0_ring_test_ib,
1595 .insert_nop = sdma_v3_0_ring_insert_nop,
1596 .pad_ib = sdma_v3_0_ring_pad_ib,
1597 };
1598
1599 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1600 {
1601 int i;
1602
1603 for (i = 0; i < adev->sdma.num_instances; i++)
1604 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1605 }
1606
1607 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1608 .set = sdma_v3_0_set_trap_irq_state,
1609 .process = sdma_v3_0_process_trap_irq,
1610 };
1611
1612 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1613 .process = sdma_v3_0_process_illegal_inst_irq,
1614 };
1615
1616 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1617 {
1618 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1619 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1620 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1621 }
1622
1623 /**
1624 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1625 *
1626 * @ring: amdgpu_ring structure holding ring information
1627 * @src_offset: src GPU address
1628 * @dst_offset: dst GPU address
1629 * @byte_count: number of bytes to xfer
1630 *
1631 * Copy GPU buffers using the DMA engine (VI).
1632 * Used by the amdgpu ttm implementation to move pages if
1633 * registered as the asic copy callback.
1634 */
1635 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1636 uint64_t src_offset,
1637 uint64_t dst_offset,
1638 uint32_t byte_count)
1639 {
1640 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1641 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1642 ib->ptr[ib->length_dw++] = byte_count;
1643 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1644 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1645 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1646 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1647 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1648 }
1649
1650 /**
1651 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1652 *
1653 * @ring: amdgpu_ring structure holding ring information
1654 * @src_data: value to write to buffer
1655 * @dst_offset: dst GPU address
1656 * @byte_count: number of bytes to xfer
1657 *
1658 * Fill GPU buffers using the DMA engine (VI).
1659 */
1660 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1661 uint32_t src_data,
1662 uint64_t dst_offset,
1663 uint32_t byte_count)
1664 {
1665 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1666 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1667 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1668 ib->ptr[ib->length_dw++] = src_data;
1669 ib->ptr[ib->length_dw++] = byte_count;
1670 }
1671
1672 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1673 .copy_max_bytes = 0x1fffff,
1674 .copy_num_dw = 7,
1675 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1676
1677 .fill_max_bytes = 0x1fffff,
1678 .fill_num_dw = 5,
1679 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1680 };
1681
1682 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1683 {
1684 if (adev->mman.buffer_funcs == NULL) {
1685 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1686 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1687 }
1688 }
1689
1690 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1691 .copy_pte = sdma_v3_0_vm_copy_pte,
1692 .write_pte = sdma_v3_0_vm_write_pte,
1693 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1694 };
1695
1696 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1697 {
1698 unsigned i;
1699
1700 if (adev->vm_manager.vm_pte_funcs == NULL) {
1701 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1702 for (i = 0; i < adev->sdma.num_instances; i++)
1703 adev->vm_manager.vm_pte_rings[i] =
1704 &adev->sdma.instance[i].ring;
1705
1706 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1707 }
1708 }
Linux kernel - Deliverables
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