drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  41 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int uvd_v6_0_start(struct amdgpu_device *adev);
  43 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  44 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  45
  46 /**
  47  * uvd_v6_0_ring_get_rptr - get read pointer
  48  *
  49  * @ring: amdgpu_ring pointer
  50  *
  51  * Returns the current hardware read pointer
  52  */
  53 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  54 {
  55         struct amdgpu_device *adev = ring->adev;
  56
  57         return RREG32(mmUVD_RBC_RB_RPTR);
  58 }
  59
  60 /**
  61  * uvd_v6_0_ring_get_wptr - get write pointer
  62  *
  63  * @ring: amdgpu_ring pointer
  64  *
  65  * Returns the current hardware write pointer
  66  */
  67 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  68 {
  69         struct amdgpu_device *adev = ring->adev;
  70
  71         return RREG32(mmUVD_RBC_RB_WPTR);
  72 }
  73
  74 /**
  75  * uvd_v6_0_ring_set_wptr - set write pointer
  76  *
  77  * @ring: amdgpu_ring pointer
  78  *
  79  * Commits the write pointer to the hardware
  80  */
  81 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  82 {
  83         struct amdgpu_device *adev = ring->adev;
  84
  85         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  86 }
  87
  88 static int uvd_v6_0_early_init(void *handle)
  89 {
  90         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  91
  92         uvd_v6_0_set_ring_funcs(adev);
  93         uvd_v6_0_set_irq_funcs(adev);
  94
  95         return 0;
  96 }
  97
  98 static int uvd_v6_0_sw_init(void *handle)
  99 {
 100         struct amdgpu_ring *ring;
 101         int r;
 102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 103
 104         /* UVD TRAP */
 105         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 106         if (r)
 107                 return r;
 108
 109         r = amdgpu_uvd_sw_init(adev);
 110         if (r)
 111                 return r;
 112
 113         r = amdgpu_uvd_resume(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->uvd.ring;
 118         sprintf(ring->name, "uvd");
 119         r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
 120                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 121
 122         return r;
 123 }
 124
 125 static int uvd_v6_0_sw_fini(void *handle)
 126 {
 127         int r;
 128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 129
 130         r = amdgpu_uvd_suspend(adev);
 131         if (r)
 132                 return r;
 133
 134         r = amdgpu_uvd_sw_fini(adev);
 135         if (r)
 136                 return r;
 137
 138         return r;
 139 }
 140
 141 /**
 142  * uvd_v6_0_hw_init - start and test UVD block
 143  *
 144  * @adev: amdgpu_device pointer
 145  *
 146  * Initialize the hardware, boot up the VCPU and do some testing
 147  */
 148 static int uvd_v6_0_hw_init(void *handle)
 149 {
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151         struct amdgpu_ring *ring = &adev->uvd.ring;
 152         uint32_t tmp;
 153         int r;
 154
 155         r = uvd_v6_0_start(adev);
 156         if (r)
 157                 goto done;
 158
 159         ring->ready = true;
 160         r = amdgpu_ring_test_ring(ring);
 161         if (r) {
 162                 ring->ready = false;
 163                 goto done;
 164         }
 165
 166         r = amdgpu_ring_alloc(ring, 10);
 167         if (r) {
 168                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 169                 goto done;
 170         }
 171
 172         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 173         amdgpu_ring_write(ring, tmp);
 174         amdgpu_ring_write(ring, 0xFFFFF);
 175
 176         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 177         amdgpu_ring_write(ring, tmp);
 178         amdgpu_ring_write(ring, 0xFFFFF);
 179
 180         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 181         amdgpu_ring_write(ring, tmp);
 182         amdgpu_ring_write(ring, 0xFFFFF);
 183
 184         /* Clear timeout status bits */
 185         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 186         amdgpu_ring_write(ring, 0x8);
 187
 188         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 189         amdgpu_ring_write(ring, 3);
 190
 191         amdgpu_ring_commit(ring);
 192
 193 done:
 194         if (!r)
 195                 DRM_INFO("UVD initialized successfully.\n");
 196
 197         return r;
 198 }
 199
 200 /**
 201  * uvd_v6_0_hw_fini - stop the hardware block
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Stop the UVD block, mark ring as not ready any more
 206  */
 207 static int uvd_v6_0_hw_fini(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210         struct amdgpu_ring *ring = &adev->uvd.ring;
 211
 212         uvd_v6_0_stop(adev);
 213         ring->ready = false;
 214
 215         return 0;
 216 }
 217
 218 static int uvd_v6_0_suspend(void *handle)
 219 {
 220         int r;
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222
 223         r = uvd_v6_0_hw_fini(adev);
 224         if (r)
 225                 return r;
 226
 227         /* Skip this for APU for now */
 228         if (!(adev->flags & AMD_IS_APU)) {
 229                 r = amdgpu_uvd_suspend(adev);
 230                 if (r)
 231                         return r;
 232         }
 233
 234         return r;
 235 }
 236
 237 static int uvd_v6_0_resume(void *handle)
 238 {
 239         int r;
 240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 241
 242         /* Skip this for APU for now */
 243         if (!(adev->flags & AMD_IS_APU)) {
 244                 r = amdgpu_uvd_resume(adev);
 245                 if (r)
 246                         return r;
 247         }
 248         r = uvd_v6_0_hw_init(adev);
 249         if (r)
 250                 return r;
 251
 252         return r;
 253 }
 254
 255 /**
 256  * uvd_v6_0_mc_resume - memory controller programming
 257  *
 258  * @adev: amdgpu_device pointer
 259  *
 260  * Let the UVD memory controller know it's offsets
 261  */
 262 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 263 {
 264         uint64_t offset;
 265         uint32_t size;
 266
 267         /* programm memory controller bits 0-27 */
 268         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 269                         lower_32_bits(adev->uvd.gpu_addr));
 270         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 271                         upper_32_bits(adev->uvd.gpu_addr));
 272
 273         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 274         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 275         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 276         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 277
 278         offset += size;
 279         size = AMDGPU_UVD_HEAP_SIZE;
 280         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 281         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 282
 283         offset += size;
 284         size = AMDGPU_UVD_STACK_SIZE +
 285                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 286         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 287         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 288
 289         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 290         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 291         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 292
 293         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 294 }
 295
 296 #if 0
 297 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 298                 bool enable)
 299 {
 300         u32 data, data1;
 301
 302         data = RREG32(mmUVD_CGC_GATE);
 303         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 304         if (enable) {
 305                 data |= UVD_CGC_GATE__SYS_MASK |
 306                                 UVD_CGC_GATE__UDEC_MASK |
 307                                 UVD_CGC_GATE__MPEG2_MASK |
 308                                 UVD_CGC_GATE__RBC_MASK |
 309                                 UVD_CGC_GATE__LMI_MC_MASK |
 310                                 UVD_CGC_GATE__IDCT_MASK |
 311                                 UVD_CGC_GATE__MPRD_MASK |
 312                                 UVD_CGC_GATE__MPC_MASK |
 313                                 UVD_CGC_GATE__LBSI_MASK |
 314                                 UVD_CGC_GATE__LRBBM_MASK |
 315                                 UVD_CGC_GATE__UDEC_RE_MASK |
 316                                 UVD_CGC_GATE__UDEC_CM_MASK |
 317                                 UVD_CGC_GATE__UDEC_IT_MASK |
 318                                 UVD_CGC_GATE__UDEC_DB_MASK |
 319                                 UVD_CGC_GATE__UDEC_MP_MASK |
 320                                 UVD_CGC_GATE__WCB_MASK |
 321                                 UVD_CGC_GATE__VCPU_MASK |
 322                                 UVD_CGC_GATE__SCPU_MASK;
 323                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 324                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 325                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 326                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 327                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 328                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 329                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 330                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 331                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 332                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 333                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 334                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 335                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 336         } else {
 337                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 338                                 UVD_CGC_GATE__UDEC_MASK |
 339                                 UVD_CGC_GATE__MPEG2_MASK |
 340                                 UVD_CGC_GATE__RBC_MASK |
 341                                 UVD_CGC_GATE__LMI_MC_MASK |
 342                                 UVD_CGC_GATE__LMI_UMC_MASK |
 343                                 UVD_CGC_GATE__IDCT_MASK |
 344                                 UVD_CGC_GATE__MPRD_MASK |
 345                                 UVD_CGC_GATE__MPC_MASK |
 346                                 UVD_CGC_GATE__LBSI_MASK |
 347                                 UVD_CGC_GATE__LRBBM_MASK |
 348                                 UVD_CGC_GATE__UDEC_RE_MASK |
 349                                 UVD_CGC_GATE__UDEC_CM_MASK |
 350                                 UVD_CGC_GATE__UDEC_IT_MASK |
 351                                 UVD_CGC_GATE__UDEC_DB_MASK |
 352                                 UVD_CGC_GATE__UDEC_MP_MASK |
 353                                 UVD_CGC_GATE__WCB_MASK |
 354                                 UVD_CGC_GATE__VCPU_MASK |
 355                                 UVD_CGC_GATE__SCPU_MASK);
 356                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 357                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 358                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 359                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 360                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 361                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 362                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 363                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 364                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 365                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 366                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 367                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 368                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 369         }
 370         WREG32(mmUVD_CGC_GATE, data);
 371         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 372 }
 373 #endif
 374
 375 /**
 376  * uvd_v6_0_start - start UVD block
 377  *
 378  * @adev: amdgpu_device pointer
 379  *
 380  * Setup and start the UVD block
 381  */
 382 static int uvd_v6_0_start(struct amdgpu_device *adev)
 383 {
 384         struct amdgpu_ring *ring = &adev->uvd.ring;
 385         uint32_t rb_bufsz, tmp;
 386         uint32_t lmi_swap_cntl;
 387         uint32_t mp_swap_cntl;
 388         int i, j, r;
 389
 390         /* disable DPG */
 391         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 392
 393         /* disable byte swapping */
 394         lmi_swap_cntl = 0;
 395         mp_swap_cntl = 0;
 396
 397         uvd_v6_0_mc_resume(adev);
 398
 399         /* Set dynamic clock gating in S/W control mode */
 400         if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
 401                 uvd_v6_0_set_sw_clock_gating(adev);
 402         } else {
 403                 /* disable clock gating */
 404                 uint32_t data = RREG32(mmUVD_CGC_CTRL);
 405                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 406                 WREG32(mmUVD_CGC_CTRL, data);
 407         }
 408
 409         /* disable interupt */
 410         WREG32_P(mmUVD_MASTINT_EN, 0, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 411
 412         /* stall UMC and register bus before resetting VCPU */
 413         WREG32_P(mmUVD_LMI_CTRL2, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 414         mdelay(1);
 415
 416         /* put LMI, VCPU, RBC etc... into reset */
 417         WREG32(mmUVD_SOFT_RESET,
 418                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 419                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 420                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 421                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 422                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 423                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 424                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 425                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 426         mdelay(5);
 427
 428         /* take UVD block out of reset */
 429         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 430         mdelay(5);
 431
 432         /* initialize UVD memory controller */
 433         WREG32(mmUVD_LMI_CTRL,
 434                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 435                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 436                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 437                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 438                 UVD_LMI_CTRL__REQ_MODE_MASK |
 439                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 440
 441 #ifdef __BIG_ENDIAN
 442         /* swap (8 in 32) RB and IB */
 443         lmi_swap_cntl = 0xa;
 444         mp_swap_cntl = 0;
 445 #endif
 446         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 447         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 448
 449         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 450         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 451         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 452         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 453         WREG32(mmUVD_MPC_SET_ALU, 0);
 454         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 455
 456         /* take all subblocks out of reset, except VCPU */
 457         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 458         mdelay(5);
 459
 460         /* enable VCPU clock */
 461         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 462
 463         /* enable UMC */
 464         WREG32_P(mmUVD_LMI_CTRL2, 0, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 465
 466         /* boot up the VCPU */
 467         WREG32(mmUVD_SOFT_RESET, 0);
 468         mdelay(10);
 469
 470         for (i = 0; i < 10; ++i) {
 471                 uint32_t status;
 472
 473                 for (j = 0; j < 100; ++j) {
 474                         status = RREG32(mmUVD_STATUS);
 475                         if (status & 2)
 476                                 break;
 477                         mdelay(10);
 478                 }
 479                 r = 0;
 480                 if (status & 2)
 481                         break;
 482
 483                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 484                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 485                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 486                 mdelay(10);
 487                 WREG32_P(mmUVD_SOFT_RESET, 0,
 488                          ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 489                 mdelay(10);
 490                 r = -1;
 491         }
 492
 493         if (r) {
 494                 DRM_ERROR("UVD not responding, giving up!!!\n");
 495                 return r;
 496         }
 497         /* enable master interrupt */
 498         WREG32_P(mmUVD_MASTINT_EN,
 499                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 500                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 501
 502         /* clear the bit 4 of UVD_STATUS */
 503         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 504
 505         rb_bufsz = order_base_2(ring->ring_size);
 506         tmp = 0;
 507         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 508         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 509         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 510         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 511         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 512         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 513         /* force RBC into idle state */
 514         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 515
 516         /* set the write pointer delay */
 517         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 518
 519         /* set the wb address */
 520         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 521
 522         /* programm the RB_BASE for ring buffer */
 523         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 524                         lower_32_bits(ring->gpu_addr));
 525         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 526                         upper_32_bits(ring->gpu_addr));
 527
 528         /* Initialize the ring buffer's read and write pointers */
 529         WREG32(mmUVD_RBC_RB_RPTR, 0);
 530
 531         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 532         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 533
 534         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 535
 536         return 0;
 537 }
 538
 539 /**
 540  * uvd_v6_0_stop - stop UVD block
 541  *
 542  * @adev: amdgpu_device pointer
 543  *
 544  * stop the UVD block
 545  */
 546 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 547 {
 548         /* force RBC into idle state */
 549         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 550
 551         /* Stall UMC and register bus before resetting VCPU */
 552         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 553         mdelay(1);
 554
 555         /* put VCPU into reset */
 556         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 557         mdelay(5);
 558
 559         /* disable VCPU clock */
 560         WREG32(mmUVD_VCPU_CNTL, 0x0);
 561
 562         /* Unstall UMC and register bus */
 563         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 564 }
 565
 566 /**
 567  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 568  *
 569  * @ring: amdgpu_ring pointer
 570  * @fence: fence to emit
 571  *
 572  * Write a fence and a trap command to the ring.
 573  */
 574 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 575                                      unsigned flags)
 576 {
 577         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 578
 579         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 580         amdgpu_ring_write(ring, seq);
 581         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 582         amdgpu_ring_write(ring, addr & 0xffffffff);
 583         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 584         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 585         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 586         amdgpu_ring_write(ring, 0);
 587
 588         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 589         amdgpu_ring_write(ring, 0);
 590         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 591         amdgpu_ring_write(ring, 0);
 592         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 593         amdgpu_ring_write(ring, 2);
 594 }
 595
 596 /**
 597  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 598  *
 599  * @ring: amdgpu_ring pointer
 600  *
 601  * Emits an hdp flush.
 602  */
 603 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 604 {
 605         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 606         amdgpu_ring_write(ring, 0);
 607 }
 608
 609 /**
 610  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 611  *
 612  * @ring: amdgpu_ring pointer
 613  *
 614  * Emits an hdp invalidate.
 615  */
 616 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 617 {
 618         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 619         amdgpu_ring_write(ring, 1);
 620 }
 621
 622 /**
 623  * uvd_v6_0_ring_test_ring - register write test
 624  *
 625  * @ring: amdgpu_ring pointer
 626  *
 627  * Test if we can successfully write to the context register
 628  */
 629 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 630 {
 631         struct amdgpu_device *adev = ring->adev;
 632         uint32_t tmp = 0;
 633         unsigned i;
 634         int r;
 635
 636         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 637         r = amdgpu_ring_alloc(ring, 3);
 638         if (r) {
 639                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 640                           ring->idx, r);
 641                 return r;
 642         }
 643         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 644         amdgpu_ring_write(ring, 0xDEADBEEF);
 645         amdgpu_ring_commit(ring);
 646         for (i = 0; i < adev->usec_timeout; i++) {
 647                 tmp = RREG32(mmUVD_CONTEXT_ID);
 648                 if (tmp == 0xDEADBEEF)
 649                         break;
 650                 DRM_UDELAY(1);
 651         }
 652
 653         if (i < adev->usec_timeout) {
 654                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 655                          ring->idx, i);
 656         } else {
 657                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 658                           ring->idx, tmp);
 659                 r = -EINVAL;
 660         }
 661         return r;
 662 }
 663
 664 /**
 665  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 666  *
 667  * @ring: amdgpu_ring pointer
 668  * @ib: indirect buffer to execute
 669  *
 670  * Write ring commands to execute the indirect buffer
 671  */
 672 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 673                                   struct amdgpu_ib *ib,
 674                                   unsigned vm_id, bool ctx_switch)
 675 {
 676         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
 677         amdgpu_ring_write(ring, vm_id);
 678
 679         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 680         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 681         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 682         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 683         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 684         amdgpu_ring_write(ring, ib->length_dw);
 685 }
 686
 687 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 688                                          unsigned vm_id, uint64_t pd_addr)
 689 {
 690         uint32_t reg;
 691
 692         if (vm_id < 8)
 693                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
 694         else
 695                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
 696
 697         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 698         amdgpu_ring_write(ring, reg << 2);
 699         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 700         amdgpu_ring_write(ring, pd_addr >> 12);
 701         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 702         amdgpu_ring_write(ring, 0x8);
 703
 704         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 705         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 706         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 707         amdgpu_ring_write(ring, 1 << vm_id);
 708         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 709         amdgpu_ring_write(ring, 0x8);
 710
 711         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 712         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 713         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 714         amdgpu_ring_write(ring, 0);
 715         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 716         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
 717         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 718         amdgpu_ring_write(ring, 0xC);
 719 }
 720
 721 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 722 {
 723         uint32_t seq = ring->fence_drv.sync_seq;
 724         uint64_t addr = ring->fence_drv.gpu_addr;
 725
 726         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 727         amdgpu_ring_write(ring, lower_32_bits(addr));
 728         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 729         amdgpu_ring_write(ring, upper_32_bits(addr));
 730         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 731         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 732         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
 733         amdgpu_ring_write(ring, seq);
 734         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 735         amdgpu_ring_write(ring, 0xE);
 736 }
 737
 738 static bool uvd_v6_0_is_idle(void *handle)
 739 {
 740         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 741
 742         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 743 }
 744
 745 static int uvd_v6_0_wait_for_idle(void *handle)
 746 {
 747         unsigned i;
 748         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 749
 750         for (i = 0; i < adev->usec_timeout; i++) {
 751                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 752                         return 0;
 753         }
 754         return -ETIMEDOUT;
 755 }
 756
 757 static int uvd_v6_0_soft_reset(void *handle)
 758 {
 759         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 760
 761         uvd_v6_0_stop(adev);
 762
 763         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 764                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 765         mdelay(5);
 766
 767         return uvd_v6_0_start(adev);
 768 }
 769
 770 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 771                                         struct amdgpu_irq_src *source,
 772                                         unsigned type,
 773                                         enum amdgpu_interrupt_state state)
 774 {
 775         // TODO
 776         return 0;
 777 }
 778
 779 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 780                                       struct amdgpu_irq_src *source,
 781                                       struct amdgpu_iv_entry *entry)
 782 {
 783         DRM_DEBUG("IH: UVD TRAP\n");
 784         amdgpu_fence_process(&adev->uvd.ring);
 785         return 0;
 786 }
 787
 788 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
 789 {
 790         uint32_t data, data1, data2, suvd_flags;
 791
 792         data = RREG32(mmUVD_CGC_CTRL);
 793         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 794         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 795
 796         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 797                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 798
 799         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 800                      UVD_SUVD_CGC_GATE__SIT_MASK |
 801                      UVD_SUVD_CGC_GATE__SMP_MASK |
 802                      UVD_SUVD_CGC_GATE__SCM_MASK |
 803                      UVD_SUVD_CGC_GATE__SDB_MASK;
 804
 805         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 806                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 807                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 808
 809         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 810                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 811                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 812                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 813                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 814                         UVD_CGC_CTRL__SYS_MODE_MASK |
 815                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 816                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 817                         UVD_CGC_CTRL__REGS_MODE_MASK |
 818                         UVD_CGC_CTRL__RBC_MODE_MASK |
 819                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 820                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 821                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 822                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 823                         UVD_CGC_CTRL__MPC_MODE_MASK |
 824                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 825                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 826                         UVD_CGC_CTRL__WCB_MODE_MASK |
 827                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 828                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 829                         UVD_CGC_CTRL__SCPU_MODE_MASK |
 830                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
 831         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 832                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 833                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 834                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 835                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 836         data1 |= suvd_flags;
 837
 838         WREG32(mmUVD_CGC_CTRL, data);
 839         WREG32(mmUVD_CGC_GATE, 0);
 840         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 841         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 842 }
 843
 844 #if 0
 845 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
 846 {
 847         uint32_t data, data1, cgc_flags, suvd_flags;
 848
 849         data = RREG32(mmUVD_CGC_GATE);
 850         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 851
 852         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 853                 UVD_CGC_GATE__UDEC_MASK |
 854                 UVD_CGC_GATE__MPEG2_MASK |
 855                 UVD_CGC_GATE__RBC_MASK |
 856                 UVD_CGC_GATE__LMI_MC_MASK |
 857                 UVD_CGC_GATE__IDCT_MASK |
 858                 UVD_CGC_GATE__MPRD_MASK |
 859                 UVD_CGC_GATE__MPC_MASK |
 860                 UVD_CGC_GATE__LBSI_MASK |
 861                 UVD_CGC_GATE__LRBBM_MASK |
 862                 UVD_CGC_GATE__UDEC_RE_MASK |
 863                 UVD_CGC_GATE__UDEC_CM_MASK |
 864                 UVD_CGC_GATE__UDEC_IT_MASK |
 865                 UVD_CGC_GATE__UDEC_DB_MASK |
 866                 UVD_CGC_GATE__UDEC_MP_MASK |
 867                 UVD_CGC_GATE__WCB_MASK |
 868                 UVD_CGC_GATE__VCPU_MASK |
 869                 UVD_CGC_GATE__SCPU_MASK |
 870                 UVD_CGC_GATE__JPEG_MASK |
 871                 UVD_CGC_GATE__JPEG2_MASK;
 872
 873         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 874                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 875                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 876                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 877                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 878
 879         data |= cgc_flags;
 880         data1 |= suvd_flags;
 881
 882         WREG32(mmUVD_CGC_GATE, data);
 883         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 884 }
 885 #endif
 886
 887 static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
 888 {
 889         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
 890
 891         if (enable)
 892                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 893                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 894         else
 895                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 896                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 897
 898         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
 899 }
 900
 901 static int uvd_v6_0_set_clockgating_state(void *handle,
 902                                           enum amd_clockgating_state state)
 903 {
 904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 905         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 906         static int curstate = -1;
 907
 908         if (adev->asic_type == CHIP_FIJI ||
 909                         adev->asic_type == CHIP_POLARIS10)
 910                 uvd_v6_set_bypass_mode(adev, enable);
 911
 912         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 913                 return 0;
 914
 915         if (curstate == state)
 916                 return 0;
 917
 918         curstate = state;
 919         if (enable) {
 920                 /* disable HW gating and enable Sw gating */
 921                 uvd_v6_0_set_sw_clock_gating(adev);
 922         } else {
 923                 /* wait for STATUS to clear */
 924                 if (uvd_v6_0_wait_for_idle(handle))
 925                         return -EBUSY;
 926
 927                 /* enable HW gates because UVD is idle */
 928 /*              uvd_v6_0_set_hw_clock_gating(adev); */
 929         }
 930
 931         return 0;
 932 }
 933
 934 static int uvd_v6_0_set_powergating_state(void *handle,
 935                                           enum amd_powergating_state state)
 936 {
 937         /* This doesn't actually powergate the UVD block.
 938          * That's done in the dpm code via the SMC.  This
 939          * just re-inits the block as necessary.  The actual
 940          * gating still happens in the dpm code.  We should
 941          * revisit this when there is a cleaner line between
 942          * the smc and the hw blocks
 943          */
 944         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 945
 946         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 947                 return 0;
 948
 949         if (state == AMD_PG_STATE_GATE) {
 950                 uvd_v6_0_stop(adev);
 951                 return 0;
 952         } else {
 953                 return uvd_v6_0_start(adev);
 954         }
 955 }
 956
 957 const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 958         .name = "uvd_v6_0",
 959         .early_init = uvd_v6_0_early_init,
 960         .late_init = NULL,
 961         .sw_init = uvd_v6_0_sw_init,
 962         .sw_fini = uvd_v6_0_sw_fini,
 963         .hw_init = uvd_v6_0_hw_init,
 964         .hw_fini = uvd_v6_0_hw_fini,
 965         .suspend = uvd_v6_0_suspend,
 966         .resume = uvd_v6_0_resume,
 967         .is_idle = uvd_v6_0_is_idle,
 968         .wait_for_idle = uvd_v6_0_wait_for_idle,
 969         .soft_reset = uvd_v6_0_soft_reset,
 970         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
 971         .set_powergating_state = uvd_v6_0_set_powergating_state,
 972 };
 973
 974 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
 975         .get_rptr = uvd_v6_0_ring_get_rptr,
 976         .get_wptr = uvd_v6_0_ring_get_wptr,
 977         .set_wptr = uvd_v6_0_ring_set_wptr,
 978         .parse_cs = amdgpu_uvd_ring_parse_cs,
 979         .emit_ib = uvd_v6_0_ring_emit_ib,
 980         .emit_fence = uvd_v6_0_ring_emit_fence,
 981         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 982         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
 983         .test_ring = uvd_v6_0_ring_test_ring,
 984         .test_ib = amdgpu_uvd_ring_test_ib,
 985         .insert_nop = amdgpu_ring_insert_nop,
 986         .pad_ib = amdgpu_ring_generic_pad_ib,
 987         .begin_use = amdgpu_uvd_ring_begin_use,
 988         .end_use = amdgpu_uvd_ring_end_use,
 989 };
 990
 991 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
 992         .get_rptr = uvd_v6_0_ring_get_rptr,
 993         .get_wptr = uvd_v6_0_ring_get_wptr,
 994         .set_wptr = uvd_v6_0_ring_set_wptr,
 995         .parse_cs = NULL,
 996         .emit_ib = uvd_v6_0_ring_emit_ib,
 997         .emit_fence = uvd_v6_0_ring_emit_fence,
 998         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
 999         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1000         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1001         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1002         .test_ring = uvd_v6_0_ring_test_ring,
1003         .test_ib = amdgpu_uvd_ring_test_ib,
1004         .insert_nop = amdgpu_ring_insert_nop,
1005         .pad_ib = amdgpu_ring_generic_pad_ib,
1006         .begin_use = amdgpu_uvd_ring_begin_use,
1007         .end_use = amdgpu_uvd_ring_end_use,
1008 };
1009
1010 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1011 {
1012         if (adev->asic_type >= CHIP_POLARIS10) {
1013                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1014                 DRM_INFO("UVD is enabled in VM mode\n");
1015         } else {
1016                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1017                 DRM_INFO("UVD is enabled in physical mode\n");
1018         }
1019 }
1020
1021 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1022         .set = uvd_v6_0_set_interrupt_state,
1023         .process = uvd_v6_0_process_interrupt,
1024 };
1025
1026 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1027 {
1028         adev->uvd.irq.num_types = 1;
1029         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1030 }