Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / gpu / drm / amd / include / amd_shared.h
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #ifndef __AMD_SHARED_H__
24 #define __AMD_SHARED_H__
25
26 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
27
28 /*
29 * Supported ASIC types
30 */
31 enum amd_asic_type {
32 CHIP_BONAIRE = 0,
33 CHIP_KAVERI,
34 CHIP_KABINI,
35 CHIP_HAWAII,
36 CHIP_MULLINS,
37 CHIP_TOPAZ,
38 CHIP_TONGA,
39 CHIP_FIJI,
40 CHIP_CARRIZO,
41 CHIP_STONEY,
42 CHIP_POLARIS10,
43 CHIP_POLARIS11,
44 CHIP_LAST,
45 };
46
47 /*
48 * Chip flags
49 */
50 enum amd_chip_flags {
51 AMD_ASIC_MASK = 0x0000ffffUL,
52 AMD_FLAGS_MASK = 0xffff0000UL,
53 AMD_IS_MOBILITY = 0x00010000UL,
54 AMD_IS_APU = 0x00020000UL,
55 AMD_IS_PX = 0x00040000UL,
56 AMD_EXP_HW_SUPPORT = 0x00080000UL,
57 };
58
59 enum amd_ip_block_type {
60 AMD_IP_BLOCK_TYPE_COMMON,
61 AMD_IP_BLOCK_TYPE_GMC,
62 AMD_IP_BLOCK_TYPE_IH,
63 AMD_IP_BLOCK_TYPE_SMC,
64 AMD_IP_BLOCK_TYPE_DCE,
65 AMD_IP_BLOCK_TYPE_GFX,
66 AMD_IP_BLOCK_TYPE_SDMA,
67 AMD_IP_BLOCK_TYPE_UVD,
68 AMD_IP_BLOCK_TYPE_VCE,
69 AMD_IP_BLOCK_TYPE_ACP,
70 };
71
72 enum amd_clockgating_state {
73 AMD_CG_STATE_GATE = 0,
74 AMD_CG_STATE_UNGATE,
75 };
76
77 enum amd_powergating_state {
78 AMD_PG_STATE_GATE = 0,
79 AMD_PG_STATE_UNGATE,
80 };
81
82 /* CG flags */
83 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
84 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
85 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
86 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
87 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
88 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
89 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
90 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
91 #define AMD_CG_SUPPORT_MC_LS (1 << 8)
92 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
93 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
94 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
95 #define AMD_CG_SUPPORT_BIF_LS (1 << 12)
96 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
97 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
98 #define AMD_CG_SUPPORT_HDP_LS (1 << 15)
99 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
100 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
101
102 /* PG flags */
103 #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
104 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
105 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
106 #define AMD_PG_SUPPORT_UVD (1 << 3)
107 #define AMD_PG_SUPPORT_VCE (1 << 4)
108 #define AMD_PG_SUPPORT_CP (1 << 5)
109 #define AMD_PG_SUPPORT_GDS (1 << 6)
110 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
111 #define AMD_PG_SUPPORT_SDMA (1 << 8)
112 #define AMD_PG_SUPPORT_ACP (1 << 9)
113 #define AMD_PG_SUPPORT_SAMU (1 << 10)
114 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
115 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
116
117 enum amd_pm_state_type {
118 /* not used for dpm */
119 POWER_STATE_TYPE_DEFAULT,
120 POWER_STATE_TYPE_POWERSAVE,
121 /* user selectable states */
122 POWER_STATE_TYPE_BATTERY,
123 POWER_STATE_TYPE_BALANCED,
124 POWER_STATE_TYPE_PERFORMANCE,
125 /* internal states */
126 POWER_STATE_TYPE_INTERNAL_UVD,
127 POWER_STATE_TYPE_INTERNAL_UVD_SD,
128 POWER_STATE_TYPE_INTERNAL_UVD_HD,
129 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
130 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
131 POWER_STATE_TYPE_INTERNAL_BOOT,
132 POWER_STATE_TYPE_INTERNAL_THERMAL,
133 POWER_STATE_TYPE_INTERNAL_ACPI,
134 POWER_STATE_TYPE_INTERNAL_ULV,
135 POWER_STATE_TYPE_INTERNAL_3DPERF,
136 };
137
138 struct amd_ip_funcs {
139 /* Name of IP block */
140 char *name;
141 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
142 int (*early_init)(void *handle);
143 /* sets up late driver/hw state (post hw_init) - Optional */
144 int (*late_init)(void *handle);
145 /* sets up driver state, does not configure hw */
146 int (*sw_init)(void *handle);
147 /* tears down driver state, does not configure hw */
148 int (*sw_fini)(void *handle);
149 /* sets up the hw state */
150 int (*hw_init)(void *handle);
151 /* tears down the hw state */
152 int (*hw_fini)(void *handle);
153 void (*late_fini)(void *handle);
154 /* handles IP specific hw/sw changes for suspend */
155 int (*suspend)(void *handle);
156 /* handles IP specific hw/sw changes for resume */
157 int (*resume)(void *handle);
158 /* returns current IP block idle status */
159 bool (*is_idle)(void *handle);
160 /* poll for idle */
161 int (*wait_for_idle)(void *handle);
162 /* check soft reset the IP block */
163 int (*check_soft_reset)(void *handle);
164 /* pre soft reset the IP block */
165 int (*pre_soft_reset)(void *handle);
166 /* soft reset the IP block */
167 int (*soft_reset)(void *handle);
168 /* post soft reset the IP block */
169 int (*post_soft_reset)(void *handle);
170 /* enable/disable cg for the IP block */
171 int (*set_clockgating_state)(void *handle,
172 enum amd_clockgating_state state);
173 /* enable/disable pg for the IP block */
174 int (*set_powergating_state)(void *handle,
175 enum amd_powergating_state state);
176 };
177
178 #endif /* __AMD_SHARED_H__ */
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