2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMD_SHARED_H__
24 #define __AMD_SHARED_H__
26 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
29 * Supported GPU families (aligned with amdgpu_drm.h)
31 #define AMD_FAMILY_UNKNOWN 0
32 #define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */
33 #define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
34 #define AMD_FAMILY_VI 130 /* Iceland, Tonga */
35 #define AMD_FAMILY_CZ 135 /* Carrizo */
38 * Supported ASIC types
58 AMD_ASIC_MASK
= 0x0000ffffUL
,
59 AMD_FLAGS_MASK
= 0xffff0000UL
,
60 AMD_IS_MOBILITY
= 0x00010000UL
,
61 AMD_IS_APU
= 0x00020000UL
,
62 AMD_IS_PX
= 0x00040000UL
,
63 AMD_EXP_HW_SUPPORT
= 0x00080000UL
,
66 enum amd_ip_block_type
{
67 AMD_IP_BLOCK_TYPE_COMMON
,
68 AMD_IP_BLOCK_TYPE_GMC
,
70 AMD_IP_BLOCK_TYPE_SMC
,
71 AMD_IP_BLOCK_TYPE_DCE
,
72 AMD_IP_BLOCK_TYPE_GFX
,
73 AMD_IP_BLOCK_TYPE_SDMA
,
74 AMD_IP_BLOCK_TYPE_UVD
,
75 AMD_IP_BLOCK_TYPE_VCE
,
78 enum amd_clockgating_state
{
79 AMD_CG_STATE_GATE
= 0,
83 enum amd_powergating_state
{
84 AMD_PG_STATE_GATE
= 0,
89 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
90 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
91 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
92 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
93 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
94 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
95 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
96 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
97 #define AMD_CG_SUPPORT_MC_LS (1 << 8)
98 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
99 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
100 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
101 #define AMD_CG_SUPPORT_BIF_LS (1 << 12)
102 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
103 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
104 #define AMD_CG_SUPPORT_HDP_LS (1 << 15)
105 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
108 #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
109 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
110 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
111 #define AMD_PG_SUPPORT_UVD (1 << 3)
112 #define AMD_PG_SUPPORT_VCE (1 << 4)
113 #define AMD_PG_SUPPORT_CP (1 << 5)
114 #define AMD_PG_SUPPORT_GDS (1 << 6)
115 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
116 #define AMD_PG_SUPPORT_SDMA (1 << 8)
117 #define AMD_PG_SUPPORT_ACP (1 << 9)
118 #define AMD_PG_SUPPORT_SAMU (1 << 10)
120 enum amd_pm_state_type
{
121 /* not used for dpm */
122 POWER_STATE_TYPE_DEFAULT
,
123 POWER_STATE_TYPE_POWERSAVE
,
124 /* user selectable states */
125 POWER_STATE_TYPE_BATTERY
,
126 POWER_STATE_TYPE_BALANCED
,
127 POWER_STATE_TYPE_PERFORMANCE
,
128 /* internal states */
129 POWER_STATE_TYPE_INTERNAL_UVD
,
130 POWER_STATE_TYPE_INTERNAL_UVD_SD
,
131 POWER_STATE_TYPE_INTERNAL_UVD_HD
,
132 POWER_STATE_TYPE_INTERNAL_UVD_HD2
,
133 POWER_STATE_TYPE_INTERNAL_UVD_MVC
,
134 POWER_STATE_TYPE_INTERNAL_BOOT
,
135 POWER_STATE_TYPE_INTERNAL_THERMAL
,
136 POWER_STATE_TYPE_INTERNAL_ACPI
,
137 POWER_STATE_TYPE_INTERNAL_ULV
,
138 POWER_STATE_TYPE_INTERNAL_3DPERF
,
141 struct amd_ip_funcs
{
142 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
143 int (*early_init
)(void *handle
);
144 /* sets up late driver/hw state (post hw_init) - Optional */
145 int (*late_init
)(void *handle
);
146 /* sets up driver state, does not configure hw */
147 int (*sw_init
)(void *handle
);
148 /* tears down driver state, does not configure hw */
149 int (*sw_fini
)(void *handle
);
150 /* sets up the hw state */
151 int (*hw_init
)(void *handle
);
152 /* tears down the hw state */
153 int (*hw_fini
)(void *handle
);
154 /* handles IP specific hw/sw changes for suspend */
155 int (*suspend
)(void *handle
);
156 /* handles IP specific hw/sw changes for resume */
157 int (*resume
)(void *handle
);
158 /* returns current IP block idle status */
159 bool (*is_idle
)(void *handle
);
161 int (*wait_for_idle
)(void *handle
);
162 /* soft reset the IP block */
163 int (*soft_reset
)(void *handle
);
164 /* dump the IP block status registers */
165 void (*print_status
)(void *handle
);
166 /* enable/disable cg for the IP block */
167 int (*set_clockgating_state
)(void *handle
,
168 enum amd_clockgating_state state
);
169 /* enable/disable pg for the IP block */
170 int (*set_powergating_state
)(void *handle
,
171 enum amd_powergating_state state
);
174 #endif /* __AMD_SHARED_H__ */