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Merge tag 'drm-vc4-next-2016-02-17' of github.com:anholt/linux into drm-next
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / cz_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include "atom-types.h"
27 #include "atombios.h"
28 #include "processpptables.h"
29 #include "pp_debug.h"
30 #include "cgs_common.h"
31 #include "smu/smu_8_0_d.h"
32 #include "smu8_fusion.h"
33 #include "smu/smu_8_0_sh_mask.h"
34 #include "smumgr.h"
35 #include "hwmgr.h"
36 #include "hardwaremanager.h"
37 #include "cz_ppsmc.h"
38 #include "cz_hwmgr.h"
39 #include "power_state.h"
40 #include "cz_clockpowergating.h"
41 #include "pp_debug.h"
42
43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
44 #define CURRENT_NB_VID_MASK 0xff000000
45 #define CURRENT_NB_VID__SHIFT 24
46 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048
47 #define CURRENT_GFX_VID_MASK 0xff000000
48 #define CURRENT_GFX_VID__SHIFT 24
49
50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
51
52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
53 {
54 if (PhwCz_Magic != hw_ps->magic)
55 return NULL;
56
57 return (struct cz_power_state *)hw_ps;
58 }
59
60 static const struct cz_power_state *cast_const_PhwCzPowerState(
61 const struct pp_hw_power_state *hw_ps)
62 {
63 if (PhwCz_Magic != hw_ps->magic)
64 return NULL;
65
66 return (struct cz_power_state *)hw_ps;
67 }
68
69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
70 uint32_t clock, uint32_t msg)
71 {
72 int i = 0;
73 struct phm_vce_clock_voltage_dependency_table *ptable =
74 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
75
76 switch (msg) {
77 case PPSMC_MSG_SetEclkSoftMin:
78 case PPSMC_MSG_SetEclkHardMin:
79 for (i = 0; i < (int)ptable->count; i++) {
80 if (clock <= ptable->entries[i].ecclk)
81 break;
82 }
83 break;
84
85 case PPSMC_MSG_SetEclkSoftMax:
86 case PPSMC_MSG_SetEclkHardMax:
87 for (i = ptable->count - 1; i >= 0; i--) {
88 if (clock >= ptable->entries[i].ecclk)
89 break;
90 }
91 break;
92
93 default:
94 break;
95 }
96
97 return i;
98 }
99
100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
101 uint32_t clock, uint32_t msg)
102 {
103 int i = 0;
104 struct phm_clock_voltage_dependency_table *table =
105 hwmgr->dyn_state.vddc_dependency_on_sclk;
106
107 switch (msg) {
108 case PPSMC_MSG_SetSclkSoftMin:
109 case PPSMC_MSG_SetSclkHardMin:
110 for (i = 0; i < (int)table->count; i++) {
111 if (clock <= table->entries[i].clk)
112 break;
113 }
114 break;
115
116 case PPSMC_MSG_SetSclkSoftMax:
117 case PPSMC_MSG_SetSclkHardMax:
118 for (i = table->count - 1; i >= 0; i--) {
119 if (clock >= table->entries[i].clk)
120 break;
121 }
122 break;
123
124 default:
125 break;
126 }
127 return i;
128 }
129
130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
131 uint32_t clock, uint32_t msg)
132 {
133 int i = 0;
134 struct phm_uvd_clock_voltage_dependency_table *ptable =
135 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
136
137 switch (msg) {
138 case PPSMC_MSG_SetUvdSoftMin:
139 case PPSMC_MSG_SetUvdHardMin:
140 for (i = 0; i < (int)ptable->count; i++) {
141 if (clock <= ptable->entries[i].vclk)
142 break;
143 }
144 break;
145
146 case PPSMC_MSG_SetUvdSoftMax:
147 case PPSMC_MSG_SetUvdHardMax:
148 for (i = ptable->count - 1; i >= 0; i--) {
149 if (clock >= ptable->entries[i].vclk)
150 break;
151 }
152 break;
153
154 default:
155 break;
156 }
157
158 return i;
159 }
160
161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
162 {
163 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
164
165 if (cz_hwmgr->max_sclk_level == 0) {
166 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
167 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
168 }
169
170 return cz_hwmgr->max_sclk_level;
171 }
172
173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
174 {
175 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
176 uint32_t i;
177
178 cz_hwmgr->gfx_ramp_step = 256*25/100;
179
180 cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
181
182 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
183 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
184
185 cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
186 cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
187
188 cz_hwmgr->clock_slow_down_freq = 25000;
189
190 cz_hwmgr->skip_clock_slow_down = 1;
191
192 cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
193
194 cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
195
196 cz_hwmgr->voting_rights_clients = 0x00C00033;
197
198 cz_hwmgr->static_screen_threshold = 8;
199
200 cz_hwmgr->ddi_power_gating_disabled = 0;
201
202 cz_hwmgr->bapm_enabled = 1;
203
204 cz_hwmgr->voltage_drop_threshold = 0;
205
206 cz_hwmgr->gfx_power_gating_threshold = 500;
207
208 cz_hwmgr->vce_slow_sclk_threshold = 20000;
209
210 cz_hwmgr->dce_slow_sclk_threshold = 30000;
211
212 cz_hwmgr->disable_driver_thermal_policy = 1;
213
214 cz_hwmgr->disable_nb_ps3_in_battery = 0;
215
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_ABM);
218
219 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_NonABMSupportInPPLib);
221
222 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_SclkDeepSleep);
224
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_DynamicM3Arbiter);
227
228 cz_hwmgr->override_dynamic_mgpg = 1;
229
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_DynamicPatchPowerState);
232
233 cz_hwmgr->thermal_auto_throttling_treshold = 0;
234
235 cz_hwmgr->tdr_clock = 0;
236
237 cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
238
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_DynamicUVDState);
241
242 cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
243 cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
244 cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
245 cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
246
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_DisableVoltageIsland);
249
250 return 0;
251 }
252
253 static uint32_t cz_convert_8Bit_index_to_voltage(
254 struct pp_hwmgr *hwmgr, uint16_t voltage)
255 {
256 return 6200 - (voltage * 25);
257 }
258
259 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
260 struct phm_clock_and_voltage_limits *table)
261 {
262 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
263 struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
264 struct phm_clock_voltage_dependency_table *dep_table =
265 hwmgr->dyn_state.vddc_dependency_on_sclk;
266
267 if (dep_table->count > 0) {
268 table->sclk = dep_table->entries[dep_table->count-1].clk;
269 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
270 (uint16_t)dep_table->entries[dep_table->count-1].v);
271 }
272 table->mclk = sys_info->nbp_memory_clock[0];
273 return 0;
274 }
275
276 static int cz_init_dynamic_state_adjustment_rule_settings(
277 struct pp_hwmgr *hwmgr,
278 ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
279 {
280 uint32_t table_size =
281 sizeof(struct phm_clock_voltage_dependency_table) +
282 (7 * sizeof(struct phm_clock_voltage_dependency_record));
283
284 struct phm_clock_voltage_dependency_table *table_clk_vlt =
285 kzalloc(table_size, GFP_KERNEL);
286
287 if (NULL == table_clk_vlt) {
288 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
289 return -ENOMEM;
290 }
291
292 table_clk_vlt->count = 8;
293 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
294 table_clk_vlt->entries[0].v = 0;
295 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
296 table_clk_vlt->entries[1].v = 1;
297 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
298 table_clk_vlt->entries[2].v = 2;
299 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
300 table_clk_vlt->entries[3].v = 3;
301 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
302 table_clk_vlt->entries[4].v = 4;
303 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
304 table_clk_vlt->entries[5].v = 5;
305 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
306 table_clk_vlt->entries[6].v = 6;
307 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
308 table_clk_vlt->entries[7].v = 7;
309 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
310
311 return 0;
312 }
313
314 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
315 {
316 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
317 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
318 uint32_t i;
319 int result = 0;
320 uint8_t frev, crev;
321 uint16_t size;
322
323 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
324 hwmgr->device,
325 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
326 &size, &frev, &crev);
327
328 if (crev != 9) {
329 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
330 return -EINVAL;
331 }
332
333 if (info == NULL) {
334 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
335 return -EINVAL;
336 }
337
338 cz_hwmgr->sys_info.bootup_uma_clock =
339 le32_to_cpu(info->ulBootUpUMAClock);
340
341 cz_hwmgr->sys_info.bootup_engine_clock =
342 le32_to_cpu(info->ulBootUpEngineClock);
343
344 cz_hwmgr->sys_info.dentist_vco_freq =
345 le32_to_cpu(info->ulDentistVCOFreq);
346
347 cz_hwmgr->sys_info.system_config =
348 le32_to_cpu(info->ulSystemConfig);
349
350 cz_hwmgr->sys_info.bootup_nb_voltage_index =
351 le16_to_cpu(info->usBootUpNBVoltage);
352
353 cz_hwmgr->sys_info.htc_hyst_lmt =
354 (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
355
356 cz_hwmgr->sys_info.htc_tmp_lmt =
357 (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
358
359 if (cz_hwmgr->sys_info.htc_tmp_lmt <=
360 cz_hwmgr->sys_info.htc_hyst_lmt) {
361 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
362 return -EINVAL;
363 }
364
365 cz_hwmgr->sys_info.nb_dpm_enable =
366 cz_hwmgr->enable_nb_ps_policy &&
367 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
368
369 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
370 if (i < CZ_NUM_NBPMEMORYCLOCK) {
371 cz_hwmgr->sys_info.nbp_memory_clock[i] =
372 le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
373 }
374 cz_hwmgr->sys_info.nbp_n_clock[i] =
375 le32_to_cpu(info->ulNbpStateNClkFreq[i]);
376 }
377
378 for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
379 cz_hwmgr->sys_info.display_clock[i] =
380 le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
381 }
382
383 /* Here use 4 levels, make sure not exceed */
384 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
385 cz_hwmgr->sys_info.nbp_voltage_index[i] =
386 le16_to_cpu(info->usNBPStateVoltage[i]);
387 }
388
389 if (!cz_hwmgr->sys_info.nb_dpm_enable) {
390 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
391 if (i < CZ_NUM_NBPMEMORYCLOCK) {
392 cz_hwmgr->sys_info.nbp_memory_clock[i] =
393 cz_hwmgr->sys_info.nbp_memory_clock[0];
394 }
395 cz_hwmgr->sys_info.nbp_n_clock[i] =
396 cz_hwmgr->sys_info.nbp_n_clock[0];
397 cz_hwmgr->sys_info.nbp_voltage_index[i] =
398 cz_hwmgr->sys_info.nbp_voltage_index[0];
399 }
400 }
401
402 if (le32_to_cpu(info->ulGPUCapInfo) &
403 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
404 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
405 PHM_PlatformCaps_EnableDFSBypass);
406 }
407
408 cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
409
410 cz_construct_max_power_limits_table (hwmgr,
411 &hwmgr->dyn_state.max_clock_voltage_on_ac);
412
413 cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
414 &info->sDISPCLK_Voltage[0]);
415
416 return result;
417 }
418
419 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
420 {
421 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
422
423 cz_hwmgr->boot_power_level.engineClock =
424 cz_hwmgr->sys_info.bootup_engine_clock;
425
426 cz_hwmgr->boot_power_level.vddcIndex =
427 (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
428
429 cz_hwmgr->boot_power_level.dsDividerIndex = 0;
430
431 cz_hwmgr->boot_power_level.ssDividerIndex = 0;
432
433 cz_hwmgr->boot_power_level.allowGnbSlow = 1;
434
435 cz_hwmgr->boot_power_level.forceNBPstate = 0;
436
437 cz_hwmgr->boot_power_level.hysteresis_up = 0;
438
439 cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
440
441 cz_hwmgr->boot_power_level.display_wm = 0;
442
443 cz_hwmgr->boot_power_level.vce_wm = 0;
444
445 return 0;
446 }
447
448 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
449 void *output, void *storage, int result)
450 {
451 return 0;
452 }
453
454 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
455 void *output, void *storage, int result)
456 {
457 struct SMU8_Fusion_ClkTable *clock_table;
458 int ret;
459 uint32_t i;
460 void *table = NULL;
461 pp_atomctrl_clock_dividers_kong dividers;
462
463 struct phm_clock_voltage_dependency_table *vddc_table =
464 hwmgr->dyn_state.vddc_dependency_on_sclk;
465 struct phm_clock_voltage_dependency_table *vdd_gfx_table =
466 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
467 struct phm_acp_clock_voltage_dependency_table *acp_table =
468 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
469 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
470 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
471 struct phm_vce_clock_voltage_dependency_table *vce_table =
472 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
473
474 if (!hwmgr->need_pp_table_upload)
475 return 0;
476
477 ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
478
479 PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
480 "Fail to get clock table from SMU!", return -EINVAL;);
481
482 clock_table = (struct SMU8_Fusion_ClkTable *)table;
483
484 /* patch clock table */
485 PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
486 "Dependency table entry exceeds max limit!", return -EINVAL;);
487 PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
488 "Dependency table entry exceeds max limit!", return -EINVAL;);
489 PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
490 "Dependency table entry exceeds max limit!", return -EINVAL;);
491 PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
492 "Dependency table entry exceeds max limit!", return -EINVAL;);
493 PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
494 "Dependency table entry exceeds max limit!", return -EINVAL;);
495
496 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
497
498 /* vddc_sclk */
499 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
500 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
501 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
502 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
503
504 atomctrl_get_engine_pll_dividers_kong(hwmgr,
505 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
506 &dividers);
507
508 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
509 (uint8_t)dividers.pll_post_divider;
510
511 /* vddgfx_sclk */
512 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
513 (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
514
515 /* acp breakdown */
516 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
517 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
518 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
519 (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
520
521 atomctrl_get_engine_pll_dividers_kong(hwmgr,
522 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
523 &dividers);
524
525 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
526 (uint8_t)dividers.pll_post_divider;
527
528
529 /* uvd breakdown */
530 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
531 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
532 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
533 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
534
535 atomctrl_get_engine_pll_dividers_kong(hwmgr,
536 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
537 &dividers);
538
539 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
540 (uint8_t)dividers.pll_post_divider;
541
542 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
543 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
544 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
545 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
546
547 atomctrl_get_engine_pll_dividers_kong(hwmgr,
548 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
549 &dividers);
550
551 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
552 (uint8_t)dividers.pll_post_divider;
553
554 /* vce breakdown */
555 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
556 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
557 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
558 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
559
560
561 atomctrl_get_engine_pll_dividers_kong(hwmgr,
562 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
563 &dividers);
564
565 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
566 (uint8_t)dividers.pll_post_divider;
567
568 }
569 ret = smum_upload_powerplay_table(hwmgr->smumgr);
570
571 return ret;
572 }
573
574 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
575 void *output, void *storage, int result)
576 {
577 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
578 struct phm_clock_voltage_dependency_table *table =
579 hwmgr->dyn_state.vddc_dependency_on_sclk;
580 unsigned long clock = 0, level;
581
582 if (NULL == table || table->count <= 0)
583 return -EINVAL;
584
585 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
586 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
587
588 level = cz_get_max_sclk_level(hwmgr) - 1;
589
590 if (level < table->count)
591 clock = table->entries[level].clk;
592 else
593 clock = table->entries[table->count - 1].clk;
594
595 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
596 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
597
598 return 0;
599 }
600
601 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
602 void *output, void *storage, int result)
603 {
604 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
605 struct phm_uvd_clock_voltage_dependency_table *table =
606 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
607 unsigned long clock = 0, level;
608
609 if (NULL == table || table->count <= 0)
610 return -EINVAL;
611
612 cz_hwmgr->uvd_dpm.soft_min_clk = 0;
613 cz_hwmgr->uvd_dpm.hard_min_clk = 0;
614
615 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
616 level = smum_get_argument(hwmgr->smumgr);
617
618 if (level < table->count)
619 clock = table->entries[level].vclk;
620 else
621 clock = table->entries[table->count - 1].vclk;
622
623 cz_hwmgr->uvd_dpm.soft_max_clk = clock;
624 cz_hwmgr->uvd_dpm.hard_max_clk = clock;
625
626 return 0;
627 }
628
629 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
630 void *output, void *storage, int result)
631 {
632 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
633 struct phm_vce_clock_voltage_dependency_table *table =
634 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
635 unsigned long clock = 0, level;
636
637 if (NULL == table || table->count <= 0)
638 return -EINVAL;
639
640 cz_hwmgr->vce_dpm.soft_min_clk = 0;
641 cz_hwmgr->vce_dpm.hard_min_clk = 0;
642
643 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
644 level = smum_get_argument(hwmgr->smumgr);
645
646 if (level < table->count)
647 clock = table->entries[level].ecclk;
648 else
649 clock = table->entries[table->count - 1].ecclk;
650
651 cz_hwmgr->vce_dpm.soft_max_clk = clock;
652 cz_hwmgr->vce_dpm.hard_max_clk = clock;
653
654 return 0;
655 }
656
657 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
658 void *output, void *storage, int result)
659 {
660 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
661 struct phm_acp_clock_voltage_dependency_table *table =
662 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
663 unsigned long clock = 0, level;
664
665 if (NULL == table || table->count <= 0)
666 return -EINVAL;
667
668 cz_hwmgr->acp_dpm.soft_min_clk = 0;
669 cz_hwmgr->acp_dpm.hard_min_clk = 0;
670
671 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
672 level = smum_get_argument(hwmgr->smumgr);
673
674 if (level < table->count)
675 clock = table->entries[level].acpclk;
676 else
677 clock = table->entries[table->count - 1].acpclk;
678
679 cz_hwmgr->acp_dpm.soft_max_clk = clock;
680 cz_hwmgr->acp_dpm.hard_max_clk = clock;
681 return 0;
682 }
683
684 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
685 void *output, void *storage, int result)
686 {
687 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
688
689 cz_hwmgr->uvd_power_gated = false;
690 cz_hwmgr->vce_power_gated = false;
691 cz_hwmgr->samu_power_gated = false;
692 cz_hwmgr->acp_power_gated = false;
693 cz_hwmgr->pgacpinit = true;
694
695 return 0;
696 }
697
698 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
699 void *output, void *storage, int result)
700 {
701 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
702
703 cz_hwmgr->low_sclk_interrupt_threshold = 0;
704
705 return 0;
706 }
707 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
708 void *input, void *output,
709 void *storage, int result)
710 {
711 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
712 struct phm_clock_voltage_dependency_table *table =
713 hwmgr->dyn_state.vddc_dependency_on_sclk;
714
715 unsigned long clock = 0;
716 unsigned long level;
717 unsigned long stable_pstate_sclk;
718 unsigned long percentage;
719
720 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
721 level = cz_get_max_sclk_level(hwmgr) - 1;
722
723 if (level < table->count)
724 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
725 else
726 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
727
728 clock = hwmgr->display_config.min_core_set_clock;
729 if (clock == 0)
730 printk(KERN_ERR "[ powerplay ] min_core_set_clock not set\n");
731
732 if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
733 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
734
735 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
736 PPSMC_MSG_SetSclkHardMin,
737 cz_get_sclk_level(hwmgr,
738 cz_hwmgr->sclk_dpm.hard_min_clk,
739 PPSMC_MSG_SetSclkHardMin));
740 }
741
742 clock = cz_hwmgr->sclk_dpm.soft_min_clk;
743
744 /* update minimum clocks for Stable P-State feature */
745 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
746 PHM_PlatformCaps_StablePState)) {
747 percentage = 75;
748 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
749 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
750 percentage) / 100;
751
752 if (clock < stable_pstate_sclk)
753 clock = stable_pstate_sclk;
754 } else {
755 if (clock < hwmgr->gfx_arbiter.sclk)
756 clock = hwmgr->gfx_arbiter.sclk;
757 }
758
759 if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
760 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
761 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
762 PPSMC_MSG_SetSclkSoftMin,
763 cz_get_sclk_level(hwmgr,
764 cz_hwmgr->sclk_dpm.soft_min_clk,
765 PPSMC_MSG_SetSclkSoftMin));
766 }
767
768 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
769 PHM_PlatformCaps_StablePState) &&
770 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
771 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
772 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
773 PPSMC_MSG_SetSclkSoftMax,
774 cz_get_sclk_level(hwmgr,
775 cz_hwmgr->sclk_dpm.soft_max_clk,
776 PPSMC_MSG_SetSclkSoftMax));
777 }
778
779 return 0;
780 }
781
782 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
783 void *input, void *output,
784 void *storage, int result)
785 {
786 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
787 PHM_PlatformCaps_SclkDeepSleep)) {
788 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
789 if (clks == 0)
790 clks = CZ_MIN_DEEP_SLEEP_SCLK;
791
792 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
793
794 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
795 PPSMC_MSG_SetMinDeepSleepSclk,
796 clks);
797 }
798
799 return 0;
800 }
801
802 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
803 void *input, void *output,
804 void *storage, int result)
805 {
806 struct cz_hwmgr *cz_hwmgr =
807 (struct cz_hwmgr *)(hwmgr->backend);
808
809 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
810 PPSMC_MSG_SetWatermarkFrequency,
811 cz_hwmgr->sclk_dpm.soft_max_clk);
812
813 return 0;
814 }
815
816 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
817 void *input, void *output,
818 void *storage, int result)
819 {
820 return 0;
821 }
822
823
824 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
825 void *input, void *output,
826 void *storage, int result)
827 {
828 int ret = 0;
829
830 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
831 unsigned long dpm_features = 0;
832
833 if (!cz_hwmgr->is_nb_dpm_enabled) {
834 PP_DBG_LOG("enabling ALL SMU features.\n");
835 dpm_features |= NB_DPM_MASK;
836 ret = smum_send_msg_to_smc_with_parameter(
837 hwmgr->smumgr,
838 PPSMC_MSG_EnableAllSmuFeatures,
839 dpm_features);
840 if (ret == 0)
841 cz_hwmgr->is_nb_dpm_enabled = true;
842 }
843
844 return ret;
845 }
846
847 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
848 {
849 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
850
851 if (hw_data->is_nb_dpm_enabled) {
852 if (enable) {
853 PP_DBG_LOG("enable Low Memory PState.\n");
854
855 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
856 PPSMC_MSG_EnableLowMemoryPstate,
857 (lock ? 1 : 0));
858 } else {
859 PP_DBG_LOG("disable Low Memory PState.\n");
860
861 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
862 PPSMC_MSG_DisableLowMemoryPstate,
863 (lock ? 1 : 0));
864 }
865 }
866
867 return 0;
868 }
869
870 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
871 void *input, void *output,
872 void *storage, int result)
873 {
874 bool disable_switch;
875 bool enable_low_mem_state;
876 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
877 const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
878 const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
879
880 if (hw_data->sys_info.nb_dpm_enable) {
881 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
882 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
883
884 if (pnew_state->action == FORCE_HIGH)
885 cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
886 else if (pnew_state->action == CANCEL_FORCE_HIGH)
887 cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
888 else
889 cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
890 }
891 return 0;
892 }
893
894 static struct phm_master_table_item cz_set_power_state_list[] = {
895 {NULL, cz_tf_update_sclk_limit},
896 {NULL, cz_tf_set_deep_sleep_sclk_threshold},
897 {NULL, cz_tf_set_watermark_threshold},
898 {NULL, cz_tf_set_enabled_levels},
899 {NULL, cz_tf_enable_nb_dpm},
900 {NULL, cz_tf_update_low_mem_pstate},
901 {NULL, NULL}
902 };
903
904 static struct phm_master_table_header cz_set_power_state_master = {
905 0,
906 PHM_MasterTableFlag_None,
907 cz_set_power_state_list
908 };
909
910 static struct phm_master_table_item cz_setup_asic_list[] = {
911 {NULL, cz_tf_reset_active_process_mask},
912 {NULL, cz_tf_upload_pptable_to_smu},
913 {NULL, cz_tf_init_sclk_limit},
914 {NULL, cz_tf_init_uvd_limit},
915 {NULL, cz_tf_init_vce_limit},
916 {NULL, cz_tf_init_acp_limit},
917 {NULL, cz_tf_init_power_gate_state},
918 {NULL, cz_tf_init_sclk_threshold},
919 {NULL, NULL}
920 };
921
922 static struct phm_master_table_header cz_setup_asic_master = {
923 0,
924 PHM_MasterTableFlag_None,
925 cz_setup_asic_list
926 };
927
928 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
929 void *input, void *output,
930 void *storage, int result)
931 {
932 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
933 hw_data->disp_clk_bypass_pending = false;
934 hw_data->disp_clk_bypass = false;
935
936 return 0;
937 }
938
939 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
940 void *input, void *output,
941 void *storage, int result)
942 {
943 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
944 hw_data->is_nb_dpm_enabled = false;
945
946 return 0;
947 }
948
949 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
950 void *input, void *output,
951 void *storage, int result)
952 {
953 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
954
955 hw_data->cc6_settings.cc6_setting_changed = false;
956 hw_data->cc6_settings.cpu_pstate_separation_time = 0;
957 hw_data->cc6_settings.cpu_cc6_disable = false;
958 hw_data->cc6_settings.cpu_pstate_disable = false;
959
960 return 0;
961 }
962
963 static struct phm_master_table_item cz_power_down_asic_list[] = {
964 {NULL, cz_tf_power_up_display_clock_sys_pll},
965 {NULL, cz_tf_clear_nb_dpm_flag},
966 {NULL, cz_tf_reset_cc6_data},
967 {NULL, NULL}
968 };
969
970 static struct phm_master_table_header cz_power_down_asic_master = {
971 0,
972 PHM_MasterTableFlag_None,
973 cz_power_down_asic_list
974 };
975
976 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
977 void *output, void *storage, int result)
978 {
979 PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
980 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
981 return 0;
982 }
983
984 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
985 void *storage, int result)
986 {
987 int res = 0xff;
988 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
989 unsigned long dpm_features = 0;
990
991 cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
992 dpm_features |= SCLK_DPM_MASK;
993
994 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
995 PPSMC_MSG_EnableAllSmuFeatures,
996 dpm_features);
997
998 return res;
999 }
1000
1001 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
1002 void *output, void *storage, int result)
1003 {
1004 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1005
1006 cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1007 cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1008
1009 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1010 PPSMC_MSG_SetSclkSoftMin,
1011 cz_get_sclk_level(hwmgr,
1012 cz_hwmgr->sclk_dpm.soft_min_clk,
1013 PPSMC_MSG_SetSclkSoftMin));
1014
1015 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1016 PPSMC_MSG_SetSclkSoftMax,
1017 cz_get_sclk_level(hwmgr,
1018 cz_hwmgr->sclk_dpm.soft_max_clk,
1019 PPSMC_MSG_SetSclkSoftMax));
1020
1021 return 0;
1022 }
1023
1024 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1025 void *output, void *storage, int result)
1026 {
1027 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1028
1029 cz_hwmgr->acp_boot_level = 0xff;
1030 return 0;
1031 }
1032
1033 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1034 unsigned long check_feature)
1035 {
1036 int result;
1037 unsigned long features;
1038
1039 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1040 if (result == 0) {
1041 features = smum_get_argument(hwmgr->smumgr);
1042 if (features & check_feature)
1043 return true;
1044 }
1045
1046 return result;
1047 }
1048
1049 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1050 void *output, void *storage, int result)
1051 {
1052 if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1053 return PP_Result_TableImmediateExit;
1054 return 0;
1055 }
1056
1057 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1058 void *output, void *storage, int result)
1059 {
1060 /* TO DO */
1061 return 0;
1062 }
1063
1064 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1065 void *input, void *output,
1066 void *storage, int result)
1067 {
1068 if (!cz_dpm_check_smu_features(hwmgr,
1069 SMU_EnabledFeatureScoreboard_SclkDpmOn))
1070 return PP_Result_TableImmediateExit;
1071 return 0;
1072 }
1073
1074 static struct phm_master_table_item cz_disable_dpm_list[] = {
1075 { NULL, cz_tf_check_for_dpm_enabled},
1076 {NULL, NULL},
1077 };
1078
1079
1080 static struct phm_master_table_header cz_disable_dpm_master = {
1081 0,
1082 PHM_MasterTableFlag_None,
1083 cz_disable_dpm_list
1084 };
1085
1086 static struct phm_master_table_item cz_enable_dpm_list[] = {
1087 { NULL, cz_tf_check_for_dpm_disabled },
1088 { NULL, cz_tf_program_voting_clients },
1089 { NULL, cz_tf_start_dpm},
1090 { NULL, cz_tf_program_bootup_state},
1091 { NULL, cz_tf_enable_didt },
1092 { NULL, cz_tf_reset_acp_boot_level },
1093 {NULL, NULL},
1094 };
1095
1096 static struct phm_master_table_header cz_enable_dpm_master = {
1097 0,
1098 PHM_MasterTableFlag_None,
1099 cz_enable_dpm_list
1100 };
1101
1102 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1103 struct pp_power_state *prequest_ps,
1104 const struct pp_power_state *pcurrent_ps)
1105 {
1106 struct cz_power_state *cz_ps =
1107 cast_PhwCzPowerState(&prequest_ps->hardware);
1108
1109 const struct cz_power_state *cz_current_ps =
1110 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1111
1112 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1113 struct PP_Clocks clocks = {0, 0, 0, 0};
1114 bool force_high;
1115 uint32_t num_of_active_displays = 0;
1116 struct cgs_display_info info = {0};
1117
1118 cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1119 cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1120
1121 cz_ps->need_dfs_bypass = true;
1122
1123 cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1124 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1125
1126 cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1127
1128 clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1129 hwmgr->display_config.min_mem_set_clock :
1130 cz_hwmgr->sys_info.nbp_memory_clock[1];
1131
1132 cgs_get_active_displays_info(hwmgr->device, &info);
1133 num_of_active_displays = info.display_count;
1134
1135 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1136 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1137
1138 if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1139 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1140
1141 force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1142 || (num_of_active_displays >= 3);
1143
1144 cz_ps->action = cz_current_ps->action;
1145
1146 if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
1147 cz_ps->action = CANCEL_FORCE_HIGH;
1148 else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
1149 cz_ps->action = FORCE_HIGH;
1150 else
1151 cz_ps->action = DO_NOTHING;
1152
1153 return 0;
1154 }
1155
1156 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1157 {
1158 int result = 0;
1159
1160 result = cz_initialize_dpm_defaults(hwmgr);
1161 if (result != 0) {
1162 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1163 return result;
1164 }
1165
1166 result = cz_get_system_info_data(hwmgr);
1167 if (result != 0) {
1168 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1169 return result;
1170 }
1171
1172 cz_construct_boot_state(hwmgr);
1173
1174 result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1175 &(hwmgr->setup_asic));
1176 if (result != 0) {
1177 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1178 return result;
1179 }
1180
1181 result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1182 &(hwmgr->power_down_asic));
1183 if (result != 0) {
1184 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1185 return result;
1186 }
1187
1188 result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1189 &(hwmgr->disable_dynamic_state_management));
1190 if (result != 0) {
1191 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1192 return result;
1193 }
1194 result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1195 &(hwmgr->enable_dynamic_state_management));
1196 if (result != 0) {
1197 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1198 return result;
1199 }
1200 result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1201 &(hwmgr->set_power_state));
1202 if (result != 0) {
1203 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1204 return result;
1205 }
1206 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS;
1207
1208 result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1209 if (result != 0) {
1210 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1211 return result;
1212 }
1213 return result;
1214 }
1215
1216 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1217 {
1218 if (hwmgr != NULL || hwmgr->backend != NULL) {
1219 kfree(hwmgr->backend);
1220 kfree(hwmgr);
1221 }
1222 return 0;
1223 }
1224
1225 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1226 {
1227 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1228
1229 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1230 cz_hwmgr->sclk_dpm.soft_max_clk)
1231 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1232 PPSMC_MSG_SetSclkSoftMin,
1233 cz_get_sclk_level(hwmgr,
1234 cz_hwmgr->sclk_dpm.soft_max_clk,
1235 PPSMC_MSG_SetSclkSoftMin));
1236 return 0;
1237 }
1238
1239 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1240 {
1241 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1242 struct phm_clock_voltage_dependency_table *table =
1243 hwmgr->dyn_state.vddc_dependency_on_sclk;
1244 unsigned long clock = 0, level;
1245
1246 if (NULL == table || table->count <= 0)
1247 return -EINVAL;
1248
1249 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1250 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1251
1252 level = cz_get_max_sclk_level(hwmgr) - 1;
1253
1254 if (level < table->count)
1255 clock = table->entries[level].clk;
1256 else
1257 clock = table->entries[table->count - 1].clk;
1258
1259 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1260 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1261
1262 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1263 PPSMC_MSG_SetSclkSoftMin,
1264 cz_get_sclk_level(hwmgr,
1265 cz_hwmgr->sclk_dpm.soft_min_clk,
1266 PPSMC_MSG_SetSclkSoftMin));
1267
1268 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1269 PPSMC_MSG_SetSclkSoftMax,
1270 cz_get_sclk_level(hwmgr,
1271 cz_hwmgr->sclk_dpm.soft_max_clk,
1272 PPSMC_MSG_SetSclkSoftMax));
1273
1274 return 0;
1275 }
1276
1277 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1278 {
1279 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1280
1281 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1282 cz_hwmgr->sclk_dpm.soft_max_clk) {
1283 cz_hwmgr->sclk_dpm.soft_max_clk =
1284 cz_hwmgr->sclk_dpm.soft_min_clk;
1285
1286 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1287 PPSMC_MSG_SetSclkSoftMax,
1288 cz_get_sclk_level(hwmgr,
1289 cz_hwmgr->sclk_dpm.soft_max_clk,
1290 PPSMC_MSG_SetSclkSoftMax));
1291 }
1292
1293 return 0;
1294 }
1295
1296 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1297 enum amd_dpm_forced_level level)
1298 {
1299 int ret = 0;
1300
1301 switch (level) {
1302 case AMD_DPM_FORCED_LEVEL_HIGH:
1303 ret = cz_phm_force_dpm_highest(hwmgr);
1304 if (ret)
1305 return ret;
1306 break;
1307 case AMD_DPM_FORCED_LEVEL_LOW:
1308 ret = cz_phm_force_dpm_lowest(hwmgr);
1309 if (ret)
1310 return ret;
1311 break;
1312 case AMD_DPM_FORCED_LEVEL_AUTO:
1313 ret = cz_phm_unforce_dpm_levels(hwmgr);
1314 if (ret)
1315 return ret;
1316 break;
1317 default:
1318 break;
1319 }
1320
1321 hwmgr->dpm_level = level;
1322
1323 return ret;
1324 }
1325
1326 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1327 {
1328 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1329 PHM_PlatformCaps_UVDPowerGating))
1330 return smum_send_msg_to_smc(hwmgr->smumgr,
1331 PPSMC_MSG_UVDPowerOFF);
1332 return 0;
1333 }
1334
1335 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1336 {
1337 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1338 PHM_PlatformCaps_UVDPowerGating)) {
1339 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1340 PHM_PlatformCaps_UVDDynamicPowerGating)) {
1341 return smum_send_msg_to_smc_with_parameter(
1342 hwmgr->smumgr,
1343 PPSMC_MSG_UVDPowerON, 1);
1344 } else {
1345 return smum_send_msg_to_smc_with_parameter(
1346 hwmgr->smumgr,
1347 PPSMC_MSG_UVDPowerON, 0);
1348 }
1349 }
1350
1351 return 0;
1352 }
1353
1354 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1355 {
1356 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1357 struct phm_uvd_clock_voltage_dependency_table *ptable =
1358 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1359
1360 if (!bgate) {
1361 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1362 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1363 PHM_PlatformCaps_StablePState)) {
1364 cz_hwmgr->uvd_dpm.hard_min_clk =
1365 ptable->entries[ptable->count - 1].vclk;
1366
1367 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1368 PPSMC_MSG_SetUvdHardMin,
1369 cz_get_uvd_level(hwmgr,
1370 cz_hwmgr->uvd_dpm.hard_min_clk,
1371 PPSMC_MSG_SetUvdHardMin));
1372
1373 cz_enable_disable_uvd_dpm(hwmgr, true);
1374 } else
1375 cz_enable_disable_uvd_dpm(hwmgr, true);
1376 } else
1377 cz_enable_disable_uvd_dpm(hwmgr, false);
1378
1379 return 0;
1380 }
1381
1382 int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1383 {
1384 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1385 struct phm_vce_clock_voltage_dependency_table *ptable =
1386 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1387
1388 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1390 PHM_PlatformCaps_StablePState)) {
1391 cz_hwmgr->vce_dpm.hard_min_clk =
1392 ptable->entries[ptable->count - 1].ecclk;
1393
1394 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1395 PPSMC_MSG_SetEclkHardMin,
1396 cz_get_eclk_level(hwmgr,
1397 cz_hwmgr->vce_dpm.hard_min_clk,
1398 PPSMC_MSG_SetEclkHardMin));
1399 } else {
1400 /*EPR# 419220 -HW limitation to to */
1401 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1402 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1403 PPSMC_MSG_SetEclkHardMin,
1404 cz_get_eclk_level(hwmgr,
1405 cz_hwmgr->vce_dpm.hard_min_clk,
1406 PPSMC_MSG_SetEclkHardMin));
1407
1408 }
1409 return 0;
1410 }
1411
1412 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1413 {
1414 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1415 PHM_PlatformCaps_VCEPowerGating))
1416 return smum_send_msg_to_smc(hwmgr->smumgr,
1417 PPSMC_MSG_VCEPowerOFF);
1418 return 0;
1419 }
1420
1421 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1422 {
1423 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1424 PHM_PlatformCaps_VCEPowerGating))
1425 return smum_send_msg_to_smc(hwmgr->smumgr,
1426 PPSMC_MSG_VCEPowerON);
1427 return 0;
1428 }
1429
1430 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1431 {
1432 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1433
1434 return cz_hwmgr->sys_info.bootup_uma_clock;
1435 }
1436
1437 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1438 {
1439 struct pp_power_state *ps;
1440 struct cz_power_state *cz_ps;
1441
1442 if (hwmgr == NULL)
1443 return -EINVAL;
1444
1445 ps = hwmgr->request_ps;
1446
1447 if (ps == NULL)
1448 return -EINVAL;
1449
1450 cz_ps = cast_PhwCzPowerState(&ps->hardware);
1451
1452 if (low)
1453 return cz_ps->levels[0].engineClock;
1454 else
1455 return cz_ps->levels[cz_ps->level-1].engineClock;
1456 }
1457
1458 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1459 struct pp_hw_power_state *hw_ps)
1460 {
1461 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1462 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1463
1464 cz_ps->level = 1;
1465 cz_ps->nbps_flags = 0;
1466 cz_ps->bapm_flags = 0;
1467 cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1468
1469 return 0;
1470 }
1471
1472 static int cz_dpm_get_pp_table_entry_callback(
1473 struct pp_hwmgr *hwmgr,
1474 struct pp_hw_power_state *hw_ps,
1475 unsigned int index,
1476 const void *clock_info)
1477 {
1478 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1479
1480 const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1481
1482 struct phm_clock_voltage_dependency_table *table =
1483 hwmgr->dyn_state.vddc_dependency_on_sclk;
1484 uint8_t clock_info_index = cz_clock_info->index;
1485
1486 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1487 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1488
1489 cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1490 cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1491
1492 cz_ps->level = index + 1;
1493
1494 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1495 cz_ps->levels[index].dsDividerIndex = 5;
1496 cz_ps->levels[index].ssDividerIndex = 5;
1497 }
1498
1499 return 0;
1500 }
1501
1502 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1503 {
1504 int result;
1505 unsigned long ret = 0;
1506
1507 result = pp_tables_get_num_of_entries(hwmgr, &ret);
1508
1509 return result ? 0 : ret;
1510 }
1511
1512 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1513 unsigned long entry, struct pp_power_state *ps)
1514 {
1515 int result;
1516 struct cz_power_state *cz_ps;
1517
1518 ps->hardware.magic = PhwCz_Magic;
1519
1520 cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1521
1522 result = pp_tables_get_entry(hwmgr, entry, ps,
1523 cz_dpm_get_pp_table_entry_callback);
1524
1525 cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1526 cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1527
1528 return result;
1529 }
1530
1531 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1532 {
1533 return sizeof(struct cz_power_state);
1534 }
1535
1536 static void
1537 cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
1538 {
1539 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1540
1541 struct phm_clock_voltage_dependency_table *table =
1542 hwmgr->dyn_state.vddc_dependency_on_sclk;
1543
1544 struct phm_vce_clock_voltage_dependency_table *vce_table =
1545 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1546
1547 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1548 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1549
1550 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1551 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1552 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1553 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1554 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1555 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1556
1557 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1558 uint16_t vddnb, vddgfx;
1559 int result;
1560
1561 if (sclk_index >= NUM_SCLK_LEVELS) {
1562 seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
1563 } else {
1564 sclk = table->entries[sclk_index].clk;
1565 seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
1566 }
1567
1568 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1569 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1570 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1571 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1572 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1573 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1574 seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
1575
1576 seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
1577 if (!cz_hwmgr->uvd_power_gated) {
1578 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1579 seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
1580 } else {
1581 vclk = uvd_table->entries[uvd_index].vclk;
1582 dclk = uvd_table->entries[uvd_index].dclk;
1583 seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
1584 }
1585 }
1586
1587 seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
1588 if (!cz_hwmgr->vce_power_gated) {
1589 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1590 seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
1591 } else {
1592 ecclk = vce_table->entries[vce_index].ecclk;
1593 seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
1594 }
1595 }
1596
1597 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1598 if (0 == result) {
1599 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1600 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1601 } else {
1602 activity_percent = 50;
1603 }
1604
1605 seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
1606 }
1607
1608 static void cz_hw_print_display_cfg(
1609 const struct cc6_settings *cc6_settings)
1610 {
1611 PP_DBG_LOG("New Display Configuration:\n");
1612
1613 PP_DBG_LOG(" cpu_cc6_disable: %d\n",
1614 cc6_settings->cpu_cc6_disable);
1615 PP_DBG_LOG(" cpu_pstate_disable: %d\n",
1616 cc6_settings->cpu_pstate_disable);
1617 PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
1618 cc6_settings->nb_pstate_switch_disable);
1619 PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
1620 cc6_settings->cpu_pstate_separation_time);
1621 }
1622
1623 static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1624 {
1625 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1626 uint32_t data = 0;
1627
1628 if (hw_data->cc6_settings.cc6_setting_changed == true) {
1629
1630 hw_data->cc6_settings.cc6_setting_changed = false;
1631
1632 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1633
1634 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1635 & PWRMGT_SEPARATION_TIME_MASK)
1636 << PWRMGT_SEPARATION_TIME_SHIFT;
1637
1638 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1639 << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1640
1641 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1642 << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1643
1644 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1645 data);
1646
1647 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1648 PPSMC_MSG_SetDisplaySizePowerParams,
1649 data);
1650 }
1651
1652 return 0;
1653 }
1654
1655
1656 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1657 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1658 {
1659 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1660
1661 if (separation_time !=
1662 hw_data->cc6_settings.cpu_pstate_separation_time
1663 || cc6_disable !=
1664 hw_data->cc6_settings.cpu_cc6_disable
1665 || pstate_disable !=
1666 hw_data->cc6_settings.cpu_pstate_disable
1667 || pstate_switch_disable !=
1668 hw_data->cc6_settings.nb_pstate_switch_disable) {
1669
1670 hw_data->cc6_settings.cc6_setting_changed = true;
1671
1672 hw_data->cc6_settings.cpu_pstate_separation_time =
1673 separation_time;
1674 hw_data->cc6_settings.cpu_cc6_disable =
1675 cc6_disable;
1676 hw_data->cc6_settings.cpu_pstate_disable =
1677 pstate_disable;
1678 hw_data->cc6_settings.nb_pstate_switch_disable =
1679 pstate_switch_disable;
1680
1681 }
1682
1683 return 0;
1684 }
1685
1686 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1687 struct amd_pp_simple_clock_info *info)
1688 {
1689 uint32_t i;
1690 const struct phm_clock_voltage_dependency_table *table =
1691 hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1692 const struct phm_clock_and_voltage_limits *limits =
1693 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1694
1695 info->engine_max_clock = limits->sclk;
1696 info->memory_max_clock = limits->mclk;
1697
1698 for (i = table->count - 1; i > 0; i--) {
1699 if (limits->vddc >= table->entries[i].v) {
1700 info->level = table->entries[i].clk;
1701 return 0;
1702 }
1703 }
1704 return -EINVAL;
1705 }
1706
1707 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1708 enum pp_clock_type type, int level)
1709 {
1710 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1711 return -EINVAL;
1712
1713 switch (type) {
1714 case PP_SCLK:
1715 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1716 PPSMC_MSG_SetSclkSoftMin,
1717 (1 << level));
1718 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1719 PPSMC_MSG_SetSclkSoftMax,
1720 (1 << level));
1721 break;
1722 default:
1723 break;
1724 }
1725
1726 return 0;
1727 }
1728
1729 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1730 enum pp_clock_type type, char *buf)
1731 {
1732 struct phm_clock_voltage_dependency_table *sclk_table =
1733 hwmgr->dyn_state.vddc_dependency_on_sclk;
1734 int i, now, size = 0;
1735
1736 switch (type) {
1737 case PP_SCLK:
1738 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1739 CGS_IND_REG__SMC,
1740 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1741 TARGET_AND_CURRENT_PROFILE_INDEX,
1742 CURR_SCLK_INDEX);
1743
1744 for (i = 0; i < sclk_table->count; i++)
1745 size += sprintf(buf + size, "%d: %uMhz %s\n",
1746 i, sclk_table->entries[i].clk / 100,
1747 (i == now) ? "*" : "");
1748 break;
1749 default:
1750 break;
1751 }
1752 return size;
1753 }
1754
1755 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1756 PHM_PerformanceLevelDesignation designation, uint32_t index,
1757 PHM_PerformanceLevel *level)
1758 {
1759 const struct cz_power_state *ps;
1760 struct cz_hwmgr *data;
1761 uint32_t level_index;
1762 uint32_t i;
1763
1764 if (level == NULL || hwmgr == NULL || state == NULL)
1765 return -EINVAL;
1766
1767 data = (struct cz_hwmgr *)(hwmgr->backend);
1768 ps = cast_const_PhwCzPowerState(state);
1769
1770 level_index = index > ps->level - 1 ? ps->level - 1 : index;
1771
1772 level->coreClock = ps->levels[level_index].engineClock;
1773
1774 if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1775 for (i = 1; i < ps->level; i++) {
1776 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1777 level->coreClock = ps->levels[i].engineClock;
1778 break;
1779 }
1780 }
1781 }
1782
1783 if (level_index == 0)
1784 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1785 else
1786 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1787
1788 level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1789 level->nonLocalMemoryFreq = 0;
1790 level->nonLocalMemoryWidth = 0;
1791
1792 return 0;
1793 }
1794
1795 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1796 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1797 {
1798 const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1799
1800 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1801 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1802
1803 return 0;
1804 }
1805
1806 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1807 struct amd_pp_clocks *clocks)
1808 {
1809 struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1810 int i;
1811 struct phm_clock_voltage_dependency_table *table;
1812
1813 clocks->count = cz_get_max_sclk_level(hwmgr);
1814 switch (type) {
1815 case amd_pp_disp_clock:
1816 for (i = 0; i < clocks->count; i++)
1817 clocks->clock[i] = data->sys_info.display_clock[i];
1818 break;
1819 case amd_pp_sys_clock:
1820 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1821 for (i = 0; i < clocks->count; i++)
1822 clocks->clock[i] = table->entries[i].clk;
1823 break;
1824 case amd_pp_mem_clock:
1825 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1826 for (i = 0; i < clocks->count; i++)
1827 clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1828 break;
1829 default:
1830 return -1;
1831 }
1832
1833 return 0;
1834 }
1835
1836 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1837 {
1838 struct phm_clock_voltage_dependency_table *table =
1839 hwmgr->dyn_state.vddc_dependency_on_sclk;
1840 unsigned long level;
1841 const struct phm_clock_and_voltage_limits *limits =
1842 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1843
1844 if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1845 return -EINVAL;
1846
1847 level = cz_get_max_sclk_level(hwmgr) - 1;
1848
1849 if (level < table->count)
1850 clocks->engine_max_clock = table->entries[level].clk;
1851 else
1852 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1853
1854 clocks->memory_max_clock = limits->mclk;
1855
1856 return 0;
1857 }
1858
1859 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1860 .backend_init = cz_hwmgr_backend_init,
1861 .backend_fini = cz_hwmgr_backend_fini,
1862 .asic_setup = NULL,
1863 .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1864 .force_dpm_level = cz_dpm_force_dpm_level,
1865 .get_power_state_size = cz_get_power_state_size,
1866 .powerdown_uvd = cz_dpm_powerdown_uvd,
1867 .powergate_uvd = cz_dpm_powergate_uvd,
1868 .powergate_vce = cz_dpm_powergate_vce,
1869 .get_mclk = cz_dpm_get_mclk,
1870 .get_sclk = cz_dpm_get_sclk,
1871 .patch_boot_state = cz_dpm_patch_boot_state,
1872 .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1873 .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1874 .print_current_perforce_level = cz_print_current_perforce_level,
1875 .set_cpu_power_state = cz_set_cpu_power_state,
1876 .store_cc6_data = cz_store_cc6_data,
1877 .force_clock_level = cz_force_clock_level,
1878 .print_clock_levels = cz_print_clock_levels,
1879 .get_dal_power_level = cz_get_dal_power_level,
1880 .get_performance_level = cz_get_performance_level,
1881 .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1882 .get_clock_by_type = cz_get_clock_by_type,
1883 .get_max_high_clocks = cz_get_max_high_clocks,
1884 };
1885
1886 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1887 {
1888 struct cz_hwmgr *cz_hwmgr;
1889 int ret = 0;
1890
1891 cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1892 if (cz_hwmgr == NULL)
1893 return -ENOMEM;
1894
1895 hwmgr->backend = cz_hwmgr;
1896 hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1897 hwmgr->pptable_func = &pptable_funcs;
1898 return ret;
1899 }
Linux kernel - Deliverables
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