drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "hwmgr.h"
  25 #include "smumgr.h"
  26 #include "fiji_hwmgr.h"
  27 #include "fiji_powertune.h"
  28 #include "fiji_smumgr.h"
  29 #include "smu73_discrete.h"
  30 #include "pp_debug.h"
  31
  32 #define VOLTAGE_SCALE  4
  33 #define POWERTUNE_DEFAULT_SET_MAX    1
  34
  35 const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
  36                 /*sviLoadLIneEn,  SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
  37                 {1,               0xF,             0xFD,
  38                 /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
  39                 0x19,        5,               45}
  40 };
  41
  42 void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
  43 {
  44         struct fiji_hwmgr *fiji_hwmgr = (struct fiji_hwmgr *)(hwmgr->backend);
  45         struct  phm_ppt_v1_information *table_info =
  46                         (struct  phm_ppt_v1_information *)(hwmgr->pptable);
  47         uint32_t tmp = 0;
  48
  49         if(table_info &&
  50                         table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
  51                         table_info->cac_dtp_table->usPowerTuneDataSetID)
  52                 fiji_hwmgr->power_tune_defaults =
  53                                 &fiji_power_tune_data_set_array
  54                                 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
  55         else
  56                 fiji_hwmgr->power_tune_defaults = &fiji_power_tune_data_set_array[0];
  57
  58         /* Assume disabled */
  59         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  60                         PHM_PlatformCaps_PowerContainment);
  61         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  62                         PHM_PlatformCaps_CAC);
  63         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  64                         PHM_PlatformCaps_SQRamping);
  65         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  66                         PHM_PlatformCaps_DBRamping);
  67         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  68                         PHM_PlatformCaps_TDRamping);
  69         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
  70                         PHM_PlatformCaps_TCPRamping);
  71
  72         fiji_hwmgr->dte_tj_offset = tmp;
  73
  74         if (!tmp) {
  75                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
  76                                 PHM_PlatformCaps_CAC);
  77
  78                 fiji_hwmgr->fast_watermark_threshold = 100;
  79
  80                 if (hwmgr->powercontainment_enabled) {
  81                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
  82                                     PHM_PlatformCaps_PowerContainment);
  83                         tmp = 1;
  84                         fiji_hwmgr->enable_dte_feature = tmp ? false : true;
  85                         fiji_hwmgr->enable_tdc_limit_feature = tmp ? true : false;
  86                         fiji_hwmgr->enable_pkg_pwr_tracking_feature = tmp ? true : false;
  87                 }
  88         }
  89 }
  90
  91 /* PPGen has the gain setting generated in x * 100 unit
  92  * This function is to convert the unit to x * 4096(0x1000) unit.
  93  *  This is the unit expected by SMC firmware
  94  */
  95 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
  96 {
  97         uint32_t tmp;
  98         tmp = raw_setting * 4096 / 100;
  99         return (uint16_t)tmp;
 100 }
 101
 102 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
 103 {
 104         switch (line) {
 105         case Fiji_I2CLineID_DDC1 :
 106                 *scl = Fiji_I2C_DDC1CLK;
 107                 *sda = Fiji_I2C_DDC1DATA;
 108                 break;
 109         case Fiji_I2CLineID_DDC2 :
 110                 *scl = Fiji_I2C_DDC2CLK;
 111                 *sda = Fiji_I2C_DDC2DATA;
 112                 break;
 113         case Fiji_I2CLineID_DDC3 :
 114                 *scl = Fiji_I2C_DDC3CLK;
 115                 *sda = Fiji_I2C_DDC3DATA;
 116                 break;
 117         case Fiji_I2CLineID_DDC4 :
 118                 *scl = Fiji_I2C_DDC4CLK;
 119                 *sda = Fiji_I2C_DDC4DATA;
 120                 break;
 121         case Fiji_I2CLineID_DDC5 :
 122                 *scl = Fiji_I2C_DDC5CLK;
 123                 *sda = Fiji_I2C_DDC5DATA;
 124                 break;
 125         case Fiji_I2CLineID_DDC6 :
 126                 *scl = Fiji_I2C_DDC6CLK;
 127                 *sda = Fiji_I2C_DDC6DATA;
 128                 break;
 129         case Fiji_I2CLineID_SCLSDA :
 130                 *scl = Fiji_I2C_SCL;
 131                 *sda = Fiji_I2C_SDA;
 132                 break;
 133         case Fiji_I2CLineID_DDCVGA :
 134                 *scl = Fiji_I2C_DDCVGACLK;
 135                 *sda = Fiji_I2C_DDCVGADATA;
 136                 break;
 137         default:
 138                 *scl = 0;
 139                 *sda = 0;
 140                 break;
 141         }
 142 }
 143
 144 int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 145 {
 146         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 147         const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
 148         SMU73_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
 149         struct phm_ppt_v1_information *table_info =
 150                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 151         struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
 152         struct pp_advance_fan_control_parameters *fan_table=
 153                         &hwmgr->thermal_controller.advanceFanControlParameters;
 154         uint8_t uc_scl, uc_sda;
 155
 156         /* TDP number of fraction bits are changed from 8 to 7 for Fiji
 157          * as requested by SMC team
 158          */
 159         dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
 160                         (uint16_t)(cac_dtp_table->usTDP * 128));
 161         dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
 162                         (uint16_t)(cac_dtp_table->usTDP * 128));
 163
 164         PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
 165                         "Target Operating Temp is out of Range!",);
 166
 167         dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
 168         dpm_table->GpuTjHyst = 8;
 169
 170         dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
 171
 172         /* The following are for new Fiji Multi-input fan/thermal control */
 173         dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
 174                         cac_dtp_table->usTargetOperatingTemp * 256);
 175         dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
 176                         cac_dtp_table->usTemperatureLimitHotspot * 256);
 177         dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
 178                         cac_dtp_table->usTemperatureLimitLiquid1 * 256);
 179         dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
 180                         cac_dtp_table->usTemperatureLimitLiquid2 * 256);
 181         dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
 182                         cac_dtp_table->usTemperatureLimitVrVddc * 256);
 183         dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
 184                         cac_dtp_table->usTemperatureLimitVrMvdd * 256);
 185         dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
 186                         cac_dtp_table->usTemperatureLimitPlx * 256);
 187
 188         dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
 189                         scale_fan_gain_settings(fan_table->usFanGainEdge));
 190         dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
 191                         scale_fan_gain_settings(fan_table->usFanGainHotspot));
 192         dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
 193                         scale_fan_gain_settings(fan_table->usFanGainLiquid));
 194         dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
 195                         scale_fan_gain_settings(fan_table->usFanGainVrVddc));
 196         dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
 197                         scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
 198         dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
 199                         scale_fan_gain_settings(fan_table->usFanGainPlx));
 200         dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
 201                         scale_fan_gain_settings(fan_table->usFanGainHbm));
 202
 203         dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
 204         dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
 205         dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
 206         dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
 207
 208         get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
 209         dpm_table->Liquid_I2C_LineSCL = uc_scl;
 210         dpm_table->Liquid_I2C_LineSDA = uc_sda;
 211
 212         get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
 213         dpm_table->Vr_I2C_LineSCL = uc_scl;
 214         dpm_table->Vr_I2C_LineSDA = uc_sda;
 215
 216         get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
 217         dpm_table->Plx_I2C_LineSCL = uc_scl;
 218         dpm_table->Plx_I2C_LineSDA = uc_sda;
 219
 220         return 0;
 221 }
 222
 223 static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 224 {
 225     struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 226     const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
 227
 228     data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
 229     data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
 230     data->power_tune_table.SviLoadLineTrimVddC = 3;
 231     data->power_tune_table.SviLoadLineOffsetVddC = 0;
 232
 233     return 0;
 234 }
 235
 236 static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 237 {
 238         uint16_t tdc_limit;
 239         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 240         struct phm_ppt_v1_information *table_info =
 241                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 242         const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
 243
 244         /* TDC number of fraction bits are changed from 8 to 7
 245          * for Fiji as requested by SMC team
 246          */
 247         tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
 248         data->power_tune_table.TDC_VDDC_PkgLimit =
 249                         CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
 250         data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 251                         defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
 252         data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
 253
 254         return 0;
 255 }
 256
 257 static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 258 {
 259         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 260         const struct fiji_pt_defaults *defaults = data->power_tune_defaults;
 261         uint32_t temp;
 262
 263         if (fiji_read_smc_sram_dword(hwmgr->smumgr,
 264                         fuse_table_offset +
 265                         offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
 266                         (uint32_t *)&temp, data->sram_end))
 267                 PP_ASSERT_WITH_CODE(false,
 268                                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
 269                                 return -EINVAL);
 270         else {
 271                 data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
 272                 data->power_tune_table.LPMLTemperatureMin =
 273                                 (uint8_t)((temp >> 16) & 0xff);
 274                 data->power_tune_table.LPMLTemperatureMax =
 275                                 (uint8_t)((temp >> 8) & 0xff);
 276                 data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
 277         }
 278         return 0;
 279 }
 280
 281 static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 282 {
 283         int i;
 284         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 285
 286         /* Currently not used. Set all to zero. */
 287         for (i = 0; i < 16; i++)
 288                 data->power_tune_table.LPMLTemperatureScaler[i] = 0;
 289
 290         return 0;
 291 }
 292
 293 static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
 294 {
 295         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 296
 297         if( (hwmgr->thermal_controller.advanceFanControlParameters.
 298                         usFanOutputSensitivity & (1 << 15)) ||
 299                         0 == hwmgr->thermal_controller.advanceFanControlParameters.
 300                         usFanOutputSensitivity )
 301                 hwmgr->thermal_controller.advanceFanControlParameters.
 302                 usFanOutputSensitivity = hwmgr->thermal_controller.
 303                         advanceFanControlParameters.usDefaultFanOutputSensitivity;
 304
 305         data->power_tune_table.FuzzyFan_PwmSetDelta =
 306                         PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
 307                                         advanceFanControlParameters.usFanOutputSensitivity);
 308         return 0;
 309 }
 310
 311 static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 312 {
 313         int i;
 314         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 315
 316         /* Currently not used. Set all to zero. */
 317         for (i = 0; i < 16; i++)
 318                 data->power_tune_table.GnbLPML[i] = 0;
 319
 320         return 0;
 321 }
 322
 323 static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
 324 {
 325  /*   int  i, min, max;
 326     struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 327     uint8_t * pHiVID = data->power_tune_table.BapmVddCVidHiSidd;
 328     uint8_t * pLoVID = data->power_tune_table.BapmVddCVidLoSidd;
 329
 330     min = max = pHiVID[0];
 331     for (i = 0; i < 8; i++) {
 332         if (0 != pHiVID[i]) {
 333             if (min > pHiVID[i])
 334                 min = pHiVID[i];
 335             if (max < pHiVID[i])
 336                 max = pHiVID[i];
 337         }
 338
 339         if (0 != pLoVID[i]) {
 340             if (min > pLoVID[i])
 341                 min = pLoVID[i];
 342             if (max < pLoVID[i])
 343                 max = pLoVID[i];
 344         }
 345     }
 346
 347     PP_ASSERT_WITH_CODE((0 != min) && (0 != max), "BapmVddcVidSidd table does not exist!", return int_Failed);
 348     data->power_tune_table.GnbLPMLMaxVid = (uint8_t)max;
 349     data->power_tune_table.GnbLPMLMinVid = (uint8_t)min;
 350 */
 351     return 0;
 352 }
 353
 354 static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 355 {
 356         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 357         struct phm_ppt_v1_information *table_info =
 358                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 359         uint16_t HiSidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
 360         uint16_t LoSidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
 361         struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
 362
 363         HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
 364         LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
 365
 366         data->power_tune_table.BapmVddCBaseLeakageHiSidd =
 367                         CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
 368         data->power_tune_table.BapmVddCBaseLeakageLoSidd =
 369                         CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
 370
 371         return 0;
 372 }
 373
 374 int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 375 {
 376         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 377         uint32_t pm_fuse_table_offset;
 378
 379         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 380                         PHM_PlatformCaps_PowerContainment)) {
 381                 if (fiji_read_smc_sram_dword(hwmgr->smumgr,
 382                                 SMU7_FIRMWARE_HEADER_LOCATION +
 383                                 offsetof(SMU73_Firmware_Header, PmFuseTable),
 384                                 &pm_fuse_table_offset, data->sram_end))
 385                         PP_ASSERT_WITH_CODE(false,
 386                                         "Attempt to get pm_fuse_table_offset Failed!",
 387                                         return -EINVAL);
 388
 389                 /* DW6 */
 390                 if (fiji_populate_svi_load_line(hwmgr))
 391                         PP_ASSERT_WITH_CODE(false,
 392                                         "Attempt to populate SviLoadLine Failed!",
 393                                         return -EINVAL);
 394                 /* DW7 */
 395                 if (fiji_populate_tdc_limit(hwmgr))
 396                         PP_ASSERT_WITH_CODE(false,
 397                                         "Attempt to populate TDCLimit Failed!", return -EINVAL);
 398                 /* DW8 */
 399                 if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
 400                         PP_ASSERT_WITH_CODE(false,
 401                                         "Attempt to populate TdcWaterfallCtl, "
 402                                         "LPMLTemperature Min and Max Failed!",
 403                                         return -EINVAL);
 404
 405                 /* DW9-DW12 */
 406                 if (0 != fiji_populate_temperature_scaler(hwmgr))
 407                         PP_ASSERT_WITH_CODE(false,
 408                                         "Attempt to populate LPMLTemperatureScaler Failed!",
 409                                         return -EINVAL);
 410
 411                 /* DW13-DW14 */
 412                 if(fiji_populate_fuzzy_fan(hwmgr))
 413                         PP_ASSERT_WITH_CODE(false,
 414                                         "Attempt to populate Fuzzy Fan Control parameters Failed!",
 415                                         return -EINVAL);
 416
 417                 /* DW15-DW18 */
 418                 if (fiji_populate_gnb_lpml(hwmgr))
 419                         PP_ASSERT_WITH_CODE(false,
 420                                         "Attempt to populate GnbLPML Failed!",
 421                                         return -EINVAL);
 422
 423                 /* DW19 */
 424                 if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
 425                         PP_ASSERT_WITH_CODE(false,
 426                                         "Attempt to populate GnbLPML Min and Max Vid Failed!",
 427                                         return -EINVAL);
 428
 429                 /* DW20 */
 430                 if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
 431                         PP_ASSERT_WITH_CODE(false,
 432                                         "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
 433                                         "Sidd Failed!", return -EINVAL);
 434
 435                 if (fiji_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
 436                                 (uint8_t *)&data->power_tune_table,
 437                                 sizeof(struct SMU73_Discrete_PmFuses), data->sram_end))
 438                         PP_ASSERT_WITH_CODE(false,
 439                                         "Attempt to download PmFuseTable Failed!",
 440                                         return -EINVAL);
 441         }
 442         return 0;
 443 }
 444
 445 int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr)
 446 {
 447         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 448         int result = 0;
 449
 450         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 451                         PHM_PlatformCaps_CAC)) {
 452                 int smc_result;
 453                 smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 454                                 (uint16_t)(PPSMC_MSG_EnableCac));
 455                 PP_ASSERT_WITH_CODE((0 == smc_result),
 456                                 "Failed to enable CAC in SMC.", result = -1);
 457
 458         data->cac_enabled = (0 == smc_result) ? true : false;
 459         }
 460         return result;
 461 }
 462
 463 int fiji_disable_smc_cac(struct pp_hwmgr *hwmgr)
 464 {
 465         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 466         int result = 0;
 467
 468         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 469                         PHM_PlatformCaps_CAC) && data->cac_enabled) {
 470                 int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 471                                 (uint16_t)(PPSMC_MSG_DisableCac));
 472                 PP_ASSERT_WITH_CODE((smc_result == 0),
 473                                 "Failed to disable CAC in SMC.", result = -1);
 474
 475                 data->cac_enabled = false;
 476         }
 477         return result;
 478 }
 479
 480 int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
 481 {
 482         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 483
 484         if(data->power_containment_features &
 485                         POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 486                 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 487                                 PPSMC_MSG_PkgPwrSetLimit, n);
 488         return 0;
 489 }
 490
 491 static int fiji_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
 492 {
 493         return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
 494                         PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
 495 }
 496
 497 int fiji_enable_power_containment(struct pp_hwmgr *hwmgr)
 498 {
 499         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 500         struct phm_ppt_v1_information *table_info =
 501                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 502         int smc_result;
 503         int result = 0;
 504
 505         data->power_containment_features = 0;
 506         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 507                         PHM_PlatformCaps_PowerContainment)) {
 508                 if (data->enable_dte_feature) {
 509                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 510                                         (uint16_t)(PPSMC_MSG_EnableDTE));
 511                         PP_ASSERT_WITH_CODE((0 == smc_result),
 512                                         "Failed to enable DTE in SMC.", result = -1;);
 513                         if (0 == smc_result)
 514                                 data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
 515                 }
 516
 517                 if (data->enable_tdc_limit_feature) {
 518                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 519                                         (uint16_t)(PPSMC_MSG_TDCLimitEnable));
 520                         PP_ASSERT_WITH_CODE((0 == smc_result),
 521                                         "Failed to enable TDCLimit in SMC.", result = -1;);
 522                         if (0 == smc_result)
 523                                 data->power_containment_features |=
 524                                                 POWERCONTAINMENT_FEATURE_TDCLimit;
 525                 }
 526
 527                 if (data->enable_pkg_pwr_tracking_feature) {
 528                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 529                                         (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
 530                         PP_ASSERT_WITH_CODE((0 == smc_result),
 531                                         "Failed to enable PkgPwrTracking in SMC.", result = -1;);
 532                         if (0 == smc_result) {
 533                                 struct phm_cac_tdp_table *cac_table =
 534                                                 table_info->cac_dtp_table;
 535                                 uint32_t default_limit =
 536                                         (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
 537
 538                                 data->power_containment_features |=
 539                                                 POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 540
 541                                 if (fiji_set_power_limit(hwmgr, default_limit))
 542                                         printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
 543                         }
 544                 }
 545         }
 546         return result;
 547 }
 548
 549 int fiji_disable_power_containment(struct pp_hwmgr *hwmgr)
 550 {
 551         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 552         int result = 0;
 553
 554         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 555                         PHM_PlatformCaps_PowerContainment) &&
 556                         data->power_containment_features) {
 557                 int smc_result;
 558
 559                 if (data->power_containment_features &
 560                                 POWERCONTAINMENT_FEATURE_TDCLimit) {
 561                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 562                                         (uint16_t)(PPSMC_MSG_TDCLimitDisable));
 563                         PP_ASSERT_WITH_CODE((smc_result == 0),
 564                                         "Failed to disable TDCLimit in SMC.",
 565                                         result = smc_result);
 566                 }
 567
 568                 if (data->power_containment_features &
 569                                 POWERCONTAINMENT_FEATURE_DTE) {
 570                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 571                                         (uint16_t)(PPSMC_MSG_DisableDTE));
 572                         PP_ASSERT_WITH_CODE((smc_result == 0),
 573                                         "Failed to disable DTE in SMC.",
 574                                         result = smc_result);
 575                 }
 576
 577                 if (data->power_containment_features &
 578                                 POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
 579                         smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
 580                                         (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
 581                         PP_ASSERT_WITH_CODE((smc_result == 0),
 582                                         "Failed to disable PkgPwrTracking in SMC.",
 583                                         result = smc_result);
 584                 }
 585                 data->power_containment_features = 0;
 586         }
 587
 588         return result;
 589 }
 590
 591 int fiji_power_control_set_level(struct pp_hwmgr *hwmgr)
 592 {
 593         struct phm_ppt_v1_information *table_info =
 594                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 595         struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
 596         int adjust_percent, target_tdp;
 597         int result = 0;
 598
 599         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 600                         PHM_PlatformCaps_PowerContainment)) {
 601                 /* adjustment percentage has already been validated */
 602                 adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
 603                                 hwmgr->platform_descriptor.TDPAdjustment :
 604                                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
 605                 /* SMC requested that target_tdp to be 7 bit fraction in DPM table
 606                  * but message to be 8 bit fraction for messages
 607                  */
 608                 target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
 609                 result = fiji_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
 610         }
 611
 612         return result;
 613 }