drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/errno.h>
  24 #include "hwmgr.h"
  25 #include "hardwaremanager.h"
  26 #include "power_state.h"
  27 #include "pp_acpi.h"
  28 #include "amd_acpi.h"
  29 #include "pp_debug.h"
  30
  31 #define PHM_FUNC_CHECK(hw) \
  32         do {                                                    \
  33                 if ((hw) == NULL || (hw)->hwmgr_func == NULL)   \
  34                         return -EINVAL;                         \
  35         } while (0)
  36
  37 void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
  38 {
  39         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
  40         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
  41         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
  42         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
  43         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
  44         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
  45         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
  46         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
  47         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
  48         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
  49
  50         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
  51         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
  52         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
  53
  54         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
  55
  56         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
  57         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
  58
  59         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
  60
  61         if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
  62                 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
  63                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
  64 }
  65
  66 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
  67 {
  68         return hwmgr->block_hw_access;
  69 }
  70
  71 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
  72 {
  73         hwmgr->block_hw_access = block;
  74         return 0;
  75 }
  76
  77 int phm_setup_asic(struct pp_hwmgr *hwmgr)
  78 {
  79         PHM_FUNC_CHECK(hwmgr);
  80
  81         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  82                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  83                 if (NULL != hwmgr->hwmgr_func->asic_setup)
  84                         return hwmgr->hwmgr_func->asic_setup(hwmgr);
  85         } else {
  86                 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
  87                                           NULL, NULL);
  88         }
  89
  90         return 0;
  91 }
  92
  93 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
  94 {
  95         PHM_FUNC_CHECK(hwmgr);
  96
  97         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  98                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  99                 if (NULL != hwmgr->hwmgr_func->power_off_asic)
 100                         return hwmgr->hwmgr_func->power_off_asic(hwmgr);
 101         } else {
 102                 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
 103                                           NULL, NULL);
 104         }
 105
 106         return 0;
 107 }
 108
 109 int phm_set_power_state(struct pp_hwmgr *hwmgr,
 110                     const struct pp_hw_power_state *pcurrent_state,
 111                     const struct pp_hw_power_state *pnew_power_state)
 112 {
 113         struct phm_set_power_state_input states;
 114
 115         PHM_FUNC_CHECK(hwmgr);
 116
 117         states.pcurrent_state = pcurrent_state;
 118         states.pnew_state = pnew_power_state;
 119
 120         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 121                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 122                 if (NULL != hwmgr->hwmgr_func->power_state_set)
 123                         return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
 124         } else {
 125                 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
 126         }
 127
 128         return 0;
 129 }
 130
 131 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 132 {
 133         PHM_FUNC_CHECK(hwmgr);
 134
 135         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 136                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 137                 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
 138                         return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
 139         } else {
 140                 return phm_dispatch_table(hwmgr,
 141                                 &(hwmgr->enable_dynamic_state_management),
 142                                 NULL, NULL);
 143         }
 144         return 0;
 145 }
 146
 147 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
 148 {
 149         PHM_FUNC_CHECK(hwmgr);
 150
 151         if (hwmgr->hwmgr_func->force_dpm_level != NULL)
 152                 return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 153
 154         return 0;
 155 }
 156
 157 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 158                                    struct pp_power_state *adjusted_ps,
 159                              const struct pp_power_state *current_ps)
 160 {
 161         PHM_FUNC_CHECK(hwmgr);
 162
 163         if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
 164                 return hwmgr->hwmgr_func->apply_state_adjust_rules(
 165                                                                         hwmgr,
 166                                                                  adjusted_ps,
 167                                                                  current_ps);
 168         return 0;
 169 }
 170
 171 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 172 {
 173         PHM_FUNC_CHECK(hwmgr);
 174
 175         if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
 176                 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
 177         return 0;
 178 }
 179
 180 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
 181 {
 182         PHM_FUNC_CHECK(hwmgr);
 183
 184         if (hwmgr->hwmgr_func->powergate_uvd != NULL)
 185                 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 186         return 0;
 187 }
 188
 189 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
 190 {
 191         PHM_FUNC_CHECK(hwmgr);
 192
 193         if (hwmgr->hwmgr_func->powergate_vce != NULL)
 194                 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 195         return 0;
 196 }
 197
 198 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 199 {
 200         PHM_FUNC_CHECK(hwmgr);
 201
 202         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 203                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 204                 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
 205                         return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
 206         } else {
 207                 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
 208         }
 209         return 0;
 210 }
 211
 212 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 213 {
 214         PHM_FUNC_CHECK(hwmgr);
 215
 216         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 217                                  PHM_PlatformCaps_TablelessHardwareInterface)) {
 218                 if (NULL != hwmgr->hwmgr_func->display_config_changed)
 219                         hwmgr->hwmgr_func->display_config_changed(hwmgr);
 220         } else
 221                 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
 222         return 0;
 223 }
 224
 225 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 226 {
 227         PHM_FUNC_CHECK(hwmgr);
 228
 229         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 230                                  PHM_PlatformCaps_TablelessHardwareInterface))
 231                 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
 232                         hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
 233
 234         return 0;
 235 }
 236
 237 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 238 {
 239         PHM_FUNC_CHECK(hwmgr);
 240
 241         if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
 242                 return -EINVAL;
 243
 244         return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
 245 }
 246
 247 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
 248 {
 249         PHM_FUNC_CHECK(hwmgr);
 250
 251         if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
 252                 return -EINVAL;
 253
 254         return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
 255 }
 256
 257 /**
 258 * Initializes the thermal controller subsystem.
 259 *
 260 * @param    pHwMgr  the address of the powerplay hardware manager.
 261 * @param    pTemperatureRange the address of the structure holding the temperature range.
 262 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
 263 */
 264 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
 265 {
 266         return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
 267 }
 268
 269
 270 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 271 {
 272         PHM_FUNC_CHECK(hwmgr);
 273
 274         if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
 275                 return -EINVAL;
 276
 277         return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
 278 }
 279
 280
 281 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 282                                  const struct pp_hw_power_state *pstate1,
 283                                  const struct pp_hw_power_state *pstate2,
 284                                  bool *equal)
 285 {
 286         PHM_FUNC_CHECK(hwmgr);
 287
 288         if (hwmgr->hwmgr_func->check_states_equal == NULL)
 289                 return -EINVAL;
 290
 291         return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
 292 }
 293
 294 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 295                     const struct amd_pp_display_configuration *display_config)
 296 {
 297         PHM_FUNC_CHECK(hwmgr);
 298
 299         if (hwmgr->hwmgr_func->store_cc6_data == NULL)
 300                 return -EINVAL;
 301
 302         hwmgr->display_config = *display_config;
 303         /* to do pass other display configuration in furture */
 304
 305         if (hwmgr->hwmgr_func->store_cc6_data)
 306                 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
 307                                 display_config->cpu_pstate_separation_time,
 308                                 display_config->cpu_cc6_disable,
 309                                 display_config->cpu_pstate_disable,
 310                                 display_config->nb_pstate_switch_disable);
 311
 312         return 0;
 313 }
 314
 315 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
 316                 struct amd_pp_simple_clock_info *info)
 317 {
 318         PHM_FUNC_CHECK(hwmgr);
 319
 320         if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
 321                 return -EINVAL;
 322         return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
 323 }
 324
 325 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 326 {
 327         PHM_FUNC_CHECK(hwmgr);
 328
 329         if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
 330                 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
 331
 332         return 0;
 333 }
 334
 335
 336 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 337                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 338                                 PHM_PerformanceLevel *level)
 339 {
 340         PHM_FUNC_CHECK(hwmgr);
 341         if (hwmgr->hwmgr_func->get_performance_level == NULL)
 342                 return -EINVAL;
 343
 344         return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
 345
 346
 347 }
 348
 349
 350 /**
 351 * Gets Clock Info.
 352 *
 353 * @param    pHwMgr  the address of the powerplay hardware manager.
 354 * @param    pPowerState the address of the Power State structure.
 355 * @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
 356 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
 357 */
 358 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
 359                         PHM_PerformanceLevelDesignation designation)
 360 {
 361         int result;
 362         PHM_PerformanceLevel performance_level;
 363
 364         PHM_FUNC_CHECK(hwmgr);
 365
 366         PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
 367         PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
 368
 369         result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
 370
 371         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
 372
 373
 374         pclock_info->min_mem_clk = performance_level.memory_clock;
 375         pclock_info->min_eng_clk = performance_level.coreClock;
 376         pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 377
 378
 379         result = phm_get_performance_level(hwmgr, state, designation,
 380                                         (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
 381
 382         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
 383
 384         pclock_info->max_mem_clk = performance_level.memory_clock;
 385         pclock_info->max_eng_clk = performance_level.coreClock;
 386         pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 387
 388         return 0;
 389 }
 390
 391 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 392 {
 393         PHM_FUNC_CHECK(hwmgr);
 394
 395         if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
 396                 return -EINVAL;
 397
 398         return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
 399
 400 }
 401
 402 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
 403 {
 404         PHM_FUNC_CHECK(hwmgr);
 405
 406         if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
 407                 return -EINVAL;
 408
 409         return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
 410
 411 }
 412
 413 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
 414 {
 415         PHM_FUNC_CHECK(hwmgr);
 416
 417         if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
 418                 return -EINVAL;
 419
 420         return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
 421 }