2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Author: Huang Rui <ray.huang@amd.com>
25 #include <linux/module.h>
26 #include <linux/slab.h>
28 #include "linux/delay.h"
32 #include "iceland_hwmgr.h"
34 #include "processpptables.h"
37 #include "cgs_common.h"
38 #include "pppcielanes.h"
39 #include "iceland_dyn_defaults.h"
41 #include "iceland_smumgr.h"
42 #include "iceland_clockpowergating.h"
43 #include "iceland_thermal.h"
44 #include "iceland_powertune.h"
46 #include "gmc/gmc_8_1_d.h"
47 #include "gmc/gmc_8_1_sh_mask.h"
49 #include "bif/bif_5_0_d.h"
50 #include "bif/bif_5_0_sh_mask.h"
52 #include "smu/smu_7_1_1_d.h"
53 #include "smu/smu_7_1_1_sh_mask.h"
55 #include "cgs_linux.h"
57 #include "amd_pcie_helpers.h"
59 #define MC_CG_ARB_FREQ_F0 0x0a
60 #define MC_CG_ARB_FREQ_F1 0x0b
61 #define MC_CG_ARB_FREQ_F2 0x0c
62 #define MC_CG_ARB_FREQ_F3 0x0d
64 #define MC_CG_SEQ_DRAMCONF_S0 0x05
65 #define MC_CG_SEQ_DRAMCONF_S1 0x06
66 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
67 #define MC_CG_SEQ_YCLK_RESUME 0x0a
69 #define PCIE_BUS_CLK 10000
70 #define TCLK (PCIE_BUS_CLK / 10)
72 #define SMC_RAM_END 0x40000
73 #define SMC_CG_IND_START 0xc0030000
74 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
76 #define VOLTAGE_SCALE 4
77 #define VOLTAGE_VID_OFFSET_SCALE1 625
78 #define VOLTAGE_VID_OFFSET_SCALE2 100
80 const uint32_t iceland_magic
= (uint32_t)(PHM_VIslands_Magic
);
82 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
83 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
84 #define MC_SEQ_MISC0_GDDR5_VALUE 5
86 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
88 DPM_EVENT_SRC_ANALOG
= 0, /* Internal analog trip point */
89 DPM_EVENT_SRC_EXTERNAL
= 1, /* External (GPIO 17) signal */
90 DPM_EVENT_SRC_DIGITAL
= 2, /* Internal digital trip point (DIG_THERM_DPM) */
91 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3, /* Internal analog or external */
92 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
= 4 /* Internal digital or external */
95 static int iceland_read_clock_registers(struct pp_hwmgr
*hwmgr
)
97 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
99 data
->clock_registers
.vCG_SPLL_FUNC_CNTL
=
100 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL
);
101 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
=
102 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_2
);
103 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
=
104 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_3
);
105 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
=
106 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_FUNC_CNTL_4
);
107 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
=
108 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_SPREAD_SPECTRUM
);
109 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
=
110 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_SPLL_SPREAD_SPECTRUM_2
);
111 data
->clock_registers
.vDLL_CNTL
=
112 cgs_read_register(hwmgr
->device
, mmDLL_CNTL
);
113 data
->clock_registers
.vMCLK_PWRMGT_CNTL
=
114 cgs_read_register(hwmgr
->device
, mmMCLK_PWRMGT_CNTL
);
115 data
->clock_registers
.vMPLL_AD_FUNC_CNTL
=
116 cgs_read_register(hwmgr
->device
, mmMPLL_AD_FUNC_CNTL
);
117 data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
=
118 cgs_read_register(hwmgr
->device
, mmMPLL_DQ_FUNC_CNTL
);
119 data
->clock_registers
.vMPLL_FUNC_CNTL
=
120 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL
);
121 data
->clock_registers
.vMPLL_FUNC_CNTL_1
=
122 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL_1
);
123 data
->clock_registers
.vMPLL_FUNC_CNTL_2
=
124 cgs_read_register(hwmgr
->device
, mmMPLL_FUNC_CNTL_2
);
125 data
->clock_registers
.vMPLL_SS1
=
126 cgs_read_register(hwmgr
->device
, mmMPLL_SS1
);
127 data
->clock_registers
.vMPLL_SS2
=
128 cgs_read_register(hwmgr
->device
, mmMPLL_SS2
);
134 * Find out if memory is GDDR5.
136 * @param hwmgr the address of the powerplay hardware manager.
139 int iceland_get_memory_type(struct pp_hwmgr
*hwmgr
)
141 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
144 temp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC0
);
146 data
->is_memory_GDDR5
= (MC_SEQ_MISC0_GDDR5_VALUE
==
147 ((temp
& MC_SEQ_MISC0_GDDR5_MASK
) >>
148 MC_SEQ_MISC0_GDDR5_SHIFT
));
153 int iceland_update_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
155 /* iceland does not have MM hardware blocks */
160 * Enables Dynamic Power Management by SMC
162 * @param hwmgr the address of the powerplay hardware manager.
165 int iceland_enable_acpi_power_management(struct pp_hwmgr
*hwmgr
)
167 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
, STATIC_PM_EN
, 1);
173 * Find the MC microcode version and store it in the HwMgr struct
175 * @param hwmgr the address of the powerplay hardware manager.
178 int iceland_get_mc_microcode_version(struct pp_hwmgr
*hwmgr
)
180 cgs_write_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_INDEX
, 0x9F);
182 hwmgr
->microcode_version_info
.MC
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_IO_DEBUG_DATA
);
187 static int iceland_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
189 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
191 data
->low_sclk_interrupt_threshold
= 0;
197 static int iceland_setup_asic_task(struct pp_hwmgr
*hwmgr
)
199 int tmp_result
, result
= 0;
201 tmp_result
= iceland_read_clock_registers(hwmgr
);
202 PP_ASSERT_WITH_CODE((0 == tmp_result
),
203 "Failed to read clock registers!", result
= tmp_result
);
205 tmp_result
= iceland_get_memory_type(hwmgr
);
206 PP_ASSERT_WITH_CODE((0 == tmp_result
),
207 "Failed to get memory type!", result
= tmp_result
);
209 tmp_result
= iceland_enable_acpi_power_management(hwmgr
);
210 PP_ASSERT_WITH_CODE((0 == tmp_result
),
211 "Failed to enable ACPI power management!", result
= tmp_result
);
213 tmp_result
= iceland_get_mc_microcode_version(hwmgr
);
214 PP_ASSERT_WITH_CODE((0 == tmp_result
),
215 "Failed to get MC microcode version!", result
= tmp_result
);
217 tmp_result
= iceland_init_sclk_threshold(hwmgr
);
218 PP_ASSERT_WITH_CODE((0 == tmp_result
),
219 "Failed to init sclk threshold!", result
= tmp_result
);
224 static bool cf_iceland_voltage_control(struct pp_hwmgr
*hwmgr
)
226 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
228 return ICELAND_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
;
232 * -------------- Voltage Tables ----------------------
233 * If the voltage table would be bigger than what will fit into the
234 * state table on the SMC keep only the higher entries.
237 static void iceland_trim_voltage_table_to_fit_state_table(
238 struct pp_hwmgr
*hwmgr
,
239 uint32_t max_voltage_steps
,
240 pp_atomctrl_voltage_table
*voltage_table
)
242 unsigned int i
, diff
;
244 if (voltage_table
->count
<= max_voltage_steps
) {
248 diff
= voltage_table
->count
- max_voltage_steps
;
250 for (i
= 0; i
< max_voltage_steps
; i
++) {
251 voltage_table
->entries
[i
] = voltage_table
->entries
[i
+ diff
];
254 voltage_table
->count
= max_voltage_steps
;
260 * Enable voltage control
262 * @param hwmgr the address of the powerplay hardware manager.
265 int iceland_enable_voltage_control(struct pp_hwmgr
*hwmgr
)
267 /* enable voltage control */
268 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, 1);
273 static int iceland_get_svi2_voltage_table(struct pp_hwmgr
*hwmgr
,
274 struct phm_clock_voltage_dependency_table
*voltage_dependency_table
,
275 pp_atomctrl_voltage_table
*voltage_table
)
279 PP_ASSERT_WITH_CODE((NULL
!= voltage_table
),
280 "Voltage Dependency Table empty.", return -EINVAL
;);
282 voltage_table
->mask_low
= 0;
283 voltage_table
->phase_delay
= 0;
284 voltage_table
->count
= voltage_dependency_table
->count
;
286 for (i
= 0; i
< voltage_dependency_table
->count
; i
++) {
287 voltage_table
->entries
[i
].value
=
288 voltage_dependency_table
->entries
[i
].v
;
289 voltage_table
->entries
[i
].smio_low
= 0;
296 * Create Voltage Tables.
298 * @param hwmgr the address of the powerplay hardware manager.
301 int iceland_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
303 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
307 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->voltage_control
) {
308 result
= atomctrl_get_voltage_table_v3(hwmgr
,
309 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_GPIO_LUT
,
310 &data
->vddc_voltage_table
);
311 PP_ASSERT_WITH_CODE((0 == result
),
312 "Failed to retrieve VDDC table.", return result
;);
313 } else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
314 /* SVI2 VDDC voltage */
315 result
= iceland_get_svi2_voltage_table(hwmgr
,
316 hwmgr
->dyn_state
.vddc_dependency_on_mclk
,
317 &data
->vddc_voltage_table
);
318 PP_ASSERT_WITH_CODE((0 == result
),
319 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result
;);
323 (data
->vddc_voltage_table
.count
<= (SMU71_MAX_LEVELS_VDDC
)),
324 "Too many voltage values for VDDC. Trimming to fit state table.",
325 iceland_trim_voltage_table_to_fit_state_table(hwmgr
,
326 SMU71_MAX_LEVELS_VDDC
, &(data
->vddc_voltage_table
));
330 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->vdd_ci_control
) {
331 result
= atomctrl_get_voltage_table_v3(hwmgr
,
332 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
, &(data
->vddci_voltage_table
));
333 PP_ASSERT_WITH_CODE((0 == result
),
334 "Failed to retrieve VDDCI table.", return result
;);
337 /* SVI2 VDDCI voltage */
338 if (ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->vdd_ci_control
) {
339 result
= iceland_get_svi2_voltage_table(hwmgr
,
340 hwmgr
->dyn_state
.vddci_dependency_on_mclk
,
341 &data
->vddci_voltage_table
);
342 PP_ASSERT_WITH_CODE((0 == result
),
343 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result
;);
347 (data
->vddci_voltage_table
.count
<= (SMU71_MAX_LEVELS_VDDCI
)),
348 "Too many voltage values for VDDCI. Trimming to fit state table.",
349 iceland_trim_voltage_table_to_fit_state_table(hwmgr
,
350 SMU71_MAX_LEVELS_VDDCI
, &(data
->vddci_voltage_table
));
355 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
356 result
= atomctrl_get_voltage_table_v3(hwmgr
,
357 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
, &(data
->mvdd_voltage_table
));
358 PP_ASSERT_WITH_CODE((0 == result
),
359 "Failed to retrieve table.", return result
;);
362 /* SVI2 voltage control */
363 if (ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
364 result
= iceland_get_svi2_voltage_table(hwmgr
,
365 hwmgr
->dyn_state
.mvdd_dependency_on_mclk
,
366 &data
->mvdd_voltage_table
);
367 PP_ASSERT_WITH_CODE((0 == result
),
368 "Failed to retrieve SVI2 MVDD table from dependancy table.", return result
;);
372 (data
->mvdd_voltage_table
.count
<= (SMU71_MAX_LEVELS_MVDD
)),
373 "Too many voltage values for MVDD. Trimming to fit state table.",
374 iceland_trim_voltage_table_to_fit_state_table(hwmgr
,
375 SMU71_MAX_LEVELS_MVDD
, &(data
->mvdd_voltage_table
));
381 /*---------------------------MC----------------------------*/
383 uint8_t iceland_get_memory_module_index(struct pp_hwmgr
*hwmgr
)
385 return (uint8_t) (0xFF & (cgs_read_register(hwmgr
->device
, mmBIOS_SCRATCH_4
) >> 16));
388 bool iceland_check_s0_mc_reg_index(uint16_t inReg
, uint16_t *outReg
)
393 case mmMC_SEQ_RAS_TIMING
:
394 *outReg
= mmMC_SEQ_RAS_TIMING_LP
;
397 case mmMC_SEQ_DLL_STBY
:
398 *outReg
= mmMC_SEQ_DLL_STBY_LP
;
401 case mmMC_SEQ_G5PDX_CMD0
:
402 *outReg
= mmMC_SEQ_G5PDX_CMD0_LP
;
405 case mmMC_SEQ_G5PDX_CMD1
:
406 *outReg
= mmMC_SEQ_G5PDX_CMD1_LP
;
409 case mmMC_SEQ_G5PDX_CTRL
:
410 *outReg
= mmMC_SEQ_G5PDX_CTRL_LP
;
413 case mmMC_SEQ_CAS_TIMING
:
414 *outReg
= mmMC_SEQ_CAS_TIMING_LP
;
417 case mmMC_SEQ_MISC_TIMING
:
418 *outReg
= mmMC_SEQ_MISC_TIMING_LP
;
421 case mmMC_SEQ_MISC_TIMING2
:
422 *outReg
= mmMC_SEQ_MISC_TIMING2_LP
;
425 case mmMC_SEQ_PMG_DVS_CMD
:
426 *outReg
= mmMC_SEQ_PMG_DVS_CMD_LP
;
429 case mmMC_SEQ_PMG_DVS_CTL
:
430 *outReg
= mmMC_SEQ_PMG_DVS_CTL_LP
;
433 case mmMC_SEQ_RD_CTL_D0
:
434 *outReg
= mmMC_SEQ_RD_CTL_D0_LP
;
437 case mmMC_SEQ_RD_CTL_D1
:
438 *outReg
= mmMC_SEQ_RD_CTL_D1_LP
;
441 case mmMC_SEQ_WR_CTL_D0
:
442 *outReg
= mmMC_SEQ_WR_CTL_D0_LP
;
445 case mmMC_SEQ_WR_CTL_D1
:
446 *outReg
= mmMC_SEQ_WR_CTL_D1_LP
;
449 case mmMC_PMG_CMD_EMRS
:
450 *outReg
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
453 case mmMC_PMG_CMD_MRS
:
454 *outReg
= mmMC_SEQ_PMG_CMD_MRS_LP
;
457 case mmMC_PMG_CMD_MRS1
:
458 *outReg
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
461 case mmMC_SEQ_PMG_TIMING
:
462 *outReg
= mmMC_SEQ_PMG_TIMING_LP
;
465 case mmMC_PMG_CMD_MRS2
:
466 *outReg
= mmMC_SEQ_PMG_CMD_MRS2_LP
;
469 case mmMC_SEQ_WR_CTL_2
:
470 *outReg
= mmMC_SEQ_WR_CTL_2_LP
;
481 int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table
*table
)
486 for (i
= 0; i
< table
->last
; i
++) {
487 table
->mc_reg_address
[i
].s0
=
488 iceland_check_s0_mc_reg_index(table
->mc_reg_address
[i
].s1
, &address
)
489 ? address
: table
->mc_reg_address
[i
].s1
;
494 int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table
*table
, phw_iceland_mc_reg_table
*ni_table
)
498 PP_ASSERT_WITH_CODE((table
->last
<= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
499 "Invalid VramInfo table.", return -1);
500 PP_ASSERT_WITH_CODE((table
->num_entries
<= MAX_AC_TIMING_ENTRIES
),
501 "Invalid VramInfo table.", return -1);
503 for (i
= 0; i
< table
->last
; i
++) {
504 ni_table
->mc_reg_address
[i
].s1
= table
->mc_reg_address
[i
].s1
;
506 ni_table
->last
= table
->last
;
508 for (i
= 0; i
< table
->num_entries
; i
++) {
509 ni_table
->mc_reg_table_entry
[i
].mclk_max
=
510 table
->mc_reg_table_entry
[i
].mclk_max
;
511 for (j
= 0; j
< table
->last
; j
++) {
512 ni_table
->mc_reg_table_entry
[i
].mc_data
[j
] =
513 table
->mc_reg_table_entry
[i
].mc_data
[j
];
517 ni_table
->num_entries
= table
->num_entries
;
523 * VBIOS omits some information to reduce size, we need to recover them here.
524 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
525 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
526 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
527 * 3. need to set these data for each clock range
529 * @param hwmgr the address of the powerplay hardware manager.
530 * @param table the address of MCRegTable
533 static int iceland_set_mc_special_registers(struct pp_hwmgr
*hwmgr
, phw_iceland_mc_reg_table
*table
)
537 const iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
539 for (i
= 0, j
= table
->last
; i
< table
->last
; i
++) {
540 PP_ASSERT_WITH_CODE((j
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
541 "Invalid VramInfo table.", return -1);
542 switch (table
->mc_reg_address
[i
].s1
) {
544 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write
545 * to mmMC_PMG_CMD_EMRS/_LP[15:0]. Bit[15:0] MRS, need
546 * to be update mmMC_PMG_CMD_MRS/_LP[15:0]
549 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_EMRS
);
550 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_EMRS
;
551 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_EMRS_LP
;
552 for (k
= 0; k
< table
->num_entries
; k
++) {
553 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
554 ((temp_reg
& 0xffff0000)) |
555 ((table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16);
558 PP_ASSERT_WITH_CODE((j
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
559 "Invalid VramInfo table.", return -1);
561 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS
);
562 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS
;
563 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS_LP
;
564 for (k
= 0; k
< table
->num_entries
; k
++) {
565 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
566 (temp_reg
& 0xffff0000) |
567 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
569 if (!data
->is_memory_GDDR5
) {
570 table
->mc_reg_table_entry
[k
].mc_data
[j
] |= 0x100;
574 PP_ASSERT_WITH_CODE((j
<= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
575 "Invalid VramInfo table.", return -1);
577 if (!data
->is_memory_GDDR5
) {
578 table
->mc_reg_address
[j
].s1
= mmMC_PMG_AUTO_CMD
;
579 table
->mc_reg_address
[j
].s0
= mmMC_PMG_AUTO_CMD
;
580 for (k
= 0; k
< table
->num_entries
; k
++) {
581 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
582 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16;
585 PP_ASSERT_WITH_CODE((j
<= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
586 "Invalid VramInfo table.", return -1);
591 case mmMC_SEQ_RESERVE_M
:
592 temp_reg
= cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS1
);
593 table
->mc_reg_address
[j
].s1
= mmMC_PMG_CMD_MRS1
;
594 table
->mc_reg_address
[j
].s0
= mmMC_SEQ_PMG_CMD_MRS1_LP
;
595 for (k
= 0; k
< table
->num_entries
; k
++) {
596 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
597 (temp_reg
& 0xffff0000) |
598 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
601 PP_ASSERT_WITH_CODE((j
<= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
),
602 "Invalid VramInfo table.", return -1);
617 static int iceland_set_valid_flag(phw_iceland_mc_reg_table
*table
)
620 for (i
= 0; i
< table
->last
; i
++) {
621 for (j
= 1; j
< table
->num_entries
; j
++) {
622 if (table
->mc_reg_table_entry
[j
-1].mc_data
[i
] !=
623 table
->mc_reg_table_entry
[j
].mc_data
[i
]) {
624 table
->validflag
|= (1<<i
);
633 static int iceland_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr
)
636 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
637 pp_atomctrl_mc_reg_table
*table
;
638 phw_iceland_mc_reg_table
*ni_table
= &data
->iceland_mc_reg_table
;
639 uint8_t module_index
= iceland_get_memory_module_index(hwmgr
);
641 table
= kzalloc(sizeof(pp_atomctrl_mc_reg_table
), GFP_KERNEL
);
646 /* Program additional LP registers that are no longer programmed by VBIOS */
647 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING
));
648 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING
));
649 cgs_write_register(hwmgr
->device
, mmMC_SEQ_DLL_STBY_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_DLL_STBY
));
650 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD0
));
651 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CMD1
));
652 cgs_write_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CTRL_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_G5PDX_CTRL
));
653 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CMD_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CMD
));
654 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CTL_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_DVS_CTL
));
655 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING
));
656 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2
));
657 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_EMRS_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_EMRS
));
658 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS
));
659 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS1_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS1
));
660 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D0
));
661 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1
));
662 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0
));
663 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1
));
664 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING
));
665 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_CMD_MRS2_LP
, cgs_read_register(hwmgr
->device
, mmMC_PMG_CMD_MRS2
));
666 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_2_LP
, cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_2
));
668 memset(table
, 0x00, sizeof(pp_atomctrl_mc_reg_table
));
670 result
= atomctrl_initialize_mc_reg_table(hwmgr
, module_index
, table
);
673 result
= iceland_copy_vbios_smc_reg_table(table
, ni_table
);
676 iceland_set_s0_mc_reg_index(ni_table
);
677 result
= iceland_set_mc_special_registers(hwmgr
, ni_table
);
681 iceland_set_valid_flag(ni_table
);
688 * Programs static screed detection parameters
690 * @param hwmgr the address of the powerplay hardware manager.
693 int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr
*hwmgr
)
695 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
697 /* Set static screen threshold unit*/
698 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
,
699 CGS_IND_REG__SMC
, CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD_UNIT
,
700 data
->static_screen_threshold_unit
);
701 /* Set static screen threshold*/
702 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
,
703 CGS_IND_REG__SMC
, CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD
,
704 data
->static_screen_threshold
);
710 * Setup display gap for glitch free memory clock switching.
712 * @param hwmgr the address of the powerplay hardware manager.
715 int iceland_enable_display_gap(struct pp_hwmgr
*hwmgr
)
717 uint32_t display_gap
= cgs_read_ind_register(hwmgr
->device
,
718 CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
);
720 display_gap
= PHM_SET_FIELD(display_gap
,
721 CG_DISPLAY_GAP_CNTL
, DISP_GAP
, DISPLAY_GAP_IGNORE
);
723 display_gap
= PHM_SET_FIELD(display_gap
,
724 CG_DISPLAY_GAP_CNTL
, DISP_GAP_MCHG
, DISPLAY_GAP_VBLANK
);
726 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
727 ixCG_DISPLAY_GAP_CNTL
, display_gap
);
733 * Programs activity state transition voting clients
735 * @param hwmgr the address of the powerplay hardware manager.
738 int iceland_program_voting_clients(struct pp_hwmgr
*hwmgr
)
740 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
742 /* Clear reset for voting clients before enabling DPM */
743 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
744 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 0);
745 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
746 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 0);
748 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
749 ixCG_FREQ_TRAN_VOTING_0
, data
->voting_rights_clients0
);
750 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
751 ixCG_FREQ_TRAN_VOTING_1
, data
->voting_rights_clients1
);
752 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
753 ixCG_FREQ_TRAN_VOTING_2
, data
->voting_rights_clients2
);
754 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
755 ixCG_FREQ_TRAN_VOTING_3
, data
->voting_rights_clients3
);
756 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
757 ixCG_FREQ_TRAN_VOTING_4
, data
->voting_rights_clients4
);
758 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
759 ixCG_FREQ_TRAN_VOTING_5
, data
->voting_rights_clients5
);
760 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
761 ixCG_FREQ_TRAN_VOTING_6
, data
->voting_rights_clients6
);
762 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
763 ixCG_FREQ_TRAN_VOTING_7
, data
->voting_rights_clients7
);
768 static int iceland_upload_firmware(struct pp_hwmgr
*hwmgr
)
772 if (!iceland_is_smc_ram_running(hwmgr
->smumgr
))
773 ret
= iceland_smu_upload_firmware_image(hwmgr
->smumgr
);
779 * Get the location of various tables inside the FW image.
781 * @param hwmgr the address of the powerplay hardware manager.
784 int iceland_process_firmware_header(struct pp_hwmgr
*hwmgr
)
786 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
792 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
793 SMU71_FIRMWARE_HEADER_LOCATION
+
794 offsetof(SMU71_Firmware_Header
, DpmTable
),
795 &tmp
, data
->sram_end
);
798 data
->dpm_table_start
= tmp
;
801 error
|= (0 != result
);
803 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
804 SMU71_FIRMWARE_HEADER_LOCATION
+
805 offsetof(SMU71_Firmware_Header
, SoftRegisters
),
806 &tmp
, data
->sram_end
);
809 data
->soft_regs_start
= tmp
;
812 error
|= (0 != result
);
815 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
816 SMU71_FIRMWARE_HEADER_LOCATION
+
817 offsetof(SMU71_Firmware_Header
, mcRegisterTable
),
818 &tmp
, data
->sram_end
);
821 data
->mc_reg_table_start
= tmp
;
824 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
825 SMU71_FIRMWARE_HEADER_LOCATION
+
826 offsetof(SMU71_Firmware_Header
, FanTable
),
827 &tmp
, data
->sram_end
);
830 data
->fan_table_start
= tmp
;
833 error
|= (0 != result
);
835 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
836 SMU71_FIRMWARE_HEADER_LOCATION
+
837 offsetof(SMU71_Firmware_Header
, mcArbDramTimingTable
),
838 &tmp
, data
->sram_end
);
841 data
->arb_table_start
= tmp
;
844 error
|= (0 != result
);
847 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
848 SMU71_FIRMWARE_HEADER_LOCATION
+
849 offsetof(SMU71_Firmware_Header
, Version
),
850 &tmp
, data
->sram_end
);
853 hwmgr
->microcode_version_info
.SMC
= tmp
;
856 error
|= (0 != result
);
858 result
= iceland_read_smc_sram_dword(hwmgr
->smumgr
,
859 SMU71_FIRMWARE_HEADER_LOCATION
+
860 offsetof(SMU71_Firmware_Header
, UlvSettings
),
861 &tmp
, data
->sram_end
);
864 data
->ulv_settings_start
= tmp
;
867 error
|= (0 != result
);
869 return error
? 1 : 0;
873 * Copy one arb setting to another and then switch the active set.
874 * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
876 int iceland_copy_and_switch_arb_sets(struct pp_hwmgr
*hwmgr
,
877 uint32_t arbFreqSrc
, uint32_t arbFreqDest
)
879 uint32_t mc_arb_dram_timing
;
880 uint32_t mc_arb_dram_timing2
;
882 uint32_t mc_cg_config
;
884 switch (arbFreqSrc
) {
885 case MC_CG_ARB_FREQ_F0
:
886 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
887 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
888 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
891 case MC_CG_ARB_FREQ_F1
:
892 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
);
893 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
);
894 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
);
901 switch (arbFreqDest
) {
902 case MC_CG_ARB_FREQ_F0
:
903 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
904 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
905 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
, burst_time
);
908 case MC_CG_ARB_FREQ_F1
:
909 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
910 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
911 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
, burst_time
);
918 mc_cg_config
= cgs_read_register(hwmgr
->device
, mmMC_CG_CONFIG
);
919 mc_cg_config
|= 0x0000000F;
920 cgs_write_register(hwmgr
->device
, mmMC_CG_CONFIG
, mc_cg_config
);
921 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_CG
, CG_ARB_REQ
, arbFreqDest
);
927 * Initial switch from ARB F0->F1
929 * @param hwmgr the address of the powerplay hardware manager.
931 * This function is to be called from the SetPowerState table.
933 int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr
*hwmgr
)
935 return iceland_copy_and_switch_arb_sets(hwmgr
, MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
938 /* ---------------------------------------- ULV related functions ----------------------------------------------------*/
941 static int iceland_reset_single_dpm_table(
942 struct pp_hwmgr
*hwmgr
,
943 struct iceland_single_dpm_table
*dpm_table
,
947 if (!(count
<= MAX_REGULAR_DPM_NUMBER
))
948 printk(KERN_ERR
"[ powerplay ] Fatal error, can not set up single DPM \
949 table entries to exceed max number! \n");
951 dpm_table
->count
= count
;
952 for (i
= 0; i
< MAX_REGULAR_DPM_NUMBER
; i
++) {
953 dpm_table
->dpm_levels
[i
].enabled
= 0;
959 static void iceland_setup_pcie_table_entry(
960 struct iceland_single_dpm_table
*dpm_table
,
961 uint32_t index
, uint32_t pcie_gen
,
964 dpm_table
->dpm_levels
[index
].value
= pcie_gen
;
965 dpm_table
->dpm_levels
[index
].param1
= pcie_lanes
;
966 dpm_table
->dpm_levels
[index
].enabled
= 1;
970 * Set up the PCIe DPM table as follows:
972 * A = Performance State, Max, Gen Speed
973 * C = Performance State, Min, Gen Speed
974 * 1 = Performance State, Max, Lane #
975 * 3 = Performance State, Min, Lane #
977 * B = Power Saving State, Max, Gen Speed
978 * D = Power Saving State, Min, Gen Speed
979 * 2 = Power Saving State, Max, Lane #
980 * 4 = Power Saving State, Min, Lane #
983 * DPM Index Gen Speed Lane #
992 static int iceland_setup_default_pcie_tables(struct pp_hwmgr
*hwmgr
)
994 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
996 PP_ASSERT_WITH_CODE((data
->use_pcie_performance_levels
||
997 data
->use_pcie_power_saving_levels
),
998 "No pcie performance levels!", return -EINVAL
);
1000 if (data
->use_pcie_performance_levels
&& !data
->use_pcie_power_saving_levels
) {
1001 data
->pcie_gen_power_saving
= data
->pcie_gen_performance
;
1002 data
->pcie_lane_power_saving
= data
->pcie_lane_performance
;
1003 } else if (!data
->use_pcie_performance_levels
&& data
->use_pcie_power_saving_levels
) {
1004 data
->pcie_gen_performance
= data
->pcie_gen_power_saving
;
1005 data
->pcie_lane_performance
= data
->pcie_lane_power_saving
;
1008 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.pcie_speed_table
, SMU71_MAX_LEVELS_LINK
);
1010 /* Hardcode Pcie Table */
1011 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 0,
1012 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Min_PCIEGen
),
1013 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1014 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 1,
1015 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Min_PCIEGen
),
1016 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1017 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 2,
1018 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Max_PCIEGen
),
1019 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1020 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 3,
1021 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Max_PCIEGen
),
1022 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1023 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 4,
1024 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Max_PCIEGen
),
1025 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1026 iceland_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 5,
1027 get_pcie_gen_support(data
->pcie_gen_cap
, PP_Max_PCIEGen
),
1028 get_pcie_lane_support(data
->pcie_lane_cap
, PP_Max_PCIELane
));
1029 data
->dpm_table
.pcie_speed_table
.count
= 6;
1037 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
1038 * Dynamic state patching function will then trim these state tables to the allowed range based
1039 * on the power policy or external client requests, such as UVD request, etc.
1041 static int iceland_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
1043 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1046 struct phm_clock_voltage_dependency_table
*allowed_vdd_sclk_table
=
1047 hwmgr
->dyn_state
.vddc_dependency_on_sclk
;
1048 struct phm_clock_voltage_dependency_table
*allowed_vdd_mclk_table
=
1049 hwmgr
->dyn_state
.vddc_dependency_on_mclk
;
1050 struct phm_cac_leakage_table
*std_voltage_table
=
1051 hwmgr
->dyn_state
.cac_leakage_table
;
1053 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table
!= NULL
,
1054 "SCLK dependency table is missing. This table is mandatory", return -1);
1055 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table
->count
>= 1,
1056 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
1058 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
!= NULL
,
1059 "MCLK dependency table is missing. This table is mandatory", return -1);
1060 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
->count
>= 1,
1061 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
1063 /* clear the state table to reset everything to default */
1064 memset(&(data
->dpm_table
), 0x00, sizeof(data
->dpm_table
));
1065 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.sclk_table
, SMU71_MAX_LEVELS_GRAPHICS
);
1066 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.mclk_table
, SMU71_MAX_LEVELS_MEMORY
);
1067 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.vddc_table
, SMU71_MAX_LEVELS_VDDC
);
1068 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.vdd_ci_table
, SMU71_MAX_LEVELS_VDDCI
);
1069 iceland_reset_single_dpm_table(hwmgr
, &data
->dpm_table
.mvdd_table
, SMU71_MAX_LEVELS_MVDD
);
1071 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table
!= NULL
,
1072 "SCLK dependency table is missing. This table is mandatory", return -1);
1073 /* Initialize Sclk DPM table based on allow Sclk values*/
1074 data
->dpm_table
.sclk_table
.count
= 0;
1076 for (i
= 0; i
< allowed_vdd_sclk_table
->count
; i
++) {
1077 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
-1].value
!=
1078 allowed_vdd_sclk_table
->entries
[i
].clk
) {
1079 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].value
=
1080 allowed_vdd_sclk_table
->entries
[i
].clk
;
1081 data
->dpm_table
.sclk_table
.dpm_levels
[data
->dpm_table
.sclk_table
.count
].enabled
= 1; /*(i==0) ? 1 : 0; to do */
1082 data
->dpm_table
.sclk_table
.count
++;
1086 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table
!= NULL
,
1087 "MCLK dependency table is missing. This table is mandatory", return -1);
1088 /* Initialize Mclk DPM table based on allow Mclk values */
1089 data
->dpm_table
.mclk_table
.count
= 0;
1090 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
1091 if (i
== 0 || data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
-1].value
!=
1092 allowed_vdd_mclk_table
->entries
[i
].clk
) {
1093 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].value
=
1094 allowed_vdd_mclk_table
->entries
[i
].clk
;
1095 data
->dpm_table
.mclk_table
.dpm_levels
[data
->dpm_table
.mclk_table
.count
].enabled
= 1; /*(i==0) ? 1 : 0; */
1096 data
->dpm_table
.mclk_table
.count
++;
1100 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
1101 for (i
= 0; i
< allowed_vdd_sclk_table
->count
; i
++) {
1102 data
->dpm_table
.vddc_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
1103 data
->dpm_table
.vddc_table
.dpm_levels
[i
].param1
= std_voltage_table
->entries
[i
].Leakage
;
1104 /* param1 is for corresponding std voltage */
1105 data
->dpm_table
.vddc_table
.dpm_levels
[i
].enabled
= 1;
1108 data
->dpm_table
.vddc_table
.count
= allowed_vdd_sclk_table
->count
;
1109 allowed_vdd_mclk_table
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
1111 if (NULL
!= allowed_vdd_mclk_table
) {
1112 /* Initialize Vddci DPM table based on allow Mclk values */
1113 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
1114 data
->dpm_table
.vdd_ci_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
1115 data
->dpm_table
.vdd_ci_table
.dpm_levels
[i
].enabled
= 1;
1117 data
->dpm_table
.vdd_ci_table
.count
= allowed_vdd_mclk_table
->count
;
1120 allowed_vdd_mclk_table
= hwmgr
->dyn_state
.mvdd_dependency_on_mclk
;
1122 if (NULL
!= allowed_vdd_mclk_table
) {
1124 * Initialize MVDD DPM table based on allow Mclk
1127 for (i
= 0; i
< allowed_vdd_mclk_table
->count
; i
++) {
1128 data
->dpm_table
.mvdd_table
.dpm_levels
[i
].value
= allowed_vdd_mclk_table
->entries
[i
].v
;
1129 data
->dpm_table
.mvdd_table
.dpm_levels
[i
].enabled
= 1;
1131 data
->dpm_table
.mvdd_table
.count
= allowed_vdd_mclk_table
->count
;
1134 /* setup PCIE gen speed levels*/
1135 iceland_setup_default_pcie_tables(hwmgr
);
1137 /* save a copy of the default DPM table*/
1138 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
), sizeof(struct iceland_dpm_table
));
1144 * @brief PhwIceland_GetVoltageOrder
1145 * Returns index of requested voltage record in lookup(table)
1146 * @param hwmgr - pointer to hardware manager
1147 * @param lookutab - lookup list to search in
1148 * @param voltage - voltage to look for
1149 * @return 0 on success
1151 uint8_t iceland_get_voltage_index(phm_ppt_v1_voltage_lookup_table
*look_up_table
,
1154 uint8_t count
= (uint8_t) (look_up_table
->count
);
1157 PP_ASSERT_WITH_CODE((NULL
!= look_up_table
), "Lookup Table empty.", return 0;);
1158 PP_ASSERT_WITH_CODE((0 != count
), "Lookup Table empty.", return 0;);
1160 for (i
= 0; i
< count
; i
++) {
1161 /* find first voltage equal or bigger than requested */
1162 if (look_up_table
->entries
[i
].us_vdd
>= voltage
)
1166 /* voltage is bigger than max voltage in the table */
1171 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr
*hwmgr
,
1172 pp_atomctrl_voltage_table_entry
*tab
, uint16_t *hi
,
1176 bool vol_found
= false;
1177 *hi
= tab
->value
* VOLTAGE_SCALE
;
1178 *lo
= tab
->value
* VOLTAGE_SCALE
;
1180 /* SCLK/VDDC Dependency Table has to exist. */
1181 PP_ASSERT_WITH_CODE(NULL
!= hwmgr
->dyn_state
.vddc_dependency_on_sclk
,
1182 "The SCLK/VDDC Dependency Table does not exist.\n",
1185 if (NULL
== hwmgr
->dyn_state
.cac_leakage_table
) {
1186 pr_warning("CAC Leakage Table does not exist, using vddc.\n");
1191 * Since voltage in the sclk/vddc dependency table is not
1192 * necessarily in ascending order because of ELB voltage
1193 * patching, loop through entire list to find exact voltage.
1195 for (v_index
= 0; (uint32_t)v_index
< hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
; v_index
++) {
1196 if (tab
->value
== hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[v_index
].v
) {
1198 if ((uint32_t)v_index
< hwmgr
->dyn_state
.cac_leakage_table
->count
) {
1199 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Vddc
* VOLTAGE_SCALE
;
1200 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Leakage
* VOLTAGE_SCALE
);
1202 pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
1203 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Vddc
* VOLTAGE_SCALE
;
1204 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Leakage
* VOLTAGE_SCALE
);
1211 * If voltage is not found in the first pass, loop again to
1212 * find the best match, equal or higher value.
1215 for (v_index
= 0; (uint32_t)v_index
< hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
; v_index
++) {
1216 if (tab
->value
<= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[v_index
].v
) {
1218 if ((uint32_t)v_index
< hwmgr
->dyn_state
.cac_leakage_table
->count
) {
1219 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Vddc
* VOLTAGE_SCALE
;
1220 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[v_index
].Leakage
) * VOLTAGE_SCALE
;
1222 pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
1223 *lo
= hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Vddc
* VOLTAGE_SCALE
;
1224 *hi
= (uint16_t)(hwmgr
->dyn_state
.cac_leakage_table
->entries
[hwmgr
->dyn_state
.cac_leakage_table
->count
- 1].Leakage
* VOLTAGE_SCALE
);
1231 pr_warning("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
1237 static int iceland_populate_smc_voltage_table(struct pp_hwmgr
*hwmgr
,
1238 pp_atomctrl_voltage_table_entry
*tab
,
1239 SMU71_Discrete_VoltageLevel
*smc_voltage_tab
) {
1243 result
= iceland_get_std_voltage_value_sidd(hwmgr
, tab
,
1244 &smc_voltage_tab
->StdVoltageHiSidd
,
1245 &smc_voltage_tab
->StdVoltageLoSidd
);
1247 smc_voltage_tab
->StdVoltageHiSidd
= tab
->value
* VOLTAGE_SCALE
;
1248 smc_voltage_tab
->StdVoltageLoSidd
= tab
->value
* VOLTAGE_SCALE
;
1251 smc_voltage_tab
->Voltage
= PP_HOST_TO_SMC_US(tab
->value
* VOLTAGE_SCALE
);
1252 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab
->StdVoltageHiSidd
);
1253 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab
->StdVoltageHiSidd
);
1259 * Vddc table preparation for SMC.
1261 * @param hwmgr the address of the hardware manager
1262 * @param table the SMC DPM table structure to be populated
1265 static int iceland_populate_smc_vddc_table(struct pp_hwmgr
*hwmgr
,
1266 SMU71_Discrete_DpmTable
*table
)
1271 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1273 table
->VddcLevelCount
= data
->vddc_voltage_table
.count
;
1274 for (count
= 0; count
< table
->VddcLevelCount
; count
++) {
1275 result
= iceland_populate_smc_voltage_table(hwmgr
,
1276 &data
->vddc_voltage_table
.entries
[count
],
1277 &table
->VddcLevel
[count
]);
1278 PP_ASSERT_WITH_CODE(0 == result
, "do not populate SMC VDDC voltage table", return -EINVAL
);
1280 /* GPIO voltage control */
1281 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->voltage_control
)
1282 table
->VddcLevel
[count
].Smio
|= data
->vddc_voltage_table
.entries
[count
].smio_low
;
1283 else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
)
1284 table
->VddcLevel
[count
].Smio
= 0;
1287 CONVERT_FROM_HOST_TO_SMC_UL(table
->VddcLevelCount
);
1293 * Vddci table preparation for SMC.
1295 * @param *hwmgr The address of the hardware manager.
1296 * @param *table The SMC DPM table structure to be populated.
1299 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr
*hwmgr
,
1300 SMU71_Discrete_DpmTable
*table
)
1304 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1306 table
->VddciLevelCount
= data
->vddci_voltage_table
.count
;
1307 for (count
= 0; count
< table
->VddciLevelCount
; count
++) {
1308 result
= iceland_populate_smc_voltage_table(hwmgr
,
1309 &data
->vddci_voltage_table
.entries
[count
],
1310 &table
->VddciLevel
[count
]);
1311 PP_ASSERT_WITH_CODE(0 == result
, "do not populate SMC VDDCI voltage table", return -EINVAL
);
1313 /* GPIO voltage control */
1314 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->vdd_ci_control
)
1315 table
->VddciLevel
[count
].Smio
|= data
->vddci_voltage_table
.entries
[count
].smio_low
;
1317 table
->VddciLevel
[count
].Smio
= 0;
1320 CONVERT_FROM_HOST_TO_SMC_UL(table
->VddcLevelCount
);
1326 * Mvdd table preparation for SMC.
1328 * @param *hwmgr The address of the hardware manager.
1329 * @param *table The SMC DPM table structure to be populated.
1332 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr
*hwmgr
,
1333 SMU71_Discrete_DpmTable
*table
)
1337 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1339 table
->MvddLevelCount
= data
->mvdd_voltage_table
.count
;
1340 for (count
= 0; count
< table
->MvddLevelCount
; count
++) {
1341 result
= iceland_populate_smc_voltage_table(hwmgr
,
1342 &data
->mvdd_voltage_table
.entries
[count
],
1343 &table
->MvddLevel
[count
]);
1344 PP_ASSERT_WITH_CODE(0 == result
, "do not populate SMC VDDCI voltage table", return -EINVAL
);
1346 /* GPIO voltage control */
1347 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
)
1348 table
->MvddLevel
[count
].Smio
|= data
->mvdd_voltage_table
.entries
[count
].smio_low
;
1350 table
->MvddLevel
[count
].Smio
= 0;
1353 CONVERT_FROM_HOST_TO_SMC_UL(table
->MvddLevelCount
);
1359 * Convert a voltage value in mv unit to VID number required by SMU firmware
1361 static uint8_t convert_to_vid(uint16_t vddc
)
1363 return (uint8_t) ((6200 - (vddc
* VOLTAGE_SCALE
)) / 25);
1366 int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr
*hwmgr
)
1369 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
1370 uint8_t * hi_vid
= data
->power_tune_table
.BapmVddCVidHiSidd
;
1371 uint8_t * lo_vid
= data
->power_tune_table
.BapmVddCVidLoSidd
;
1373 PP_ASSERT_WITH_CODE(NULL
!= hwmgr
->dyn_state
.cac_leakage_table
,
1374 "The CAC Leakage table does not exist!", return -EINVAL
);
1375 PP_ASSERT_WITH_CODE(hwmgr
->dyn_state
.cac_leakage_table
->count
<= 8,
1376 "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL
);
1377 PP_ASSERT_WITH_CODE(hwmgr
->dyn_state
.cac_leakage_table
->count
== hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
,
1378 "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL
);
1380 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_EVV
)) {
1381 for (i
= 0; (uint32_t) i
< hwmgr
->dyn_state
.cac_leakage_table
->count
; i
++) {
1382 lo_vid
[i
] = convert_to_vid(hwmgr
->dyn_state
.cac_leakage_table
->entries
[i
].Vddc1
);
1383 hi_vid
[i
] = convert_to_vid(hwmgr
->dyn_state
.cac_leakage_table
->entries
[i
].Vddc2
);
1386 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL
);
1392 int iceland_populate_vddc_vid(struct pp_hwmgr
*hwmgr
)
1395 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
1396 uint8_t *vid
= data
->power_tune_table
.VddCVid
;
1398 PP_ASSERT_WITH_CODE(data
->vddc_voltage_table
.count
<= 8,
1399 "There should never be more than 8 entries for VddcVid!!!",
1402 for (i
= 0; i
< (int)data
->vddc_voltage_table
.count
; i
++) {
1403 vid
[i
] = convert_to_vid(data
->vddc_voltage_table
.entries
[i
].value
);
1410 * Preparation of voltage tables for SMC.
1412 * @param hwmgr the address of the hardware manager
1413 * @param table the SMC DPM table structure to be populated
1417 int iceland_populate_smc_voltage_tables(struct pp_hwmgr
*hwmgr
,
1418 SMU71_Discrete_DpmTable
*table
)
1422 result
= iceland_populate_smc_vddc_table(hwmgr
, table
);
1423 PP_ASSERT_WITH_CODE(0 == result
,
1424 "can not populate VDDC voltage table to SMC", return -1);
1426 result
= iceland_populate_smc_vdd_ci_table(hwmgr
, table
);
1427 PP_ASSERT_WITH_CODE(0 == result
,
1428 "can not populate VDDCI voltage table to SMC", return -1);
1430 result
= iceland_populate_smc_mvdd_table(hwmgr
, table
);
1431 PP_ASSERT_WITH_CODE(0 == result
,
1432 "can not populate MVDD voltage table to SMC", return -1);
1439 * Re-generate the DPM level mask value
1440 * @param hwmgr the address of the hardware manager
1442 static uint32_t iceland_get_dpm_level_enable_mask_value(
1443 struct iceland_single_dpm_table
* dpm_table
)
1446 uint32_t mask_value
= 0;
1448 for (i
= dpm_table
->count
; i
> 0; i
--) {
1449 mask_value
= mask_value
<< 1;
1451 if (dpm_table
->dpm_levels
[i
-1].enabled
)
1454 mask_value
&= 0xFFFFFFFE;
1459 int iceland_populate_memory_timing_parameters(
1460 struct pp_hwmgr
*hwmgr
,
1461 uint32_t engine_clock
,
1462 uint32_t memory_clock
,
1463 struct SMU71_Discrete_MCArbDramTimingTableEntry
*arb_regs
1466 uint32_t dramTiming
;
1467 uint32_t dramTiming2
;
1471 result
= atomctrl_set_engine_dram_timings_rv770(hwmgr
,
1472 engine_clock
, memory_clock
);
1474 PP_ASSERT_WITH_CODE(result
== 0,
1475 "Error calling VBIOS to set DRAM_TIMING.", return result
);
1477 dramTiming
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
1478 dramTiming2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
1479 burstTime
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
1481 arb_regs
->McArbDramTiming
= PP_HOST_TO_SMC_UL(dramTiming
);
1482 arb_regs
->McArbDramTiming2
= PP_HOST_TO_SMC_UL(dramTiming2
);
1483 arb_regs
->McArbBurstTime
= (uint8_t)burstTime
;
1489 * Setup parameters for the MC ARB.
1491 * @param hwmgr the address of the powerplay hardware manager.
1493 * This function is to be called from the SetPowerState table.
1495 int iceland_program_memory_timing_parameters(struct pp_hwmgr
*hwmgr
)
1497 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1499 SMU71_Discrete_MCArbDramTimingTable arb_regs
;
1502 memset(&arb_regs
, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable
));
1504 for (i
= 0; i
< data
->dpm_table
.sclk_table
.count
; i
++) {
1505 for (j
= 0; j
< data
->dpm_table
.mclk_table
.count
; j
++) {
1506 result
= iceland_populate_memory_timing_parameters
1507 (hwmgr
, data
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
1508 data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
1509 &arb_regs
.entries
[i
][j
]);
1518 result
= iceland_copy_bytes_to_smc(
1520 data
->arb_table_start
,
1521 (uint8_t *)&arb_regs
,
1522 sizeof(SMU71_Discrete_MCArbDramTimingTable
),
1530 static int iceland_populate_smc_link_level(struct pp_hwmgr
*hwmgr
, SMU71_Discrete_DpmTable
*table
)
1532 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1533 struct iceland_dpm_table
*dpm_table
= &data
->dpm_table
;
1536 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1537 for (i
= 0; i
<= dpm_table
->pcie_speed_table
.count
; i
++) {
1538 table
->LinkLevel
[i
].PcieGenSpeed
=
1539 (uint8_t)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
1540 table
->LinkLevel
[i
].PcieLaneCount
=
1541 (uint8_t)encode_pcie_lane_width(dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
1542 table
->LinkLevel
[i
].EnabledForActivity
=
1544 table
->LinkLevel
[i
].SPC
=
1545 (uint8_t)(data
->pcie_spc_cap
& 0xff);
1546 table
->LinkLevel
[i
].DownThreshold
=
1547 PP_HOST_TO_SMC_UL(5);
1548 table
->LinkLevel
[i
].UpThreshold
=
1549 PP_HOST_TO_SMC_UL(30);
1552 data
->smc_state_table
.LinkLevelCount
=
1553 (uint8_t)dpm_table
->pcie_speed_table
.count
;
1554 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
1555 iceland_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
1560 static int iceland_populate_smc_uvd_level(struct pp_hwmgr
*hwmgr
,
1561 SMU71_Discrete_DpmTable
*table
)
1566 uint8_t iceland_get_voltage_id(pp_atomctrl_voltage_table
*voltage_table
,
1569 uint8_t count
= (uint8_t) (voltage_table
->count
);
1572 PP_ASSERT_WITH_CODE((NULL
!= voltage_table
),
1573 "Voltage Table empty.", return 0;);
1574 PP_ASSERT_WITH_CODE((0 != count
),
1575 "Voltage Table empty.", return 0;);
1577 for (i
= 0; i
< count
; i
++) {
1578 /* find first voltage bigger than requested */
1579 if (voltage_table
->entries
[i
].value
>= voltage
)
1583 /* voltage is bigger than max voltage in the table */
1587 static int iceland_populate_smc_vce_level(struct pp_hwmgr
*hwmgr
,
1588 SMU71_Discrete_DpmTable
*table
)
1593 static int iceland_populate_smc_acp_level(struct pp_hwmgr
*hwmgr
,
1594 SMU71_Discrete_DpmTable
*table
)
1599 static int iceland_populate_smc_samu_level(struct pp_hwmgr
*hwmgr
,
1600 SMU71_Discrete_DpmTable
*table
)
1606 static int iceland_populate_smc_svi2_config(struct pp_hwmgr
*hwmgr
,
1607 SMU71_Discrete_DpmTable
*tab
)
1609 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1611 if(ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
)
1612 tab
->SVI2Enable
|= VDDC_ON_SVI2
;
1614 if(ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->vdd_ci_control
)
1615 tab
->SVI2Enable
|= VDDCI_ON_SVI2
;
1617 tab
->MergedVddci
= 1;
1619 if(ICELAND_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
)
1620 tab
->SVI2Enable
|= MVDD_ON_SVI2
;
1622 PP_ASSERT_WITH_CODE( tab
->SVI2Enable
!= (VDDC_ON_SVI2
| VDDCI_ON_SVI2
| MVDD_ON_SVI2
) &&
1623 (tab
->SVI2Enable
& VDDC_ON_SVI2
), "SVI2 domain configuration is incorrect!", return -EINVAL
);
1628 static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr
*hwmgr
,
1629 struct phm_clock_voltage_dependency_table
*allowed_clock_voltage_table
,
1630 uint32_t clock
, uint32_t *vol
)
1634 /* clock - voltage dependency table is empty table */
1635 if (allowed_clock_voltage_table
->count
== 0)
1638 for (i
= 0; i
< allowed_clock_voltage_table
->count
; i
++) {
1639 /* find first sclk bigger than request */
1640 if (allowed_clock_voltage_table
->entries
[i
].clk
>= clock
) {
1641 *vol
= allowed_clock_voltage_table
->entries
[i
].v
;
1646 /* sclk is bigger than max sclk in the dependence table */
1647 *vol
= allowed_clock_voltage_table
->entries
[i
- 1].v
;
1652 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock
,
1655 uint8_t mc_para_index
;
1658 if (memory_clock
< 12500) {
1659 mc_para_index
= 0x00;
1660 } else if (memory_clock
> 47500) {
1661 mc_para_index
= 0x0f;
1663 mc_para_index
= (uint8_t)((memory_clock
- 10000) / 2500);
1666 if (memory_clock
< 65000) {
1667 mc_para_index
= 0x00;
1668 } else if (memory_clock
> 135000) {
1669 mc_para_index
= 0x0f;
1671 mc_para_index
= (uint8_t)((memory_clock
- 60000) / 5000);
1675 return mc_para_index
;
1678 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock
)
1680 uint8_t mc_para_index
;
1682 if (memory_clock
< 10000) {
1684 } else if (memory_clock
>= 80000) {
1685 mc_para_index
= 0x0f;
1687 mc_para_index
= (uint8_t)((memory_clock
- 10000) / 5000 + 1);
1690 return mc_para_index
;
1693 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr
*hwmgr
, const struct phm_phase_shedding_limits_table
*pl
,
1694 uint32_t sclk
, uint32_t *p_shed
)
1698 /* use the minimum phase shedding */
1702 * PPGen ensures the phase shedding limits table is sorted
1703 * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk.
1704 * VBIOS ensures the phase shedding masks table is sorted from
1705 * least phases enabled (phase shedding on) to most phases
1706 * enabled (phase shedding off).
1708 for (i
= 0; i
< pl
->count
; i
++) {
1709 if (sclk
< pl
->entries
[i
].Sclk
) {
1710 /* Enable phase shedding */
1719 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr
*hwmgr
, const struct phm_phase_shedding_limits_table
*pl
,
1720 uint32_t memory_clock
, uint32_t *p_shed
)
1724 /* use the minimum phase shedding */
1728 * PPGen ensures the phase shedding limits table is sorted
1729 * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk.
1730 * VBIOS ensures the phase shedding masks table is sorted from
1731 * least phases enabled (phase shedding on) to most phases
1732 * enabled (phase shedding off).
1734 for (i
= 0; i
< pl
->count
; i
++) {
1735 if (memory_clock
< pl
->entries
[i
].Mclk
) {
1736 /* Enable phase shedding */
1746 * Populates the SMC MCLK structure using the provided memory clock
1748 * @param hwmgr the address of the hardware manager
1749 * @param memory_clock the memory clock to use to populate the structure
1750 * @param sclk the SMC SCLK structure to be populated
1752 static int iceland_calculate_mclk_params(
1753 struct pp_hwmgr
*hwmgr
,
1754 uint32_t memory_clock
,
1755 SMU71_Discrete_MemoryLevel
*mclk
,
1760 const iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1761 uint32_t dll_cntl
= data
->clock_registers
.vDLL_CNTL
;
1762 uint32_t mclk_pwrmgt_cntl
= data
->clock_registers
.vMCLK_PWRMGT_CNTL
;
1763 uint32_t mpll_ad_func_cntl
= data
->clock_registers
.vMPLL_AD_FUNC_CNTL
;
1764 uint32_t mpll_dq_func_cntl
= data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
;
1765 uint32_t mpll_func_cntl
= data
->clock_registers
.vMPLL_FUNC_CNTL
;
1766 uint32_t mpll_func_cntl_1
= data
->clock_registers
.vMPLL_FUNC_CNTL_1
;
1767 uint32_t mpll_func_cntl_2
= data
->clock_registers
.vMPLL_FUNC_CNTL_2
;
1768 uint32_t mpll_ss1
= data
->clock_registers
.vMPLL_SS1
;
1769 uint32_t mpll_ss2
= data
->clock_registers
.vMPLL_SS2
;
1771 pp_atomctrl_memory_clock_param mpll_param
;
1774 result
= atomctrl_get_memory_pll_dividers_si(hwmgr
,
1775 memory_clock
, &mpll_param
, strobe_mode
);
1776 PP_ASSERT_WITH_CODE(0 == result
,
1777 "Error retrieving Memory Clock Parameters from VBIOS.", return result
);
1779 /* MPLL_FUNC_CNTL setup*/
1780 mpll_func_cntl
= PHM_SET_FIELD(mpll_func_cntl
, MPLL_FUNC_CNTL
, BWCTRL
, mpll_param
.bw_ctrl
);
1782 /* MPLL_FUNC_CNTL_1 setup*/
1783 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1784 MPLL_FUNC_CNTL_1
, CLKF
, mpll_param
.mpll_fb_divider
.cl_kf
);
1785 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1786 MPLL_FUNC_CNTL_1
, CLKFRAC
, mpll_param
.mpll_fb_divider
.clk_frac
);
1787 mpll_func_cntl_1
= PHM_SET_FIELD(mpll_func_cntl_1
,
1788 MPLL_FUNC_CNTL_1
, VCO_MODE
, mpll_param
.vco_mode
);
1790 /* MPLL_AD_FUNC_CNTL setup*/
1791 mpll_ad_func_cntl
= PHM_SET_FIELD(mpll_ad_func_cntl
,
1792 MPLL_AD_FUNC_CNTL
, YCLK_POST_DIV
, mpll_param
.mpll_post_divider
);
1794 if (data
->is_memory_GDDR5
) {
1795 /* MPLL_DQ_FUNC_CNTL setup*/
1796 mpll_dq_func_cntl
= PHM_SET_FIELD(mpll_dq_func_cntl
,
1797 MPLL_DQ_FUNC_CNTL
, YCLK_SEL
, mpll_param
.yclk_sel
);
1798 mpll_dq_func_cntl
= PHM_SET_FIELD(mpll_dq_func_cntl
,
1799 MPLL_DQ_FUNC_CNTL
, YCLK_POST_DIV
, mpll_param
.mpll_post_divider
);
1802 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1803 PHM_PlatformCaps_MemorySpreadSpectrumSupport
)) {
1805 ************************************
1806 Fref = Reference Frequency
1807 NF = Feedback divider ratio
1808 NR = Reference divider ratio
1809 Fnom = Nominal VCO output frequency = Fref * NF / NR
1811 D = Percentage down-spread / 2
1812 Fint = Reference input frequency to PFD = Fref / NR
1813 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1814 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1815 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1816 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1817 *************************************
1819 pp_atomctrl_internal_ss_info ss_info
;
1822 uint32_t reference_clock
= atomctrl_get_mpll_reference_clock(hwmgr
);
1824 /* for GDDR5 for all modes and DDR3 */
1825 if (1 == mpll_param
.qdr
)
1826 freq_nom
= memory_clock
* 4 * (1 << mpll_param
.mpll_post_divider
);
1828 freq_nom
= memory_clock
* 2 * (1 << mpll_param
.mpll_post_divider
);
1830 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1831 tmp
= (freq_nom
/ reference_clock
);
1834 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr
, freq_nom
, &ss_info
)) {
1835 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1836 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1837 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1838 /* = reference_clock * 5 / speed_spectrum_rate */
1839 uint32_t clks
= reference_clock
* 5 / ss_info
.speed_spectrum_rate
;
1841 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1842 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1844 (uint32_t)((((131 * ss_info
.speed_spectrum_percentage
*
1845 ss_info
.speed_spectrum_rate
) / 100) * tmp
) / freq_nom
);
1847 mpll_ss1
= PHM_SET_FIELD(mpll_ss1
, MPLL_SS1
, CLKV
, clkv
);
1848 mpll_ss2
= PHM_SET_FIELD(mpll_ss2
, MPLL_SS2
, CLKS
, clks
);
1852 /* MCLK_PWRMGT_CNTL setup */
1853 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1854 MCLK_PWRMGT_CNTL
, DLL_SPEED
, mpll_param
.dll_speed
);
1855 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1856 MCLK_PWRMGT_CNTL
, MRDCK0_PDNB
, dllStateOn
);
1857 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
1858 MCLK_PWRMGT_CNTL
, MRDCK1_PDNB
, dllStateOn
);
1861 /* Save the result data to outpupt memory level structure */
1862 mclk
->MclkFrequency
= memory_clock
;
1863 mclk
->MpllFuncCntl
= mpll_func_cntl
;
1864 mclk
->MpllFuncCntl_1
= mpll_func_cntl_1
;
1865 mclk
->MpllFuncCntl_2
= mpll_func_cntl_2
;
1866 mclk
->MpllAdFuncCntl
= mpll_ad_func_cntl
;
1867 mclk
->MpllDqFuncCntl
= mpll_dq_func_cntl
;
1868 mclk
->MclkPwrmgtCntl
= mclk_pwrmgt_cntl
;
1869 mclk
->DllCntl
= dll_cntl
;
1870 mclk
->MpllSs1
= mpll_ss1
;
1871 mclk
->MpllSs2
= mpll_ss2
;
1876 static int iceland_populate_single_memory_level(
1877 struct pp_hwmgr
*hwmgr
,
1878 uint32_t memory_clock
,
1879 SMU71_Discrete_MemoryLevel
*memory_level
1882 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
1885 struct cgs_display_info info
= {0};
1888 if (NULL
!= hwmgr
->dyn_state
.vddc_dependency_on_mclk
) {
1889 result
= iceland_get_dependecy_volt_by_clk(hwmgr
,
1890 hwmgr
->dyn_state
.vddc_dependency_on_mclk
, memory_clock
, &memory_level
->MinVddc
);
1891 PP_ASSERT_WITH_CODE((0 == result
),
1892 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result
);
1895 if (data
->vdd_ci_control
== ICELAND_VOLTAGE_CONTROL_NONE
) {
1896 memory_level
->MinVddci
= memory_level
->MinVddc
;
1897 } else if (NULL
!= hwmgr
->dyn_state
.vddci_dependency_on_mclk
) {
1898 result
= iceland_get_dependecy_volt_by_clk(hwmgr
,
1899 hwmgr
->dyn_state
.vddci_dependency_on_mclk
,
1901 &memory_level
->MinVddci
);
1902 PP_ASSERT_WITH_CODE((0 == result
),
1903 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result
);
1906 if (NULL
!= hwmgr
->dyn_state
.mvdd_dependency_on_mclk
) {
1907 result
= iceland_get_dependecy_volt_by_clk(hwmgr
,
1908 hwmgr
->dyn_state
.mvdd_dependency_on_mclk
, memory_clock
, &memory_level
->MinMvdd
);
1909 PP_ASSERT_WITH_CODE((0 == result
),
1910 "can not find MinMVDD voltage value from memory MVDD voltage dependency table", return result
);
1913 memory_level
->MinVddcPhases
= 1;
1915 if (data
->vddc_phase_shed_control
) {
1916 iceland_populate_phase_value_based_on_mclk(hwmgr
, hwmgr
->dyn_state
.vddc_phase_shed_limits_table
,
1917 memory_clock
, &memory_level
->MinVddcPhases
);
1920 memory_level
->EnabledForThrottle
= 1;
1921 memory_level
->EnabledForActivity
= 1;
1922 memory_level
->UpHyst
= 0;
1923 memory_level
->DownHyst
= 100;
1924 memory_level
->VoltageDownHyst
= 0;
1926 /* Indicates maximum activity level for this performance level.*/
1927 memory_level
->ActivityLevel
= (uint16_t)data
->mclk_activity_target
;
1928 memory_level
->StutterEnable
= 0;
1929 memory_level
->StrobeEnable
= 0;
1930 memory_level
->EdcReadEnable
= 0;
1931 memory_level
->EdcWriteEnable
= 0;
1932 memory_level
->RttEnable
= 0;
1934 /* default set to low watermark. Highest level will be set to high later.*/
1935 memory_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1937 cgs_get_active_displays_info(hwmgr
->device
, &info
);
1938 data
->display_timing
.num_existing_displays
= info
.display_count
;
1940 //if ((data->mclk_stutter_mode_threshold != 0) &&
1941 // (memory_clock <= data->mclk_stutter_mode_threshold) &&
1942 // (data->is_uvd_enabled == 0)
1943 // && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1944 // && (data->display_timing.num_existing_displays <= 2)
1945 // && (data->display_timing.num_existing_displays != 0))
1946 // memory_level->StutterEnable = 1;
1948 /* decide strobe mode*/
1949 memory_level
->StrobeEnable
= (data
->mclk_strobe_mode_threshold
!= 0) &&
1950 (memory_clock
<= data
->mclk_strobe_mode_threshold
);
1952 /* decide EDC mode and memory clock ratio*/
1953 if (data
->is_memory_GDDR5
) {
1954 memory_level
->StrobeRatio
= iceland_get_mclk_frequency_ratio(memory_clock
,
1955 memory_level
->StrobeEnable
);
1957 if ((data
->mclk_edc_enable_threshold
!= 0) &&
1958 (memory_clock
> data
->mclk_edc_enable_threshold
)) {
1959 memory_level
->EdcReadEnable
= 1;
1962 if ((data
->mclk_edc_wr_enable_threshold
!= 0) &&
1963 (memory_clock
> data
->mclk_edc_wr_enable_threshold
)) {
1964 memory_level
->EdcWriteEnable
= 1;
1967 if (memory_level
->StrobeEnable
) {
1968 if (iceland_get_mclk_frequency_ratio(memory_clock
, 1) >=
1969 ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC7
) >> 16) & 0xf)) {
1970 dllStateOn
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC5
) >> 1) & 0x1) ? 1 : 0;
1972 dllStateOn
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC6
) >> 1) & 0x1) ? 1 : 0;
1976 dllStateOn
= data
->dll_defaule_on
;
1979 memory_level
->StrobeRatio
=
1980 iceland_get_ddr3_mclk_frequency_ratio(memory_clock
);
1981 dllStateOn
= ((cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC5
) >> 1) & 0x1) ? 1 : 0;
1984 result
= iceland_calculate_mclk_params(hwmgr
,
1985 memory_clock
, memory_level
, memory_level
->StrobeEnable
, dllStateOn
);
1988 memory_level
->MinVddc
= PP_HOST_TO_SMC_UL(memory_level
->MinVddc
* VOLTAGE_SCALE
);
1989 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MinVddcPhases
);
1990 memory_level
->MinVddci
= PP_HOST_TO_SMC_UL(memory_level
->MinVddci
* VOLTAGE_SCALE
);
1991 memory_level
->MinMvdd
= PP_HOST_TO_SMC_UL(memory_level
->MinMvdd
* VOLTAGE_SCALE
);
1992 /* MCLK frequency in units of 10KHz*/
1993 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MclkFrequency
);
1994 /* Indicates maximum activity level for this performance level.*/
1995 CONVERT_FROM_HOST_TO_SMC_US(memory_level
->ActivityLevel
);
1996 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl
);
1997 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl_1
);
1998 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllFuncCntl_2
);
1999 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllAdFuncCntl
);
2000 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllDqFuncCntl
);
2001 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MclkPwrmgtCntl
);
2002 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->DllCntl
);
2003 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllSs1
);
2004 CONVERT_FROM_HOST_TO_SMC_UL(memory_level
->MpllSs2
);
2011 * Populates the SMC MVDD structure using the provided memory clock.
2013 * @param hwmgr the address of the hardware manager
2014 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2015 * @param voltage the SMC VOLTAGE structure to be populated
2017 int iceland_populate_mvdd_value(struct pp_hwmgr
*hwmgr
, uint32_t mclk
, SMU71_Discrete_VoltageLevel
*voltage
)
2019 const iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2022 if (ICELAND_VOLTAGE_CONTROL_NONE
!= data
->mvdd_control
) {
2023 /* find mvdd value which clock is more than request */
2024 for (i
= 0; i
< hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->count
; i
++) {
2025 if (mclk
<= hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->entries
[i
].clk
) {
2026 /* Always round to higher voltage. */
2027 voltage
->Voltage
= data
->mvdd_voltage_table
.entries
[i
].value
;
2032 PP_ASSERT_WITH_CODE(i
< hwmgr
->dyn_state
.mvdd_dependency_on_mclk
->count
,
2033 "MVDD Voltage is outside the supported range.", return -1);
2043 static int iceland_populate_smc_acpi_level(struct pp_hwmgr
*hwmgr
,
2044 SMU71_Discrete_DpmTable
*table
)
2047 const iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2048 pp_atomctrl_clock_dividers_vi dividers
;
2049 SMU71_Discrete_VoltageLevel voltage_level
;
2050 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
2051 uint32_t spll_func_cntl_2
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
;
2052 uint32_t dll_cntl
= data
->clock_registers
.vDLL_CNTL
;
2053 uint32_t mclk_pwrmgt_cntl
= data
->clock_registers
.vMCLK_PWRMGT_CNTL
;
2055 /* The ACPI state should not do DPM on DC (or ever).*/
2056 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
2058 if (data
->acpi_vddc
)
2059 table
->ACPILevel
.MinVddc
= PP_HOST_TO_SMC_UL(data
->acpi_vddc
* VOLTAGE_SCALE
);
2061 table
->ACPILevel
.MinVddc
= PP_HOST_TO_SMC_UL(data
->min_vddc_in_pp_table
* VOLTAGE_SCALE
);
2063 table
->ACPILevel
.MinVddcPhases
= (data
->vddc_phase_shed_control
) ? 0 : 1;
2065 /* assign zero for now*/
2066 table
->ACPILevel
.SclkFrequency
= atomctrl_get_reference_clock(hwmgr
);
2068 /* get the engine clock dividers for this clock value*/
2069 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
,
2070 table
->ACPILevel
.SclkFrequency
, ÷rs
);
2072 PP_ASSERT_WITH_CODE(result
== 0,
2073 "Error retrieving Engine Clock dividers from VBIOS.", return result
);
2075 /* divider ID for required SCLK*/
2076 table
->ACPILevel
.SclkDid
= (uint8_t)dividers
.pll_post_divider
;
2077 table
->ACPILevel
.DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2078 table
->ACPILevel
.DeepSleepDivId
= 0;
2080 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
2081 CG_SPLL_FUNC_CNTL
, SPLL_PWRON
, 0);
2082 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
2083 CG_SPLL_FUNC_CNTL
, SPLL_RESET
, 1);
2084 spll_func_cntl_2
= PHM_SET_FIELD(spll_func_cntl_2
,
2085 CG_SPLL_FUNC_CNTL_2
, SCLK_MUX_SEL
, 4);
2087 table
->ACPILevel
.CgSpllFuncCntl
= spll_func_cntl
;
2088 table
->ACPILevel
.CgSpllFuncCntl2
= spll_func_cntl_2
;
2089 table
->ACPILevel
.CgSpllFuncCntl3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
2090 table
->ACPILevel
.CgSpllFuncCntl4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
2091 table
->ACPILevel
.SpllSpreadSpectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
2092 table
->ACPILevel
.SpllSpreadSpectrum2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
2093 table
->ACPILevel
.CcPwrDynRm
= 0;
2094 table
->ACPILevel
.CcPwrDynRm1
= 0;
2097 /* For various features to be enabled/disabled while this level is active.*/
2098 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.Flags
);
2099 /* SCLK frequency in units of 10KHz*/
2100 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SclkFrequency
);
2101 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl
);
2102 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl2
);
2103 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl3
);
2104 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl4
);
2105 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum
);
2106 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum2
);
2107 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm
);
2108 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm1
);
2110 table
->MemoryACPILevel
.MinVddc
= table
->ACPILevel
.MinVddc
;
2111 table
->MemoryACPILevel
.MinVddcPhases
= table
->ACPILevel
.MinVddcPhases
;
2113 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2115 if (0 == iceland_populate_mvdd_value(hwmgr
, 0, &voltage_level
))
2116 table
->MemoryACPILevel
.MinMvdd
=
2117 PP_HOST_TO_SMC_UL(voltage_level
.Voltage
* VOLTAGE_SCALE
);
2119 table
->MemoryACPILevel
.MinMvdd
= 0;
2121 /* Force reset on DLL*/
2122 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
2123 MCLK_PWRMGT_CNTL
, MRDCK0_RESET
, 0x1);
2124 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
2125 MCLK_PWRMGT_CNTL
, MRDCK1_RESET
, 0x1);
2127 /* Disable DLL in ACPIState*/
2128 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
2129 MCLK_PWRMGT_CNTL
, MRDCK0_PDNB
, 0);
2130 mclk_pwrmgt_cntl
= PHM_SET_FIELD(mclk_pwrmgt_cntl
,
2131 MCLK_PWRMGT_CNTL
, MRDCK1_PDNB
, 0);
2133 /* Enable DLL bypass signal*/
2134 dll_cntl
= PHM_SET_FIELD(dll_cntl
,
2135 DLL_CNTL
, MRDCK0_BYPASS
, 0);
2136 dll_cntl
= PHM_SET_FIELD(dll_cntl
,
2137 DLL_CNTL
, MRDCK1_BYPASS
, 0);
2139 table
->MemoryACPILevel
.DllCntl
=
2140 PP_HOST_TO_SMC_UL(dll_cntl
);
2141 table
->MemoryACPILevel
.MclkPwrmgtCntl
=
2142 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl
);
2143 table
->MemoryACPILevel
.MpllAdFuncCntl
=
2144 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_AD_FUNC_CNTL
);
2145 table
->MemoryACPILevel
.MpllDqFuncCntl
=
2146 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_DQ_FUNC_CNTL
);
2147 table
->MemoryACPILevel
.MpllFuncCntl
=
2148 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL
);
2149 table
->MemoryACPILevel
.MpllFuncCntl_1
=
2150 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL_1
);
2151 table
->MemoryACPILevel
.MpllFuncCntl_2
=
2152 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_FUNC_CNTL_2
);
2153 table
->MemoryACPILevel
.MpllSs1
=
2154 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_SS1
);
2155 table
->MemoryACPILevel
.MpllSs2
=
2156 PP_HOST_TO_SMC_UL(data
->clock_registers
.vMPLL_SS2
);
2158 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
2159 table
->MemoryACPILevel
.EnabledForActivity
= 0;
2160 table
->MemoryACPILevel
.UpHyst
= 0;
2161 table
->MemoryACPILevel
.DownHyst
= 100;
2162 table
->MemoryACPILevel
.VoltageDownHyst
= 0;
2163 /* Indicates maximum activity level for this performance level.*/
2164 table
->MemoryACPILevel
.ActivityLevel
= PP_HOST_TO_SMC_US((uint16_t)data
->mclk_activity_target
);
2166 table
->MemoryACPILevel
.StutterEnable
= 0;
2167 table
->MemoryACPILevel
.StrobeEnable
= 0;
2168 table
->MemoryACPILevel
.EdcReadEnable
= 0;
2169 table
->MemoryACPILevel
.EdcWriteEnable
= 0;
2170 table
->MemoryACPILevel
.RttEnable
= 0;
2175 static int iceland_find_boot_level(struct iceland_single_dpm_table
*table
, uint32_t value
, uint32_t *boot_level
)
2180 for (i
= 0; i
< table
->count
; i
++) {
2181 if (value
== table
->dpm_levels
[i
].value
) {
2190 * Calculates the SCLK dividers using the provided engine clock
2192 * @param hwmgr the address of the hardware manager
2193 * @param engine_clock the engine clock to use to populate the structure
2194 * @param sclk the SMC SCLK structure to be populated
2196 int iceland_calculate_sclk_params(struct pp_hwmgr
*hwmgr
,
2197 uint32_t engine_clock
, SMU71_Discrete_GraphicsLevel
*sclk
)
2199 const iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2200 pp_atomctrl_clock_dividers_vi dividers
;
2201 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
2202 uint32_t spll_func_cntl_3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
2203 uint32_t spll_func_cntl_4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
2204 uint32_t cg_spll_spread_spectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
2205 uint32_t cg_spll_spread_spectrum_2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
2206 uint32_t reference_clock
;
2207 uint32_t reference_divider
;
2211 /* get the engine clock dividers for this clock value*/
2212 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
, engine_clock
, ÷rs
);
2214 PP_ASSERT_WITH_CODE(result
== 0,
2215 "Error retrieving Engine Clock dividers from VBIOS.", return result
);
2217 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2218 reference_clock
= atomctrl_get_reference_clock(hwmgr
);
2220 reference_divider
= 1 + dividers
.uc_pll_ref_div
;
2222 /* low 14 bits is fraction and high 12 bits is divider*/
2223 fbdiv
= dividers
.ul_fb_div
.ul_fb_divider
& 0x3FFFFFF;
2225 /* SPLL_FUNC_CNTL setup*/
2226 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
2227 CG_SPLL_FUNC_CNTL
, SPLL_REF_DIV
, dividers
.uc_pll_ref_div
);
2228 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
,
2229 CG_SPLL_FUNC_CNTL
, SPLL_PDIV_A
, dividers
.uc_pll_post_div
);
2231 /* SPLL_FUNC_CNTL_3 setup*/
2232 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
,
2233 CG_SPLL_FUNC_CNTL_3
, SPLL_FB_DIV
, fbdiv
);
2235 /* set to use fractional accumulation*/
2236 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
,
2237 CG_SPLL_FUNC_CNTL_3
, SPLL_DITHEN
, 1);
2239 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2240 PHM_PlatformCaps_EngineSpreadSpectrumSupport
)) {
2241 pp_atomctrl_internal_ss_info ss_info
;
2243 uint32_t vcoFreq
= engine_clock
* dividers
.uc_pll_post_div
;
2244 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr
, vcoFreq
, &ss_info
)) {
2246 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2247 * ss_info.speed_spectrum_rate -- in unit of khz
2249 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2250 uint32_t clkS
= reference_clock
* 5 / (reference_divider
* ss_info
.speed_spectrum_rate
);
2252 /* clkv = 2 * D * fbdiv / NS */
2253 uint32_t clkV
= 4 * ss_info
.speed_spectrum_percentage
* fbdiv
/ (clkS
* 10000);
2255 cg_spll_spread_spectrum
=
2256 PHM_SET_FIELD(cg_spll_spread_spectrum
, CG_SPLL_SPREAD_SPECTRUM
, CLKS
, clkS
);
2257 cg_spll_spread_spectrum
=
2258 PHM_SET_FIELD(cg_spll_spread_spectrum
, CG_SPLL_SPREAD_SPECTRUM
, SSEN
, 1);
2259 cg_spll_spread_spectrum_2
=
2260 PHM_SET_FIELD(cg_spll_spread_spectrum_2
, CG_SPLL_SPREAD_SPECTRUM_2
, CLKV
, clkV
);
2264 sclk
->SclkFrequency
= engine_clock
;
2265 sclk
->CgSpllFuncCntl3
= spll_func_cntl_3
;
2266 sclk
->CgSpllFuncCntl4
= spll_func_cntl_4
;
2267 sclk
->SpllSpreadSpectrum
= cg_spll_spread_spectrum
;
2268 sclk
->SpllSpreadSpectrum2
= cg_spll_spread_spectrum_2
;
2269 sclk
->SclkDid
= (uint8_t)dividers
.pll_post_divider
;
2274 static uint8_t iceland_get_sleep_divider_id_from_clock(struct pp_hwmgr
*hwmgr
,
2275 uint32_t engine_clock
, uint32_t min_engine_clock_in_sr
)
2278 uint32_t min
= (min_engine_clock_in_sr
> ICELAND_MINIMUM_ENGINE_CLOCK
) ?
2279 min_engine_clock_in_sr
: ICELAND_MINIMUM_ENGINE_CLOCK
;
2281 PP_ASSERT_WITH_CODE((engine_clock
>= min
),
2282 "Engine clock can't satisfy stutter requirement!", return 0);
2284 for (i
= ICELAND_MAX_DEEPSLEEP_DIVIDER_ID
;; i
--) {
2285 temp
= engine_clock
/ (1 << i
);
2287 if(temp
>= min
|| i
== 0)
2294 * Populates single SMC SCLK structure using the provided engine clock
2296 * @param hwmgr the address of the hardware manager
2297 * @param engine_clock the engine clock to use to populate the structure
2298 * @param sclk the SMC SCLK structure to be populated
2300 static int iceland_populate_single_graphic_level(struct pp_hwmgr
*hwmgr
,
2301 uint32_t engine_clock
, uint16_t sclk_activity_level_threshold
,
2302 SMU71_Discrete_GraphicsLevel
*graphic_level
)
2306 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2308 result
= iceland_calculate_sclk_params(hwmgr
, engine_clock
, graphic_level
);
2311 /* populate graphics levels*/
2312 result
= iceland_get_dependecy_volt_by_clk(hwmgr
,
2313 hwmgr
->dyn_state
.vddc_dependency_on_sclk
, engine_clock
, &graphic_level
->MinVddc
);
2314 PP_ASSERT_WITH_CODE((0 == result
),
2315 "can not find VDDC voltage value for VDDC engine clock dependency table", return result
);
2317 /* SCLK frequency in units of 10KHz*/
2318 graphic_level
->SclkFrequency
= engine_clock
;
2321 * Minimum VDDC phases required to support this level, it
2322 * should get from dependence table.
2324 graphic_level
->MinVddcPhases
= 1;
2326 if (data
->vddc_phase_shed_control
) {
2327 iceland_populate_phase_value_based_on_sclk(hwmgr
,
2328 hwmgr
->dyn_state
.vddc_phase_shed_limits_table
,
2330 &graphic_level
->MinVddcPhases
);
2333 /* Indicates maximum activity level for this performance level. 50% for now*/
2334 graphic_level
->ActivityLevel
= sclk_activity_level_threshold
;
2336 graphic_level
->CcPwrDynRm
= 0;
2337 graphic_level
->CcPwrDynRm1
= 0;
2338 /* this level can be used if activity is high enough.*/
2339 graphic_level
->EnabledForActivity
= 1;
2340 /* this level can be used for throttling.*/
2341 graphic_level
->EnabledForThrottle
= 1;
2342 graphic_level
->UpHyst
= 0;
2343 graphic_level
->DownHyst
= 100;
2344 graphic_level
->VoltageDownHyst
= 0;
2345 graphic_level
->PowerThrottle
= 0;
2347 threshold
= engine_clock
* data
->fast_watermark_threshold
/ 100;
2349 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2350 PHM_PlatformCaps_SclkDeepSleep
)) {
2351 graphic_level
->DeepSleepDivId
=
2352 iceland_get_sleep_divider_id_from_clock(hwmgr
, engine_clock
,
2353 data
->display_timing
.min_clock_insr
);
2356 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2357 graphic_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2360 graphic_level
->MinVddc
= PP_HOST_TO_SMC_UL(graphic_level
->MinVddc
* VOLTAGE_SCALE
);
2361 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2362 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->MinVddcPhases
);
2363 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SclkFrequency
);
2364 CONVERT_FROM_HOST_TO_SMC_US(graphic_level
->ActivityLevel
);
2365 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CgSpllFuncCntl3
);
2366 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CgSpllFuncCntl4
);
2367 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SpllSpreadSpectrum
);
2368 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->SpllSpreadSpectrum2
);
2369 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CcPwrDynRm
);
2370 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level
->CcPwrDynRm1
);
2377 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2379 * @param hwmgr the address of the hardware manager
2381 static int iceland_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
2383 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2384 struct iceland_dpm_table
*dpm_table
= &data
->dpm_table
;
2386 uint32_t level_array_adress
= data
->dpm_table_start
+
2387 offsetof(SMU71_Discrete_DpmTable
, GraphicsLevel
);
2389 uint32_t level_array_size
= sizeof(SMU71_Discrete_GraphicsLevel
) * SMU71_MAX_LEVELS_GRAPHICS
;
2390 SMU71_Discrete_GraphicsLevel
*levels
= data
->smc_state_table
.GraphicsLevel
;
2392 uint8_t highest_pcie_level_enabled
= 0, lowest_pcie_level_enabled
= 0, mid_pcie_level_enabled
= 0, count
= 0;
2393 memset(levels
, 0x00, level_array_size
);
2395 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
2396 result
= iceland_populate_single_graphic_level(hwmgr
,
2397 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
2398 (uint16_t)data
->activity_target
[i
],
2399 &(data
->smc_state_table
.GraphicsLevel
[i
]));
2403 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2405 data
->smc_state_table
.GraphicsLevel
[i
].DeepSleepDivId
= 0;
2408 /* set highest level watermark to high */
2409 if (dpm_table
->sclk_table
.count
> 1)
2410 data
->smc_state_table
.GraphicsLevel
[dpm_table
->sclk_table
.count
-1].DisplayWatermark
=
2411 PPSMC_DISPLAY_WATERMARK_HIGH
;
2413 data
->smc_state_table
.GraphicsDpmLevelCount
=
2414 (uint8_t)dpm_table
->sclk_table
.count
;
2415 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
2416 iceland_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
2418 while ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2419 (1 << (highest_pcie_level_enabled
+ 1))) != 0) {
2420 highest_pcie_level_enabled
++;
2423 while ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2424 (1 << lowest_pcie_level_enabled
)) == 0) {
2425 lowest_pcie_level_enabled
++;
2428 while ((count
< highest_pcie_level_enabled
) &&
2429 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2430 (1 << (lowest_pcie_level_enabled
+ 1 + count
))) == 0)) {
2434 mid_pcie_level_enabled
= (lowest_pcie_level_enabled
+1+count
) < highest_pcie_level_enabled
?
2435 (lowest_pcie_level_enabled
+ 1 + count
) : highest_pcie_level_enabled
;
2437 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2438 for (i
= 2; i
< dpm_table
->sclk_table
.count
; i
++) {
2439 data
->smc_state_table
.GraphicsLevel
[i
].pcieDpmLevel
= highest_pcie_level_enabled
;
2442 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2443 data
->smc_state_table
.GraphicsLevel
[0].pcieDpmLevel
= lowest_pcie_level_enabled
;
2445 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2446 data
->smc_state_table
.GraphicsLevel
[1].pcieDpmLevel
= mid_pcie_level_enabled
;
2448 /* level count will send to smc once at init smc table and never change*/
2449 result
= iceland_copy_bytes_to_smc(hwmgr
->smumgr
, level_array_adress
, (uint8_t *)levels
, (uint32_t)level_array_size
, data
->sram_end
);
2458 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2460 * @param hwmgr the address of the hardware manager
2463 static int iceland_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
2465 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2466 struct iceland_dpm_table
*dpm_table
= &data
->dpm_table
;
2468 /* populate MCLK dpm table to SMU7 */
2469 uint32_t level_array_adress
= data
->dpm_table_start
+ offsetof(SMU71_Discrete_DpmTable
, MemoryLevel
);
2470 uint32_t level_array_size
= sizeof(SMU71_Discrete_MemoryLevel
) * SMU71_MAX_LEVELS_MEMORY
;
2471 SMU71_Discrete_MemoryLevel
*levels
= data
->smc_state_table
.MemoryLevel
;
2474 memset(levels
, 0x00, level_array_size
);
2476 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
2477 PP_ASSERT_WITH_CODE((0 != dpm_table
->mclk_table
.dpm_levels
[i
].value
),
2478 "can not populate memory level as memory clock is zero", return -1);
2479 result
= iceland_populate_single_memory_level(hwmgr
, dpm_table
->mclk_table
.dpm_levels
[i
].value
,
2480 &(data
->smc_state_table
.MemoryLevel
[i
]));
2486 /* Only enable level 0 for now.*/
2487 data
->smc_state_table
.MemoryLevel
[0].EnabledForActivity
= 1;
2490 * in order to prevent MC activity from stutter mode to push DPM up.
2491 * the UVD change complements this by putting the MCLK in a higher state
2492 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2494 data
->smc_state_table
.MemoryLevel
[0].ActivityLevel
= 0x1F;
2495 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.MemoryLevel
[0].ActivityLevel
);
2497 data
->smc_state_table
.MemoryDpmLevelCount
= (uint8_t)dpm_table
->mclk_table
.count
;
2498 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
= iceland_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
2499 /* set highest level watermark to high*/
2500 data
->smc_state_table
.MemoryLevel
[dpm_table
->mclk_table
.count
-1].DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_HIGH
;
2502 /* level count will send to smc once at init smc table and never change*/
2503 result
= iceland_copy_bytes_to_smc(hwmgr
->smumgr
,
2504 level_array_adress
, (uint8_t *)levels
, (uint32_t)level_array_size
, data
->sram_end
);
2513 struct ICELAND_DLL_SPEED_SETTING
2515 uint16_t Min
; /* Minimum Data Rate*/
2516 uint16_t Max
; /* Maximum Data Rate*/
2517 uint32_t dll_speed
; /* The desired DLL_SPEED setting*/
2520 static int iceland_populate_ulv_level(struct pp_hwmgr
*hwmgr
, SMU71_Discrete_Ulv
*pstate
)
2523 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2524 uint32_t voltage_response_time
, ulv_voltage
;
2526 pstate
->CcPwrDynRm
= 0;
2527 pstate
->CcPwrDynRm1
= 0;
2529 //backbiasResponseTime is use for ULV state voltage value.
2530 result
= pp_tables_get_response_times(hwmgr
, &voltage_response_time
, &ulv_voltage
);
2531 PP_ASSERT_WITH_CODE((0 == result
), "can not get ULV voltage value", return result
;);
2534 data
->ulv
.ulv_supported
= false;
2538 if (ICELAND_VOLTAGE_CONTROL_BY_SVID2
!= data
->voltage_control
) {
2539 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
2540 if (ulv_voltage
> hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
) {
2541 pstate
->VddcOffset
= 0;
2544 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
2545 pstate
->VddcOffset
= (uint16_t)(hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
- ulv_voltage
);
2548 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
2549 if(ulv_voltage
> hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
) {
2550 pstate
->VddcOffsetVid
= 0;
2552 /* used in SVI2 Mode */
2553 pstate
->VddcOffsetVid
= (uint8_t)((hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].v
- ulv_voltage
) * VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
2557 /* used in SVI2 Mode to shed phase */
2558 pstate
->VddcPhase
= (data
->vddc_phase_shed_control
) ? 0 : 1;
2561 CONVERT_FROM_HOST_TO_SMC_UL(pstate
->CcPwrDynRm
);
2562 CONVERT_FROM_HOST_TO_SMC_UL(pstate
->CcPwrDynRm1
);
2563 CONVERT_FROM_HOST_TO_SMC_US(pstate
->VddcOffset
);
2569 static int iceland_populate_ulv_state(struct pp_hwmgr
*hwmgr
, SMU71_Discrete_Ulv
*ulv
)
2571 return iceland_populate_ulv_level(hwmgr
, ulv
);
2574 static int iceland_populate_smc_initial_state(struct pp_hwmgr
*hwmgr
)
2576 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2577 uint8_t count
, level
;
2579 count
= (uint8_t)(hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
);
2581 for (level
= 0; level
< count
; level
++) {
2582 if (hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[level
].clk
2583 >= data
->vbios_boot_state
.sclk_bootup_value
) {
2584 data
->smc_state_table
.GraphicsBootLevel
= level
;
2589 count
= (uint8_t)(hwmgr
->dyn_state
.vddc_dependency_on_mclk
->count
);
2591 for (level
= 0; level
< count
; level
++) {
2592 if (hwmgr
->dyn_state
.vddc_dependency_on_mclk
->entries
[level
].clk
2593 >= data
->vbios_boot_state
.mclk_bootup_value
) {
2594 data
->smc_state_table
.MemoryBootLevel
= level
;
2603 * Initializes the SMC table and uploads it
2605 * @param hwmgr the address of the powerplay hardware manager.
2606 * @param pInput the pointer to input data (PowerState)
2609 int iceland_init_smc_table(struct pp_hwmgr
*hwmgr
)
2612 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2613 SMU71_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
2614 const struct phw_iceland_ulv_parm
*ulv
= &(data
->ulv
);
2616 result
= iceland_setup_default_dpm_tables(hwmgr
);
2617 PP_ASSERT_WITH_CODE(0 == result
,
2618 "Failed to setup default DPM tables!", return result
;);
2619 memset(&(data
->smc_state_table
), 0x00, sizeof(data
->smc_state_table
));
2621 if (ICELAND_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
) {
2622 iceland_populate_smc_voltage_tables(hwmgr
, table
);
2625 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2626 PHM_PlatformCaps_AutomaticDCTransition
)) {
2627 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
2630 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2631 PHM_PlatformCaps_StepVddc
)) {
2632 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
2635 if (data
->is_memory_GDDR5
) {
2636 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
2639 if (ulv
->ulv_supported
) {
2640 result
= iceland_populate_ulv_state(hwmgr
, &data
->ulv_setting
);
2641 PP_ASSERT_WITH_CODE(0 == result
,
2642 "Failed to initialize ULV state!", return result
;);
2644 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2645 ixCG_ULV_PARAMETER
, ulv
->ch_ulv_parameter
);
2648 result
= iceland_populate_smc_link_level(hwmgr
, table
);
2649 PP_ASSERT_WITH_CODE(0 == result
,
2650 "Failed to initialize Link Level!", return result
;);
2652 result
= iceland_populate_all_graphic_levels(hwmgr
);
2653 PP_ASSERT_WITH_CODE(0 == result
,
2654 "Failed to initialize Graphics Level!", return result
;);
2656 result
= iceland_populate_all_memory_levels(hwmgr
);
2657 PP_ASSERT_WITH_CODE(0 == result
,
2658 "Failed to initialize Memory Level!", return result
;);
2660 result
= iceland_populate_smc_acpi_level(hwmgr
, table
);
2661 PP_ASSERT_WITH_CODE(0 == result
,
2662 "Failed to initialize ACPI Level!", return result
;);
2664 result
= iceland_populate_smc_vce_level(hwmgr
, table
);
2665 PP_ASSERT_WITH_CODE(0 == result
,
2666 "Failed to initialize VCE Level!", return result
;);
2668 result
= iceland_populate_smc_acp_level(hwmgr
, table
);
2669 PP_ASSERT_WITH_CODE(0 == result
,
2670 "Failed to initialize ACP Level!", return result
;);
2672 result
= iceland_populate_smc_samu_level(hwmgr
, table
);
2673 PP_ASSERT_WITH_CODE(0 == result
,
2674 "Failed to initialize SAMU Level!", return result
;);
2677 * Since only the initial state is completely set up at this
2678 * point (the other states are just copies of the boot state)
2679 * we only need to populate the ARB settings for the initial
2682 result
= iceland_program_memory_timing_parameters(hwmgr
);
2683 PP_ASSERT_WITH_CODE(0 == result
,
2684 "Failed to Write ARB settings for the initial state.", return result
;);
2686 result
= iceland_populate_smc_uvd_level(hwmgr
, table
);
2687 PP_ASSERT_WITH_CODE(0 == result
,
2688 "Failed to initialize UVD Level!", return result
;);
2690 table
->GraphicsBootLevel
= 0;
2691 table
->MemoryBootLevel
= 0;
2693 /* find boot level from dpm table */
2694 result
= iceland_find_boot_level(&(data
->dpm_table
.sclk_table
),
2695 data
->vbios_boot_state
.sclk_bootup_value
,
2696 (uint32_t *)&(data
->smc_state_table
.GraphicsBootLevel
));
2699 pr_warning("VBIOS did not find boot engine clock value in dependency table.\n");
2701 result
= iceland_find_boot_level(&(data
->dpm_table
.mclk_table
),
2702 data
->vbios_boot_state
.mclk_bootup_value
,
2703 (uint32_t *)&(data
->smc_state_table
.MemoryBootLevel
));
2706 pr_warning("VBIOS did not find boot memory clock value in dependency table.\n");
2708 table
->BootVddc
= data
->vbios_boot_state
.vddc_bootup_value
;
2709 if (ICELAND_VOLTAGE_CONTROL_NONE
== data
->vdd_ci_control
) {
2710 table
->BootVddci
= table
->BootVddc
;
2713 table
->BootVddci
= data
->vbios_boot_state
.vddci_bootup_value
;
2715 table
->BootMVdd
= data
->vbios_boot_state
.mvdd_bootup_value
;
2717 result
= iceland_populate_smc_initial_state(hwmgr
);
2718 PP_ASSERT_WITH_CODE(0 == result
, "Failed to initialize Boot State!", return result
);
2720 result
= iceland_populate_bapm_parameters_in_dpm_table(hwmgr
);
2721 PP_ASSERT_WITH_CODE(0 == result
, "Failed to populate BAPM Parameters!", return result
);
2723 table
->GraphicsVoltageChangeEnable
= 1;
2724 table
->GraphicsThermThrottleEnable
= 1;
2725 table
->GraphicsInterval
= 1;
2726 table
->VoltageInterval
= 1;
2727 table
->ThermalInterval
= 1;
2728 table
->TemperatureLimitHigh
=
2729 (data
->thermal_temp_setting
.temperature_high
*
2730 ICELAND_Q88_FORMAT_CONVERSION_UNIT
) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES
;
2731 table
->TemperatureLimitLow
=
2732 (data
->thermal_temp_setting
.temperature_low
*
2733 ICELAND_Q88_FORMAT_CONVERSION_UNIT
) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES
;
2734 table
->MemoryVoltageChangeEnable
= 1;
2735 table
->MemoryInterval
= 1;
2736 table
->VoltageResponseTime
= 0;
2737 table
->PhaseResponseTime
= 0;
2738 table
->MemoryThermThrottleEnable
= 1;
2739 table
->PCIeBootLinkLevel
= 0;
2740 table
->PCIeGenInterval
= 1;
2742 result
= iceland_populate_smc_svi2_config(hwmgr
, table
);
2743 PP_ASSERT_WITH_CODE(0 == result
,
2744 "Failed to populate SVI2 setting!", return result
);
2746 table
->ThermGpio
= 17;
2747 table
->SclkStepSize
= 0x4000;
2749 CONVERT_FROM_HOST_TO_SMC_UL(table
->SystemFlags
);
2750 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddcVid
);
2751 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddcPhase
);
2752 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskVddciVid
);
2753 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMaskMvddVid
);
2754 CONVERT_FROM_HOST_TO_SMC_UL(table
->SclkStepSize
);
2755 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitHigh
);
2756 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitLow
);
2757 CONVERT_FROM_HOST_TO_SMC_US(table
->VoltageResponseTime
);
2758 CONVERT_FROM_HOST_TO_SMC_US(table
->PhaseResponseTime
);
2760 table
->BootVddc
= PP_HOST_TO_SMC_US(table
->BootVddc
* VOLTAGE_SCALE
);
2761 table
->BootVddci
= PP_HOST_TO_SMC_US(table
->BootVddci
* VOLTAGE_SCALE
);
2762 table
->BootMVdd
= PP_HOST_TO_SMC_US(table
->BootMVdd
* VOLTAGE_SCALE
);
2764 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2765 result
= iceland_copy_bytes_to_smc(hwmgr
->smumgr
, data
->dpm_table_start
+
2766 offsetof(SMU71_Discrete_DpmTable
, SystemFlags
),
2767 (uint8_t *)&(table
->SystemFlags
),
2768 sizeof(SMU71_Discrete_DpmTable
) - 3 * sizeof(SMU71_PIDController
),
2771 PP_ASSERT_WITH_CODE(0 == result
,
2772 "Failed to upload dpm data to SMC memory!", return result
);
2774 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2775 result
= iceland_copy_bytes_to_smc(hwmgr
->smumgr
,
2776 data
->ulv_settings_start
,
2777 (uint8_t *)&(data
->ulv_setting
),
2778 sizeof(SMU71_Discrete_Ulv
),
2782 /* Notify SMC to follow new GPIO scheme */
2783 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2784 PHM_PlatformCaps_AutomaticDCTransition
)) {
2785 if (0 == iceland_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_UseNewGPIOScheme
))
2786 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2787 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme
);
2794 int iceland_populate_mc_reg_address(struct pp_hwmgr
*hwmgr
, SMU71_Discrete_MCRegisters
*mc_reg_table
)
2796 const struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
2800 for (i
= 0, j
= 0; j
< data
->iceland_mc_reg_table
.last
; j
++) {
2801 if (data
->iceland_mc_reg_table
.validflag
& 1<<j
) {
2802 PP_ASSERT_WITH_CODE(i
< SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE
,
2803 "Index of mc_reg_table->address[] array out of boundary", return -1);
2804 mc_reg_table
->address
[i
].s0
=
2805 PP_HOST_TO_SMC_US(data
->iceland_mc_reg_table
.mc_reg_address
[j
].s0
);
2806 mc_reg_table
->address
[i
].s1
=
2807 PP_HOST_TO_SMC_US(data
->iceland_mc_reg_table
.mc_reg_address
[j
].s1
);
2812 mc_reg_table
->last
= (uint8_t)i
;
2817 /* convert register values from driver to SMC format */
2818 void iceland_convert_mc_registers(
2819 const phw_iceland_mc_reg_entry
* pEntry
,
2820 SMU71_Discrete_MCRegisterSet
*pData
,
2821 uint32_t numEntries
, uint32_t validflag
)
2825 for (i
= 0, j
= 0; j
< numEntries
; j
++) {
2826 if (validflag
& 1<<j
) {
2827 pData
->value
[i
] = PP_HOST_TO_SMC_UL(pEntry
->mc_data
[j
]);
2833 /* find the entry in the memory range table, then populate the value to SMC's iceland_mc_reg_table */
2834 int iceland_convert_mc_reg_table_entry_to_smc(
2835 struct pp_hwmgr
*hwmgr
,
2836 const uint32_t memory_clock
,
2837 SMU71_Discrete_MCRegisterSet
*mc_reg_table_data
2840 const iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
2843 for (i
= 0; i
< data
->iceland_mc_reg_table
.num_entries
; i
++) {
2845 data
->iceland_mc_reg_table
.mc_reg_table_entry
[i
].mclk_max
) {
2850 if ((i
== data
->iceland_mc_reg_table
.num_entries
) && (i
> 0))
2853 iceland_convert_mc_registers(&data
->iceland_mc_reg_table
.mc_reg_table_entry
[i
],
2854 mc_reg_table_data
, data
->iceland_mc_reg_table
.last
, data
->iceland_mc_reg_table
.validflag
);
2859 int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr
*hwmgr
,
2860 SMU71_Discrete_MCRegisters
*mc_reg_table
)
2863 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
2867 for (i
= 0; i
< data
->dpm_table
.mclk_table
.count
; i
++) {
2868 res
= iceland_convert_mc_reg_table_entry_to_smc(
2870 data
->dpm_table
.mclk_table
.dpm_levels
[i
].value
,
2871 &mc_reg_table
->data
[i
]
2881 int iceland_populate_initial_mc_reg_table(struct pp_hwmgr
*hwmgr
)
2884 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
2886 memset(&data
->mc_reg_table
, 0x00, sizeof(SMU71_Discrete_MCRegisters
));
2887 result
= iceland_populate_mc_reg_address(hwmgr
, &(data
->mc_reg_table
));
2888 PP_ASSERT_WITH_CODE(0 == result
,
2889 "Failed to initialize MCRegTable for the MC register addresses!", return result
;);
2891 result
= iceland_convert_mc_reg_table_to_smc(hwmgr
, &data
->mc_reg_table
);
2892 PP_ASSERT_WITH_CODE(0 == result
,
2893 "Failed to initialize MCRegTable for driver state!", return result
;);
2895 return iceland_copy_bytes_to_smc(hwmgr
->smumgr
, data
->mc_reg_table_start
,
2896 (uint8_t *)&data
->mc_reg_table
, sizeof(SMU71_Discrete_MCRegisters
), data
->sram_end
);
2899 int iceland_notify_smc_display_change(struct pp_hwmgr
*hwmgr
, bool has_display
)
2901 PPSMC_Msg msg
= has_display
? (PPSMC_Msg
)PPSMC_HasDisplay
: (PPSMC_Msg
)PPSMC_NoDisplay
;
2903 return (smum_send_msg_to_smc(hwmgr
->smumgr
, msg
) == 0) ? 0 : -1;
2906 int iceland_enable_sclk_control(struct pp_hwmgr
*hwmgr
)
2908 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
, SCLK_PWRMGT_OFF
, 0);
2913 int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
2915 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2917 /* enable SCLK dpm */
2918 if (0 == data
->sclk_dpm_key_disabled
) {
2919 PP_ASSERT_WITH_CODE(
2920 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2921 PPSMC_MSG_DPM_Enable
)),
2922 "Failed to enable SCLK DPM during DPM Start Function!",
2926 /* enable MCLK dpm */
2927 if (0 == data
->mclk_dpm_key_disabled
) {
2928 PP_ASSERT_WITH_CODE(
2929 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2930 PPSMC_MSG_MCLKDPM_Enable
)),
2931 "Failed to enable MCLK DPM during DPM Start Function!",
2934 PHM_WRITE_FIELD(hwmgr
->device
, MC_SEQ_CNTL_3
, CAC_EN
, 0x1);
2936 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2937 ixLCAC_MC0_CNTL
, 0x05);/* CH0,1 read */
2938 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2939 ixLCAC_MC1_CNTL
, 0x05);/* CH2,3 read */
2940 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2941 ixLCAC_CPL_CNTL
, 0x100005);/*Read */
2945 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2946 ixLCAC_MC0_CNTL
, 0x400005);/* CH0,1 write */
2947 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2948 ixLCAC_MC1_CNTL
, 0x400005);/* CH2,3 write */
2949 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2950 ixLCAC_CPL_CNTL
, 0x500005);/* write */
2957 int iceland_start_dpm(struct pp_hwmgr
*hwmgr
)
2959 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
2961 /* enable general power management */
2962 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
, GLOBAL_PWRMGT_EN
, 1);
2963 /* enable sclk deep sleep */
2964 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
, DYNAMIC_PM_EN
, 1);
2966 /* prepare for PCIE DPM */
2967 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SOFT_REGISTERS_TABLE_12
, VoltageChangeTimeout
, 0x1000);
2969 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
, SWRST_COMMAND_1
, RESETLC
, 0x0);
2971 PP_ASSERT_WITH_CODE(
2972 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2973 PPSMC_MSG_Voltage_Cntl_Enable
)),
2974 "Failed to enable voltage DPM during DPM Start Function!",
2977 if (0 != iceland_enable_sclk_mclk_dpm(hwmgr
)) {
2978 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
2981 /* enable PCIE dpm */
2982 if (0 == data
->pcie_dpm_key_disabled
) {
2983 PP_ASSERT_WITH_CODE(
2984 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
2985 PPSMC_MSG_PCIeDPM_Enable
)),
2986 "Failed to enable pcie DPM during DPM Start Function!",
2991 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2992 PHM_PlatformCaps_Falcon_QuickTransition
)) {
2993 smum_send_msg_to_smc(hwmgr
->smumgr
,
2994 PPSMC_MSG_EnableACDCGPIOInterrupt
);
3000 static void iceland_set_dpm_event_sources(struct pp_hwmgr
*hwmgr
,
3004 enum DPM_EVENT_SRC src
;
3008 printk(KERN_ERR
"Unknown throttling event sources.");
3014 case (1 << PHM_AutoThrottleSource_Thermal
):
3016 src
= DPM_EVENT_SRC_DIGITAL
;
3018 case (1 << PHM_AutoThrottleSource_External
):
3020 src
= DPM_EVENT_SRC_EXTERNAL
;
3022 case (1 << PHM_AutoThrottleSource_External
) |
3023 (1 << PHM_AutoThrottleSource_Thermal
):
3025 src
= DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
;
3028 /* Order matters - don't enable thermal protection for the wrong source. */
3030 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_THERMAL_CTRL
,
3031 DPM_EVENT_SRC
, src
);
3032 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3033 THERMAL_PROTECTION_DIS
,
3034 !phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3035 PHM_PlatformCaps_ThermalController
));
3037 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3038 THERMAL_PROTECTION_DIS
, 1);
3041 static int iceland_enable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
3042 PHM_AutoThrottleSource source
)
3044 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3046 if (!(data
->active_auto_throttle_sources
& (1 << source
))) {
3047 data
->active_auto_throttle_sources
|= 1 << source
;
3048 iceland_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
3053 static int iceland_enable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
3055 return iceland_enable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
3058 static int iceland_tf_start_smc(struct pp_hwmgr
*hwmgr
)
3062 if (!iceland_is_smc_ram_running(hwmgr
->smumgr
))
3063 ret
= iceland_smu_start_smc(hwmgr
->smumgr
);
3069 * Programs the Deep Sleep registers
3071 * @param pHwMgr the address of the powerplay hardware manager.
3072 * @param pInput the pointer to input data (PhwEvergreen_DisplayConfiguration)
3073 * @param pOutput the pointer to output data (unused)
3074 * @param pStorage the pointer to temporary storage (unused)
3075 * @param Result the last failure code (unused)
3078 static int iceland_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
3080 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3081 PHM_PlatformCaps_SclkDeepSleep
)) {
3082 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
3083 PPSMC_MSG_MASTER_DeepSleep_ON
) != 0)
3084 PP_ASSERT_WITH_CODE(false,
3085 "Attempt to enable Master Deep Sleep switch failed!",
3088 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
3089 PPSMC_MSG_MASTER_DeepSleep_OFF
) != 0)
3090 PP_ASSERT_WITH_CODE(false,
3091 "Attempt to disable Master Deep Sleep switch failed!",
3098 static int iceland_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
3100 int tmp_result
, result
= 0;
3102 if (cf_iceland_voltage_control(hwmgr
)) {
3103 tmp_result
= iceland_enable_voltage_control(hwmgr
);
3104 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3105 "Failed to enable voltage control!", return tmp_result
);
3107 tmp_result
= iceland_construct_voltage_tables(hwmgr
);
3108 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3109 "Failed to contruct voltage tables!", return tmp_result
);
3112 tmp_result
= iceland_initialize_mc_reg_table(hwmgr
);
3113 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3114 "Failed to initialize MC reg table!", return tmp_result
);
3116 tmp_result
= iceland_program_static_screen_threshold_parameters(hwmgr
);
3117 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3118 "Failed to program static screen threshold parameters!", return tmp_result
);
3120 tmp_result
= iceland_enable_display_gap(hwmgr
);
3121 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3122 "Failed to enable display gap!", return tmp_result
);
3124 tmp_result
= iceland_program_voting_clients(hwmgr
);
3125 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3126 "Failed to program voting clients!", return tmp_result
);
3128 tmp_result
= iceland_upload_firmware(hwmgr
);
3129 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3130 "Failed to upload firmware header!", return tmp_result
);
3132 tmp_result
= iceland_process_firmware_header(hwmgr
);
3133 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3134 "Failed to process firmware header!", return tmp_result
);
3136 tmp_result
= iceland_initial_switch_from_arb_f0_to_f1(hwmgr
);
3137 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3138 "Failed to initialize switch from ArbF0 to F1!", return tmp_result
);
3140 tmp_result
= iceland_init_smc_table(hwmgr
);
3141 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3142 "Failed to initialize SMC table!", return tmp_result
);
3144 tmp_result
= iceland_populate_initial_mc_reg_table(hwmgr
);
3145 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3146 "Failed to populate initialize MC Reg table!", return tmp_result
);
3148 tmp_result
= iceland_populate_pm_fuses(hwmgr
);
3149 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3150 "Failed to populate PM fuses!", return tmp_result
);
3153 tmp_result
= iceland_tf_start_smc(hwmgr
);
3154 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3155 "Failed to start SMC!", return tmp_result
);
3157 /* enable SCLK control */
3158 tmp_result
= iceland_enable_sclk_control(hwmgr
);
3159 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3160 "Failed to enable SCLK control!", return tmp_result
);
3162 tmp_result
= iceland_enable_deep_sleep_master_switch(hwmgr
);
3163 PP_ASSERT_WITH_CODE((tmp_result
== 0),
3164 "Failed to enable deep sleep!", return tmp_result
);
3167 tmp_result
= iceland_start_dpm(hwmgr
);
3168 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3169 "Failed to start DPM!", return tmp_result
);
3171 tmp_result
= iceland_enable_smc_cac(hwmgr
);
3172 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3173 "Failed to enable SMC CAC!", return tmp_result
);
3175 tmp_result
= iceland_enable_power_containment(hwmgr
);
3176 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3177 "Failed to enable power containment!", return tmp_result
);
3179 tmp_result
= iceland_power_control_set_level(hwmgr
);
3180 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3181 "Failed to power control set level!", result
= tmp_result
);
3183 tmp_result
= iceland_enable_thermal_auto_throttle(hwmgr
);
3184 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3185 "Failed to enable thermal auto throttle!", result
= tmp_result
);
3190 static int iceland_hwmgr_backend_fini(struct pp_hwmgr
*hwmgr
)
3192 return phm_hwmgr_backend_fini(hwmgr
);
3195 static void iceland_initialize_dpm_defaults(struct pp_hwmgr
*hwmgr
)
3197 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3198 struct phw_iceland_ulv_parm
*ulv
;
3201 ulv
->ch_ulv_parameter
= PPICELAND_CGULVPARAMETER_DFLT
;
3202 data
->voting_rights_clients0
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT0
;
3203 data
->voting_rights_clients1
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT1
;
3204 data
->voting_rights_clients2
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT2
;
3205 data
->voting_rights_clients3
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT3
;
3206 data
->voting_rights_clients4
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT4
;
3207 data
->voting_rights_clients5
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT5
;
3208 data
->voting_rights_clients6
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT6
;
3209 data
->voting_rights_clients7
= PPICELAND_VOTINGRIGHTSCLIENTS_DFLT7
;
3211 data
->static_screen_threshold_unit
= PPICELAND_STATICSCREENTHRESHOLDUNIT_DFLT
;
3212 data
->static_screen_threshold
= PPICELAND_STATICSCREENTHRESHOLD_DFLT
;
3214 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3215 PHM_PlatformCaps_ABM
);
3216 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3217 PHM_PlatformCaps_NonABMSupportInPPLib
);
3219 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3220 PHM_PlatformCaps_DynamicACTiming
);
3222 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3223 PHM_PlatformCaps_DisableMemoryTransition
);
3225 iceland_initialize_power_tune_defaults(hwmgr
);
3227 data
->mclk_strobe_mode_threshold
= 40000;
3228 data
->mclk_stutter_mode_threshold
= 30000;
3229 data
->mclk_edc_enable_threshold
= 40000;
3230 data
->mclk_edc_wr_enable_threshold
= 40000;
3232 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3233 PHM_PlatformCaps_DisableMCLS
);
3235 data
->pcie_gen_performance
.max
= PP_PCIEGen1
;
3236 data
->pcie_gen_performance
.min
= PP_PCIEGen3
;
3237 data
->pcie_gen_power_saving
.max
= PP_PCIEGen1
;
3238 data
->pcie_gen_power_saving
.min
= PP_PCIEGen3
;
3240 data
->pcie_lane_performance
.max
= 0;
3241 data
->pcie_lane_performance
.min
= 16;
3242 data
->pcie_lane_power_saving
.max
= 0;
3243 data
->pcie_lane_power_saving
.min
= 16;
3245 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3246 PHM_PlatformCaps_SclkThrottleLowNotification
);
3249 static int iceland_get_evv_voltage(struct pp_hwmgr
*hwmgr
)
3251 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
3252 uint16_t virtual_voltage_id
;
3256 /* the count indicates actual number of entries */
3257 data
->vddc_leakage
.count
= 0;
3258 data
->vddci_leakage
.count
= 0;
3260 if (!phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_EVV
)) {
3261 pr_err("Iceland should always support EVV\n");
3265 /* retrieve voltage for leakage ID (0xff01 + i) */
3266 for (i
= 0; i
< ICELAND_MAX_LEAKAGE_COUNT
; i
++) {
3267 virtual_voltage_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
3269 PP_ASSERT_WITH_CODE((0 == atomctrl_get_voltage_evv(hwmgr
, virtual_voltage_id
, &vddc
)),
3270 "Error retrieving EVV voltage value!\n", continue);
3273 pr_warning("Invalid VDDC value!\n");
3275 if (vddc
!= 0 && vddc
!= virtual_voltage_id
) {
3276 data
->vddc_leakage
.actual_voltage
[data
->vddc_leakage
.count
] = vddc
;
3277 data
->vddc_leakage
.leakage_id
[data
->vddc_leakage
.count
] = virtual_voltage_id
;
3278 data
->vddc_leakage
.count
++;
3285 static void iceland_patch_with_vddc_leakage(struct pp_hwmgr
*hwmgr
,
3288 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3289 uint32_t leakage_index
;
3290 struct phw_iceland_leakage_voltage
*leakage_table
= &data
->vddc_leakage
;
3292 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3293 for (leakage_index
= 0; leakage_index
< leakage_table
->count
; leakage_index
++) {
3295 * If this voltage matches a leakage voltage ID, patch
3296 * with actual leakage voltage.
3298 if (leakage_table
->leakage_id
[leakage_index
] == *vddc
) {
3300 * Need to make sure vddc is less than 2v or
3301 * else, it could burn the ASIC.
3303 if (leakage_table
->actual_voltage
[leakage_index
] >= 2000)
3304 pr_warning("Invalid VDDC value!\n");
3305 *vddc
= leakage_table
->actual_voltage
[leakage_index
];
3306 /* we found leakage voltage */
3311 if (*vddc
>= ATOM_VIRTUAL_VOLTAGE_ID0
)
3312 pr_warning("Voltage value looks like a Leakage ID but it's not patched\n");
3315 static void iceland_patch_with_vddci_leakage(struct pp_hwmgr
*hwmgr
,
3318 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3319 uint32_t leakage_index
;
3320 struct phw_iceland_leakage_voltage
*leakage_table
= &data
->vddci_leakage
;
3322 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3323 for (leakage_index
= 0; leakage_index
< leakage_table
->count
; leakage_index
++) {
3325 * If this voltage matches a leakage voltage ID, patch
3326 * with actual leakage voltage.
3328 if (leakage_table
->leakage_id
[leakage_index
] == *vddci
) {
3329 *vddci
= leakage_table
->actual_voltage
[leakage_index
];
3330 /* we found leakage voltage */
3335 if (*vddci
>= ATOM_VIRTUAL_VOLTAGE_ID0
)
3336 pr_warning("Voltage value looks like a Leakage ID but it's not patched\n");
3339 static int iceland_patch_vddc(struct pp_hwmgr
*hwmgr
,
3340 struct phm_clock_voltage_dependency_table
*tab
)
3345 for (i
= 0; i
< tab
->count
; i
++)
3346 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].v
);
3351 static int iceland_patch_vddci(struct pp_hwmgr
*hwmgr
,
3352 struct phm_clock_voltage_dependency_table
*tab
)
3357 for (i
= 0; i
< tab
->count
; i
++)
3358 iceland_patch_with_vddci_leakage(hwmgr
, &tab
->entries
[i
].v
);
3363 static int iceland_patch_vce_vddc(struct pp_hwmgr
*hwmgr
,
3364 struct phm_vce_clock_voltage_dependency_table
*tab
)
3369 for (i
= 0; i
< tab
->count
; i
++)
3370 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].v
);
3376 static int iceland_patch_uvd_vddc(struct pp_hwmgr
*hwmgr
,
3377 struct phm_uvd_clock_voltage_dependency_table
*tab
)
3382 for (i
= 0; i
< tab
->count
; i
++)
3383 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].v
);
3388 static int iceland_patch_vddc_shed_limit(struct pp_hwmgr
*hwmgr
,
3389 struct phm_phase_shedding_limits_table
*tab
)
3394 for (i
= 0; i
< tab
->count
; i
++)
3395 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].Voltage
);
3400 static int iceland_patch_samu_vddc(struct pp_hwmgr
*hwmgr
,
3401 struct phm_samu_clock_voltage_dependency_table
*tab
)
3406 for (i
= 0; i
< tab
->count
; i
++)
3407 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].v
);
3412 static int iceland_patch_acp_vddc(struct pp_hwmgr
*hwmgr
,
3413 struct phm_acp_clock_voltage_dependency_table
*tab
)
3418 for (i
= 0; i
< tab
->count
; i
++)
3419 iceland_patch_with_vddc_leakage(hwmgr
, &tab
->entries
[i
].v
);
3424 static int iceland_patch_limits_vddc(struct pp_hwmgr
*hwmgr
,
3425 struct phm_clock_and_voltage_limits
*tab
)
3428 iceland_patch_with_vddc_leakage(hwmgr
, (uint32_t *)&tab
->vddc
);
3429 iceland_patch_with_vddci_leakage(hwmgr
, (uint32_t *)&tab
->vddci
);
3435 static int iceland_patch_cac_vddc(struct pp_hwmgr
*hwmgr
, struct phm_cac_leakage_table
*tab
)
3441 for (i
= 0; i
< tab
->count
; i
++) {
3442 vddc
= (uint32_t)(tab
->entries
[i
].Vddc
);
3443 iceland_patch_with_vddc_leakage(hwmgr
, &vddc
);
3444 tab
->entries
[i
].Vddc
= (uint16_t)vddc
;
3451 static int iceland_patch_dependency_tables_with_leakage(struct pp_hwmgr
*hwmgr
)
3455 tmp
= iceland_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dependency_on_sclk
);
3459 tmp
= iceland_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dependency_on_mclk
);
3463 tmp
= iceland_patch_vddc(hwmgr
, hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
);
3467 tmp
= iceland_patch_vddci(hwmgr
, hwmgr
->dyn_state
.vddci_dependency_on_mclk
);
3471 tmp
= iceland_patch_vce_vddc(hwmgr
, hwmgr
->dyn_state
.vce_clock_voltage_dependency_table
);
3475 tmp
= iceland_patch_uvd_vddc(hwmgr
, hwmgr
->dyn_state
.uvd_clock_voltage_dependency_table
);
3479 tmp
= iceland_patch_samu_vddc(hwmgr
, hwmgr
->dyn_state
.samu_clock_voltage_dependency_table
);
3483 tmp
= iceland_patch_acp_vddc(hwmgr
, hwmgr
->dyn_state
.acp_clock_voltage_dependency_table
);
3487 tmp
= iceland_patch_vddc_shed_limit(hwmgr
, hwmgr
->dyn_state
.vddc_phase_shed_limits_table
);
3491 tmp
= iceland_patch_limits_vddc(hwmgr
, &hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3495 tmp
= iceland_patch_limits_vddc(hwmgr
, &hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3499 tmp
= iceland_patch_cac_vddc(hwmgr
, hwmgr
->dyn_state
.cac_leakage_table
);
3506 static int iceland_set_private_var_based_on_pptale(struct pp_hwmgr
*hwmgr
)
3508 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
3510 struct phm_clock_voltage_dependency_table
*allowed_sclk_vddc_table
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
;
3511 struct phm_clock_voltage_dependency_table
*allowed_mclk_vddc_table
= hwmgr
->dyn_state
.vddc_dependency_on_mclk
;
3512 struct phm_clock_voltage_dependency_table
*allowed_mclk_vddci_table
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
3514 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table
!= NULL
,
3515 "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL
);
3516 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table
->count
>= 1,
3517 "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL
);
3519 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table
!= NULL
,
3520 "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL
);
3521 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table
->count
>= 1,
3522 "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL
);
3524 data
->min_vddc_in_pp_table
= (uint16_t)allowed_sclk_vddc_table
->entries
[0].v
;
3525 data
->max_vddc_in_pp_table
= (uint16_t)allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
3527 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
=
3528 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].clk
;
3529 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
=
3530 allowed_mclk_vddc_table
->entries
[allowed_mclk_vddc_table
->count
- 1].clk
;
3531 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
=
3532 allowed_sclk_vddc_table
->entries
[allowed_sclk_vddc_table
->count
- 1].v
;
3534 if (allowed_mclk_vddci_table
!= NULL
&& allowed_mclk_vddci_table
->count
>= 1) {
3535 data
->min_vddci_in_pp_table
= (uint16_t)allowed_mclk_vddci_table
->entries
[0].v
;
3536 data
->max_vddci_in_pp_table
= (uint16_t)allowed_mclk_vddci_table
->entries
[allowed_mclk_vddci_table
->count
- 1].v
;
3539 if (hwmgr
->dyn_state
.vddci_dependency_on_mclk
!= NULL
&& hwmgr
->dyn_state
.vddci_dependency_on_mclk
->count
> 1)
3540 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
= hwmgr
->dyn_state
.vddci_dependency_on_mclk
->entries
[hwmgr
->dyn_state
.vddci_dependency_on_mclk
->count
- 1].v
;
3545 static int iceland_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr
*hwmgr
)
3547 uint32_t table_size
;
3548 struct phm_clock_voltage_dependency_table
*table_clk_vlt
;
3550 hwmgr
->dyn_state
.mclk_sclk_ratio
= 4;
3551 hwmgr
->dyn_state
.sclk_mclk_delta
= 15000; /* 150 MHz */
3552 hwmgr
->dyn_state
.vddc_vddci_delta
= 200; /* 200mV */
3554 /* initialize vddc_dep_on_dal_pwrl table */
3555 table_size
= sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record
);
3556 table_clk_vlt
= (struct phm_clock_voltage_dependency_table
*)kzalloc(table_size
, GFP_KERNEL
);
3558 if (NULL
== table_clk_vlt
) {
3559 pr_err("[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3562 table_clk_vlt
->count
= 4;
3563 table_clk_vlt
->entries
[0].clk
= PP_DAL_POWERLEVEL_ULTRALOW
;
3564 table_clk_vlt
->entries
[0].v
= 0;
3565 table_clk_vlt
->entries
[1].clk
= PP_DAL_POWERLEVEL_LOW
;
3566 table_clk_vlt
->entries
[1].v
= 720;
3567 table_clk_vlt
->entries
[2].clk
= PP_DAL_POWERLEVEL_NOMINAL
;
3568 table_clk_vlt
->entries
[2].v
= 810;
3569 table_clk_vlt
->entries
[3].clk
= PP_DAL_POWERLEVEL_PERFORMANCE
;
3570 table_clk_vlt
->entries
[3].v
= 900;
3571 hwmgr
->dyn_state
.vddc_dep_on_dal_pwrl
= table_clk_vlt
;
3578 * Initializes the Volcanic Islands Hardware Manager
3580 * @param hwmgr the address of the powerplay hardware manager.
3581 * @return 1 if success; otherwise appropriate error code.
3583 static int iceland_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
3586 SMU71_Discrete_DpmTable
*table
= NULL
;
3587 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3588 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment
;
3590 struct phw_iceland_ulv_parm
*ulv
;
3591 struct cgs_system_info sys_info
= {0};
3593 PP_ASSERT_WITH_CODE((NULL
!= hwmgr
),
3594 "Invalid Parameter!", return -EINVAL
;);
3596 data
->dll_defaule_on
= 0;
3597 data
->sram_end
= SMC_RAM_END
;
3599 data
->activity_target
[0] = PPICELAND_TARGETACTIVITY_DFLT
;
3600 data
->activity_target
[1] = PPICELAND_TARGETACTIVITY_DFLT
;
3601 data
->activity_target
[2] = PPICELAND_TARGETACTIVITY_DFLT
;
3602 data
->activity_target
[3] = PPICELAND_TARGETACTIVITY_DFLT
;
3603 data
->activity_target
[4] = PPICELAND_TARGETACTIVITY_DFLT
;
3604 data
->activity_target
[5] = PPICELAND_TARGETACTIVITY_DFLT
;
3605 data
->activity_target
[6] = PPICELAND_TARGETACTIVITY_DFLT
;
3606 data
->activity_target
[7] = PPICELAND_TARGETACTIVITY_DFLT
;
3608 data
->mclk_activity_target
= PPICELAND_MCLK_TARGETACTIVITY_DFLT
;
3610 data
->sclk_dpm_key_disabled
= 0;
3611 data
->mclk_dpm_key_disabled
= 0;
3612 data
->pcie_dpm_key_disabled
= 0;
3613 data
->pcc_monitor_enabled
= 0;
3615 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3616 PHM_PlatformCaps_UnTabledHardwareInterface
);
3618 data
->gpio_debug
= 0;
3619 data
->engine_clock_data
= 0;
3620 data
->memory_clock_data
= 0;
3622 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3623 PHM_PlatformCaps_SclkDeepSleepAboveLow
);
3625 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3626 PHM_PlatformCaps_DynamicPatchPowerState
);
3628 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3629 PHM_PlatformCaps_TablelessHardwareInterface
);
3631 /* Initializes DPM default values. */
3632 iceland_initialize_dpm_defaults(hwmgr
);
3634 /* Enable Platform EVV support. */
3635 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3636 PHM_PlatformCaps_EVV
);
3638 /* Get leakage voltage based on leakage ID. */
3639 result
= iceland_get_evv_voltage(hwmgr
);
3644 * Patch our voltage dependency table with actual leakage
3645 * voltage. We need to perform leakage translation before it's
3646 * used by other functions such as
3647 * iceland_set_hwmgr_variables_based_on_pptable.
3649 result
= iceland_patch_dependency_tables_with_leakage(hwmgr
);
3653 /* Parse pptable data read from VBIOS. */
3654 result
= iceland_set_private_var_based_on_pptale(hwmgr
);
3660 ulv
->ulv_supported
= 1;
3662 /* Initalize Dynamic State Adjustment Rule Settings*/
3663 result
= iceland_initializa_dynamic_state_adjustment_rule_settings(hwmgr
);
3665 pr_err("[ powerplay ] iceland_initializa_dynamic_state_adjustment_rule_settings failed!\n");
3669 data
->voltage_control
= ICELAND_VOLTAGE_CONTROL_NONE
;
3670 data
->vdd_ci_control
= ICELAND_VOLTAGE_CONTROL_NONE
;
3671 data
->mvdd_control
= ICELAND_VOLTAGE_CONTROL_NONE
;
3674 * Hardcode thermal temperature settings for now, these will
3675 * be overwritten if a custom policy exists.
3677 data
->thermal_temp_setting
.temperature_low
= 99500;
3678 data
->thermal_temp_setting
.temperature_high
= 100000;
3679 data
->thermal_temp_setting
.temperature_shutdown
= 104000;
3680 data
->uvd_enabled
= false;
3682 table
= &data
->smc_state_table
;
3684 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_VRHOT_GPIO_PINID
,
3685 &gpio_pin_assignment
)) {
3686 table
->VRHotGpio
= gpio_pin_assignment
.uc_gpio_pin_bit_shift
;
3687 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3688 PHM_PlatformCaps_RegulatorHot
);
3690 table
->VRHotGpio
= ICELAND_UNUSED_GPIO_PIN
;
3691 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3692 PHM_PlatformCaps_RegulatorHot
);
3695 if (atomctrl_get_pp_assign_pin(hwmgr
, PP_AC_DC_SWITCH_GPIO_PINID
,
3696 &gpio_pin_assignment
)) {
3697 table
->AcDcGpio
= gpio_pin_assignment
.uc_gpio_pin_bit_shift
;
3698 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3699 PHM_PlatformCaps_AutomaticDCTransition
);
3701 table
->AcDcGpio
= ICELAND_UNUSED_GPIO_PIN
;
3702 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3703 PHM_PlatformCaps_AutomaticDCTransition
);
3707 * If ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak.
3708 * Current Control feature is enabled and we should program
3711 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_PCC_GPIO_PINID
,
3712 &gpio_pin_assignment
)) {
3713 uint32_t temp_reg
= cgs_read_ind_register(hwmgr
->device
,
3717 switch (gpio_pin_assignment
.uc_gpio_pin_bit_shift
) {
3719 temp_reg
= PHM_SET_FIELD(temp_reg
,
3720 CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x1);
3723 temp_reg
= PHM_SET_FIELD(temp_reg
,
3724 CNB_PWRMGT_CNTL
, GNB_SLOW_MODE
, 0x2);
3727 temp_reg
= PHM_SET_FIELD(temp_reg
,
3728 CNB_PWRMGT_CNTL
, GNB_SLOW
, 0x1);
3731 temp_reg
= PHM_SET_FIELD(temp_reg
,
3732 CNB_PWRMGT_CNTL
, FORCE_NB_PS1
, 0x1);
3735 temp_reg
= PHM_SET_FIELD(temp_reg
,
3736 CNB_PWRMGT_CNTL
, DPM_ENABLED
, 0x1);
3739 pr_warning("[ powerplay ] Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!\n");
3742 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3743 ixCNB_PWRMGT_CNTL
, temp_reg
);
3746 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3747 PHM_PlatformCaps_EnableSMU7ThermalManagement
);
3748 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3749 PHM_PlatformCaps_SMU7
);
3751 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3753 VOLTAGE_OBJ_GPIO_LUT
))
3754 data
->voltage_control
= ICELAND_VOLTAGE_CONTROL_BY_GPIO
;
3755 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3758 data
->voltage_control
= ICELAND_VOLTAGE_CONTROL_BY_SVID2
;
3760 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3761 PHM_PlatformCaps_ControlVDDCI
)) {
3762 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3764 VOLTAGE_OBJ_GPIO_LUT
))
3765 data
->vdd_ci_control
= ICELAND_VOLTAGE_CONTROL_BY_GPIO
;
3766 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3769 data
->vdd_ci_control
= ICELAND_VOLTAGE_CONTROL_BY_SVID2
;
3772 if (data
->vdd_ci_control
== ICELAND_VOLTAGE_CONTROL_NONE
)
3773 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3774 PHM_PlatformCaps_ControlVDDCI
);
3776 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3777 PHM_PlatformCaps_EnableMVDDControl
)) {
3778 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3780 VOLTAGE_OBJ_GPIO_LUT
))
3781 data
->mvdd_control
= ICELAND_VOLTAGE_CONTROL_BY_GPIO
;
3782 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
3785 data
->mvdd_control
= ICELAND_VOLTAGE_CONTROL_BY_SVID2
;
3788 if (data
->mvdd_control
== ICELAND_VOLTAGE_CONTROL_NONE
)
3789 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3790 PHM_PlatformCaps_EnableMVDDControl
);
3792 data
->vddc_phase_shed_control
= false;
3794 stay_in_boot
= phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3795 PHM_PlatformCaps_StayInBootState
);
3797 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3798 PHM_PlatformCaps_DynamicPowerManagement
);
3800 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3801 PHM_PlatformCaps_ActivityReporting
);
3803 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3804 PHM_PlatformCaps_GFXClockGatingSupport
);
3806 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3807 PHM_PlatformCaps_MemorySpreadSpectrumSupport
);
3808 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3809 PHM_PlatformCaps_EngineSpreadSpectrumSupport
);
3811 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3812 PHM_PlatformCaps_DynamicPCIEGen2Support
);
3813 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3814 PHM_PlatformCaps_SMC
);
3816 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3817 PHM_PlatformCaps_DisablePowerGating
);
3818 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3819 PHM_PlatformCaps_BACO
);
3821 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3822 PHM_PlatformCaps_ThermalAutoThrottling
);
3823 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3824 PHM_PlatformCaps_DisableLSClockGating
);
3825 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3826 PHM_PlatformCaps_SamuDPM
);
3827 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3828 PHM_PlatformCaps_AcpDPM
);
3829 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3830 PHM_PlatformCaps_OD6inACSupport
);
3831 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3832 PHM_PlatformCaps_EnablePlatformPowerManagement
);
3834 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3835 PHM_PlatformCaps_PauseMMSessions
);
3837 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3838 PHM_PlatformCaps_OD6PlusinACSupport
);
3839 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3840 PHM_PlatformCaps_PauseMMSessions
);
3841 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3842 PHM_PlatformCaps_GFXClockGatingManagedInCAIL
);
3843 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3844 PHM_PlatformCaps_IcelandULPSSWWorkAround
);
3847 /* iceland doesn't support UVD and VCE */
3848 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3849 PHM_PlatformCaps_UVDPowerGating
);
3850 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3851 PHM_PlatformCaps_VCEPowerGating
);
3853 sys_info
.size
= sizeof(struct cgs_system_info
);
3854 sys_info
.info_id
= CGS_SYSTEM_INFO_PG_FLAGS
;
3855 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
3857 if (sys_info
.value
& AMD_PG_SUPPORT_UVD
)
3858 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3859 PHM_PlatformCaps_UVDPowerGating
);
3860 if (sys_info
.value
& AMD_PG_SUPPORT_VCE
)
3861 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3862 PHM_PlatformCaps_VCEPowerGating
);
3864 data
->is_tlu_enabled
= false;
3865 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
3866 ICELAND_MAX_HARDWARE_POWERLEVELS
;
3867 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
3868 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
3870 sys_info
.size
= sizeof(struct cgs_system_info
);
3871 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_GEN_INFO
;
3872 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
3874 data
->pcie_gen_cap
= AMDGPU_DEFAULT_PCIE_GEN_MASK
;
3876 data
->pcie_gen_cap
= (uint32_t)sys_info
.value
;
3877 if (data
->pcie_gen_cap
& CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)
3878 data
->pcie_spc_cap
= 20;
3879 sys_info
.size
= sizeof(struct cgs_system_info
);
3880 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_MLW
;
3881 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
3883 data
->pcie_lane_cap
= AMDGPU_DEFAULT_PCIE_MLW_MASK
;
3885 data
->pcie_lane_cap
= (uint32_t)sys_info
.value
;
3887 /* Ignore return value in here, we are cleaning up a mess. */
3888 iceland_hwmgr_backend_fini(hwmgr
);
3896 static int iceland_get_num_of_entries(struct pp_hwmgr
*hwmgr
)
3899 unsigned long ret
= 0;
3901 result
= pp_tables_get_num_of_entries(hwmgr
, &ret
);
3903 return result
? 0 : ret
;
3906 static const unsigned long PhwIceland_Magic
= (unsigned long)(PHM_VIslands_Magic
);
3908 struct iceland_power_state
*cast_phw_iceland_power_state(
3909 struct pp_hw_power_state
*hw_ps
)
3914 PP_ASSERT_WITH_CODE((PhwIceland_Magic
== hw_ps
->magic
),
3915 "Invalid Powerstate Type!",
3918 return (struct iceland_power_state
*)hw_ps
;
3921 static int iceland_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
3922 struct pp_power_state
*prequest_ps
,
3923 const struct pp_power_state
*pcurrent_ps
)
3925 struct iceland_power_state
*iceland_ps
=
3926 cast_phw_iceland_power_state(&prequest_ps
->hardware
);
3930 struct PP_Clocks minimum_clocks
= {0};
3931 bool disable_mclk_switching
;
3932 bool disable_mclk_switching_for_frame_lock
;
3933 struct cgs_display_info info
= {0};
3934 const struct phm_clock_and_voltage_limits
*max_limits
;
3936 iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
3939 int32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
3941 data
->battery_state
= (PP_StateUILabel_Battery
== prequest_ps
->classification
.ui_label
);
3943 PP_ASSERT_WITH_CODE(iceland_ps
->performance_level_count
== 2,
3944 "VI should always have 2 performance levels",
3947 max_limits
= (PP_PowerSource_AC
== hwmgr
->power_source
) ?
3948 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
3949 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3951 if (PP_PowerSource_DC
== hwmgr
->power_source
) {
3952 for (i
= 0; i
< iceland_ps
->performance_level_count
; i
++) {
3953 if (iceland_ps
->performance_levels
[i
].memory_clock
> max_limits
->mclk
)
3954 iceland_ps
->performance_levels
[i
].memory_clock
= max_limits
->mclk
;
3955 if (iceland_ps
->performance_levels
[i
].engine_clock
> max_limits
->sclk
)
3956 iceland_ps
->performance_levels
[i
].engine_clock
= max_limits
->sclk
;
3960 iceland_ps
->vce_clocks
.EVCLK
= hwmgr
->vce_arbiter
.evclk
;
3961 iceland_ps
->vce_clocks
.ECCLK
= hwmgr
->vce_arbiter
.ecclk
;
3963 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3965 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_StablePState
)) {
3967 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3968 stable_pstate_sclk
= (max_limits
->sclk
* 75) / 100;
3970 for (count
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->count
-1; count
>= 0; count
--) {
3971 if (stable_pstate_sclk
>= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[count
].clk
) {
3972 stable_pstate_sclk
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[count
].clk
;
3978 stable_pstate_sclk
= hwmgr
->dyn_state
.vddc_dependency_on_sclk
->entries
[0].clk
;
3980 stable_pstate_mclk
= max_limits
->mclk
;
3982 minimum_clocks
.engineClock
= stable_pstate_sclk
;
3983 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
3986 if (minimum_clocks
.engineClock
< hwmgr
->gfx_arbiter
.sclk
)
3987 minimum_clocks
.engineClock
= hwmgr
->gfx_arbiter
.sclk
;
3989 if (minimum_clocks
.memoryClock
< hwmgr
->gfx_arbiter
.mclk
)
3990 minimum_clocks
.memoryClock
= hwmgr
->gfx_arbiter
.mclk
;
3992 iceland_ps
->sclk_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
3994 if (0 != hwmgr
->gfx_arbiter
.sclk_over_drive
) {
3995 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.sclk_over_drive
<= hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
),
3996 "Overdrive sclk exceeds limit",
3997 hwmgr
->gfx_arbiter
.sclk_over_drive
= hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
3999 if (hwmgr
->gfx_arbiter
.sclk_over_drive
>= hwmgr
->gfx_arbiter
.sclk
)
4000 iceland_ps
->performance_levels
[1].engine_clock
= hwmgr
->gfx_arbiter
.sclk_over_drive
;
4003 if (0 != hwmgr
->gfx_arbiter
.mclk_over_drive
) {
4004 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.mclk_over_drive
<= hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
),
4005 "Overdrive mclk exceeds limit",
4006 hwmgr
->gfx_arbiter
.mclk_over_drive
= hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
4008 if (hwmgr
->gfx_arbiter
.mclk_over_drive
>= hwmgr
->gfx_arbiter
.mclk
)
4009 iceland_ps
->performance_levels
[1].memory_clock
= hwmgr
->gfx_arbiter
.mclk_over_drive
;
4012 disable_mclk_switching_for_frame_lock
= phm_cap_enabled(
4013 hwmgr
->platform_descriptor
.platformCaps
,
4014 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
4016 disable_mclk_switching
= (1 < info
.display_count
) ||
4017 disable_mclk_switching_for_frame_lock
;
4019 sclk
= iceland_ps
->performance_levels
[0].engine_clock
;
4020 mclk
= iceland_ps
->performance_levels
[0].memory_clock
;
4022 if (disable_mclk_switching
)
4023 mclk
= iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
- 1].memory_clock
;
4025 if (sclk
< minimum_clocks
.engineClock
)
4026 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ? max_limits
->sclk
: minimum_clocks
.engineClock
;
4028 if (mclk
< minimum_clocks
.memoryClock
)
4029 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ? max_limits
->mclk
: minimum_clocks
.memoryClock
;
4031 iceland_ps
->performance_levels
[0].engine_clock
= sclk
;
4032 iceland_ps
->performance_levels
[0].memory_clock
= mclk
;
4034 iceland_ps
->performance_levels
[1].engine_clock
=
4035 (iceland_ps
->performance_levels
[1].engine_clock
>= iceland_ps
->performance_levels
[0].engine_clock
) ?
4036 iceland_ps
->performance_levels
[1].engine_clock
:
4037 iceland_ps
->performance_levels
[0].engine_clock
;
4039 if (disable_mclk_switching
) {
4040 if (mclk
< iceland_ps
->performance_levels
[1].memory_clock
)
4041 mclk
= iceland_ps
->performance_levels
[1].memory_clock
;
4043 iceland_ps
->performance_levels
[0].memory_clock
= mclk
;
4044 iceland_ps
->performance_levels
[1].memory_clock
= mclk
;
4046 if (iceland_ps
->performance_levels
[1].memory_clock
< iceland_ps
->performance_levels
[0].memory_clock
)
4047 iceland_ps
->performance_levels
[1].memory_clock
= iceland_ps
->performance_levels
[0].memory_clock
;
4050 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_StablePState
)) {
4051 for (i
=0; i
< iceland_ps
->performance_level_count
; i
++) {
4052 iceland_ps
->performance_levels
[i
].engine_clock
= stable_pstate_sclk
;
4053 iceland_ps
->performance_levels
[i
].memory_clock
= stable_pstate_mclk
;
4054 iceland_ps
->performance_levels
[i
].pcie_gen
= data
->pcie_gen_performance
.max
;
4055 iceland_ps
->performance_levels
[i
].pcie_lane
= data
->pcie_gen_performance
.max
;
4062 static bool iceland_is_dpm_running(struct pp_hwmgr
*hwmgr
)
4065 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
4066 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
4067 * whereas voltage control is a fundemental change that will not be disabled
4069 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
4070 FEATURE_STATUS
, VOLTAGE_CONTROLLER_ON
) ? 1 : 0);
4074 * force DPM power State
4076 * @param hwmgr: the address of the powerplay hardware manager.
4077 * @param n : DPM level
4078 * @return The response that came from the SMC.
4080 int iceland_dpm_force_state(struct pp_hwmgr
*hwmgr
, uint32_t n
)
4082 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4084 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
4085 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr
),
4086 "Trying to force SCLK when DPM is disabled", return -1;);
4087 if (0 == data
->sclk_dpm_key_disabled
)
4088 return (0 == smum_send_msg_to_smc_with_parameter(
4090 PPSMC_MSG_DPM_ForceState
,
4097 * force DPM power State
4099 * @param hwmgr: the address of the powerplay hardware manager.
4100 * @param n : DPM level
4101 * @return The response that came from the SMC.
4103 int iceland_dpm_force_state_mclk(struct pp_hwmgr
*hwmgr
, uint32_t n
)
4105 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4107 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
4108 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr
),
4109 "Trying to Force MCLK when DPM is disabled", return -1;);
4110 if (0 == data
->mclk_dpm_key_disabled
)
4111 return (0 == smum_send_msg_to_smc_with_parameter(
4113 PPSMC_MSG_MCLKDPM_ForceState
,
4120 * force DPM power State
4122 * @param hwmgr: the address of the powerplay hardware manager.
4123 * @param n : DPM level
4124 * @return The response that came from the SMC.
4126 int iceland_dpm_force_state_pcie(struct pp_hwmgr
*hwmgr
, uint32_t n
)
4128 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4130 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
4131 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr
),
4132 "Trying to Force PCIE level when DPM is disabled", return -1;);
4133 if (0 == data
->pcie_dpm_key_disabled
)
4134 return (0 == smum_send_msg_to_smc_with_parameter(
4136 PPSMC_MSG_PCIeDPM_ForceLevel
,
4142 static int iceland_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
4144 uint32_t level
, tmp
;
4145 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4147 if (0 == data
->sclk_dpm_key_disabled
) {
4149 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
!= 0) {
4151 tmp
= data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
4156 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr
, level
)),
4157 "force highest sclk dpm state failed!", return -1);
4158 PHM_WAIT_INDIRECT_FIELD(hwmgr
->device
,
4159 SMC_IND
, TARGET_AND_CURRENT_PROFILE_INDEX
, CURR_SCLK_INDEX
, level
);
4164 if (0 == data
->mclk_dpm_key_disabled
) {
4166 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
!= 0) {
4168 tmp
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4173 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_mclk(hwmgr
, level
)),
4174 "force highest mclk dpm state failed!", return -1);
4175 PHM_WAIT_INDIRECT_FIELD(hwmgr
->device
, SMC_IND
,
4176 TARGET_AND_CURRENT_PROFILE_INDEX
, CURR_MCLK_INDEX
, level
);
4181 if (0 == data
->pcie_dpm_key_disabled
) {
4183 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
!= 0) {
4185 tmp
= data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
4190 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_pcie(hwmgr
, level
)),
4191 "force highest pcie dpm state failed!", return -1);
4199 static uint32_t iceland_get_lowest_enable_level(struct pp_hwmgr
*hwmgr
,
4200 uint32_t level_mask
)
4204 while (0 == (level_mask
& (1 << level
)))
4210 static int iceland_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
4213 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4215 /* for now force only sclk */
4216 if (0 != data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4217 level
= iceland_get_lowest_enable_level(hwmgr
,
4218 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4220 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr
, level
)),
4221 "force sclk dpm state failed!", return -1);
4223 PHM_WAIT_INDIRECT_FIELD(hwmgr
->device
, SMC_IND
,
4224 TARGET_AND_CURRENT_PROFILE_INDEX
,
4232 int iceland_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
4234 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4236 PP_ASSERT_WITH_CODE (0 == iceland_is_dpm_running(hwmgr
),
4237 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
4240 if (0 == data
->sclk_dpm_key_disabled
) {
4241 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4243 PPSMC_MSG_NoForcedLevel
)),
4244 "unforce sclk dpm state failed!",
4248 if (0 == data
->mclk_dpm_key_disabled
) {
4249 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4251 PPSMC_MSG_MCLKDPM_NoForcedLevel
)),
4252 "unforce mclk dpm state failed!",
4256 if (0 == data
->pcie_dpm_key_disabled
) {
4257 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4259 PPSMC_MSG_PCIeDPM_UnForceLevel
)),
4260 "unforce pcie level failed!",
4267 static int iceland_force_dpm_level(struct pp_hwmgr
*hwmgr
,
4268 enum amd_dpm_forced_level level
)
4273 case AMD_DPM_FORCED_LEVEL_HIGH
:
4274 ret
= iceland_force_dpm_highest(hwmgr
);
4278 case AMD_DPM_FORCED_LEVEL_LOW
:
4279 ret
= iceland_force_dpm_lowest(hwmgr
);
4283 case AMD_DPM_FORCED_LEVEL_AUTO
:
4284 ret
= iceland_unforce_dpm_levels(hwmgr
);
4292 hwmgr
->dpm_level
= level
;
4296 const struct iceland_power_state
*cast_const_phw_iceland_power_state(
4297 const struct pp_hw_power_state
*hw_ps
)
4302 PP_ASSERT_WITH_CODE((PhwIceland_Magic
== hw_ps
->magic
),
4303 "Invalid Powerstate Type!",
4306 return (const struct iceland_power_state
*)hw_ps
;
4309 static int iceland_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
4311 const struct phm_set_power_state_input
*states
= (const struct phm_set_power_state_input
*)input
;
4312 const struct iceland_power_state
*iceland_ps
= cast_const_phw_iceland_power_state(states
->pnew_state
);
4313 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4314 struct iceland_single_dpm_table
*psclk_table
= &(data
->dpm_table
.sclk_table
);
4315 uint32_t sclk
= iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].engine_clock
;
4316 struct iceland_single_dpm_table
*pmclk_table
= &(data
->dpm_table
.mclk_table
);
4317 uint32_t mclk
= iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].memory_clock
;
4318 struct PP_Clocks min_clocks
= {0};
4320 struct cgs_display_info info
= {0};
4322 data
->need_update_smu7_dpm_table
= 0;
4324 for (i
= 0; i
< psclk_table
->count
; i
++) {
4325 if (sclk
== psclk_table
->dpm_levels
[i
].value
)
4329 if (i
>= psclk_table
->count
)
4330 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
4333 * TODO: Check SCLK in DAL's minimum clocks in case DeepSleep
4334 * divider update is required.
4336 if(data
->display_timing
.min_clock_insr
!= min_clocks
.engineClockInSR
)
4337 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
4340 for (i
= 0; i
< pmclk_table
->count
; i
++) {
4341 if (mclk
== pmclk_table
->dpm_levels
[i
].value
)
4345 if (i
>= pmclk_table
->count
)
4346 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
4348 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4350 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
4351 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
4356 static uint16_t iceland_get_maximum_link_speed(struct pp_hwmgr
*hwmgr
, const struct iceland_power_state
*hw_ps
)
4359 uint32_t pcie_speed
, max_speed
= 0;
4361 for (i
= 0; i
< hw_ps
->performance_level_count
; i
++) {
4362 pcie_speed
= hw_ps
->performance_levels
[i
].pcie_gen
;
4363 if (max_speed
< pcie_speed
)
4364 max_speed
= pcie_speed
;
4370 static uint16_t iceland_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
4372 uint32_t speed_cntl
= 0;
4374 speed_cntl
= cgs_read_ind_register(hwmgr
->device
,
4376 ixPCIE_LC_SPEED_CNTL
);
4377 return((uint16_t)PHM_GET_FIELD(speed_cntl
,
4378 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
4382 static int iceland_request_link_speed_change_before_state_change(struct pp_hwmgr
*hwmgr
, const void *input
)
4384 const struct phm_set_power_state_input
*states
= (const struct phm_set_power_state_input
*)input
;
4385 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4386 const struct iceland_power_state
*iceland_nps
= cast_const_phw_iceland_power_state(states
->pnew_state
);
4387 const struct iceland_power_state
*iceland_cps
= cast_const_phw_iceland_power_state(states
->pcurrent_state
);
4389 uint16_t target_link_speed
= iceland_get_maximum_link_speed(hwmgr
, iceland_nps
);
4390 uint16_t current_link_speed
;
4392 if (data
->force_pcie_gen
== PP_PCIEGenInvalid
)
4393 current_link_speed
= iceland_get_maximum_link_speed(hwmgr
, iceland_cps
);
4395 current_link_speed
= data
->force_pcie_gen
;
4397 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
4398 data
->pspp_notify_required
= false;
4399 if (target_link_speed
> current_link_speed
) {
4400 switch(target_link_speed
) {
4402 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN3
, false))
4404 data
->force_pcie_gen
= PP_PCIEGen2
;
4405 if (current_link_speed
== PP_PCIEGen2
)
4408 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN2
, false))
4411 data
->force_pcie_gen
= iceland_get_current_pcie_speed(hwmgr
);
4415 if (target_link_speed
< current_link_speed
)
4416 data
->pspp_notify_required
= true;
4422 static int iceland_freeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4424 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4426 if (0 == data
->need_update_smu7_dpm_table
)
4429 if ((0 == data
->sclk_dpm_key_disabled
) &&
4430 (data
->need_update_smu7_dpm_table
&
4431 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4432 PP_ASSERT_WITH_CODE(
4433 0 == iceland_is_dpm_running(hwmgr
),
4434 "Trying to freeze SCLK DPM when DPM is disabled",
4436 PP_ASSERT_WITH_CODE(
4437 0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4438 PPSMC_MSG_SCLKDPM_FreezeLevel
),
4439 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4443 if ((0 == data
->mclk_dpm_key_disabled
) &&
4444 (data
->need_update_smu7_dpm_table
&
4445 DPMTABLE_OD_UPDATE_MCLK
)) {
4446 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr
),
4447 "Trying to freeze MCLK DPM when DPM is disabled",
4449 PP_ASSERT_WITH_CODE(
4450 0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4451 PPSMC_MSG_MCLKDPM_FreezeLevel
),
4452 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4459 static int iceland_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr
*hwmgr
, const void *input
)
4463 const struct phm_set_power_state_input
*states
= (const struct phm_set_power_state_input
*)input
;
4464 const struct iceland_power_state
*iceland_ps
= cast_const_phw_iceland_power_state(states
->pnew_state
);
4465 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4466 uint32_t sclk
= iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].engine_clock
;
4467 uint32_t mclk
= iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].memory_clock
;
4468 struct iceland_dpm_table
*pdpm_table
= &data
->dpm_table
;
4470 struct iceland_dpm_table
*pgolden_dpm_table
= &data
->golden_dpm_table
;
4471 uint32_t dpm_count
, clock_percent
;
4474 if (0 == data
->need_update_smu7_dpm_table
)
4477 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
4478 pdpm_table
->sclk_table
.dpm_levels
[pdpm_table
->sclk_table
.count
-1].value
= sclk
;
4480 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
4481 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4483 * Need to do calculation based on the golden DPM table
4484 * as the Heatmap GPU Clock axis is also based on the default values
4486 PP_ASSERT_WITH_CODE(
4487 (pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
!= 0),
4490 dpm_count
= pdpm_table
->sclk_table
.count
< 2 ? 0 : pdpm_table
->sclk_table
.count
-2;
4491 for (i
= dpm_count
; i
> 1; i
--) {
4492 if (sclk
> pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
) {
4493 clock_percent
= ((sclk
- pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
)*100) /
4494 pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
;
4496 pdpm_table
->sclk_table
.dpm_levels
[i
].value
=
4497 pgolden_dpm_table
->sclk_table
.dpm_levels
[i
].value
+
4498 (pgolden_dpm_table
->sclk_table
.dpm_levels
[i
].value
* clock_percent
)/100;
4500 } else if (pgolden_dpm_table
->sclk_table
.dpm_levels
[pdpm_table
->sclk_table
.count
-1].value
> sclk
) {
4501 clock_percent
= ((pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
- sclk
)*100) /
4502 pgolden_dpm_table
->sclk_table
.dpm_levels
[pgolden_dpm_table
->sclk_table
.count
-1].value
;
4504 pdpm_table
->sclk_table
.dpm_levels
[i
].value
=
4505 pgolden_dpm_table
->sclk_table
.dpm_levels
[i
].value
-
4506 (pgolden_dpm_table
->sclk_table
.dpm_levels
[i
].value
* clock_percent
)/100;
4508 pdpm_table
->sclk_table
.dpm_levels
[i
].value
=
4509 pgolden_dpm_table
->sclk_table
.dpm_levels
[i
].value
;
4514 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
4515 pdpm_table
->mclk_table
.dpm_levels
[pdpm_table
->mclk_table
.count
-1].value
= mclk
;
4517 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinACSupport
) ||
4518 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4520 PP_ASSERT_WITH_CODE(
4521 (pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
!= 0),
4524 dpm_count
= pdpm_table
->mclk_table
.count
< 2? 0 : pdpm_table
->mclk_table
.count
-2;
4525 for (i
= dpm_count
; i
> 1; i
--) {
4526 if (mclk
> pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
) {
4527 clock_percent
= ((mclk
- pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
)*100) /
4528 pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
;
4530 pdpm_table
->mclk_table
.dpm_levels
[i
].value
=
4531 pgolden_dpm_table
->mclk_table
.dpm_levels
[i
].value
+
4532 (pgolden_dpm_table
->mclk_table
.dpm_levels
[i
].value
* clock_percent
)/100;
4534 } else if (pgolden_dpm_table
->mclk_table
.dpm_levels
[pdpm_table
->mclk_table
.count
-1].value
> mclk
) {
4535 clock_percent
= ((pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
- mclk
)*100) /
4536 pgolden_dpm_table
->mclk_table
.dpm_levels
[pgolden_dpm_table
->mclk_table
.count
-1].value
;
4538 pdpm_table
->mclk_table
.dpm_levels
[i
].value
=
4539 pgolden_dpm_table
->mclk_table
.dpm_levels
[i
].value
-
4540 (pgolden_dpm_table
->mclk_table
.dpm_levels
[i
].value
* clock_percent
)/100;
4542 pdpm_table
->mclk_table
.dpm_levels
[i
].value
= pgolden_dpm_table
->mclk_table
.dpm_levels
[i
].value
;
4548 if (data
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
)) {
4549 result
= iceland_populate_all_graphic_levels(hwmgr
);
4550 PP_ASSERT_WITH_CODE((0 == result
),
4551 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4555 if (data
->need_update_smu7_dpm_table
& (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
4556 /*populate MCLK dpm table to SMU7 */
4557 result
= iceland_populate_all_memory_levels(hwmgr
);
4558 PP_ASSERT_WITH_CODE((0 == result
),
4559 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4566 static int iceland_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
4567 struct iceland_single_dpm_table
*pdpm_table
,
4568 uint32_t low_limit
, uint32_t high_limit
)
4572 for (i
= 0; i
< pdpm_table
->count
; i
++) {
4573 if ((pdpm_table
->dpm_levels
[i
].value
< low_limit
) ||
4574 (pdpm_table
->dpm_levels
[i
].value
> high_limit
))
4575 pdpm_table
->dpm_levels
[i
].enabled
= false;
4577 pdpm_table
->dpm_levels
[i
].enabled
= true;
4582 static int iceland_trim_dpm_states(struct pp_hwmgr
*hwmgr
, const struct iceland_power_state
*hw_state
)
4585 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4586 uint32_t high_limit_count
;
4588 PP_ASSERT_WITH_CODE((hw_state
->performance_level_count
>= 1),
4589 "power state did not have any performance level",
4592 high_limit_count
= (1 == hw_state
->performance_level_count
) ? 0: 1;
4594 iceland_trim_single_dpm_states(hwmgr
, &(data
->dpm_table
.sclk_table
),
4595 hw_state
->performance_levels
[0].engine_clock
,
4596 hw_state
->performance_levels
[high_limit_count
].engine_clock
);
4598 iceland_trim_single_dpm_states(hwmgr
, &(data
->dpm_table
.mclk_table
),
4599 hw_state
->performance_levels
[0].memory_clock
,
4600 hw_state
->performance_levels
[high_limit_count
].memory_clock
);
4605 static int iceland_generate_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
, const void *input
)
4608 const struct phm_set_power_state_input
*states
= (const struct phm_set_power_state_input
*)input
;
4609 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4610 const struct iceland_power_state
*iceland_ps
= cast_const_phw_iceland_power_state(states
->pnew_state
);
4612 result
= iceland_trim_dpm_states(hwmgr
, iceland_ps
);
4616 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
= iceland_get_dpm_level_enable_mask_value(&data
->dpm_table
.sclk_table
);
4617 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
= iceland_get_dpm_level_enable_mask_value(&data
->dpm_table
.mclk_table
);
4618 data
->last_mclk_dpm_enable_mask
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4619 if (data
->uvd_enabled
&& (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& 1))
4620 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
&= 0xFFFFFFFE;
4622 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
= iceland_get_dpm_level_enable_mask_value(&data
->dpm_table
.pcie_speed_table
);
4627 static int iceland_update_vce_dpm(struct pp_hwmgr
*hwmgr
, const void *input
)
4632 int iceland_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4634 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4637 uint32_t low_sclk_interrupt_threshold
= 0;
4639 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4640 PHM_PlatformCaps_SclkThrottleLowNotification
)
4641 && (hwmgr
->gfx_arbiter
.sclk_threshold
!= data
->low_sclk_interrupt_threshold
)) {
4642 data
->low_sclk_interrupt_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
4643 low_sclk_interrupt_threshold
= data
->low_sclk_interrupt_threshold
;
4645 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold
);
4647 result
= iceland_copy_bytes_to_smc(
4649 data
->dpm_table_start
+ offsetof(SMU71_Discrete_DpmTable
,
4650 LowSclkInterruptThreshold
),
4651 (uint8_t *)&low_sclk_interrupt_threshold
,
4660 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr
*hwmgr
)
4662 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4667 if (0 == (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
))
4671 memset(&data
->mc_reg_table
, 0, sizeof(SMU71_Discrete_MCRegisters
));
4673 result
= iceland_convert_mc_reg_table_to_smc(hwmgr
, &(data
->mc_reg_table
));
4679 address
= data
->mc_reg_table_start
+ (uint32_t)offsetof(SMU71_Discrete_MCRegisters
, data
[0]);
4681 return iceland_copy_bytes_to_smc(hwmgr
->smumgr
, address
,
4682 (uint8_t *)&data
->mc_reg_table
.data
[0],
4683 sizeof(SMU71_Discrete_MCRegisterSet
) * data
->dpm_table
.mclk_table
.count
,
4687 static int iceland_program_memory_timing_parameters_conditionally(struct pp_hwmgr
*hwmgr
)
4689 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4691 if (data
->need_update_smu7_dpm_table
&
4692 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_OD_UPDATE_MCLK
))
4693 return iceland_program_memory_timing_parameters(hwmgr
);
4698 static int iceland_unfreeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4700 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4702 if (0 == data
->need_update_smu7_dpm_table
)
4705 if ((0 == data
->sclk_dpm_key_disabled
) &&
4706 (data
->need_update_smu7_dpm_table
&
4707 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4709 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr
),
4710 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4712 PP_ASSERT_WITH_CODE(
4713 0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4714 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4715 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4719 if ((0 == data
->mclk_dpm_key_disabled
) &&
4720 (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
4722 PP_ASSERT_WITH_CODE(
4723 0 == iceland_is_dpm_running(hwmgr
),
4724 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4726 PP_ASSERT_WITH_CODE(
4727 0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4728 PPSMC_MSG_MCLKDPM_UnfreezeLevel
),
4729 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4733 data
->need_update_smu7_dpm_table
= 0;
4738 static int iceland_notify_link_speed_change_after_state_change(struct pp_hwmgr
*hwmgr
, const void *input
)
4740 const struct phm_set_power_state_input
*states
= (const struct phm_set_power_state_input
*)input
;
4741 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4742 const struct iceland_power_state
*iceland_ps
= cast_const_phw_iceland_power_state(states
->pnew_state
);
4743 uint16_t target_link_speed
= iceland_get_maximum_link_speed(hwmgr
, iceland_ps
);
4746 if (data
->pspp_notify_required
||
4747 data
->pcie_performance_request
) {
4748 if (target_link_speed
== PP_PCIEGen3
)
4749 request
= PCIE_PERF_REQ_GEN3
;
4750 else if (target_link_speed
== PP_PCIEGen2
)
4751 request
= PCIE_PERF_REQ_GEN2
;
4753 request
= PCIE_PERF_REQ_GEN1
;
4755 if(request
== PCIE_PERF_REQ_GEN1
&& iceland_get_current_pcie_speed(hwmgr
) > 0) {
4756 data
->pcie_performance_request
= false;
4760 if (0 != acpi_pcie_perf_request(hwmgr
->device
, request
, false)) {
4761 if (PP_PCIEGen2
== target_link_speed
)
4762 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4764 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4768 data
->pcie_performance_request
= false;
4772 int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
)
4774 PPSMC_Result result
;
4775 iceland_hwmgr
*data
= (iceland_hwmgr
*)(hwmgr
->backend
);
4777 if (0 == data
->sclk_dpm_key_disabled
) {
4778 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
4779 if (0 != iceland_is_dpm_running(hwmgr
))
4780 printk(KERN_ERR
"[ powerplay ] Trying to set Enable Sclk Mask when DPM is disabled \n");
4782 if (0 != data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4783 result
= smum_send_msg_to_smc_with_parameter(
4785 (PPSMC_Msg
)PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4786 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4787 PP_ASSERT_WITH_CODE((0 == result
),
4788 "Set Sclk Dpm enable Mask failed", return -1);
4792 if (0 == data
->mclk_dpm_key_disabled
) {
4793 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
4794 if (0 != iceland_is_dpm_running(hwmgr
))
4795 printk(KERN_ERR
"[ powerplay ] Trying to set Enable Mclk Mask when DPM is disabled \n");
4797 if (0 != data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4798 result
= smum_send_msg_to_smc_with_parameter(
4800 (PPSMC_Msg
)PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4801 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4802 PP_ASSERT_WITH_CODE((0 == result
),
4803 "Set Mclk Dpm enable Mask failed", return -1);
4810 static int iceland_set_power_state_tasks(struct pp_hwmgr
*hwmgr
, const void *input
)
4812 int tmp_result
, result
= 0;
4814 tmp_result
= iceland_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
4815 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to find DPM states clocks in DPM table!", result
= tmp_result
);
4817 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4818 tmp_result
= iceland_request_link_speed_change_before_state_change(hwmgr
, input
);
4819 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to request link speed change before state change!", result
= tmp_result
);
4822 tmp_result
= iceland_freeze_sclk_mclk_dpm(hwmgr
);
4823 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to freeze SCLK MCLK DPM!", result
= tmp_result
);
4825 tmp_result
= iceland_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
4826 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to populate and upload SCLK MCLK DPM levels!", result
= tmp_result
);
4828 tmp_result
= iceland_generate_dpm_level_enable_mask(hwmgr
, input
);
4829 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to generate DPM level enabled mask!", result
= tmp_result
);
4831 tmp_result
= iceland_update_vce_dpm(hwmgr
, input
);
4832 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to update VCE DPM!", result
= tmp_result
);
4834 tmp_result
= iceland_update_sclk_threshold(hwmgr
);
4835 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to update SCLK threshold!", result
= tmp_result
);
4837 tmp_result
= iceland_update_and_upload_mc_reg_table(hwmgr
);
4838 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to upload MC reg table!", result
= tmp_result
);
4840 tmp_result
= iceland_program_memory_timing_parameters_conditionally(hwmgr
);
4841 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to program memory timing parameters!", result
= tmp_result
);
4843 tmp_result
= iceland_unfreeze_sclk_mclk_dpm(hwmgr
);
4844 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to unfreeze SCLK MCLK DPM!", result
= tmp_result
);
4846 tmp_result
= iceland_upload_dpm_level_enable_mask(hwmgr
);
4847 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to upload DPM level enabled mask!", result
= tmp_result
);
4849 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
, PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4850 tmp_result
= iceland_notify_link_speed_change_after_state_change(hwmgr
, input
);
4851 PP_ASSERT_WITH_CODE((0 == tmp_result
), "Failed to notify link speed change after state change!", result
= tmp_result
);
4857 static int iceland_get_power_state_size(struct pp_hwmgr
*hwmgr
)
4859 return sizeof(struct iceland_power_state
);
4862 static int iceland_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
4864 struct pp_power_state
*ps
;
4865 struct iceland_power_state
*iceland_ps
;
4870 ps
= hwmgr
->request_ps
;
4875 iceland_ps
= cast_phw_iceland_power_state(&ps
->hardware
);
4878 return iceland_ps
->performance_levels
[0].memory_clock
;
4880 return iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].memory_clock
;
4883 static int iceland_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
4885 struct pp_power_state
*ps
;
4886 struct iceland_power_state
*iceland_ps
;
4891 ps
= hwmgr
->request_ps
;
4896 iceland_ps
= cast_phw_iceland_power_state(&ps
->hardware
);
4899 return iceland_ps
->performance_levels
[0].engine_clock
;
4901 return iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
-1].engine_clock
;
4904 static int iceland_get_current_pcie_lane_number(
4905 struct pp_hwmgr
*hwmgr
)
4907 uint32_t link_width
;
4909 link_width
= PHM_READ_INDIRECT_FIELD(hwmgr
->device
,
4911 PCIE_LC_LINK_WIDTH_CNTL
,
4914 PP_ASSERT_WITH_CODE((7 >= link_width
),
4915 "Invalid PCIe lane width!", return 0);
4917 return decode_pcie_lane_width(link_width
);
4920 static int iceland_dpm_patch_boot_state(struct pp_hwmgr
*hwmgr
,
4921 struct pp_hw_power_state
*hw_ps
)
4923 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4924 struct iceland_power_state
*ps
= (struct iceland_power_state
*)hw_ps
;
4925 ATOM_FIRMWARE_INFO_V2_2
*fw_info
;
4928 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
4930 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4931 * We assume here that fw_info is unchanged if this call fails.
4933 fw_info
= (ATOM_FIRMWARE_INFO_V2_2
*)cgs_atom_get_data_table(
4934 hwmgr
->device
, index
,
4935 &size
, &frev
, &crev
);
4937 /* During a test, there is no firmware info table. */
4940 /* Patch the state. */
4941 data
->vbios_boot_state
.sclk_bootup_value
= le32_to_cpu(fw_info
->ulDefaultEngineClock
);
4942 data
->vbios_boot_state
.mclk_bootup_value
= le32_to_cpu(fw_info
->ulDefaultMemoryClock
);
4943 data
->vbios_boot_state
.mvdd_bootup_value
= le16_to_cpu(fw_info
->usBootUpMVDDCVoltage
);
4944 data
->vbios_boot_state
.vddc_bootup_value
= le16_to_cpu(fw_info
->usBootUpVDDCVoltage
);
4945 data
->vbios_boot_state
.vddci_bootup_value
= le16_to_cpu(fw_info
->usBootUpVDDCIVoltage
);
4946 data
->vbios_boot_state
.pcie_gen_bootup_value
= iceland_get_current_pcie_speed(hwmgr
);
4947 data
->vbios_boot_state
.pcie_lane_bootup_value
=
4948 (uint16_t)iceland_get_current_pcie_lane_number(hwmgr
);
4950 /* set boot power state */
4951 ps
->performance_levels
[0].memory_clock
= data
->vbios_boot_state
.mclk_bootup_value
;
4952 ps
->performance_levels
[0].engine_clock
= data
->vbios_boot_state
.sclk_bootup_value
;
4953 ps
->performance_levels
[0].pcie_gen
= data
->vbios_boot_state
.pcie_gen_bootup_value
;
4954 ps
->performance_levels
[0].pcie_lane
= data
->vbios_boot_state
.pcie_lane_bootup_value
;
4959 static int iceland_get_pp_table_entry_callback_func(struct pp_hwmgr
*hwmgr
,
4960 struct pp_hw_power_state
*power_state
,
4961 unsigned int index
, const void *clock_info
)
4963 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
4964 struct iceland_power_state
*iceland_power_state
= cast_phw_iceland_power_state(power_state
);
4965 const ATOM_PPLIB_CI_CLOCK_INFO
*visland_clk_info
= clock_info
;
4966 struct iceland_performance_level
*performance_level
;
4967 uint32_t engine_clock
, memory_clock
;
4968 uint16_t pcie_gen_from_bios
;
4970 engine_clock
= visland_clk_info
->ucEngineClockHigh
<< 16 | visland_clk_info
->usEngineClockLow
;
4971 memory_clock
= visland_clk_info
->ucMemoryClockHigh
<< 16 | visland_clk_info
->usMemoryClockLow
;
4973 if (!(data
->mc_micro_code_feature
& DISABLE_MC_LOADMICROCODE
) && memory_clock
> data
->highest_mclk
)
4974 data
->highest_mclk
= memory_clock
;
4976 performance_level
= &(iceland_power_state
->performance_levels
4977 [iceland_power_state
->performance_level_count
++]);
4979 PP_ASSERT_WITH_CODE(
4980 (iceland_power_state
->performance_level_count
< SMU71_MAX_LEVELS_GRAPHICS
),
4981 "Performance levels exceeds SMC limit!",
4984 PP_ASSERT_WITH_CODE(
4985 (iceland_power_state
->performance_level_count
<=
4986 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
4987 "Performance levels exceeds Driver limit!",
4990 /* Performance levels are arranged from low to high. */
4991 performance_level
->memory_clock
= memory_clock
;
4992 performance_level
->engine_clock
= engine_clock
;
4994 pcie_gen_from_bios
= visland_clk_info
->ucPCIEGen
;
4996 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
, pcie_gen_from_bios
);
4997 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
, visland_clk_info
->usPCIELane
);
5002 static int iceland_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
5003 unsigned long entry_index
, struct pp_power_state
*state
)
5006 struct iceland_power_state
*ps
;
5007 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5008 struct phm_clock_voltage_dependency_table
*dep_mclk_table
=
5009 hwmgr
->dyn_state
.vddci_dependency_on_mclk
;
5011 memset(&state
->hardware
, 0x00, sizeof(struct pp_hw_power_state
));
5013 state
->hardware
.magic
= PHM_VIslands_Magic
;
5015 ps
= (struct iceland_power_state
*)(&state
->hardware
);
5017 result
= pp_tables_get_entry(hwmgr
, entry_index
, state
,
5018 iceland_get_pp_table_entry_callback_func
);
5021 * This is the earliest time we have all the dependency table
5022 * and the VBIOS boot state as
5023 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
5024 * state if there is only one VDDCI/MCLK level, check if it's
5025 * the same as VBIOS boot state
5027 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
5028 if (dep_mclk_table
->entries
[0].clk
!=
5029 data
->vbios_boot_state
.mclk_bootup_value
)
5030 printk(KERN_ERR
"Single MCLK entry VDDCI/MCLK dependency table "
5031 "does not match VBIOS boot MCLK level");
5032 if (dep_mclk_table
->entries
[0].v
!=
5033 data
->vbios_boot_state
.vddci_bootup_value
)
5034 printk(KERN_ERR
"Single VDDCI entry VDDCI/MCLK dependency table "
5035 "does not match VBIOS boot VDDCI level");
5038 /* set DC compatible flag if this state supports DC */
5039 if (!state
->validation
.disallowOnDC
)
5040 ps
->dc_compatible
= true;
5042 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
5043 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
5044 else if (0 != (state
->classification
.flags
& PP_StateClassificationFlag_Boot
)) {
5045 if (data
->bacos
.best_match
== 0xffff) {
5046 /* For C.I. use boot state as base BACO state */
5047 data
->bacos
.best_match
= PP_StateClassificationFlag_Boot
;
5048 data
->bacos
.performance_level
= ps
->performance_levels
[0];
5053 ps
->uvd_clocks
.VCLK
= state
->uvd_clocks
.VCLK
;
5054 ps
->uvd_clocks
.DCLK
= state
->uvd_clocks
.DCLK
;
5059 switch (state
->classification
.ui_label
) {
5060 case PP_StateUILabel_Performance
:
5061 data
->use_pcie_performance_levels
= true;
5063 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
5064 if (data
->pcie_gen_performance
.max
<
5065 ps
->performance_levels
[i
].pcie_gen
)
5066 data
->pcie_gen_performance
.max
=
5067 ps
->performance_levels
[i
].pcie_gen
;
5069 if (data
->pcie_gen_performance
.min
>
5070 ps
->performance_levels
[i
].pcie_gen
)
5071 data
->pcie_gen_performance
.min
=
5072 ps
->performance_levels
[i
].pcie_gen
;
5074 if (data
->pcie_lane_performance
.max
<
5075 ps
->performance_levels
[i
].pcie_lane
)
5076 data
->pcie_lane_performance
.max
=
5077 ps
->performance_levels
[i
].pcie_lane
;
5079 if (data
->pcie_lane_performance
.min
>
5080 ps
->performance_levels
[i
].pcie_lane
)
5081 data
->pcie_lane_performance
.min
=
5082 ps
->performance_levels
[i
].pcie_lane
;
5085 case PP_StateUILabel_Battery
:
5086 data
->use_pcie_power_saving_levels
= true;
5088 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
5089 if (data
->pcie_gen_power_saving
.max
<
5090 ps
->performance_levels
[i
].pcie_gen
)
5091 data
->pcie_gen_power_saving
.max
=
5092 ps
->performance_levels
[i
].pcie_gen
;
5094 if (data
->pcie_gen_power_saving
.min
>
5095 ps
->performance_levels
[i
].pcie_gen
)
5096 data
->pcie_gen_power_saving
.min
=
5097 ps
->performance_levels
[i
].pcie_gen
;
5099 if (data
->pcie_lane_power_saving
.max
<
5100 ps
->performance_levels
[i
].pcie_lane
)
5101 data
->pcie_lane_power_saving
.max
=
5102 ps
->performance_levels
[i
].pcie_lane
;
5104 if (data
->pcie_lane_power_saving
.min
>
5105 ps
->performance_levels
[i
].pcie_lane
)
5106 data
->pcie_lane_power_saving
.min
=
5107 ps
->performance_levels
[i
].pcie_lane
;
5118 iceland_print_current_perforce_level(struct pp_hwmgr
*hwmgr
, struct seq_file
*m
)
5120 uint32_t sclk
, mclk
, activity_percent
;
5122 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5124 smum_send_msg_to_smc(hwmgr
->smumgr
, (PPSMC_Msg
)(PPSMC_MSG_API_GetSclkFrequency
));
5126 sclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5128 smum_send_msg_to_smc(hwmgr
->smumgr
, (PPSMC_Msg
)(PPSMC_MSG_API_GetMclkFrequency
));
5130 mclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5131 seq_printf(m
, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk
/100, sclk
/100);
5133 offset
= data
->soft_regs_start
+ offsetof(SMU71_SoftRegisters
, AverageGraphicsActivity
);
5134 activity_percent
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, offset
);
5135 activity_percent
+= 0x80;
5136 activity_percent
>>= 8;
5138 seq_printf(m
, "\n [GPU load]: %u%%\n\n", activity_percent
> 100 ? 100 : activity_percent
);
5140 seq_printf(m
, "uvd %sabled\n", data
->uvd_power_gated
? "dis" : "en");
5142 seq_printf(m
, "vce %sabled\n", data
->vce_power_gated
? "dis" : "en");
5145 int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr
*hwmgr
)
5147 uint32_t num_active_displays
= 0;
5148 struct cgs_display_info info
= {0};
5149 info
.mode_info
= NULL
;
5151 cgs_get_active_displays_info(hwmgr
->device
, &info
);
5153 num_active_displays
= info
.display_count
;
5155 if (num_active_displays
> 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5156 iceland_notify_smc_display_change(hwmgr
, false);
5158 iceland_notify_smc_display_change(hwmgr
, true);
5164 * Programs the display gap
5166 * @param hwmgr the address of the powerplay hardware manager.
5169 int iceland_program_display_gap(struct pp_hwmgr
*hwmgr
)
5171 uint32_t num_active_displays
= 0;
5172 uint32_t display_gap
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
);
5173 uint32_t display_gap2
;
5174 uint32_t pre_vbi_time_in_us
;
5175 uint32_t frame_time_in_us
;
5177 uint32_t refresh_rate
= 0;
5178 struct cgs_display_info info
= {0};
5179 struct cgs_mode_info mode_info
;
5181 info
.mode_info
= &mode_info
;
5183 cgs_get_active_displays_info(hwmgr
->device
, &info
);
5184 num_active_displays
= info
.display_count
;
5186 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
, DISP_GAP
, (num_active_displays
> 0)? DISPLAY_GAP_VBLANK_OR_WM
: DISPLAY_GAP_IGNORE
);
5187 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
, display_gap
);
5189 ref_clock
= mode_info
.ref_clock
;
5190 refresh_rate
= mode_info
.refresh_rate
;
5192 if(0 == refresh_rate
)
5195 frame_time_in_us
= 1000000 / refresh_rate
;
5197 pre_vbi_time_in_us
= frame_time_in_us
- 200 - mode_info
.vblank_time_us
;
5198 display_gap2
= pre_vbi_time_in_us
* (ref_clock
/ 100);
5200 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL2
, display_gap2
);
5202 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SOFT_REGISTERS_TABLE_4
, PreVBlankGap
, 0x64);
5204 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SOFT_REGISTERS_TABLE_5
, VBlankTimeout
, (frame_time_in_us
- pre_vbi_time_in_us
));
5206 if (num_active_displays
== 1)
5207 iceland_notify_smc_display_change(hwmgr
, true);
5212 int iceland_display_configuration_changed_task(struct pp_hwmgr
*hwmgr
)
5214 iceland_program_display_gap(hwmgr
);
5220 * Set maximum target operating fan output PWM
5222 * @param pHwMgr: the address of the powerplay hardware manager.
5223 * @param usMaxFanPwm: max operating fan PWM in percents
5224 * @return The response that came from the SMC.
5226 static int iceland_set_max_fan_pwm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
)
5228 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanPWM
= us_max_fan_pwm
;
5230 if (phm_is_hw_access_blocked(hwmgr
))
5233 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
, PPSMC_MSG_SetFanPwmMax
, us_max_fan_pwm
) ? 0 : -1);
5237 * Set maximum target operating fan output RPM
5239 * @param pHwMgr: the address of the powerplay hardware manager.
5240 * @param usMaxFanRpm: max operating fan RPM value.
5241 * @return The response that came from the SMC.
5243 static int iceland_set_max_fan_rpm_output(struct pp_hwmgr
*hwmgr
, uint16_t us_max_fan_pwm
)
5245 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanRPM
= us_max_fan_pwm
;
5247 if (phm_is_hw_access_blocked(hwmgr
))
5250 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
, PPSMC_MSG_SetFanRpmMax
, us_max_fan_pwm
) ? 0 : -1);
5253 static int iceland_dpm_set_interrupt_state(void *private_data
,
5254 unsigned src_id
, unsigned type
,
5257 uint32_t cg_thermal_int
;
5258 struct pp_hwmgr
*hwmgr
= ((struct pp_eventmgr
*)private_data
)->hwmgr
;
5264 case AMD_THERMAL_IRQ_LOW_TO_HIGH
:
5266 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5267 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
5268 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5270 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5271 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
5272 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5276 case AMD_THERMAL_IRQ_HIGH_TO_LOW
:
5278 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5279 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
5280 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5282 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5283 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
5284 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5293 static int iceland_register_internal_thermal_interrupt(struct pp_hwmgr
*hwmgr
,
5294 const void *thermal_interrupt_info
)
5297 const struct pp_interrupt_registration_info
*info
=
5298 (const struct pp_interrupt_registration_info
*)thermal_interrupt_info
;
5303 result
= cgs_add_irq_source(hwmgr
->device
, 230, AMD_THERMAL_IRQ_LAST
,
5304 iceland_dpm_set_interrupt_state
,
5305 info
->call_back
, info
->context
);
5310 result
= cgs_add_irq_source(hwmgr
->device
, 231, AMD_THERMAL_IRQ_LAST
,
5311 iceland_dpm_set_interrupt_state
,
5312 info
->call_back
, info
->context
);
5321 static bool iceland_check_smc_update_required_for_display_configuration(struct pp_hwmgr
*hwmgr
)
5323 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5324 bool is_update_required
= false;
5325 struct cgs_display_info info
= {0,0,NULL
};
5327 cgs_get_active_displays_info(hwmgr
->device
, &info
);
5329 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
5330 is_update_required
= true;
5331 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5332 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5333 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5334 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5335 is_update_required = true;
5337 return is_update_required
;
5341 static inline bool iceland_are_power_levels_equal(const struct iceland_performance_level
*pl1
,
5342 const struct iceland_performance_level
*pl2
)
5344 return ((pl1
->memory_clock
== pl2
->memory_clock
) &&
5345 (pl1
->engine_clock
== pl2
->engine_clock
) &&
5346 (pl1
->pcie_gen
== pl2
->pcie_gen
) &&
5347 (pl1
->pcie_lane
== pl2
->pcie_lane
));
5350 int iceland_check_states_equal(struct pp_hwmgr
*hwmgr
, const struct pp_hw_power_state
*pstate1
,
5351 const struct pp_hw_power_state
*pstate2
, bool *equal
)
5353 const struct iceland_power_state
*psa
= cast_const_phw_iceland_power_state(pstate1
);
5354 const struct iceland_power_state
*psb
= cast_const_phw_iceland_power_state(pstate2
);
5357 if (equal
== NULL
|| psa
== NULL
|| psb
== NULL
)
5360 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5361 if (psa
->performance_level_count
!= psb
->performance_level_count
) {
5366 for (i
= 0; i
< psa
->performance_level_count
; i
++) {
5367 if (!iceland_are_power_levels_equal(&(psa
->performance_levels
[i
]), &(psb
->performance_levels
[i
]))) {
5368 /* If we have found even one performance level pair that is different the states are different. */
5374 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5375 *equal
= ((psa
->uvd_clocks
.VCLK
== psb
->uvd_clocks
.VCLK
) && (psa
->uvd_clocks
.DCLK
== psb
->uvd_clocks
.DCLK
));
5376 *equal
&= ((psa
->vce_clocks
.EVCLK
== psb
->vce_clocks
.EVCLK
) && (psa
->vce_clocks
.ECCLK
== psb
->vce_clocks
.ECCLK
));
5377 *equal
&= (psa
->sclk_threshold
== psb
->sclk_threshold
);
5378 *equal
&= (psa
->acp_clk
== psb
->acp_clk
);
5383 static int iceland_set_fan_control_mode(struct pp_hwmgr
*hwmgr
, uint32_t mode
)
5386 /* stop auto-manage */
5387 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
5388 PHM_PlatformCaps_MicrocodeFanControl
))
5389 iceland_fan_ctrl_stop_smc_fan_control(hwmgr
);
5390 iceland_fan_ctrl_set_static_mode(hwmgr
, mode
);
5392 /* restart auto-manage */
5393 iceland_fan_ctrl_reset_fan_speed_to_default(hwmgr
);
5398 static int iceland_get_fan_control_mode(struct pp_hwmgr
*hwmgr
)
5400 if (hwmgr
->fan_ctrl_is_in_default_mode
)
5401 return hwmgr
->fan_ctrl_default_mode
;
5403 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
5404 CG_FDO_CTRL2
, FDO_PWM_MODE
);
5407 static int iceland_force_clock_level(struct pp_hwmgr
*hwmgr
,
5408 enum pp_clock_type type
, uint32_t mask
)
5410 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5412 if (hwmgr
->dpm_level
!= AMD_DPM_FORCED_LEVEL_MANUAL
)
5417 if (!data
->sclk_dpm_key_disabled
)
5418 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5419 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
5420 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
& mask
);
5423 if (!data
->mclk_dpm_key_disabled
)
5424 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5425 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
5426 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& mask
);
5430 uint32_t tmp
= mask
& data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
5436 if (!data
->pcie_dpm_key_disabled
)
5437 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5438 PPSMC_MSG_PCIeDPM_ForceLevel
,
5449 static int iceland_print_clock_levels(struct pp_hwmgr
*hwmgr
,
5450 enum pp_clock_type type
, char *buf
)
5452 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5453 struct iceland_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
5454 struct iceland_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
5455 struct iceland_single_dpm_table
*pcie_table
= &(data
->dpm_table
.pcie_speed_table
);
5456 int i
, now
, size
= 0;
5457 uint32_t clock
, pcie_speed
;
5461 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
5462 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5464 for (i
= 0; i
< sclk_table
->count
; i
++) {
5465 if (clock
> sclk_table
->dpm_levels
[i
].value
)
5471 for (i
= 0; i
< sclk_table
->count
; i
++)
5472 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
5473 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
5474 (i
== now
) ? "*" : "");
5477 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
5478 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5480 for (i
= 0; i
< mclk_table
->count
; i
++) {
5481 if (clock
> mclk_table
->dpm_levels
[i
].value
)
5487 for (i
= 0; i
< mclk_table
->count
; i
++)
5488 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
5489 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
5490 (i
== now
) ? "*" : "");
5493 pcie_speed
= iceland_get_current_pcie_speed(hwmgr
);
5494 for (i
= 0; i
< pcie_table
->count
; i
++) {
5495 if (pcie_speed
!= pcie_table
->dpm_levels
[i
].value
)
5501 for (i
= 0; i
< pcie_table
->count
; i
++)
5502 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
5503 (pcie_table
->dpm_levels
[i
].value
== 0) ? "2.5GB, x8" :
5504 (pcie_table
->dpm_levels
[i
].value
== 1) ? "5.0GB, x16" :
5505 (pcie_table
->dpm_levels
[i
].value
== 2) ? "8.0GB, x16" : "",
5506 (i
== now
) ? "*" : "");
5514 static int iceland_get_sclk_od(struct pp_hwmgr
*hwmgr
)
5516 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5517 struct iceland_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
5518 struct iceland_single_dpm_table
*golden_sclk_table
=
5519 &(data
->golden_dpm_table
.sclk_table
);
5522 value
= (sclk_table
->dpm_levels
[sclk_table
->count
- 1].value
-
5523 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
) *
5525 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
5530 static int iceland_set_sclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
5532 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5533 struct iceland_single_dpm_table
*golden_sclk_table
=
5534 &(data
->golden_dpm_table
.sclk_table
);
5535 struct pp_power_state
*ps
;
5536 struct iceland_power_state
*iceland_ps
;
5541 ps
= hwmgr
->request_ps
;
5546 iceland_ps
= cast_phw_iceland_power_state(&ps
->hardware
);
5548 iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
- 1].engine_clock
=
5549 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
*
5551 golden_sclk_table
->dpm_levels
[golden_sclk_table
->count
- 1].value
;
5556 static int iceland_get_mclk_od(struct pp_hwmgr
*hwmgr
)
5558 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5559 struct iceland_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
5560 struct iceland_single_dpm_table
*golden_mclk_table
=
5561 &(data
->golden_dpm_table
.mclk_table
);
5564 value
= (mclk_table
->dpm_levels
[mclk_table
->count
- 1].value
-
5565 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
) *
5567 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
5572 uint32_t iceland_get_xclk(struct pp_hwmgr
*hwmgr
)
5574 uint32_t reference_clock
;
5578 ATOM_FIRMWARE_INFO
*fw_info
;
5581 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
5583 tc
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
);
5588 fw_info
= (ATOM_FIRMWARE_INFO
*)cgs_atom_get_data_table(hwmgr
->device
, index
,
5589 &size
, &frev
, &crev
);
5594 reference_clock
= le16_to_cpu(fw_info
->usReferenceClock
);
5596 divide
= PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
);
5599 return reference_clock
/ 4;
5601 return reference_clock
;
5604 static int iceland_set_mclk_od(struct pp_hwmgr
*hwmgr
, uint32_t value
)
5606 struct iceland_hwmgr
*data
= (struct iceland_hwmgr
*)(hwmgr
->backend
);
5607 struct iceland_single_dpm_table
*golden_mclk_table
=
5608 &(data
->golden_dpm_table
.mclk_table
);
5609 struct pp_power_state
*ps
;
5610 struct iceland_power_state
*iceland_ps
;
5615 ps
= hwmgr
->request_ps
;
5620 iceland_ps
= cast_phw_iceland_power_state(&ps
->hardware
);
5622 iceland_ps
->performance_levels
[iceland_ps
->performance_level_count
- 1].memory_clock
=
5623 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
*
5625 golden_mclk_table
->dpm_levels
[golden_mclk_table
->count
- 1].value
;
5630 static const struct pp_hwmgr_func iceland_hwmgr_funcs
= {
5631 .backend_init
= &iceland_hwmgr_backend_init
,
5632 .backend_fini
= &iceland_hwmgr_backend_fini
,
5633 .asic_setup
= &iceland_setup_asic_task
,
5634 .dynamic_state_management_enable
= &iceland_enable_dpm_tasks
,
5635 .apply_state_adjust_rules
= iceland_apply_state_adjust_rules
,
5636 .force_dpm_level
= &iceland_force_dpm_level
,
5637 .power_state_set
= iceland_set_power_state_tasks
,
5638 .get_power_state_size
= iceland_get_power_state_size
,
5639 .get_mclk
= iceland_dpm_get_mclk
,
5640 .get_sclk
= iceland_dpm_get_sclk
,
5641 .patch_boot_state
= iceland_dpm_patch_boot_state
,
5642 .get_pp_table_entry
= iceland_get_pp_table_entry
,
5643 .get_num_of_pp_table_entries
= iceland_get_num_of_entries
,
5644 .print_current_perforce_level
= iceland_print_current_perforce_level
,
5645 .powerdown_uvd
= iceland_phm_powerdown_uvd
,
5646 .powergate_uvd
= iceland_phm_powergate_uvd
,
5647 .powergate_vce
= iceland_phm_powergate_vce
,
5648 .disable_clock_power_gating
= iceland_phm_disable_clock_power_gating
,
5649 .update_clock_gatings
= iceland_phm_update_clock_gatings
,
5650 .notify_smc_display_config_after_ps_adjustment
= iceland_notify_smc_display_config_after_ps_adjustment
,
5651 .display_config_changed
= iceland_display_configuration_changed_task
,
5652 .set_max_fan_pwm_output
= iceland_set_max_fan_pwm_output
,
5653 .set_max_fan_rpm_output
= iceland_set_max_fan_rpm_output
,
5654 .get_temperature
= iceland_thermal_get_temperature
,
5655 .stop_thermal_controller
= iceland_thermal_stop_thermal_controller
,
5656 .get_fan_speed_info
= iceland_fan_ctrl_get_fan_speed_info
,
5657 .get_fan_speed_percent
= iceland_fan_ctrl_get_fan_speed_percent
,
5658 .set_fan_speed_percent
= iceland_fan_ctrl_set_fan_speed_percent
,
5659 .reset_fan_speed_to_default
= iceland_fan_ctrl_reset_fan_speed_to_default
,
5660 .get_fan_speed_rpm
= iceland_fan_ctrl_get_fan_speed_rpm
,
5661 .set_fan_speed_rpm
= iceland_fan_ctrl_set_fan_speed_rpm
,
5662 .uninitialize_thermal_controller
= iceland_thermal_ctrl_uninitialize_thermal_controller
,
5663 .register_internal_thermal_interrupt
= iceland_register_internal_thermal_interrupt
,
5664 .check_smc_update_required_for_display_configuration
= iceland_check_smc_update_required_for_display_configuration
,
5665 .check_states_equal
= iceland_check_states_equal
,
5666 .set_fan_control_mode
= iceland_set_fan_control_mode
,
5667 .get_fan_control_mode
= iceland_get_fan_control_mode
,
5668 .force_clock_level
= iceland_force_clock_level
,
5669 .print_clock_levels
= iceland_print_clock_levels
,
5670 .get_sclk_od
= iceland_get_sclk_od
,
5671 .set_sclk_od
= iceland_set_sclk_od
,
5672 .get_mclk_od
= iceland_get_mclk_od
,
5673 .set_mclk_od
= iceland_set_mclk_od
,
5676 int iceland_hwmgr_init(struct pp_hwmgr
*hwmgr
)
5678 iceland_hwmgr
*data
;
5680 data
= kzalloc (sizeof(iceland_hwmgr
), GFP_KERNEL
);
5683 memset(data
, 0x00, sizeof(iceland_hwmgr
));
5685 hwmgr
->backend
= data
;
5686 hwmgr
->hwmgr_func
= &iceland_hwmgr_funcs
;
5687 hwmgr
->pptable_func
= &pptable_funcs
;
5690 pp_iceland_thermal_initialize(hwmgr
);