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vfio/pci: Fix typos in comments
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
28 #include "pp_acpi.h"
29 #include "hwmgr.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
34 #include "pp_debug.h"
35 #include "ppatomctrl.h"
36 #include "atombios.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
43 #include "smu74.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
60
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
63
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
68
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
73
74
75 #define SMC_RAM_END 0x40000
76
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
79
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
83
84 #define VDDC_VDDCI_DELTA 200
85
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
88
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
92
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
96
97
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
100
101
102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
104
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
109
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
113
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
115 enum DPM_EVENT_SRC {
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
121 };
122
123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
124
125 struct polaris10_power_state *cast_phw_polaris10_power_state(
126 struct pp_hw_power_state *hw_ps)
127 {
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
129 "Invalid Powerstate Type!",
130 return NULL);
131
132 return (struct polaris10_power_state *)hw_ps;
133 }
134
135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state *hw_ps)
137 {
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
139 "Invalid Powerstate Type!",
140 return NULL);
141
142 return (const struct polaris10_power_state *)hw_ps;
143 }
144
145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
146 {
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
149 ? true : false;
150 }
151
152 /**
153 * Find the MC microcode version and store it in the HwMgr struct
154 *
155 * @param hwmgr the address of the powerplay hardware manager.
156 * @return always 0
157 */
158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
159 {
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
161
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
163
164 return 0;
165 }
166
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
168 {
169 uint32_t speedCntl = 0;
170
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
176 }
177
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
179 {
180 uint32_t link_width;
181
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
185
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
188
189 return decode_pcie_lane_width(link_width);
190 }
191
192 /**
193 * Enable voltage control
194 *
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
197 */
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
199 {
200 PP_ASSERT_WITH_CODE(
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
203 return 1;
204 );
205
206 return 0;
207 }
208
209 /**
210 * Checks if we want to support voltage control
211 *
212 * @param hwmgr the address of the powerplay hardware manager.
213 */
214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
215 {
216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
218
219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
220 }
221
222 /**
223 * Enable voltage control
224 *
225 * @param hwmgr the address of the powerplay hardware manager.
226 * @return always 0
227 */
228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
229 {
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
233
234 return 0;
235 }
236
237 /**
238 * Create Voltage Tables.
239 *
240 * @param hwmgr the address of the powerplay hardware manager.
241 * @return always 0
242 */
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
244 {
245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
248 int result;
249
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
256 return result);
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
262 return result;);
263 }
264
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
271 return result);
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
277 return result);
278 }
279
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
285 return result);
286 }
287
288 PP_ASSERT_WITH_CODE(
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
293
294 PP_ASSERT_WITH_CODE(
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
299
300 PP_ASSERT_WITH_CODE(
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
305
306 return 0;
307 }
308
309 /**
310 * Programs static screed detection parameters
311 *
312 * @param hwmgr the address of the powerplay hardware manager.
313 * @return always 0
314 */
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr *hwmgr)
317 {
318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
319
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
328
329 return 0;
330 }
331
332 /**
333 * Setup display gap for glitch free memory clock switching.
334 *
335 * @param hwmgr the address of the powerplay hardware manager.
336 * @return always 0
337 */
338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
339 {
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
343
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
346
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
349
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
352
353 return 0;
354 }
355
356 /**
357 * Programs activity state transition voting clients
358 *
359 * @param hwmgr the address of the powerplay hardware manager.
360 * @return always 0
361 */
362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
363 {
364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
365
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
371
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
388
389 return 0;
390 }
391
392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
393 {
394 /* Reset voting clients before disabling DPM */
395 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
396 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
397 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
398 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
399
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
401 ixCG_FREQ_TRAN_VOTING_0, 0);
402 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
403 ixCG_FREQ_TRAN_VOTING_1, 0);
404 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
405 ixCG_FREQ_TRAN_VOTING_2, 0);
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
407 ixCG_FREQ_TRAN_VOTING_3, 0);
408 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
409 ixCG_FREQ_TRAN_VOTING_4, 0);
410 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
411 ixCG_FREQ_TRAN_VOTING_5, 0);
412 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
413 ixCG_FREQ_TRAN_VOTING_6, 0);
414 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
415 ixCG_FREQ_TRAN_VOTING_7, 0);
416
417 return 0;
418 }
419
420 /**
421 * Get the location of various tables inside the FW image.
422 *
423 * @param hwmgr the address of the powerplay hardware manager.
424 * @return always 0
425 */
426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
427 {
428 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
429 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
430 uint32_t tmp;
431 int result;
432 bool error = false;
433
434 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
435 SMU7_FIRMWARE_HEADER_LOCATION +
436 offsetof(SMU74_Firmware_Header, DpmTable),
437 &tmp, data->sram_end);
438
439 if (0 == result)
440 data->dpm_table_start = tmp;
441
442 error |= (0 != result);
443
444 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
445 SMU7_FIRMWARE_HEADER_LOCATION +
446 offsetof(SMU74_Firmware_Header, SoftRegisters),
447 &tmp, data->sram_end);
448
449 if (!result) {
450 data->soft_regs_start = tmp;
451 smu_data->soft_regs_start = tmp;
452 }
453
454 error |= (0 != result);
455
456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, mcRegisterTable),
459 &tmp, data->sram_end);
460
461 if (!result)
462 data->mc_reg_table_start = tmp;
463
464 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
465 SMU7_FIRMWARE_HEADER_LOCATION +
466 offsetof(SMU74_Firmware_Header, FanTable),
467 &tmp, data->sram_end);
468
469 if (!result)
470 data->fan_table_start = tmp;
471
472 error |= (0 != result);
473
474 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
475 SMU7_FIRMWARE_HEADER_LOCATION +
476 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
477 &tmp, data->sram_end);
478
479 if (!result)
480 data->arb_table_start = tmp;
481
482 error |= (0 != result);
483
484 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
485 SMU7_FIRMWARE_HEADER_LOCATION +
486 offsetof(SMU74_Firmware_Header, Version),
487 &tmp, data->sram_end);
488
489 if (!result)
490 hwmgr->microcode_version_info.SMC = tmp;
491
492 error |= (0 != result);
493
494 return error ? -1 : 0;
495 }
496
497 /* Copy one arb setting to another and then switch the active set.
498 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
499 */
500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
501 uint32_t arb_src, uint32_t arb_dest)
502 {
503 uint32_t mc_arb_dram_timing;
504 uint32_t mc_arb_dram_timing2;
505 uint32_t burst_time;
506 uint32_t mc_cg_config;
507
508 switch (arb_src) {
509 case MC_CG_ARB_FREQ_F0:
510 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
511 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
512 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
513 break;
514 case MC_CG_ARB_FREQ_F1:
515 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
516 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
517 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
518 break;
519 default:
520 return -EINVAL;
521 }
522
523 switch (arb_dest) {
524 case MC_CG_ARB_FREQ_F0:
525 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
526 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
527 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
528 break;
529 case MC_CG_ARB_FREQ_F1:
530 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
531 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
532 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
533 break;
534 default:
535 return -EINVAL;
536 }
537
538 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
539 mc_cg_config |= 0x0000000F;
540 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
541 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
542
543 return 0;
544 }
545
546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
547 {
548 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
549 }
550
551 /**
552 * Initial switch from ARB F0->F1
553 *
554 * @param hwmgr the address of the powerplay hardware manager.
555 * @return always 0
556 * This function is to be called from the SetPowerState table.
557 */
558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
559 {
560 return polaris10_copy_and_switch_arb_sets(hwmgr,
561 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
562 }
563
564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
565 {
566 uint32_t tmp;
567
568 tmp = (cgs_read_ind_register(hwmgr->device,
569 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
570 0x0000ff00) >> 8;
571
572 if (tmp == MC_CG_ARB_FREQ_F0)
573 return 0;
574
575 return polaris10_copy_and_switch_arb_sets(hwmgr,
576 tmp, MC_CG_ARB_FREQ_F0);
577 }
578
579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
580 {
581 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
582 struct phm_ppt_v1_information *table_info =
583 (struct phm_ppt_v1_information *)(hwmgr->pptable);
584 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
585 uint32_t i, max_entry;
586
587 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
588 data->use_pcie_power_saving_levels), "No pcie performance levels!",
589 return -EINVAL);
590
591 if (data->use_pcie_performance_levels &&
592 !data->use_pcie_power_saving_levels) {
593 data->pcie_gen_power_saving = data->pcie_gen_performance;
594 data->pcie_lane_power_saving = data->pcie_lane_performance;
595 } else if (!data->use_pcie_performance_levels &&
596 data->use_pcie_power_saving_levels) {
597 data->pcie_gen_performance = data->pcie_gen_power_saving;
598 data->pcie_lane_performance = data->pcie_lane_power_saving;
599 }
600
601 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
602 SMU74_MAX_LEVELS_LINK,
603 MAX_REGULAR_DPM_NUMBER);
604
605 if (pcie_table != NULL) {
606 /* max_entry is used to make sure we reserve one PCIE level
607 * for boot level (fix for A+A PSPP issue).
608 * If PCIE table from PPTable have ULV entry + 8 entries,
609 * then ignore the last entry.*/
610 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
611 SMU74_MAX_LEVELS_LINK : pcie_table->count;
612 for (i = 1; i < max_entry; i++) {
613 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
614 get_pcie_gen_support(data->pcie_gen_cap,
615 pcie_table->entries[i].gen_speed),
616 get_pcie_lane_support(data->pcie_lane_cap,
617 pcie_table->entries[i].lane_width));
618 }
619 data->dpm_table.pcie_speed_table.count = max_entry - 1;
620
621 /* Setup BIF_SCLK levels */
622 for (i = 0; i < max_entry; i++)
623 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
624 } else {
625 /* Hardcode Pcie Table */
626 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
627 get_pcie_gen_support(data->pcie_gen_cap,
628 PP_Min_PCIEGen),
629 get_pcie_lane_support(data->pcie_lane_cap,
630 PP_Max_PCIELane));
631 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
632 get_pcie_gen_support(data->pcie_gen_cap,
633 PP_Min_PCIEGen),
634 get_pcie_lane_support(data->pcie_lane_cap,
635 PP_Max_PCIELane));
636 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
637 get_pcie_gen_support(data->pcie_gen_cap,
638 PP_Max_PCIEGen),
639 get_pcie_lane_support(data->pcie_lane_cap,
640 PP_Max_PCIELane));
641 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
642 get_pcie_gen_support(data->pcie_gen_cap,
643 PP_Max_PCIEGen),
644 get_pcie_lane_support(data->pcie_lane_cap,
645 PP_Max_PCIELane));
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
647 get_pcie_gen_support(data->pcie_gen_cap,
648 PP_Max_PCIEGen),
649 get_pcie_lane_support(data->pcie_lane_cap,
650 PP_Max_PCIELane));
651 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
652 get_pcie_gen_support(data->pcie_gen_cap,
653 PP_Max_PCIEGen),
654 get_pcie_lane_support(data->pcie_lane_cap,
655 PP_Max_PCIELane));
656
657 data->dpm_table.pcie_speed_table.count = 6;
658 }
659 /* Populate last level for boot PCIE level, but do not increment count. */
660 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
661 data->dpm_table.pcie_speed_table.count,
662 get_pcie_gen_support(data->pcie_gen_cap,
663 PP_Min_PCIEGen),
664 get_pcie_lane_support(data->pcie_lane_cap,
665 PP_Max_PCIELane));
666
667 return 0;
668 }
669
670 /*
671 * This function is to initalize all DPM state tables
672 * for SMU7 based on the dependency table.
673 * Dynamic state patching function will then trim these
674 * state tables to the allowed range based
675 * on the power policy or external client requests,
676 * such as UVD request, etc.
677 */
678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
679 {
680 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
681 struct phm_ppt_v1_information *table_info =
682 (struct phm_ppt_v1_information *)(hwmgr->pptable);
683 uint32_t i;
684
685 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
686 table_info->vdd_dep_on_sclk;
687 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
688 table_info->vdd_dep_on_mclk;
689
690 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
691 "SCLK dependency table is missing. This table is mandatory",
692 return -EINVAL);
693 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
694 "SCLK dependency table has to have is missing."
695 "This table is mandatory",
696 return -EINVAL);
697
698 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
699 "MCLK dependency table is missing. This table is mandatory",
700 return -EINVAL);
701 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
702 "MCLK dependency table has to have is missing."
703 "This table is mandatory",
704 return -EINVAL);
705
706 /* clear the state table to reset everything to default */
707 phm_reset_single_dpm_table(
708 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
709 phm_reset_single_dpm_table(
710 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
711
712
713 /* Initialize Sclk DPM table based on allow Sclk values */
714 data->dpm_table.sclk_table.count = 0;
715 for (i = 0; i < dep_sclk_table->count; i++) {
716 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
717 dep_sclk_table->entries[i].clk) {
718
719 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
720 dep_sclk_table->entries[i].clk;
721
722 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
723 (i == 0) ? true : false;
724 data->dpm_table.sclk_table.count++;
725 }
726 }
727
728 /* Initialize Mclk DPM table based on allow Mclk values */
729 data->dpm_table.mclk_table.count = 0;
730 for (i = 0; i < dep_mclk_table->count; i++) {
731 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
732 [data->dpm_table.mclk_table.count - 1].value !=
733 dep_mclk_table->entries[i].clk) {
734 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
735 dep_mclk_table->entries[i].clk;
736 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
737 (i == 0) ? true : false;
738 data->dpm_table.mclk_table.count++;
739 }
740 }
741
742 /* setup PCIE gen speed levels */
743 polaris10_setup_default_pcie_table(hwmgr);
744
745 /* save a copy of the default DPM table */
746 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
747 sizeof(struct polaris10_dpm_table));
748
749 return 0;
750 }
751
752 uint8_t convert_to_vid(uint16_t vddc)
753 {
754 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
755 }
756
757 /**
758 * Mvdd table preparation for SMC.
759 *
760 * @param *hwmgr The address of the hardware manager.
761 * @param *table The SMC DPM table structure to be populated.
762 * @return 0
763 */
764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
765 SMU74_Discrete_DpmTable *table)
766 {
767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
768 uint32_t count, level;
769
770 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
771 count = data->mvdd_voltage_table.count;
772 if (count > SMU_MAX_SMIO_LEVELS)
773 count = SMU_MAX_SMIO_LEVELS;
774 for (level = 0; level < count; level++) {
775 table->SmioTable2.Pattern[level].Voltage =
776 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
777 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
778 table->SmioTable2.Pattern[level].Smio =
779 (uint8_t) level;
780 table->Smio[level] |=
781 data->mvdd_voltage_table.entries[level].smio_low;
782 }
783 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
784
785 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
786 }
787
788 return 0;
789 }
790
791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
792 struct SMU74_Discrete_DpmTable *table)
793 {
794 uint32_t count, level;
795 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
796
797 count = data->vddci_voltage_table.count;
798
799 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
800 if (count > SMU_MAX_SMIO_LEVELS)
801 count = SMU_MAX_SMIO_LEVELS;
802 for (level = 0; level < count; ++level) {
803 table->SmioTable1.Pattern[level].Voltage =
804 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
805 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
806
807 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
808 }
809 }
810
811 table->SmioMask1 = data->vddci_voltage_table.mask_low;
812
813 return 0;
814 }
815
816 /**
817 * Preparation of vddc and vddgfx CAC tables for SMC.
818 *
819 * @param hwmgr the address of the hardware manager
820 * @param table the SMC DPM table structure to be populated
821 * @return always 0
822 */
823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
824 struct SMU74_Discrete_DpmTable *table)
825 {
826 uint32_t count;
827 uint8_t index;
828 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
829 struct phm_ppt_v1_information *table_info =
830 (struct phm_ppt_v1_information *)(hwmgr->pptable);
831 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
832 table_info->vddc_lookup_table;
833 /* tables is already swapped, so in order to use the value from it,
834 * we need to swap it back.
835 * We are populating vddc CAC data to BapmVddc table
836 * in split and merged mode
837 */
838 for (count = 0; count < lookup_table->count; count++) {
839 index = phm_get_voltage_index(lookup_table,
840 data->vddc_voltage_table.entries[count].value);
841 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
842 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
843 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
844 }
845
846 return 0;
847 }
848
849 /**
850 * Preparation of voltage tables for SMC.
851 *
852 * @param hwmgr the address of the hardware manager
853 * @param table the SMC DPM table structure to be populated
854 * @return always 0
855 */
856
857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
858 struct SMU74_Discrete_DpmTable *table)
859 {
860 polaris10_populate_smc_vddci_table(hwmgr, table);
861 polaris10_populate_smc_mvdd_table(hwmgr, table);
862 polaris10_populate_cac_table(hwmgr, table);
863
864 return 0;
865 }
866
867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
868 struct SMU74_Discrete_Ulv *state)
869 {
870 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
871 struct phm_ppt_v1_information *table_info =
872 (struct phm_ppt_v1_information *)(hwmgr->pptable);
873
874 state->CcPwrDynRm = 0;
875 state->CcPwrDynRm1 = 0;
876
877 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
878 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
879 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
880
881 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
882
883 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
884 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
885 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
886
887 return 0;
888 }
889
890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
891 struct SMU74_Discrete_DpmTable *table)
892 {
893 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
894 }
895
896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
897 struct SMU74_Discrete_DpmTable *table)
898 {
899 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
900 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
901 int i;
902
903 /* Index (dpm_table->pcie_speed_table.count)
904 * is reserved for PCIE boot level. */
905 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
906 table->LinkLevel[i].PcieGenSpeed =
907 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
908 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
909 dpm_table->pcie_speed_table.dpm_levels[i].param1);
910 table->LinkLevel[i].EnabledForActivity = 1;
911 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
912 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
913 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
914 }
915
916 data->smc_state_table.LinkLevelCount =
917 (uint8_t)dpm_table->pcie_speed_table.count;
918 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
919 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
920
921 return 0;
922 }
923
924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
925 {
926 uint32_t reference_clock, tmp;
927 struct cgs_display_info info = {0};
928 struct cgs_mode_info mode_info;
929
930 info.mode_info = &mode_info;
931
932 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
933
934 if (tmp)
935 return TCLK;
936
937 cgs_get_active_displays_info(hwmgr->device, &info);
938 reference_clock = mode_info.ref_clock;
939
940 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
941
942 if (0 != tmp)
943 return reference_clock / 4;
944
945 return reference_clock;
946 }
947
948 /**
949 * Calculates the SCLK dividers using the provided engine clock
950 *
951 * @param hwmgr the address of the hardware manager
952 * @param clock the engine clock to use to populate the structure
953 * @param sclk the SMC SCLK structure to be populated
954 */
955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
956 uint32_t clock, SMU_SclkSetting *sclk_setting)
957 {
958 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
959 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
960 struct pp_atomctrl_clock_dividers_ai dividers;
961
962 uint32_t ref_clock;
963 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
964 uint8_t i;
965 int result;
966 uint64_t temp;
967
968 sclk_setting->SclkFrequency = clock;
969 /* get the engine clock dividers for this clock value */
970 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
971 if (result == 0) {
972 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
973 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
974 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
975 sclk_setting->PllRange = dividers.ucSclkPllRange;
976 sclk_setting->Sclk_slew_rate = 0x400;
977 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
978 sclk_setting->Pcc_down_slew_rate = 0xffff;
979 sclk_setting->SSc_En = dividers.ucSscEnable;
980 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
981 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
982 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
983 return result;
984 }
985
986 ref_clock = polaris10_get_xclk(hwmgr);
987
988 for (i = 0; i < NUM_SCLK_RANGE; i++) {
989 if (clock > data->range_table[i].trans_lower_frequency
990 && clock <= data->range_table[i].trans_upper_frequency) {
991 sclk_setting->PllRange = i;
992 break;
993 }
994 }
995
996 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
997 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
998 temp <<= 0x10;
999 do_div(temp, ref_clock);
1000 sclk_setting->Fcw_frac = temp & 0xffff;
1001
1002 pcc_target_percent = 10; /* Hardcode 10% for now. */
1003 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1005
1006 ss_target_percent = 2; /* Hardcode 2% for now. */
1007 sclk_setting->SSc_En = 0;
1008 if (ss_target_percent) {
1009 sclk_setting->SSc_En = 1;
1010 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1013 temp <<= 0x10;
1014 do_div(temp, ref_clock);
1015 sclk_setting->Fcw1_frac = temp & 0xffff;
1016 }
1017
1018 return 0;
1019 }
1020
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1024 {
1025 uint32_t i;
1026 uint16_t vddci;
1027 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1028
1029 *voltage = *mvdd = 0;
1030
1031 /* clock - voltage dependency table is empty table */
1032 if (dep_table->count == 0)
1033 return -EINVAL;
1034
1035 for (i = 0; i < dep_table->count; i++) {
1036 /* find first sclk bigger than request */
1037 if (dep_table->entries[i].clk >= clock) {
1038 *voltage |= (dep_table->entries[i].vddc *
1039 VOLTAGE_SCALE) << VDDC_SHIFT;
1040 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043 else if (dep_table->entries[i].vddci)
1044 *voltage |= (dep_table->entries[i].vddci *
1045 VOLTAGE_SCALE) << VDDCI_SHIFT;
1046 else {
1047 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048 (dep_table->entries[i].vddc -
1049 (uint16_t)data->vddc_vddci_delta));
1050 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1051 }
1052
1053 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1055 VOLTAGE_SCALE;
1056 else if (dep_table->entries[i].mvdd)
1057 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1058 VOLTAGE_SCALE;
1059
1060 *voltage |= 1 << PHASES_SHIFT;
1061 return 0;
1062 }
1063 }
1064
1065 /* sclk is bigger than max sclk in the dependence table */
1066 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1067
1068 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071 else if (dep_table->entries[i-1].vddci) {
1072 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073 (dep_table->entries[i].vddc -
1074 (uint16_t)data->vddc_vddci_delta));
1075 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1076 }
1077
1078 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080 else if (dep_table->entries[i].mvdd)
1081 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1082
1083 return 0;
1084 }
1085
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1088 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1090 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1091 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1092 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1093 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1094 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1095
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1097 {
1098 uint32_t i, ref_clk;
1099 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1101 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1102
1103 ref_clk = polaris10_get_xclk(hwmgr);
1104
1105 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1110
1111 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1113
1114 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1117 }
1118 return;
1119 }
1120
1121 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1122
1123 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1125
1126 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1129
1130 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1132
1133 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1136 }
1137 }
1138
1139 /**
1140 * Populates single SMC SCLK structure using the provided engine clock
1141 *
1142 * @param hwmgr the address of the hardware manager
1143 * @param clock the engine clock to use to populate the structure
1144 * @param sclk the SMC SCLK structure to be populated
1145 */
1146
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148 uint32_t clock, uint16_t sclk_al_threshold,
1149 struct SMU74_Discrete_GraphicsLevel *level)
1150 {
1151 int result, i, temp;
1152 /* PP_Clocks minClocks; */
1153 uint32_t mvdd;
1154 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155 struct phm_ppt_v1_information *table_info =
1156 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157 SMU_SclkSetting curr_sclk_setting = { 0 };
1158
1159 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1160
1161 /* populate graphics levels */
1162 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163 table_info->vdd_dep_on_sclk, clock,
1164 &level->MinVoltage, &mvdd);
1165
1166 PP_ASSERT_WITH_CODE((0 == result),
1167 "can not find VDDC voltage value for "
1168 "VDDC engine clock dependency table",
1169 return result);
1170 level->ActivityLevel = sclk_al_threshold;
1171
1172 level->CcPwrDynRm = 0;
1173 level->CcPwrDynRm1 = 0;
1174 level->EnabledForActivity = 0;
1175 level->EnabledForThrottle = 1;
1176 level->UpHyst = 10;
1177 level->DownHyst = 0;
1178 level->VoltageDownHyst = 0;
1179 level->PowerThrottle = 0;
1180
1181 /*
1182 * TODO: get minimum clocks from dal configaration
1183 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1184 */
1185 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1186
1187 /* get level->DeepSleepDivId
1188 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1190 */
1191 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1193 temp = clock >> i;
1194
1195 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1196 break;
1197 }
1198
1199 level->DeepSleepDivId = i;
1200
1201 /* Default to slow, highest DPM level will be
1202 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1203 */
1204 if (data->update_up_hyst)
1205 level->UpHyst = (uint8_t)data->up_hyst;
1206 if (data->update_down_hyst)
1207 level->DownHyst = (uint8_t)data->down_hyst;
1208
1209 level->SclkSetting = curr_sclk_setting;
1210
1211 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1225 return 0;
1226 }
1227
1228 /**
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1230 *
1231 * @param hwmgr the address of the hardware manager
1232 */
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1234 {
1235 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237 struct phm_ppt_v1_information *table_info =
1238 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1241 int result = 0;
1242 uint32_t array = data->dpm_table_start +
1243 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245 SMU74_MAX_LEVELS_GRAPHICS;
1246 struct SMU74_Discrete_GraphicsLevel *levels =
1247 data->smc_state_table.GraphicsLevel;
1248 uint32_t i, max_entry;
1249 uint8_t hightest_pcie_level_enabled = 0,
1250 lowest_pcie_level_enabled = 0,
1251 mid_pcie_level_enabled = 0,
1252 count = 0;
1253
1254 polaris10_get_sclk_range_table(hwmgr);
1255
1256 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1257
1258 result = polaris10_populate_single_graphic_level(hwmgr,
1259 dpm_table->sclk_table.dpm_levels[i].value,
1260 (uint16_t)data->activity_target[i],
1261 &(data->smc_state_table.GraphicsLevel[i]));
1262 if (result)
1263 return result;
1264
1265 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1266 if (i > 1)
1267 levels[i].DeepSleepDivId = 0;
1268 }
1269 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270 PHM_PlatformCaps_SPLLShutdownSupport))
1271 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1272
1273 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274 data->smc_state_table.GraphicsDpmLevelCount =
1275 (uint8_t)dpm_table->sclk_table.count;
1276 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1278
1279
1280 if (pcie_table != NULL) {
1281 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282 "There must be 1 or more PCIE levels defined in PPTable.",
1283 return -EINVAL);
1284 max_entry = pcie_entry_cnt - 1;
1285 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286 levels[i].pcieDpmLevel =
1287 (uint8_t) ((i < max_entry) ? i : max_entry);
1288 } else {
1289 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292 hightest_pcie_level_enabled++;
1293
1294 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296 (1 << lowest_pcie_level_enabled)) == 0))
1297 lowest_pcie_level_enabled++;
1298
1299 while ((count < hightest_pcie_level_enabled) &&
1300 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1302 count++;
1303
1304 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305 hightest_pcie_level_enabled ?
1306 (lowest_pcie_level_enabled + 1 + count) :
1307 hightest_pcie_level_enabled;
1308
1309 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1312
1313 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1315
1316 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1318 }
1319 /* level count will send to smc once at init smc table and never change */
1320 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321 (uint32_t)array_size, data->sram_end);
1322
1323 return result;
1324 }
1325
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1328 {
1329 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330 struct phm_ppt_v1_information *table_info =
1331 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1332 int result = 0;
1333 struct cgs_display_info info = {0, 0, NULL};
1334
1335 cgs_get_active_displays_info(hwmgr->device, &info);
1336
1337 if (table_info->vdd_dep_on_mclk) {
1338 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339 table_info->vdd_dep_on_mclk, clock,
1340 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341 PP_ASSERT_WITH_CODE((0 == result),
1342 "can not find MinVddc voltage value from memory "
1343 "VDDC voltage dependency table", return result);
1344 }
1345
1346 mem_level->MclkFrequency = clock;
1347 mem_level->EnabledForThrottle = 1;
1348 mem_level->EnabledForActivity = 0;
1349 mem_level->UpHyst = 0;
1350 mem_level->DownHyst = 100;
1351 mem_level->VoltageDownHyst = 0;
1352 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353 mem_level->StutterEnable = false;
1354 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1355
1356 data->display_timing.num_existing_displays = info.display_count;
1357
1358 if ((data->mclk_stutter_mode_threshold) &&
1359 (clock <= data->mclk_stutter_mode_threshold) &&
1360 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361 STUTTER_ENABLE) & 0x1))
1362 mem_level->StutterEnable = true;
1363
1364 if (!result) {
1365 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1369 }
1370 return result;
1371 }
1372
1373 /**
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1375 *
1376 * @param hwmgr the address of the hardware manager
1377 */
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1379 {
1380 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1382 int result;
1383 /* populate MCLK dpm table to SMU7 */
1384 uint32_t array = data->dpm_table_start +
1385 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387 SMU74_MAX_LEVELS_MEMORY;
1388 struct SMU74_Discrete_MemoryLevel *levels =
1389 data->smc_state_table.MemoryLevel;
1390 uint32_t i;
1391
1392 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394 "can not populate memory level as memory clock is zero",
1395 return -EINVAL);
1396 result = polaris10_populate_single_memory_level(hwmgr,
1397 dpm_table->mclk_table.dpm_levels[i].value,
1398 &levels[i]);
1399 if (i == dpm_table->mclk_table.count - 1) {
1400 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401 levels[i].EnabledForActivity = 1;
1402 }
1403 if (result)
1404 return result;
1405 }
1406
1407 /* In order to prevent MC activity from stutter mode to push DPM up,
1408 * the UVD change complements this by putting the MCLK in
1409 * a higher state by default such that we are not affected by
1410 * up threshold or and MCLK DPM latency.
1411 */
1412 levels[0].ActivityLevel = 0x1f;
1413 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1414
1415 data->smc_state_table.MemoryDpmLevelCount =
1416 (uint8_t)dpm_table->mclk_table.count;
1417 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1419
1420 /* level count will send to smc once at init smc table and never change */
1421 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422 (uint32_t)array_size, data->sram_end);
1423
1424 return result;
1425 }
1426
1427 /**
1428 * Populates the SMC MVDD structure using the provided memory clock.
1429 *
1430 * @param hwmgr the address of the hardware manager
1431 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param voltage the SMC VOLTAGE structure to be populated
1433 */
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435 uint32_t mclk, SMIO_Pattern *smio_pat)
1436 {
1437 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438 struct phm_ppt_v1_information *table_info =
1439 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1440 uint32_t i = 0;
1441
1442 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443 /* find mvdd value which clock is more than request */
1444 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1447 break;
1448 }
1449 }
1450 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451 "MVDD Voltage is outside the supported range.",
1452 return -EINVAL);
1453 } else
1454 return -EINVAL;
1455
1456 return 0;
1457 }
1458
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460 SMU74_Discrete_DpmTable *table)
1461 {
1462 int result = 0;
1463 uint32_t sclk_frequency;
1464 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465 struct phm_ppt_v1_information *table_info =
1466 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467 SMIO_Pattern vol_level;
1468 uint32_t mvdd;
1469 uint16_t us_mvdd;
1470
1471 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1472
1473
1474 /* Get MinVoltage and Frequency from DPM0,
1475 * already converted to SMC_UL */
1476 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1477 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478 table_info->vdd_dep_on_sclk,
1479 sclk_frequency,
1480 &table->ACPILevel.MinVoltage, &mvdd);
1481 PP_ASSERT_WITH_CODE((0 == result),
1482 "Cannot find ACPI VDDC voltage value "
1483 "in Clock Dependency Table",
1484 );
1485
1486
1487 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1488 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1489
1490 table->ACPILevel.DeepSleepDivId = 0;
1491 table->ACPILevel.CcPwrDynRm = 0;
1492 table->ACPILevel.CcPwrDynRm1 = 0;
1493
1494 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1495 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1496 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1497 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1498
1499 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1500 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1501 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1502 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1503 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1504 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1505 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1506 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1507 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1508 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1509
1510
1511 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1512 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1513 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1514 table_info->vdd_dep_on_mclk,
1515 table->MemoryACPILevel.MclkFrequency,
1516 &table->MemoryACPILevel.MinVoltage, &mvdd);
1517 PP_ASSERT_WITH_CODE((0 == result),
1518 "Cannot find ACPI VDDCI voltage value "
1519 "in Clock Dependency Table",
1520 );
1521
1522 us_mvdd = 0;
1523 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1524 (data->mclk_dpm_key_disabled))
1525 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1526 else {
1527 if (!polaris10_populate_mvdd_value(hwmgr,
1528 data->dpm_table.mclk_table.dpm_levels[0].value,
1529 &vol_level))
1530 us_mvdd = vol_level.Voltage;
1531 }
1532
1533 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1534 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1535 else
1536 table->MemoryACPILevel.MinMvdd = 0;
1537
1538 table->MemoryACPILevel.StutterEnable = false;
1539
1540 table->MemoryACPILevel.EnabledForThrottle = 0;
1541 table->MemoryACPILevel.EnabledForActivity = 0;
1542 table->MemoryACPILevel.UpHyst = 0;
1543 table->MemoryACPILevel.DownHyst = 100;
1544 table->MemoryACPILevel.VoltageDownHyst = 0;
1545 table->MemoryACPILevel.ActivityLevel =
1546 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1547
1548 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1549 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1550
1551 return result;
1552 }
1553
1554 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1555 SMU74_Discrete_DpmTable *table)
1556 {
1557 int result = -EINVAL;
1558 uint8_t count;
1559 struct pp_atomctrl_clock_dividers_vi dividers;
1560 struct phm_ppt_v1_information *table_info =
1561 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1562 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1563 table_info->mm_dep_table;
1564 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1565 uint32_t vddci;
1566
1567 table->VceLevelCount = (uint8_t)(mm_table->count);
1568 table->VceBootLevel = 0;
1569
1570 for (count = 0; count < table->VceLevelCount; count++) {
1571 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1572 table->VceLevel[count].MinVoltage = 0;
1573 table->VceLevel[count].MinVoltage |=
1574 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1575
1576 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1577 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1578 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1579 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1580 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1581 else
1582 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1583
1584
1585 table->VceLevel[count].MinVoltage |=
1586 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1587 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1588
1589 /*retrieve divider value for VBIOS */
1590 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1591 table->VceLevel[count].Frequency, &dividers);
1592 PP_ASSERT_WITH_CODE((0 == result),
1593 "can not find divide id for VCE engine clock",
1594 return result);
1595
1596 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1597
1598 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1599 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1600 }
1601 return result;
1602 }
1603
1604 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1605 SMU74_Discrete_DpmTable *table)
1606 {
1607 int result = -EINVAL;
1608 uint8_t count;
1609 struct pp_atomctrl_clock_dividers_vi dividers;
1610 struct phm_ppt_v1_information *table_info =
1611 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1612 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1613 table_info->mm_dep_table;
1614 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1615 uint32_t vddci;
1616
1617 table->SamuBootLevel = 0;
1618 table->SamuLevelCount = (uint8_t)(mm_table->count);
1619
1620 for (count = 0; count < table->SamuLevelCount; count++) {
1621 /* not sure whether we need evclk or not */
1622 table->SamuLevel[count].MinVoltage = 0;
1623 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1624 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1625 VOLTAGE_SCALE) << VDDC_SHIFT;
1626
1627 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1628 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1629 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1630 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1631 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1632 else
1633 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1634
1635 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1636 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1637
1638 /* retrieve divider value for VBIOS */
1639 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1640 table->SamuLevel[count].Frequency, &dividers);
1641 PP_ASSERT_WITH_CODE((0 == result),
1642 "can not find divide id for samu clock", return result);
1643
1644 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1645
1646 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1647 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1648 }
1649 return result;
1650 }
1651
1652 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1653 int32_t eng_clock, int32_t mem_clock,
1654 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1655 {
1656 uint32_t dram_timing;
1657 uint32_t dram_timing2;
1658 uint32_t burst_time;
1659 int result;
1660
1661 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1662 eng_clock, mem_clock);
1663 PP_ASSERT_WITH_CODE(result == 0,
1664 "Error calling VBIOS to set DRAM_TIMING.", return result);
1665
1666 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1667 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1668 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1669
1670
1671 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1672 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1673 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1674
1675 return 0;
1676 }
1677
1678 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1679 {
1680 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1681 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1682 uint32_t i, j;
1683 int result = 0;
1684
1685 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1686 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1687 result = polaris10_populate_memory_timing_parameters(hwmgr,
1688 data->dpm_table.sclk_table.dpm_levels[i].value,
1689 data->dpm_table.mclk_table.dpm_levels[j].value,
1690 &arb_regs.entries[i][j]);
1691 if (result == 0)
1692 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1693 if (result != 0)
1694 return result;
1695 }
1696 }
1697
1698 result = polaris10_copy_bytes_to_smc(
1699 hwmgr->smumgr,
1700 data->arb_table_start,
1701 (uint8_t *)&arb_regs,
1702 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1703 data->sram_end);
1704 return result;
1705 }
1706
1707 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1708 struct SMU74_Discrete_DpmTable *table)
1709 {
1710 int result = -EINVAL;
1711 uint8_t count;
1712 struct pp_atomctrl_clock_dividers_vi dividers;
1713 struct phm_ppt_v1_information *table_info =
1714 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1715 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1716 table_info->mm_dep_table;
1717 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1718 uint32_t vddci;
1719
1720 table->UvdLevelCount = (uint8_t)(mm_table->count);
1721 table->UvdBootLevel = 0;
1722
1723 for (count = 0; count < table->UvdLevelCount; count++) {
1724 table->UvdLevel[count].MinVoltage = 0;
1725 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1726 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1727 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1728 VOLTAGE_SCALE) << VDDC_SHIFT;
1729
1730 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1731 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1732 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1733 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1734 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1735 else
1736 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1737
1738 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1739 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1740
1741 /* retrieve divider value for VBIOS */
1742 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1743 table->UvdLevel[count].VclkFrequency, &dividers);
1744 PP_ASSERT_WITH_CODE((0 == result),
1745 "can not find divide id for Vclk clock", return result);
1746
1747 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1748
1749 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1750 table->UvdLevel[count].DclkFrequency, &dividers);
1751 PP_ASSERT_WITH_CODE((0 == result),
1752 "can not find divide id for Dclk clock", return result);
1753
1754 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1755
1756 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1757 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1758 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1759 }
1760
1761 return result;
1762 }
1763
1764 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1765 struct SMU74_Discrete_DpmTable *table)
1766 {
1767 int result = 0;
1768 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1769
1770 table->GraphicsBootLevel = 0;
1771 table->MemoryBootLevel = 0;
1772
1773 /* find boot level from dpm table */
1774 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1775 data->vbios_boot_state.sclk_bootup_value,
1776 (uint32_t *)&(table->GraphicsBootLevel));
1777
1778 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1779 data->vbios_boot_state.mclk_bootup_value,
1780 (uint32_t *)&(table->MemoryBootLevel));
1781
1782 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1783 VOLTAGE_SCALE;
1784 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1785 VOLTAGE_SCALE;
1786 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1787 VOLTAGE_SCALE;
1788
1789 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1790 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1791 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1792
1793 return 0;
1794 }
1795
1796
1797 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1798 {
1799 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1800 struct phm_ppt_v1_information *table_info =
1801 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1802 uint8_t count, level;
1803
1804 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1805
1806 for (level = 0; level < count; level++) {
1807 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1808 data->vbios_boot_state.sclk_bootup_value) {
1809 data->smc_state_table.GraphicsBootLevel = level;
1810 break;
1811 }
1812 }
1813
1814 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1815 for (level = 0; level < count; level++) {
1816 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1817 data->vbios_boot_state.mclk_bootup_value) {
1818 data->smc_state_table.MemoryBootLevel = level;
1819 break;
1820 }
1821 }
1822
1823 return 0;
1824 }
1825
1826 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1827 {
1828 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1829 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1830 uint8_t i, stretch_amount, volt_offset = 0;
1831 struct phm_ppt_v1_information *table_info =
1832 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1833 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1834 table_info->vdd_dep_on_sclk;
1835
1836 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1837
1838 /* Read SMU_Eefuse to read and calculate RO and determine
1839 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1840 */
1841 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1842 ixSMU_EFUSE_0 + (67 * 4));
1843 efuse &= 0xFF000000;
1844 efuse = efuse >> 24;
1845
1846 if (hwmgr->chip_id == CHIP_POLARIS10) {
1847 min = 1000;
1848 max = 2300;
1849 } else {
1850 min = 1100;
1851 max = 2100;
1852 }
1853
1854 ro = efuse * (max -min)/255 + min;
1855
1856 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1857 for (i = 0; i < sclk_table->count; i++) {
1858 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1859 sclk_table->entries[i].cks_enable << i;
1860 if (hwmgr->chip_id == CHIP_POLARIS10) {
1861 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1862 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1863 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1864 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1865 } else {
1866 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1867 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1868 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1869 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1870 }
1871
1872 if (volt_without_cks >= volt_with_cks)
1873 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1874 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1875
1876 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1877 }
1878
1879 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1880 /* Populate CKS Lookup Table */
1881 if (stretch_amount != 1 && stretch_amount != 2 && stretch_amount != 3 &&
1882 stretch_amount != 4 && stretch_amount != 5) {
1883 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1884 PHM_PlatformCaps_ClockStretcher);
1885 PP_ASSERT_WITH_CODE(false,
1886 "Stretch Amount in PPTable not supported\n",
1887 return -EINVAL);
1888 }
1889
1890 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1891 value &= 0xFFFFFFFE;
1892 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1893
1894 return 0;
1895 }
1896
1897 /**
1898 * Populates the SMC VRConfig field in DPM table.
1899 *
1900 * @param hwmgr the address of the hardware manager
1901 * @param table the SMC DPM table structure to be populated
1902 * @return always 0
1903 */
1904 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1905 struct SMU74_Discrete_DpmTable *table)
1906 {
1907 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1908 uint16_t config;
1909
1910 config = VR_MERGED_WITH_VDDC;
1911 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1912
1913 /* Set Vddc Voltage Controller */
1914 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1915 config = VR_SVI2_PLANE_1;
1916 table->VRConfig |= config;
1917 } else {
1918 PP_ASSERT_WITH_CODE(false,
1919 "VDDC should be on SVI2 control in merged mode!",
1920 );
1921 }
1922 /* Set Vddci Voltage Controller */
1923 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1924 config = VR_SVI2_PLANE_2; /* only in merged mode */
1925 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1926 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1927 config = VR_SMIO_PATTERN_1;
1928 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1929 } else {
1930 config = VR_STATIC_VOLTAGE;
1931 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1932 }
1933 /* Set Mvdd Voltage Controller */
1934 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1935 config = VR_SVI2_PLANE_2;
1936 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1937 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
1938 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1939 } else {
1940 config = VR_STATIC_VOLTAGE;
1941 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1942 }
1943
1944 return 0;
1945 }
1946
1947
1948 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1949 {
1950 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1951 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1952 int result = 0;
1953 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1954 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1955 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1956 uint32_t tmp, i;
1957 struct pp_smumgr *smumgr = hwmgr->smumgr;
1958 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1959
1960 struct phm_ppt_v1_information *table_info =
1961 (struct phm_ppt_v1_information *)hwmgr->pptable;
1962 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1963 table_info->vdd_dep_on_sclk;
1964
1965
1966 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1967 return result;
1968
1969 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1970
1971 if (0 == result) {
1972 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1973 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1974 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1975 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1976 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1977 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1978 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1979 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1980 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1981 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1982 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1983 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1984 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1985 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1986 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1987 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1988 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1989 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1990 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1991 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1992 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1993 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1994 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1995 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1996
1997 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1998 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1999 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
2000 }
2001
2002 result = polaris10_read_smc_sram_dword(smumgr,
2003 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
2004 &tmp, data->sram_end);
2005
2006 polaris10_copy_bytes_to_smc(smumgr,
2007 tmp,
2008 (uint8_t *)&AVFS_meanNsigma,
2009 sizeof(AVFS_meanNsigma_t),
2010 data->sram_end);
2011
2012 result = polaris10_read_smc_sram_dword(smumgr,
2013 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
2014 &tmp, data->sram_end);
2015 polaris10_copy_bytes_to_smc(smumgr,
2016 tmp,
2017 (uint8_t *)&AVFS_SclkOffset,
2018 sizeof(AVFS_Sclk_Offset_t),
2019 data->sram_end);
2020
2021 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2022 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2023 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2024 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2025 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2026 }
2027 return result;
2028 }
2029
2030
2031 /**
2032 * Initializes the SMC table and uploads it
2033 *
2034 * @param hwmgr the address of the powerplay hardware manager.
2035 * @return always 0
2036 */
2037 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2038 {
2039 int result;
2040 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2041 struct phm_ppt_v1_information *table_info =
2042 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2043 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2044 const struct polaris10_ulv_parm *ulv = &(data->ulv);
2045 uint8_t i;
2046 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2047 pp_atomctrl_clock_dividers_vi dividers;
2048
2049 result = polaris10_setup_default_dpm_tables(hwmgr);
2050 PP_ASSERT_WITH_CODE(0 == result,
2051 "Failed to setup default DPM tables!", return result);
2052
2053 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2054 polaris10_populate_smc_voltage_tables(hwmgr, table);
2055
2056 table->SystemFlags = 0;
2057 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2058 PHM_PlatformCaps_AutomaticDCTransition))
2059 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2060
2061 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2062 PHM_PlatformCaps_StepVddc))
2063 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2064
2065 if (data->is_memory_gddr5)
2066 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2067
2068 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2069 result = polaris10_populate_ulv_state(hwmgr, table);
2070 PP_ASSERT_WITH_CODE(0 == result,
2071 "Failed to initialize ULV state!", return result);
2072 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2073 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2074 }
2075
2076 result = polaris10_populate_smc_link_level(hwmgr, table);
2077 PP_ASSERT_WITH_CODE(0 == result,
2078 "Failed to initialize Link Level!", return result);
2079
2080 result = polaris10_populate_all_graphic_levels(hwmgr);
2081 PP_ASSERT_WITH_CODE(0 == result,
2082 "Failed to initialize Graphics Level!", return result);
2083
2084 result = polaris10_populate_all_memory_levels(hwmgr);
2085 PP_ASSERT_WITH_CODE(0 == result,
2086 "Failed to initialize Memory Level!", return result);
2087
2088 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2089 PP_ASSERT_WITH_CODE(0 == result,
2090 "Failed to initialize ACPI Level!", return result);
2091
2092 result = polaris10_populate_smc_vce_level(hwmgr, table);
2093 PP_ASSERT_WITH_CODE(0 == result,
2094 "Failed to initialize VCE Level!", return result);
2095
2096 result = polaris10_populate_smc_samu_level(hwmgr, table);
2097 PP_ASSERT_WITH_CODE(0 == result,
2098 "Failed to initialize SAMU Level!", return result);
2099
2100 /* Since only the initial state is completely set up at this point
2101 * (the other states are just copies of the boot state) we only
2102 * need to populate the ARB settings for the initial state.
2103 */
2104 result = polaris10_program_memory_timing_parameters(hwmgr);
2105 PP_ASSERT_WITH_CODE(0 == result,
2106 "Failed to Write ARB settings for the initial state.", return result);
2107
2108 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2109 PP_ASSERT_WITH_CODE(0 == result,
2110 "Failed to initialize UVD Level!", return result);
2111
2112 result = polaris10_populate_smc_boot_level(hwmgr, table);
2113 PP_ASSERT_WITH_CODE(0 == result,
2114 "Failed to initialize Boot Level!", return result);
2115
2116 result = polaris10_populate_smc_initailial_state(hwmgr);
2117 PP_ASSERT_WITH_CODE(0 == result,
2118 "Failed to initialize Boot State!", return result);
2119
2120 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2121 PP_ASSERT_WITH_CODE(0 == result,
2122 "Failed to populate BAPM Parameters!", return result);
2123
2124 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2125 PHM_PlatformCaps_ClockStretcher)) {
2126 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2127 PP_ASSERT_WITH_CODE(0 == result,
2128 "Failed to populate Clock Stretcher Data Table!",
2129 return result);
2130 }
2131
2132 result = polaris10_populate_avfs_parameters(hwmgr);
2133 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2134
2135 table->CurrSclkPllRange = 0xff;
2136 table->GraphicsVoltageChangeEnable = 1;
2137 table->GraphicsThermThrottleEnable = 1;
2138 table->GraphicsInterval = 1;
2139 table->VoltageInterval = 1;
2140 table->ThermalInterval = 1;
2141 table->TemperatureLimitHigh =
2142 table_info->cac_dtp_table->usTargetOperatingTemp *
2143 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2144 table->TemperatureLimitLow =
2145 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2146 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2147 table->MemoryVoltageChangeEnable = 1;
2148 table->MemoryInterval = 1;
2149 table->VoltageResponseTime = 0;
2150 table->PhaseResponseTime = 0;
2151 table->MemoryThermThrottleEnable = 1;
2152 table->PCIeBootLinkLevel = 0;
2153 table->PCIeGenInterval = 1;
2154 table->VRConfig = 0;
2155
2156 result = polaris10_populate_vr_config(hwmgr, table);
2157 PP_ASSERT_WITH_CODE(0 == result,
2158 "Failed to populate VRConfig setting!", return result);
2159
2160 table->ThermGpio = 17;
2161 table->SclkStepSize = 0x4000;
2162
2163 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2164 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2165 } else {
2166 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2167 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2168 PHM_PlatformCaps_RegulatorHot);
2169 }
2170
2171 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2172 &gpio_pin)) {
2173 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2174 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2175 PHM_PlatformCaps_AutomaticDCTransition);
2176 } else {
2177 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2178 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2179 PHM_PlatformCaps_AutomaticDCTransition);
2180 }
2181
2182 /* Thermal Output GPIO */
2183 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2184 &gpio_pin)) {
2185 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2186 PHM_PlatformCaps_ThermalOutGPIO);
2187
2188 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2189
2190 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2191 * since VBIOS will program this register to set 'inactive state',
2192 * driver can then determine 'active state' from this and
2193 * program SMU with correct polarity
2194 */
2195 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2196 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2197 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2198
2199 /* if required, combine VRHot/PCC with thermal out GPIO */
2200 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2201 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2202 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2203 } else {
2204 table->ThermOutGpio = 17;
2205 table->ThermOutPolarity = 1;
2206 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2207 }
2208
2209 /* Populate BIF_SCLK levels into SMC DPM table */
2210 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2211 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2212 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2213
2214 if (i == 0)
2215 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2216 else
2217 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2218 }
2219
2220 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2221 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2222
2223 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2224 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2225 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2226 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2227 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2228 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2229 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2230 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2231 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2232 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2233
2234 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2235 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2236 data->dpm_table_start +
2237 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2238 (uint8_t *)&(table->SystemFlags),
2239 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2240 data->sram_end);
2241 PP_ASSERT_WITH_CODE(0 == result,
2242 "Failed to upload dpm data to SMC memory!", return result);
2243
2244 return 0;
2245 }
2246
2247 /**
2248 * Initialize the ARB DRAM timing table's index field.
2249 *
2250 * @param hwmgr the address of the powerplay hardware manager.
2251 * @return always 0
2252 */
2253 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2254 {
2255 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2256 uint32_t tmp;
2257 int result;
2258
2259 /* This is a read-modify-write on the first byte of the ARB table.
2260 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2261 * is the field 'current'.
2262 * This solution is ugly, but we never write the whole table only
2263 * individual fields in it.
2264 * In reality this field should not be in that structure
2265 * but in a soft register.
2266 */
2267 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2268 data->arb_table_start, &tmp, data->sram_end);
2269
2270 if (result)
2271 return result;
2272
2273 tmp &= 0x00FFFFFF;
2274 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2275
2276 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2277 data->arb_table_start, tmp, data->sram_end);
2278 }
2279
2280 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2281 {
2282 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2283 PHM_PlatformCaps_RegulatorHot))
2284 return smum_send_msg_to_smc(hwmgr->smumgr,
2285 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2286
2287 return 0;
2288 }
2289
2290 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2291 {
2292 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2293 SCLK_PWRMGT_OFF, 0);
2294 return 0;
2295 }
2296
2297 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2298 {
2299 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2300 struct polaris10_ulv_parm *ulv = &(data->ulv);
2301
2302 if (ulv->ulv_supported)
2303 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2304
2305 return 0;
2306 }
2307
2308 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2309 {
2310 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2311 struct polaris10_ulv_parm *ulv = &(data->ulv);
2312
2313 if (ulv->ulv_supported)
2314 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2315
2316 return 0;
2317 }
2318
2319 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2320 {
2321 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2322 PHM_PlatformCaps_SclkDeepSleep)) {
2323 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2324 PP_ASSERT_WITH_CODE(false,
2325 "Attempt to enable Master Deep Sleep switch failed!",
2326 return -1);
2327 } else {
2328 if (smum_send_msg_to_smc(hwmgr->smumgr,
2329 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2330 PP_ASSERT_WITH_CODE(false,
2331 "Attempt to disable Master Deep Sleep switch failed!",
2332 return -1);
2333 }
2334 }
2335
2336 return 0;
2337 }
2338
2339 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2340 {
2341 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2342 PHM_PlatformCaps_SclkDeepSleep)) {
2343 if (smum_send_msg_to_smc(hwmgr->smumgr,
2344 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2345 PP_ASSERT_WITH_CODE(false,
2346 "Attempt to disable Master Deep Sleep switch failed!",
2347 return -1);
2348 }
2349 }
2350
2351 return 0;
2352 }
2353
2354 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2355 {
2356 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2357 uint32_t soft_register_value = 0;
2358 uint32_t handshake_disables_offset = data->soft_regs_start
2359 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2360
2361 /* enable SCLK dpm */
2362 if (!data->sclk_dpm_key_disabled)
2363 PP_ASSERT_WITH_CODE(
2364 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2365 "Failed to enable SCLK DPM during DPM Start Function!",
2366 return -1);
2367
2368 /* enable MCLK dpm */
2369 if (0 == data->mclk_dpm_key_disabled) {
2370 /* Disable UVD - SMU handshake for MCLK. */
2371 soft_register_value = cgs_read_ind_register(hwmgr->device,
2372 CGS_IND_REG__SMC, handshake_disables_offset);
2373 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2375 handshake_disables_offset, soft_register_value);
2376
2377 PP_ASSERT_WITH_CODE(
2378 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2379 PPSMC_MSG_MCLKDPM_Enable)),
2380 "Failed to enable MCLK DPM during DPM Start Function!",
2381 return -1);
2382
2383 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2384
2385 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2387 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2388 udelay(10);
2389 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2390 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2391 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2392 }
2393
2394 return 0;
2395 }
2396
2397 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2398 {
2399 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2400
2401 /*enable general power management */
2402
2403 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2404 GLOBAL_PWRMGT_EN, 1);
2405
2406 /* enable sclk deep sleep */
2407
2408 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2409 DYNAMIC_PM_EN, 1);
2410
2411 /* prepare for PCIE DPM */
2412
2413 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2414 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2415 VoltageChangeTimeout), 0x1000);
2416 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2417 SWRST_COMMAND_1, RESETLC, 0x0);
2418 /*
2419 PP_ASSERT_WITH_CODE(
2420 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2421 PPSMC_MSG_Voltage_Cntl_Enable)),
2422 "Failed to enable voltage DPM during DPM Start Function!",
2423 return -1);
2424 */
2425
2426 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2427 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2428 return -1;
2429 }
2430
2431 /* enable PCIE dpm */
2432 if (0 == data->pcie_dpm_key_disabled) {
2433 PP_ASSERT_WITH_CODE(
2434 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2435 PPSMC_MSG_PCIeDPM_Enable)),
2436 "Failed to enable pcie DPM during DPM Start Function!",
2437 return -1);
2438 }
2439
2440 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2441 PHM_PlatformCaps_Falcon_QuickTransition)) {
2442 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2443 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2444 "Failed to enable AC DC GPIO Interrupt!",
2445 );
2446 }
2447
2448 return 0;
2449 }
2450
2451 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2452 {
2453 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2454
2455 /* disable SCLK dpm */
2456 if (!data->sclk_dpm_key_disabled)
2457 PP_ASSERT_WITH_CODE(
2458 (smum_send_msg_to_smc(hwmgr->smumgr,
2459 PPSMC_MSG_DPM_Disable) == 0),
2460 "Failed to disable SCLK DPM!",
2461 return -1);
2462
2463 /* disable MCLK dpm */
2464 if (!data->mclk_dpm_key_disabled) {
2465 PP_ASSERT_WITH_CODE(
2466 (smum_send_msg_to_smc(hwmgr->smumgr,
2467 PPSMC_MSG_MCLKDPM_Disable) == 0),
2468 "Failed to disable MCLK DPM!",
2469 return -1);
2470 }
2471
2472 return 0;
2473 }
2474
2475 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2476 {
2477 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2478
2479 /* disable general power management */
2480 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2481 GLOBAL_PWRMGT_EN, 0);
2482 /* disable sclk deep sleep */
2483 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2484 DYNAMIC_PM_EN, 0);
2485
2486 /* disable PCIE dpm */
2487 if (!data->pcie_dpm_key_disabled) {
2488 PP_ASSERT_WITH_CODE(
2489 (smum_send_msg_to_smc(hwmgr->smumgr,
2490 PPSMC_MSG_PCIeDPM_Disable) == 0),
2491 "Failed to disable pcie DPM during DPM Stop Function!",
2492 return -1);
2493 }
2494
2495 if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2496 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2497 return -1;
2498 }
2499
2500 return 0;
2501 }
2502
2503 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2504 {
2505 bool protection;
2506 enum DPM_EVENT_SRC src;
2507
2508 switch (sources) {
2509 default:
2510 printk(KERN_ERR "Unknown throttling event sources.");
2511 /* fall through */
2512 case 0:
2513 protection = false;
2514 /* src is unused */
2515 break;
2516 case (1 << PHM_AutoThrottleSource_Thermal):
2517 protection = true;
2518 src = DPM_EVENT_SRC_DIGITAL;
2519 break;
2520 case (1 << PHM_AutoThrottleSource_External):
2521 protection = true;
2522 src = DPM_EVENT_SRC_EXTERNAL;
2523 break;
2524 case (1 << PHM_AutoThrottleSource_External) |
2525 (1 << PHM_AutoThrottleSource_Thermal):
2526 protection = true;
2527 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2528 break;
2529 }
2530 /* Order matters - don't enable thermal protection for the wrong source. */
2531 if (protection) {
2532 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2533 DPM_EVENT_SRC, src);
2534 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2535 THERMAL_PROTECTION_DIS,
2536 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2537 PHM_PlatformCaps_ThermalController));
2538 } else
2539 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2540 THERMAL_PROTECTION_DIS, 1);
2541 }
2542
2543 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2544 PHM_AutoThrottleSource source)
2545 {
2546 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2547
2548 if (!(data->active_auto_throttle_sources & (1 << source))) {
2549 data->active_auto_throttle_sources |= 1 << source;
2550 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2551 }
2552 return 0;
2553 }
2554
2555 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2556 {
2557 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2558 }
2559
2560 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2561 PHM_AutoThrottleSource source)
2562 {
2563 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2564
2565 if (data->active_auto_throttle_sources & (1 << source)) {
2566 data->active_auto_throttle_sources &= ~(1 << source);
2567 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2568 }
2569 return 0;
2570 }
2571
2572 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2573 {
2574 return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2575 }
2576
2577 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2578 {
2579 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2580 data->pcie_performance_request = true;
2581
2582 return 0;
2583 }
2584
2585 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2586 {
2587 int tmp_result, result = 0;
2588 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2589 PP_ASSERT_WITH_CODE(result == 0,
2590 "DPM is already running right now, no need to enable DPM!",
2591 return 0);
2592
2593 if (polaris10_voltage_control(hwmgr)) {
2594 tmp_result = polaris10_enable_voltage_control(hwmgr);
2595 PP_ASSERT_WITH_CODE(tmp_result == 0,
2596 "Failed to enable voltage control!",
2597 result = tmp_result);
2598
2599 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2600 PP_ASSERT_WITH_CODE((0 == tmp_result),
2601 "Failed to contruct voltage tables!",
2602 result = tmp_result);
2603 }
2604
2605 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2606 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2607 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2608 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2609
2610 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2611 PHM_PlatformCaps_ThermalController))
2612 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2613 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2614
2615 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2616 PP_ASSERT_WITH_CODE((0 == tmp_result),
2617 "Failed to program static screen threshold parameters!",
2618 result = tmp_result);
2619
2620 tmp_result = polaris10_enable_display_gap(hwmgr);
2621 PP_ASSERT_WITH_CODE((0 == tmp_result),
2622 "Failed to enable display gap!", result = tmp_result);
2623
2624 tmp_result = polaris10_program_voting_clients(hwmgr);
2625 PP_ASSERT_WITH_CODE((0 == tmp_result),
2626 "Failed to program voting clients!", result = tmp_result);
2627
2628 tmp_result = polaris10_process_firmware_header(hwmgr);
2629 PP_ASSERT_WITH_CODE((0 == tmp_result),
2630 "Failed to process firmware header!", result = tmp_result);
2631
2632 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2633 PP_ASSERT_WITH_CODE((0 == tmp_result),
2634 "Failed to initialize switch from ArbF0 to F1!",
2635 result = tmp_result);
2636
2637 tmp_result = polaris10_init_smc_table(hwmgr);
2638 PP_ASSERT_WITH_CODE((0 == tmp_result),
2639 "Failed to initialize SMC table!", result = tmp_result);
2640
2641 tmp_result = polaris10_init_arb_table_index(hwmgr);
2642 PP_ASSERT_WITH_CODE((0 == tmp_result),
2643 "Failed to initialize ARB table index!", result = tmp_result);
2644
2645 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2646 PP_ASSERT_WITH_CODE((0 == tmp_result),
2647 "Failed to populate PM fuses!", result = tmp_result);
2648
2649 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2650 PP_ASSERT_WITH_CODE((0 == tmp_result),
2651 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2652
2653 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2654
2655 tmp_result = polaris10_enable_sclk_control(hwmgr);
2656 PP_ASSERT_WITH_CODE((0 == tmp_result),
2657 "Failed to enable SCLK control!", result = tmp_result);
2658
2659 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2660 PP_ASSERT_WITH_CODE((0 == tmp_result),
2661 "Failed to enable voltage control!", result = tmp_result);
2662
2663 tmp_result = polaris10_enable_ulv(hwmgr);
2664 PP_ASSERT_WITH_CODE((0 == tmp_result),
2665 "Failed to enable ULV!", result = tmp_result);
2666
2667 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2668 PP_ASSERT_WITH_CODE((0 == tmp_result),
2669 "Failed to enable deep sleep master switch!", result = tmp_result);
2670
2671 tmp_result = polaris10_enable_didt_config(hwmgr);
2672 PP_ASSERT_WITH_CODE((tmp_result == 0),
2673 "Failed to enable deep sleep master switch!", result = tmp_result);
2674
2675 tmp_result = polaris10_start_dpm(hwmgr);
2676 PP_ASSERT_WITH_CODE((0 == tmp_result),
2677 "Failed to start DPM!", result = tmp_result);
2678
2679 tmp_result = polaris10_enable_smc_cac(hwmgr);
2680 PP_ASSERT_WITH_CODE((0 == tmp_result),
2681 "Failed to enable SMC CAC!", result = tmp_result);
2682
2683 tmp_result = polaris10_enable_power_containment(hwmgr);
2684 PP_ASSERT_WITH_CODE((0 == tmp_result),
2685 "Failed to enable power containment!", result = tmp_result);
2686
2687 tmp_result = polaris10_power_control_set_level(hwmgr);
2688 PP_ASSERT_WITH_CODE((0 == tmp_result),
2689 "Failed to power control set level!", result = tmp_result);
2690
2691 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2692 PP_ASSERT_WITH_CODE((0 == tmp_result),
2693 "Failed to enable thermal auto throttle!", result = tmp_result);
2694
2695 tmp_result = polaris10_pcie_performance_request(hwmgr);
2696 PP_ASSERT_WITH_CODE((0 == tmp_result),
2697 "pcie performance request failed!", result = tmp_result);
2698
2699 return result;
2700 }
2701
2702 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2703 {
2704 int tmp_result, result = 0;
2705
2706 tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2707 PP_ASSERT_WITH_CODE(tmp_result == 0,
2708 "DPM is not running right now, no need to disable DPM!",
2709 return 0);
2710
2711 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2712 PHM_PlatformCaps_ThermalController))
2713 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2714 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2715
2716 tmp_result = polaris10_disable_power_containment(hwmgr);
2717 PP_ASSERT_WITH_CODE((tmp_result == 0),
2718 "Failed to disable power containment!", result = tmp_result);
2719
2720 tmp_result = polaris10_disable_smc_cac(hwmgr);
2721 PP_ASSERT_WITH_CODE((tmp_result == 0),
2722 "Failed to disable SMC CAC!", result = tmp_result);
2723
2724 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2725 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2726 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2727 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2728
2729 tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2730 PP_ASSERT_WITH_CODE((tmp_result == 0),
2731 "Failed to disable thermal auto throttle!", result = tmp_result);
2732
2733 tmp_result = polaris10_stop_dpm(hwmgr);
2734 PP_ASSERT_WITH_CODE((tmp_result == 0),
2735 "Failed to stop DPM!", result = tmp_result);
2736
2737 tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2738 PP_ASSERT_WITH_CODE((tmp_result == 0),
2739 "Failed to disable deep sleep master switch!", result = tmp_result);
2740
2741 tmp_result = polaris10_disable_ulv(hwmgr);
2742 PP_ASSERT_WITH_CODE((tmp_result == 0),
2743 "Failed to disable ULV!", result = tmp_result);
2744
2745 tmp_result = polaris10_clear_voting_clients(hwmgr);
2746 PP_ASSERT_WITH_CODE((tmp_result == 0),
2747 "Failed to clear voting clients!", result = tmp_result);
2748
2749 tmp_result = polaris10_reset_to_default(hwmgr);
2750 PP_ASSERT_WITH_CODE((tmp_result == 0),
2751 "Failed to reset to default!", result = tmp_result);
2752
2753 tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2754 PP_ASSERT_WITH_CODE((tmp_result == 0),
2755 "Failed to force to switch arbf0!", result = tmp_result);
2756
2757 return result;
2758 }
2759
2760 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2761 {
2762
2763 return 0;
2764 }
2765
2766 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2767 {
2768 return phm_hwmgr_backend_fini(hwmgr);
2769 }
2770
2771 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2772 {
2773 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2774
2775 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2776 PHM_PlatformCaps_SclkDeepSleep);
2777
2778 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2779 PHM_PlatformCaps_DynamicPatchPowerState);
2780
2781 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2782 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2783 PHM_PlatformCaps_EnableMVDDControl);
2784
2785 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2786 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2787 PHM_PlatformCaps_ControlVDDCI);
2788
2789 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2790 PHM_PlatformCaps_TablelessHardwareInterface);
2791
2792 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2793 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2794
2795 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2796 PHM_PlatformCaps_DynamicPowerManagement);
2797
2798 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2799 PHM_PlatformCaps_UnTabledHardwareInterface);
2800
2801 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2802 PHM_PlatformCaps_TablelessHardwareInterface);
2803
2804 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2805 PHM_PlatformCaps_SMC);
2806
2807 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2808 PHM_PlatformCaps_NonABMSupportInPPLib);
2809
2810 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2811 PHM_PlatformCaps_DynamicUVDState);
2812
2813 /* power tune caps Assume disabled */
2814 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2815 PHM_PlatformCaps_SQRamping);
2816 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2817 PHM_PlatformCaps_DBRamping);
2818 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2819 PHM_PlatformCaps_TDRamping);
2820 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2821 PHM_PlatformCaps_TCPRamping);
2822
2823 if (hwmgr->powercontainment_enabled)
2824 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2825 PHM_PlatformCaps_PowerContainment);
2826 else
2827 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2828 PHM_PlatformCaps_PowerContainment);
2829
2830 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2831 PHM_PlatformCaps_CAC);
2832
2833 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2834 PHM_PlatformCaps_RegulatorHot);
2835
2836 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2837 PHM_PlatformCaps_AutomaticDCTransition);
2838
2839 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2840 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2841
2842 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2843 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2844
2845 if (hwmgr->chip_id == CHIP_POLARIS11)
2846 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2847 PHM_PlatformCaps_SPLLShutdownSupport);
2848 return 0;
2849 }
2850
2851 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2852 {
2853 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2854
2855 polaris10_initialize_power_tune_defaults(hwmgr);
2856
2857 data->pcie_gen_performance.max = PP_PCIEGen1;
2858 data->pcie_gen_performance.min = PP_PCIEGen3;
2859 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2860 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2861 data->pcie_lane_performance.max = 0;
2862 data->pcie_lane_performance.min = 16;
2863 data->pcie_lane_power_saving.max = 0;
2864 data->pcie_lane_power_saving.min = 16;
2865 }
2866
2867 /**
2868 * Get Leakage VDDC based on leakage ID.
2869 *
2870 * @param hwmgr the address of the powerplay hardware manager.
2871 * @return always 0
2872 */
2873 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2874 {
2875 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2876 uint16_t vv_id;
2877 uint32_t vddc = 0;
2878 uint16_t i, j;
2879 uint32_t sclk = 0;
2880 struct phm_ppt_v1_information *table_info =
2881 (struct phm_ppt_v1_information *)hwmgr->pptable;
2882 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2883 table_info->vdd_dep_on_sclk;
2884 int result;
2885
2886 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2887 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2888 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2889 table_info->vddc_lookup_table, vv_id, &sclk)) {
2890 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2891 PHM_PlatformCaps_ClockStretcher)) {
2892 for (j = 1; j < sclk_table->count; j++) {
2893 if (sclk_table->entries[j].clk == sclk &&
2894 sclk_table->entries[j].cks_enable == 0) {
2895 sclk += 5000;
2896 break;
2897 }
2898 }
2899 }
2900
2901 if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2902 VOLTAGE_TYPE_VDDC,
2903 sclk, vv_id, &vddc) != 0) {
2904 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
2905 continue;
2906 }
2907
2908 /* need to make sure vddc is less than 2v or else, it could burn the ASIC.
2909 * real voltage level in unit of 0.01mv */
2910 PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
2911 "Invalid VDDC value", result = -EINVAL;);
2912
2913 /* the voltage should not be zero nor equal to leakage ID */
2914 if (vddc != 0 && vddc != vv_id) {
2915 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2916 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2917 data->vddc_leakage.count++;
2918 }
2919 }
2920 }
2921
2922 return 0;
2923 }
2924
2925 /**
2926 * Change virtual leakage voltage to actual value.
2927 *
2928 * @param hwmgr the address of the powerplay hardware manager.
2929 * @param pointer to changing voltage
2930 * @param pointer to leakage table
2931 */
2932 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2933 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2934 {
2935 uint32_t index;
2936
2937 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2938 for (index = 0; index < leakage_table->count; index++) {
2939 /* if this voltage matches a leakage voltage ID */
2940 /* patch with actual leakage voltage */
2941 if (leakage_table->leakage_id[index] == *voltage) {
2942 *voltage = leakage_table->actual_voltage[index];
2943 break;
2944 }
2945 }
2946
2947 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2948 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2949 }
2950
2951 /**
2952 * Patch voltage lookup table by EVV leakages.
2953 *
2954 * @param hwmgr the address of the powerplay hardware manager.
2955 * @param pointer to voltage lookup table
2956 * @param pointer to leakage table
2957 * @return always 0
2958 */
2959 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2960 phm_ppt_v1_voltage_lookup_table *lookup_table,
2961 struct polaris10_leakage_voltage *leakage_table)
2962 {
2963 uint32_t i;
2964
2965 for (i = 0; i < lookup_table->count; i++)
2966 polaris10_patch_with_vdd_leakage(hwmgr,
2967 &lookup_table->entries[i].us_vdd, leakage_table);
2968
2969 return 0;
2970 }
2971
2972 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2973 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2974 uint16_t *vddc)
2975 {
2976 struct phm_ppt_v1_information *table_info =
2977 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2978 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2979 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2980 table_info->max_clock_voltage_on_dc.vddc;
2981 return 0;
2982 }
2983
2984 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2985 struct pp_hwmgr *hwmgr)
2986 {
2987 uint8_t entryId;
2988 uint8_t voltageId;
2989 struct phm_ppt_v1_information *table_info =
2990 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2991
2992 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2993 table_info->vdd_dep_on_sclk;
2994 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2995 table_info->vdd_dep_on_mclk;
2996 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2997 table_info->mm_dep_table;
2998
2999 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3000 voltageId = sclk_table->entries[entryId].vddInd;
3001 sclk_table->entries[entryId].vddc =
3002 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3003 }
3004
3005 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3006 voltageId = mclk_table->entries[entryId].vddInd;
3007 mclk_table->entries[entryId].vddc =
3008 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3009 }
3010
3011 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3012 voltageId = mm_table->entries[entryId].vddcInd;
3013 mm_table->entries[entryId].vddc =
3014 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3015 }
3016
3017 return 0;
3018
3019 }
3020
3021 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3022 {
3023 /* Need to determine if we need calculated voltage. */
3024 return 0;
3025 }
3026
3027 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3028 {
3029 /* Need to determine if we need calculated voltage from mm table. */
3030 return 0;
3031 }
3032
3033 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3034 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3035 {
3036 uint32_t table_size, i, j;
3037 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3038 table_size = lookup_table->count;
3039
3040 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3041 "Lookup table is empty", return -EINVAL);
3042
3043 /* Sorting voltages */
3044 for (i = 0; i < table_size - 1; i++) {
3045 for (j = i + 1; j > 0; j--) {
3046 if (lookup_table->entries[j].us_vdd <
3047 lookup_table->entries[j - 1].us_vdd) {
3048 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3049 lookup_table->entries[j - 1] = lookup_table->entries[j];
3050 lookup_table->entries[j] = tmp_voltage_lookup_record;
3051 }
3052 }
3053 }
3054
3055 return 0;
3056 }
3057
3058 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3059 {
3060 int result = 0;
3061 int tmp_result;
3062 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3063 struct phm_ppt_v1_information *table_info =
3064 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3065
3066 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3067 table_info->vddc_lookup_table, &(data->vddc_leakage));
3068 if (tmp_result)
3069 result = tmp_result;
3070
3071 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3072 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3073 if (tmp_result)
3074 result = tmp_result;
3075
3076 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3077 if (tmp_result)
3078 result = tmp_result;
3079
3080 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3081 if (tmp_result)
3082 result = tmp_result;
3083
3084 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3085 if (tmp_result)
3086 result = tmp_result;
3087
3088 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3089 if (tmp_result)
3090 result = tmp_result;
3091
3092 return result;
3093 }
3094
3095 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3096 {
3097 struct phm_ppt_v1_information *table_info =
3098 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3099
3100 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3101 table_info->vdd_dep_on_sclk;
3102 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3103 table_info->vdd_dep_on_mclk;
3104
3105 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3106 "VDD dependency on SCLK table is missing. \
3107 This table is mandatory", return -EINVAL);
3108 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3109 "VDD dependency on SCLK table has to have is missing. \
3110 This table is mandatory", return -EINVAL);
3111
3112 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3113 "VDD dependency on MCLK table is missing. \
3114 This table is mandatory", return -EINVAL);
3115 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3116 "VDD dependency on MCLK table has to have is missing. \
3117 This table is mandatory", return -EINVAL);
3118
3119 table_info->max_clock_voltage_on_ac.sclk =
3120 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3121 table_info->max_clock_voltage_on_ac.mclk =
3122 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3123 table_info->max_clock_voltage_on_ac.vddc =
3124 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3125 table_info->max_clock_voltage_on_ac.vddci =
3126 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3127
3128 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3129 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3130 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3131 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3132
3133 return 0;
3134 }
3135
3136 int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
3137 {
3138 struct phm_ppt_v1_information *table_info =
3139 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3140 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3141 table_info->vdd_dep_on_mclk;
3142 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
3143 table_info->vddc_lookup_table;
3144 uint32_t i;
3145
3146 if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
3147 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
3148 return 0;
3149
3150 for (i = 0; i < lookup_table->count; i++) {
3151 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
3152 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
3153 return 0;
3154 }
3155 }
3156 }
3157 return 0;
3158 }
3159
3160
3161 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3162 {
3163 struct polaris10_hwmgr *data;
3164 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3165 uint32_t temp_reg;
3166 int result;
3167 struct phm_ppt_v1_information *table_info =
3168 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3169
3170 data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3171 if (data == NULL)
3172 return -ENOMEM;
3173
3174 hwmgr->backend = data;
3175
3176 data->dll_default_on = false;
3177 data->sram_end = SMC_RAM_END;
3178 data->mclk_dpm0_activity_target = 0xa;
3179 data->disable_dpm_mask = 0xFF;
3180 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3181 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3182 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3183 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3184 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3185 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3186 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3187 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3188 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3189 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3190
3191 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3192 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3193 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3194 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3195 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3196 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3197 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3198 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3199
3200 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3201
3202 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3203
3204 /* need to set voltage control types before EVV patching */
3205 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3206 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3207 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3208
3209 data->enable_tdc_limit_feature = true;
3210 data->enable_pkg_pwr_tracking_feature = true;
3211 data->force_pcie_gen = PP_PCIEGenInvalid;
3212 data->mclk_stutter_mode_threshold = 40000;
3213
3214 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3215 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3216 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3217
3218 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3219 PHM_PlatformCaps_EnableMVDDControl)) {
3220 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3221 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3222 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3223 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3224 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3225 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3226 }
3227
3228 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3229 PHM_PlatformCaps_ControlVDDCI)) {
3230 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3231 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3232 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3233 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3234 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3235 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3236 }
3237
3238 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3240 PHM_PlatformCaps_ClockStretcher);
3241
3242 polaris10_set_features_platform_caps(hwmgr);
3243
3244 polaris10_patch_voltage_workaround(hwmgr);
3245 polaris10_init_dpm_defaults(hwmgr);
3246
3247 /* Get leakage voltage based on leakage ID. */
3248 result = polaris10_get_evv_voltages(hwmgr);
3249
3250 if (result) {
3251 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3252 return -1;
3253 }
3254
3255 polaris10_complete_dependency_tables(hwmgr);
3256 polaris10_set_private_data_based_on_pptable(hwmgr);
3257
3258 /* Initalize Dynamic State Adjustment Rule Settings */
3259 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3260
3261 if (0 == result) {
3262 struct cgs_system_info sys_info = {0};
3263
3264 data->is_tlu_enabled = false;
3265
3266 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3267 POLARIS10_MAX_HARDWARE_POWERLEVELS;
3268 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3269 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3270
3271
3272 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3273 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3274 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3275 case 0:
3276 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3277 break;
3278 case 1:
3279 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3280 break;
3281 case 2:
3282 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3283 break;
3284 case 3:
3285 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3286 break;
3287 case 4:
3288 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3289 break;
3290 default:
3291 PP_ASSERT_WITH_CODE(0,
3292 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3293 );
3294 break;
3295 }
3296 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3297 }
3298
3299 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3300 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3301 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3302 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3303
3304 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3305 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3306
3307 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3308
3309 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3310
3311 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3312 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3313
3314 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3315
3316 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3317 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3318
3319 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3320 table_info->cac_dtp_table->usOperatingTempStep = 1;
3321 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3322
3323 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3324 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3325
3326 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3327 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3328
3329 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3330 table_info->cac_dtp_table->usOperatingTempMinLimit;
3331
3332 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3333 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3334
3335 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3336 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3337
3338 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3339 table_info->cac_dtp_table->usOperatingTempStep;
3340
3341 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3342 table_info->cac_dtp_table->usTargetOperatingTemp;
3343 }
3344
3345 sys_info.size = sizeof(struct cgs_system_info);
3346 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3347 result = cgs_query_system_info(hwmgr->device, &sys_info);
3348 if (result)
3349 data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3350 else
3351 data->pcie_gen_cap = (uint32_t)sys_info.value;
3352 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3353 data->pcie_spc_cap = 20;
3354 sys_info.size = sizeof(struct cgs_system_info);
3355 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3356 result = cgs_query_system_info(hwmgr->device, &sys_info);
3357 if (result)
3358 data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3359 else
3360 data->pcie_lane_cap = (uint32_t)sys_info.value;
3361
3362 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3363 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3364 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3365 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3366 } else {
3367 /* Ignore return value in here, we are cleaning up a mess. */
3368 polaris10_hwmgr_backend_fini(hwmgr);
3369 }
3370
3371 return 0;
3372 }
3373
3374 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3375 {
3376 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3377 uint32_t level, tmp;
3378
3379 if (!data->pcie_dpm_key_disabled) {
3380 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3381 level = 0;
3382 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3383 while (tmp >>= 1)
3384 level++;
3385
3386 if (level)
3387 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3388 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3389 }
3390 }
3391
3392 if (!data->sclk_dpm_key_disabled) {
3393 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3394 level = 0;
3395 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3396 while (tmp >>= 1)
3397 level++;
3398
3399 if (level)
3400 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3401 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3402 (1 << level));
3403 }
3404 }
3405
3406 if (!data->mclk_dpm_key_disabled) {
3407 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3408 level = 0;
3409 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3410 while (tmp >>= 1)
3411 level++;
3412
3413 if (level)
3414 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3415 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3416 (1 << level));
3417 }
3418 }
3419
3420 return 0;
3421 }
3422
3423 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3424 {
3425 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3426
3427 phm_apply_dal_min_voltage_request(hwmgr);
3428
3429 if (!data->sclk_dpm_key_disabled) {
3430 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3431 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3432 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3433 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3434 }
3435
3436 if (!data->mclk_dpm_key_disabled) {
3437 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3438 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3439 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3440 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3441 }
3442
3443 return 0;
3444 }
3445
3446 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3447 {
3448 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3449
3450 if (!polaris10_is_dpm_running(hwmgr))
3451 return -EINVAL;
3452
3453 if (!data->pcie_dpm_key_disabled) {
3454 smum_send_msg_to_smc(hwmgr->smumgr,
3455 PPSMC_MSG_PCIeDPM_UnForceLevel);
3456 }
3457
3458 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3459 }
3460
3461 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3462 {
3463 struct polaris10_hwmgr *data =
3464 (struct polaris10_hwmgr *)(hwmgr->backend);
3465 uint32_t level;
3466
3467 if (!data->sclk_dpm_key_disabled)
3468 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3469 level = phm_get_lowest_enabled_level(hwmgr,
3470 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3471 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3472 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3473 (1 << level));
3474
3475 }
3476
3477 if (!data->mclk_dpm_key_disabled) {
3478 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3479 level = phm_get_lowest_enabled_level(hwmgr,
3480 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3481 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3482 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3483 (1 << level));
3484 }
3485 }
3486
3487 if (!data->pcie_dpm_key_disabled) {
3488 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3489 level = phm_get_lowest_enabled_level(hwmgr,
3490 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3491 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3492 PPSMC_MSG_PCIeDPM_ForceLevel,
3493 (level));
3494 }
3495 }
3496
3497 return 0;
3498
3499 }
3500 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3501 enum amd_dpm_forced_level level)
3502 {
3503 int ret = 0;
3504
3505 switch (level) {
3506 case AMD_DPM_FORCED_LEVEL_HIGH:
3507 ret = polaris10_force_dpm_highest(hwmgr);
3508 if (ret)
3509 return ret;
3510 break;
3511 case AMD_DPM_FORCED_LEVEL_LOW:
3512 ret = polaris10_force_dpm_lowest(hwmgr);
3513 if (ret)
3514 return ret;
3515 break;
3516 case AMD_DPM_FORCED_LEVEL_AUTO:
3517 ret = polaris10_unforce_dpm_levels(hwmgr);
3518 if (ret)
3519 return ret;
3520 break;
3521 default:
3522 break;
3523 }
3524
3525 hwmgr->dpm_level = level;
3526
3527 return ret;
3528 }
3529
3530 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3531 {
3532 return sizeof(struct polaris10_power_state);
3533 }
3534
3535
3536 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3537 struct pp_power_state *request_ps,
3538 const struct pp_power_state *current_ps)
3539 {
3540
3541 struct polaris10_power_state *polaris10_ps =
3542 cast_phw_polaris10_power_state(&request_ps->hardware);
3543 uint32_t sclk;
3544 uint32_t mclk;
3545 struct PP_Clocks minimum_clocks = {0};
3546 bool disable_mclk_switching;
3547 bool disable_mclk_switching_for_frame_lock;
3548 struct cgs_display_info info = {0};
3549 const struct phm_clock_and_voltage_limits *max_limits;
3550 uint32_t i;
3551 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3552 struct phm_ppt_v1_information *table_info =
3553 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3554 int32_t count;
3555 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3556
3557 data->battery_state = (PP_StateUILabel_Battery ==
3558 request_ps->classification.ui_label);
3559
3560 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3561 "VI should always have 2 performance levels",
3562 );
3563
3564 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3565 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3566 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3567
3568 /* Cap clock DPM tables at DC MAX if it is in DC. */
3569 if (PP_PowerSource_DC == hwmgr->power_source) {
3570 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3571 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3572 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3573 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3574 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3575 }
3576 }
3577
3578 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3579 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3580
3581 cgs_get_active_displays_info(hwmgr->device, &info);
3582
3583 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3584
3585 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3586
3587 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3588 PHM_PlatformCaps_StablePState)) {
3589 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3590 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3591
3592 for (count = table_info->vdd_dep_on_sclk->count - 1;
3593 count >= 0; count--) {
3594 if (stable_pstate_sclk >=
3595 table_info->vdd_dep_on_sclk->entries[count].clk) {
3596 stable_pstate_sclk =
3597 table_info->vdd_dep_on_sclk->entries[count].clk;
3598 break;
3599 }
3600 }
3601
3602 if (count < 0)
3603 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3604
3605 stable_pstate_mclk = max_limits->mclk;
3606
3607 minimum_clocks.engineClock = stable_pstate_sclk;
3608 minimum_clocks.memoryClock = stable_pstate_mclk;
3609 }
3610
3611 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3612 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3613
3614 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3615 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3616
3617 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3618
3619 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3620 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3621 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3622 "Overdrive sclk exceeds limit",
3623 hwmgr->gfx_arbiter.sclk_over_drive =
3624 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3625
3626 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3627 polaris10_ps->performance_levels[1].engine_clock =
3628 hwmgr->gfx_arbiter.sclk_over_drive;
3629 }
3630
3631 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3632 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3633 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3634 "Overdrive mclk exceeds limit",
3635 hwmgr->gfx_arbiter.mclk_over_drive =
3636 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3637
3638 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3639 polaris10_ps->performance_levels[1].memory_clock =
3640 hwmgr->gfx_arbiter.mclk_over_drive;
3641 }
3642
3643 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3644 hwmgr->platform_descriptor.platformCaps,
3645 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3646
3647
3648 disable_mclk_switching = (1 < info.display_count) ||
3649 disable_mclk_switching_for_frame_lock;
3650
3651 sclk = polaris10_ps->performance_levels[0].engine_clock;
3652 mclk = polaris10_ps->performance_levels[0].memory_clock;
3653
3654 if (disable_mclk_switching)
3655 mclk = polaris10_ps->performance_levels
3656 [polaris10_ps->performance_level_count - 1].memory_clock;
3657
3658 if (sclk < minimum_clocks.engineClock)
3659 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3660 max_limits->sclk : minimum_clocks.engineClock;
3661
3662 if (mclk < minimum_clocks.memoryClock)
3663 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3664 max_limits->mclk : minimum_clocks.memoryClock;
3665
3666 polaris10_ps->performance_levels[0].engine_clock = sclk;
3667 polaris10_ps->performance_levels[0].memory_clock = mclk;
3668
3669 polaris10_ps->performance_levels[1].engine_clock =
3670 (polaris10_ps->performance_levels[1].engine_clock >=
3671 polaris10_ps->performance_levels[0].engine_clock) ?
3672 polaris10_ps->performance_levels[1].engine_clock :
3673 polaris10_ps->performance_levels[0].engine_clock;
3674
3675 if (disable_mclk_switching) {
3676 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3677 mclk = polaris10_ps->performance_levels[1].memory_clock;
3678
3679 polaris10_ps->performance_levels[0].memory_clock = mclk;
3680 polaris10_ps->performance_levels[1].memory_clock = mclk;
3681 } else {
3682 if (polaris10_ps->performance_levels[1].memory_clock <
3683 polaris10_ps->performance_levels[0].memory_clock)
3684 polaris10_ps->performance_levels[1].memory_clock =
3685 polaris10_ps->performance_levels[0].memory_clock;
3686 }
3687
3688 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3689 PHM_PlatformCaps_StablePState)) {
3690 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3691 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3692 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3693 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3694 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3695 }
3696 }
3697 return 0;
3698 }
3699
3700
3701 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3702 {
3703 struct pp_power_state *ps;
3704 struct polaris10_power_state *polaris10_ps;
3705
3706 if (hwmgr == NULL)
3707 return -EINVAL;
3708
3709 ps = hwmgr->request_ps;
3710
3711 if (ps == NULL)
3712 return -EINVAL;
3713
3714 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3715
3716 if (low)
3717 return polaris10_ps->performance_levels[0].memory_clock;
3718 else
3719 return polaris10_ps->performance_levels
3720 [polaris10_ps->performance_level_count-1].memory_clock;
3721 }
3722
3723 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3724 {
3725 struct pp_power_state *ps;
3726 struct polaris10_power_state *polaris10_ps;
3727
3728 if (hwmgr == NULL)
3729 return -EINVAL;
3730
3731 ps = hwmgr->request_ps;
3732
3733 if (ps == NULL)
3734 return -EINVAL;
3735
3736 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3737
3738 if (low)
3739 return polaris10_ps->performance_levels[0].engine_clock;
3740 else
3741 return polaris10_ps->performance_levels
3742 [polaris10_ps->performance_level_count-1].engine_clock;
3743 }
3744
3745 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3746 struct pp_hw_power_state *hw_ps)
3747 {
3748 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3749 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3750 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3751 uint16_t size;
3752 uint8_t frev, crev;
3753 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3754
3755 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3756 * We assume here that fw_info is unchanged if this call fails.
3757 */
3758 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3759 hwmgr->device, index,
3760 &size, &frev, &crev);
3761 if (!fw_info)
3762 /* During a test, there is no firmware info table. */
3763 return 0;
3764
3765 /* Patch the state. */
3766 data->vbios_boot_state.sclk_bootup_value =
3767 le32_to_cpu(fw_info->ulDefaultEngineClock);
3768 data->vbios_boot_state.mclk_bootup_value =
3769 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3770 data->vbios_boot_state.mvdd_bootup_value =
3771 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3772 data->vbios_boot_state.vddc_bootup_value =
3773 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3774 data->vbios_boot_state.vddci_bootup_value =
3775 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3776 data->vbios_boot_state.pcie_gen_bootup_value =
3777 phm_get_current_pcie_speed(hwmgr);
3778
3779 data->vbios_boot_state.pcie_lane_bootup_value =
3780 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3781
3782 /* set boot power state */
3783 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3784 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3785 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3786 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3787
3788 return 0;
3789 }
3790
3791 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3792 void *state, struct pp_power_state *power_state,
3793 void *pp_table, uint32_t classification_flag)
3794 {
3795 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3796 struct polaris10_power_state *polaris10_power_state =
3797 (struct polaris10_power_state *)(&(power_state->hardware));
3798 struct polaris10_performance_level *performance_level;
3799 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3800 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3801 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3802 PPTable_Generic_SubTable_Header *sclk_dep_table =
3803 (PPTable_Generic_SubTable_Header *)
3804 (((unsigned long)powerplay_table) +
3805 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3806
3807 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3808 (ATOM_Tonga_MCLK_Dependency_Table *)
3809 (((unsigned long)powerplay_table) +
3810 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3811
3812 /* The following fields are not initialized here: id orderedList allStatesList */
3813 power_state->classification.ui_label =
3814 (le16_to_cpu(state_entry->usClassification) &
3815 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3816 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3817 power_state->classification.flags = classification_flag;
3818 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3819
3820 power_state->classification.temporary_state = false;
3821 power_state->classification.to_be_deleted = false;
3822
3823 power_state->validation.disallowOnDC =
3824 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3825 ATOM_Tonga_DISALLOW_ON_DC));
3826
3827 power_state->pcie.lanes = 0;
3828
3829 power_state->display.disableFrameModulation = false;
3830 power_state->display.limitRefreshrate = false;
3831 power_state->display.enableVariBright =
3832 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3833 ATOM_Tonga_ENABLE_VARIBRIGHT));
3834
3835 power_state->validation.supportedPowerLevels = 0;
3836 power_state->uvd_clocks.VCLK = 0;
3837 power_state->uvd_clocks.DCLK = 0;
3838 power_state->temperatures.min = 0;
3839 power_state->temperatures.max = 0;
3840
3841 performance_level = &(polaris10_power_state->performance_levels
3842 [polaris10_power_state->performance_level_count++]);
3843
3844 PP_ASSERT_WITH_CODE(
3845 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3846 "Performance levels exceeds SMC limit!",
3847 return -1);
3848
3849 PP_ASSERT_WITH_CODE(
3850 (polaris10_power_state->performance_level_count <=
3851 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3852 "Performance levels exceeds Driver limit!",
3853 return -1);
3854
3855 /* Performance levels are arranged from low to high. */
3856 performance_level->memory_clock = mclk_dep_table->entries
3857 [state_entry->ucMemoryClockIndexLow].ulMclk;
3858 if (sclk_dep_table->ucRevId == 0)
3859 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3860 [state_entry->ucEngineClockIndexLow].ulSclk;
3861 else if (sclk_dep_table->ucRevId == 1)
3862 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3863 [state_entry->ucEngineClockIndexLow].ulSclk;
3864 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3865 state_entry->ucPCIEGenLow);
3866 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3867 state_entry->ucPCIELaneHigh);
3868
3869 performance_level = &(polaris10_power_state->performance_levels
3870 [polaris10_power_state->performance_level_count++]);
3871 performance_level->memory_clock = mclk_dep_table->entries
3872 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3873
3874 if (sclk_dep_table->ucRevId == 0)
3875 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3876 [state_entry->ucEngineClockIndexHigh].ulSclk;
3877 else if (sclk_dep_table->ucRevId == 1)
3878 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3879 [state_entry->ucEngineClockIndexHigh].ulSclk;
3880
3881 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3882 state_entry->ucPCIEGenHigh);
3883 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3884 state_entry->ucPCIELaneHigh);
3885
3886 return 0;
3887 }
3888
3889 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3890 unsigned long entry_index, struct pp_power_state *state)
3891 {
3892 int result;
3893 struct polaris10_power_state *ps;
3894 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3895 struct phm_ppt_v1_information *table_info =
3896 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3897 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3898 table_info->vdd_dep_on_mclk;
3899
3900 state->hardware.magic = PHM_VIslands_Magic;
3901
3902 ps = (struct polaris10_power_state *)(&state->hardware);
3903
3904 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3905 polaris10_get_pp_table_entry_callback_func);
3906
3907 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3908 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3909 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3910 */
3911 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3912 if (dep_mclk_table->entries[0].clk !=
3913 data->vbios_boot_state.mclk_bootup_value)
3914 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3915 "does not match VBIOS boot MCLK level");
3916 if (dep_mclk_table->entries[0].vddci !=
3917 data->vbios_boot_state.vddci_bootup_value)
3918 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3919 "does not match VBIOS boot VDDCI level");
3920 }
3921
3922 /* set DC compatible flag if this state supports DC */
3923 if (!state->validation.disallowOnDC)
3924 ps->dc_compatible = true;
3925
3926 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3927 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3928
3929 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3930 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3931
3932 if (!result) {
3933 uint32_t i;
3934
3935 switch (state->classification.ui_label) {
3936 case PP_StateUILabel_Performance:
3937 data->use_pcie_performance_levels = true;
3938 for (i = 0; i < ps->performance_level_count; i++) {
3939 if (data->pcie_gen_performance.max <
3940 ps->performance_levels[i].pcie_gen)
3941 data->pcie_gen_performance.max =
3942 ps->performance_levels[i].pcie_gen;
3943
3944 if (data->pcie_gen_performance.min >
3945 ps->performance_levels[i].pcie_gen)
3946 data->pcie_gen_performance.min =
3947 ps->performance_levels[i].pcie_gen;
3948
3949 if (data->pcie_lane_performance.max <
3950 ps->performance_levels[i].pcie_lane)
3951 data->pcie_lane_performance.max =
3952 ps->performance_levels[i].pcie_lane;
3953 if (data->pcie_lane_performance.min >
3954 ps->performance_levels[i].pcie_lane)
3955 data->pcie_lane_performance.min =
3956 ps->performance_levels[i].pcie_lane;
3957 }
3958 break;
3959 case PP_StateUILabel_Battery:
3960 data->use_pcie_power_saving_levels = true;
3961
3962 for (i = 0; i < ps->performance_level_count; i++) {
3963 if (data->pcie_gen_power_saving.max <
3964 ps->performance_levels[i].pcie_gen)
3965 data->pcie_gen_power_saving.max =
3966 ps->performance_levels[i].pcie_gen;
3967
3968 if (data->pcie_gen_power_saving.min >
3969 ps->performance_levels[i].pcie_gen)
3970 data->pcie_gen_power_saving.min =
3971 ps->performance_levels[i].pcie_gen;
3972
3973 if (data->pcie_lane_power_saving.max <
3974 ps->performance_levels[i].pcie_lane)
3975 data->pcie_lane_power_saving.max =
3976 ps->performance_levels[i].pcie_lane;
3977
3978 if (data->pcie_lane_power_saving.min >
3979 ps->performance_levels[i].pcie_lane)
3980 data->pcie_lane_power_saving.min =
3981 ps->performance_levels[i].pcie_lane;
3982 }
3983 break;
3984 default:
3985 break;
3986 }
3987 }
3988 return 0;
3989 }
3990
3991 static void
3992 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3993 {
3994 uint32_t sclk, mclk, activity_percent;
3995 uint32_t offset;
3996 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3997
3998 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3999
4000 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4001
4002 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4003
4004 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4005 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4006 mclk / 100, sclk / 100);
4007
4008 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
4009 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4010 activity_percent += 0x80;
4011 activity_percent >>= 8;
4012
4013 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4014
4015 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
4016
4017 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
4018 }
4019
4020 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4021 {
4022 const struct phm_set_power_state_input *states =
4023 (const struct phm_set_power_state_input *)input;
4024 const struct polaris10_power_state *polaris10_ps =
4025 cast_const_phw_polaris10_power_state(states->pnew_state);
4026 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4027 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4028 uint32_t sclk = polaris10_ps->performance_levels
4029 [polaris10_ps->performance_level_count - 1].engine_clock;
4030 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4031 uint32_t mclk = polaris10_ps->performance_levels
4032 [polaris10_ps->performance_level_count - 1].memory_clock;
4033 struct PP_Clocks min_clocks = {0};
4034 uint32_t i;
4035 struct cgs_display_info info = {0};
4036
4037 data->need_update_smu7_dpm_table = 0;
4038
4039 for (i = 0; i < sclk_table->count; i++) {
4040 if (sclk == sclk_table->dpm_levels[i].value)
4041 break;
4042 }
4043
4044 if (i >= sclk_table->count)
4045 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4046 else {
4047 /* TODO: Check SCLK in DAL's minimum clocks
4048 * in case DeepSleep divider update is required.
4049 */
4050 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4051 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4052 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4053 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4054 }
4055
4056 for (i = 0; i < mclk_table->count; i++) {
4057 if (mclk == mclk_table->dpm_levels[i].value)
4058 break;
4059 }
4060
4061 if (i >= mclk_table->count)
4062 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4063
4064 cgs_get_active_displays_info(hwmgr->device, &info);
4065
4066 if (data->display_timing.num_existing_displays != info.display_count)
4067 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4068
4069 return 0;
4070 }
4071
4072 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4073 const struct polaris10_power_state *polaris10_ps)
4074 {
4075 uint32_t i;
4076 uint32_t sclk, max_sclk = 0;
4077 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4078 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4079
4080 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4081 sclk = polaris10_ps->performance_levels[i].engine_clock;
4082 if (max_sclk < sclk)
4083 max_sclk = sclk;
4084 }
4085
4086 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4087 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4088 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4089 dpm_table->pcie_speed_table.dpm_levels
4090 [dpm_table->pcie_speed_table.count - 1].value :
4091 dpm_table->pcie_speed_table.dpm_levels[i].value);
4092 }
4093
4094 return 0;
4095 }
4096
4097 static int polaris10_request_link_speed_change_before_state_change(
4098 struct pp_hwmgr *hwmgr, const void *input)
4099 {
4100 const struct phm_set_power_state_input *states =
4101 (const struct phm_set_power_state_input *)input;
4102 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4103 const struct polaris10_power_state *polaris10_nps =
4104 cast_const_phw_polaris10_power_state(states->pnew_state);
4105 const struct polaris10_power_state *polaris10_cps =
4106 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4107
4108 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4109 uint16_t current_link_speed;
4110
4111 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4112 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4113 else
4114 current_link_speed = data->force_pcie_gen;
4115
4116 data->force_pcie_gen = PP_PCIEGenInvalid;
4117 data->pspp_notify_required = false;
4118
4119 if (target_link_speed > current_link_speed) {
4120 switch (target_link_speed) {
4121 case PP_PCIEGen3:
4122 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4123 break;
4124 data->force_pcie_gen = PP_PCIEGen2;
4125 if (current_link_speed == PP_PCIEGen2)
4126 break;
4127 case PP_PCIEGen2:
4128 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4129 break;
4130 default:
4131 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4132 break;
4133 }
4134 } else {
4135 if (target_link_speed < current_link_speed)
4136 data->pspp_notify_required = true;
4137 }
4138
4139 return 0;
4140 }
4141
4142 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4143 {
4144 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4145
4146 if (0 == data->need_update_smu7_dpm_table)
4147 return 0;
4148
4149 if ((0 == data->sclk_dpm_key_disabled) &&
4150 (data->need_update_smu7_dpm_table &
4151 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4152 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4153 "Trying to freeze SCLK DPM when DPM is disabled",
4154 );
4155 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4156 PPSMC_MSG_SCLKDPM_FreezeLevel),
4157 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4158 return -1);
4159 }
4160
4161 if ((0 == data->mclk_dpm_key_disabled) &&
4162 (data->need_update_smu7_dpm_table &
4163 DPMTABLE_OD_UPDATE_MCLK)) {
4164 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4165 "Trying to freeze MCLK DPM when DPM is disabled",
4166 );
4167 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4168 PPSMC_MSG_MCLKDPM_FreezeLevel),
4169 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4170 return -1);
4171 }
4172
4173 return 0;
4174 }
4175
4176 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4177 struct pp_hwmgr *hwmgr, const void *input)
4178 {
4179 int result = 0;
4180 const struct phm_set_power_state_input *states =
4181 (const struct phm_set_power_state_input *)input;
4182 const struct polaris10_power_state *polaris10_ps =
4183 cast_const_phw_polaris10_power_state(states->pnew_state);
4184 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4185 uint32_t sclk = polaris10_ps->performance_levels
4186 [polaris10_ps->performance_level_count - 1].engine_clock;
4187 uint32_t mclk = polaris10_ps->performance_levels
4188 [polaris10_ps->performance_level_count - 1].memory_clock;
4189 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4190
4191 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4192 uint32_t dpm_count, clock_percent;
4193 uint32_t i;
4194
4195 if (0 == data->need_update_smu7_dpm_table)
4196 return 0;
4197
4198 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4199 dpm_table->sclk_table.dpm_levels
4200 [dpm_table->sclk_table.count - 1].value = sclk;
4201
4202 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4203 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4204 /* Need to do calculation based on the golden DPM table
4205 * as the Heatmap GPU Clock axis is also based on the default values
4206 */
4207 PP_ASSERT_WITH_CODE(
4208 (golden_dpm_table->sclk_table.dpm_levels
4209 [golden_dpm_table->sclk_table.count - 1].value != 0),
4210 "Divide by 0!",
4211 return -1);
4212 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4213
4214 for (i = dpm_count; i > 1; i--) {
4215 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4216 clock_percent =
4217 ((sclk
4218 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4219 ) * 100)
4220 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4221
4222 dpm_table->sclk_table.dpm_levels[i].value =
4223 golden_dpm_table->sclk_table.dpm_levels[i].value +
4224 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4225 clock_percent)/100;
4226
4227 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4228 clock_percent =
4229 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4230 - sclk) * 100)
4231 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4232
4233 dpm_table->sclk_table.dpm_levels[i].value =
4234 golden_dpm_table->sclk_table.dpm_levels[i].value -
4235 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4236 clock_percent) / 100;
4237 } else
4238 dpm_table->sclk_table.dpm_levels[i].value =
4239 golden_dpm_table->sclk_table.dpm_levels[i].value;
4240 }
4241 }
4242 }
4243
4244 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4245 dpm_table->mclk_table.dpm_levels
4246 [dpm_table->mclk_table.count - 1].value = mclk;
4247
4248 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4249 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4250
4251 PP_ASSERT_WITH_CODE(
4252 (golden_dpm_table->mclk_table.dpm_levels
4253 [golden_dpm_table->mclk_table.count-1].value != 0),
4254 "Divide by 0!",
4255 return -1);
4256 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4257 for (i = dpm_count; i > 1; i--) {
4258 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4259 clock_percent = ((mclk -
4260 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4261 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4262
4263 dpm_table->mclk_table.dpm_levels[i].value =
4264 golden_dpm_table->mclk_table.dpm_levels[i].value +
4265 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4266 clock_percent) / 100;
4267
4268 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4269 clock_percent = (
4270 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4271 * 100)
4272 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4273
4274 dpm_table->mclk_table.dpm_levels[i].value =
4275 golden_dpm_table->mclk_table.dpm_levels[i].value -
4276 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4277 clock_percent) / 100;
4278 } else
4279 dpm_table->mclk_table.dpm_levels[i].value =
4280 golden_dpm_table->mclk_table.dpm_levels[i].value;
4281 }
4282 }
4283 }
4284
4285 if (data->need_update_smu7_dpm_table &
4286 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4287 result = polaris10_populate_all_graphic_levels(hwmgr);
4288 PP_ASSERT_WITH_CODE((0 == result),
4289 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4290 return result);
4291 }
4292
4293 if (data->need_update_smu7_dpm_table &
4294 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4295 /*populate MCLK dpm table to SMU7 */
4296 result = polaris10_populate_all_memory_levels(hwmgr);
4297 PP_ASSERT_WITH_CODE((0 == result),
4298 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4299 return result);
4300 }
4301
4302 return result;
4303 }
4304
4305 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4306 struct polaris10_single_dpm_table *dpm_table,
4307 uint32_t low_limit, uint32_t high_limit)
4308 {
4309 uint32_t i;
4310
4311 for (i = 0; i < dpm_table->count; i++) {
4312 if ((dpm_table->dpm_levels[i].value < low_limit)
4313 || (dpm_table->dpm_levels[i].value > high_limit))
4314 dpm_table->dpm_levels[i].enabled = false;
4315 else
4316 dpm_table->dpm_levels[i].enabled = true;
4317 }
4318
4319 return 0;
4320 }
4321
4322 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4323 const struct polaris10_power_state *polaris10_ps)
4324 {
4325 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4326 uint32_t high_limit_count;
4327
4328 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4329 "power state did not have any performance level",
4330 return -1);
4331
4332 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4333
4334 polaris10_trim_single_dpm_states(hwmgr,
4335 &(data->dpm_table.sclk_table),
4336 polaris10_ps->performance_levels[0].engine_clock,
4337 polaris10_ps->performance_levels[high_limit_count].engine_clock);
4338
4339 polaris10_trim_single_dpm_states(hwmgr,
4340 &(data->dpm_table.mclk_table),
4341 polaris10_ps->performance_levels[0].memory_clock,
4342 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4343
4344 return 0;
4345 }
4346
4347 static int polaris10_generate_dpm_level_enable_mask(
4348 struct pp_hwmgr *hwmgr, const void *input)
4349 {
4350 int result;
4351 const struct phm_set_power_state_input *states =
4352 (const struct phm_set_power_state_input *)input;
4353 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4354 const struct polaris10_power_state *polaris10_ps =
4355 cast_const_phw_polaris10_power_state(states->pnew_state);
4356
4357 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4358 if (result)
4359 return result;
4360
4361 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4362 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4363 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4364 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4365 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4366 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4367
4368 return 0;
4369 }
4370
4371 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4372 {
4373 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4374 PPSMC_MSG_UVDDPM_Enable :
4375 PPSMC_MSG_UVDDPM_Disable);
4376 }
4377
4378 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4379 {
4380 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4381 PPSMC_MSG_VCEDPM_Enable :
4382 PPSMC_MSG_VCEDPM_Disable);
4383 }
4384
4385 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4386 {
4387 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4388 PPSMC_MSG_SAMUDPM_Enable :
4389 PPSMC_MSG_SAMUDPM_Disable);
4390 }
4391
4392 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4393 {
4394 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4395 uint32_t mm_boot_level_offset, mm_boot_level_value;
4396 struct phm_ppt_v1_information *table_info =
4397 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4398
4399 if (!bgate) {
4400 data->smc_state_table.UvdBootLevel = 0;
4401 if (table_info->mm_dep_table->count > 0)
4402 data->smc_state_table.UvdBootLevel =
4403 (uint8_t) (table_info->mm_dep_table->count - 1);
4404 mm_boot_level_offset = data->dpm_table_start +
4405 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4406 mm_boot_level_offset /= 4;
4407 mm_boot_level_offset *= 4;
4408 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4409 CGS_IND_REG__SMC, mm_boot_level_offset);
4410 mm_boot_level_value &= 0x00FFFFFF;
4411 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4412 cgs_write_ind_register(hwmgr->device,
4413 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4414
4415 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4416 PHM_PlatformCaps_UVDDPM) ||
4417 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4418 PHM_PlatformCaps_StablePState))
4419 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4420 PPSMC_MSG_UVDDPM_SetEnabledMask,
4421 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4422 }
4423
4424 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4425 }
4426
4427 int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4428 {
4429 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4430 uint32_t mm_boot_level_offset, mm_boot_level_value;
4431 struct phm_ppt_v1_information *table_info =
4432 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4433
4434 if (!bgate) {
4435 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4436 PHM_PlatformCaps_StablePState))
4437 data->smc_state_table.VceBootLevel =
4438 (uint8_t) (table_info->mm_dep_table->count - 1);
4439 else
4440 data->smc_state_table.VceBootLevel = 0;
4441
4442 mm_boot_level_offset = data->dpm_table_start +
4443 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4444 mm_boot_level_offset /= 4;
4445 mm_boot_level_offset *= 4;
4446 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4447 CGS_IND_REG__SMC, mm_boot_level_offset);
4448 mm_boot_level_value &= 0xFF00FFFF;
4449 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4450 cgs_write_ind_register(hwmgr->device,
4451 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4452
4453 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
4454 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4455 PPSMC_MSG_VCEDPM_SetEnabledMask,
4456 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4457 }
4458
4459 polaris10_enable_disable_vce_dpm(hwmgr, !bgate);
4460
4461 return 0;
4462 }
4463
4464 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4465 {
4466 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4467 uint32_t mm_boot_level_offset, mm_boot_level_value;
4468
4469 if (!bgate) {
4470 data->smc_state_table.SamuBootLevel = 0;
4471 mm_boot_level_offset = data->dpm_table_start +
4472 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4473 mm_boot_level_offset /= 4;
4474 mm_boot_level_offset *= 4;
4475 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4476 CGS_IND_REG__SMC, mm_boot_level_offset);
4477 mm_boot_level_value &= 0xFFFFFF00;
4478 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4479 cgs_write_ind_register(hwmgr->device,
4480 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4481
4482 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4483 PHM_PlatformCaps_StablePState))
4484 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4485 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4486 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4487 }
4488
4489 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4490 }
4491
4492 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4493 {
4494 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4495
4496 int result = 0;
4497 uint32_t low_sclk_interrupt_threshold = 0;
4498
4499 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4500 PHM_PlatformCaps_SclkThrottleLowNotification)
4501 && (hwmgr->gfx_arbiter.sclk_threshold !=
4502 data->low_sclk_interrupt_threshold)) {
4503 data->low_sclk_interrupt_threshold =
4504 hwmgr->gfx_arbiter.sclk_threshold;
4505 low_sclk_interrupt_threshold =
4506 data->low_sclk_interrupt_threshold;
4507
4508 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4509
4510 result = polaris10_copy_bytes_to_smc(
4511 hwmgr->smumgr,
4512 data->dpm_table_start +
4513 offsetof(SMU74_Discrete_DpmTable,
4514 LowSclkInterruptThreshold),
4515 (uint8_t *)&low_sclk_interrupt_threshold,
4516 sizeof(uint32_t),
4517 data->sram_end);
4518 }
4519
4520 return result;
4521 }
4522
4523 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4524 {
4525 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4526
4527 if (data->need_update_smu7_dpm_table &
4528 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4529 return polaris10_program_memory_timing_parameters(hwmgr);
4530
4531 return 0;
4532 }
4533
4534 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4535 {
4536 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4537
4538 if (0 == data->need_update_smu7_dpm_table)
4539 return 0;
4540
4541 if ((0 == data->sclk_dpm_key_disabled) &&
4542 (data->need_update_smu7_dpm_table &
4543 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4544
4545 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4546 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4547 );
4548 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4549 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4550 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4551 return -1);
4552 }
4553
4554 if ((0 == data->mclk_dpm_key_disabled) &&
4555 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4556
4557 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4558 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4559 );
4560 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4561 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4562 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4563 return -1);
4564 }
4565
4566 data->need_update_smu7_dpm_table = 0;
4567
4568 return 0;
4569 }
4570
4571 static int polaris10_notify_link_speed_change_after_state_change(
4572 struct pp_hwmgr *hwmgr, const void *input)
4573 {
4574 const struct phm_set_power_state_input *states =
4575 (const struct phm_set_power_state_input *)input;
4576 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4577 const struct polaris10_power_state *polaris10_ps =
4578 cast_const_phw_polaris10_power_state(states->pnew_state);
4579 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4580 uint8_t request;
4581
4582 if (data->pspp_notify_required) {
4583 if (target_link_speed == PP_PCIEGen3)
4584 request = PCIE_PERF_REQ_GEN3;
4585 else if (target_link_speed == PP_PCIEGen2)
4586 request = PCIE_PERF_REQ_GEN2;
4587 else
4588 request = PCIE_PERF_REQ_GEN1;
4589
4590 if (request == PCIE_PERF_REQ_GEN1 &&
4591 phm_get_current_pcie_speed(hwmgr) > 0)
4592 return 0;
4593
4594 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4595 if (PP_PCIEGen2 == target_link_speed)
4596 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4597 else
4598 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4599 }
4600 }
4601
4602 return 0;
4603 }
4604
4605 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4606 {
4607 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4608
4609 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4610 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4611 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
4612 }
4613
4614
4615
4616 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4617 {
4618 int tmp_result, result = 0;
4619 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4620
4621 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4622 PP_ASSERT_WITH_CODE((0 == tmp_result),
4623 "Failed to find DPM states clocks in DPM table!",
4624 result = tmp_result);
4625
4626 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4627 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4628 tmp_result =
4629 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4630 PP_ASSERT_WITH_CODE((0 == tmp_result),
4631 "Failed to request link speed change before state change!",
4632 result = tmp_result);
4633 }
4634
4635 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4636 PP_ASSERT_WITH_CODE((0 == tmp_result),
4637 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4638
4639 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4640 PP_ASSERT_WITH_CODE((0 == tmp_result),
4641 "Failed to populate and upload SCLK MCLK DPM levels!",
4642 result = tmp_result);
4643
4644 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4645 PP_ASSERT_WITH_CODE((0 == tmp_result),
4646 "Failed to generate DPM level enabled mask!",
4647 result = tmp_result);
4648
4649 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4650 PP_ASSERT_WITH_CODE((0 == tmp_result),
4651 "Failed to update SCLK threshold!",
4652 result = tmp_result);
4653
4654 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4655 PP_ASSERT_WITH_CODE((0 == tmp_result),
4656 "Failed to program memory timing parameters!",
4657 result = tmp_result);
4658
4659 tmp_result = polaris10_notify_smc_display(hwmgr);
4660 PP_ASSERT_WITH_CODE((0 == tmp_result),
4661 "Failed to notify smc display settings!",
4662 result = tmp_result);
4663
4664 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4665 PP_ASSERT_WITH_CODE((0 == tmp_result),
4666 "Failed to unfreeze SCLK MCLK DPM!",
4667 result = tmp_result);
4668
4669 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4670 PP_ASSERT_WITH_CODE((0 == tmp_result),
4671 "Failed to upload DPM level enabled mask!",
4672 result = tmp_result);
4673
4674 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4675 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4676 tmp_result =
4677 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4678 PP_ASSERT_WITH_CODE((0 == tmp_result),
4679 "Failed to notify link speed change after state change!",
4680 result = tmp_result);
4681 }
4682 data->apply_optimized_settings = false;
4683 return result;
4684 }
4685
4686 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4687 {
4688 hwmgr->thermal_controller.
4689 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4690
4691 if (phm_is_hw_access_blocked(hwmgr))
4692 return 0;
4693
4694 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4695 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4696 }
4697
4698
4699 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4700 {
4701 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4702
4703 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4704 }
4705
4706 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4707 {
4708 uint32_t num_active_displays = 0;
4709 struct cgs_display_info info = {0};
4710 info.mode_info = NULL;
4711
4712 cgs_get_active_displays_info(hwmgr->device, &info);
4713
4714 num_active_displays = info.display_count;
4715
4716 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4717 polaris10_notify_smc_display_change(hwmgr, false);
4718
4719
4720 return 0;
4721 }
4722
4723 /**
4724 * Programs the display gap
4725 *
4726 * @param hwmgr the address of the powerplay hardware manager.
4727 * @return always OK
4728 */
4729 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4730 {
4731 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4732 uint32_t num_active_displays = 0;
4733 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4734 uint32_t display_gap2;
4735 uint32_t pre_vbi_time_in_us;
4736 uint32_t frame_time_in_us;
4737 uint32_t ref_clock;
4738 uint32_t refresh_rate = 0;
4739 struct cgs_display_info info = {0};
4740 struct cgs_mode_info mode_info;
4741
4742 info.mode_info = &mode_info;
4743
4744 cgs_get_active_displays_info(hwmgr->device, &info);
4745 num_active_displays = info.display_count;
4746
4747 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4748 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4749
4750 ref_clock = mode_info.ref_clock;
4751 refresh_rate = mode_info.refresh_rate;
4752
4753 if (0 == refresh_rate)
4754 refresh_rate = 60;
4755
4756 frame_time_in_us = 1000000 / refresh_rate;
4757
4758 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4759 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4760
4761 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4762
4763 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4764
4765 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4766
4767 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4768
4769
4770 return 0;
4771 }
4772
4773
4774 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4775 {
4776 return polaris10_program_display_gap(hwmgr);
4777 }
4778
4779 /**
4780 * Set maximum target operating fan output RPM
4781 *
4782 * @param hwmgr: the address of the powerplay hardware manager.
4783 * @param usMaxFanRpm: max operating fan RPM value.
4784 * @return The response that came from the SMC.
4785 */
4786 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4787 {
4788 hwmgr->thermal_controller.
4789 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4790
4791 if (phm_is_hw_access_blocked(hwmgr))
4792 return 0;
4793
4794 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4795 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4796 }
4797
4798 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4799 const void *thermal_interrupt_info)
4800 {
4801 return 0;
4802 }
4803
4804 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4805 {
4806 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4807 bool is_update_required = false;
4808 struct cgs_display_info info = {0, 0, NULL};
4809
4810 cgs_get_active_displays_info(hwmgr->device, &info);
4811
4812 if (data->display_timing.num_existing_displays != info.display_count)
4813 is_update_required = true;
4814 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4815 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4816 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4817 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4818 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4819 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4820 is_update_required = true;
4821 */
4822 return is_update_required;
4823 }
4824
4825 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4826 const struct polaris10_performance_level *pl2)
4827 {
4828 return ((pl1->memory_clock == pl2->memory_clock) &&
4829 (pl1->engine_clock == pl2->engine_clock) &&
4830 (pl1->pcie_gen == pl2->pcie_gen) &&
4831 (pl1->pcie_lane == pl2->pcie_lane));
4832 }
4833
4834 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4835 {
4836 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4837 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4838 int i;
4839
4840 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4841 return -EINVAL;
4842
4843 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4844 if (psa->performance_level_count != psb->performance_level_count) {
4845 *equal = false;
4846 return 0;
4847 }
4848
4849 for (i = 0; i < psa->performance_level_count; i++) {
4850 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4851 /* If we have found even one performance level pair that is different the states are different. */
4852 *equal = false;
4853 return 0;
4854 }
4855 }
4856
4857 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4858 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4859 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4860 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4861
4862 return 0;
4863 }
4864
4865 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4866 {
4867 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4868
4869 uint32_t vbios_version;
4870
4871 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4872
4873 phm_get_mc_microcode_version(hwmgr);
4874 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4875 /* Full version of MC ucode has already been loaded. */
4876 if (vbios_version == 0) {
4877 data->need_long_memory_training = false;
4878 return 0;
4879 }
4880
4881 data->need_long_memory_training = false;
4882
4883 /*
4884 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4885 pfd = &tonga_mcmeFirmware;
4886 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4887 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4888 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4889 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4890 */
4891 return 0;
4892 }
4893
4894 /**
4895 * Read clock related registers.
4896 *
4897 * @param hwmgr the address of the powerplay hardware manager.
4898 * @return always 0
4899 */
4900 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4901 {
4902 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4903
4904 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4905 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4906 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4907
4908 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4909 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4910 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4911
4912 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4913 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4914 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4915
4916 return 0;
4917 }
4918
4919 /**
4920 * Find out if memory is GDDR5.
4921 *
4922 * @param hwmgr the address of the powerplay hardware manager.
4923 * @return always 0
4924 */
4925 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4926 {
4927 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4928 uint32_t temp;
4929
4930 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4931
4932 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4933 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4934 MC_SEQ_MISC0_GDDR5_SHIFT));
4935
4936 return 0;
4937 }
4938
4939 /**
4940 * Enables Dynamic Power Management by SMC
4941 *
4942 * @param hwmgr the address of the powerplay hardware manager.
4943 * @return always 0
4944 */
4945 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4946 {
4947 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4948 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4949
4950 return 0;
4951 }
4952
4953 /**
4954 * Initialize PowerGating States for different engines
4955 *
4956 * @param hwmgr the address of the powerplay hardware manager.
4957 * @return always 0
4958 */
4959 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4960 {
4961 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4962
4963 data->uvd_power_gated = false;
4964 data->vce_power_gated = false;
4965 data->samu_power_gated = false;
4966
4967 return 0;
4968 }
4969
4970 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4971 {
4972 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4973 data->low_sclk_interrupt_threshold = 0;
4974
4975 return 0;
4976 }
4977
4978 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4979 {
4980 int tmp_result, result = 0;
4981
4982 polaris10_upload_mc_firmware(hwmgr);
4983
4984 tmp_result = polaris10_read_clock_registers(hwmgr);
4985 PP_ASSERT_WITH_CODE((0 == tmp_result),
4986 "Failed to read clock registers!", result = tmp_result);
4987
4988 tmp_result = polaris10_get_memory_type(hwmgr);
4989 PP_ASSERT_WITH_CODE((0 == tmp_result),
4990 "Failed to get memory type!", result = tmp_result);
4991
4992 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4993 PP_ASSERT_WITH_CODE((0 == tmp_result),
4994 "Failed to enable ACPI power management!", result = tmp_result);
4995
4996 tmp_result = polaris10_init_power_gate_state(hwmgr);
4997 PP_ASSERT_WITH_CODE((0 == tmp_result),
4998 "Failed to init power gate state!", result = tmp_result);
4999
5000 tmp_result = phm_get_mc_microcode_version(hwmgr);
5001 PP_ASSERT_WITH_CODE((0 == tmp_result),
5002 "Failed to get MC microcode version!", result = tmp_result);
5003
5004 tmp_result = polaris10_init_sclk_threshold(hwmgr);
5005 PP_ASSERT_WITH_CODE((0 == tmp_result),
5006 "Failed to init sclk threshold!", result = tmp_result);
5007
5008 return result;
5009 }
5010
5011 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5012 enum pp_clock_type type, uint32_t mask)
5013 {
5014 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5015
5016 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5017 return -EINVAL;
5018
5019 switch (type) {
5020 case PP_SCLK:
5021 if (!data->sclk_dpm_key_disabled)
5022 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5023 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5024 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5025 break;
5026 case PP_MCLK:
5027 if (!data->mclk_dpm_key_disabled)
5028 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5029 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5030 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5031 break;
5032 case PP_PCIE:
5033 {
5034 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5035 uint32_t level = 0;
5036
5037 while (tmp >>= 1)
5038 level++;
5039
5040 if (!data->pcie_dpm_key_disabled)
5041 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5042 PPSMC_MSG_PCIeDPM_ForceLevel,
5043 level);
5044 break;
5045 }
5046 default:
5047 break;
5048 }
5049
5050 return 0;
5051 }
5052
5053 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5054 {
5055 uint32_t speedCntl = 0;
5056
5057 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5058 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5059 ixPCIE_LC_SPEED_CNTL);
5060 return((uint16_t)PHM_GET_FIELD(speedCntl,
5061 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5062 }
5063
5064 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5065 enum pp_clock_type type, char *buf)
5066 {
5067 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5068 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5069 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5070 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5071 int i, now, size = 0;
5072 uint32_t clock, pcie_speed;
5073
5074 switch (type) {
5075 case PP_SCLK:
5076 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5077 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5078
5079 for (i = 0; i < sclk_table->count; i++) {
5080 if (clock > sclk_table->dpm_levels[i].value)
5081 continue;
5082 break;
5083 }
5084 now = i;
5085
5086 for (i = 0; i < sclk_table->count; i++)
5087 size += sprintf(buf + size, "%d: %uMhz %s\n",
5088 i, sclk_table->dpm_levels[i].value / 100,
5089 (i == now) ? "*" : "");
5090 break;
5091 case PP_MCLK:
5092 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5093 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5094
5095 for (i = 0; i < mclk_table->count; i++) {
5096 if (clock > mclk_table->dpm_levels[i].value)
5097 continue;
5098 break;
5099 }
5100 now = i;
5101
5102 for (i = 0; i < mclk_table->count; i++)
5103 size += sprintf(buf + size, "%d: %uMhz %s\n",
5104 i, mclk_table->dpm_levels[i].value / 100,
5105 (i == now) ? "*" : "");
5106 break;
5107 case PP_PCIE:
5108 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5109 for (i = 0; i < pcie_table->count; i++) {
5110 if (pcie_speed != pcie_table->dpm_levels[i].value)
5111 continue;
5112 break;
5113 }
5114 now = i;
5115
5116 for (i = 0; i < pcie_table->count; i++)
5117 size += sprintf(buf + size, "%d: %s %s\n", i,
5118 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5119 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5120 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5121 (i == now) ? "*" : "");
5122 break;
5123 default:
5124 break;
5125 }
5126 return size;
5127 }
5128
5129 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5130 {
5131 if (mode) {
5132 /* stop auto-manage */
5133 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5134 PHM_PlatformCaps_MicrocodeFanControl))
5135 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5136 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5137 } else
5138 /* restart auto-manage */
5139 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5140
5141 return 0;
5142 }
5143
5144 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5145 {
5146 if (hwmgr->fan_ctrl_is_in_default_mode)
5147 return hwmgr->fan_ctrl_default_mode;
5148 else
5149 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5150 CG_FDO_CTRL2, FDO_PWM_MODE);
5151 }
5152
5153 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5154 {
5155 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5156 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5157 struct polaris10_single_dpm_table *golden_sclk_table =
5158 &(data->golden_dpm_table.sclk_table);
5159 int value;
5160
5161 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5162 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5163 100 /
5164 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5165
5166 return value;
5167 }
5168
5169 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5170 {
5171 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5172 struct polaris10_single_dpm_table *golden_sclk_table =
5173 &(data->golden_dpm_table.sclk_table);
5174 struct pp_power_state *ps;
5175 struct polaris10_power_state *polaris10_ps;
5176
5177 if (value > 20)
5178 value = 20;
5179
5180 ps = hwmgr->request_ps;
5181
5182 if (ps == NULL)
5183 return -EINVAL;
5184
5185 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5186
5187 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5188 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5189 value / 100 +
5190 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5191
5192 return 0;
5193 }
5194
5195 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5196 {
5197 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5198 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5199 struct polaris10_single_dpm_table *golden_mclk_table =
5200 &(data->golden_dpm_table.mclk_table);
5201 int value;
5202
5203 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5204 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5205 100 /
5206 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5207
5208 return value;
5209 }
5210
5211 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5212 {
5213 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5214 struct polaris10_single_dpm_table *golden_mclk_table =
5215 &(data->golden_dpm_table.mclk_table);
5216 struct pp_power_state *ps;
5217 struct polaris10_power_state *polaris10_ps;
5218
5219 if (value > 20)
5220 value = 20;
5221
5222 ps = hwmgr->request_ps;
5223
5224 if (ps == NULL)
5225 return -EINVAL;
5226
5227 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5228
5229 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5230 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5231 value / 100 +
5232 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5233
5234 return 0;
5235 }
5236 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5237 .backend_init = &polaris10_hwmgr_backend_init,
5238 .backend_fini = &polaris10_hwmgr_backend_fini,
5239 .asic_setup = &polaris10_setup_asic_task,
5240 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5241 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5242 .force_dpm_level = &polaris10_force_dpm_level,
5243 .power_state_set = polaris10_set_power_state_tasks,
5244 .get_power_state_size = polaris10_get_power_state_size,
5245 .get_mclk = polaris10_dpm_get_mclk,
5246 .get_sclk = polaris10_dpm_get_sclk,
5247 .patch_boot_state = polaris10_dpm_patch_boot_state,
5248 .get_pp_table_entry = polaris10_get_pp_table_entry,
5249 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5250 .print_current_perforce_level = polaris10_print_current_perforce_level,
5251 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5252 .powergate_uvd = polaris10_phm_powergate_uvd,
5253 .powergate_vce = polaris10_phm_powergate_vce,
5254 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5255 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5256 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5257 .display_config_changed = polaris10_display_configuration_changed_task,
5258 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5259 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5260 .get_temperature = polaris10_thermal_get_temperature,
5261 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5262 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5263 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5264 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5265 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5266 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5267 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5268 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5269 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5270 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5271 .check_states_equal = polaris10_check_states_equal,
5272 .set_fan_control_mode = polaris10_set_fan_control_mode,
5273 .get_fan_control_mode = polaris10_get_fan_control_mode,
5274 .force_clock_level = polaris10_force_clock_level,
5275 .print_clock_levels = polaris10_print_clock_levels,
5276 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5277 .get_sclk_od = polaris10_get_sclk_od,
5278 .set_sclk_od = polaris10_set_sclk_od,
5279 .get_mclk_od = polaris10_get_mclk_od,
5280 .set_mclk_od = polaris10_set_mclk_od,
5281 };
5282
5283 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5284 {
5285 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5286 hwmgr->pptable_func = &tonga_pptable_funcs;
5287 pp_polaris10_thermal_initialize(hwmgr);
5288
5289 return 0;
5290 }
Linux kernel - Deliverables
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