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mmc: sdhci-acpi: Set MMC_CAP_CMD_DURING_TFR for Intel eMMC controllers
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / tonga_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include "linux/delay.h"
27 #include "pp_acpi.h"
28 #include "hwmgr.h"
29 #include <atombios.h>
30 #include "tonga_hwmgr.h"
31 #include "pptable.h"
32 #include "processpptables.h"
33 #include "tonga_processpptables.h"
34 #include "tonga_pptable.h"
35 #include "pp_debug.h"
36 #include "tonga_ppsmc.h"
37 #include "cgs_common.h"
38 #include "pppcielanes.h"
39 #include "tonga_dyn_defaults.h"
40 #include "smumgr.h"
41 #include "tonga_smumgr.h"
42 #include "tonga_clockpowergating.h"
43 #include "tonga_thermal.h"
44
45 #include "smu/smu_7_1_2_d.h"
46 #include "smu/smu_7_1_2_sh_mask.h"
47
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50
51 #include "bif/bif_5_0_d.h"
52 #include "bif/bif_5_0_sh_mask.h"
53
54 #include "dce/dce_10_0_d.h"
55 #include "dce/dce_10_0_sh_mask.h"
56
57 #include "cgs_linux.h"
58 #include "eventmgr.h"
59 #include "amd_pcie_helpers.h"
60
61 #define MC_CG_ARB_FREQ_F0 0x0a
62 #define MC_CG_ARB_FREQ_F1 0x0b
63 #define MC_CG_ARB_FREQ_F2 0x0c
64 #define MC_CG_ARB_FREQ_F3 0x0d
65
66 #define MC_CG_SEQ_DRAMCONF_S0 0x05
67 #define MC_CG_SEQ_DRAMCONF_S1 0x06
68 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
69 #define MC_CG_SEQ_YCLK_RESUME 0x0a
70
71 #define PCIE_BUS_CLK 10000
72 #define TCLK (PCIE_BUS_CLK / 10)
73
74 #define SMC_RAM_END 0x40000
75 #define SMC_CG_IND_START 0xc0030000
76 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
77
78 #define VOLTAGE_SCALE 4
79 #define VOLTAGE_VID_OFFSET_SCALE1 625
80 #define VOLTAGE_VID_OFFSET_SCALE2 100
81
82 #define VDDC_VDDCI_DELTA 200
83 #define VDDC_VDDGFX_DELTA 300
84
85 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
86 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
87 #define MC_SEQ_MISC0_GDDR5_VALUE 5
88
89 typedef uint32_t PECI_RegistryValue;
90
91 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
92 static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
93 {600, 1050, 3, 0},
94 {600, 1050, 6, 1} };
95
96 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
97 static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
98 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
99 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
100
101 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
102 static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
103 {0, 1, 3, 2, 4, 5},
104 {0, 2, 4, 5, 6, 5} };
105
106 /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
107 enum DPM_EVENT_SRC {
108 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
109 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
110 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
111 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
112 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
113 };
114 typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
115
116 static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
117
118 struct tonga_power_state *cast_phw_tonga_power_state(
119 struct pp_hw_power_state *hw_ps)
120 {
121 if (hw_ps == NULL)
122 return NULL;
123
124 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
125 "Invalid Powerstate Type!",
126 return NULL);
127
128 return (struct tonga_power_state *)hw_ps;
129 }
130
131 const struct tonga_power_state *cast_const_phw_tonga_power_state(
132 const struct pp_hw_power_state *hw_ps)
133 {
134 if (hw_ps == NULL)
135 return NULL;
136
137 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
138 "Invalid Powerstate Type!",
139 return NULL);
140
141 return (const struct tonga_power_state *)hw_ps;
142 }
143
144 int tonga_add_voltage(struct pp_hwmgr *hwmgr,
145 phm_ppt_v1_voltage_lookup_table *look_up_table,
146 phm_ppt_v1_voltage_lookup_record *record)
147 {
148 uint32_t i;
149 PP_ASSERT_WITH_CODE((NULL != look_up_table),
150 "Lookup Table empty.", return -1;);
151 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
152 "Lookup Table empty.", return -1;);
153 PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
154 "Lookup Table is full.", return -1;);
155
156 /* This is to avoid entering duplicate calculated records. */
157 for (i = 0; i < look_up_table->count; i++) {
158 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
159 if (look_up_table->entries[i].us_calculated == 1)
160 return 0;
161 else
162 break;
163 }
164 }
165
166 look_up_table->entries[i].us_calculated = 1;
167 look_up_table->entries[i].us_vdd = record->us_vdd;
168 look_up_table->entries[i].us_cac_low = record->us_cac_low;
169 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
170 look_up_table->entries[i].us_cac_high = record->us_cac_high;
171 /* Only increment the count when we're appending, not replacing duplicate entry. */
172 if (i == look_up_table->count)
173 look_up_table->count++;
174
175 return 0;
176 }
177
178 int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
179 {
180 PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
181
182 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
183 }
184
185 uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
186 uint32_t voltage)
187 {
188 uint8_t count = (uint8_t) (voltage_table->count);
189 uint8_t i = 0;
190
191 PP_ASSERT_WITH_CODE((NULL != voltage_table),
192 "Voltage Table empty.", return 0;);
193 PP_ASSERT_WITH_CODE((0 != count),
194 "Voltage Table empty.", return 0;);
195
196 for (i = 0; i < count; i++) {
197 /* find first voltage bigger than requested */
198 if (voltage_table->entries[i].value >= voltage)
199 return i;
200 }
201
202 /* voltage is bigger than max voltage in the table */
203 return i - 1;
204 }
205
206 /**
207 * @brief PhwTonga_GetVoltageOrder
208 * Returns index of requested voltage record in lookup(table)
209 * @param hwmgr - pointer to hardware manager
210 * @param lookupTable - lookup list to search in
211 * @param voltage - voltage to look for
212 * @return 0 on success
213 */
214 uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
215 uint16_t voltage)
216 {
217 uint8_t count = (uint8_t) (look_up_table->count);
218 uint8_t i;
219
220 PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
221 PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
222
223 for (i = 0; i < count; i++) {
224 /* find first voltage equal or bigger than requested */
225 if (look_up_table->entries[i].us_vdd >= voltage)
226 return i;
227 }
228
229 /* voltage is bigger than max voltage in the table */
230 return i-1;
231 }
232
233 bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
234 {
235 /*
236 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
237 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
238 * whereas voltage control is a fundemental change that will not be disabled
239 */
240
241 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
242 FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
243 }
244
245 /**
246 * Re-generate the DPM level mask value
247 * @param hwmgr the address of the hardware manager
248 */
249 static uint32_t tonga_get_dpm_level_enable_mask_value(
250 struct tonga_single_dpm_table * dpm_table)
251 {
252 uint32_t i;
253 uint32_t mask_value = 0;
254
255 for (i = dpm_table->count; i > 0; i--) {
256 mask_value = mask_value << 1;
257
258 if (dpm_table->dpm_levels[i-1].enabled)
259 mask_value |= 0x1;
260 else
261 mask_value &= 0xFFFFFFFE;
262 }
263 return mask_value;
264 }
265
266 /**
267 * Retrieve DPM default values from registry (if available)
268 *
269 * @param hwmgr the address of the powerplay hardware manager.
270 */
271 void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
272 {
273 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
274 phw_tonga_ulv_parm *ulv = &(data->ulv);
275 uint32_t tmp;
276
277 ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
278 data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
279 data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
280 data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
281 data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
282 data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
283 data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
284 data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
285 data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
286
287 data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
288 data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
289
290 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_ABM);
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 PHM_PlatformCaps_NonABMSupportInPPLib);
294
295 tmp = 0;
296 if (tmp == 0)
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 PHM_PlatformCaps_DynamicACTiming);
299
300 tmp = 0;
301 if (0 != tmp)
302 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
303 PHM_PlatformCaps_DisableMemoryTransition);
304
305 data->mclk_strobe_mode_threshold = 40000;
306 data->mclk_stutter_mode_threshold = 30000;
307 data->mclk_edc_enable_threshold = 40000;
308 data->mclk_edc_wr_enable_threshold = 40000;
309
310 tmp = 0;
311 if (tmp != 0)
312 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313 PHM_PlatformCaps_DisableMCLS);
314
315 data->pcie_gen_performance.max = PP_PCIEGen1;
316 data->pcie_gen_performance.min = PP_PCIEGen3;
317 data->pcie_gen_power_saving.max = PP_PCIEGen1;
318 data->pcie_gen_power_saving.min = PP_PCIEGen3;
319
320 data->pcie_lane_performance.max = 0;
321 data->pcie_lane_performance.min = 16;
322 data->pcie_lane_power_saving.max = 0;
323 data->pcie_lane_power_saving.min = 16;
324
325 tmp = 0;
326
327 if (tmp)
328 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
329 PHM_PlatformCaps_SclkThrottleLowNotification);
330
331 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
332 PHM_PlatformCaps_DynamicUVDState);
333
334 }
335
336 int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
337 {
338 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
339
340 int result = 0;
341 uint32_t low_sclk_interrupt_threshold = 0;
342
343 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
344 PHM_PlatformCaps_SclkThrottleLowNotification)
345 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
346 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
347 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
348
349 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
350
351 result = tonga_copy_bytes_to_smc(
352 hwmgr->smumgr,
353 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
354 LowSclkInterruptThreshold),
355 (uint8_t *)&low_sclk_interrupt_threshold,
356 sizeof(uint32_t),
357 data->sram_end
358 );
359 }
360
361 return result;
362 }
363
364 /**
365 * Find SCLK value that is associated with specified virtual_voltage_Id.
366 *
367 * @param hwmgr the address of the powerplay hardware manager.
368 * @param virtual_voltage_Id voltageId to look for.
369 * @param sclk output value .
370 * @return always 0 if success and 2 if association not found
371 */
372 static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
373 phm_ppt_v1_voltage_lookup_table *lookup_table,
374 uint16_t virtual_voltage_id, uint32_t *sclk)
375 {
376 uint8_t entryId;
377 uint8_t voltageId;
378 struct phm_ppt_v1_information *pptable_info =
379 (struct phm_ppt_v1_information *)(hwmgr->pptable);
380
381 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
382
383 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
384 for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
385 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
386 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
387 break;
388 }
389
390 PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
391 "Can't find requested voltage id in vdd_dep_on_sclk table!",
392 return -1;
393 );
394
395 *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
396
397 return 0;
398 }
399
400 /**
401 * Get Leakage VDDC based on leakage ID.
402 *
403 * @param hwmgr the address of the powerplay hardware manager.
404 * @return 2 if vddgfx returned is greater than 2V or if BIOS
405 */
406 int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
407 {
408 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
409 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
410 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
411 uint16_t virtual_voltage_id;
412 uint16_t vddc = 0;
413 uint16_t vddgfx = 0;
414 uint16_t i, j;
415 uint32_t sclk = 0;
416
417 /* retrieve voltage for leakage ID (0xff01 + i) */
418 for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
419 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
420
421 /* in split mode we should have only vddgfx EVV leakages */
422 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
423 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
424 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
425 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
426 PHM_PlatformCaps_ClockStretcher)) {
427 for (j = 1; j < sclk_table->count; j++) {
428 if (sclk_table->entries[j].clk == sclk &&
429 sclk_table->entries[j].cks_enable == 0) {
430 sclk += 5000;
431 break;
432 }
433 }
434 }
435 if (0 == atomctrl_get_voltage_evv_on_sclk
436 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
437 virtual_voltage_id, &vddgfx)) {
438 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
439 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
440
441 /* the voltage should not be zero nor equal to leakage ID */
442 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
443 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
444 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
445 data->vddcgfx_leakage.count++;
446 }
447 } else {
448 printk("Error retrieving EVV voltage value!\n");
449 }
450 }
451 } else {
452 /* in merged mode we have only vddc EVV leakages */
453 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
454 pptable_info->vddc_lookup_table,
455 virtual_voltage_id, &sclk)) {
456 if (0 == atomctrl_get_voltage_evv_on_sclk
457 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
458 virtual_voltage_id, &vddc)) {
459 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
460 PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
461
462 /* the voltage should not be zero nor equal to leakage ID */
463 if (vddc != 0 && vddc != virtual_voltage_id) {
464 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
465 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
466 data->vddc_leakage.count++;
467 }
468 } else {
469 printk("Error retrieving EVV voltage value!\n");
470 }
471 }
472 }
473 }
474
475 return 0;
476 }
477
478 int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
479 {
480 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
481
482 /* enable SCLK dpm */
483 if (0 == data->sclk_dpm_key_disabled) {
484 PP_ASSERT_WITH_CODE(
485 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
486 PPSMC_MSG_DPM_Enable)),
487 "Failed to enable SCLK DPM during DPM Start Function!",
488 return -1);
489 }
490
491 /* enable MCLK dpm */
492 if (0 == data->mclk_dpm_key_disabled) {
493 PP_ASSERT_WITH_CODE(
494 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
495 PPSMC_MSG_MCLKDPM_Enable)),
496 "Failed to enable MCLK DPM during DPM Start Function!",
497 return -1);
498
499 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
500
501 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
502 ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
503 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
504 ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
505 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
506 ixLCAC_CPL_CNTL, 0x100005);/*Read */
507
508 udelay(10);
509
510 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
511 ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
512 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
513 ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
514 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
515 ixLCAC_CPL_CNTL, 0x500005);/* write */
516
517 }
518
519 return 0;
520 }
521
522 int tonga_start_dpm(struct pp_hwmgr *hwmgr)
523 {
524 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
525
526 /* enable general power management */
527 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
528 /* enable sclk deep sleep */
529 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
530
531 /* prepare for PCIE DPM */
532 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
533 offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
534
535 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
536
537 PP_ASSERT_WITH_CODE(
538 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
539 PPSMC_MSG_Voltage_Cntl_Enable)),
540 "Failed to enable voltage DPM during DPM Start Function!",
541 return -1);
542
543 if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
544 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
545 }
546
547 /* enable PCIE dpm */
548 if (0 == data->pcie_dpm_key_disabled) {
549 PP_ASSERT_WITH_CODE(
550 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
551 PPSMC_MSG_PCIeDPM_Enable)),
552 "Failed to enable pcie DPM during DPM Start Function!",
553 return -1
554 );
555 }
556
557 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
558 PHM_PlatformCaps_Falcon_QuickTransition)) {
559 smum_send_msg_to_smc(hwmgr->smumgr,
560 PPSMC_MSG_EnableACDCGPIOInterrupt);
561 }
562
563 return 0;
564 }
565
566 int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
567 {
568 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
569
570 /* disable SCLK dpm */
571 if (0 == data->sclk_dpm_key_disabled) {
572 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
573 PP_ASSERT_WITH_CODE(
574 !tonga_is_dpm_running(hwmgr),
575 "Trying to Disable SCLK DPM when DPM is disabled",
576 return -1
577 );
578
579 PP_ASSERT_WITH_CODE(
580 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
581 PPSMC_MSG_DPM_Disable)),
582 "Failed to disable SCLK DPM during DPM stop Function!",
583 return -1);
584 }
585
586 /* disable MCLK dpm */
587 if (0 == data->mclk_dpm_key_disabled) {
588 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
589 PP_ASSERT_WITH_CODE(
590 !tonga_is_dpm_running(hwmgr),
591 "Trying to Disable MCLK DPM when DPM is disabled",
592 return -1
593 );
594
595 PP_ASSERT_WITH_CODE(
596 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
597 PPSMC_MSG_MCLKDPM_Disable)),
598 "Failed to Disable MCLK DPM during DPM stop Function!",
599 return -1);
600 }
601
602 return 0;
603 }
604
605 int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
606 {
607 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
608
609 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
610 /* disable sclk deep sleep*/
611 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
612
613 /* disable PCIE dpm */
614 if (0 == data->pcie_dpm_key_disabled) {
615 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
616 PP_ASSERT_WITH_CODE(
617 !tonga_is_dpm_running(hwmgr),
618 "Trying to Disable PCIE DPM when DPM is disabled",
619 return -1
620 );
621 PP_ASSERT_WITH_CODE(
622 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
623 PPSMC_MSG_PCIeDPM_Disable)),
624 "Failed to disable pcie DPM during DPM stop Function!",
625 return -1);
626 }
627
628 if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
629 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
630
631 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
632 PP_ASSERT_WITH_CODE(
633 !tonga_is_dpm_running(hwmgr),
634 "Trying to Disable Voltage CNTL when DPM is disabled",
635 return -1
636 );
637
638 PP_ASSERT_WITH_CODE(
639 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
640 PPSMC_MSG_Voltage_Cntl_Disable)),
641 "Failed to disable voltage DPM during DPM stop Function!",
642 return -1);
643
644 return 0;
645 }
646
647 int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
648 {
649 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
650
651 return 0;
652 }
653
654 /**
655 * Send a message to the SMC and return a parameter
656 *
657 * @param hwmgr: the address of the powerplay hardware manager.
658 * @param msg: the message to send.
659 * @param parameter: pointer to the received parameter
660 * @return The response that came from the SMC.
661 */
662 PPSMC_Result tonga_send_msg_to_smc_return_parameter(
663 struct pp_hwmgr *hwmgr,
664 PPSMC_Msg msg,
665 uint32_t *parameter)
666 {
667 int result;
668
669 result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
670
671 if ((0 == result) && parameter) {
672 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
673 }
674
675 return result;
676 }
677
678 /**
679 * force DPM power State
680 *
681 * @param hwmgr: the address of the powerplay hardware manager.
682 * @param n : DPM level
683 * @return The response that came from the SMC.
684 */
685 int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
686 {
687 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
688 uint32_t level_mask = 1 << n;
689
690 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
691 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
692 "Trying to force SCLK when DPM is disabled",
693 return -1;);
694 if (0 == data->sclk_dpm_key_disabled)
695 return (0 == smum_send_msg_to_smc_with_parameter(
696 hwmgr->smumgr,
697 (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
698 level_mask) ? 0 : 1);
699
700 return 0;
701 }
702
703 /**
704 * force DPM power State
705 *
706 * @param hwmgr: the address of the powerplay hardware manager.
707 * @param n : DPM level
708 * @return The response that came from the SMC.
709 */
710 int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
711 {
712 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
713 uint32_t level_mask = 1 << n;
714
715 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
716 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
717 "Trying to Force MCLK when DPM is disabled",
718 return -1;);
719 if (0 == data->mclk_dpm_key_disabled)
720 return (0 == smum_send_msg_to_smc_with_parameter(
721 hwmgr->smumgr,
722 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
723 level_mask) ? 0 : 1);
724
725 return 0;
726 }
727
728 /**
729 * force DPM power State
730 *
731 * @param hwmgr: the address of the powerplay hardware manager.
732 * @param n : DPM level
733 * @return The response that came from the SMC.
734 */
735 int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
736 {
737 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
738
739 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
740 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
741 "Trying to Force PCIE level when DPM is disabled",
742 return -1;);
743 if (0 == data->pcie_dpm_key_disabled)
744 return (0 == smum_send_msg_to_smc_with_parameter(
745 hwmgr->smumgr,
746 (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
747 n) ? 0 : 1);
748
749 return 0;
750 }
751
752 /**
753 * Set the initial state by calling SMC to switch to this state directly
754 *
755 * @param hwmgr the address of the powerplay hardware manager.
756 * @return always 0
757 */
758 int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
759 {
760 /*
761 * SMC only stores one state that SW will ask to switch too,
762 * so we switch the the just uploaded one
763 */
764 return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
765 }
766
767 /**
768 * Get the location of various tables inside the FW image.
769 *
770 * @param hwmgr the address of the powerplay hardware manager.
771 * @return always 0
772 */
773 int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
774 {
775 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
776 struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
777
778 uint32_t tmp;
779 int result;
780 bool error = false;
781
782 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
783 SMU72_FIRMWARE_HEADER_LOCATION +
784 offsetof(SMU72_Firmware_Header, DpmTable),
785 &tmp, data->sram_end);
786
787 if (0 == result) {
788 data->dpm_table_start = tmp;
789 }
790
791 error |= (0 != result);
792
793 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
794 SMU72_FIRMWARE_HEADER_LOCATION +
795 offsetof(SMU72_Firmware_Header, SoftRegisters),
796 &tmp, data->sram_end);
797
798 if (0 == result) {
799 data->soft_regs_start = tmp;
800 tonga_smu->ulSoftRegsStart = tmp;
801 }
802
803 error |= (0 != result);
804
805
806 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
807 SMU72_FIRMWARE_HEADER_LOCATION +
808 offsetof(SMU72_Firmware_Header, mcRegisterTable),
809 &tmp, data->sram_end);
810
811 if (0 == result) {
812 data->mc_reg_table_start = tmp;
813 }
814
815 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
816 SMU72_FIRMWARE_HEADER_LOCATION +
817 offsetof(SMU72_Firmware_Header, FanTable),
818 &tmp, data->sram_end);
819
820 if (0 == result) {
821 data->fan_table_start = tmp;
822 }
823
824 error |= (0 != result);
825
826 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
827 SMU72_FIRMWARE_HEADER_LOCATION +
828 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
829 &tmp, data->sram_end);
830
831 if (0 == result) {
832 data->arb_table_start = tmp;
833 }
834
835 error |= (0 != result);
836
837
838 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
839 SMU72_FIRMWARE_HEADER_LOCATION +
840 offsetof(SMU72_Firmware_Header, Version),
841 &tmp, data->sram_end);
842
843 if (0 == result) {
844 hwmgr->microcode_version_info.SMC = tmp;
845 }
846
847 error |= (0 != result);
848
849 return error ? 1 : 0;
850 }
851
852 /**
853 * Read clock related registers.
854 *
855 * @param hwmgr the address of the powerplay hardware manager.
856 * @return always 0
857 */
858 int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
859 {
860 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
861
862 data->clock_registers.vCG_SPLL_FUNC_CNTL =
863 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
864 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
865 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
866 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
867 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
868 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
869 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
870 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
871 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
872 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
873 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
874 data->clock_registers.vDLL_CNTL =
875 cgs_read_register(hwmgr->device, mmDLL_CNTL);
876 data->clock_registers.vMCLK_PWRMGT_CNTL =
877 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
878 data->clock_registers.vMPLL_AD_FUNC_CNTL =
879 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
880 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
881 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
882 data->clock_registers.vMPLL_FUNC_CNTL =
883 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
884 data->clock_registers.vMPLL_FUNC_CNTL_1 =
885 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
886 data->clock_registers.vMPLL_FUNC_CNTL_2 =
887 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
888 data->clock_registers.vMPLL_SS1 =
889 cgs_read_register(hwmgr->device, mmMPLL_SS1);
890 data->clock_registers.vMPLL_SS2 =
891 cgs_read_register(hwmgr->device, mmMPLL_SS2);
892
893 return 0;
894 }
895
896 /**
897 * Find out if memory is GDDR5.
898 *
899 * @param hwmgr the address of the powerplay hardware manager.
900 * @return always 0
901 */
902 int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
903 {
904 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
905 uint32_t temp;
906
907 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
908
909 data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
910 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
911 MC_SEQ_MISC0_GDDR5_SHIFT));
912
913 return 0;
914 }
915
916 /**
917 * Enables Dynamic Power Management by SMC
918 *
919 * @param hwmgr the address of the powerplay hardware manager.
920 * @return always 0
921 */
922 int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
923 {
924 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
925
926 return 0;
927 }
928
929 /**
930 * Initialize PowerGating States for different engines
931 *
932 * @param hwmgr the address of the powerplay hardware manager.
933 * @return always 0
934 */
935 int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
936 {
937 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
938
939 data->uvd_power_gated = false;
940 data->vce_power_gated = false;
941 data->samu_power_gated = false;
942 data->acp_power_gated = false;
943 data->pg_acp_init = true;
944
945 return 0;
946 }
947
948 /**
949 * Checks if DPM is enabled
950 *
951 * @param hwmgr the address of the powerplay hardware manager.
952 * @return always 0
953 */
954 int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
955 {
956 /*
957 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
958 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
959 * whereas voltage control is a fundemental change that will not be disabled
960 */
961 return (!tonga_is_dpm_running(hwmgr) ? 0 : 1);
962 }
963
964 /**
965 * Checks if DPM is stopped
966 *
967 * @param hwmgr the address of the powerplay hardware manager.
968 * @return always 0
969 */
970 int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
971 {
972 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
973
974 if (tonga_is_dpm_running(hwmgr)) {
975 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
976 if (!data->dpm_table_start) {
977 return 1;
978 }
979 }
980
981 return 0;
982 }
983
984 /**
985 * Remove repeated voltage values and create table with unique values.
986 *
987 * @param hwmgr the address of the powerplay hardware manager.
988 * @param voltage_table the pointer to changing voltage table
989 * @return 1 in success
990 */
991
992 static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
993 pp_atomctrl_voltage_table *voltage_table)
994 {
995 uint32_t table_size, i, j;
996 uint16_t vvalue;
997 bool bVoltageFound = false;
998 pp_atomctrl_voltage_table *table;
999
1000 PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
1001 table_size = sizeof(pp_atomctrl_voltage_table);
1002 table = kzalloc(table_size, GFP_KERNEL);
1003
1004 if (NULL == table)
1005 return -ENOMEM;
1006
1007 memset(table, 0x00, table_size);
1008 table->mask_low = voltage_table->mask_low;
1009 table->phase_delay = voltage_table->phase_delay;
1010
1011 for (i = 0; i < voltage_table->count; i++) {
1012 vvalue = voltage_table->entries[i].value;
1013 bVoltageFound = false;
1014
1015 for (j = 0; j < table->count; j++) {
1016 if (vvalue == table->entries[j].value) {
1017 bVoltageFound = true;
1018 break;
1019 }
1020 }
1021
1022 if (!bVoltageFound) {
1023 table->entries[table->count].value = vvalue;
1024 table->entries[table->count].smio_low =
1025 voltage_table->entries[i].smio_low;
1026 table->count++;
1027 }
1028 }
1029
1030 memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1031
1032 kfree(table);
1033
1034 return 0;
1035 }
1036
1037 static int tonga_get_svi2_vdd_ci_voltage_table(
1038 struct pp_hwmgr *hwmgr,
1039 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1040 {
1041 uint32_t i;
1042 int result;
1043 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1044 pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1045
1046 PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1047 "Voltage Dependency Table empty.", return -1;);
1048
1049 vddci_voltage_table->mask_low = 0;
1050 vddci_voltage_table->phase_delay = 0;
1051 vddci_voltage_table->count = voltage_dependency_table->count;
1052
1053 for (i = 0; i < voltage_dependency_table->count; i++) {
1054 vddci_voltage_table->entries[i].value =
1055 voltage_dependency_table->entries[i].vddci;
1056 vddci_voltage_table->entries[i].smio_low = 0;
1057 }
1058
1059 result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1060 PP_ASSERT_WITH_CODE((0 == result),
1061 "Failed to trim VDDCI table.", return result;);
1062
1063 return 0;
1064 }
1065
1066
1067
1068 static int tonga_get_svi2_vdd_voltage_table(
1069 struct pp_hwmgr *hwmgr,
1070 phm_ppt_v1_voltage_lookup_table *look_up_table,
1071 pp_atomctrl_voltage_table *voltage_table)
1072 {
1073 uint8_t i = 0;
1074
1075 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1076 "Voltage Lookup Table empty.", return -1;);
1077
1078 voltage_table->mask_low = 0;
1079 voltage_table->phase_delay = 0;
1080
1081 voltage_table->count = look_up_table->count;
1082
1083 for (i = 0; i < voltage_table->count; i++) {
1084 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1085 voltage_table->entries[i].smio_low = 0;
1086 }
1087
1088 return 0;
1089 }
1090
1091 /*
1092 * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1093 * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1094 */
1095
1096 static void tonga_trim_voltage_table_to_fit_state_table(
1097 struct pp_hwmgr *hwmgr,
1098 uint32_t max_voltage_steps,
1099 pp_atomctrl_voltage_table *voltage_table)
1100 {
1101 unsigned int i, diff;
1102
1103 if (voltage_table->count <= max_voltage_steps) {
1104 return;
1105 }
1106
1107 diff = voltage_table->count - max_voltage_steps;
1108
1109 for (i = 0; i < max_voltage_steps; i++) {
1110 voltage_table->entries[i] = voltage_table->entries[i + diff];
1111 }
1112
1113 voltage_table->count = max_voltage_steps;
1114
1115 return;
1116 }
1117
1118 /**
1119 * Create Voltage Tables.
1120 *
1121 * @param hwmgr the address of the powerplay hardware manager.
1122 * @return always 0
1123 */
1124 int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1125 {
1126 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1127 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1128 int result;
1129
1130 /* MVDD has only GPIO voltage control */
1131 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1132 result = atomctrl_get_voltage_table_v3(hwmgr,
1133 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1134 PP_ASSERT_WITH_CODE((0 == result),
1135 "Failed to retrieve MVDD table.", return result;);
1136 }
1137
1138 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1139 /* GPIO voltage */
1140 result = atomctrl_get_voltage_table_v3(hwmgr,
1141 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1142 PP_ASSERT_WITH_CODE((0 == result),
1143 "Failed to retrieve VDDCI table.", return result;);
1144 } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1145 /* SVI2 voltage */
1146 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1147 pptable_info->vdd_dep_on_mclk);
1148 PP_ASSERT_WITH_CODE((0 == result),
1149 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1150 }
1151
1152 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1153 /* VDDGFX has only SVI2 voltage control */
1154 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1155 pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1156 PP_ASSERT_WITH_CODE((0 == result),
1157 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1158 }
1159
1160 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1161 /* VDDC has only SVI2 voltage control */
1162 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1163 pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1164 PP_ASSERT_WITH_CODE((0 == result),
1165 "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1166 }
1167
1168 PP_ASSERT_WITH_CODE(
1169 (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1170 "Too many voltage values for VDDC. Trimming to fit state table.",
1171 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1172 SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1173 );
1174
1175 PP_ASSERT_WITH_CODE(
1176 (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1177 "Too many voltage values for VDDGFX. Trimming to fit state table.",
1178 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1179 SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1180 );
1181
1182 PP_ASSERT_WITH_CODE(
1183 (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1184 "Too many voltage values for VDDCI. Trimming to fit state table.",
1185 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1186 SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1187 );
1188
1189 PP_ASSERT_WITH_CODE(
1190 (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1191 "Too many voltage values for MVDD. Trimming to fit state table.",
1192 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1193 SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1194 );
1195
1196 return 0;
1197 }
1198
1199 /**
1200 * Vddc table preparation for SMC.
1201 *
1202 * @param hwmgr the address of the hardware manager
1203 * @param table the SMC DPM table structure to be populated
1204 * @return always 0
1205 */
1206 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1207 SMU72_Discrete_DpmTable *table)
1208 {
1209 unsigned int count;
1210 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1211
1212 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1213 table->VddcLevelCount = data->vddc_voltage_table.count;
1214 for (count = 0; count < table->VddcLevelCount; count++) {
1215 table->VddcTable[count] =
1216 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1217 }
1218 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1219 }
1220 return 0;
1221 }
1222
1223 /**
1224 * VddGfx table preparation for SMC.
1225 *
1226 * @param hwmgr the address of the hardware manager
1227 * @param table the SMC DPM table structure to be populated
1228 * @return always 0
1229 */
1230 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1231 SMU72_Discrete_DpmTable *table)
1232 {
1233 unsigned int count;
1234 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1235
1236 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1237 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1238 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1239 table->VddGfxTable[count] =
1240 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1241 }
1242 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1243 }
1244 return 0;
1245 }
1246
1247 /**
1248 * Vddci table preparation for SMC.
1249 *
1250 * @param *hwmgr The address of the hardware manager.
1251 * @param *table The SMC DPM table structure to be populated.
1252 * @return 0
1253 */
1254 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1255 SMU72_Discrete_DpmTable *table)
1256 {
1257 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1258 uint32_t count;
1259
1260 table->VddciLevelCount = data->vddci_voltage_table.count;
1261 for (count = 0; count < table->VddciLevelCount; count++) {
1262 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1263 table->VddciTable[count] =
1264 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1265 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1266 table->SmioTable1.Pattern[count].Voltage =
1267 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1268 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1269 table->SmioTable1.Pattern[count].Smio =
1270 (uint8_t) count;
1271 table->Smio[count] |=
1272 data->vddci_voltage_table.entries[count].smio_low;
1273 table->VddciTable[count] =
1274 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1275 }
1276 }
1277
1278 table->SmioMask1 = data->vddci_voltage_table.mask_low;
1279 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1280
1281 return 0;
1282 }
1283
1284 /**
1285 * Mvdd table preparation for SMC.
1286 *
1287 * @param *hwmgr The address of the hardware manager.
1288 * @param *table The SMC DPM table structure to be populated.
1289 * @return 0
1290 */
1291 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1292 SMU72_Discrete_DpmTable *table)
1293 {
1294 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1295 uint32_t count;
1296
1297 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1298 table->MvddLevelCount = data->mvdd_voltage_table.count;
1299 for (count = 0; count < table->MvddLevelCount; count++) {
1300 table->SmioTable2.Pattern[count].Voltage =
1301 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1302 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1303 table->SmioTable2.Pattern[count].Smio =
1304 (uint8_t) count;
1305 table->Smio[count] |=
1306 data->mvdd_voltage_table.entries[count].smio_low;
1307 }
1308 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
1309
1310 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1311 }
1312
1313 return 0;
1314 }
1315
1316 /**
1317 * Convert a voltage value in mv unit to VID number required by SMU firmware
1318 */
1319 static uint8_t convert_to_vid(uint16_t vddc)
1320 {
1321 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1322 }
1323
1324
1325 /**
1326 * Preparation of vddc and vddgfx CAC tables for SMC.
1327 *
1328 * @param hwmgr the address of the hardware manager
1329 * @param table the SMC DPM table structure to be populated
1330 * @return always 0
1331 */
1332 static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1333 SMU72_Discrete_DpmTable *table)
1334 {
1335 uint32_t count;
1336 uint8_t index;
1337 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1338 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1339 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1340 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1341
1342 /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1343 uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1344 uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1345
1346 for (count = 0; count < vddcLevelCount; count++) {
1347 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1348 index = tonga_get_voltage_index(vddc_lookup_table,
1349 data->vddc_voltage_table.entries[count].value);
1350 table->BapmVddcVidLoSidd[count] =
1351 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1352 table->BapmVddcVidHiSidd[count] =
1353 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1354 table->BapmVddcVidHiSidd2[count] =
1355 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1356 }
1357
1358 if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1359 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1360 for (count = 0; count < vddgfxLevelCount; count++) {
1361 index = tonga_get_voltage_index(vddgfx_lookup_table,
1362 data->vddgfx_voltage_table.entries[count].value);
1363 table->BapmVddGfxVidLoSidd[count] =
1364 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1365 table->BapmVddGfxVidHiSidd[count] =
1366 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1367 table->BapmVddGfxVidHiSidd2[count] =
1368 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1369 }
1370 } else {
1371 for (count = 0; count < vddcLevelCount; count++) {
1372 index = tonga_get_voltage_index(vddc_lookup_table,
1373 data->vddc_voltage_table.entries[count].value);
1374 table->BapmVddGfxVidLoSidd[count] =
1375 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1376 table->BapmVddGfxVidHiSidd[count] =
1377 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1378 table->BapmVddGfxVidHiSidd2[count] =
1379 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1380 }
1381 }
1382
1383 return 0;
1384 }
1385
1386
1387 /**
1388 * Preparation of voltage tables for SMC.
1389 *
1390 * @param hwmgr the address of the hardware manager
1391 * @param table the SMC DPM table structure to be populated
1392 * @return always 0
1393 */
1394
1395 int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1396 SMU72_Discrete_DpmTable *table)
1397 {
1398 int result;
1399
1400 result = tonga_populate_smc_vddc_table(hwmgr, table);
1401 PP_ASSERT_WITH_CODE(0 == result,
1402 "can not populate VDDC voltage table to SMC", return -1);
1403
1404 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1405 PP_ASSERT_WITH_CODE(0 == result,
1406 "can not populate VDDCI voltage table to SMC", return -1);
1407
1408 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1409 PP_ASSERT_WITH_CODE(0 == result,
1410 "can not populate VDDGFX voltage table to SMC", return -1);
1411
1412 result = tonga_populate_smc_mvdd_table(hwmgr, table);
1413 PP_ASSERT_WITH_CODE(0 == result,
1414 "can not populate MVDD voltage table to SMC", return -1);
1415
1416 result = tonga_populate_cac_tables(hwmgr, table);
1417 PP_ASSERT_WITH_CODE(0 == result,
1418 "can not populate CAC voltage tables to SMC", return -1);
1419
1420 return 0;
1421 }
1422
1423 /**
1424 * Populates the SMC VRConfig field in DPM table.
1425 *
1426 * @param hwmgr the address of the hardware manager
1427 * @param table the SMC DPM table structure to be populated
1428 * @return always 0
1429 */
1430 static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1431 SMU72_Discrete_DpmTable *table)
1432 {
1433 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1434 uint16_t config;
1435
1436 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1437 /* Splitted mode */
1438 config = VR_SVI2_PLANE_1;
1439 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1440
1441 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1442 config = VR_SVI2_PLANE_2;
1443 table->VRConfig |= config;
1444 } else {
1445 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1446 }
1447 } else {
1448 /* Merged mode */
1449 config = VR_MERGED_WITH_VDDC;
1450 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1451
1452 /* Set Vddc Voltage Controller */
1453 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1454 config = VR_SVI2_PLANE_1;
1455 table->VRConfig |= config;
1456 } else {
1457 printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1458 }
1459 }
1460
1461 /* Set Vddci Voltage Controller */
1462 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1463 config = VR_SVI2_PLANE_2; /* only in merged mode */
1464 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1465 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1466 config = VR_SMIO_PATTERN_1;
1467 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1468 }
1469
1470 /* Set Mvdd Voltage Controller */
1471 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1472 config = VR_SMIO_PATTERN_2;
1473 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1474 }
1475
1476 return 0;
1477 }
1478
1479 static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1480 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1481 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1482 {
1483 uint32_t i = 0;
1484 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1485 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1486
1487 /* clock - voltage dependency table is empty table */
1488 if (allowed_clock_voltage_table->count == 0)
1489 return -1;
1490
1491 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1492 /* find first sclk bigger than request */
1493 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1494 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1495 allowed_clock_voltage_table->entries[i].vddgfx);
1496
1497 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1498 allowed_clock_voltage_table->entries[i].vddc);
1499
1500 if (allowed_clock_voltage_table->entries[i].vddci) {
1501 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1502 allowed_clock_voltage_table->entries[i].vddci);
1503 } else {
1504 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1505 allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1506 }
1507
1508 if (allowed_clock_voltage_table->entries[i].mvdd) {
1509 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1510 }
1511
1512 voltage->Phases = 1;
1513 return 0;
1514 }
1515 }
1516
1517 /* sclk is bigger than max sclk in the dependence table */
1518 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1519 allowed_clock_voltage_table->entries[i-1].vddgfx);
1520 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1521 allowed_clock_voltage_table->entries[i-1].vddc);
1522
1523 if (allowed_clock_voltage_table->entries[i-1].vddci) {
1524 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1525 allowed_clock_voltage_table->entries[i-1].vddci);
1526 }
1527 if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1528 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1529 }
1530
1531 return 0;
1532 }
1533
1534 /**
1535 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1536 *
1537 * @param hwmgr the address of the powerplay hardware manager.
1538 * @return always 0
1539 */
1540 int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1541 {
1542 return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1543 }
1544
1545 int tonga_populate_memory_timing_parameters(
1546 struct pp_hwmgr *hwmgr,
1547 uint32_t engine_clock,
1548 uint32_t memory_clock,
1549 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1550 )
1551 {
1552 uint32_t dramTiming;
1553 uint32_t dramTiming2;
1554 uint32_t burstTime;
1555 int result;
1556
1557 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1558 engine_clock, memory_clock);
1559
1560 PP_ASSERT_WITH_CODE(result == 0,
1561 "Error calling VBIOS to set DRAM_TIMING.", return result);
1562
1563 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1564 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1565 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1566
1567 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1568 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1569 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1570
1571 return 0;
1572 }
1573
1574 /**
1575 * Setup parameters for the MC ARB.
1576 *
1577 * @param hwmgr the address of the powerplay hardware manager.
1578 * @return always 0
1579 * This function is to be called from the SetPowerState table.
1580 */
1581 int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1582 {
1583 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1584 int result = 0;
1585 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1586 uint32_t i, j;
1587
1588 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1589
1590 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1591 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1592 result = tonga_populate_memory_timing_parameters
1593 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1594 data->dpm_table.mclk_table.dpm_levels[j].value,
1595 &arb_regs.entries[i][j]);
1596
1597 if (0 != result) {
1598 break;
1599 }
1600 }
1601 }
1602
1603 if (0 == result) {
1604 result = tonga_copy_bytes_to_smc(
1605 hwmgr->smumgr,
1606 data->arb_table_start,
1607 (uint8_t *)&arb_regs,
1608 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1609 data->sram_end
1610 );
1611 }
1612
1613 return result;
1614 }
1615
1616 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1617 {
1618 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1619 struct tonga_dpm_table *dpm_table = &data->dpm_table;
1620 uint32_t i;
1621
1622 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1623 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1624 table->LinkLevel[i].PcieGenSpeed =
1625 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1626 table->LinkLevel[i].PcieLaneCount =
1627 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1628 table->LinkLevel[i].EnabledForActivity =
1629 1;
1630 table->LinkLevel[i].SPC =
1631 (uint8_t)(data->pcie_spc_cap & 0xff);
1632 table->LinkLevel[i].DownThreshold =
1633 PP_HOST_TO_SMC_UL(5);
1634 table->LinkLevel[i].UpThreshold =
1635 PP_HOST_TO_SMC_UL(30);
1636 }
1637
1638 data->smc_state_table.LinkLevelCount =
1639 (uint8_t)dpm_table->pcie_speed_table.count;
1640 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1641 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1642
1643 return 0;
1644 }
1645
1646 static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1647 SMU72_Discrete_DpmTable *table)
1648 {
1649 int result = 0;
1650
1651 uint8_t count;
1652 pp_atomctrl_clock_dividers_vi dividers;
1653 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1654 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1655 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1656
1657 table->UvdLevelCount = (uint8_t) (mm_table->count);
1658 table->UvdBootLevel = 0;
1659
1660 for (count = 0; count < table->UvdLevelCount; count++) {
1661 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1662 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1663 table->UvdLevel[count].MinVoltage.Vddc =
1664 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1665 mm_table->entries[count].vddc);
1666 table->UvdLevel[count].MinVoltage.VddGfx =
1667 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1668 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1669 mm_table->entries[count].vddgfx) : 0;
1670 table->UvdLevel[count].MinVoltage.Vddci =
1671 tonga_get_voltage_id(&data->vddci_voltage_table,
1672 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1673 table->UvdLevel[count].MinVoltage.Phases = 1;
1674
1675 /* retrieve divider value for VBIOS */
1676 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1677 table->UvdLevel[count].VclkFrequency, &dividers);
1678 PP_ASSERT_WITH_CODE((0 == result),
1679 "can not find divide id for Vclk clock", return result);
1680
1681 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1682
1683 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1684 table->UvdLevel[count].DclkFrequency, &dividers);
1685 PP_ASSERT_WITH_CODE((0 == result),
1686 "can not find divide id for Dclk clock", return result);
1687
1688 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1689
1690 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692 //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
1693 }
1694
1695 return result;
1696
1697 }
1698
1699 static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1700 SMU72_Discrete_DpmTable *table)
1701 {
1702 int result = 0;
1703
1704 uint8_t count;
1705 pp_atomctrl_clock_dividers_vi dividers;
1706 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1707 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1708 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1709
1710 table->VceLevelCount = (uint8_t) (mm_table->count);
1711 table->VceBootLevel = 0;
1712
1713 for (count = 0; count < table->VceLevelCount; count++) {
1714 table->VceLevel[count].Frequency =
1715 mm_table->entries[count].eclk;
1716 table->VceLevel[count].MinVoltage.Vddc =
1717 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1718 mm_table->entries[count].vddc);
1719 table->VceLevel[count].MinVoltage.VddGfx =
1720 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1721 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1722 mm_table->entries[count].vddgfx) : 0;
1723 table->VceLevel[count].MinVoltage.Vddci =
1724 tonga_get_voltage_id(&data->vddci_voltage_table,
1725 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1726 table->VceLevel[count].MinVoltage.Phases = 1;
1727
1728 /* retrieve divider value for VBIOS */
1729 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1730 table->VceLevel[count].Frequency, &dividers);
1731 PP_ASSERT_WITH_CODE((0 == result),
1732 "can not find divide id for VCE engine clock", return result);
1733
1734 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1735
1736 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1737 }
1738
1739 return result;
1740 }
1741
1742 static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1743 SMU72_Discrete_DpmTable *table)
1744 {
1745 int result = 0;
1746 uint8_t count;
1747 pp_atomctrl_clock_dividers_vi dividers;
1748 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1749 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1750 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1751
1752 table->AcpLevelCount = (uint8_t) (mm_table->count);
1753 table->AcpBootLevel = 0;
1754
1755 for (count = 0; count < table->AcpLevelCount; count++) {
1756 table->AcpLevel[count].Frequency =
1757 pptable_info->mm_dep_table->entries[count].aclk;
1758 table->AcpLevel[count].MinVoltage.Vddc =
1759 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1760 mm_table->entries[count].vddc);
1761 table->AcpLevel[count].MinVoltage.VddGfx =
1762 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1763 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1764 mm_table->entries[count].vddgfx) : 0;
1765 table->AcpLevel[count].MinVoltage.Vddci =
1766 tonga_get_voltage_id(&data->vddci_voltage_table,
1767 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1768 table->AcpLevel[count].MinVoltage.Phases = 1;
1769
1770 /* retrieve divider value for VBIOS */
1771 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1772 table->AcpLevel[count].Frequency, &dividers);
1773 PP_ASSERT_WITH_CODE((0 == result),
1774 "can not find divide id for engine clock", return result);
1775
1776 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1777
1778 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1779 }
1780
1781 return result;
1782 }
1783
1784 static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1785 SMU72_Discrete_DpmTable *table)
1786 {
1787 int result = 0;
1788 uint8_t count;
1789 pp_atomctrl_clock_dividers_vi dividers;
1790 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1791 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1792 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1793
1794 table->SamuBootLevel = 0;
1795 table->SamuLevelCount = (uint8_t) (mm_table->count);
1796
1797 for (count = 0; count < table->SamuLevelCount; count++) {
1798 /* not sure whether we need evclk or not */
1799 table->SamuLevel[count].Frequency =
1800 pptable_info->mm_dep_table->entries[count].samclock;
1801 table->SamuLevel[count].MinVoltage.Vddc =
1802 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1803 mm_table->entries[count].vddc);
1804 table->SamuLevel[count].MinVoltage.VddGfx =
1805 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1806 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1807 mm_table->entries[count].vddgfx) : 0;
1808 table->SamuLevel[count].MinVoltage.Vddci =
1809 tonga_get_voltage_id(&data->vddci_voltage_table,
1810 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1811 table->SamuLevel[count].MinVoltage.Phases = 1;
1812
1813 /* retrieve divider value for VBIOS */
1814 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1815 table->SamuLevel[count].Frequency, &dividers);
1816 PP_ASSERT_WITH_CODE((0 == result),
1817 "can not find divide id for samu clock", return result);
1818
1819 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1820
1821 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1822 }
1823
1824 return result;
1825 }
1826
1827 /**
1828 * Populates the SMC MCLK structure using the provided memory clock
1829 *
1830 * @param hwmgr the address of the hardware manager
1831 * @param memory_clock the memory clock to use to populate the structure
1832 * @param sclk the SMC SCLK structure to be populated
1833 */
1834 static int tonga_calculate_mclk_params(
1835 struct pp_hwmgr *hwmgr,
1836 uint32_t memory_clock,
1837 SMU72_Discrete_MemoryLevel *mclk,
1838 bool strobe_mode,
1839 bool dllStateOn
1840 )
1841 {
1842 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1843 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1844 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1845 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1846 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1847 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1848 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1849 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1850 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1851 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1852
1853 pp_atomctrl_memory_clock_param mpll_param;
1854 int result;
1855
1856 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1857 memory_clock, &mpll_param, strobe_mode);
1858 PP_ASSERT_WITH_CODE(0 == result,
1859 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1860
1861 /* MPLL_FUNC_CNTL setup*/
1862 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1863
1864 /* MPLL_FUNC_CNTL_1 setup*/
1865 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1866 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1867 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1868 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1869 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1870 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1871
1872 /* MPLL_AD_FUNC_CNTL setup*/
1873 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1874 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1875
1876 if (data->is_memory_GDDR5) {
1877 /* MPLL_DQ_FUNC_CNTL setup*/
1878 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1879 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1880 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1881 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1882 }
1883
1884 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1885 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1886 /*
1887 ************************************
1888 Fref = Reference Frequency
1889 NF = Feedback divider ratio
1890 NR = Reference divider ratio
1891 Fnom = Nominal VCO output frequency = Fref * NF / NR
1892 Fs = Spreading Rate
1893 D = Percentage down-spread / 2
1894 Fint = Reference input frequency to PFD = Fref / NR
1895 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1896 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1897 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1898 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1899 *************************************
1900 */
1901 pp_atomctrl_internal_ss_info ss_info;
1902 uint32_t freq_nom;
1903 uint32_t tmp;
1904 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1905
1906 /* for GDDR5 for all modes and DDR3 */
1907 if (1 == mpll_param.qdr)
1908 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1909 else
1910 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1911
1912 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1913 tmp = (freq_nom / reference_clock);
1914 tmp = tmp * tmp;
1915
1916 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1917 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1918 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1919 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1920 /* = reference_clock * 5 / speed_spectrum_rate */
1921 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1922
1923 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1924 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1925 uint32_t clkv =
1926 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1927 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1928
1929 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1930 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1931 }
1932 }
1933
1934 /* MCLK_PWRMGT_CNTL setup */
1935 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1936 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1937 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1938 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1939 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1940 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1941
1942
1943 /* Save the result data to outpupt memory level structure */
1944 mclk->MclkFrequency = memory_clock;
1945 mclk->MpllFuncCntl = mpll_func_cntl;
1946 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1947 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1948 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1949 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1950 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1951 mclk->DllCntl = dll_cntl;
1952 mclk->MpllSs1 = mpll_ss1;
1953 mclk->MpllSs2 = mpll_ss2;
1954
1955 return 0;
1956 }
1957
1958 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1959 bool strobe_mode)
1960 {
1961 uint8_t mc_para_index;
1962
1963 if (strobe_mode) {
1964 if (memory_clock < 12500) {
1965 mc_para_index = 0x00;
1966 } else if (memory_clock > 47500) {
1967 mc_para_index = 0x0f;
1968 } else {
1969 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1970 }
1971 } else {
1972 if (memory_clock < 65000) {
1973 mc_para_index = 0x00;
1974 } else if (memory_clock > 135000) {
1975 mc_para_index = 0x0f;
1976 } else {
1977 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1978 }
1979 }
1980
1981 return mc_para_index;
1982 }
1983
1984 static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1985 {
1986 uint8_t mc_para_index;
1987
1988 if (memory_clock < 10000) {
1989 mc_para_index = 0;
1990 } else if (memory_clock >= 80000) {
1991 mc_para_index = 0x0f;
1992 } else {
1993 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1994 }
1995
1996 return mc_para_index;
1997 }
1998
1999 static int tonga_populate_single_memory_level(
2000 struct pp_hwmgr *hwmgr,
2001 uint32_t memory_clock,
2002 SMU72_Discrete_MemoryLevel *memory_level
2003 )
2004 {
2005 uint32_t minMvdd = 0;
2006 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2007 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2008 int result = 0;
2009 bool dllStateOn;
2010 struct cgs_display_info info = {0};
2011
2012
2013 if (NULL != pptable_info->vdd_dep_on_mclk) {
2014 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2015 pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
2016 PP_ASSERT_WITH_CODE((0 == result),
2017 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
2018 }
2019
2020 if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
2021 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
2022 } else {
2023 memory_level->MinMvdd = minMvdd;
2024 }
2025 memory_level->EnabledForThrottle = 1;
2026 memory_level->EnabledForActivity = 0;
2027 memory_level->UpHyst = 0;
2028 memory_level->DownHyst = 100;
2029 memory_level->VoltageDownHyst = 0;
2030
2031 /* Indicates maximum activity level for this performance level.*/
2032 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2033 memory_level->StutterEnable = 0;
2034 memory_level->StrobeEnable = 0;
2035 memory_level->EdcReadEnable = 0;
2036 memory_level->EdcWriteEnable = 0;
2037 memory_level->RttEnable = 0;
2038
2039 /* default set to low watermark. Highest level will be set to high later.*/
2040 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2041
2042 cgs_get_active_displays_info(hwmgr->device, &info);
2043 data->display_timing.num_existing_displays = info.display_count;
2044
2045 if ((data->mclk_stutter_mode_threshold != 0) &&
2046 (memory_clock <= data->mclk_stutter_mode_threshold) &&
2047 (!data->is_uvd_enabled)
2048 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2049 && (data->display_timing.num_existing_displays <= 2)
2050 && (data->display_timing.num_existing_displays != 0))
2051 memory_level->StutterEnable = 1;
2052
2053 /* decide strobe mode*/
2054 memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2055 (memory_clock <= data->mclk_strobe_mode_threshold);
2056
2057 /* decide EDC mode and memory clock ratio*/
2058 if (data->is_memory_GDDR5) {
2059 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2060 memory_level->StrobeEnable);
2061
2062 if ((data->mclk_edc_enable_threshold != 0) &&
2063 (memory_clock > data->mclk_edc_enable_threshold)) {
2064 memory_level->EdcReadEnable = 1;
2065 }
2066
2067 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2068 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2069 memory_level->EdcWriteEnable = 1;
2070 }
2071
2072 if (memory_level->StrobeEnable) {
2073 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2074 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2075 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2076 } else {
2077 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2078 }
2079
2080 } else {
2081 dllStateOn = data->dll_defaule_on;
2082 }
2083 } else {
2084 memory_level->StrobeRatio =
2085 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2086 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2087 }
2088
2089 result = tonga_calculate_mclk_params(hwmgr,
2090 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2091
2092 if (0 == result) {
2093 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2094 /* MCLK frequency in units of 10KHz*/
2095 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2096 /* Indicates maximum activity level for this performance level.*/
2097 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2098 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2099 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2100 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2101 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2102 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2103 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2104 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2105 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2106 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2107 }
2108
2109 return result;
2110 }
2111
2112 /**
2113 * Populates the SMC MVDD structure using the provided memory clock.
2114 *
2115 * @param hwmgr the address of the hardware manager
2116 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2117 * @param voltage the SMC VOLTAGE structure to be populated
2118 */
2119 int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2120 {
2121 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2122 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2123 uint32_t i = 0;
2124
2125 if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2126 /* find mvdd value which clock is more than request */
2127 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2128 if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2129 /* Always round to higher voltage. */
2130 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2131 break;
2132 }
2133 }
2134
2135 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2136 "MVDD Voltage is outside the supported range.", return -1);
2137
2138 } else {
2139 return -1;
2140 }
2141
2142 return 0;
2143 }
2144
2145
2146 static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2147 SMU72_Discrete_DpmTable *table)
2148 {
2149 int result = 0;
2150 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2151 pp_atomctrl_clock_dividers_vi dividers;
2152 SMIO_Pattern voltage_level;
2153 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2154 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2155 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
2156 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
2157
2158 /* The ACPI state should not do DPM on DC (or ever).*/
2159 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2160
2161 table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2162
2163 /* assign zero for now*/
2164 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2165
2166 /* get the engine clock dividers for this clock value*/
2167 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2168 table->ACPILevel.SclkFrequency, &dividers);
2169
2170 PP_ASSERT_WITH_CODE(result == 0,
2171 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2172
2173 /* divider ID for required SCLK*/
2174 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2175 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2176 table->ACPILevel.DeepSleepDivId = 0;
2177
2178 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2179 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
2180 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2181 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
2182 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
2183 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
2184
2185 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2186 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2187 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2188 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2189 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2190 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2191 table->ACPILevel.CcPwrDynRm = 0;
2192 table->ACPILevel.CcPwrDynRm1 = 0;
2193
2194
2195 /* For various features to be enabled/disabled while this level is active.*/
2196 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2197 /* SCLK frequency in units of 10KHz*/
2198 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2199 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2200 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2201 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2202 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2203 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2204 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2205 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2206 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2207
2208 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2209 table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2210
2211 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2212
2213 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2214 table->MemoryACPILevel.MinMvdd =
2215 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2216 else
2217 table->MemoryACPILevel.MinMvdd = 0;
2218
2219 /* Force reset on DLL*/
2220 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2221 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2222 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2223 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2224
2225 /* Disable DLL in ACPIState*/
2226 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2227 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2228 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2229 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2230
2231 /* Enable DLL bypass signal*/
2232 dll_cntl = PHM_SET_FIELD(dll_cntl,
2233 DLL_CNTL, MRDCK0_BYPASS, 0);
2234 dll_cntl = PHM_SET_FIELD(dll_cntl,
2235 DLL_CNTL, MRDCK1_BYPASS, 0);
2236
2237 table->MemoryACPILevel.DllCntl =
2238 PP_HOST_TO_SMC_UL(dll_cntl);
2239 table->MemoryACPILevel.MclkPwrmgtCntl =
2240 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2241 table->MemoryACPILevel.MpllAdFuncCntl =
2242 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2243 table->MemoryACPILevel.MpllDqFuncCntl =
2244 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2245 table->MemoryACPILevel.MpllFuncCntl =
2246 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2247 table->MemoryACPILevel.MpllFuncCntl_1 =
2248 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2249 table->MemoryACPILevel.MpllFuncCntl_2 =
2250 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2251 table->MemoryACPILevel.MpllSs1 =
2252 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2253 table->MemoryACPILevel.MpllSs2 =
2254 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2255
2256 table->MemoryACPILevel.EnabledForThrottle = 0;
2257 table->MemoryACPILevel.EnabledForActivity = 0;
2258 table->MemoryACPILevel.UpHyst = 0;
2259 table->MemoryACPILevel.DownHyst = 100;
2260 table->MemoryACPILevel.VoltageDownHyst = 0;
2261 /* Indicates maximum activity level for this performance level.*/
2262 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2263
2264 table->MemoryACPILevel.StutterEnable = 0;
2265 table->MemoryACPILevel.StrobeEnable = 0;
2266 table->MemoryACPILevel.EdcReadEnable = 0;
2267 table->MemoryACPILevel.EdcWriteEnable = 0;
2268 table->MemoryACPILevel.RttEnable = 0;
2269
2270 return result;
2271 }
2272
2273 static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2274 {
2275 int result = 0;
2276 uint32_t i;
2277
2278 for (i = 0; i < table->count; i++) {
2279 if (value == table->dpm_levels[i].value) {
2280 *boot_level = i;
2281 result = 0;
2282 }
2283 }
2284 return result;
2285 }
2286
2287 static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2288 SMU72_Discrete_DpmTable *table)
2289 {
2290 int result = 0;
2291 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2292
2293 table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2294 table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2295
2296 /* find boot level from dpm table*/
2297 result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2298 data->vbios_boot_state.sclk_bootup_value,
2299 (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2300
2301 if (0 != result) {
2302 data->smc_state_table.GraphicsBootLevel = 0;
2303 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2304 in dependency table. Using Graphics DPM level 0!");
2305 result = 0;
2306 }
2307
2308 result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2309 data->vbios_boot_state.mclk_bootup_value,
2310 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2311
2312 if (0 != result) {
2313 data->smc_state_table.MemoryBootLevel = 0;
2314 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2315 in dependency table. Using Memory DPM level 0!");
2316 result = 0;
2317 }
2318
2319 table->BootVoltage.Vddc =
2320 tonga_get_voltage_id(&(data->vddc_voltage_table),
2321 data->vbios_boot_state.vddc_bootup_value);
2322 table->BootVoltage.VddGfx =
2323 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2324 data->vbios_boot_state.vddgfx_bootup_value);
2325 table->BootVoltage.Vddci =
2326 tonga_get_voltage_id(&(data->vddci_voltage_table),
2327 data->vbios_boot_state.vddci_bootup_value);
2328 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2329
2330 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2331
2332 return result;
2333 }
2334
2335
2336 /**
2337 * Calculates the SCLK dividers using the provided engine clock
2338 *
2339 * @param hwmgr the address of the hardware manager
2340 * @param engine_clock the engine clock to use to populate the structure
2341 * @param sclk the SMC SCLK structure to be populated
2342 */
2343 int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2344 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2345 {
2346 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2347 pp_atomctrl_clock_dividers_vi dividers;
2348 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2349 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2350 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2351 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2352 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2353 uint32_t reference_clock;
2354 uint32_t reference_divider;
2355 uint32_t fbdiv;
2356 int result;
2357
2358 /* get the engine clock dividers for this clock value*/
2359 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
2360
2361 PP_ASSERT_WITH_CODE(result == 0,
2362 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2363
2364 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2365 reference_clock = atomctrl_get_reference_clock(hwmgr);
2366
2367 reference_divider = 1 + dividers.uc_pll_ref_div;
2368
2369 /* low 14 bits is fraction and high 12 bits is divider*/
2370 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2371
2372 /* SPLL_FUNC_CNTL setup*/
2373 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2374 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2375 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2376 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
2377
2378 /* SPLL_FUNC_CNTL_3 setup*/
2379 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2380 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2381
2382 /* set to use fractional accumulation*/
2383 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2384 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2385
2386 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2387 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2388 pp_atomctrl_internal_ss_info ss_info;
2389
2390 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2391 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2392 /*
2393 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2394 * ss_info.speed_spectrum_rate -- in unit of khz
2395 */
2396 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2397 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2398
2399 /* clkv = 2 * D * fbdiv / NS */
2400 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2401
2402 cg_spll_spread_spectrum =
2403 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2404 cg_spll_spread_spectrum =
2405 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2406 cg_spll_spread_spectrum_2 =
2407 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2408 }
2409 }
2410
2411 sclk->SclkFrequency = engine_clock;
2412 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2413 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2414 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2415 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2416 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
2417
2418 return 0;
2419 }
2420
2421 static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock,
2422 uint32_t min_engine_clock_in_sr)
2423 {
2424 uint32_t i, temp;
2425 uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK);
2426
2427 PP_ASSERT_WITH_CODE((engine_clock >= min),
2428 "Engine clock can't satisfy stutter requirement!", return 0);
2429
2430 for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
2431 temp = engine_clock >> i;
2432
2433 if(temp >= min || i == 0)
2434 break;
2435 }
2436 return (uint8_t)i;
2437 }
2438
2439 /**
2440 * Populates single SMC SCLK structure using the provided engine clock
2441 *
2442 * @param hwmgr the address of the hardware manager
2443 * @param engine_clock the engine clock to use to populate the structure
2444 * @param sclk the SMC SCLK structure to be populated
2445 */
2446 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2447 {
2448 int result;
2449 uint32_t threshold;
2450 uint32_t mvdd;
2451 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2452 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2453
2454 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2455
2456
2457 /* populate graphics levels*/
2458 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2459 pptable_info->vdd_dep_on_sclk, engine_clock,
2460 &graphic_level->MinVoltage, &mvdd);
2461 PP_ASSERT_WITH_CODE((0 == result),
2462 "can not find VDDC voltage value for VDDC \
2463 engine clock dependency table", return result);
2464
2465 /* SCLK frequency in units of 10KHz*/
2466 graphic_level->SclkFrequency = engine_clock;
2467
2468 /* Indicates maximum activity level for this performance level. 50% for now*/
2469 graphic_level->ActivityLevel = sclk_activity_level_threshold;
2470
2471 graphic_level->CcPwrDynRm = 0;
2472 graphic_level->CcPwrDynRm1 = 0;
2473 /* this level can be used if activity is high enough.*/
2474 graphic_level->EnabledForActivity = 0;
2475 /* this level can be used for throttling.*/
2476 graphic_level->EnabledForThrottle = 1;
2477 graphic_level->UpHyst = 0;
2478 graphic_level->DownHyst = 0;
2479 graphic_level->VoltageDownHyst = 0;
2480 graphic_level->PowerThrottle = 0;
2481
2482 threshold = engine_clock * data->fast_watemark_threshold / 100;
2483 /*
2484 *get the DAL clock. do it in funture.
2485 PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2486 data->display_timing.min_clock_insr = minClocks.engineClockInSR;
2487 */
2488 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2489 PHM_PlatformCaps_SclkDeepSleep))
2490 graphic_level->DeepSleepDivId =
2491 tonga_get_sleep_divider_id_from_clock(engine_clock,
2492 data->display_timing.min_clock_insr);
2493
2494 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2495 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2496
2497 if (0 == result) {
2498 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2499 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2500 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2501 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2502 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2503 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2504 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2505 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2506 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2507 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2508 }
2509
2510 return result;
2511 }
2512
2513 /**
2514 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2515 *
2516 * @param hwmgr the address of the hardware manager
2517 */
2518 static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2519 {
2520 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2521 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2522 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2523 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2524 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2525 int result = 0;
2526 uint32_t level_array_adress = data->dpm_table_start +
2527 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2528 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2529 SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
2530 SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2531 uint32_t i, maxEntry;
2532 uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2533 PECI_RegistryValue reg_value;
2534 memset(levels, 0x00, level_array_size);
2535
2536 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2537 result = tonga_populate_single_graphic_level(hwmgr,
2538 dpm_table->sclk_table.dpm_levels[i].value,
2539 (uint16_t)data->activity_target[i],
2540 &(data->smc_state_table.GraphicsLevel[i]));
2541
2542 if (0 != result)
2543 return result;
2544
2545 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2546 if (i > 1)
2547 data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2548
2549 if (0 == i) {
2550 reg_value = 0;
2551 if (reg_value != 0)
2552 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2553 }
2554
2555 if (1 == i) {
2556 reg_value = 0;
2557 if (reg_value != 0)
2558 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2559 }
2560 }
2561
2562 /* Only enable level 0 for now. */
2563 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2564
2565 /* set highest level watermark to high */
2566 if (dpm_table->sclk_table.count > 1)
2567 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2568 PPSMC_DISPLAY_WATERMARK_HIGH;
2569
2570 data->smc_state_table.GraphicsDpmLevelCount =
2571 (uint8_t)dpm_table->sclk_table.count;
2572 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2573 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2574
2575 if (pcie_table != NULL) {
2576 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2577 "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2578 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2579 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2580 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2581 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2582 }
2583 } else {
2584 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2585 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2586
2587 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2588 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2589 (1<<(highest_pcie_level_enabled+1))) != 0)) {
2590 highest_pcie_level_enabled++;
2591 }
2592
2593 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2594 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2595 (1<<lowest_pcie_level_enabled)) == 0)) {
2596 lowest_pcie_level_enabled++;
2597 }
2598
2599 while ((count < highest_pcie_level_enabled) &&
2600 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2601 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2602 count++;
2603 }
2604 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2605 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2606
2607
2608 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2609 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2610 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2611 }
2612
2613 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2614 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2615
2616 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2617 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2618 }
2619 /* level count will send to smc once at init smc table and never change*/
2620 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2621
2622 if (0 != result)
2623 return result;
2624
2625 return 0;
2626 }
2627
2628 /**
2629 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2630 *
2631 * @param hwmgr the address of the hardware manager
2632 */
2633
2634 static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2635 {
2636 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2637 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2638 int result;
2639 /* populate MCLK dpm table to SMU7 */
2640 uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2641 uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2642 SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2643 uint32_t i;
2644
2645 memset(levels, 0x00, level_array_size);
2646
2647 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2648 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2649 "can not populate memory level as memory clock is zero", return -1);
2650 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2651 &(data->smc_state_table.MemoryLevel[i]));
2652 if (0 != result) {
2653 return result;
2654 }
2655 }
2656
2657 /* Only enable level 0 for now.*/
2658 data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2659
2660 /*
2661 * in order to prevent MC activity from stutter mode to push DPM up.
2662 * the UVD change complements this by putting the MCLK in a higher state
2663 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2664 */
2665 data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2666 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2667
2668 data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2669 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2670 /* set highest level watermark to high*/
2671 data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2672
2673 /* level count will send to smc once at init smc table and never change*/
2674 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2675 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2676
2677 if (0 != result) {
2678 return result;
2679 }
2680
2681 return 0;
2682 }
2683
2684 struct TONGA_DLL_SPEED_SETTING {
2685 uint16_t Min; /* Minimum Data Rate*/
2686 uint16_t Max; /* Maximum Data Rate*/
2687 uint32_t dll_speed; /* The desired DLL_SPEED setting*/
2688 };
2689
2690 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2691 {
2692 return 0;
2693 }
2694
2695 /* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2696
2697
2698 static int tonga_reset_single_dpm_table(
2699 struct pp_hwmgr *hwmgr,
2700 struct tonga_single_dpm_table *dpm_table,
2701 uint32_t count)
2702 {
2703 uint32_t i;
2704 if (!(count <= MAX_REGULAR_DPM_NUMBER))
2705 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2706 table entries to exceed max number! \n");
2707
2708 dpm_table->count = count;
2709 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2710 dpm_table->dpm_levels[i].enabled = false;
2711 }
2712
2713 return 0;
2714 }
2715
2716 static void tonga_setup_pcie_table_entry(
2717 struct tonga_single_dpm_table *dpm_table,
2718 uint32_t index, uint32_t pcie_gen,
2719 uint32_t pcie_lanes)
2720 {
2721 dpm_table->dpm_levels[index].value = pcie_gen;
2722 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2723 dpm_table->dpm_levels[index].enabled = true;
2724 }
2725
2726 static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2727 {
2728 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2729 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2730 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2731 uint32_t i, maxEntry;
2732
2733 if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2734 data->pcie_gen_power_saving = data->pcie_gen_performance;
2735 data->pcie_lane_power_saving = data->pcie_lane_performance;
2736 } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2737 data->pcie_gen_performance = data->pcie_gen_power_saving;
2738 data->pcie_lane_performance = data->pcie_lane_power_saving;
2739 }
2740
2741 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2742
2743 if (pcie_table != NULL) {
2744 /*
2745 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2746 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2747 */
2748 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2749 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2750 for (i = 1; i < maxEntry; i++) {
2751 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2752 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2753 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2754 }
2755 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2756 } else {
2757 /* Hardcode Pcie Table */
2758 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2759 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2760 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2761 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2762 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2763 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2764 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2765 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2766 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2767 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2768 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2769 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2770 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2771 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2772 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2773 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2774 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2775 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2776 data->dpm_table.pcie_speed_table.count = 6;
2777 }
2778 /* Populate last level for boot PCIE level, but do not increment count. */
2779 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2780 data->dpm_table.pcie_speed_table.count,
2781 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2782 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2783
2784 return 0;
2785
2786 }
2787
2788 /*
2789 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2790 * Dynamic state patching function will then trim these state tables to the allowed range based
2791 * on the power policy or external client requests, such as UVD request, etc.
2792 */
2793 static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2794 {
2795 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2796 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2797 uint32_t i;
2798
2799 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2800 pptable_info->vdd_dep_on_sclk;
2801 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2802 pptable_info->vdd_dep_on_mclk;
2803
2804 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2805 "SCLK dependency table is missing. This table is mandatory", return -1);
2806 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2807 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2808
2809 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2810 "MCLK dependency table is missing. This table is mandatory", return -1);
2811 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2812 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2813
2814 /* clear the state table to reset everything to default */
2815 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2816 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2817 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2818 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2819 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2820 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2821 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2822
2823 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2824 "SCLK dependency table is missing. This table is mandatory", return -1);
2825 /* Initialize Sclk DPM table based on allow Sclk values*/
2826 data->dpm_table.sclk_table.count = 0;
2827
2828 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2829 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2830 allowed_vdd_sclk_table->entries[i].clk) {
2831 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2832 allowed_vdd_sclk_table->entries[i].clk;
2833 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */
2834 data->dpm_table.sclk_table.count++;
2835 }
2836 }
2837
2838 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2839 "MCLK dependency table is missing. This table is mandatory", return -1);
2840 /* Initialize Mclk DPM table based on allow Mclk values */
2841 data->dpm_table.mclk_table.count = 0;
2842 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2843 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2844 allowed_vdd_mclk_table->entries[i].clk) {
2845 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2846 allowed_vdd_mclk_table->entries[i].clk;
2847 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */
2848 data->dpm_table.mclk_table.count++;
2849 }
2850 }
2851
2852 /* setup PCIE gen speed levels*/
2853 tonga_setup_default_pcie_tables(hwmgr);
2854
2855 /* save a copy of the default DPM table*/
2856 memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2857
2858 return 0;
2859 }
2860
2861 int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2862 const struct tonga_power_state *bootState)
2863 {
2864 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2865 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2866 uint8_t count, level;
2867
2868 count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2869 for (level = 0; level < count; level++) {
2870 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2871 bootState->performance_levels[0].engine_clock) {
2872 data->smc_state_table.GraphicsBootLevel = level;
2873 break;
2874 }
2875 }
2876
2877 count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2878 for (level = 0; level < count; level++) {
2879 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2880 bootState->performance_levels[0].memory_clock) {
2881 data->smc_state_table.MemoryBootLevel = level;
2882 break;
2883 }
2884 }
2885
2886 return 0;
2887 }
2888
2889 /**
2890 * Initializes the SMC table and uploads it
2891 *
2892 * @param hwmgr the address of the powerplay hardware manager.
2893 * @param pInput the pointer to input data (PowerState)
2894 * @return always 0
2895 */
2896 int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2897 {
2898 int result;
2899 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2900 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2901 SMU72_Discrete_DpmTable *table = &(data->smc_state_table);
2902 const phw_tonga_ulv_parm *ulv = &(data->ulv);
2903 uint8_t i;
2904 PECI_RegistryValue reg_value;
2905 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2906
2907 result = tonga_setup_default_dpm_tables(hwmgr);
2908 PP_ASSERT_WITH_CODE(0 == result,
2909 "Failed to setup default DPM tables!", return result;);
2910 memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2911 if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2912 tonga_populate_smc_voltage_tables(hwmgr, table);
2913 }
2914
2915 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2916 PHM_PlatformCaps_AutomaticDCTransition)) {
2917 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2918 }
2919
2920 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2921 PHM_PlatformCaps_StepVddc)) {
2922 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2923 }
2924
2925 if (data->is_memory_GDDR5) {
2926 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2927 }
2928
2929 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2930
2931 if (i == 1 || i == 0) {
2932 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2933 }
2934
2935 if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2936 PP_ASSERT_WITH_CODE(0 == result,
2937 "Failed to initialize ULV state!", return result;);
2938
2939 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2940 ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2941 }
2942
2943 result = tonga_populate_smc_link_level(hwmgr, table);
2944 PP_ASSERT_WITH_CODE(0 == result,
2945 "Failed to initialize Link Level!", return result;);
2946
2947 result = tonga_populate_all_graphic_levels(hwmgr);
2948 PP_ASSERT_WITH_CODE(0 == result,
2949 "Failed to initialize Graphics Level!", return result;);
2950
2951 result = tonga_populate_all_memory_levels(hwmgr);
2952 PP_ASSERT_WITH_CODE(0 == result,
2953 "Failed to initialize Memory Level!", return result;);
2954
2955 result = tonga_populate_smv_acpi_level(hwmgr, table);
2956 PP_ASSERT_WITH_CODE(0 == result,
2957 "Failed to initialize ACPI Level!", return result;);
2958
2959 result = tonga_populate_smc_vce_level(hwmgr, table);
2960 PP_ASSERT_WITH_CODE(0 == result,
2961 "Failed to initialize VCE Level!", return result;);
2962
2963 result = tonga_populate_smc_acp_level(hwmgr, table);
2964 PP_ASSERT_WITH_CODE(0 == result,
2965 "Failed to initialize ACP Level!", return result;);
2966
2967 result = tonga_populate_smc_samu_level(hwmgr, table);
2968 PP_ASSERT_WITH_CODE(0 == result,
2969 "Failed to initialize SAMU Level!", return result;);
2970
2971 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2972 /* need to populate the ARB settings for the initial state. */
2973 result = tonga_program_memory_timing_parameters(hwmgr);
2974 PP_ASSERT_WITH_CODE(0 == result,
2975 "Failed to Write ARB settings for the initial state.", return result;);
2976
2977 result = tonga_populate_smc_uvd_level(hwmgr, table);
2978 PP_ASSERT_WITH_CODE(0 == result,
2979 "Failed to initialize UVD Level!", return result;);
2980
2981 result = tonga_populate_smc_boot_level(hwmgr, table);
2982 PP_ASSERT_WITH_CODE(0 == result,
2983 "Failed to initialize Boot Level!", return result;);
2984
2985 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2986 PHM_PlatformCaps_ClockStretcher)) {
2987 result = tonga_populate_clock_stretcher_data_table(hwmgr);
2988 PP_ASSERT_WITH_CODE(0 == result,
2989 "Failed to populate Clock Stretcher Data Table!", return result;);
2990 }
2991 table->GraphicsVoltageChangeEnable = 1;
2992 table->GraphicsThermThrottleEnable = 1;
2993 table->GraphicsInterval = 1;
2994 table->VoltageInterval = 1;
2995 table->ThermalInterval = 1;
2996 table->TemperatureLimitHigh =
2997 pptable_info->cac_dtp_table->usTargetOperatingTemp *
2998 TONGA_Q88_FORMAT_CONVERSION_UNIT;
2999 table->TemperatureLimitLow =
3000 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3001 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3002 table->MemoryVoltageChangeEnable = 1;
3003 table->MemoryInterval = 1;
3004 table->VoltageResponseTime = 0;
3005 table->PhaseResponseTime = 0;
3006 table->MemoryThermThrottleEnable = 1;
3007
3008 /*
3009 * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3010 * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3011 * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3012 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3013 */
3014 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3015 "There must be 1 or more PCIE levels defined in PPTable.",
3016 return -1);
3017
3018 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3019
3020 table->PCIeGenInterval = 1;
3021
3022 result = tonga_populate_vr_config(hwmgr, table);
3023 PP_ASSERT_WITH_CODE(0 == result,
3024 "Failed to populate VRConfig setting!", return result);
3025
3026 table->ThermGpio = 17;
3027 table->SclkStepSize = 0x4000;
3028
3029 reg_value = 0;
3030 if ((0 == reg_value) &&
3031 (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
3032 &gpio_pin_assignment))) {
3033 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3034 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3035 PHM_PlatformCaps_RegulatorHot);
3036 } else {
3037 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3038 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3039 PHM_PlatformCaps_RegulatorHot);
3040 }
3041
3042 /* ACDC Switch GPIO */
3043 reg_value = 0;
3044 if ((0 == reg_value) &&
3045 (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3046 &gpio_pin_assignment))) {
3047 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3048 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3049 PHM_PlatformCaps_AutomaticDCTransition);
3050 } else {
3051 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3052 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3053 PHM_PlatformCaps_AutomaticDCTransition);
3054 }
3055
3056 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3057 PHM_PlatformCaps_Falcon_QuickTransition);
3058
3059 reg_value = 0;
3060 if (1 == reg_value) {
3061 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3062 PHM_PlatformCaps_AutomaticDCTransition);
3063 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3064 PHM_PlatformCaps_Falcon_QuickTransition);
3065 }
3066
3067 reg_value = 0;
3068 if ((0 == reg_value) && (atomctrl_get_pp_assign_pin(hwmgr,
3069 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3070 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3071 PHM_PlatformCaps_ThermalOutGPIO);
3072
3073 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3074
3075 table->ThermOutPolarity =
3076 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3077 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3078
3079 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3080
3081 /* if required, combine VRHot/PCC with thermal out GPIO*/
3082 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3083 PHM_PlatformCaps_RegulatorHot) &&
3084 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3085 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3086 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3087 }
3088 } else {
3089 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3090 PHM_PlatformCaps_ThermalOutGPIO);
3091
3092 table->ThermOutGpio = 17;
3093 table->ThermOutPolarity = 1;
3094 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3095 }
3096
3097 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3098 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3099 }
3100 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3101 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3102 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3103 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3104 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3105 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3106 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3107 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3108 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3109
3110 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3111 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3112 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3113 (uint8_t *)&(table->SystemFlags),
3114 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3115 data->sram_end);
3116
3117 PP_ASSERT_WITH_CODE(0 == result,
3118 "Failed to upload dpm data to SMC memory!", return result;);
3119
3120 return result;
3121 }
3122
3123 /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3124 static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3125 {
3126 return;
3127 }
3128
3129 int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3130 {
3131 PPSMC_Result result;
3132 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3133
3134 /* Apply minimum voltage based on DAL's request level */
3135 tonga_apply_dal_minimum_voltage_request(hwmgr);
3136
3137 if (0 == data->sclk_dpm_key_disabled) {
3138 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3139 if (tonga_is_dpm_running(hwmgr))
3140 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3141
3142 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3143 result = smum_send_msg_to_smc_with_parameter(
3144 hwmgr->smumgr,
3145 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3146 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3147 PP_ASSERT_WITH_CODE((0 == result),
3148 "Set Sclk Dpm enable Mask failed", return -1);
3149 }
3150 }
3151
3152 if (0 == data->mclk_dpm_key_disabled) {
3153 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3154 if (tonga_is_dpm_running(hwmgr))
3155 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3156
3157 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3158 result = smum_send_msg_to_smc_with_parameter(
3159 hwmgr->smumgr,
3160 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3161 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3162 PP_ASSERT_WITH_CODE((0 == result),
3163 "Set Mclk Dpm enable Mask failed", return -1);
3164 }
3165 }
3166
3167 return 0;
3168 }
3169
3170
3171 int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3172 {
3173 uint32_t level, tmp;
3174 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3175
3176 if (0 == data->pcie_dpm_key_disabled) {
3177 /* PCIE */
3178 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3179 level = 0;
3180 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3181 while (tmp >>= 1)
3182 level++ ;
3183
3184 if (0 != level) {
3185 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3186 "force highest pcie dpm state failed!", return -1);
3187 }
3188 }
3189 }
3190
3191 if (0 == data->sclk_dpm_key_disabled) {
3192 /* SCLK */
3193 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3194 level = 0;
3195 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3196 while (tmp >>= 1)
3197 level++ ;
3198
3199 if (0 != level) {
3200 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3201 "force highest sclk dpm state failed!", return -1);
3202 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3203 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3204 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3205 Curr_Sclk_Index does not match the level \n");
3206
3207 }
3208 }
3209 }
3210
3211 if (0 == data->mclk_dpm_key_disabled) {
3212 /* MCLK */
3213 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3214 level = 0;
3215 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3216 while (tmp >>= 1)
3217 level++ ;
3218
3219 if (0 != level) {
3220 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3221 "force highest mclk dpm state failed!", return -1);
3222 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3223 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3224 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3225 Curr_Mclk_Index does not match the level \n");
3226 }
3227 }
3228 }
3229
3230 return 0;
3231 }
3232
3233 /**
3234 * Find the MC microcode version and store it in the HwMgr struct
3235 *
3236 * @param hwmgr the address of the powerplay hardware manager.
3237 * @return always 0
3238 */
3239 int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3240 {
3241 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3242
3243 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3244
3245 return 0;
3246 }
3247
3248 /**
3249 * Initialize Dynamic State Adjustment Rule Settings
3250 *
3251 * @param hwmgr the address of the powerplay hardware manager.
3252 */
3253 int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3254 {
3255 uint32_t table_size;
3256 struct phm_clock_voltage_dependency_table *table_clk_vlt;
3257 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3258
3259 hwmgr->dyn_state.mclk_sclk_ratio = 4;
3260 hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */
3261 hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */
3262
3263 /* initialize vddc_dep_on_dal_pwrl table */
3264 table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3265 table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
3266
3267 if (NULL == table_clk_vlt) {
3268 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3269 return -ENOMEM;
3270 } else {
3271 table_clk_vlt->count = 4;
3272 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3273 table_clk_vlt->entries[0].v = 0;
3274 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3275 table_clk_vlt->entries[1].v = 720;
3276 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3277 table_clk_vlt->entries[2].v = 810;
3278 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3279 table_clk_vlt->entries[3].v = 900;
3280 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3281 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3282 }
3283
3284 return 0;
3285 }
3286
3287 static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3288 {
3289 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3290 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3291
3292 phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3293 pptable_info->vdd_dep_on_sclk;
3294 phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3295 pptable_info->vdd_dep_on_mclk;
3296
3297 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3298 "VDD dependency on SCLK table is missing. \
3299 This table is mandatory", return -1);
3300 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3301 "VDD dependency on SCLK table has to have is missing. \
3302 This table is mandatory", return -1);
3303
3304 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3305 "VDD dependency on MCLK table is missing. \
3306 This table is mandatory", return -1);
3307 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3308 "VDD dependency on MCLK table has to have is missing. \
3309 This table is mandatory", return -1);
3310
3311 data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3312 data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3313
3314 pptable_info->max_clock_voltage_on_ac.sclk =
3315 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3316 pptable_info->max_clock_voltage_on_ac.mclk =
3317 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3318 pptable_info->max_clock_voltage_on_ac.vddc =
3319 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3320 pptable_info->max_clock_voltage_on_ac.vddci =
3321 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3322
3323 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3324 pptable_info->max_clock_voltage_on_ac.sclk;
3325 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3326 pptable_info->max_clock_voltage_on_ac.mclk;
3327 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3328 pptable_info->max_clock_voltage_on_ac.vddc;
3329 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3330 pptable_info->max_clock_voltage_on_ac.vddci;
3331
3332 return 0;
3333 }
3334
3335 int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3336 {
3337 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3338 int result = 1;
3339
3340 PP_ASSERT_WITH_CODE (!tonga_is_dpm_running(hwmgr),
3341 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3342 return result);
3343
3344 if (0 == data->pcie_dpm_key_disabled) {
3345 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3346 hwmgr->smumgr,
3347 PPSMC_MSG_PCIeDPM_UnForceLevel)),
3348 "unforce pcie level failed!",
3349 return -1);
3350 }
3351
3352 result = tonga_upload_dpm_level_enable_mask(hwmgr);
3353
3354 return result;
3355 }
3356
3357 static uint32_t tonga_get_lowest_enable_level(
3358 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3359 {
3360 uint32_t level = 0;
3361
3362 while (0 == (level_mask & (1 << level)))
3363 level++;
3364
3365 return level;
3366 }
3367
3368 static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3369 {
3370 uint32_t level;
3371 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3372
3373 if (0 == data->pcie_dpm_key_disabled) {
3374 /* PCIE */
3375 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3376 level = tonga_get_lowest_enable_level(hwmgr,
3377 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3378 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3379 "force lowest pcie dpm state failed!", return -1);
3380 }
3381 }
3382
3383 if (0 == data->sclk_dpm_key_disabled) {
3384 /* SCLK */
3385 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3386 level = tonga_get_lowest_enable_level(hwmgr,
3387 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3388
3389 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3390 "force sclk dpm state failed!", return -1);
3391
3392 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3393 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3394 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3395 Curr_Sclk_Index does not match the level \n");
3396 }
3397 }
3398
3399 if (0 == data->mclk_dpm_key_disabled) {
3400 /* MCLK */
3401 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3402 level = tonga_get_lowest_enable_level(hwmgr,
3403 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3404 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3405 "force lowest mclk dpm state failed!", return -1);
3406 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3407 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3408 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3409 Curr_Mclk_Index does not match the level \n");
3410 }
3411 }
3412
3413 return 0;
3414 }
3415
3416 static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3417 {
3418 uint8_t entryId;
3419 uint8_t voltageId;
3420 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3421 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3422
3423 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3424 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3425 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3426
3427 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3428 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3429 voltageId = sclk_table->entries[entryId].vddInd;
3430 sclk_table->entries[entryId].vddgfx =
3431 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3432 }
3433 } else {
3434 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3435 voltageId = sclk_table->entries[entryId].vddInd;
3436 sclk_table->entries[entryId].vddc =
3437 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3438 }
3439 }
3440
3441 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3442 voltageId = mclk_table->entries[entryId].vddInd;
3443 mclk_table->entries[entryId].vddc =
3444 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3445 }
3446
3447 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3448 voltageId = mm_table->entries[entryId].vddcInd;
3449 mm_table->entries[entryId].vddc =
3450 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3451 }
3452
3453 return 0;
3454
3455 }
3456
3457 static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3458 {
3459 uint8_t entryId;
3460 phm_ppt_v1_voltage_lookup_record v_record;
3461 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3462 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3463
3464 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3465 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3466
3467 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3468 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3469 if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3470 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3471 sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3472 else
3473 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3474 sclk_table->entries[entryId].vdd_offset;
3475
3476 sclk_table->entries[entryId].vddc =
3477 v_record.us_cac_low = v_record.us_cac_mid =
3478 v_record.us_cac_high = v_record.us_vdd;
3479
3480 tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3481 }
3482
3483 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3484 if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3485 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3486 mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3487 else
3488 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3489 mclk_table->entries[entryId].vdd_offset;
3490
3491 mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3492 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3493 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3494 }
3495 }
3496
3497 return 0;
3498
3499 }
3500
3501 static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3502 {
3503 uint32_t entryId;
3504 phm_ppt_v1_voltage_lookup_record v_record;
3505 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3506 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3507 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3508
3509 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3510 for (entryId = 0; entryId < mm_table->count; entryId++) {
3511 if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3512 v_record.us_vdd = mm_table->entries[entryId].vddc +
3513 mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3514 else
3515 v_record.us_vdd = mm_table->entries[entryId].vddc +
3516 mm_table->entries[entryId].vddgfx_offset;
3517
3518 /* Add the calculated VDDGFX to the VDDGFX lookup table */
3519 mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3520 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3521 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3522 }
3523 }
3524 return 0;
3525 }
3526
3527
3528 /**
3529 * Change virtual leakage voltage to actual value.
3530 *
3531 * @param hwmgr the address of the powerplay hardware manager.
3532 * @param pointer to changing voltage
3533 * @param pointer to leakage table
3534 */
3535 static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3536 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3537 {
3538 uint32_t leakage_index;
3539
3540 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3541 for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3542 /* if this voltage matches a leakage voltage ID */
3543 /* patch with actual leakage voltage */
3544 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3545 *voltage = pLeakageTable->actual_voltage[leakage_index];
3546 break;
3547 }
3548 }
3549
3550 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3551 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3552 }
3553
3554 /**
3555 * Patch voltage lookup table by EVV leakages.
3556 *
3557 * @param hwmgr the address of the powerplay hardware manager.
3558 * @param pointer to voltage lookup table
3559 * @param pointer to leakage table
3560 * @return always 0
3561 */
3562 static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3563 phm_ppt_v1_voltage_lookup_table *lookup_table,
3564 phw_tonga_leakage_voltage *pLeakageTable)
3565 {
3566 uint32_t i;
3567
3568 for (i = 0; i < lookup_table->count; i++) {
3569 tonga_patch_with_vdd_leakage(hwmgr,
3570 &lookup_table->entries[i].us_vdd, pLeakageTable);
3571 }
3572
3573 return 0;
3574 }
3575
3576 static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3577 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3578 {
3579 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3580
3581 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3582 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3583 pptable_info->max_clock_voltage_on_dc.vddc;
3584
3585 return 0;
3586 }
3587
3588 static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3589 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3590 uint16_t *Vddgfx)
3591 {
3592 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3593 return 0;
3594 }
3595
3596 int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3597 phm_ppt_v1_voltage_lookup_table *lookup_table)
3598 {
3599 uint32_t table_size, i, j;
3600 phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3601 table_size = lookup_table->count;
3602
3603 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3604 "Lookup table is empty", return -1);
3605
3606 /* Sorting voltages */
3607 for (i = 0; i < table_size - 1; i++) {
3608 for (j = i + 1; j > 0; j--) {
3609 if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3610 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3611 lookup_table->entries[j-1] = lookup_table->entries[j];
3612 lookup_table->entries[j] = tmp_voltage_lookup_record;
3613 }
3614 }
3615 }
3616
3617 return 0;
3618 }
3619
3620 static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3621 {
3622 int result = 0;
3623 int tmp_result;
3624 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3625 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3626
3627 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3628 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3629 pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3630 if (tmp_result != 0)
3631 result = tmp_result;
3632
3633 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3634 &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3635 if (tmp_result != 0)
3636 result = tmp_result;
3637 } else {
3638 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3639 pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3640 if (tmp_result != 0)
3641 result = tmp_result;
3642
3643 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3644 &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3645 if (tmp_result != 0)
3646 result = tmp_result;
3647 }
3648
3649 tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3650 if (tmp_result != 0)
3651 result = tmp_result;
3652
3653 tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3654 if (tmp_result != 0)
3655 result = tmp_result;
3656
3657 tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3658 if (tmp_result != 0)
3659 result = tmp_result;
3660
3661 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3662 if (tmp_result != 0)
3663 result = tmp_result;
3664
3665 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3666 if (tmp_result != 0)
3667 result = tmp_result;
3668
3669 return result;
3670 }
3671
3672 int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3673 {
3674 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3675 data->low_sclk_interrupt_threshold = 0;
3676
3677 return 0;
3678 }
3679
3680 int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3681 {
3682 int tmp_result, result = 0;
3683
3684 tmp_result = tonga_read_clock_registers(hwmgr);
3685 PP_ASSERT_WITH_CODE((0 == tmp_result),
3686 "Failed to read clock registers!", result = tmp_result);
3687
3688 tmp_result = tonga_get_memory_type(hwmgr);
3689 PP_ASSERT_WITH_CODE((0 == tmp_result),
3690 "Failed to get memory type!", result = tmp_result);
3691
3692 tmp_result = tonga_enable_acpi_power_management(hwmgr);
3693 PP_ASSERT_WITH_CODE((0 == tmp_result),
3694 "Failed to enable ACPI power management!", result = tmp_result);
3695
3696 tmp_result = tonga_init_power_gate_state(hwmgr);
3697 PP_ASSERT_WITH_CODE((0 == tmp_result),
3698 "Failed to init power gate state!", result = tmp_result);
3699
3700 tmp_result = tonga_get_mc_microcode_version(hwmgr);
3701 PP_ASSERT_WITH_CODE((0 == tmp_result),
3702 "Failed to get MC microcode version!", result = tmp_result);
3703
3704 tmp_result = tonga_init_sclk_threshold(hwmgr);
3705 PP_ASSERT_WITH_CODE((0 == tmp_result),
3706 "Failed to init sclk threshold!", result = tmp_result);
3707
3708 return result;
3709 }
3710
3711 /**
3712 * Enable voltage control
3713 *
3714 * @param hwmgr the address of the powerplay hardware manager.
3715 * @return always 0
3716 */
3717 int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3718 {
3719 /* enable voltage control */
3720 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3721
3722 return 0;
3723 }
3724
3725 /**
3726 * Checks if we want to support voltage control
3727 *
3728 * @param hwmgr the address of the powerplay hardware manager.
3729 */
3730 bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3731 {
3732 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3733
3734 return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3735 }
3736
3737 /*---------------------------MC----------------------------*/
3738
3739 uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3740 {
3741 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3742 }
3743
3744 bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3745 {
3746 bool result = true;
3747
3748 switch (inReg) {
3749 case mmMC_SEQ_RAS_TIMING:
3750 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3751 break;
3752
3753 case mmMC_SEQ_DLL_STBY:
3754 *outReg = mmMC_SEQ_DLL_STBY_LP;
3755 break;
3756
3757 case mmMC_SEQ_G5PDX_CMD0:
3758 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3759 break;
3760
3761 case mmMC_SEQ_G5PDX_CMD1:
3762 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3763 break;
3764
3765 case mmMC_SEQ_G5PDX_CTRL:
3766 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3767 break;
3768
3769 case mmMC_SEQ_CAS_TIMING:
3770 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3771 break;
3772
3773 case mmMC_SEQ_MISC_TIMING:
3774 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3775 break;
3776
3777 case mmMC_SEQ_MISC_TIMING2:
3778 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3779 break;
3780
3781 case mmMC_SEQ_PMG_DVS_CMD:
3782 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3783 break;
3784
3785 case mmMC_SEQ_PMG_DVS_CTL:
3786 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3787 break;
3788
3789 case mmMC_SEQ_RD_CTL_D0:
3790 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3791 break;
3792
3793 case mmMC_SEQ_RD_CTL_D1:
3794 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3795 break;
3796
3797 case mmMC_SEQ_WR_CTL_D0:
3798 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3799 break;
3800
3801 case mmMC_SEQ_WR_CTL_D1:
3802 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3803 break;
3804
3805 case mmMC_PMG_CMD_EMRS:
3806 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3807 break;
3808
3809 case mmMC_PMG_CMD_MRS:
3810 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3811 break;
3812
3813 case mmMC_PMG_CMD_MRS1:
3814 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3815 break;
3816
3817 case mmMC_SEQ_PMG_TIMING:
3818 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3819 break;
3820
3821 case mmMC_PMG_CMD_MRS2:
3822 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3823 break;
3824
3825 case mmMC_SEQ_WR_CTL_2:
3826 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3827 break;
3828
3829 default:
3830 result = false;
3831 break;
3832 }
3833
3834 return result;
3835 }
3836
3837 int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3838 {
3839 uint32_t i;
3840 uint16_t address;
3841
3842 for (i = 0; i < table->last; i++) {
3843 table->mc_reg_address[i].s0 =
3844 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3845 ? address : table->mc_reg_address[i].s1;
3846 }
3847 return 0;
3848 }
3849
3850 int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3851 {
3852 uint8_t i, j;
3853
3854 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3855 "Invalid VramInfo table.", return -1);
3856 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3857 "Invalid VramInfo table.", return -1);
3858
3859 for (i = 0; i < table->last; i++) {
3860 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3861 }
3862 ni_table->last = table->last;
3863
3864 for (i = 0; i < table->num_entries; i++) {
3865 ni_table->mc_reg_table_entry[i].mclk_max =
3866 table->mc_reg_table_entry[i].mclk_max;
3867 for (j = 0; j < table->last; j++) {
3868 ni_table->mc_reg_table_entry[i].mc_data[j] =
3869 table->mc_reg_table_entry[i].mc_data[j];
3870 }
3871 }
3872
3873 ni_table->num_entries = table->num_entries;
3874
3875 return 0;
3876 }
3877
3878 /**
3879 * VBIOS omits some information to reduce size, we need to recover them here.
3880 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3881 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3882 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3883 * 3. need to set these data for each clock range
3884 *
3885 * @param hwmgr the address of the powerplay hardware manager.
3886 * @param table the address of MCRegTable
3887 * @return always 0
3888 */
3889 int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3890 {
3891 uint8_t i, j, k;
3892 uint32_t temp_reg;
3893 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3894
3895 for (i = 0, j = table->last; i < table->last; i++) {
3896 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3897 "Invalid VramInfo table.", return -1);
3898 switch (table->mc_reg_address[i].s1) {
3899 /*
3900 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3901 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3902 */
3903 case mmMC_SEQ_MISC1:
3904 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3905 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3906 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3907 for (k = 0; k < table->num_entries; k++) {
3908 table->mc_reg_table_entry[k].mc_data[j] =
3909 ((temp_reg & 0xffff0000)) |
3910 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3911 }
3912 j++;
3913 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3914 "Invalid VramInfo table.", return -1);
3915
3916 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3917 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3918 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3919 for (k = 0; k < table->num_entries; k++) {
3920 table->mc_reg_table_entry[k].mc_data[j] =
3921 (temp_reg & 0xffff0000) |
3922 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3923
3924 if (!data->is_memory_GDDR5) {
3925 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3926 }
3927 }
3928 j++;
3929 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3930 "Invalid VramInfo table.", return -1);
3931
3932 if (!data->is_memory_GDDR5) {
3933 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3934 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3935 for (k = 0; k < table->num_entries; k++) {
3936 table->mc_reg_table_entry[k].mc_data[j] =
3937 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3938 }
3939 j++;
3940 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3941 "Invalid VramInfo table.", return -1);
3942 }
3943
3944 break;
3945
3946 case mmMC_SEQ_RESERVE_M:
3947 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3948 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3949 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3950 for (k = 0; k < table->num_entries; k++) {
3951 table->mc_reg_table_entry[k].mc_data[j] =
3952 (temp_reg & 0xffff0000) |
3953 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3954 }
3955 j++;
3956 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3957 "Invalid VramInfo table.", return -1);
3958 break;
3959
3960 default:
3961 break;
3962 }
3963
3964 }
3965
3966 table->last = j;
3967
3968 return 0;
3969 }
3970
3971 int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
3972 {
3973 uint8_t i, j;
3974 for (i = 0; i < table->last; i++) {
3975 for (j = 1; j < table->num_entries; j++) {
3976 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3977 table->mc_reg_table_entry[j].mc_data[i]) {
3978 table->validflag |= (1<<i);
3979 break;
3980 }
3981 }
3982 }
3983
3984 return 0;
3985 }
3986
3987 int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3988 {
3989 int result;
3990 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3991 pp_atomctrl_mc_reg_table *table;
3992 phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
3993 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
3994
3995 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
3996
3997 if (NULL == table)
3998 return -ENOMEM;
3999
4000 /* Program additional LP registers that are no longer programmed by VBIOS */
4001 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4002 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4003 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4004 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4005 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4006 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4007 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4008 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4009 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4010 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4011 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4012 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4013 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4014 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4015 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4016 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4017 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4018 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4019 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4020 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4021
4022 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4023
4024 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4025
4026 if (0 == result)
4027 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4028
4029 if (0 == result) {
4030 tonga_set_s0_mc_reg_index(ni_table);
4031 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4032 }
4033
4034 if (0 == result)
4035 tonga_set_valid_flag(ni_table);
4036
4037 kfree(table);
4038 return result;
4039 }
4040
4041 /*
4042 * Copy one arb setting to another and then switch the active set.
4043 * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4044 */
4045 int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4046 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4047 {
4048 uint32_t mc_arb_dram_timing;
4049 uint32_t mc_arb_dram_timing2;
4050 uint32_t burst_time;
4051 uint32_t mc_cg_config;
4052
4053 switch (arbFreqSrc) {
4054 case MC_CG_ARB_FREQ_F0:
4055 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4056 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4057 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4058 break;
4059
4060 case MC_CG_ARB_FREQ_F1:
4061 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4062 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4063 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4064 break;
4065
4066 default:
4067 return -1;
4068 }
4069
4070 switch (arbFreqDest) {
4071 case MC_CG_ARB_FREQ_F0:
4072 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4073 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4074 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4075 break;
4076
4077 case MC_CG_ARB_FREQ_F1:
4078 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4079 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4080 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4081 break;
4082
4083 default:
4084 return -1;
4085 }
4086
4087 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4088 mc_cg_config |= 0x0000000F;
4089 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4090 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4091
4092 return 0;
4093 }
4094
4095 /**
4096 * Initial switch from ARB F0->F1
4097 *
4098 * @param hwmgr the address of the powerplay hardware manager.
4099 * @return always 0
4100 * This function is to be called from the SetPowerState table.
4101 */
4102 int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4103 {
4104 return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4105 }
4106
4107 /**
4108 * Initialize the ARB DRAM timing table's index field.
4109 *
4110 * @param hwmgr the address of the powerplay hardware manager.
4111 * @return always 0
4112 */
4113 int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4114 {
4115 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4116 uint32_t tmp;
4117 int result;
4118
4119 /*
4120 * This is a read-modify-write on the first byte of the ARB table.
4121 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4122 * This solution is ugly, but we never write the whole table only individual fields in it.
4123 * In reality this field should not be in that structure but in a soft register.
4124 */
4125 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4126 data->arb_table_start, &tmp, data->sram_end);
4127
4128 if (0 != result)
4129 return result;
4130
4131 tmp &= 0x00FFFFFF;
4132 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4133
4134 return tonga_write_smc_sram_dword(hwmgr->smumgr,
4135 data->arb_table_start, tmp, data->sram_end);
4136 }
4137
4138 int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4139 {
4140 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4141
4142 uint32_t i, j;
4143
4144 for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4145 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4146 PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4147 "Index of mc_reg_table->address[] array out of boundary", return -1);
4148 mc_reg_table->address[i].s0 =
4149 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4150 mc_reg_table->address[i].s1 =
4151 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4152 i++;
4153 }
4154 }
4155
4156 mc_reg_table->last = (uint8_t)i;
4157
4158 return 0;
4159 }
4160
4161 /*convert register values from driver to SMC format */
4162 void tonga_convert_mc_registers(
4163 const phw_tonga_mc_reg_entry * pEntry,
4164 SMU72_Discrete_MCRegisterSet *pData,
4165 uint32_t numEntries, uint32_t validflag)
4166 {
4167 uint32_t i, j;
4168
4169 for (i = 0, j = 0; j < numEntries; j++) {
4170 if (validflag & 1<<j) {
4171 pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4172 i++;
4173 }
4174 }
4175 }
4176
4177 /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4178 int tonga_convert_mc_reg_table_entry_to_smc(
4179 struct pp_hwmgr *hwmgr,
4180 const uint32_t memory_clock,
4181 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4182 )
4183 {
4184 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4185 uint32_t i = 0;
4186
4187 for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4188 if (memory_clock <=
4189 data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4190 break;
4191 }
4192 }
4193
4194 if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4195 --i;
4196
4197 tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4198 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4199
4200 return 0;
4201 }
4202
4203 int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4204 SMU72_Discrete_MCRegisters *mc_reg_table)
4205 {
4206 int result = 0;
4207 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4208 int res;
4209 uint32_t i;
4210
4211 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4212 res = tonga_convert_mc_reg_table_entry_to_smc(
4213 hwmgr,
4214 data->dpm_table.mclk_table.dpm_levels[i].value,
4215 &mc_reg_table->data[i]
4216 );
4217
4218 if (0 != res)
4219 result = res;
4220 }
4221
4222 return result;
4223 }
4224
4225 int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4226 {
4227 int result;
4228 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4229
4230 memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4231 result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4232 PP_ASSERT_WITH_CODE(0 == result,
4233 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4234
4235 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4236 PP_ASSERT_WITH_CODE(0 == result,
4237 "Failed to initialize MCRegTable for driver state!", return result;);
4238
4239 return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4240 (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4241 }
4242
4243 /**
4244 * Programs static screed detection parameters
4245 *
4246 * @param hwmgr the address of the powerplay hardware manager.
4247 * @return always 0
4248 */
4249 int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4250 {
4251 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4252
4253 /* Set static screen threshold unit*/
4254 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4255 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4256 data->static_screen_threshold_unit);
4257 /* Set static screen threshold*/
4258 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4259 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4260 data->static_screen_threshold);
4261
4262 return 0;
4263 }
4264
4265 /**
4266 * Setup display gap for glitch free memory clock switching.
4267 *
4268 * @param hwmgr the address of the powerplay hardware manager.
4269 * @return always 0
4270 */
4271 int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4272 {
4273 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4274 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4275
4276 display_gap = PHM_SET_FIELD(display_gap,
4277 CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4278
4279 display_gap = PHM_SET_FIELD(display_gap,
4280 CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4281
4282 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4283 ixCG_DISPLAY_GAP_CNTL, display_gap);
4284
4285 return 0;
4286 }
4287
4288 /**
4289 * Programs activity state transition voting clients
4290 *
4291 * @param hwmgr the address of the powerplay hardware manager.
4292 * @return always 0
4293 */
4294 int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4295 {
4296 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4297
4298 /* Clear reset for voting clients before enabling DPM */
4299 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4300 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4301 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4302 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4303
4304 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4305 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4306 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4307 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4308 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4309 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4310 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4311 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4312 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4313 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4314 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4315 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4316 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4317 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4318 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4319 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4320
4321 return 0;
4322 }
4323
4324
4325 int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4326 {
4327 int tmp_result, result = 0;
4328
4329 tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4330
4331 if (cf_tonga_voltage_control(hwmgr)) {
4332 tmp_result = tonga_enable_voltage_control(hwmgr);
4333 PP_ASSERT_WITH_CODE((0 == tmp_result),
4334 "Failed to enable voltage control!", result = tmp_result);
4335
4336 tmp_result = tonga_construct_voltage_tables(hwmgr);
4337 PP_ASSERT_WITH_CODE((0 == tmp_result),
4338 "Failed to contruct voltage tables!", result = tmp_result);
4339 }
4340
4341 tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4342 PP_ASSERT_WITH_CODE((0 == tmp_result),
4343 "Failed to initialize MC reg table!", result = tmp_result);
4344
4345 tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4346 PP_ASSERT_WITH_CODE((0 == tmp_result),
4347 "Failed to program static screen threshold parameters!", result = tmp_result);
4348
4349 tmp_result = tonga_enable_display_gap(hwmgr);
4350 PP_ASSERT_WITH_CODE((0 == tmp_result),
4351 "Failed to enable display gap!", result = tmp_result);
4352
4353 tmp_result = tonga_program_voting_clients(hwmgr);
4354 PP_ASSERT_WITH_CODE((0 == tmp_result),
4355 "Failed to program voting clients!", result = tmp_result);
4356
4357 tmp_result = tonga_process_firmware_header(hwmgr);
4358 PP_ASSERT_WITH_CODE((0 == tmp_result),
4359 "Failed to process firmware header!", result = tmp_result);
4360
4361 tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4362 PP_ASSERT_WITH_CODE((0 == tmp_result),
4363 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4364
4365 tmp_result = tonga_init_smc_table(hwmgr);
4366 PP_ASSERT_WITH_CODE((0 == tmp_result),
4367 "Failed to initialize SMC table!", result = tmp_result);
4368
4369 tmp_result = tonga_init_arb_table_index(hwmgr);
4370 PP_ASSERT_WITH_CODE((0 == tmp_result),
4371 "Failed to initialize ARB table index!", result = tmp_result);
4372
4373 tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4374 PP_ASSERT_WITH_CODE((0 == tmp_result),
4375 "Failed to populate initialize MC Reg table!", result = tmp_result);
4376
4377 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4378 PP_ASSERT_WITH_CODE((0 == tmp_result),
4379 "Failed to notify no display!", result = tmp_result);
4380
4381 /* enable SCLK control */
4382 tmp_result = tonga_enable_sclk_control(hwmgr);
4383 PP_ASSERT_WITH_CODE((0 == tmp_result),
4384 "Failed to enable SCLK control!", result = tmp_result);
4385
4386 /* enable DPM */
4387 tmp_result = tonga_start_dpm(hwmgr);
4388 PP_ASSERT_WITH_CODE((0 == tmp_result),
4389 "Failed to start DPM!", result = tmp_result);
4390
4391 return result;
4392 }
4393
4394 int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4395 {
4396 int tmp_result, result = 0;
4397
4398 tmp_result = tonga_check_for_dpm_running(hwmgr);
4399 PP_ASSERT_WITH_CODE((0 == tmp_result),
4400 "SMC is still running!", return 0);
4401
4402 tmp_result = tonga_stop_dpm(hwmgr);
4403 PP_ASSERT_WITH_CODE((0 == tmp_result),
4404 "Failed to stop DPM!", result = tmp_result);
4405
4406 tmp_result = tonga_reset_to_default(hwmgr);
4407 PP_ASSERT_WITH_CODE((0 == tmp_result),
4408 "Failed to reset to default!", result = tmp_result);
4409
4410 return result;
4411 }
4412
4413 int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4414 {
4415 int result;
4416
4417 result = tonga_set_boot_state(hwmgr);
4418 if (0 != result)
4419 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4420
4421 return result;
4422 }
4423
4424 int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4425 {
4426 return phm_hwmgr_backend_fini(hwmgr);
4427 }
4428
4429 /**
4430 * Initializes the Volcanic Islands Hardware Manager
4431 *
4432 * @param hwmgr the address of the powerplay hardware manager.
4433 * @return 1 if success; otherwise appropriate error code.
4434 */
4435 int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4436 {
4437 int result = 0;
4438 SMU72_Discrete_DpmTable *table = NULL;
4439 tonga_hwmgr *data;
4440 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4441 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4442 phw_tonga_ulv_parm *ulv;
4443 struct cgs_system_info sys_info = {0};
4444
4445 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4446 "Invalid Parameter!", return -1;);
4447
4448 data = kzalloc(sizeof(struct tonga_hwmgr), GFP_KERNEL);
4449 if (data == NULL)
4450 return -ENOMEM;
4451
4452 hwmgr->backend = data;
4453
4454 data->dll_defaule_on = false;
4455 data->sram_end = SMC_RAM_END;
4456
4457 data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4458 data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4459 data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4460 data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4461 data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4462 data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4463 data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4464 data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4465
4466 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4467 data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4468 data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4469
4470 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4471 PHM_PlatformCaps_DisableVoltageIsland);
4472
4473 data->sclk_dpm_key_disabled = 0;
4474 data->mclk_dpm_key_disabled = 0;
4475 data->pcie_dpm_key_disabled = 0;
4476 data->pcc_monitor_enabled = 0;
4477
4478 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4479 PHM_PlatformCaps_UnTabledHardwareInterface);
4480
4481 data->gpio_debug = 0;
4482 data->engine_clock_data = 0;
4483 data->memory_clock_data = 0;
4484 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4485 PHM_PlatformCaps_DynamicPatchPowerState);
4486
4487 /* need to set voltage control types before EVV patching*/
4488 data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4489 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4490 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4491 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4492 data->force_pcie_gen = PP_PCIEGenInvalid;
4493
4494 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4495 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4496 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4497 }
4498
4499 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4500 PHM_PlatformCaps_ControlVDDGFX)) {
4501 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4502 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4503 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4504 }
4505 }
4506
4507 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4508 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4509 PHM_PlatformCaps_ControlVDDGFX);
4510 }
4511
4512 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4513 PHM_PlatformCaps_EnableMVDDControl)) {
4514 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4515 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4516 data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4517 }
4518 }
4519
4520 if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4521 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4522 PHM_PlatformCaps_EnableMVDDControl);
4523 }
4524
4525 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4526 PHM_PlatformCaps_ControlVDDCI)) {
4527 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4528 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4529 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4530 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4531 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4532 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4533 }
4534
4535 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4536 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4537 PHM_PlatformCaps_ControlVDDCI);
4538
4539 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4540 PHM_PlatformCaps_TablelessHardwareInterface);
4541
4542 if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4543 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4544 PHM_PlatformCaps_ClockStretcher);
4545
4546 /* Initializes DPM default values*/
4547 tonga_initialize_dpm_defaults(hwmgr);
4548
4549 /* Get leakage voltage based on leakage ID.*/
4550 PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4551 "Get EVV Voltage Failed. Abort Driver loading!", return -1);
4552
4553 tonga_complete_dependency_tables(hwmgr);
4554
4555 /* Parse pptable data read from VBIOS*/
4556 tonga_set_private_var_based_on_pptale(hwmgr);
4557
4558 /* ULV Support*/
4559 ulv = &(data->ulv);
4560 ulv->ulv_supported = false;
4561
4562 /* Initalize Dynamic State Adjustment Rule Settings*/
4563 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
4564 if (result)
4565 printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
4566 data->uvd_enabled = false;
4567
4568 table = &(data->smc_state_table);
4569
4570 /*
4571 * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4572 * Peak Current Control feature is enabled and we should program PCC HW register
4573 */
4574 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4575 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4576 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4577
4578 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4579 case 0:
4580 temp_reg = PHM_SET_FIELD(temp_reg,
4581 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4582 break;
4583 case 1:
4584 temp_reg = PHM_SET_FIELD(temp_reg,
4585 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4586 break;
4587 case 2:
4588 temp_reg = PHM_SET_FIELD(temp_reg,
4589 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4590 break;
4591 case 3:
4592 temp_reg = PHM_SET_FIELD(temp_reg,
4593 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4594 break;
4595 case 4:
4596 temp_reg = PHM_SET_FIELD(temp_reg,
4597 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4598 break;
4599 default:
4600 printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4601 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4602 break;
4603 }
4604 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4605 ixCNB_PWRMGT_CNTL, temp_reg);
4606 }
4607
4608 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4609 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4610 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4611 PHM_PlatformCaps_SMU7);
4612
4613 data->vddc_phase_shed_control = false;
4614
4615 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4616 PHM_PlatformCaps_UVDPowerGating);
4617 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4618 PHM_PlatformCaps_VCEPowerGating);
4619 sys_info.size = sizeof(struct cgs_system_info);
4620 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4621 result = cgs_query_system_info(hwmgr->device, &sys_info);
4622 if (!result) {
4623 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4624 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4625 PHM_PlatformCaps_UVDPowerGating);
4626 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4627 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4628 PHM_PlatformCaps_VCEPowerGating);
4629 }
4630
4631 if (0 == result) {
4632 data->is_tlu_enabled = false;
4633 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4634 TONGA_MAX_HARDWARE_POWERLEVELS;
4635 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4636 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
4637
4638 sys_info.size = sizeof(struct cgs_system_info);
4639 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
4640 result = cgs_query_system_info(hwmgr->device, &sys_info);
4641 if (result)
4642 data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
4643 else
4644 data->pcie_gen_cap = (uint32_t)sys_info.value;
4645 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
4646 data->pcie_spc_cap = 20;
4647 sys_info.size = sizeof(struct cgs_system_info);
4648 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
4649 result = cgs_query_system_info(hwmgr->device, &sys_info);
4650 if (result)
4651 data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
4652 else
4653 data->pcie_lane_cap = (uint32_t)sys_info.value;
4654 } else {
4655 /* Ignore return value in here, we are cleaning up a mess. */
4656 tonga_hwmgr_backend_fini(hwmgr);
4657 }
4658
4659 return result;
4660 }
4661
4662 static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4663 enum amd_dpm_forced_level level)
4664 {
4665 int ret = 0;
4666
4667 switch (level) {
4668 case AMD_DPM_FORCED_LEVEL_HIGH:
4669 ret = tonga_force_dpm_highest(hwmgr);
4670 if (ret)
4671 return ret;
4672 break;
4673 case AMD_DPM_FORCED_LEVEL_LOW:
4674 ret = tonga_force_dpm_lowest(hwmgr);
4675 if (ret)
4676 return ret;
4677 break;
4678 case AMD_DPM_FORCED_LEVEL_AUTO:
4679 ret = tonga_unforce_dpm_levels(hwmgr);
4680 if (ret)
4681 return ret;
4682 break;
4683 default:
4684 break;
4685 }
4686
4687 hwmgr->dpm_level = level;
4688 return ret;
4689 }
4690
4691 static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4692 struct pp_power_state *prequest_ps,
4693 const struct pp_power_state *pcurrent_ps)
4694 {
4695 struct tonga_power_state *tonga_ps =
4696 cast_phw_tonga_power_state(&prequest_ps->hardware);
4697
4698 uint32_t sclk;
4699 uint32_t mclk;
4700 struct PP_Clocks minimum_clocks = {0};
4701 bool disable_mclk_switching;
4702 bool disable_mclk_switching_for_frame_lock;
4703 struct cgs_display_info info = {0};
4704 const struct phm_clock_and_voltage_limits *max_limits;
4705 uint32_t i;
4706 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4707 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4708
4709 int32_t count;
4710 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4711
4712 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4713
4714 PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4715 "VI should always have 2 performance levels",
4716 );
4717
4718 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4719 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4720 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4721
4722 if (PP_PowerSource_DC == hwmgr->power_source) {
4723 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4724 if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4725 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4726 if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4727 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4728 }
4729 }
4730
4731 tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4732 tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4733
4734 tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4735
4736 cgs_get_active_displays_info(hwmgr->device, &info);
4737
4738 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4739
4740 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4741
4742 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4743
4744 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4745 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4746
4747 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4748 if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4749 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4750 break;
4751 }
4752 }
4753
4754 if (count < 0)
4755 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4756
4757 stable_pstate_mclk = max_limits->mclk;
4758
4759 minimum_clocks.engineClock = stable_pstate_sclk;
4760 minimum_clocks.memoryClock = stable_pstate_mclk;
4761 }
4762
4763 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4764 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4765
4766 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4767 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4768
4769 tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4770
4771 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4772 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4773 "Overdrive sclk exceeds limit",
4774 hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4775
4776 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4777 tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4778 }
4779
4780 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4781 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4782 "Overdrive mclk exceeds limit",
4783 hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4784
4785 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4786 tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4787 }
4788
4789 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4790 hwmgr->platform_descriptor.platformCaps,
4791 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4792
4793 disable_mclk_switching = (1 < info.display_count) ||
4794 disable_mclk_switching_for_frame_lock;
4795
4796 sclk = tonga_ps->performance_levels[0].engine_clock;
4797 mclk = tonga_ps->performance_levels[0].memory_clock;
4798
4799 if (disable_mclk_switching)
4800 mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4801
4802 if (sclk < minimum_clocks.engineClock)
4803 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4804
4805 if (mclk < minimum_clocks.memoryClock)
4806 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4807
4808 tonga_ps->performance_levels[0].engine_clock = sclk;
4809 tonga_ps->performance_levels[0].memory_clock = mclk;
4810
4811 tonga_ps->performance_levels[1].engine_clock =
4812 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4813 tonga_ps->performance_levels[1].engine_clock :
4814 tonga_ps->performance_levels[0].engine_clock;
4815
4816 if (disable_mclk_switching) {
4817 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4818 mclk = tonga_ps->performance_levels[1].memory_clock;
4819
4820 tonga_ps->performance_levels[0].memory_clock = mclk;
4821 tonga_ps->performance_levels[1].memory_clock = mclk;
4822 } else {
4823 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4824 tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4825 }
4826
4827 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4828 for (i=0; i < tonga_ps->performance_level_count; i++) {
4829 tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4830 tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4831 tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4832 tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4833 }
4834 }
4835
4836 return 0;
4837 }
4838
4839 int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4840 {
4841 return sizeof(struct tonga_power_state);
4842 }
4843
4844 static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4845 {
4846 struct pp_power_state *ps;
4847 struct tonga_power_state *tonga_ps;
4848
4849 if (hwmgr == NULL)
4850 return -EINVAL;
4851
4852 ps = hwmgr->request_ps;
4853
4854 if (ps == NULL)
4855 return -EINVAL;
4856
4857 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4858
4859 if (low)
4860 return tonga_ps->performance_levels[0].memory_clock;
4861 else
4862 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4863 }
4864
4865 static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4866 {
4867 struct pp_power_state *ps;
4868 struct tonga_power_state *tonga_ps;
4869
4870 if (hwmgr == NULL)
4871 return -EINVAL;
4872
4873 ps = hwmgr->request_ps;
4874
4875 if (ps == NULL)
4876 return -EINVAL;
4877
4878 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4879
4880 if (low)
4881 return tonga_ps->performance_levels[0].engine_clock;
4882 else
4883 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4884 }
4885
4886 static uint16_t tonga_get_current_pcie_speed(
4887 struct pp_hwmgr *hwmgr)
4888 {
4889 uint32_t speed_cntl = 0;
4890
4891 speed_cntl = cgs_read_ind_register(hwmgr->device,
4892 CGS_IND_REG__PCIE,
4893 ixPCIE_LC_SPEED_CNTL);
4894 return((uint16_t)PHM_GET_FIELD(speed_cntl,
4895 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4896 }
4897
4898 static int tonga_get_current_pcie_lane_number(
4899 struct pp_hwmgr *hwmgr)
4900 {
4901 uint32_t link_width;
4902
4903 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4904 CGS_IND_REG__PCIE,
4905 PCIE_LC_LINK_WIDTH_CNTL,
4906 LC_LINK_WIDTH_RD);
4907
4908 PP_ASSERT_WITH_CODE((7 >= link_width),
4909 "Invalid PCIe lane width!", return 0);
4910
4911 return decode_pcie_lane_width(link_width);
4912 }
4913
4914 static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4915 struct pp_hw_power_state *hw_ps)
4916 {
4917 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4918 struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4919 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4920 uint16_t size;
4921 uint8_t frev, crev;
4922 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4923
4924 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4925 * We assume here that fw_info is unchanged if this call fails.
4926 */
4927 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4928 hwmgr->device, index,
4929 &size, &frev, &crev);
4930 if (!fw_info)
4931 /* During a test, there is no firmware info table. */
4932 return 0;
4933
4934 /* Patch the state. */
4935 data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock);
4936 data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4937 data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4938 data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4939 data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4940 data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4941 data->vbios_boot_state.pcie_lane_bootup_value =
4942 (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4943
4944 /* set boot power state */
4945 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4946 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4947 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4948 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4949
4950 return 0;
4951 }
4952
4953 static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4954 void *state, struct pp_power_state *power_state,
4955 void *pp_table, uint32_t classification_flag)
4956 {
4957 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4958
4959 struct tonga_power_state *tonga_ps =
4960 (struct tonga_power_state *)(&(power_state->hardware));
4961
4962 struct tonga_performance_level *performance_level;
4963
4964 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4965
4966 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4967 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4968
4969 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4970 (ATOM_Tonga_SCLK_Dependency_Table *)
4971 (((unsigned long)powerplay_table) +
4972 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4973
4974 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4975 (ATOM_Tonga_MCLK_Dependency_Table *)
4976 (((unsigned long)powerplay_table) +
4977 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
4978
4979 /* The following fields are not initialized here: id orderedList allStatesList */
4980 power_state->classification.ui_label =
4981 (le16_to_cpu(state_entry->usClassification) &
4982 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
4983 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
4984 power_state->classification.flags = classification_flag;
4985 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
4986
4987 power_state->classification.temporary_state = false;
4988 power_state->classification.to_be_deleted = false;
4989
4990 power_state->validation.disallowOnDC =
4991 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
4992
4993 power_state->pcie.lanes = 0;
4994
4995 power_state->display.disableFrameModulation = false;
4996 power_state->display.limitRefreshrate = false;
4997 power_state->display.enableVariBright =
4998 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
4999
5000 power_state->validation.supportedPowerLevels = 0;
5001 power_state->uvd_clocks.VCLK = 0;
5002 power_state->uvd_clocks.DCLK = 0;
5003 power_state->temperatures.min = 0;
5004 power_state->temperatures.max = 0;
5005
5006 performance_level = &(tonga_ps->performance_levels
5007 [tonga_ps->performance_level_count++]);
5008
5009 PP_ASSERT_WITH_CODE(
5010 (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5011 "Performance levels exceeds SMC limit!",
5012 return -1);
5013
5014 PP_ASSERT_WITH_CODE(
5015 (tonga_ps->performance_level_count <=
5016 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5017 "Performance levels exceeds Driver limit!",
5018 return -1);
5019
5020 /* Performance levels are arranged from low to high. */
5021 performance_level->memory_clock =
5022 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5023
5024 performance_level->engine_clock =
5025 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5026
5027 performance_level->pcie_gen = get_pcie_gen_support(
5028 data->pcie_gen_cap,
5029 state_entry->ucPCIEGenLow);
5030
5031 performance_level->pcie_lane = get_pcie_lane_support(
5032 data->pcie_lane_cap,
5033 state_entry->ucPCIELaneHigh);
5034
5035 performance_level =
5036 &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5037
5038 performance_level->memory_clock =
5039 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5040
5041 performance_level->engine_clock =
5042 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5043
5044 performance_level->pcie_gen = get_pcie_gen_support(
5045 data->pcie_gen_cap,
5046 state_entry->ucPCIEGenHigh);
5047
5048 performance_level->pcie_lane = get_pcie_lane_support(
5049 data->pcie_lane_cap,
5050 state_entry->ucPCIELaneHigh);
5051
5052 return 0;
5053 }
5054
5055 static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5056 unsigned long entry_index, struct pp_power_state *ps)
5057 {
5058 int result;
5059 struct tonga_power_state *tonga_ps;
5060 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5061
5062 struct phm_ppt_v1_information *table_info =
5063 (struct phm_ppt_v1_information *)(hwmgr->pptable);
5064
5065 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5066 table_info->vdd_dep_on_mclk;
5067
5068 ps->hardware.magic = PhwTonga_Magic;
5069
5070 tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5071
5072 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5073 tonga_get_pp_table_entry_callback_func);
5074
5075 /* This is the earliest time we have all the dependency table and the VBIOS boot state
5076 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5077 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5078 */
5079 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5080 if (dep_mclk_table->entries[0].clk !=
5081 data->vbios_boot_state.mclk_bootup_value)
5082 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5083 "does not match VBIOS boot MCLK level");
5084 if (dep_mclk_table->entries[0].vddci !=
5085 data->vbios_boot_state.vddci_bootup_value)
5086 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5087 "does not match VBIOS boot VDDCI level");
5088 }
5089
5090 /* set DC compatible flag if this state supports DC */
5091 if (!ps->validation.disallowOnDC)
5092 tonga_ps->dc_compatible = true;
5093
5094 if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5095 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5096 else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5097 if (data->bacos.best_match == 0xffff) {
5098 /* For V.I. use boot state as base BACO state */
5099 data->bacos.best_match = PP_StateClassificationFlag_Boot;
5100 data->bacos.performance_level = tonga_ps->performance_levels[0];
5101 }
5102 }
5103
5104 tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5105 tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5106
5107 if (!result) {
5108 uint32_t i;
5109
5110 switch (ps->classification.ui_label) {
5111 case PP_StateUILabel_Performance:
5112 data->use_pcie_performance_levels = true;
5113
5114 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5115 if (data->pcie_gen_performance.max <
5116 tonga_ps->performance_levels[i].pcie_gen)
5117 data->pcie_gen_performance.max =
5118 tonga_ps->performance_levels[i].pcie_gen;
5119
5120 if (data->pcie_gen_performance.min >
5121 tonga_ps->performance_levels[i].pcie_gen)
5122 data->pcie_gen_performance.min =
5123 tonga_ps->performance_levels[i].pcie_gen;
5124
5125 if (data->pcie_lane_performance.max <
5126 tonga_ps->performance_levels[i].pcie_lane)
5127 data->pcie_lane_performance.max =
5128 tonga_ps->performance_levels[i].pcie_lane;
5129
5130 if (data->pcie_lane_performance.min >
5131 tonga_ps->performance_levels[i].pcie_lane)
5132 data->pcie_lane_performance.min =
5133 tonga_ps->performance_levels[i].pcie_lane;
5134 }
5135 break;
5136 case PP_StateUILabel_Battery:
5137 data->use_pcie_power_saving_levels = true;
5138
5139 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5140 if (data->pcie_gen_power_saving.max <
5141 tonga_ps->performance_levels[i].pcie_gen)
5142 data->pcie_gen_power_saving.max =
5143 tonga_ps->performance_levels[i].pcie_gen;
5144
5145 if (data->pcie_gen_power_saving.min >
5146 tonga_ps->performance_levels[i].pcie_gen)
5147 data->pcie_gen_power_saving.min =
5148 tonga_ps->performance_levels[i].pcie_gen;
5149
5150 if (data->pcie_lane_power_saving.max <
5151 tonga_ps->performance_levels[i].pcie_lane)
5152 data->pcie_lane_power_saving.max =
5153 tonga_ps->performance_levels[i].pcie_lane;
5154
5155 if (data->pcie_lane_power_saving.min >
5156 tonga_ps->performance_levels[i].pcie_lane)
5157 data->pcie_lane_power_saving.min =
5158 tonga_ps->performance_levels[i].pcie_lane;
5159 }
5160 break;
5161 default:
5162 break;
5163 }
5164 }
5165 return 0;
5166 }
5167
5168 static void
5169 tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5170 {
5171 uint32_t sclk, mclk, activity_percent;
5172 uint32_t offset;
5173 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5174
5175 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5176
5177 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5178
5179 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5180
5181 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5182 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
5183
5184 offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
5185 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5186 activity_percent += 0x80;
5187 activity_percent >>= 8;
5188
5189 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
5190
5191 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
5192
5193 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
5194 }
5195
5196 static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5197 {
5198 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5199 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5200 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5201 struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5202 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5203 struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5204 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5205 struct PP_Clocks min_clocks = {0};
5206 uint32_t i;
5207 struct cgs_display_info info = {0};
5208
5209 data->need_update_smu7_dpm_table = 0;
5210
5211 for (i = 0; i < psclk_table->count; i++) {
5212 if (sclk == psclk_table->dpm_levels[i].value)
5213 break;
5214 }
5215
5216 if (i >= psclk_table->count)
5217 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5218 else {
5219 /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5220 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5221 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5222 }
5223
5224 for (i=0; i < pmclk_table->count; i++) {
5225 if (mclk == pmclk_table->dpm_levels[i].value)
5226 break;
5227 }
5228
5229 if (i >= pmclk_table->count)
5230 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5231
5232 cgs_get_active_displays_info(hwmgr->device, &info);
5233
5234 if (data->display_timing.num_existing_displays != info.display_count)
5235 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5236
5237 return 0;
5238 }
5239
5240 static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5241 {
5242 uint32_t i;
5243 uint32_t sclk, max_sclk = 0;
5244 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5245 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5246
5247 for (i = 0; i < hw_ps->performance_level_count; i++) {
5248 sclk = hw_ps->performance_levels[i].engine_clock;
5249 if (max_sclk < sclk)
5250 max_sclk = sclk;
5251 }
5252
5253 for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5254 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5255 return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5256 pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5257 pdpm_table->pcie_speed_table.dpm_levels[i].value);
5258 }
5259
5260 return 0;
5261 }
5262
5263 static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5264 {
5265 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5266 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5267 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5268 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5269
5270 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5271 uint16_t current_link_speed;
5272
5273 if (data->force_pcie_gen == PP_PCIEGenInvalid)
5274 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5275 else
5276 current_link_speed = data->force_pcie_gen;
5277
5278 data->force_pcie_gen = PP_PCIEGenInvalid;
5279 data->pspp_notify_required = false;
5280 if (target_link_speed > current_link_speed) {
5281 switch(target_link_speed) {
5282 case PP_PCIEGen3:
5283 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5284 break;
5285 data->force_pcie_gen = PP_PCIEGen2;
5286 if (current_link_speed == PP_PCIEGen2)
5287 break;
5288 case PP_PCIEGen2:
5289 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5290 break;
5291 default:
5292 data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5293 break;
5294 }
5295 } else {
5296 if (target_link_speed < current_link_speed)
5297 data->pspp_notify_required = true;
5298 }
5299
5300 return 0;
5301 }
5302
5303 static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5304 {
5305 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5306
5307 if (0 == data->need_update_smu7_dpm_table)
5308 return 0;
5309
5310 if ((0 == data->sclk_dpm_key_disabled) &&
5311 (data->need_update_smu7_dpm_table &
5312 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5313 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5314 "Trying to freeze SCLK DPM when DPM is disabled",
5315 );
5316 PP_ASSERT_WITH_CODE(
5317 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5318 PPSMC_MSG_SCLKDPM_FreezeLevel),
5319 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5320 return -1);
5321 }
5322
5323 if ((0 == data->mclk_dpm_key_disabled) &&
5324 (data->need_update_smu7_dpm_table &
5325 DPMTABLE_OD_UPDATE_MCLK)) {
5326 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5327 "Trying to freeze MCLK DPM when DPM is disabled",
5328 );
5329 PP_ASSERT_WITH_CODE(
5330 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5331 PPSMC_MSG_MCLKDPM_FreezeLevel),
5332 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5333 return -1);
5334 }
5335
5336 return 0;
5337 }
5338
5339 static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5340 {
5341 int result = 0;
5342
5343 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5344 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5345 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5346 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5347 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5348 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5349
5350 struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5351 uint32_t dpm_count, clock_percent;
5352 uint32_t i;
5353
5354 if (0 == data->need_update_smu7_dpm_table)
5355 return 0;
5356
5357 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5358 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5359
5360 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5361 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5362 /* Need to do calculation based on the golden DPM table
5363 * as the Heatmap GPU Clock axis is also based on the default values
5364 */
5365 PP_ASSERT_WITH_CODE(
5366 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5367 "Divide by 0!",
5368 return -1);
5369 dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5370 for (i = dpm_count; i > 1; i--) {
5371 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5372 clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5373 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5374
5375 pdpm_table->sclk_table.dpm_levels[i].value =
5376 pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5377 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5378
5379 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5380 clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5381 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5382
5383 pdpm_table->sclk_table.dpm_levels[i].value =
5384 pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5385 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5386 } else
5387 pdpm_table->sclk_table.dpm_levels[i].value =
5388 pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5389 }
5390 }
5391 }
5392
5393 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5394 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5395
5396 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5397 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5398
5399 PP_ASSERT_WITH_CODE(
5400 (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5401 "Divide by 0!",
5402 return -1);
5403 dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5404 for (i = dpm_count; i > 1; i--) {
5405 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5406 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5407 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5408
5409 pdpm_table->mclk_table.dpm_levels[i].value =
5410 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5411 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5412
5413 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5414 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5415 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5416
5417 pdpm_table->mclk_table.dpm_levels[i].value =
5418 pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5419 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5420 } else
5421 pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5422 }
5423 }
5424 }
5425
5426 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5427 result = tonga_populate_all_graphic_levels(hwmgr);
5428 PP_ASSERT_WITH_CODE((0 == result),
5429 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5430 return result);
5431 }
5432
5433 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5434 /*populate MCLK dpm table to SMU7 */
5435 result = tonga_populate_all_memory_levels(hwmgr);
5436 PP_ASSERT_WITH_CODE((0 == result),
5437 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5438 return result);
5439 }
5440
5441 return result;
5442 }
5443
5444 static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5445 struct tonga_single_dpm_table * pdpm_table,
5446 uint32_t low_limit, uint32_t high_limit)
5447 {
5448 uint32_t i;
5449
5450 for (i = 0; i < pdpm_table->count; i++) {
5451 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5452 (pdpm_table->dpm_levels[i].value > high_limit))
5453 pdpm_table->dpm_levels[i].enabled = false;
5454 else
5455 pdpm_table->dpm_levels[i].enabled = true;
5456 }
5457 return 0;
5458 }
5459
5460 static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5461 {
5462 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5463 uint32_t high_limit_count;
5464
5465 PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5466 "power state did not have any performance level",
5467 return -1);
5468
5469 high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5470
5471 tonga_trim_single_dpm_states(hwmgr,
5472 &(data->dpm_table.sclk_table),
5473 hw_state->performance_levels[0].engine_clock,
5474 hw_state->performance_levels[high_limit_count].engine_clock);
5475
5476 tonga_trim_single_dpm_states(hwmgr,
5477 &(data->dpm_table.mclk_table),
5478 hw_state->performance_levels[0].memory_clock,
5479 hw_state->performance_levels[high_limit_count].memory_clock);
5480
5481 return 0;
5482 }
5483
5484 static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5485 {
5486 int result;
5487 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5488 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5489 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5490
5491 result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5492 if (0 != result)
5493 return result;
5494
5495 data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5496 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5497 data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5498 if (data->uvd_enabled)
5499 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5500
5501 data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5502
5503 return 0;
5504 }
5505
5506 int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
5507 {
5508 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5509 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5510 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5511 }
5512
5513 int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5514 {
5515 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5516 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5517 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5518 }
5519
5520 int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5521 {
5522 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5523 uint32_t mm_boot_level_offset, mm_boot_level_value;
5524 struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5525
5526 if (!bgate) {
5527 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5528 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5529 mm_boot_level_offset /= 4;
5530 mm_boot_level_offset *= 4;
5531 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5532 mm_boot_level_value &= 0x00FFFFFF;
5533 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5534 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5535
5536 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5537 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5538 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5539 PPSMC_MSG_UVDDPM_SetEnabledMask,
5540 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5541 }
5542
5543 return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5544 }
5545
5546 int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
5547 {
5548 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5549 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5550 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5551 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5552
5553 uint32_t mm_boot_level_offset, mm_boot_level_value;
5554 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5555
5556 if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
5557 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5558
5559 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5560 mm_boot_level_offset /= 4;
5561 mm_boot_level_offset *= 4;
5562 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5563 mm_boot_level_value &= 0xFF00FFFF;
5564 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5565 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5566
5567 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5568 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5569 PPSMC_MSG_VCEDPM_SetEnabledMask,
5570 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
5571
5572 tonga_enable_disable_vce_dpm(hwmgr, true);
5573 } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5574 tonga_enable_disable_vce_dpm(hwmgr, false);
5575
5576 return 0;
5577 }
5578
5579 static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5580 {
5581 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5582
5583 uint32_t address;
5584 int32_t result;
5585
5586 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5587 return 0;
5588
5589
5590 memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5591
5592 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5593
5594 if(result != 0)
5595 return result;
5596
5597
5598 address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5599
5600 return tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5601 (uint8_t *)&data->mc_reg_table.data[0],
5602 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5603 data->sram_end);
5604 }
5605
5606 static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5607 {
5608 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5609
5610 if (data->need_update_smu7_dpm_table &
5611 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5612 return tonga_program_memory_timing_parameters(hwmgr);
5613
5614 return 0;
5615 }
5616
5617 static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5618 {
5619 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5620
5621 if (0 == data->need_update_smu7_dpm_table)
5622 return 0;
5623
5624 if ((0 == data->sclk_dpm_key_disabled) &&
5625 (data->need_update_smu7_dpm_table &
5626 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5627
5628 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5629 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5630 );
5631 PP_ASSERT_WITH_CODE(
5632 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5633 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5634 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5635 return -1);
5636 }
5637
5638 if ((0 == data->mclk_dpm_key_disabled) &&
5639 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5640
5641 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5642 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5643 );
5644 PP_ASSERT_WITH_CODE(
5645 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5646 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5647 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5648 return -1);
5649 }
5650
5651 data->need_update_smu7_dpm_table = 0;
5652
5653 return 0;
5654 }
5655
5656 static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5657 {
5658 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5659 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5660 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5661 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5662 uint8_t request;
5663
5664 if (data->pspp_notify_required ||
5665 data->pcie_performance_request) {
5666 if (target_link_speed == PP_PCIEGen3)
5667 request = PCIE_PERF_REQ_GEN3;
5668 else if (target_link_speed == PP_PCIEGen2)
5669 request = PCIE_PERF_REQ_GEN2;
5670 else
5671 request = PCIE_PERF_REQ_GEN1;
5672
5673 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5674 data->pcie_performance_request = false;
5675 return 0;
5676 }
5677
5678 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5679 if (PP_PCIEGen2 == target_link_speed)
5680 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5681 else
5682 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5683 }
5684 }
5685
5686 data->pcie_performance_request = false;
5687 return 0;
5688 }
5689
5690 static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5691 {
5692 int tmp_result, result = 0;
5693
5694 tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5695 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5696
5697 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5698 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5699 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5700 }
5701
5702 tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5703 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5704
5705 tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5706 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5707
5708 tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5709 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5710
5711 tmp_result = tonga_update_vce_dpm(hwmgr, input);
5712 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5713
5714 tmp_result = tonga_update_sclk_threshold(hwmgr);
5715 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5716
5717 tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5718 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5719
5720 tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5721 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5722
5723 tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5724 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5725
5726 tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5727 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5728
5729 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5730 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5731 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5732 }
5733
5734 return result;
5735 }
5736
5737 /**
5738 * Set maximum target operating fan output PWM
5739 *
5740 * @param pHwMgr: the address of the powerplay hardware manager.
5741 * @param usMaxFanPwm: max operating fan PWM in percents
5742 * @return The response that came from the SMC.
5743 */
5744 static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5745 {
5746 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5747
5748 if (phm_is_hw_access_blocked(hwmgr))
5749 return 0;
5750
5751 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
5752 }
5753
5754 int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5755 {
5756 uint32_t num_active_displays = 0;
5757 struct cgs_display_info info = {0};
5758 info.mode_info = NULL;
5759
5760 cgs_get_active_displays_info(hwmgr->device, &info);
5761
5762 num_active_displays = info.display_count;
5763
5764 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5765 tonga_notify_smc_display_change(hwmgr, false);
5766 else
5767 tonga_notify_smc_display_change(hwmgr, true);
5768
5769 return 0;
5770 }
5771
5772 /**
5773 * Programs the display gap
5774 *
5775 * @param hwmgr the address of the powerplay hardware manager.
5776 * @return always OK
5777 */
5778 int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5779 {
5780 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5781 uint32_t num_active_displays = 0;
5782 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5783 uint32_t display_gap2;
5784 uint32_t pre_vbi_time_in_us;
5785 uint32_t frame_time_in_us;
5786 uint32_t ref_clock;
5787 uint32_t refresh_rate = 0;
5788 struct cgs_display_info info = {0};
5789 struct cgs_mode_info mode_info;
5790
5791 info.mode_info = &mode_info;
5792
5793 cgs_get_active_displays_info(hwmgr->device, &info);
5794 num_active_displays = info.display_count;
5795
5796 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5797 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5798
5799 ref_clock = mode_info.ref_clock;
5800 refresh_rate = mode_info.refresh_rate;
5801
5802 if(0 == refresh_rate)
5803 refresh_rate = 60;
5804
5805 frame_time_in_us = 1000000 / refresh_rate;
5806
5807 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5808 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5809
5810 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5811
5812 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5813
5814 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5815
5816 if (num_active_displays == 1)
5817 tonga_notify_smc_display_change(hwmgr, true);
5818
5819 return 0;
5820 }
5821
5822 int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5823 {
5824
5825 tonga_program_display_gap(hwmgr);
5826
5827 /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5828 return 0;
5829 }
5830
5831 /**
5832 * Set maximum target operating fan output RPM
5833 *
5834 * @param pHwMgr: the address of the powerplay hardware manager.
5835 * @param usMaxFanRpm: max operating fan RPM value.
5836 * @return The response that came from the SMC.
5837 */
5838 static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5839 {
5840 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5841
5842 if (phm_is_hw_access_blocked(hwmgr))
5843 return 0;
5844
5845 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
5846 }
5847
5848 uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5849 {
5850 uint32_t reference_clock;
5851 uint32_t tc;
5852 uint32_t divide;
5853
5854 ATOM_FIRMWARE_INFO *fw_info;
5855 uint16_t size;
5856 uint8_t frev, crev;
5857 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5858
5859 tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5860
5861 if (tc)
5862 return TCLK;
5863
5864 fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5865 &size, &frev, &crev);
5866
5867 if (!fw_info)
5868 return 0;
5869
5870 reference_clock = le16_to_cpu(fw_info->usReferenceClock);
5871
5872 divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5873
5874 if (0 != divide)
5875 return reference_clock / 4;
5876
5877 return reference_clock;
5878 }
5879
5880 int tonga_dpm_set_interrupt_state(void *private_data,
5881 unsigned src_id, unsigned type,
5882 int enabled)
5883 {
5884 uint32_t cg_thermal_int;
5885 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5886
5887 if (hwmgr == NULL)
5888 return -EINVAL;
5889
5890 switch (type) {
5891 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5892 if (enabled) {
5893 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5894 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5895 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5896 } else {
5897 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5898 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5899 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5900 }
5901 break;
5902
5903 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5904 if (enabled) {
5905 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5906 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5907 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5908 } else {
5909 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5910 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5911 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5912 }
5913 break;
5914 default:
5915 break;
5916 }
5917 return 0;
5918 }
5919
5920 int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5921 const void *thermal_interrupt_info)
5922 {
5923 int result;
5924 const struct pp_interrupt_registration_info *info =
5925 (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5926
5927 if (info == NULL)
5928 return -EINVAL;
5929
5930 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5931 tonga_dpm_set_interrupt_state,
5932 info->call_back, info->context);
5933
5934 if (result)
5935 return -EINVAL;
5936
5937 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5938 tonga_dpm_set_interrupt_state,
5939 info->call_back, info->context);
5940
5941 if (result)
5942 return -EINVAL;
5943
5944 return 0;
5945 }
5946
5947 bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5948 {
5949 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5950 bool is_update_required = false;
5951 struct cgs_display_info info = {0,0,NULL};
5952
5953 cgs_get_active_displays_info(hwmgr->device, &info);
5954
5955 if (data->display_timing.num_existing_displays != info.display_count)
5956 is_update_required = true;
5957 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5958 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5959 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5960 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5961 is_update_required = true;
5962 */
5963 return is_update_required;
5964 }
5965
5966 static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5967 const struct tonga_performance_level *pl2)
5968 {
5969 return ((pl1->memory_clock == pl2->memory_clock) &&
5970 (pl1->engine_clock == pl2->engine_clock) &&
5971 (pl1->pcie_gen == pl2->pcie_gen) &&
5972 (pl1->pcie_lane == pl2->pcie_lane));
5973 }
5974
5975 int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5976 {
5977 const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
5978 const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
5979 int i;
5980
5981 if (equal == NULL || psa == NULL || psb == NULL)
5982 return -EINVAL;
5983
5984 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5985 if (psa->performance_level_count != psb->performance_level_count) {
5986 *equal = false;
5987 return 0;
5988 }
5989
5990 for (i = 0; i < psa->performance_level_count; i++) {
5991 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5992 /* If we have found even one performance level pair that is different the states are different. */
5993 *equal = false;
5994 return 0;
5995 }
5996 }
5997
5998 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5999 *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6000 *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6001 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6002 *equal &= (psa->acp_clk == psb->acp_clk);
6003
6004 return 0;
6005 }
6006
6007 static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
6008 {
6009 if (mode) {
6010 /* stop auto-manage */
6011 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
6012 PHM_PlatformCaps_MicrocodeFanControl))
6013 tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
6014 tonga_fan_ctrl_set_static_mode(hwmgr, mode);
6015 } else
6016 /* restart auto-manage */
6017 tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
6018
6019 return 0;
6020 }
6021
6022 static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
6023 {
6024 if (hwmgr->fan_ctrl_is_in_default_mode)
6025 return hwmgr->fan_ctrl_default_mode;
6026 else
6027 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
6028 CG_FDO_CTRL2, FDO_PWM_MODE);
6029 }
6030
6031 static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
6032 enum pp_clock_type type, uint32_t mask)
6033 {
6034 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6035
6036 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6037 return -EINVAL;
6038
6039 switch (type) {
6040 case PP_SCLK:
6041 if (!data->sclk_dpm_key_disabled)
6042 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6043 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6044 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6045 break;
6046 case PP_MCLK:
6047 if (!data->mclk_dpm_key_disabled)
6048 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6049 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6050 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6051 break;
6052 case PP_PCIE:
6053 {
6054 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
6055 uint32_t level = 0;
6056
6057 while (tmp >>= 1)
6058 level++;
6059
6060 if (!data->pcie_dpm_key_disabled)
6061 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6062 PPSMC_MSG_PCIeDPM_ForceLevel,
6063 level);
6064 break;
6065 }
6066 default:
6067 break;
6068 }
6069
6070 return 0;
6071 }
6072
6073 static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
6074 enum pp_clock_type type, char *buf)
6075 {
6076 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6077 struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6078 struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6079 struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
6080 int i, now, size = 0;
6081 uint32_t clock, pcie_speed;
6082
6083 switch (type) {
6084 case PP_SCLK:
6085 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
6086 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6087
6088 for (i = 0; i < sclk_table->count; i++) {
6089 if (clock > sclk_table->dpm_levels[i].value)
6090 continue;
6091 break;
6092 }
6093 now = i;
6094
6095 for (i = 0; i < sclk_table->count; i++)
6096 size += sprintf(buf + size, "%d: %uMhz %s\n",
6097 i, sclk_table->dpm_levels[i].value / 100,
6098 (i == now) ? "*" : "");
6099 break;
6100 case PP_MCLK:
6101 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
6102 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6103
6104 for (i = 0; i < mclk_table->count; i++) {
6105 if (clock > mclk_table->dpm_levels[i].value)
6106 continue;
6107 break;
6108 }
6109 now = i;
6110
6111 for (i = 0; i < mclk_table->count; i++)
6112 size += sprintf(buf + size, "%d: %uMhz %s\n",
6113 i, mclk_table->dpm_levels[i].value / 100,
6114 (i == now) ? "*" : "");
6115 break;
6116 case PP_PCIE:
6117 pcie_speed = tonga_get_current_pcie_speed(hwmgr);
6118 for (i = 0; i < pcie_table->count; i++) {
6119 if (pcie_speed != pcie_table->dpm_levels[i].value)
6120 continue;
6121 break;
6122 }
6123 now = i;
6124
6125 for (i = 0; i < pcie_table->count; i++)
6126 size += sprintf(buf + size, "%d: %s %s\n", i,
6127 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
6128 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6129 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6130 (i == now) ? "*" : "");
6131 break;
6132 default:
6133 break;
6134 }
6135 return size;
6136 }
6137
6138 static int tonga_get_sclk_od(struct pp_hwmgr *hwmgr)
6139 {
6140 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6141 struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6142 struct tonga_single_dpm_table *golden_sclk_table =
6143 &(data->golden_dpm_table.sclk_table);
6144 int value;
6145
6146 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
6147 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
6148 100 /
6149 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6150
6151 return value;
6152 }
6153
6154 static int tonga_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
6155 {
6156 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6157 struct tonga_single_dpm_table *golden_sclk_table =
6158 &(data->golden_dpm_table.sclk_table);
6159 struct pp_power_state *ps;
6160 struct tonga_power_state *tonga_ps;
6161
6162 if (value > 20)
6163 value = 20;
6164
6165 ps = hwmgr->request_ps;
6166
6167 if (ps == NULL)
6168 return -EINVAL;
6169
6170 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
6171
6172 tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].engine_clock =
6173 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
6174 value / 100 +
6175 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
6176
6177 return 0;
6178 }
6179
6180 static int tonga_get_mclk_od(struct pp_hwmgr *hwmgr)
6181 {
6182 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6183 struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6184 struct tonga_single_dpm_table *golden_mclk_table =
6185 &(data->golden_dpm_table.mclk_table);
6186 int value;
6187
6188 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
6189 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
6190 100 /
6191 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6192
6193 return value;
6194 }
6195
6196 static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
6197 {
6198 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6199 struct tonga_single_dpm_table *golden_mclk_table =
6200 &(data->golden_dpm_table.mclk_table);
6201 struct pp_power_state *ps;
6202 struct tonga_power_state *tonga_ps;
6203
6204 if (value > 20)
6205 value = 20;
6206
6207 ps = hwmgr->request_ps;
6208
6209 if (ps == NULL)
6210 return -EINVAL;
6211
6212 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
6213
6214 tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock =
6215 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
6216 value / 100 +
6217 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
6218
6219 return 0;
6220 }
6221
6222 static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6223 .backend_init = &tonga_hwmgr_backend_init,
6224 .backend_fini = &tonga_hwmgr_backend_fini,
6225 .asic_setup = &tonga_setup_asic_task,
6226 .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6227 .dynamic_state_management_disable = &tonga_disable_dpm_tasks,
6228 .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6229 .force_dpm_level = &tonga_force_dpm_level,
6230 .power_state_set = tonga_set_power_state_tasks,
6231 .get_power_state_size = tonga_get_power_state_size,
6232 .get_mclk = tonga_dpm_get_mclk,
6233 .get_sclk = tonga_dpm_get_sclk,
6234 .patch_boot_state = tonga_dpm_patch_boot_state,
6235 .get_pp_table_entry = tonga_get_pp_table_entry,
6236 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6237 .print_current_perforce_level = tonga_print_current_perforce_level,
6238 .powerdown_uvd = tonga_phm_powerdown_uvd,
6239 .powergate_uvd = tonga_phm_powergate_uvd,
6240 .powergate_vce = tonga_phm_powergate_vce,
6241 .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
6242 .update_clock_gatings = tonga_phm_update_clock_gatings,
6243 .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6244 .display_config_changed = tonga_display_configuration_changed_task,
6245 .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6246 .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6247 .get_temperature = tonga_thermal_get_temperature,
6248 .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6249 .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6250 .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6251 .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6252 .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6253 .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6254 .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6255 .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6256 .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
6257 .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6258 .check_states_equal = tonga_check_states_equal,
6259 .set_fan_control_mode = tonga_set_fan_control_mode,
6260 .get_fan_control_mode = tonga_get_fan_control_mode,
6261 .force_clock_level = tonga_force_clock_level,
6262 .print_clock_levels = tonga_print_clock_levels,
6263 .get_sclk_od = tonga_get_sclk_od,
6264 .set_sclk_od = tonga_set_sclk_od,
6265 .get_mclk_od = tonga_get_mclk_od,
6266 .set_mclk_od = tonga_set_mclk_od,
6267 };
6268
6269 int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6270 {
6271 hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6272 hwmgr->pptable_func = &tonga_pptable_funcs;
6273 pp_tonga_thermal_initialize(hwmgr);
6274 return 0;
6275 }
6276
Linux kernel - Deliverables
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