drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32 #include "ppatomctrl.h"
  33 #include "hwmgr_ppt.h"
  34
  35 struct pp_instance;
  36 struct pp_hwmgr;
  37 struct pp_hw_power_state;
  38 struct pp_power_state;
  39 struct PP_VCEState;
  40 struct phm_fan_speed_info;
  41 struct pp_atomctrl_voltage_table;
  42
  43
  44 extern int amdgpu_powercontainment;
  45 extern int amdgpu_sclk_deep_sleep_en;
  46
  47 enum DISPLAY_GAP {
  48         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  49         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  50         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  51         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  52 };
  53 typedef enum DISPLAY_GAP DISPLAY_GAP;
  54
  55
  56 struct vi_dpm_level {
  57         bool enabled;
  58         uint32_t value;
  59         uint32_t param1;
  60 };
  61
  62 struct vi_dpm_table {
  63         uint32_t count;
  64         struct vi_dpm_level dpm_level[1];
  65 };
  66
  67 enum PP_Result {
  68         PP_Result_TableImmediateExit = 0x13,
  69 };
  70
  71 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  72 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  73 #define PCIE_PERF_REQ_GEN1         2
  74 #define PCIE_PERF_REQ_GEN2         3
  75 #define PCIE_PERF_REQ_GEN3         4
  76
  77 enum PHM_BackEnd_Magic {
  78         PHM_Dummy_Magic       = 0xAA5555AA,
  79         PHM_RV770_Magic       = 0xDCBAABCD,
  80         PHM_Kong_Magic        = 0x239478DF,
  81         PHM_NIslands_Magic    = 0x736C494E,
  82         PHM_Sumo_Magic        = 0x8339FA11,
  83         PHM_SIslands_Magic    = 0x369431AC,
  84         PHM_Trinity_Magic     = 0x96751873,
  85         PHM_CIslands_Magic    = 0x38AC78B0,
  86         PHM_Kv_Magic          = 0xDCBBABC0,
  87         PHM_VIslands_Magic    = 0x20130307,
  88         PHM_Cz_Magic          = 0x67DCBA25
  89 };
  90
  91
  92 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
  93 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
  94 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
  95 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
  96
  97 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
  98                                   void *output, void *storage, int result);
  99
 100 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
 101
 102 struct phm_set_power_state_input {
 103         const struct pp_hw_power_state *pcurrent_state;
 104         const struct pp_hw_power_state *pnew_state;
 105 };
 106
 107 struct phm_acp_arbiter {
 108         uint32_t acpclk;
 109 };
 110
 111 struct phm_uvd_arbiter {
 112         uint32_t vclk;
 113         uint32_t dclk;
 114         uint32_t vclk_ceiling;
 115         uint32_t dclk_ceiling;
 116 };
 117
 118 struct phm_vce_arbiter {
 119         uint32_t   evclk;
 120         uint32_t   ecclk;
 121 };
 122
 123 struct phm_gfx_arbiter {
 124         uint32_t sclk;
 125         uint32_t mclk;
 126         uint32_t sclk_over_drive;
 127         uint32_t mclk_over_drive;
 128         uint32_t sclk_threshold;
 129         uint32_t num_cus;
 130 };
 131
 132 /* Entries in the master tables */
 133 struct phm_master_table_item {
 134         phm_check_function isFunctionNeededInRuntimeTable;
 135         phm_table_function tableFunction;
 136 };
 137
 138 enum phm_master_table_flag {
 139         PHM_MasterTableFlag_None         = 0,
 140         PHM_MasterTableFlag_ExitOnError  = 1,
 141 };
 142
 143 /* The header of the master tables */
 144 struct phm_master_table_header {
 145         uint32_t storage_size;
 146         uint32_t flags;
 147         const struct phm_master_table_item *master_list;
 148 };
 149
 150 struct phm_runtime_table_header {
 151         uint32_t storage_size;
 152         bool exit_error;
 153         phm_table_function *function_list;
 154 };
 155
 156 struct phm_clock_array {
 157         uint32_t count;
 158         uint32_t values[1];
 159 };
 160
 161 struct phm_clock_voltage_dependency_record {
 162         uint32_t clk;
 163         uint32_t v;
 164 };
 165
 166 struct phm_vceclock_voltage_dependency_record {
 167         uint32_t ecclk;
 168         uint32_t evclk;
 169         uint32_t v;
 170 };
 171
 172 struct phm_uvdclock_voltage_dependency_record {
 173         uint32_t vclk;
 174         uint32_t dclk;
 175         uint32_t v;
 176 };
 177
 178 struct phm_samuclock_voltage_dependency_record {
 179         uint32_t samclk;
 180         uint32_t v;
 181 };
 182
 183 struct phm_acpclock_voltage_dependency_record {
 184         uint32_t acpclk;
 185         uint32_t v;
 186 };
 187
 188 struct phm_clock_voltage_dependency_table {
 189         uint32_t count;                                                                         /* Number of entries. */
 190         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 191 };
 192
 193 struct phm_phase_shedding_limits_record {
 194         uint32_t  Voltage;
 195         uint32_t    Sclk;
 196         uint32_t    Mclk;
 197 };
 198
 199
 200 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
 201                               struct phm_runtime_table_header *rt_table,
 202                               void *input, void *output);
 203
 204 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
 205                                const struct phm_master_table_header *master_table,
 206                                struct phm_runtime_table_header *rt_table);
 207
 208 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
 209                              struct phm_runtime_table_header *rt_table);
 210
 211
 212 struct phm_uvd_clock_voltage_dependency_record {
 213         uint32_t vclk;
 214         uint32_t dclk;
 215         uint32_t v;
 216 };
 217
 218 struct phm_uvd_clock_voltage_dependency_table {
 219         uint8_t count;
 220         struct phm_uvd_clock_voltage_dependency_record entries[1];
 221 };
 222
 223 struct phm_acp_clock_voltage_dependency_record {
 224         uint32_t acpclk;
 225         uint32_t v;
 226 };
 227
 228 struct phm_acp_clock_voltage_dependency_table {
 229         uint32_t count;
 230         struct phm_acp_clock_voltage_dependency_record entries[1];
 231 };
 232
 233 struct phm_vce_clock_voltage_dependency_record {
 234         uint32_t ecclk;
 235         uint32_t evclk;
 236         uint32_t v;
 237 };
 238
 239 struct phm_phase_shedding_limits_table {
 240         uint32_t                           count;
 241         struct phm_phase_shedding_limits_record  entries[1];
 242 };
 243
 244 struct phm_vceclock_voltage_dependency_table {
 245         uint8_t count;                                    /* Number of entries. */
 246         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 247 };
 248
 249 struct phm_uvdclock_voltage_dependency_table {
 250         uint8_t count;                                    /* Number of entries. */
 251         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 252 };
 253
 254 struct phm_samuclock_voltage_dependency_table {
 255         uint8_t count;                                    /* Number of entries. */
 256         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 257 };
 258
 259 struct phm_acpclock_voltage_dependency_table {
 260         uint32_t count;                                    /* Number of entries. */
 261         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 262 };
 263
 264 struct phm_vce_clock_voltage_dependency_table {
 265         uint8_t count;
 266         struct phm_vce_clock_voltage_dependency_record entries[1];
 267 };
 268
 269 struct pp_hwmgr_func {
 270         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 271         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 272         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 273         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 274
 275         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 276                                 struct pp_power_state  *prequest_ps,
 277                         const struct pp_power_state *pcurrent_ps);
 278
 279         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 280                                         enum amd_dpm_forced_level level);
 281
 282         int (*dynamic_state_management_enable)(
 283                                                 struct pp_hwmgr *hw_mgr);
 284         int (*dynamic_state_management_disable)(
 285                                                 struct pp_hwmgr *hw_mgr);
 286
 287         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 288                                      struct pp_hw_power_state *hw_ps);
 289
 290         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 291                             unsigned long, struct pp_power_state *);
 292         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 293         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 294         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 295         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 296         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 297         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 298         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 299                                                 const void *state);
 300         void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
 301                                                         struct seq_file *m);
 302         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 303         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 304         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 305         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 306         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 307                                                 const uint32_t *msg_id);
 308         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 309         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 310         int (*get_temperature)(struct pp_hwmgr *hwmgr);
 311         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 312         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 313         int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 314         int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 315         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 316         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 317         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 318         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 319         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 320         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 321         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 322                                         const void *thermal_interrupt_info);
 323         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 324         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 325                                         const struct pp_hw_power_state *pstate1,
 326                                         const struct pp_hw_power_state *pstate2,
 327                                         bool *equal);
 328         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 329         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 330                                 bool cc6_disable, bool pstate_disable,
 331                                 bool pstate_switch_disable);
 332         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 333                         struct amd_pp_simple_clock_info *info);
 334         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 335                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 336         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 337                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 338         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 339         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 340         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 341         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 342         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 343         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 344         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 345         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 346         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 347         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 348 };
 349
 350 struct pp_table_func {
 351         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 352         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 353         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 354         int (*pptable_get_vce_state_table_entry)(
 355                                                 struct pp_hwmgr *hwmgr,
 356                                                 unsigned long i,
 357                                                 struct PP_VCEState *vce_state,
 358                                                 void **clock_info,
 359                                                 unsigned long *flag);
 360 };
 361
 362 union phm_cac_leakage_record {
 363         struct {
 364                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 365                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 366         };
 367         struct {
 368                 uint16_t Vddc1;
 369                 uint16_t Vddc2;
 370                 uint16_t Vddc3;
 371         };
 372 };
 373
 374 struct phm_cac_leakage_table {
 375         uint32_t count;
 376         union phm_cac_leakage_record entries[1];
 377 };
 378
 379 struct phm_samu_clock_voltage_dependency_record {
 380         uint32_t samclk;
 381         uint32_t v;
 382 };
 383
 384
 385 struct phm_samu_clock_voltage_dependency_table {
 386         uint8_t count;
 387         struct phm_samu_clock_voltage_dependency_record entries[1];
 388 };
 389
 390 struct phm_cac_tdp_table {
 391         uint16_t usTDP;
 392         uint16_t usConfigurableTDP;
 393         uint16_t usTDC;
 394         uint16_t usBatteryPowerLimit;
 395         uint16_t usSmallPowerLimit;
 396         uint16_t usLowCACLeakage;
 397         uint16_t usHighCACLeakage;
 398         uint16_t usMaximumPowerDeliveryLimit;
 399         uint16_t usOperatingTempMinLimit;
 400         uint16_t usOperatingTempMaxLimit;
 401         uint16_t usOperatingTempStep;
 402         uint16_t usOperatingTempHyst;
 403         uint16_t usDefaultTargetOperatingTemp;
 404         uint16_t usTargetOperatingTemp;
 405         uint16_t usPowerTuneDataSetID;
 406         uint16_t usSoftwareShutdownTemp;
 407         uint16_t usClockStretchAmount;
 408         uint16_t usTemperatureLimitHotspot;
 409         uint16_t usTemperatureLimitLiquid1;
 410         uint16_t usTemperatureLimitLiquid2;
 411         uint16_t usTemperatureLimitVrVddc;
 412         uint16_t usTemperatureLimitVrMvdd;
 413         uint16_t usTemperatureLimitPlx;
 414         uint8_t  ucLiquid1_I2C_address;
 415         uint8_t  ucLiquid2_I2C_address;
 416         uint8_t  ucLiquid_I2C_Line;
 417         uint8_t  ucVr_I2C_address;
 418         uint8_t  ucVr_I2C_Line;
 419         uint8_t  ucPlx_I2C_address;
 420         uint8_t  ucPlx_I2C_Line;
 421         uint32_t usBoostPowerLimit;
 422         uint8_t  ucCKS_LDO_REFSEL;
 423 };
 424
 425 struct phm_ppm_table {
 426         uint8_t   ppm_design;
 427         uint16_t  cpu_core_number;
 428         uint32_t  platform_tdp;
 429         uint32_t  small_ac_platform_tdp;
 430         uint32_t  platform_tdc;
 431         uint32_t  small_ac_platform_tdc;
 432         uint32_t  apu_tdp;
 433         uint32_t  dgpu_tdp;
 434         uint32_t  dgpu_ulv_power;
 435         uint32_t  tj_max;
 436 };
 437
 438 struct phm_vq_budgeting_record {
 439         uint32_t ulCUs;
 440         uint32_t ulSustainableSOCPowerLimitLow;
 441         uint32_t ulSustainableSOCPowerLimitHigh;
 442         uint32_t ulMinSclkLow;
 443         uint32_t ulMinSclkHigh;
 444         uint8_t  ucDispConfig;
 445         uint32_t ulDClk;
 446         uint32_t ulEClk;
 447         uint32_t ulSustainableSclk;
 448         uint32_t ulSustainableCUs;
 449 };
 450
 451 struct phm_vq_budgeting_table {
 452         uint8_t numEntries;
 453         struct phm_vq_budgeting_record entries[1];
 454 };
 455
 456 struct phm_clock_and_voltage_limits {
 457         uint32_t sclk;
 458         uint32_t mclk;
 459         uint16_t vddc;
 460         uint16_t vddci;
 461         uint16_t vddgfx;
 462 };
 463
 464 /* Structure to hold PPTable information */
 465
 466 struct phm_ppt_v1_information {
 467         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 468         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 469         struct phm_clock_array *valid_sclk_values;
 470         struct phm_clock_array *valid_mclk_values;
 471         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 472         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 473         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 474         struct phm_ppm_table *ppm_parameter_table;
 475         struct phm_cac_tdp_table *cac_dtp_table;
 476         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 477         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 478         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 479         struct phm_ppt_v1_pcie_table *pcie_table;
 480         uint16_t us_ulv_voltage_offset;
 481 };
 482
 483 struct phm_dynamic_state_info {
 484         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 485         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 486         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 487         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 488         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 489         struct phm_clock_array                    *valid_sclk_values;
 490         struct phm_clock_array                    *valid_mclk_values;
 491         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 492         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 493         uint32_t                                  mclk_sclk_ratio;
 494         uint32_t                                  sclk_mclk_delta;
 495         uint32_t                                  vddc_vddci_delta;
 496         uint32_t                                  min_vddc_for_pcie_gen2;
 497         struct phm_cac_leakage_table              *cac_leakage_table;
 498         struct phm_phase_shedding_limits_table    *vddc_phase_shed_limits_table;
 499
 500         struct phm_vce_clock_voltage_dependency_table
 501                                             *vce_clock_voltage_dependency_table;
 502         struct phm_uvd_clock_voltage_dependency_table
 503                                             *uvd_clock_voltage_dependency_table;
 504         struct phm_acp_clock_voltage_dependency_table
 505                                             *acp_clock_voltage_dependency_table;
 506         struct phm_samu_clock_voltage_dependency_table
 507                                            *samu_clock_voltage_dependency_table;
 508
 509         struct phm_ppm_table                          *ppm_parameter_table;
 510         struct phm_cac_tdp_table                      *cac_dtp_table;
 511         struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
 512         struct phm_vq_budgeting_table                             *vq_budgeting_table;
 513 };
 514
 515 struct pp_fan_info {
 516         bool bNoFan;
 517         uint8_t   ucTachometerPulsesPerRevolution;
 518         uint32_t   ulMinRPM;
 519         uint32_t   ulMaxRPM;
 520 };
 521
 522 struct pp_advance_fan_control_parameters {
 523         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 524         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 525         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 526         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 527         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 528         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 529         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 530         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 531         uint16_t  usTMax;                          /* The max temperature */
 532         uint8_t   ucFanControlMode;
 533         uint16_t  usFanPWMMinLimit;
 534         uint16_t  usFanPWMMaxLimit;
 535         uint16_t  usFanPWMStep;
 536         uint16_t  usDefaultMaxFanPWM;
 537         uint16_t  usFanOutputSensitivity;
 538         uint16_t  usDefaultFanOutputSensitivity;
 539         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 540         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 541         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 542         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 543         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 544         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 545         uint16_t  usFanCurrentLow;                 /* Low current */
 546         uint16_t  usFanCurrentHigh;                /* High current */
 547         uint16_t  usFanRPMLow;                     /* Low RPM */
 548         uint16_t  usFanRPMHigh;                    /* High RPM */
 549         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 550         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 551         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 552         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 553         uint16_t  usFanGainHotspot;
 554         uint16_t  usFanGainLiquid;
 555         uint16_t  usFanGainVrVddc;
 556         uint16_t  usFanGainVrMvdd;
 557         uint16_t  usFanGainPlx;
 558         uint16_t  usFanGainHbm;
 559 };
 560
 561 struct pp_thermal_controller_info {
 562         uint8_t ucType;
 563         uint8_t ucI2cLine;
 564         uint8_t ucI2cAddress;
 565         struct pp_fan_info fanInfo;
 566         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 567 };
 568
 569 struct phm_microcode_version_info {
 570         uint32_t SMC;
 571         uint32_t DMCU;
 572         uint32_t MC;
 573         uint32_t NB;
 574 };
 575
 576 /**
 577  * The main hardware manager structure.
 578  */
 579 struct pp_hwmgr {
 580         uint32_t chip_family;
 581         uint32_t chip_id;
 582         uint32_t hw_revision;
 583         uint32_t sub_sys_id;
 584         uint32_t sub_vendor_id;
 585
 586         void *device;
 587         struct pp_smumgr *smumgr;
 588         const void *soft_pp_table;
 589         uint32_t soft_pp_table_size;
 590         void *hardcode_pp_table;
 591         bool need_pp_table_upload;
 592         enum amd_dpm_forced_level dpm_level;
 593         bool block_hw_access;
 594         struct phm_gfx_arbiter gfx_arbiter;
 595         struct phm_acp_arbiter acp_arbiter;
 596         struct phm_uvd_arbiter uvd_arbiter;
 597         struct phm_vce_arbiter vce_arbiter;
 598         uint32_t usec_timeout;
 599         void *pptable;
 600         struct phm_platform_descriptor platform_descriptor;
 601         void *backend;
 602         enum PP_DAL_POWERLEVEL dal_power_level;
 603         struct phm_dynamic_state_info dyn_state;
 604         struct phm_runtime_table_header setup_asic;
 605         struct phm_runtime_table_header power_down_asic;
 606         struct phm_runtime_table_header disable_dynamic_state_management;
 607         struct phm_runtime_table_header enable_dynamic_state_management;
 608         struct phm_runtime_table_header set_power_state;
 609         struct phm_runtime_table_header enable_clock_power_gatings;
 610         struct phm_runtime_table_header display_configuration_changed;
 611         struct phm_runtime_table_header start_thermal_controller;
 612         struct phm_runtime_table_header set_temperature_range;
 613         const struct pp_hwmgr_func *hwmgr_func;
 614         const struct pp_table_func *pptable_func;
 615         struct pp_power_state    *ps;
 616         enum pp_power_source  power_source;
 617         uint32_t num_ps;
 618         struct pp_thermal_controller_info thermal_controller;
 619         bool fan_ctrl_is_in_default_mode;
 620         uint32_t fan_ctrl_default_mode;
 621         uint32_t tmin;
 622         struct phm_microcode_version_info microcode_version_info;
 623         uint32_t ps_size;
 624         struct pp_power_state    *current_ps;
 625         struct pp_power_state    *request_ps;
 626         struct pp_power_state    *boot_ps;
 627         struct pp_power_state    *uvd_ps;
 628         struct amd_pp_display_configuration display_config;
 629 };
 630
 631
 632 extern int hwmgr_init(struct amd_pp_init *pp_init,
 633                       struct pp_instance *handle);
 634
 635 extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
 636
 637 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
 638
 639 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 640                                 uint32_t value, uint32_t mask);
 641
 642
 643
 644 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 645                                 uint32_t indirect_port,
 646                                 uint32_t index,
 647                                 uint32_t value,
 648                                 uint32_t mask);
 649
 650
 651
 652 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 653 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 654 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
 655
 656 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
 657 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 658 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 659 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
 660 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
 661 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
 662 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
 663 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
 664 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
 665 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
 666 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
 667 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
 668                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
 669 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 670 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 671 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
 672 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 673
 674 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 675
 676 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 677 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 678
 679 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 680         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 681          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 682
 683 #define PHM_GET_FIELD(value, reg, field)        \
 684         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 685          PHM_FIELD_SHIFT(reg, field))
 686
 687
 688
 689
 690 /* Operations on named fields. */
 691
 692 #define PHM_READ_FIELD(device, reg, field)      \
 693         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 694
 695 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 696         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 697                         reg, field)
 698
 699 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 700         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 701                         reg, field)
 702
 703 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 704         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 705                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 706
 707 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 708         cgs_write_ind_register(device, port, ix##reg,   \
 709                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 710                                 reg, field, fieldval))
 711
 712 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 713         cgs_write_ind_register(device, port, ix##reg,   \
 714                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 715                                 reg, field, fieldval))
 716
 717 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
 718        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 719
 720
 721 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
 722        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 723
 724 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 725         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 726                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 727
 728
 729 #endif /* _HWMGR_H_ */