drivers/gpu/drm/arc/arcpgu_crtc.c

   1 /*
   2  * ARC PGU DRM driver.
   3  *
   4  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <linux/clk.h>
  23 #include <linux/platform_data/simplefb.h>
  24
  25 #include "arcpgu.h"
  26 #include "arcpgu_regs.h"
  27
  28 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
  29
  30 static struct simplefb_format supported_formats[] = {
  31         { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
  32         { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
  33 };
  34
  35 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
  36 {
  37         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  38         uint32_t pixel_format = crtc->primary->state->fb->pixel_format;
  39         struct simplefb_format *format = NULL;
  40         int i;
  41
  42         for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
  43                 if (supported_formats[i].fourcc == pixel_format)
  44                         format = &supported_formats[i];
  45         }
  46
  47         if (WARN_ON(!format))
  48                 return;
  49
  50         if (format->fourcc == DRM_FORMAT_RGB888)
  51                 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
  52                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
  53                                            ARCPGU_MODE_RGB888_MASK);
  54
  55 }
  56
  57 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
  58         .destroy = drm_crtc_cleanup,
  59         .set_config = drm_atomic_helper_set_config,
  60         .page_flip = drm_atomic_helper_page_flip,
  61         .reset = drm_atomic_helper_crtc_reset,
  62         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  63         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  64 };
  65
  66 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  67 {
  68         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  69         struct drm_display_mode *m = &crtc->state->adjusted_mode;
  70         u32 val;
  71
  72         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
  73                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
  74
  75         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
  76                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
  77                                     m->crtc_hsync_end - m->crtc_hdisplay));
  78
  79         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
  80                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
  81                                     m->crtc_vsync_end - m->crtc_vdisplay));
  82
  83         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
  84                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
  85                                     m->crtc_vblank_end - m->crtc_vblank_start));
  86
  87         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  88
  89         if (m->flags & DRM_MODE_FLAG_PVSYNC)
  90                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
  91         else
  92                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
  93
  94         if (m->flags & DRM_MODE_FLAG_PHSYNC)
  95                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
  96         else
  97                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
  98
  99         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 100         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 101         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 102
 103         arc_pgu_set_pxl_fmt(crtc);
 104
 105         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 106 }
 107
 108 static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
 109 {
 110         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 111
 112         clk_prepare_enable(arcpgu->clk);
 113         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 114                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 115                       ARCPGU_CTRL_ENABLE_MASK);
 116 }
 117
 118 static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
 119 {
 120         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 121
 122         if (!crtc->primary->fb)
 123                 return;
 124
 125         clk_disable_unprepare(arcpgu->clk);
 126         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 127                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 128                               ~ARCPGU_CTRL_ENABLE_MASK);
 129 }
 130
 131 static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
 132                                      struct drm_crtc_state *state)
 133 {
 134         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 135         struct drm_display_mode *mode = &state->adjusted_mode;
 136         long rate, clk_rate = mode->clock * 1000;
 137
 138         rate = clk_round_rate(arcpgu->clk, clk_rate);
 139         if (rate != clk_rate)
 140                 return -EINVAL;
 141
 142         return 0;
 143 }
 144
 145 static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
 146                                       struct drm_crtc_state *state)
 147 {
 148         struct drm_pending_vblank_event *event = crtc->state->event;
 149
 150         if (event) {
 151                 crtc->state->event = NULL;
 152
 153                 spin_lock_irq(&crtc->dev->event_lock);
 154                 drm_crtc_send_vblank_event(crtc, event);
 155                 spin_unlock_irq(&crtc->dev->event_lock);
 156         }
 157 }
 158
 159 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
 160         .mode_set       = drm_helper_crtc_mode_set,
 161         .mode_set_base  = drm_helper_crtc_mode_set_base,
 162         .mode_set_nofb  = arc_pgu_crtc_mode_set_nofb,
 163         .enable         = arc_pgu_crtc_enable,
 164         .disable        = arc_pgu_crtc_disable,
 165         .prepare        = arc_pgu_crtc_disable,
 166         .commit         = arc_pgu_crtc_enable,
 167         .atomic_check   = arc_pgu_crtc_atomic_check,
 168         .atomic_begin   = arc_pgu_crtc_atomic_begin,
 169 };
 170
 171 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
 172                                         struct drm_plane_state *state)
 173 {
 174         struct arcpgu_drm_private *arcpgu;
 175         struct drm_gem_cma_object *gem;
 176
 177         if (!plane->state->crtc || !plane->state->fb)
 178                 return;
 179
 180         arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
 181         gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
 182         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 183 }
 184
 185 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
 186         .prepare_fb = NULL,
 187         .cleanup_fb = NULL,
 188         .atomic_update = arc_pgu_plane_atomic_update,
 189 };
 190
 191 static void arc_pgu_plane_destroy(struct drm_plane *plane)
 192 {
 193         drm_plane_helper_disable(plane);
 194         drm_plane_cleanup(plane);
 195 }
 196
 197 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
 198         .update_plane           = drm_atomic_helper_update_plane,
 199         .disable_plane          = drm_atomic_helper_disable_plane,
 200         .destroy                = arc_pgu_plane_destroy,
 201         .reset                  = drm_atomic_helper_plane_reset,
 202         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 203         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 204 };
 205
 206 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
 207 {
 208         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 209         struct drm_plane *plane = NULL;
 210         u32 formats[ARRAY_SIZE(supported_formats)], i;
 211         int ret;
 212
 213         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 214         if (!plane)
 215                 return ERR_PTR(-ENOMEM);
 216
 217         for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
 218                 formats[i] = supported_formats[i].fourcc;
 219
 220         ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
 221                                        formats, ARRAY_SIZE(formats),
 222                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 223         if (ret)
 224                 return ERR_PTR(ret);
 225
 226         drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
 227         arcpgu->plane = plane;
 228
 229         return plane;
 230 }
 231
 232 int arc_pgu_setup_crtc(struct drm_device *drm)
 233 {
 234         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 235         struct drm_plane *primary;
 236         int ret;
 237
 238         primary = arc_pgu_plane_init(drm);
 239         if (IS_ERR(primary))
 240                 return PTR_ERR(primary);
 241
 242         ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
 243                                         &arc_pgu_crtc_funcs, NULL);
 244         if (ret) {
 245                 arc_pgu_plane_destroy(primary);
 246                 return ret;
 247         }
 248
 249         drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
 250         return 0;
 251 }