2 * Analogix DP (Display Port) core interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/interrupt.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/component.h>
23 #include <linux/phy/phy.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_panel.h>
31 #include <drm/bridge/analogix_dp.h>
33 #include "analogix_dp_core.h"
35 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
38 struct i2c_client
*client
;
39 struct device_node
*node
;
42 static void analogix_dp_init_dp(struct analogix_dp_device
*dp
)
44 analogix_dp_reset(dp
);
46 analogix_dp_swreset(dp
);
48 analogix_dp_init_analog_param(dp
);
49 analogix_dp_init_interrupt(dp
);
51 /* SW defined function Normal operation */
52 analogix_dp_enable_sw_function(dp
);
54 analogix_dp_config_interrupt(dp
);
55 analogix_dp_init_analog_func(dp
);
57 analogix_dp_init_hpd(dp
);
58 analogix_dp_init_aux(dp
);
61 static int analogix_dp_detect_hpd(struct analogix_dp_device
*dp
)
65 while (timeout_loop
< DP_TIMEOUT_LOOP_COUNT
) {
66 if (analogix_dp_get_plug_in_status(dp
) == 0)
74 * Some edp screen do not have hpd signal, so we can't just
75 * return failed when hpd plug in detect failed, DT property
76 * "force-hpd" would indicate whether driver need this.
82 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
83 * will not work, so we need to give a force hpd action to
84 * set HPD_STATUS manually.
86 dev_dbg(dp
->dev
, "failed to get hpd plug status, try to force hpd\n");
88 analogix_dp_force_hpd(dp
);
90 if (analogix_dp_get_plug_in_status(dp
) != 0) {
91 dev_err(dp
->dev
, "failed to get hpd plug in status\n");
95 dev_dbg(dp
->dev
, "success to get plug in status after force hpd\n");
100 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data
)
103 unsigned char sum
= 0;
105 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
106 sum
= sum
+ edid_data
[i
];
111 static int analogix_dp_read_edid(struct analogix_dp_device
*dp
)
113 unsigned char *edid
= dp
->edid
;
114 unsigned int extend_block
= 0;
116 unsigned char test_vector
;
120 * EDID device address is 0x50.
121 * However, if necessary, you must have set upper address
122 * into E-EDID in I2C device, 0x30.
125 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
126 retval
= analogix_dp_read_byte_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
132 if (extend_block
> 0) {
133 dev_dbg(dp
->dev
, "EDID data includes a single extension!\n");
136 retval
= analogix_dp_read_bytes_from_i2c(dp
,
137 I2C_EDID_DEVICE_ADDR
,
140 &edid
[EDID_HEADER_PATTERN
]);
142 dev_err(dp
->dev
, "EDID Read failed!\n");
145 sum
= analogix_dp_calc_edid_check_sum(edid
);
147 dev_err(dp
->dev
, "EDID bad checksum!\n");
151 /* Read additional EDID data */
152 retval
= analogix_dp_read_bytes_from_i2c(dp
,
153 I2C_EDID_DEVICE_ADDR
,
156 &edid
[EDID_BLOCK_LENGTH
]);
158 dev_err(dp
->dev
, "EDID Read failed!\n");
161 sum
= analogix_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
163 dev_err(dp
->dev
, "EDID bad checksum!\n");
167 analogix_dp_read_byte_from_dpcd(dp
, DP_TEST_REQUEST
,
169 if (test_vector
& DP_TEST_LINK_EDID_READ
) {
170 analogix_dp_write_byte_to_dpcd(dp
,
171 DP_TEST_EDID_CHECKSUM
,
172 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
173 analogix_dp_write_byte_to_dpcd(dp
,
175 DP_TEST_EDID_CHECKSUM_WRITE
);
178 dev_info(dp
->dev
, "EDID data does not include any extensions.\n");
181 retval
= analogix_dp_read_bytes_from_i2c(dp
,
182 I2C_EDID_DEVICE_ADDR
, EDID_HEADER_PATTERN
,
183 EDID_BLOCK_LENGTH
, &edid
[EDID_HEADER_PATTERN
]);
185 dev_err(dp
->dev
, "EDID Read failed!\n");
188 sum
= analogix_dp_calc_edid_check_sum(edid
);
190 dev_err(dp
->dev
, "EDID bad checksum!\n");
194 analogix_dp_read_byte_from_dpcd(dp
, DP_TEST_REQUEST
,
196 if (test_vector
& DP_TEST_LINK_EDID_READ
) {
197 analogix_dp_write_byte_to_dpcd(dp
,
198 DP_TEST_EDID_CHECKSUM
, edid
[EDID_CHECKSUM
]);
199 analogix_dp_write_byte_to_dpcd(dp
,
200 DP_TEST_RESPONSE
, DP_TEST_EDID_CHECKSUM_WRITE
);
204 dev_dbg(dp
->dev
, "EDID Read success!\n");
208 static int analogix_dp_handle_edid(struct analogix_dp_device
*dp
)
214 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
215 retval
= analogix_dp_read_bytes_from_dpcd(dp
, DP_DPCD_REV
, 12, buf
);
220 for (i
= 0; i
< 3; i
++) {
221 retval
= analogix_dp_read_edid(dp
);
230 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device
*dp
,
235 analogix_dp_read_byte_from_dpcd(dp
, DP_LANE_COUNT_SET
, &data
);
238 analogix_dp_write_byte_to_dpcd(dp
, DP_LANE_COUNT_SET
,
239 DP_LANE_COUNT_ENHANCED_FRAME_EN
|
240 DPCD_LANE_COUNT_SET(data
));
242 analogix_dp_write_byte_to_dpcd(dp
, DP_LANE_COUNT_SET
,
243 DPCD_LANE_COUNT_SET(data
));
246 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device
*dp
)
251 analogix_dp_read_byte_from_dpcd(dp
, DP_MAX_LANE_COUNT
, &data
);
252 retval
= DPCD_ENHANCED_FRAME_CAP(data
);
257 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device
*dp
)
261 data
= analogix_dp_is_enhanced_mode_available(dp
);
262 analogix_dp_enable_rx_to_enhanced_mode(dp
, data
);
263 analogix_dp_enable_enhanced_mode(dp
, data
);
266 static void analogix_dp_training_pattern_dis(struct analogix_dp_device
*dp
)
268 analogix_dp_set_training_pattern(dp
, DP_NONE
);
270 analogix_dp_write_byte_to_dpcd(dp
, DP_TRAINING_PATTERN_SET
,
271 DP_TRAINING_PATTERN_DISABLE
);
275 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device
*dp
,
276 int pre_emphasis
, int lane
)
280 analogix_dp_set_lane0_pre_emphasis(dp
, pre_emphasis
);
283 analogix_dp_set_lane1_pre_emphasis(dp
, pre_emphasis
);
287 analogix_dp_set_lane2_pre_emphasis(dp
, pre_emphasis
);
291 analogix_dp_set_lane3_pre_emphasis(dp
, pre_emphasis
);
296 static int analogix_dp_link_start(struct analogix_dp_device
*dp
)
299 int lane
, lane_count
, pll_tries
, retval
;
301 lane_count
= dp
->link_train
.lane_count
;
303 dp
->link_train
.lt_state
= CLOCK_RECOVERY
;
304 dp
->link_train
.eq_loop
= 0;
306 for (lane
= 0; lane
< lane_count
; lane
++)
307 dp
->link_train
.cr_loop
[lane
] = 0;
309 /* Set link rate and count as you want to establish*/
310 analogix_dp_set_link_bandwidth(dp
, dp
->link_train
.link_rate
);
311 analogix_dp_set_lane_count(dp
, dp
->link_train
.lane_count
);
313 /* Setup RX configuration */
314 buf
[0] = dp
->link_train
.link_rate
;
315 buf
[1] = dp
->link_train
.lane_count
;
316 retval
= analogix_dp_write_bytes_to_dpcd(dp
, DP_LINK_BW_SET
, 2, buf
);
320 /* Set TX pre-emphasis to minimum */
321 for (lane
= 0; lane
< lane_count
; lane
++)
322 analogix_dp_set_lane_lane_pre_emphasis(dp
,
323 PRE_EMPHASIS_LEVEL_0
, lane
);
325 /* Wait for PLL lock */
327 while (analogix_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
328 if (pll_tries
== DP_TIMEOUT_LOOP_COUNT
) {
329 dev_err(dp
->dev
, "Wait for PLL lock timed out\n");
334 usleep_range(90, 120);
337 /* Set training pattern 1 */
338 analogix_dp_set_training_pattern(dp
, TRAINING_PTN1
);
340 /* Set RX training pattern */
341 retval
= analogix_dp_write_byte_to_dpcd(dp
,
342 DP_TRAINING_PATTERN_SET
,
343 DP_LINK_SCRAMBLING_DISABLE
| DP_TRAINING_PATTERN_1
);
347 for (lane
= 0; lane
< lane_count
; lane
++)
348 buf
[lane
] = DP_TRAIN_PRE_EMPH_LEVEL_0
|
349 DP_TRAIN_VOLTAGE_SWING_LEVEL_0
;
351 retval
= analogix_dp_write_bytes_to_dpcd(dp
, DP_TRAINING_LANE0_SET
,
357 static unsigned char analogix_dp_get_lane_status(u8 link_status
[2], int lane
)
359 int shift
= (lane
& 1) * 4;
360 u8 link_value
= link_status
[lane
>> 1];
362 return (link_value
>> shift
) & 0xf;
365 static int analogix_dp_clock_recovery_ok(u8 link_status
[2], int lane_count
)
370 for (lane
= 0; lane
< lane_count
; lane
++) {
371 lane_status
= analogix_dp_get_lane_status(link_status
, lane
);
372 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
378 static int analogix_dp_channel_eq_ok(u8 link_status
[2], u8 link_align
,
384 if ((link_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
387 for (lane
= 0; lane
< lane_count
; lane
++) {
388 lane_status
= analogix_dp_get_lane_status(link_status
, lane
);
389 lane_status
&= DP_CHANNEL_EQ_BITS
;
390 if (lane_status
!= DP_CHANNEL_EQ_BITS
)
398 analogix_dp_get_adjust_request_voltage(u8 adjust_request
[2], int lane
)
400 int shift
= (lane
& 1) * 4;
401 u8 link_value
= adjust_request
[lane
>> 1];
403 return (link_value
>> shift
) & 0x3;
406 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
407 u8 adjust_request
[2],
410 int shift
= (lane
& 1) * 4;
411 u8 link_value
= adjust_request
[lane
>> 1];
413 return ((link_value
>> shift
) & 0xc) >> 2;
416 static void analogix_dp_set_lane_link_training(struct analogix_dp_device
*dp
,
417 u8 training_lane_set
, int lane
)
421 analogix_dp_set_lane0_link_training(dp
, training_lane_set
);
424 analogix_dp_set_lane1_link_training(dp
, training_lane_set
);
428 analogix_dp_set_lane2_link_training(dp
, training_lane_set
);
432 analogix_dp_set_lane3_link_training(dp
, training_lane_set
);
438 analogix_dp_get_lane_link_training(struct analogix_dp_device
*dp
,
445 reg
= analogix_dp_get_lane0_link_training(dp
);
448 reg
= analogix_dp_get_lane1_link_training(dp
);
451 reg
= analogix_dp_get_lane2_link_training(dp
);
454 reg
= analogix_dp_get_lane3_link_training(dp
);
464 static void analogix_dp_reduce_link_rate(struct analogix_dp_device
*dp
)
466 analogix_dp_training_pattern_dis(dp
);
467 analogix_dp_set_enhanced_mode(dp
);
469 dp
->link_train
.lt_state
= FAILED
;
472 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device
*dp
,
473 u8 adjust_request
[2])
475 int lane
, lane_count
;
476 u8 voltage_swing
, pre_emphasis
, training_lane
;
478 lane_count
= dp
->link_train
.lane_count
;
479 for (lane
= 0; lane
< lane_count
; lane
++) {
480 voltage_swing
= analogix_dp_get_adjust_request_voltage(
481 adjust_request
, lane
);
482 pre_emphasis
= analogix_dp_get_adjust_request_pre_emphasis(
483 adjust_request
, lane
);
484 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
485 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
487 if (voltage_swing
== VOLTAGE_LEVEL_3
)
488 training_lane
|= DP_TRAIN_MAX_SWING_REACHED
;
489 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
490 training_lane
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
492 dp
->link_train
.training_lane
[lane
] = training_lane
;
496 static int analogix_dp_process_clock_recovery(struct analogix_dp_device
*dp
)
498 int lane
, lane_count
, retval
;
499 u8 voltage_swing
, pre_emphasis
, training_lane
;
500 u8 link_status
[2], adjust_request
[2];
502 usleep_range(100, 101);
504 lane_count
= dp
->link_train
.lane_count
;
506 retval
= analogix_dp_read_bytes_from_dpcd(dp
,
507 DP_LANE0_1_STATUS
, 2, link_status
);
511 retval
= analogix_dp_read_bytes_from_dpcd(dp
,
512 DP_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
516 if (analogix_dp_clock_recovery_ok(link_status
, lane_count
) == 0) {
517 /* set training pattern 2 for EQ */
518 analogix_dp_set_training_pattern(dp
, TRAINING_PTN2
);
520 retval
= analogix_dp_write_byte_to_dpcd(dp
,
521 DP_TRAINING_PATTERN_SET
,
522 DP_LINK_SCRAMBLING_DISABLE
|
523 DP_TRAINING_PATTERN_2
);
527 dev_info(dp
->dev
, "Link Training Clock Recovery success\n");
528 dp
->link_train
.lt_state
= EQUALIZER_TRAINING
;
530 for (lane
= 0; lane
< lane_count
; lane
++) {
531 training_lane
= analogix_dp_get_lane_link_training(
533 voltage_swing
= analogix_dp_get_adjust_request_voltage(
534 adjust_request
, lane
);
535 pre_emphasis
= analogix_dp_get_adjust_request_pre_emphasis(
536 adjust_request
, lane
);
538 if (DPCD_VOLTAGE_SWING_GET(training_lane
) ==
540 DPCD_PRE_EMPHASIS_GET(training_lane
) ==
542 dp
->link_train
.cr_loop
[lane
]++;
544 if (dp
->link_train
.cr_loop
[lane
] == MAX_CR_LOOP
||
545 voltage_swing
== VOLTAGE_LEVEL_3
||
546 pre_emphasis
== PRE_EMPHASIS_LEVEL_3
) {
547 dev_err(dp
->dev
, "CR Max reached (%d,%d,%d)\n",
548 dp
->link_train
.cr_loop
[lane
],
549 voltage_swing
, pre_emphasis
);
550 analogix_dp_reduce_link_rate(dp
);
556 analogix_dp_get_adjust_training_lane(dp
, adjust_request
);
558 for (lane
= 0; lane
< lane_count
; lane
++)
559 analogix_dp_set_lane_link_training(dp
,
560 dp
->link_train
.training_lane
[lane
], lane
);
562 retval
= analogix_dp_write_bytes_to_dpcd(dp
,
563 DP_TRAINING_LANE0_SET
, lane_count
,
564 dp
->link_train
.training_lane
);
571 static int analogix_dp_process_equalizer_training(struct analogix_dp_device
*dp
)
573 int lane
, lane_count
, retval
;
575 u8 link_align
, link_status
[2], adjust_request
[2];
577 usleep_range(400, 401);
579 lane_count
= dp
->link_train
.lane_count
;
581 retval
= analogix_dp_read_bytes_from_dpcd(dp
,
582 DP_LANE0_1_STATUS
, 2, link_status
);
586 if (analogix_dp_clock_recovery_ok(link_status
, lane_count
)) {
587 analogix_dp_reduce_link_rate(dp
);
591 retval
= analogix_dp_read_bytes_from_dpcd(dp
,
592 DP_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
596 retval
= analogix_dp_read_byte_from_dpcd(dp
,
597 DP_LANE_ALIGN_STATUS_UPDATED
, &link_align
);
601 analogix_dp_get_adjust_training_lane(dp
, adjust_request
);
603 if (!analogix_dp_channel_eq_ok(link_status
, link_align
, lane_count
)) {
604 /* traing pattern Set to Normal */
605 analogix_dp_training_pattern_dis(dp
);
607 dev_info(dp
->dev
, "Link Training success!\n");
609 analogix_dp_get_link_bandwidth(dp
, ®
);
610 dp
->link_train
.link_rate
= reg
;
611 dev_dbg(dp
->dev
, "final bandwidth = %.2x\n",
612 dp
->link_train
.link_rate
);
614 analogix_dp_get_lane_count(dp
, ®
);
615 dp
->link_train
.lane_count
= reg
;
616 dev_dbg(dp
->dev
, "final lane count = %.2x\n",
617 dp
->link_train
.lane_count
);
619 /* set enhanced mode if available */
620 analogix_dp_set_enhanced_mode(dp
);
621 dp
->link_train
.lt_state
= FINISHED
;
627 dp
->link_train
.eq_loop
++;
629 if (dp
->link_train
.eq_loop
> MAX_EQ_LOOP
) {
630 dev_err(dp
->dev
, "EQ Max loop\n");
631 analogix_dp_reduce_link_rate(dp
);
635 for (lane
= 0; lane
< lane_count
; lane
++)
636 analogix_dp_set_lane_link_training(dp
,
637 dp
->link_train
.training_lane
[lane
], lane
);
639 retval
= analogix_dp_write_bytes_to_dpcd(dp
, DP_TRAINING_LANE0_SET
,
640 lane_count
, dp
->link_train
.training_lane
);
645 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device
*dp
,
651 * For DP rev.1.1, Maximum link rate of Main Link lanes
652 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
653 * For DP rev.1.2, Maximum link rate of Main Link lanes
654 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
656 analogix_dp_read_byte_from_dpcd(dp
, DP_MAX_LINK_RATE
, &data
);
660 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device
*dp
,
666 * For DP rev.1.1, Maximum number of Main Link lanes
667 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
669 analogix_dp_read_byte_from_dpcd(dp
, DP_MAX_LANE_COUNT
, &data
);
670 *lane_count
= DPCD_MAX_LANE_COUNT(data
);
673 static void analogix_dp_init_training(struct analogix_dp_device
*dp
,
674 enum link_lane_count_type max_lane
,
678 * MACRO_RST must be applied after the PLL_LOCK to avoid
679 * the DP inter pair skew issue for at least 10 us
681 analogix_dp_reset_macro(dp
);
683 /* Initialize by reading RX's DPCD */
684 analogix_dp_get_max_rx_bandwidth(dp
, &dp
->link_train
.link_rate
);
685 analogix_dp_get_max_rx_lane_count(dp
, &dp
->link_train
.lane_count
);
687 if ((dp
->link_train
.link_rate
!= DP_LINK_BW_1_62
) &&
688 (dp
->link_train
.link_rate
!= DP_LINK_BW_2_7
) &&
689 (dp
->link_train
.link_rate
!= DP_LINK_BW_5_4
)) {
690 dev_err(dp
->dev
, "Rx Max Link Rate is abnormal :%x !\n",
691 dp
->link_train
.link_rate
);
692 dp
->link_train
.link_rate
= DP_LINK_BW_1_62
;
695 if (dp
->link_train
.lane_count
== 0) {
696 dev_err(dp
->dev
, "Rx Max Lane count is abnormal :%x !\n",
697 dp
->link_train
.lane_count
);
698 dp
->link_train
.lane_count
= (u8
)LANE_COUNT1
;
701 /* Setup TX lane count & rate */
702 if (dp
->link_train
.lane_count
> max_lane
)
703 dp
->link_train
.lane_count
= max_lane
;
704 if (dp
->link_train
.link_rate
> max_rate
)
705 dp
->link_train
.link_rate
= max_rate
;
707 /* All DP analog module power up */
708 analogix_dp_set_analog_power_down(dp
, POWER_ALL
, 0);
711 static int analogix_dp_sw_link_training(struct analogix_dp_device
*dp
)
713 int retval
= 0, training_finished
= 0;
715 dp
->link_train
.lt_state
= START
;
718 while (!retval
&& !training_finished
) {
719 switch (dp
->link_train
.lt_state
) {
721 retval
= analogix_dp_link_start(dp
);
723 dev_err(dp
->dev
, "LT link start failed!\n");
726 retval
= analogix_dp_process_clock_recovery(dp
);
728 dev_err(dp
->dev
, "LT CR failed!\n");
730 case EQUALIZER_TRAINING
:
731 retval
= analogix_dp_process_equalizer_training(dp
);
733 dev_err(dp
->dev
, "LT EQ failed!\n");
736 training_finished
= 1;
743 dev_err(dp
->dev
, "eDP link training failed (%d)\n", retval
);
748 static int analogix_dp_set_link_train(struct analogix_dp_device
*dp
,
749 u32 count
, u32 bwtype
)
754 for (i
= 0; i
< DP_TIMEOUT_LOOP_COUNT
; i
++) {
755 analogix_dp_init_training(dp
, count
, bwtype
);
756 retval
= analogix_dp_sw_link_training(dp
);
760 usleep_range(100, 110);
766 static int analogix_dp_config_video(struct analogix_dp_device
*dp
)
769 int timeout_loop
= 0;
772 analogix_dp_config_video_slave_mode(dp
);
774 analogix_dp_set_video_color_format(dp
);
776 if (analogix_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
777 dev_err(dp
->dev
, "PLL is not locked yet.\n");
783 if (analogix_dp_is_slave_video_stream_clock_on(dp
) == 0)
785 if (timeout_loop
> DP_TIMEOUT_LOOP_COUNT
) {
786 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
793 /* Set to use the register calculated M/N video */
794 analogix_dp_set_video_cr_mn(dp
, CALCULATED_M
, 0, 0);
796 /* For video bist, Video timing must be generated by register */
797 analogix_dp_set_video_timing_mode(dp
, VIDEO_TIMING_FROM_CAPTURE
);
799 /* Disable video mute */
800 analogix_dp_enable_video_mute(dp
, 0);
802 /* Configure video slave mode */
803 analogix_dp_enable_video_master(dp
, 0);
809 if (analogix_dp_is_video_stream_on(dp
) == 0) {
813 } else if (done_count
) {
816 if (timeout_loop
> DP_TIMEOUT_LOOP_COUNT
) {
817 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
821 usleep_range(1000, 1001);
825 dev_err(dp
->dev
, "Video stream is not detected!\n");
830 static void analogix_dp_enable_scramble(struct analogix_dp_device
*dp
,
836 analogix_dp_enable_scrambling(dp
);
838 analogix_dp_read_byte_from_dpcd(dp
, DP_TRAINING_PATTERN_SET
,
840 analogix_dp_write_byte_to_dpcd(dp
,
841 DP_TRAINING_PATTERN_SET
,
842 (u8
)(data
& ~DP_LINK_SCRAMBLING_DISABLE
));
844 analogix_dp_disable_scrambling(dp
);
846 analogix_dp_read_byte_from_dpcd(dp
, DP_TRAINING_PATTERN_SET
,
848 analogix_dp_write_byte_to_dpcd(dp
,
849 DP_TRAINING_PATTERN_SET
,
850 (u8
)(data
| DP_LINK_SCRAMBLING_DISABLE
));
854 static irqreturn_t
analogix_dp_hardirq(int irq
, void *arg
)
856 struct analogix_dp_device
*dp
= arg
;
857 irqreturn_t ret
= IRQ_NONE
;
858 enum dp_irq_type irq_type
;
860 irq_type
= analogix_dp_get_irq_type(dp
);
861 if (irq_type
!= DP_IRQ_TYPE_UNKNOWN
) {
862 analogix_dp_mute_hpd_interrupt(dp
);
863 ret
= IRQ_WAKE_THREAD
;
869 static irqreturn_t
analogix_dp_irq_thread(int irq
, void *arg
)
871 struct analogix_dp_device
*dp
= arg
;
872 enum dp_irq_type irq_type
;
874 irq_type
= analogix_dp_get_irq_type(dp
);
875 if (irq_type
& DP_IRQ_TYPE_HP_CABLE_IN
||
876 irq_type
& DP_IRQ_TYPE_HP_CABLE_OUT
) {
877 dev_dbg(dp
->dev
, "Detected cable status changed!\n");
879 drm_helper_hpd_irq_event(dp
->drm_dev
);
882 if (irq_type
!= DP_IRQ_TYPE_UNKNOWN
) {
883 analogix_dp_clear_hotplug_interrupts(dp
);
884 analogix_dp_unmute_hpd_interrupt(dp
);
890 static void analogix_dp_commit(struct analogix_dp_device
*dp
)
894 /* Keep the panel disabled while we configure video */
895 if (dp
->plat_data
->panel
) {
896 if (drm_panel_disable(dp
->plat_data
->panel
))
897 DRM_ERROR("failed to disable the panel\n");
900 ret
= analogix_dp_set_link_train(dp
, dp
->video_info
.max_lane_count
,
901 dp
->video_info
.max_link_rate
);
903 dev_err(dp
->dev
, "unable to do link train\n");
907 analogix_dp_enable_scramble(dp
, 1);
908 analogix_dp_enable_rx_to_enhanced_mode(dp
, 1);
909 analogix_dp_enable_enhanced_mode(dp
, 1);
911 analogix_dp_init_video(dp
);
912 ret
= analogix_dp_config_video(dp
);
914 dev_err(dp
->dev
, "unable to config video\n");
916 /* Safe to enable the panel now */
917 if (dp
->plat_data
->panel
) {
918 if (drm_panel_enable(dp
->plat_data
->panel
))
919 DRM_ERROR("failed to enable the panel\n");
923 analogix_dp_start_video(dp
);
926 int analogix_dp_get_modes(struct drm_connector
*connector
)
928 struct analogix_dp_device
*dp
= to_dp(connector
);
929 struct edid
*edid
= (struct edid
*)dp
->edid
;
932 if (analogix_dp_handle_edid(dp
) == 0) {
933 drm_mode_connector_update_edid_property(&dp
->connector
, edid
);
934 num_modes
+= drm_add_edid_modes(&dp
->connector
, edid
);
937 if (dp
->plat_data
->panel
)
938 num_modes
+= drm_panel_get_modes(dp
->plat_data
->panel
);
940 if (dp
->plat_data
->get_modes
)
941 num_modes
+= dp
->plat_data
->get_modes(dp
->plat_data
, connector
);
946 static struct drm_encoder
*
947 analogix_dp_best_encoder(struct drm_connector
*connector
)
949 struct analogix_dp_device
*dp
= to_dp(connector
);
954 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs
= {
955 .get_modes
= analogix_dp_get_modes
,
956 .best_encoder
= analogix_dp_best_encoder
,
959 enum drm_connector_status
960 analogix_dp_detect(struct drm_connector
*connector
, bool force
)
962 struct analogix_dp_device
*dp
= to_dp(connector
);
964 if (analogix_dp_detect_hpd(dp
))
965 return connector_status_disconnected
;
967 return connector_status_connected
;
970 static void analogix_dp_connector_destroy(struct drm_connector
*connector
)
972 drm_connector_unregister(connector
);
973 drm_connector_cleanup(connector
);
977 static const struct drm_connector_funcs analogix_dp_connector_funcs
= {
978 .dpms
= drm_atomic_helper_connector_dpms
,
979 .fill_modes
= drm_helper_probe_single_connector_modes
,
980 .detect
= analogix_dp_detect
,
981 .destroy
= analogix_dp_connector_destroy
,
982 .reset
= drm_atomic_helper_connector_reset
,
983 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
984 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
987 static int analogix_dp_bridge_attach(struct drm_bridge
*bridge
)
989 struct analogix_dp_device
*dp
= bridge
->driver_private
;
990 struct drm_encoder
*encoder
= dp
->encoder
;
991 struct drm_connector
*connector
= &dp
->connector
;
994 if (!bridge
->encoder
) {
995 DRM_ERROR("Parent encoder object not found");
999 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1001 ret
= drm_connector_init(dp
->drm_dev
, connector
,
1002 &analogix_dp_connector_funcs
,
1003 DRM_MODE_CONNECTOR_eDP
);
1005 DRM_ERROR("Failed to initialize connector with drm\n");
1009 drm_connector_helper_add(connector
,
1010 &analogix_dp_connector_helper_funcs
);
1011 drm_mode_connector_attach_encoder(connector
, encoder
);
1014 * NOTE: the connector registration is implemented in analogix
1015 * platform driver, that to say connector would be exist after
1016 * plat_data->attch return, that's why we record the connector
1017 * point after plat attached.
1019 if (dp
->plat_data
->attach
) {
1020 ret
= dp
->plat_data
->attach(dp
->plat_data
, bridge
, connector
);
1022 DRM_ERROR("Failed at platform attch func\n");
1027 if (dp
->plat_data
->panel
) {
1028 ret
= drm_panel_attach(dp
->plat_data
->panel
, &dp
->connector
);
1030 DRM_ERROR("Failed to attach panel\n");
1038 static void analogix_dp_bridge_enable(struct drm_bridge
*bridge
)
1040 struct analogix_dp_device
*dp
= bridge
->driver_private
;
1042 if (dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1045 pm_runtime_get_sync(dp
->dev
);
1047 if (dp
->plat_data
->power_on
)
1048 dp
->plat_data
->power_on(dp
->plat_data
);
1050 phy_power_on(dp
->phy
);
1051 analogix_dp_init_dp(dp
);
1052 enable_irq(dp
->irq
);
1053 analogix_dp_commit(dp
);
1055 dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1058 static void analogix_dp_bridge_disable(struct drm_bridge
*bridge
)
1060 struct analogix_dp_device
*dp
= bridge
->driver_private
;
1062 if (dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1065 if (dp
->plat_data
->panel
) {
1066 if (drm_panel_disable(dp
->plat_data
->panel
)) {
1067 DRM_ERROR("failed to disable the panel\n");
1072 disable_irq(dp
->irq
);
1073 phy_power_off(dp
->phy
);
1075 if (dp
->plat_data
->power_off
)
1076 dp
->plat_data
->power_off(dp
->plat_data
);
1078 pm_runtime_put_sync(dp
->dev
);
1080 dp
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1083 static void analogix_dp_bridge_mode_set(struct drm_bridge
*bridge
,
1084 struct drm_display_mode
*orig_mode
,
1085 struct drm_display_mode
*mode
)
1087 struct analogix_dp_device
*dp
= bridge
->driver_private
;
1088 struct drm_display_info
*display_info
= &dp
->connector
.display_info
;
1089 struct video_info
*video
= &dp
->video_info
;
1090 struct device_node
*dp_node
= dp
->dev
->of_node
;
1093 /* Input video interlaces & hsync pol & vsync pol */
1094 video
->interlaced
= !!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
);
1095 video
->v_sync_polarity
= !!(mode
->flags
& DRM_MODE_FLAG_NVSYNC
);
1096 video
->h_sync_polarity
= !!(mode
->flags
& DRM_MODE_FLAG_NHSYNC
);
1098 /* Input video dynamic_range & colorimetry */
1099 vic
= drm_match_cea_mode(mode
);
1100 if ((vic
== 6) || (vic
== 7) || (vic
== 21) || (vic
== 22) ||
1101 (vic
== 2) || (vic
== 3) || (vic
== 17) || (vic
== 18)) {
1102 video
->dynamic_range
= CEA
;
1103 video
->ycbcr_coeff
= COLOR_YCBCR601
;
1105 video
->dynamic_range
= CEA
;
1106 video
->ycbcr_coeff
= COLOR_YCBCR709
;
1108 video
->dynamic_range
= VESA
;
1109 video
->ycbcr_coeff
= COLOR_YCBCR709
;
1112 /* Input vide bpc and color_formats */
1113 switch (display_info
->bpc
) {
1115 video
->color_depth
= COLOR_12
;
1118 video
->color_depth
= COLOR_10
;
1121 video
->color_depth
= COLOR_8
;
1124 video
->color_depth
= COLOR_6
;
1127 video
->color_depth
= COLOR_8
;
1130 if (display_info
->color_formats
& DRM_COLOR_FORMAT_YCRCB444
)
1131 video
->color_space
= COLOR_YCBCR444
;
1132 else if (display_info
->color_formats
& DRM_COLOR_FORMAT_YCRCB422
)
1133 video
->color_space
= COLOR_YCBCR422
;
1134 else if (display_info
->color_formats
& DRM_COLOR_FORMAT_RGB444
)
1135 video
->color_space
= COLOR_RGB
;
1137 video
->color_space
= COLOR_RGB
;
1140 * NOTE: those property parsing code is used for providing backward
1141 * compatibility for samsung platform.
1142 * Due to we used the "of_property_read_u32" interfaces, when this
1143 * property isn't present, the "video_info" can keep the original
1144 * values and wouldn't be modified.
1146 of_property_read_u32(dp_node
, "samsung,color-space",
1147 &video
->color_space
);
1148 of_property_read_u32(dp_node
, "samsung,dynamic-range",
1149 &video
->dynamic_range
);
1150 of_property_read_u32(dp_node
, "samsung,ycbcr-coeff",
1151 &video
->ycbcr_coeff
);
1152 of_property_read_u32(dp_node
, "samsung,color-depth",
1153 &video
->color_depth
);
1154 if (of_property_read_bool(dp_node
, "hsync-active-high"))
1155 video
->h_sync_polarity
= true;
1156 if (of_property_read_bool(dp_node
, "vsync-active-high"))
1157 video
->v_sync_polarity
= true;
1158 if (of_property_read_bool(dp_node
, "interlaced"))
1159 video
->interlaced
= true;
1162 static void analogix_dp_bridge_nop(struct drm_bridge
*bridge
)
1167 static const struct drm_bridge_funcs analogix_dp_bridge_funcs
= {
1168 .enable
= analogix_dp_bridge_enable
,
1169 .disable
= analogix_dp_bridge_disable
,
1170 .pre_enable
= analogix_dp_bridge_nop
,
1171 .post_disable
= analogix_dp_bridge_nop
,
1172 .mode_set
= analogix_dp_bridge_mode_set
,
1173 .attach
= analogix_dp_bridge_attach
,
1176 static int analogix_dp_create_bridge(struct drm_device
*drm_dev
,
1177 struct analogix_dp_device
*dp
)
1179 struct drm_bridge
*bridge
;
1182 bridge
= devm_kzalloc(drm_dev
->dev
, sizeof(*bridge
), GFP_KERNEL
);
1184 DRM_ERROR("failed to allocate for drm bridge\n");
1188 dp
->bridge
= bridge
;
1190 dp
->encoder
->bridge
= bridge
;
1191 bridge
->driver_private
= dp
;
1192 bridge
->encoder
= dp
->encoder
;
1193 bridge
->funcs
= &analogix_dp_bridge_funcs
;
1195 ret
= drm_bridge_attach(drm_dev
, bridge
);
1197 DRM_ERROR("failed to attach drm bridge\n");
1204 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device
*dp
)
1206 struct device_node
*dp_node
= dp
->dev
->of_node
;
1207 struct video_info
*video_info
= &dp
->video_info
;
1209 switch (dp
->plat_data
->dev_type
) {
1213 * Like Rk3288 DisplayPort TRM indicate that "Main link
1214 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1216 video_info
->max_link_rate
= 0x0A;
1217 video_info
->max_lane_count
= 0x04;
1221 * NOTE: those property parseing code is used for
1222 * providing backward compatibility for samsung platform.
1224 of_property_read_u32(dp_node
, "samsung,link-rate",
1225 &video_info
->max_link_rate
);
1226 of_property_read_u32(dp_node
, "samsung,lane-count",
1227 &video_info
->max_lane_count
);
1234 int analogix_dp_bind(struct device
*dev
, struct drm_device
*drm_dev
,
1235 struct analogix_dp_plat_data
*plat_data
)
1237 struct platform_device
*pdev
= to_platform_device(dev
);
1238 struct analogix_dp_device
*dp
;
1239 struct resource
*res
;
1240 unsigned int irq_flags
;
1244 dev_err(dev
, "Invalided input plat_data\n");
1248 dp
= devm_kzalloc(dev
, sizeof(struct analogix_dp_device
), GFP_KERNEL
);
1252 dev_set_drvdata(dev
, dp
);
1254 dp
->dev
= &pdev
->dev
;
1255 dp
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1258 * platform dp driver need containor_of the plat_data to get
1259 * the driver private data, so we need to store the point of
1260 * plat_data, not the context of plat_data.
1262 dp
->plat_data
= plat_data
;
1264 ret
= analogix_dp_dt_parse_pdata(dp
);
1268 dp
->phy
= devm_phy_get(dp
->dev
, "dp");
1269 if (IS_ERR(dp
->phy
)) {
1270 dev_err(dp
->dev
, "no DP phy configured\n");
1271 ret
= PTR_ERR(dp
->phy
);
1274 * phy itself is not enabled, so we can move forward
1275 * assigning NULL to phy pointer.
1277 if (ret
== -ENOSYS
|| ret
== -ENODEV
)
1284 dp
->clock
= devm_clk_get(&pdev
->dev
, "dp");
1285 if (IS_ERR(dp
->clock
)) {
1286 dev_err(&pdev
->dev
, "failed to get clock\n");
1287 return PTR_ERR(dp
->clock
);
1290 clk_prepare_enable(dp
->clock
);
1292 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1294 dp
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1295 if (IS_ERR(dp
->reg_base
))
1296 return PTR_ERR(dp
->reg_base
);
1298 dp
->force_hpd
= of_property_read_bool(dev
->of_node
, "force-hpd");
1300 dp
->hpd_gpio
= of_get_named_gpio(dev
->of_node
, "hpd-gpios", 0);
1301 if (!gpio_is_valid(dp
->hpd_gpio
))
1302 dp
->hpd_gpio
= of_get_named_gpio(dev
->of_node
,
1303 "samsung,hpd-gpio", 0);
1305 if (gpio_is_valid(dp
->hpd_gpio
)) {
1307 * Set up the hotplug GPIO from the device tree as an interrupt.
1308 * Simply specifying a different interrupt in the device tree
1309 * doesn't work since we handle hotplug rather differently when
1310 * using a GPIO. We also need the actual GPIO specifier so
1311 * that we can get the current state of the GPIO.
1313 ret
= devm_gpio_request_one(&pdev
->dev
, dp
->hpd_gpio
, GPIOF_IN
,
1316 dev_err(&pdev
->dev
, "failed to get hpd gpio\n");
1319 dp
->irq
= gpio_to_irq(dp
->hpd_gpio
);
1320 irq_flags
= IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
;
1322 dp
->hpd_gpio
= -ENODEV
;
1323 dp
->irq
= platform_get_irq(pdev
, 0);
1327 if (dp
->irq
== -ENXIO
) {
1328 dev_err(&pdev
->dev
, "failed to get irq\n");
1332 pm_runtime_enable(dev
);
1334 phy_power_on(dp
->phy
);
1336 if (dp
->plat_data
->panel
) {
1337 if (drm_panel_prepare(dp
->plat_data
->panel
)) {
1338 DRM_ERROR("failed to setup the panel\n");
1343 analogix_dp_init_dp(dp
);
1345 ret
= devm_request_threaded_irq(&pdev
->dev
, dp
->irq
,
1346 analogix_dp_hardirq
,
1347 analogix_dp_irq_thread
,
1348 irq_flags
, "analogix-dp", dp
);
1350 dev_err(&pdev
->dev
, "failed to request irq\n");
1351 goto err_disable_pm_runtime
;
1353 disable_irq(dp
->irq
);
1355 dp
->drm_dev
= drm_dev
;
1356 dp
->encoder
= dp
->plat_data
->encoder
;
1358 ret
= analogix_dp_create_bridge(drm_dev
, dp
);
1360 DRM_ERROR("failed to create bridge (%d)\n", ret
);
1361 drm_encoder_cleanup(dp
->encoder
);
1362 goto err_disable_pm_runtime
;
1367 err_disable_pm_runtime
:
1368 pm_runtime_disable(dev
);
1372 EXPORT_SYMBOL_GPL(analogix_dp_bind
);
1374 void analogix_dp_unbind(struct device
*dev
, struct device
*master
,
1377 struct analogix_dp_device
*dp
= dev_get_drvdata(dev
);
1379 analogix_dp_bridge_disable(dp
->bridge
);
1381 if (dp
->plat_data
->panel
) {
1382 if (drm_panel_unprepare(dp
->plat_data
->panel
))
1383 DRM_ERROR("failed to turnoff the panel\n");
1386 pm_runtime_disable(dev
);
1388 EXPORT_SYMBOL_GPL(analogix_dp_unbind
);
1391 int analogix_dp_suspend(struct device
*dev
)
1393 struct analogix_dp_device
*dp
= dev_get_drvdata(dev
);
1395 clk_disable_unprepare(dp
->clock
);
1397 if (dp
->plat_data
->panel
) {
1398 if (drm_panel_unprepare(dp
->plat_data
->panel
))
1399 DRM_ERROR("failed to turnoff the panel\n");
1404 EXPORT_SYMBOL_GPL(analogix_dp_suspend
);
1406 int analogix_dp_resume(struct device
*dev
)
1408 struct analogix_dp_device
*dp
= dev_get_drvdata(dev
);
1411 ret
= clk_prepare_enable(dp
->clock
);
1413 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret
);
1417 if (dp
->plat_data
->panel
) {
1418 if (drm_panel_prepare(dp
->plat_data
->panel
)) {
1419 DRM_ERROR("failed to setup the panel\n");
1426 EXPORT_SYMBOL_GPL(analogix_dp_resume
);
1429 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1430 MODULE_DESCRIPTION("Analogix DP Core Driver");
1431 MODULE_LICENSE("GPL v2");