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fb: adv7393: off by one in probe function
[deliverable/linux.git] / drivers / gpu / drm / bridge / analogix / analogix_dp_core.c
1 /*
2 * Analogix DP (Display Port) core interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/of.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/component.h>
23 #include <linux/phy/phy.h>
24
25 #include <drm/drmP.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_panel.h>
30
31 #include <drm/bridge/analogix_dp.h>
32
33 #include "analogix_dp_core.h"
34
35 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
36
37 struct bridge_init {
38 struct i2c_client *client;
39 struct device_node *node;
40 };
41
42 static void analogix_dp_init_dp(struct analogix_dp_device *dp)
43 {
44 analogix_dp_reset(dp);
45
46 analogix_dp_swreset(dp);
47
48 analogix_dp_init_analog_param(dp);
49 analogix_dp_init_interrupt(dp);
50
51 /* SW defined function Normal operation */
52 analogix_dp_enable_sw_function(dp);
53
54 analogix_dp_config_interrupt(dp);
55 analogix_dp_init_analog_func(dp);
56
57 analogix_dp_init_hpd(dp);
58 analogix_dp_init_aux(dp);
59 }
60
61 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
62 {
63 int timeout_loop = 0;
64
65 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
66 if (analogix_dp_get_plug_in_status(dp) == 0)
67 return 0;
68
69 timeout_loop++;
70 usleep_range(10, 11);
71 }
72
73 /*
74 * Some edp screen do not have hpd signal, so we can't just
75 * return failed when hpd plug in detect failed, DT property
76 * "force-hpd" would indicate whether driver need this.
77 */
78 if (!dp->force_hpd)
79 return -ETIMEDOUT;
80
81 /*
82 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
83 * will not work, so we need to give a force hpd action to
84 * set HPD_STATUS manually.
85 */
86 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
87
88 analogix_dp_force_hpd(dp);
89
90 if (analogix_dp_get_plug_in_status(dp) != 0) {
91 dev_err(dp->dev, "failed to get hpd plug in status\n");
92 return -EINVAL;
93 }
94
95 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
96
97 return 0;
98 }
99
100 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
101 {
102 int i;
103 unsigned char sum = 0;
104
105 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
106 sum = sum + edid_data[i];
107
108 return sum;
109 }
110
111 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
112 {
113 unsigned char *edid = dp->edid;
114 unsigned int extend_block = 0;
115 unsigned char sum;
116 unsigned char test_vector;
117 int retval;
118
119 /*
120 * EDID device address is 0x50.
121 * However, if necessary, you must have set upper address
122 * into E-EDID in I2C device, 0x30.
123 */
124
125 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
126 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
127 EDID_EXTENSION_FLAG,
128 &extend_block);
129 if (retval)
130 return retval;
131
132 if (extend_block > 0) {
133 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
134
135 /* Read EDID data */
136 retval = analogix_dp_read_bytes_from_i2c(dp,
137 I2C_EDID_DEVICE_ADDR,
138 EDID_HEADER_PATTERN,
139 EDID_BLOCK_LENGTH,
140 &edid[EDID_HEADER_PATTERN]);
141 if (retval != 0) {
142 dev_err(dp->dev, "EDID Read failed!\n");
143 return -EIO;
144 }
145 sum = analogix_dp_calc_edid_check_sum(edid);
146 if (sum != 0) {
147 dev_err(dp->dev, "EDID bad checksum!\n");
148 return -EIO;
149 }
150
151 /* Read additional EDID data */
152 retval = analogix_dp_read_bytes_from_i2c(dp,
153 I2C_EDID_DEVICE_ADDR,
154 EDID_BLOCK_LENGTH,
155 EDID_BLOCK_LENGTH,
156 &edid[EDID_BLOCK_LENGTH]);
157 if (retval != 0) {
158 dev_err(dp->dev, "EDID Read failed!\n");
159 return -EIO;
160 }
161 sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
162 if (sum != 0) {
163 dev_err(dp->dev, "EDID bad checksum!\n");
164 return -EIO;
165 }
166
167 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
168 &test_vector);
169 if (test_vector & DP_TEST_LINK_EDID_READ) {
170 analogix_dp_write_byte_to_dpcd(dp,
171 DP_TEST_EDID_CHECKSUM,
172 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
173 analogix_dp_write_byte_to_dpcd(dp,
174 DP_TEST_RESPONSE,
175 DP_TEST_EDID_CHECKSUM_WRITE);
176 }
177 } else {
178 dev_info(dp->dev, "EDID data does not include any extensions.\n");
179
180 /* Read EDID data */
181 retval = analogix_dp_read_bytes_from_i2c(dp,
182 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
183 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
184 if (retval != 0) {
185 dev_err(dp->dev, "EDID Read failed!\n");
186 return -EIO;
187 }
188 sum = analogix_dp_calc_edid_check_sum(edid);
189 if (sum != 0) {
190 dev_err(dp->dev, "EDID bad checksum!\n");
191 return -EIO;
192 }
193
194 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
195 &test_vector);
196 if (test_vector & DP_TEST_LINK_EDID_READ) {
197 analogix_dp_write_byte_to_dpcd(dp,
198 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
199 analogix_dp_write_byte_to_dpcd(dp,
200 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
201 }
202 }
203
204 dev_dbg(dp->dev, "EDID Read success!\n");
205 return 0;
206 }
207
208 static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
209 {
210 u8 buf[12];
211 int i;
212 int retval;
213
214 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
215 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
216 if (retval)
217 return retval;
218
219 /* Read EDID */
220 for (i = 0; i < 3; i++) {
221 retval = analogix_dp_read_edid(dp);
222 if (!retval)
223 break;
224 }
225
226 return retval;
227 }
228
229 static void
230 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
231 bool enable)
232 {
233 u8 data;
234
235 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
236
237 if (enable)
238 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
239 DP_LANE_COUNT_ENHANCED_FRAME_EN |
240 DPCD_LANE_COUNT_SET(data));
241 else
242 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
243 DPCD_LANE_COUNT_SET(data));
244 }
245
246 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
247 {
248 u8 data;
249 int retval;
250
251 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
252 retval = DPCD_ENHANCED_FRAME_CAP(data);
253
254 return retval;
255 }
256
257 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
258 {
259 u8 data;
260
261 data = analogix_dp_is_enhanced_mode_available(dp);
262 analogix_dp_enable_rx_to_enhanced_mode(dp, data);
263 analogix_dp_enable_enhanced_mode(dp, data);
264 }
265
266 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
267 {
268 analogix_dp_set_training_pattern(dp, DP_NONE);
269
270 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
271 DP_TRAINING_PATTERN_DISABLE);
272 }
273
274 static void
275 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
276 int pre_emphasis, int lane)
277 {
278 switch (lane) {
279 case 0:
280 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
281 break;
282 case 1:
283 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
284 break;
285
286 case 2:
287 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
288 break;
289
290 case 3:
291 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
292 break;
293 }
294 }
295
296 static int analogix_dp_link_start(struct analogix_dp_device *dp)
297 {
298 u8 buf[4];
299 int lane, lane_count, pll_tries, retval;
300
301 lane_count = dp->link_train.lane_count;
302
303 dp->link_train.lt_state = CLOCK_RECOVERY;
304 dp->link_train.eq_loop = 0;
305
306 for (lane = 0; lane < lane_count; lane++)
307 dp->link_train.cr_loop[lane] = 0;
308
309 /* Set link rate and count as you want to establish*/
310 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
311 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
312
313 /* Setup RX configuration */
314 buf[0] = dp->link_train.link_rate;
315 buf[1] = dp->link_train.lane_count;
316 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
317 if (retval)
318 return retval;
319
320 /* Set TX pre-emphasis to minimum */
321 for (lane = 0; lane < lane_count; lane++)
322 analogix_dp_set_lane_lane_pre_emphasis(dp,
323 PRE_EMPHASIS_LEVEL_0, lane);
324
325 /* Wait for PLL lock */
326 pll_tries = 0;
327 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
328 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
329 dev_err(dp->dev, "Wait for PLL lock timed out\n");
330 return -ETIMEDOUT;
331 }
332
333 pll_tries++;
334 usleep_range(90, 120);
335 }
336
337 /* Set training pattern 1 */
338 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
339
340 /* Set RX training pattern */
341 retval = analogix_dp_write_byte_to_dpcd(dp,
342 DP_TRAINING_PATTERN_SET,
343 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
344 if (retval)
345 return retval;
346
347 for (lane = 0; lane < lane_count; lane++)
348 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
349 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
350
351 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
352 lane_count, buf);
353
354 return retval;
355 }
356
357 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
358 {
359 int shift = (lane & 1) * 4;
360 u8 link_value = link_status[lane >> 1];
361
362 return (link_value >> shift) & 0xf;
363 }
364
365 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
366 {
367 int lane;
368 u8 lane_status;
369
370 for (lane = 0; lane < lane_count; lane++) {
371 lane_status = analogix_dp_get_lane_status(link_status, lane);
372 if ((lane_status & DP_LANE_CR_DONE) == 0)
373 return -EINVAL;
374 }
375 return 0;
376 }
377
378 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
379 int lane_count)
380 {
381 int lane;
382 u8 lane_status;
383
384 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
385 return -EINVAL;
386
387 for (lane = 0; lane < lane_count; lane++) {
388 lane_status = analogix_dp_get_lane_status(link_status, lane);
389 lane_status &= DP_CHANNEL_EQ_BITS;
390 if (lane_status != DP_CHANNEL_EQ_BITS)
391 return -EINVAL;
392 }
393
394 return 0;
395 }
396
397 static unsigned char
398 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
399 {
400 int shift = (lane & 1) * 4;
401 u8 link_value = adjust_request[lane >> 1];
402
403 return (link_value >> shift) & 0x3;
404 }
405
406 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
407 u8 adjust_request[2],
408 int lane)
409 {
410 int shift = (lane & 1) * 4;
411 u8 link_value = adjust_request[lane >> 1];
412
413 return ((link_value >> shift) & 0xc) >> 2;
414 }
415
416 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
417 u8 training_lane_set, int lane)
418 {
419 switch (lane) {
420 case 0:
421 analogix_dp_set_lane0_link_training(dp, training_lane_set);
422 break;
423 case 1:
424 analogix_dp_set_lane1_link_training(dp, training_lane_set);
425 break;
426
427 case 2:
428 analogix_dp_set_lane2_link_training(dp, training_lane_set);
429 break;
430
431 case 3:
432 analogix_dp_set_lane3_link_training(dp, training_lane_set);
433 break;
434 }
435 }
436
437 static unsigned int
438 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
439 int lane)
440 {
441 u32 reg;
442
443 switch (lane) {
444 case 0:
445 reg = analogix_dp_get_lane0_link_training(dp);
446 break;
447 case 1:
448 reg = analogix_dp_get_lane1_link_training(dp);
449 break;
450 case 2:
451 reg = analogix_dp_get_lane2_link_training(dp);
452 break;
453 case 3:
454 reg = analogix_dp_get_lane3_link_training(dp);
455 break;
456 default:
457 WARN_ON(1);
458 return 0;
459 }
460
461 return reg;
462 }
463
464 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
465 {
466 analogix_dp_training_pattern_dis(dp);
467 analogix_dp_set_enhanced_mode(dp);
468
469 dp->link_train.lt_state = FAILED;
470 }
471
472 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
473 u8 adjust_request[2])
474 {
475 int lane, lane_count;
476 u8 voltage_swing, pre_emphasis, training_lane;
477
478 lane_count = dp->link_train.lane_count;
479 for (lane = 0; lane < lane_count; lane++) {
480 voltage_swing = analogix_dp_get_adjust_request_voltage(
481 adjust_request, lane);
482 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
483 adjust_request, lane);
484 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
485 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
486
487 if (voltage_swing == VOLTAGE_LEVEL_3)
488 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
489 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
490 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
491
492 dp->link_train.training_lane[lane] = training_lane;
493 }
494 }
495
496 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
497 {
498 int lane, lane_count, retval;
499 u8 voltage_swing, pre_emphasis, training_lane;
500 u8 link_status[2], adjust_request[2];
501
502 usleep_range(100, 101);
503
504 lane_count = dp->link_train.lane_count;
505
506 retval = analogix_dp_read_bytes_from_dpcd(dp,
507 DP_LANE0_1_STATUS, 2, link_status);
508 if (retval)
509 return retval;
510
511 retval = analogix_dp_read_bytes_from_dpcd(dp,
512 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
513 if (retval)
514 return retval;
515
516 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
517 /* set training pattern 2 for EQ */
518 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
519
520 retval = analogix_dp_write_byte_to_dpcd(dp,
521 DP_TRAINING_PATTERN_SET,
522 DP_LINK_SCRAMBLING_DISABLE |
523 DP_TRAINING_PATTERN_2);
524 if (retval)
525 return retval;
526
527 dev_info(dp->dev, "Link Training Clock Recovery success\n");
528 dp->link_train.lt_state = EQUALIZER_TRAINING;
529 } else {
530 for (lane = 0; lane < lane_count; lane++) {
531 training_lane = analogix_dp_get_lane_link_training(
532 dp, lane);
533 voltage_swing = analogix_dp_get_adjust_request_voltage(
534 adjust_request, lane);
535 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
536 adjust_request, lane);
537
538 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
539 voltage_swing &&
540 DPCD_PRE_EMPHASIS_GET(training_lane) ==
541 pre_emphasis)
542 dp->link_train.cr_loop[lane]++;
543
544 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
545 voltage_swing == VOLTAGE_LEVEL_3 ||
546 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
547 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
548 dp->link_train.cr_loop[lane],
549 voltage_swing, pre_emphasis);
550 analogix_dp_reduce_link_rate(dp);
551 return -EIO;
552 }
553 }
554 }
555
556 analogix_dp_get_adjust_training_lane(dp, adjust_request);
557
558 for (lane = 0; lane < lane_count; lane++)
559 analogix_dp_set_lane_link_training(dp,
560 dp->link_train.training_lane[lane], lane);
561
562 retval = analogix_dp_write_bytes_to_dpcd(dp,
563 DP_TRAINING_LANE0_SET, lane_count,
564 dp->link_train.training_lane);
565 if (retval)
566 return retval;
567
568 return retval;
569 }
570
571 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
572 {
573 int lane, lane_count, retval;
574 u32 reg;
575 u8 link_align, link_status[2], adjust_request[2];
576
577 usleep_range(400, 401);
578
579 lane_count = dp->link_train.lane_count;
580
581 retval = analogix_dp_read_bytes_from_dpcd(dp,
582 DP_LANE0_1_STATUS, 2, link_status);
583 if (retval)
584 return retval;
585
586 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
587 analogix_dp_reduce_link_rate(dp);
588 return -EIO;
589 }
590
591 retval = analogix_dp_read_bytes_from_dpcd(dp,
592 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
593 if (retval)
594 return retval;
595
596 retval = analogix_dp_read_byte_from_dpcd(dp,
597 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
598 if (retval)
599 return retval;
600
601 analogix_dp_get_adjust_training_lane(dp, adjust_request);
602
603 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
604 /* traing pattern Set to Normal */
605 analogix_dp_training_pattern_dis(dp);
606
607 dev_info(dp->dev, "Link Training success!\n");
608
609 analogix_dp_get_link_bandwidth(dp, &reg);
610 dp->link_train.link_rate = reg;
611 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
612 dp->link_train.link_rate);
613
614 analogix_dp_get_lane_count(dp, &reg);
615 dp->link_train.lane_count = reg;
616 dev_dbg(dp->dev, "final lane count = %.2x\n",
617 dp->link_train.lane_count);
618
619 /* set enhanced mode if available */
620 analogix_dp_set_enhanced_mode(dp);
621 dp->link_train.lt_state = FINISHED;
622
623 return 0;
624 }
625
626 /* not all locked */
627 dp->link_train.eq_loop++;
628
629 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
630 dev_err(dp->dev, "EQ Max loop\n");
631 analogix_dp_reduce_link_rate(dp);
632 return -EIO;
633 }
634
635 for (lane = 0; lane < lane_count; lane++)
636 analogix_dp_set_lane_link_training(dp,
637 dp->link_train.training_lane[lane], lane);
638
639 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
640 lane_count, dp->link_train.training_lane);
641
642 return retval;
643 }
644
645 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
646 u8 *bandwidth)
647 {
648 u8 data;
649
650 /*
651 * For DP rev.1.1, Maximum link rate of Main Link lanes
652 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
653 * For DP rev.1.2, Maximum link rate of Main Link lanes
654 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
655 */
656 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
657 *bandwidth = data;
658 }
659
660 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
661 u8 *lane_count)
662 {
663 u8 data;
664
665 /*
666 * For DP rev.1.1, Maximum number of Main Link lanes
667 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
668 */
669 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
670 *lane_count = DPCD_MAX_LANE_COUNT(data);
671 }
672
673 static void analogix_dp_init_training(struct analogix_dp_device *dp,
674 enum link_lane_count_type max_lane,
675 int max_rate)
676 {
677 /*
678 * MACRO_RST must be applied after the PLL_LOCK to avoid
679 * the DP inter pair skew issue for at least 10 us
680 */
681 analogix_dp_reset_macro(dp);
682
683 /* Initialize by reading RX's DPCD */
684 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
685 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
686
687 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
688 (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
689 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
690 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
691 dp->link_train.link_rate);
692 dp->link_train.link_rate = DP_LINK_BW_1_62;
693 }
694
695 if (dp->link_train.lane_count == 0) {
696 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
697 dp->link_train.lane_count);
698 dp->link_train.lane_count = (u8)LANE_COUNT1;
699 }
700
701 /* Setup TX lane count & rate */
702 if (dp->link_train.lane_count > max_lane)
703 dp->link_train.lane_count = max_lane;
704 if (dp->link_train.link_rate > max_rate)
705 dp->link_train.link_rate = max_rate;
706
707 /* All DP analog module power up */
708 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
709 }
710
711 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
712 {
713 int retval = 0, training_finished = 0;
714
715 dp->link_train.lt_state = START;
716
717 /* Process here */
718 while (!retval && !training_finished) {
719 switch (dp->link_train.lt_state) {
720 case START:
721 retval = analogix_dp_link_start(dp);
722 if (retval)
723 dev_err(dp->dev, "LT link start failed!\n");
724 break;
725 case CLOCK_RECOVERY:
726 retval = analogix_dp_process_clock_recovery(dp);
727 if (retval)
728 dev_err(dp->dev, "LT CR failed!\n");
729 break;
730 case EQUALIZER_TRAINING:
731 retval = analogix_dp_process_equalizer_training(dp);
732 if (retval)
733 dev_err(dp->dev, "LT EQ failed!\n");
734 break;
735 case FINISHED:
736 training_finished = 1;
737 break;
738 case FAILED:
739 return -EREMOTEIO;
740 }
741 }
742 if (retval)
743 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
744
745 return retval;
746 }
747
748 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
749 u32 count, u32 bwtype)
750 {
751 int i;
752 int retval;
753
754 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
755 analogix_dp_init_training(dp, count, bwtype);
756 retval = analogix_dp_sw_link_training(dp);
757 if (retval == 0)
758 break;
759
760 usleep_range(100, 110);
761 }
762
763 return retval;
764 }
765
766 static int analogix_dp_config_video(struct analogix_dp_device *dp)
767 {
768 int retval = 0;
769 int timeout_loop = 0;
770 int done_count = 0;
771
772 analogix_dp_config_video_slave_mode(dp);
773
774 analogix_dp_set_video_color_format(dp);
775
776 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
777 dev_err(dp->dev, "PLL is not locked yet.\n");
778 return -EINVAL;
779 }
780
781 for (;;) {
782 timeout_loop++;
783 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
784 break;
785 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
786 dev_err(dp->dev, "Timeout of video streamclk ok\n");
787 return -ETIMEDOUT;
788 }
789
790 usleep_range(1, 2);
791 }
792
793 /* Set to use the register calculated M/N video */
794 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
795
796 /* For video bist, Video timing must be generated by register */
797 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
798
799 /* Disable video mute */
800 analogix_dp_enable_video_mute(dp, 0);
801
802 /* Configure video slave mode */
803 analogix_dp_enable_video_master(dp, 0);
804
805 timeout_loop = 0;
806
807 for (;;) {
808 timeout_loop++;
809 if (analogix_dp_is_video_stream_on(dp) == 0) {
810 done_count++;
811 if (done_count > 10)
812 break;
813 } else if (done_count) {
814 done_count = 0;
815 }
816 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
817 dev_err(dp->dev, "Timeout of video streamclk ok\n");
818 return -ETIMEDOUT;
819 }
820
821 usleep_range(1000, 1001);
822 }
823
824 if (retval != 0)
825 dev_err(dp->dev, "Video stream is not detected!\n");
826
827 return retval;
828 }
829
830 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
831 bool enable)
832 {
833 u8 data;
834
835 if (enable) {
836 analogix_dp_enable_scrambling(dp);
837
838 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
839 &data);
840 analogix_dp_write_byte_to_dpcd(dp,
841 DP_TRAINING_PATTERN_SET,
842 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
843 } else {
844 analogix_dp_disable_scrambling(dp);
845
846 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
847 &data);
848 analogix_dp_write_byte_to_dpcd(dp,
849 DP_TRAINING_PATTERN_SET,
850 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
851 }
852 }
853
854 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
855 {
856 struct analogix_dp_device *dp = arg;
857 irqreturn_t ret = IRQ_NONE;
858 enum dp_irq_type irq_type;
859
860 irq_type = analogix_dp_get_irq_type(dp);
861 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
862 analogix_dp_mute_hpd_interrupt(dp);
863 ret = IRQ_WAKE_THREAD;
864 }
865
866 return ret;
867 }
868
869 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
870 {
871 struct analogix_dp_device *dp = arg;
872 enum dp_irq_type irq_type;
873
874 irq_type = analogix_dp_get_irq_type(dp);
875 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
876 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
877 dev_dbg(dp->dev, "Detected cable status changed!\n");
878 if (dp->drm_dev)
879 drm_helper_hpd_irq_event(dp->drm_dev);
880 }
881
882 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
883 analogix_dp_clear_hotplug_interrupts(dp);
884 analogix_dp_unmute_hpd_interrupt(dp);
885 }
886
887 return IRQ_HANDLED;
888 }
889
890 static void analogix_dp_commit(struct analogix_dp_device *dp)
891 {
892 int ret;
893
894 /* Keep the panel disabled while we configure video */
895 if (dp->plat_data->panel) {
896 if (drm_panel_disable(dp->plat_data->panel))
897 DRM_ERROR("failed to disable the panel\n");
898 }
899
900 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
901 dp->video_info.max_link_rate);
902 if (ret) {
903 dev_err(dp->dev, "unable to do link train\n");
904 return;
905 }
906
907 analogix_dp_enable_scramble(dp, 1);
908 analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
909 analogix_dp_enable_enhanced_mode(dp, 1);
910
911 analogix_dp_init_video(dp);
912 ret = analogix_dp_config_video(dp);
913 if (ret)
914 dev_err(dp->dev, "unable to config video\n");
915
916 /* Safe to enable the panel now */
917 if (dp->plat_data->panel) {
918 if (drm_panel_enable(dp->plat_data->panel))
919 DRM_ERROR("failed to enable the panel\n");
920 }
921
922 /* Enable video */
923 analogix_dp_start_video(dp);
924 }
925
926 int analogix_dp_get_modes(struct drm_connector *connector)
927 {
928 struct analogix_dp_device *dp = to_dp(connector);
929 struct edid *edid = (struct edid *)dp->edid;
930 int num_modes = 0;
931
932 if (analogix_dp_handle_edid(dp) == 0) {
933 drm_mode_connector_update_edid_property(&dp->connector, edid);
934 num_modes += drm_add_edid_modes(&dp->connector, edid);
935 }
936
937 if (dp->plat_data->panel)
938 num_modes += drm_panel_get_modes(dp->plat_data->panel);
939
940 if (dp->plat_data->get_modes)
941 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
942
943 return num_modes;
944 }
945
946 static struct drm_encoder *
947 analogix_dp_best_encoder(struct drm_connector *connector)
948 {
949 struct analogix_dp_device *dp = to_dp(connector);
950
951 return dp->encoder;
952 }
953
954 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
955 .get_modes = analogix_dp_get_modes,
956 .best_encoder = analogix_dp_best_encoder,
957 };
958
959 enum drm_connector_status
960 analogix_dp_detect(struct drm_connector *connector, bool force)
961 {
962 struct analogix_dp_device *dp = to_dp(connector);
963
964 if (analogix_dp_detect_hpd(dp))
965 return connector_status_disconnected;
966
967 return connector_status_connected;
968 }
969
970 static void analogix_dp_connector_destroy(struct drm_connector *connector)
971 {
972 drm_connector_unregister(connector);
973 drm_connector_cleanup(connector);
974
975 }
976
977 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
978 .dpms = drm_atomic_helper_connector_dpms,
979 .fill_modes = drm_helper_probe_single_connector_modes,
980 .detect = analogix_dp_detect,
981 .destroy = analogix_dp_connector_destroy,
982 .reset = drm_atomic_helper_connector_reset,
983 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
984 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
985 };
986
987 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
988 {
989 struct analogix_dp_device *dp = bridge->driver_private;
990 struct drm_encoder *encoder = dp->encoder;
991 struct drm_connector *connector = &dp->connector;
992 int ret;
993
994 if (!bridge->encoder) {
995 DRM_ERROR("Parent encoder object not found");
996 return -ENODEV;
997 }
998
999 connector->polled = DRM_CONNECTOR_POLL_HPD;
1000
1001 ret = drm_connector_init(dp->drm_dev, connector,
1002 &analogix_dp_connector_funcs,
1003 DRM_MODE_CONNECTOR_eDP);
1004 if (ret) {
1005 DRM_ERROR("Failed to initialize connector with drm\n");
1006 return ret;
1007 }
1008
1009 drm_connector_helper_add(connector,
1010 &analogix_dp_connector_helper_funcs);
1011 drm_mode_connector_attach_encoder(connector, encoder);
1012
1013 /*
1014 * NOTE: the connector registration is implemented in analogix
1015 * platform driver, that to say connector would be exist after
1016 * plat_data->attch return, that's why we record the connector
1017 * point after plat attached.
1018 */
1019 if (dp->plat_data->attach) {
1020 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1021 if (ret) {
1022 DRM_ERROR("Failed at platform attch func\n");
1023 return ret;
1024 }
1025 }
1026
1027 if (dp->plat_data->panel) {
1028 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1029 if (ret) {
1030 DRM_ERROR("Failed to attach panel\n");
1031 return ret;
1032 }
1033 }
1034
1035 return 0;
1036 }
1037
1038 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1039 {
1040 struct analogix_dp_device *dp = bridge->driver_private;
1041
1042 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1043 return;
1044
1045 pm_runtime_get_sync(dp->dev);
1046
1047 if (dp->plat_data->power_on)
1048 dp->plat_data->power_on(dp->plat_data);
1049
1050 phy_power_on(dp->phy);
1051 analogix_dp_init_dp(dp);
1052 enable_irq(dp->irq);
1053 analogix_dp_commit(dp);
1054
1055 dp->dpms_mode = DRM_MODE_DPMS_ON;
1056 }
1057
1058 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1059 {
1060 struct analogix_dp_device *dp = bridge->driver_private;
1061
1062 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1063 return;
1064
1065 if (dp->plat_data->panel) {
1066 if (drm_panel_disable(dp->plat_data->panel)) {
1067 DRM_ERROR("failed to disable the panel\n");
1068 return;
1069 }
1070 }
1071
1072 disable_irq(dp->irq);
1073 phy_power_off(dp->phy);
1074
1075 if (dp->plat_data->power_off)
1076 dp->plat_data->power_off(dp->plat_data);
1077
1078 pm_runtime_put_sync(dp->dev);
1079
1080 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1081 }
1082
1083 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1084 struct drm_display_mode *orig_mode,
1085 struct drm_display_mode *mode)
1086 {
1087 struct analogix_dp_device *dp = bridge->driver_private;
1088 struct drm_display_info *display_info = &dp->connector.display_info;
1089 struct video_info *video = &dp->video_info;
1090 struct device_node *dp_node = dp->dev->of_node;
1091 int vic;
1092
1093 /* Input video interlaces & hsync pol & vsync pol */
1094 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1095 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1096 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1097
1098 /* Input video dynamic_range & colorimetry */
1099 vic = drm_match_cea_mode(mode);
1100 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1101 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1102 video->dynamic_range = CEA;
1103 video->ycbcr_coeff = COLOR_YCBCR601;
1104 } else if (vic) {
1105 video->dynamic_range = CEA;
1106 video->ycbcr_coeff = COLOR_YCBCR709;
1107 } else {
1108 video->dynamic_range = VESA;
1109 video->ycbcr_coeff = COLOR_YCBCR709;
1110 }
1111
1112 /* Input vide bpc and color_formats */
1113 switch (display_info->bpc) {
1114 case 12:
1115 video->color_depth = COLOR_12;
1116 break;
1117 case 10:
1118 video->color_depth = COLOR_10;
1119 break;
1120 case 8:
1121 video->color_depth = COLOR_8;
1122 break;
1123 case 6:
1124 video->color_depth = COLOR_6;
1125 break;
1126 default:
1127 video->color_depth = COLOR_8;
1128 break;
1129 }
1130 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1131 video->color_space = COLOR_YCBCR444;
1132 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1133 video->color_space = COLOR_YCBCR422;
1134 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1135 video->color_space = COLOR_RGB;
1136 else
1137 video->color_space = COLOR_RGB;
1138
1139 /*
1140 * NOTE: those property parsing code is used for providing backward
1141 * compatibility for samsung platform.
1142 * Due to we used the "of_property_read_u32" interfaces, when this
1143 * property isn't present, the "video_info" can keep the original
1144 * values and wouldn't be modified.
1145 */
1146 of_property_read_u32(dp_node, "samsung,color-space",
1147 &video->color_space);
1148 of_property_read_u32(dp_node, "samsung,dynamic-range",
1149 &video->dynamic_range);
1150 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1151 &video->ycbcr_coeff);
1152 of_property_read_u32(dp_node, "samsung,color-depth",
1153 &video->color_depth);
1154 if (of_property_read_bool(dp_node, "hsync-active-high"))
1155 video->h_sync_polarity = true;
1156 if (of_property_read_bool(dp_node, "vsync-active-high"))
1157 video->v_sync_polarity = true;
1158 if (of_property_read_bool(dp_node, "interlaced"))
1159 video->interlaced = true;
1160 }
1161
1162 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1163 {
1164 /* do nothing */
1165 }
1166
1167 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1168 .enable = analogix_dp_bridge_enable,
1169 .disable = analogix_dp_bridge_disable,
1170 .pre_enable = analogix_dp_bridge_nop,
1171 .post_disable = analogix_dp_bridge_nop,
1172 .mode_set = analogix_dp_bridge_mode_set,
1173 .attach = analogix_dp_bridge_attach,
1174 };
1175
1176 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1177 struct analogix_dp_device *dp)
1178 {
1179 struct drm_bridge *bridge;
1180 int ret;
1181
1182 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1183 if (!bridge) {
1184 DRM_ERROR("failed to allocate for drm bridge\n");
1185 return -ENOMEM;
1186 }
1187
1188 dp->bridge = bridge;
1189
1190 dp->encoder->bridge = bridge;
1191 bridge->driver_private = dp;
1192 bridge->encoder = dp->encoder;
1193 bridge->funcs = &analogix_dp_bridge_funcs;
1194
1195 ret = drm_bridge_attach(drm_dev, bridge);
1196 if (ret) {
1197 DRM_ERROR("failed to attach drm bridge\n");
1198 return -EINVAL;
1199 }
1200
1201 return 0;
1202 }
1203
1204 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1205 {
1206 struct device_node *dp_node = dp->dev->of_node;
1207 struct video_info *video_info = &dp->video_info;
1208
1209 switch (dp->plat_data->dev_type) {
1210 case RK3288_DP:
1211 case RK3399_EDP:
1212 /*
1213 * Like Rk3288 DisplayPort TRM indicate that "Main link
1214 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1215 */
1216 video_info->max_link_rate = 0x0A;
1217 video_info->max_lane_count = 0x04;
1218 break;
1219 case EXYNOS_DP:
1220 /*
1221 * NOTE: those property parseing code is used for
1222 * providing backward compatibility for samsung platform.
1223 */
1224 of_property_read_u32(dp_node, "samsung,link-rate",
1225 &video_info->max_link_rate);
1226 of_property_read_u32(dp_node, "samsung,lane-count",
1227 &video_info->max_lane_count);
1228 break;
1229 }
1230
1231 return 0;
1232 }
1233
1234 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1235 struct analogix_dp_plat_data *plat_data)
1236 {
1237 struct platform_device *pdev = to_platform_device(dev);
1238 struct analogix_dp_device *dp;
1239 struct resource *res;
1240 unsigned int irq_flags;
1241 int ret;
1242
1243 if (!plat_data) {
1244 dev_err(dev, "Invalided input plat_data\n");
1245 return -EINVAL;
1246 }
1247
1248 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1249 if (!dp)
1250 return -ENOMEM;
1251
1252 dev_set_drvdata(dev, dp);
1253
1254 dp->dev = &pdev->dev;
1255 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1256
1257 /*
1258 * platform dp driver need containor_of the plat_data to get
1259 * the driver private data, so we need to store the point of
1260 * plat_data, not the context of plat_data.
1261 */
1262 dp->plat_data = plat_data;
1263
1264 ret = analogix_dp_dt_parse_pdata(dp);
1265 if (ret)
1266 return ret;
1267
1268 dp->phy = devm_phy_get(dp->dev, "dp");
1269 if (IS_ERR(dp->phy)) {
1270 dev_err(dp->dev, "no DP phy configured\n");
1271 ret = PTR_ERR(dp->phy);
1272 if (ret) {
1273 /*
1274 * phy itself is not enabled, so we can move forward
1275 * assigning NULL to phy pointer.
1276 */
1277 if (ret == -ENOSYS || ret == -ENODEV)
1278 dp->phy = NULL;
1279 else
1280 return ret;
1281 }
1282 }
1283
1284 dp->clock = devm_clk_get(&pdev->dev, "dp");
1285 if (IS_ERR(dp->clock)) {
1286 dev_err(&pdev->dev, "failed to get clock\n");
1287 return PTR_ERR(dp->clock);
1288 }
1289
1290 clk_prepare_enable(dp->clock);
1291
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293
1294 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1295 if (IS_ERR(dp->reg_base))
1296 return PTR_ERR(dp->reg_base);
1297
1298 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1299
1300 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1301 if (!gpio_is_valid(dp->hpd_gpio))
1302 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1303 "samsung,hpd-gpio", 0);
1304
1305 if (gpio_is_valid(dp->hpd_gpio)) {
1306 /*
1307 * Set up the hotplug GPIO from the device tree as an interrupt.
1308 * Simply specifying a different interrupt in the device tree
1309 * doesn't work since we handle hotplug rather differently when
1310 * using a GPIO. We also need the actual GPIO specifier so
1311 * that we can get the current state of the GPIO.
1312 */
1313 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1314 "hpd_gpio");
1315 if (ret) {
1316 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1317 return ret;
1318 }
1319 dp->irq = gpio_to_irq(dp->hpd_gpio);
1320 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1321 } else {
1322 dp->hpd_gpio = -ENODEV;
1323 dp->irq = platform_get_irq(pdev, 0);
1324 irq_flags = 0;
1325 }
1326
1327 if (dp->irq == -ENXIO) {
1328 dev_err(&pdev->dev, "failed to get irq\n");
1329 return -ENODEV;
1330 }
1331
1332 pm_runtime_enable(dev);
1333
1334 phy_power_on(dp->phy);
1335
1336 if (dp->plat_data->panel) {
1337 if (drm_panel_prepare(dp->plat_data->panel)) {
1338 DRM_ERROR("failed to setup the panel\n");
1339 return -EBUSY;
1340 }
1341 }
1342
1343 analogix_dp_init_dp(dp);
1344
1345 ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1346 analogix_dp_hardirq,
1347 analogix_dp_irq_thread,
1348 irq_flags, "analogix-dp", dp);
1349 if (ret) {
1350 dev_err(&pdev->dev, "failed to request irq\n");
1351 goto err_disable_pm_runtime;
1352 }
1353 disable_irq(dp->irq);
1354
1355 dp->drm_dev = drm_dev;
1356 dp->encoder = dp->plat_data->encoder;
1357
1358 ret = analogix_dp_create_bridge(drm_dev, dp);
1359 if (ret) {
1360 DRM_ERROR("failed to create bridge (%d)\n", ret);
1361 drm_encoder_cleanup(dp->encoder);
1362 goto err_disable_pm_runtime;
1363 }
1364
1365 return 0;
1366
1367 err_disable_pm_runtime:
1368 pm_runtime_disable(dev);
1369
1370 return ret;
1371 }
1372 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1373
1374 void analogix_dp_unbind(struct device *dev, struct device *master,
1375 void *data)
1376 {
1377 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1378
1379 analogix_dp_bridge_disable(dp->bridge);
1380
1381 if (dp->plat_data->panel) {
1382 if (drm_panel_unprepare(dp->plat_data->panel))
1383 DRM_ERROR("failed to turnoff the panel\n");
1384 }
1385
1386 pm_runtime_disable(dev);
1387 }
1388 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1389
1390 #ifdef CONFIG_PM
1391 int analogix_dp_suspend(struct device *dev)
1392 {
1393 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1394
1395 clk_disable_unprepare(dp->clock);
1396
1397 if (dp->plat_data->panel) {
1398 if (drm_panel_unprepare(dp->plat_data->panel))
1399 DRM_ERROR("failed to turnoff the panel\n");
1400 }
1401
1402 return 0;
1403 }
1404 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1405
1406 int analogix_dp_resume(struct device *dev)
1407 {
1408 struct analogix_dp_device *dp = dev_get_drvdata(dev);
1409 int ret;
1410
1411 ret = clk_prepare_enable(dp->clock);
1412 if (ret < 0) {
1413 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1414 return ret;
1415 }
1416
1417 if (dp->plat_data->panel) {
1418 if (drm_panel_prepare(dp->plat_data->panel)) {
1419 DRM_ERROR("failed to setup the panel\n");
1420 return -EBUSY;
1421 }
1422 }
1423
1424 return 0;
1425 }
1426 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1427 #endif
1428
1429 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1430 MODULE_DESCRIPTION("Analogix DP Core Driver");
1431 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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