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Merge remote-tracking branch 'xen-tip/linux-next'
[deliverable/linux.git] / drivers / gpu / drm / bridge / analogix / analogix_dp_reg.c
1 /*
2 * Analogix DP (Display port) core register interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17
18 #include <drm/bridge/analogix_dp.h>
19
20 #include "analogix_dp_core.h"
21 #include "analogix_dp_reg.h"
22
23 #define COMMON_INT_MASK_1 0
24 #define COMMON_INT_MASK_2 0
25 #define COMMON_INT_MASK_3 0
26 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
27 #define INT_STA_MASK INT_HPD
28
29 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
30 {
31 u32 reg;
32
33 if (enable) {
34 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
35 reg |= HDCP_VIDEO_MUTE;
36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
37 } else {
38 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
39 reg &= ~HDCP_VIDEO_MUTE;
40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
41 }
42 }
43
44 void analogix_dp_stop_video(struct analogix_dp_device *dp)
45 {
46 u32 reg;
47
48 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
49 reg &= ~VIDEO_EN;
50 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
51 }
52
53 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
54 {
55 u32 reg;
56
57 if (enable)
58 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
59 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
60 else
61 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
62 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
63
64 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
65 }
66
67 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
68 {
69 u32 reg;
70
71 reg = TX_TERMINAL_CTRL_50_OHM;
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
73
74 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
75 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
76
77 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
78 reg = REF_CLK_24M;
79 if (dp->plat_data->dev_type == RK3288_DP)
80 reg ^= REF_CLK_MASK;
81
82 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
83 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
84 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
85 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
86 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
87 }
88
89 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
90 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
91
92 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
93 TX_CUR1_2X | TX_CUR_16_MA;
94 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
95
96 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
97 CH1_AMP_400_MV | CH0_AMP_400_MV;
98 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
99 }
100
101 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
102 {
103 /* Set interrupt pin assertion polarity as high */
104 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
105
106 /* Clear pending regisers */
107 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
108 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
109 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
110 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
111 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
112
113 /* 0:mask,1: unmask */
114 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
115 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
116 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
117 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
118 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
119 }
120
121 void analogix_dp_reset(struct analogix_dp_device *dp)
122 {
123 u32 reg;
124
125 analogix_dp_stop_video(dp);
126 analogix_dp_enable_video_mute(dp, 0);
127
128 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
129 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
130 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
131 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
132
133 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
134 SERDES_FIFO_FUNC_EN_N |
135 LS_CLK_DOMAIN_FUNC_EN_N;
136 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
137
138 usleep_range(20, 30);
139
140 analogix_dp_lane_swap(dp, 0);
141
142 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
143 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
144 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
145 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
146
147 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
148 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
149
150 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
151 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
152
153 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
154
155 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
156
157 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
158 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
159
160 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
161 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
162
163 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
164 }
165
166 void analogix_dp_swreset(struct analogix_dp_device *dp)
167 {
168 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
169 }
170
171 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
172 {
173 u32 reg;
174
175 /* 0: mask, 1: unmask */
176 reg = COMMON_INT_MASK_1;
177 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
178
179 reg = COMMON_INT_MASK_2;
180 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
181
182 reg = COMMON_INT_MASK_3;
183 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
184
185 reg = COMMON_INT_MASK_4;
186 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
187
188 reg = INT_STA_MASK;
189 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
190 }
191
192 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
193 {
194 u32 reg;
195
196 /* 0: mask, 1: unmask */
197 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
198 reg &= ~COMMON_INT_MASK_4;
199 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
200
201 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
202 reg &= ~INT_STA_MASK;
203 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
204 }
205
206 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
207 {
208 u32 reg;
209
210 /* 0: mask, 1: unmask */
211 reg = COMMON_INT_MASK_4;
212 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
213
214 reg = INT_STA_MASK;
215 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
216 }
217
218 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
219 {
220 u32 reg;
221
222 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
223 if (reg & PLL_LOCK)
224 return PLL_LOCKED;
225 else
226 return PLL_UNLOCKED;
227 }
228
229 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
230 {
231 u32 reg;
232
233 if (enable) {
234 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
235 reg |= DP_PLL_PD;
236 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
237 } else {
238 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
239 reg &= ~DP_PLL_PD;
240 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
241 }
242 }
243
244 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
245 enum analog_power_block block,
246 bool enable)
247 {
248 u32 reg;
249 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
250
251 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
252 phy_pd_addr = ANALOGIX_DP_PD;
253
254 switch (block) {
255 case AUX_BLOCK:
256 if (enable) {
257 reg = readl(dp->reg_base + phy_pd_addr);
258 reg |= AUX_PD;
259 writel(reg, dp->reg_base + phy_pd_addr);
260 } else {
261 reg = readl(dp->reg_base + phy_pd_addr);
262 reg &= ~AUX_PD;
263 writel(reg, dp->reg_base + phy_pd_addr);
264 }
265 break;
266 case CH0_BLOCK:
267 if (enable) {
268 reg = readl(dp->reg_base + phy_pd_addr);
269 reg |= CH0_PD;
270 writel(reg, dp->reg_base + phy_pd_addr);
271 } else {
272 reg = readl(dp->reg_base + phy_pd_addr);
273 reg &= ~CH0_PD;
274 writel(reg, dp->reg_base + phy_pd_addr);
275 }
276 break;
277 case CH1_BLOCK:
278 if (enable) {
279 reg = readl(dp->reg_base + phy_pd_addr);
280 reg |= CH1_PD;
281 writel(reg, dp->reg_base + phy_pd_addr);
282 } else {
283 reg = readl(dp->reg_base + phy_pd_addr);
284 reg &= ~CH1_PD;
285 writel(reg, dp->reg_base + phy_pd_addr);
286 }
287 break;
288 case CH2_BLOCK:
289 if (enable) {
290 reg = readl(dp->reg_base + phy_pd_addr);
291 reg |= CH2_PD;
292 writel(reg, dp->reg_base + phy_pd_addr);
293 } else {
294 reg = readl(dp->reg_base + phy_pd_addr);
295 reg &= ~CH2_PD;
296 writel(reg, dp->reg_base + phy_pd_addr);
297 }
298 break;
299 case CH3_BLOCK:
300 if (enable) {
301 reg = readl(dp->reg_base + phy_pd_addr);
302 reg |= CH3_PD;
303 writel(reg, dp->reg_base + phy_pd_addr);
304 } else {
305 reg = readl(dp->reg_base + phy_pd_addr);
306 reg &= ~CH3_PD;
307 writel(reg, dp->reg_base + phy_pd_addr);
308 }
309 break;
310 case ANALOG_TOTAL:
311 if (enable) {
312 reg = readl(dp->reg_base + phy_pd_addr);
313 reg |= DP_PHY_PD;
314 writel(reg, dp->reg_base + phy_pd_addr);
315 } else {
316 reg = readl(dp->reg_base + phy_pd_addr);
317 reg &= ~DP_PHY_PD;
318 writel(reg, dp->reg_base + phy_pd_addr);
319 }
320 break;
321 case POWER_ALL:
322 if (enable) {
323 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
324 CH1_PD | CH0_PD;
325 writel(reg, dp->reg_base + phy_pd_addr);
326 } else {
327 writel(0x00, dp->reg_base + phy_pd_addr);
328 }
329 break;
330 default:
331 break;
332 }
333 }
334
335 void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
336 {
337 u32 reg;
338 int timeout_loop = 0;
339
340 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
341
342 reg = PLL_LOCK_CHG;
343 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
344
345 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
346 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
347 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
348
349 /* Power up PLL */
350 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
351 analogix_dp_set_pll_power_down(dp, 0);
352
353 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
354 timeout_loop++;
355 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
356 dev_err(dp->dev, "failed to get pll lock status\n");
357 return;
358 }
359 usleep_range(10, 20);
360 }
361 }
362
363 /* Enable Serdes FIFO function and Link symbol clock domain module */
364 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
365 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
366 | AUX_FUNC_EN_N);
367 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
368 }
369
370 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
371 {
372 u32 reg;
373
374 if (gpio_is_valid(dp->hpd_gpio))
375 return;
376
377 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
378 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
379
380 reg = INT_HPD;
381 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
382 }
383
384 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
385 {
386 u32 reg;
387
388 if (gpio_is_valid(dp->hpd_gpio))
389 return;
390
391 analogix_dp_clear_hotplug_interrupts(dp);
392
393 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
394 reg &= ~(F_HPD | HPD_CTRL);
395 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
396 }
397
398 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
399 {
400 u32 reg;
401
402 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
403 reg = (F_HPD | HPD_CTRL);
404 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
405 }
406
407 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
408 {
409 u32 reg;
410
411 if (gpio_is_valid(dp->hpd_gpio)) {
412 reg = gpio_get_value(dp->hpd_gpio);
413 if (reg)
414 return DP_IRQ_TYPE_HP_CABLE_IN;
415 else
416 return DP_IRQ_TYPE_HP_CABLE_OUT;
417 } else {
418 /* Parse hotplug interrupt status register */
419 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
420
421 if (reg & PLUG)
422 return DP_IRQ_TYPE_HP_CABLE_IN;
423
424 if (reg & HPD_LOST)
425 return DP_IRQ_TYPE_HP_CABLE_OUT;
426
427 if (reg & HOTPLUG_CHG)
428 return DP_IRQ_TYPE_HP_CHANGE;
429
430 return DP_IRQ_TYPE_UNKNOWN;
431 }
432 }
433
434 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
435 {
436 u32 reg;
437
438 /* Disable AUX channel module */
439 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
440 reg |= AUX_FUNC_EN_N;
441 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
442 }
443
444 void analogix_dp_init_aux(struct analogix_dp_device *dp)
445 {
446 u32 reg;
447
448 /* Clear inerrupts related to AUX channel */
449 reg = RPLY_RECEIV | AUX_ERR;
450 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
451
452 analogix_dp_reset_aux(dp);
453
454 /* Disable AUX transaction H/W retry */
455 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
456 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
457 AUX_HW_RETRY_COUNT_SEL(3) |
458 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
459 else
460 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
461 AUX_HW_RETRY_COUNT_SEL(0) |
462 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
463 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
464
465 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
466 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
467 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
468
469 /* Enable AUX channel module */
470 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
471 reg &= ~AUX_FUNC_EN_N;
472 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
473 }
474
475 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
476 {
477 u32 reg;
478
479 if (gpio_is_valid(dp->hpd_gpio)) {
480 if (gpio_get_value(dp->hpd_gpio))
481 return 0;
482 } else {
483 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
484 if (reg & HPD_STATUS)
485 return 0;
486 }
487
488 return -EINVAL;
489 }
490
491 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
492 {
493 u32 reg;
494
495 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
496 reg &= ~SW_FUNC_EN_N;
497 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
498 }
499
500 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
501 {
502 int reg;
503 int retval = 0;
504 int timeout_loop = 0;
505
506 /* Enable AUX CH operation */
507 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
508 reg |= AUX_EN;
509 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
510
511 /* Is AUX CH command reply received? */
512 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
513 while (!(reg & RPLY_RECEIV)) {
514 timeout_loop++;
515 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
516 dev_err(dp->dev, "AUX CH command reply failed!\n");
517 return -ETIMEDOUT;
518 }
519 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
520 usleep_range(10, 11);
521 }
522
523 /* Clear interrupt source for AUX CH command reply */
524 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
525
526 /* Clear interrupt source for AUX CH access error */
527 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
528 if (reg & AUX_ERR) {
529 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
530 return -EREMOTEIO;
531 }
532
533 /* Check AUX CH error access status */
534 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
535 if ((reg & AUX_STATUS_MASK) != 0) {
536 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
537 reg & AUX_STATUS_MASK);
538 return -EREMOTEIO;
539 }
540
541 return retval;
542 }
543
544 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
545 unsigned int reg_addr,
546 unsigned char data)
547 {
548 u32 reg;
549 int i;
550 int retval;
551
552 for (i = 0; i < 3; i++) {
553 /* Clear AUX CH data buffer */
554 reg = BUF_CLR;
555 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
556
557 /* Select DPCD device address */
558 reg = AUX_ADDR_7_0(reg_addr);
559 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
560 reg = AUX_ADDR_15_8(reg_addr);
561 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
562 reg = AUX_ADDR_19_16(reg_addr);
563 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
564
565 /* Write data buffer */
566 reg = (unsigned int)data;
567 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
568
569 /*
570 * Set DisplayPort transaction and write 1 byte
571 * If bit 3 is 1, DisplayPort transaction.
572 * If Bit 3 is 0, I2C transaction.
573 */
574 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
575 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
576
577 /* Start AUX transaction */
578 retval = analogix_dp_start_aux_transaction(dp);
579 if (retval == 0)
580 break;
581
582 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
583 }
584
585 return retval;
586 }
587
588 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
589 unsigned int reg_addr,
590 unsigned char *data)
591 {
592 u32 reg;
593 int i;
594 int retval;
595
596 for (i = 0; i < 3; i++) {
597 /* Clear AUX CH data buffer */
598 reg = BUF_CLR;
599 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
600
601 /* Select DPCD device address */
602 reg = AUX_ADDR_7_0(reg_addr);
603 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
604 reg = AUX_ADDR_15_8(reg_addr);
605 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
606 reg = AUX_ADDR_19_16(reg_addr);
607 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
608
609 /*
610 * Set DisplayPort transaction and read 1 byte
611 * If bit 3 is 1, DisplayPort transaction.
612 * If Bit 3 is 0, I2C transaction.
613 */
614 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
615 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
616
617 /* Start AUX transaction */
618 retval = analogix_dp_start_aux_transaction(dp);
619 if (retval == 0)
620 break;
621
622 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
623 }
624
625 /* Read data buffer */
626 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
627 *data = (unsigned char)(reg & 0xff);
628
629 return retval;
630 }
631
632 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
633 unsigned int reg_addr,
634 unsigned int count,
635 unsigned char data[])
636 {
637 u32 reg;
638 unsigned int start_offset;
639 unsigned int cur_data_count;
640 unsigned int cur_data_idx;
641 int i;
642 int retval = 0;
643
644 /* Clear AUX CH data buffer */
645 reg = BUF_CLR;
646 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
647
648 start_offset = 0;
649 while (start_offset < count) {
650 /* Buffer size of AUX CH is 16 * 4bytes */
651 if ((count - start_offset) > 16)
652 cur_data_count = 16;
653 else
654 cur_data_count = count - start_offset;
655
656 for (i = 0; i < 3; i++) {
657 /* Select DPCD device address */
658 reg = AUX_ADDR_7_0(reg_addr + start_offset);
659 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
660 reg = AUX_ADDR_15_8(reg_addr + start_offset);
661 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
662 reg = AUX_ADDR_19_16(reg_addr + start_offset);
663 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
664
665 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
666 cur_data_idx++) {
667 reg = data[start_offset + cur_data_idx];
668 writel(reg, dp->reg_base +
669 ANALOGIX_DP_BUF_DATA_0 +
670 4 * cur_data_idx);
671 }
672
673 /*
674 * Set DisplayPort transaction and write
675 * If bit 3 is 1, DisplayPort transaction.
676 * If Bit 3 is 0, I2C transaction.
677 */
678 reg = AUX_LENGTH(cur_data_count) |
679 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
680 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
681
682 /* Start AUX transaction */
683 retval = analogix_dp_start_aux_transaction(dp);
684 if (retval == 0)
685 break;
686
687 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
688 __func__);
689 }
690
691 start_offset += cur_data_count;
692 }
693
694 return retval;
695 }
696
697 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
698 unsigned int reg_addr,
699 unsigned int count,
700 unsigned char data[])
701 {
702 u32 reg;
703 unsigned int start_offset;
704 unsigned int cur_data_count;
705 unsigned int cur_data_idx;
706 int i;
707 int retval = 0;
708
709 /* Clear AUX CH data buffer */
710 reg = BUF_CLR;
711 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
712
713 start_offset = 0;
714 while (start_offset < count) {
715 /* Buffer size of AUX CH is 16 * 4bytes */
716 if ((count - start_offset) > 16)
717 cur_data_count = 16;
718 else
719 cur_data_count = count - start_offset;
720
721 /* AUX CH Request Transaction process */
722 for (i = 0; i < 3; i++) {
723 /* Select DPCD device address */
724 reg = AUX_ADDR_7_0(reg_addr + start_offset);
725 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
726 reg = AUX_ADDR_15_8(reg_addr + start_offset);
727 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
728 reg = AUX_ADDR_19_16(reg_addr + start_offset);
729 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
730
731 /*
732 * Set DisplayPort transaction and read
733 * If bit 3 is 1, DisplayPort transaction.
734 * If Bit 3 is 0, I2C transaction.
735 */
736 reg = AUX_LENGTH(cur_data_count) |
737 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
738 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
739
740 /* Start AUX transaction */
741 retval = analogix_dp_start_aux_transaction(dp);
742 if (retval == 0)
743 break;
744
745 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
746 __func__);
747 }
748
749 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
750 cur_data_idx++) {
751 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
752 + 4 * cur_data_idx);
753 data[start_offset + cur_data_idx] =
754 (unsigned char)reg;
755 }
756
757 start_offset += cur_data_count;
758 }
759
760 return retval;
761 }
762
763 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
764 unsigned int device_addr,
765 unsigned int reg_addr)
766 {
767 u32 reg;
768 int retval;
769
770 /* Set EDID device address */
771 reg = device_addr;
772 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
773 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
774 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
775
776 /* Set offset from base address of EDID device */
777 writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
778
779 /*
780 * Set I2C transaction and write address
781 * If bit 3 is 1, DisplayPort transaction.
782 * If Bit 3 is 0, I2C transaction.
783 */
784 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
785 AUX_TX_COMM_WRITE;
786 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
787
788 /* Start AUX transaction */
789 retval = analogix_dp_start_aux_transaction(dp);
790 if (retval != 0)
791 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
792
793 return retval;
794 }
795
796 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
797 unsigned int device_addr,
798 unsigned int reg_addr,
799 unsigned int *data)
800 {
801 u32 reg;
802 int i;
803 int retval;
804
805 for (i = 0; i < 3; i++) {
806 /* Clear AUX CH data buffer */
807 reg = BUF_CLR;
808 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
809
810 /* Select EDID device */
811 retval = analogix_dp_select_i2c_device(dp, device_addr,
812 reg_addr);
813 if (retval != 0)
814 continue;
815
816 /*
817 * Set I2C transaction and read data
818 * If bit 3 is 1, DisplayPort transaction.
819 * If Bit 3 is 0, I2C transaction.
820 */
821 reg = AUX_TX_COMM_I2C_TRANSACTION |
822 AUX_TX_COMM_READ;
823 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
824
825 /* Start AUX transaction */
826 retval = analogix_dp_start_aux_transaction(dp);
827 if (retval == 0)
828 break;
829
830 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
831 }
832
833 /* Read data */
834 if (retval == 0)
835 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
836
837 return retval;
838 }
839
840 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
841 unsigned int device_addr,
842 unsigned int reg_addr,
843 unsigned int count,
844 unsigned char edid[])
845 {
846 u32 reg;
847 unsigned int i, j;
848 unsigned int cur_data_idx;
849 unsigned int defer = 0;
850 int retval = 0;
851
852 for (i = 0; i < count; i += 16) {
853 for (j = 0; j < 3; j++) {
854 /* Clear AUX CH data buffer */
855 reg = BUF_CLR;
856 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
857
858 /* Set normal AUX CH command */
859 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
860 reg &= ~ADDR_ONLY;
861 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
862
863 /*
864 * If Rx sends defer, Tx sends only reads
865 * request without sending address
866 */
867 if (!defer)
868 retval = analogix_dp_select_i2c_device(dp,
869 device_addr, reg_addr + i);
870 else
871 defer = 0;
872
873 if (retval == 0) {
874 /*
875 * Set I2C transaction and write data
876 * If bit 3 is 1, DisplayPort transaction.
877 * If Bit 3 is 0, I2C transaction.
878 */
879 reg = AUX_LENGTH(16) |
880 AUX_TX_COMM_I2C_TRANSACTION |
881 AUX_TX_COMM_READ;
882 writel(reg, dp->reg_base +
883 ANALOGIX_DP_AUX_CH_CTL_1);
884
885 /* Start AUX transaction */
886 retval = analogix_dp_start_aux_transaction(dp);
887 if (retval == 0)
888 break;
889
890 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
891 __func__);
892 }
893 /* Check if Rx sends defer */
894 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
895 if (reg == AUX_RX_COMM_AUX_DEFER ||
896 reg == AUX_RX_COMM_I2C_DEFER) {
897 dev_err(dp->dev, "Defer: %d\n\n", reg);
898 defer = 1;
899 }
900 }
901
902 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
903 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
904 + 4 * cur_data_idx);
905 edid[i + cur_data_idx] = (unsigned char)reg;
906 }
907 }
908
909 return retval;
910 }
911
912 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
913 {
914 u32 reg;
915
916 reg = bwtype;
917 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
918 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
919 }
920
921 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
922 {
923 u32 reg;
924
925 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
926 *bwtype = reg;
927 }
928
929 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
930 {
931 u32 reg;
932
933 reg = count;
934 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
935 }
936
937 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
938 {
939 u32 reg;
940
941 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
942 *count = reg;
943 }
944
945 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
946 bool enable)
947 {
948 u32 reg;
949
950 if (enable) {
951 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
952 reg |= ENHANCED;
953 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
954 } else {
955 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
956 reg &= ~ENHANCED;
957 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
958 }
959 }
960
961 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
962 enum pattern_set pattern)
963 {
964 u32 reg;
965
966 switch (pattern) {
967 case PRBS7:
968 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
969 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
970 break;
971 case D10_2:
972 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
973 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
974 break;
975 case TRAINING_PTN1:
976 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
977 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
978 break;
979 case TRAINING_PTN2:
980 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
981 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
982 break;
983 case DP_NONE:
984 reg = SCRAMBLING_ENABLE |
985 LINK_QUAL_PATTERN_SET_DISABLE |
986 SW_TRAINING_PATTERN_SET_NORMAL;
987 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
988 break;
989 default:
990 break;
991 }
992 }
993
994 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
995 u32 level)
996 {
997 u32 reg;
998
999 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1000 reg &= ~PRE_EMPHASIS_SET_MASK;
1001 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1002 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1003 }
1004
1005 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
1006 u32 level)
1007 {
1008 u32 reg;
1009
1010 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1011 reg &= ~PRE_EMPHASIS_SET_MASK;
1012 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1013 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1014 }
1015
1016 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
1017 u32 level)
1018 {
1019 u32 reg;
1020
1021 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1022 reg &= ~PRE_EMPHASIS_SET_MASK;
1023 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1024 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1025 }
1026
1027 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
1028 u32 level)
1029 {
1030 u32 reg;
1031
1032 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1033 reg &= ~PRE_EMPHASIS_SET_MASK;
1034 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1035 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1036 }
1037
1038 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
1039 u32 training_lane)
1040 {
1041 u32 reg;
1042
1043 reg = training_lane;
1044 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1045 }
1046
1047 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
1048 u32 training_lane)
1049 {
1050 u32 reg;
1051
1052 reg = training_lane;
1053 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1054 }
1055
1056 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
1057 u32 training_lane)
1058 {
1059 u32 reg;
1060
1061 reg = training_lane;
1062 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1063 }
1064
1065 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
1066 u32 training_lane)
1067 {
1068 u32 reg;
1069
1070 reg = training_lane;
1071 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1072 }
1073
1074 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
1075 {
1076 u32 reg;
1077
1078 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1079 return reg;
1080 }
1081
1082 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
1083 {
1084 u32 reg;
1085
1086 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1087 return reg;
1088 }
1089
1090 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
1091 {
1092 u32 reg;
1093
1094 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1095 return reg;
1096 }
1097
1098 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
1099 {
1100 u32 reg;
1101
1102 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1103 return reg;
1104 }
1105
1106 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
1107 {
1108 u32 reg;
1109
1110 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
1111 reg |= MACRO_RST;
1112 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1113
1114 /* 10 us is the minimum reset time. */
1115 usleep_range(10, 20);
1116
1117 reg &= ~MACRO_RST;
1118 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1119 }
1120
1121 void analogix_dp_init_video(struct analogix_dp_device *dp)
1122 {
1123 u32 reg;
1124
1125 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1126 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
1127
1128 reg = 0x0;
1129 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1130
1131 reg = CHA_CRI(4) | CHA_CTRL;
1132 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1133
1134 reg = 0x0;
1135 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1136
1137 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1138 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
1139 }
1140
1141 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
1142 {
1143 u32 reg;
1144
1145 /* Configure the input color depth, color space, dynamic range */
1146 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
1147 (dp->video_info.color_depth << IN_BPC_SHIFT) |
1148 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
1149 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
1150
1151 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1152 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1153 reg &= ~IN_YC_COEFFI_MASK;
1154 if (dp->video_info.ycbcr_coeff)
1155 reg |= IN_YC_COEFFI_ITU709;
1156 else
1157 reg |= IN_YC_COEFFI_ITU601;
1158 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1159 }
1160
1161 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
1162 {
1163 u32 reg;
1164
1165 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1166 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1167
1168 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1169
1170 if (!(reg & DET_STA)) {
1171 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1172 return -EINVAL;
1173 }
1174
1175 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1176 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1177
1178 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1179 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1180
1181 if (reg & CHA_STA) {
1182 dev_dbg(dp->dev, "Input stream clk is changing\n");
1183 return -EINVAL;
1184 }
1185
1186 return 0;
1187 }
1188
1189 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
1190 enum clock_recovery_m_value_type type,
1191 u32 m_value, u32 n_value)
1192 {
1193 u32 reg;
1194
1195 if (type == REGISTER_M) {
1196 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1197 reg |= FIX_M_VID;
1198 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1199 reg = m_value & 0xff;
1200 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
1201 reg = (m_value >> 8) & 0xff;
1202 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
1203 reg = (m_value >> 16) & 0xff;
1204 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
1205
1206 reg = n_value & 0xff;
1207 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
1208 reg = (n_value >> 8) & 0xff;
1209 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
1210 reg = (n_value >> 16) & 0xff;
1211 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
1212 } else {
1213 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1214 reg &= ~FIX_M_VID;
1215 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1216
1217 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
1218 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
1219 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
1220 }
1221 }
1222
1223 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
1224 {
1225 u32 reg;
1226
1227 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1228 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1229 reg &= ~FORMAT_SEL;
1230 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1231 } else {
1232 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1233 reg |= FORMAT_SEL;
1234 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1235 }
1236 }
1237
1238 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
1239 {
1240 u32 reg;
1241
1242 if (enable) {
1243 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1244 reg &= ~VIDEO_MODE_MASK;
1245 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1246 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1247 } else {
1248 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1249 reg &= ~VIDEO_MODE_MASK;
1250 reg |= VIDEO_MODE_SLAVE_MODE;
1251 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1252 }
1253 }
1254
1255 void analogix_dp_start_video(struct analogix_dp_device *dp)
1256 {
1257 u32 reg;
1258
1259 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1260 reg |= VIDEO_EN;
1261 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1262 }
1263
1264 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
1265 {
1266 u32 reg;
1267
1268 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1269 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1270
1271 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1272 if (!(reg & STRM_VALID)) {
1273 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1274 return -EINVAL;
1275 }
1276
1277 return 0;
1278 }
1279
1280 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
1281 {
1282 u32 reg;
1283
1284 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1285 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
1286 reg |= MASTER_VID_FUNC_EN_N;
1287 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1288
1289 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1290 reg &= ~INTERACE_SCAN_CFG;
1291 reg |= (dp->video_info.interlaced << 2);
1292 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1293
1294 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1295 reg &= ~VSYNC_POLARITY_CFG;
1296 reg |= (dp->video_info.v_sync_polarity << 1);
1297 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1298
1299 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1300 reg &= ~HSYNC_POLARITY_CFG;
1301 reg |= (dp->video_info.h_sync_polarity << 0);
1302 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1303
1304 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1305 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1306 }
1307
1308 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
1309 {
1310 u32 reg;
1311
1312 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1313 reg &= ~SCRAMBLING_DISABLE;
1314 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1315 }
1316
1317 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
1318 {
1319 u32 reg;
1320
1321 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1322 reg |= SCRAMBLING_DISABLE;
1323 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1324 }
1325
1326 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
1327 {
1328 writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
1329 }
1330
1331 void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
1332 struct edp_vsc_psr *vsc)
1333 {
1334 unsigned int val;
1335
1336 /* don't send info frame */
1337 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1338 val &= ~IF_EN;
1339 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1340
1341 /* configure single frame update mode */
1342 writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE,
1343 dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL);
1344
1345 /* configure VSC HB0~HB3 */
1346 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0);
1347 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1);
1348 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2);
1349 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3);
1350
1351 /* configure reused VSC PB0~PB3, magic number from vendor */
1352 writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
1353 writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
1354 writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
1355 writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
1356
1357 /* configure DB0 / DB1 values */
1358 writel(vsc->DB0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
1359 writel(vsc->DB1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
1360
1361 /* set reuse spd inforframe */
1362 val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1363 val |= REUSE_SPD_EN;
1364 writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1365
1366 /* mark info frame update */
1367 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1368 val = (val | IF_UP) & ~IF_EN;
1369 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1370
1371 /* send info frame */
1372 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1373 val |= IF_EN;
1374 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1375 }
Linux kernel - Deliverables
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