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38d7762ebdcba765c37637a2802db03b1bd7255c
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos7_drm_decon.c
1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15 #include <drm/exynos_drm.h>
16
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
29
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_iommu.h"
35
36 /*
37 * DECON stands for Display and Enhancement controller.
38 */
39
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
41
42 #define WINDOWS_NR 2
43 #define CURSOR_WIN 1
44
45 struct decon_context {
46 struct device *dev;
47 struct drm_device *drm_dev;
48 struct exynos_drm_crtc *crtc;
49 struct exynos_drm_plane planes[WINDOWS_NR];
50 struct clk *pclk;
51 struct clk *aclk;
52 struct clk *eclk;
53 struct clk *vclk;
54 void __iomem *regs;
55 unsigned long irq_flags;
56 bool i80_if;
57 bool suspended;
58 int pipe;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
61
62 struct exynos_drm_panel_info panel;
63 struct drm_encoder *encoder;
64 };
65
66 static const struct of_device_id decon_driver_dt_match[] = {
67 {.compatible = "samsung,exynos7-decon"},
68 {},
69 };
70 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
71
72 static const uint32_t decon_formats[] = {
73 DRM_FORMAT_RGB565,
74 DRM_FORMAT_XRGB8888,
75 DRM_FORMAT_XBGR8888,
76 DRM_FORMAT_RGBX8888,
77 DRM_FORMAT_BGRX8888,
78 DRM_FORMAT_ARGB8888,
79 DRM_FORMAT_ABGR8888,
80 DRM_FORMAT_RGBA8888,
81 DRM_FORMAT_BGRA8888,
82 };
83
84 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
85 {
86 struct decon_context *ctx = crtc->ctx;
87
88 if (ctx->suspended)
89 return;
90
91 atomic_set(&ctx->wait_vsync_event, 1);
92
93 /*
94 * wait for DECON to signal VSYNC interrupt or return after
95 * timeout which is set to 50ms (refresh rate of 20).
96 */
97 if (!wait_event_timeout(ctx->wait_vsync_queue,
98 !atomic_read(&ctx->wait_vsync_event),
99 HZ/20))
100 DRM_DEBUG_KMS("vblank wait timed out.\n");
101 }
102
103 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
104 {
105 struct decon_context *ctx = crtc->ctx;
106 unsigned int win, ch_enabled = 0;
107
108 DRM_DEBUG_KMS("%s\n", __FILE__);
109
110 /* Check if any channel is enabled. */
111 for (win = 0; win < WINDOWS_NR; win++) {
112 u32 val = readl(ctx->regs + WINCON(win));
113
114 if (val & WINCONx_ENWIN) {
115 val &= ~WINCONx_ENWIN;
116 writel(val, ctx->regs + WINCON(win));
117 ch_enabled = 1;
118 }
119 }
120
121 /* Wait for vsync, as disable channel takes effect at next vsync */
122 if (ch_enabled)
123 decon_wait_for_vblank(ctx->crtc);
124 }
125
126 static int decon_ctx_initialize(struct decon_context *ctx,
127 struct drm_device *drm_dev)
128 {
129 struct exynos_drm_private *priv = drm_dev->dev_private;
130 int ret;
131
132 ctx->drm_dev = drm_dev;
133 ctx->pipe = priv->pipe++;
134
135 decon_clear_channels(ctx->crtc);
136
137 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
138 if (ret)
139 priv->pipe--;
140
141 return ret;
142 }
143
144 static void decon_ctx_remove(struct decon_context *ctx)
145 {
146 /* detach this sub driver from iommu mapping if supported. */
147 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
148 }
149
150 static u32 decon_calc_clkdiv(struct decon_context *ctx,
151 const struct drm_display_mode *mode)
152 {
153 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
154 u32 clkdiv;
155
156 /* Find the clock divider value that gets us closest to ideal_clk */
157 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
158
159 return (clkdiv < 0x100) ? clkdiv : 0xff;
160 }
161
162 static void decon_commit(struct exynos_drm_crtc *crtc)
163 {
164 struct decon_context *ctx = crtc->ctx;
165 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
166 u32 val, clkdiv;
167
168 if (ctx->suspended)
169 return;
170
171 /* nothing to do if we haven't set the mode yet */
172 if (mode->htotal == 0 || mode->vtotal == 0)
173 return;
174
175 if (!ctx->i80_if) {
176 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
177 /* setup vertical timing values. */
178 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
179 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
180 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
181
182 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
183 writel(val, ctx->regs + VIDTCON0);
184
185 val = VIDTCON1_VSPW(vsync_len - 1);
186 writel(val, ctx->regs + VIDTCON1);
187
188 /* setup horizontal timing values. */
189 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
190 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
191 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
192
193 /* setup horizontal timing values. */
194 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
195 writel(val, ctx->regs + VIDTCON2);
196
197 val = VIDTCON3_HSPW(hsync_len - 1);
198 writel(val, ctx->regs + VIDTCON3);
199 }
200
201 /* setup horizontal and vertical display size. */
202 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
203 VIDTCON4_HOZVAL(mode->hdisplay - 1);
204 writel(val, ctx->regs + VIDTCON4);
205
206 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
207
208 /*
209 * fields of register with prefix '_F' would be updated
210 * at vsync(same as dma start)
211 */
212 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
213 writel(val, ctx->regs + VIDCON0);
214
215 clkdiv = decon_calc_clkdiv(ctx, mode);
216 if (clkdiv > 1) {
217 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
218 writel(val, ctx->regs + VCLKCON1);
219 writel(val, ctx->regs + VCLKCON2);
220 }
221
222 val = readl(ctx->regs + DECON_UPDATE);
223 val |= DECON_UPDATE_STANDALONE_F;
224 writel(val, ctx->regs + DECON_UPDATE);
225 }
226
227 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
228 {
229 struct decon_context *ctx = crtc->ctx;
230 u32 val;
231
232 if (ctx->suspended)
233 return -EPERM;
234
235 if (!test_and_set_bit(0, &ctx->irq_flags)) {
236 val = readl(ctx->regs + VIDINTCON0);
237
238 val |= VIDINTCON0_INT_ENABLE;
239
240 if (!ctx->i80_if) {
241 val |= VIDINTCON0_INT_FRAME;
242 val &= ~VIDINTCON0_FRAMESEL0_MASK;
243 val |= VIDINTCON0_FRAMESEL0_VSYNC;
244 }
245
246 writel(val, ctx->regs + VIDINTCON0);
247 }
248
249 return 0;
250 }
251
252 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
253 {
254 struct decon_context *ctx = crtc->ctx;
255 u32 val;
256
257 if (ctx->suspended)
258 return;
259
260 if (test_and_clear_bit(0, &ctx->irq_flags)) {
261 val = readl(ctx->regs + VIDINTCON0);
262
263 val &= ~VIDINTCON0_INT_ENABLE;
264 if (!ctx->i80_if)
265 val &= ~VIDINTCON0_INT_FRAME;
266
267 writel(val, ctx->regs + VIDINTCON0);
268 }
269 }
270
271 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
272 struct drm_framebuffer *fb)
273 {
274 unsigned long val;
275 int padding;
276
277 val = readl(ctx->regs + WINCON(win));
278 val &= ~WINCONx_BPPMODE_MASK;
279
280 switch (fb->pixel_format) {
281 case DRM_FORMAT_RGB565:
282 val |= WINCONx_BPPMODE_16BPP_565;
283 val |= WINCONx_BURSTLEN_16WORD;
284 break;
285 case DRM_FORMAT_XRGB8888:
286 val |= WINCONx_BPPMODE_24BPP_xRGB;
287 val |= WINCONx_BURSTLEN_16WORD;
288 break;
289 case DRM_FORMAT_XBGR8888:
290 val |= WINCONx_BPPMODE_24BPP_xBGR;
291 val |= WINCONx_BURSTLEN_16WORD;
292 break;
293 case DRM_FORMAT_RGBX8888:
294 val |= WINCONx_BPPMODE_24BPP_RGBx;
295 val |= WINCONx_BURSTLEN_16WORD;
296 break;
297 case DRM_FORMAT_BGRX8888:
298 val |= WINCONx_BPPMODE_24BPP_BGRx;
299 val |= WINCONx_BURSTLEN_16WORD;
300 break;
301 case DRM_FORMAT_ARGB8888:
302 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
303 WINCONx_ALPHA_SEL;
304 val |= WINCONx_BURSTLEN_16WORD;
305 break;
306 case DRM_FORMAT_ABGR8888:
307 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
308 WINCONx_ALPHA_SEL;
309 val |= WINCONx_BURSTLEN_16WORD;
310 break;
311 case DRM_FORMAT_RGBA8888:
312 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
313 WINCONx_ALPHA_SEL;
314 val |= WINCONx_BURSTLEN_16WORD;
315 break;
316 case DRM_FORMAT_BGRA8888:
317 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
318 WINCONx_ALPHA_SEL;
319 val |= WINCONx_BURSTLEN_16WORD;
320 break;
321 default:
322 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
323
324 val |= WINCONx_BPPMODE_24BPP_xRGB;
325 val |= WINCONx_BURSTLEN_16WORD;
326 break;
327 }
328
329 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
330
331 /*
332 * In case of exynos, setting dma-burst to 16Word causes permanent
333 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
334 * switching which is based on plane size is not recommended as
335 * plane size varies a lot towards the end of the screen and rapid
336 * movement causes unstable DMA which results into iommu crash/tear.
337 */
338
339 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
340 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
341 val &= ~WINCONx_BURSTLEN_MASK;
342 val |= WINCONx_BURSTLEN_8WORD;
343 }
344
345 writel(val, ctx->regs + WINCON(win));
346 }
347
348 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
349 {
350 unsigned int keycon0 = 0, keycon1 = 0;
351
352 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
353 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
354
355 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
356
357 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
358 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
359 }
360
361 /**
362 * shadow_protect_win() - disable updating values from shadow registers at vsync
363 *
364 * @win: window to protect registers for
365 * @protect: 1 to protect (disable updates)
366 */
367 static void decon_shadow_protect_win(struct decon_context *ctx,
368 unsigned int win, bool protect)
369 {
370 u32 bits, val;
371
372 bits = SHADOWCON_WINx_PROTECT(win);
373
374 val = readl(ctx->regs + SHADOWCON);
375 if (protect)
376 val |= bits;
377 else
378 val &= ~bits;
379 writel(val, ctx->regs + SHADOWCON);
380 }
381
382 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
383 struct exynos_drm_plane *plane)
384 {
385 struct decon_context *ctx = crtc->ctx;
386
387 if (ctx->suspended)
388 return;
389
390 decon_shadow_protect_win(ctx, plane->zpos, true);
391 }
392
393 static void decon_update_plane(struct exynos_drm_crtc *crtc,
394 struct exynos_drm_plane *plane)
395 {
396 struct decon_context *ctx = crtc->ctx;
397 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
398 struct drm_plane_state *state = plane->base.state;
399 int padding;
400 unsigned long val, alpha;
401 unsigned int last_x;
402 unsigned int last_y;
403 unsigned int win = plane->zpos;
404 unsigned int bpp = state->fb->bits_per_pixel >> 3;
405 unsigned int pitch = state->fb->pitches[0];
406
407 if (ctx->suspended)
408 return;
409
410 /*
411 * SHADOWCON/PRTCON register is used for enabling timing.
412 *
413 * for example, once only width value of a register is set,
414 * if the dma is started then decon hardware could malfunction so
415 * with protect window setting, the register fields with prefix '_F'
416 * wouldn't be updated at vsync also but updated once unprotect window
417 * is set.
418 */
419
420 /* buffer start address */
421 val = (unsigned long)plane->dma_addr[0];
422 writel(val, ctx->regs + VIDW_BUF_START(win));
423
424 padding = (pitch / bpp) - state->fb->width;
425
426 /* buffer size */
427 writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
428 writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win));
429
430 /* offset from the start of the buffer to read */
431 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win));
432 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win));
433
434 DRM_DEBUG_KMS("start addr = 0x%lx\n",
435 (unsigned long)val);
436 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
437 plane->crtc_w, plane->crtc_h);
438
439 /*
440 * OSD position.
441 * In case the window layout goes of LCD layout, DECON fails.
442 */
443 if ((plane->crtc_x + plane->crtc_w) > mode->hdisplay)
444 plane->crtc_x = mode->hdisplay - plane->crtc_w;
445 if ((plane->crtc_y + plane->crtc_h) > mode->vdisplay)
446 plane->crtc_y = mode->vdisplay - plane->crtc_h;
447
448 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
449 VIDOSDxA_TOPLEFT_Y(plane->crtc_y);
450 writel(val, ctx->regs + VIDOSD_A(win));
451
452 last_x = plane->crtc_x + plane->crtc_w;
453 if (last_x)
454 last_x--;
455 last_y = plane->crtc_y + plane->crtc_h;
456 if (last_y)
457 last_y--;
458
459 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
460
461 writel(val, ctx->regs + VIDOSD_B(win));
462
463 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
464 plane->crtc_x, plane->crtc_y, last_x, last_y);
465
466 /* OSD alpha */
467 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
468 VIDOSDxC_ALPHA0_G_F(0x0) |
469 VIDOSDxC_ALPHA0_B_F(0x0);
470
471 writel(alpha, ctx->regs + VIDOSD_C(win));
472
473 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
474 VIDOSDxD_ALPHA1_G_F(0xff) |
475 VIDOSDxD_ALPHA1_B_F(0xff);
476
477 writel(alpha, ctx->regs + VIDOSD_D(win));
478
479 decon_win_set_pixfmt(ctx, win, state->fb);
480
481 /* hardware window 0 doesn't support color key. */
482 if (win != 0)
483 decon_win_set_colkey(ctx, win);
484
485 /* wincon */
486 val = readl(ctx->regs + WINCON(win));
487 val |= WINCONx_TRIPLE_BUF_MODE;
488 val |= WINCONx_ENWIN;
489 writel(val, ctx->regs + WINCON(win));
490
491 /* Enable DMA channel and unprotect windows */
492 decon_shadow_protect_win(ctx, win, false);
493
494 val = readl(ctx->regs + DECON_UPDATE);
495 val |= DECON_UPDATE_STANDALONE_F;
496 writel(val, ctx->regs + DECON_UPDATE);
497 }
498
499 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
500 struct exynos_drm_plane *plane)
501 {
502 struct decon_context *ctx = crtc->ctx;
503 unsigned int win = plane->zpos;
504 u32 val;
505
506 if (ctx->suspended)
507 return;
508
509 /* protect windows */
510 decon_shadow_protect_win(ctx, win, true);
511
512 /* wincon */
513 val = readl(ctx->regs + WINCON(win));
514 val &= ~WINCONx_ENWIN;
515 writel(val, ctx->regs + WINCON(win));
516
517 val = readl(ctx->regs + DECON_UPDATE);
518 val |= DECON_UPDATE_STANDALONE_F;
519 writel(val, ctx->regs + DECON_UPDATE);
520 }
521
522 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
523 struct exynos_drm_plane *plane)
524 {
525 struct decon_context *ctx = crtc->ctx;
526
527 if (ctx->suspended)
528 return;
529
530 decon_shadow_protect_win(ctx, plane->zpos, false);
531 }
532
533 static void decon_init(struct decon_context *ctx)
534 {
535 u32 val;
536
537 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
538
539 val = VIDOUTCON0_DISP_IF_0_ON;
540 if (!ctx->i80_if)
541 val |= VIDOUTCON0_RGBIF;
542 writel(val, ctx->regs + VIDOUTCON0);
543
544 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
545
546 if (!ctx->i80_if)
547 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
548 }
549
550 static void decon_enable(struct exynos_drm_crtc *crtc)
551 {
552 struct decon_context *ctx = crtc->ctx;
553
554 if (!ctx->suspended)
555 return;
556
557 pm_runtime_get_sync(ctx->dev);
558
559 decon_init(ctx);
560
561 /* if vblank was enabled status, enable it again. */
562 if (test_and_clear_bit(0, &ctx->irq_flags))
563 decon_enable_vblank(ctx->crtc);
564
565 decon_commit(ctx->crtc);
566
567 ctx->suspended = false;
568 }
569
570 static void decon_disable(struct exynos_drm_crtc *crtc)
571 {
572 struct decon_context *ctx = crtc->ctx;
573 int i;
574
575 if (ctx->suspended)
576 return;
577
578 /*
579 * We need to make sure that all windows are disabled before we
580 * suspend that connector. Otherwise we might try to scan from
581 * a destroyed buffer later.
582 */
583 for (i = 0; i < WINDOWS_NR; i++)
584 decon_disable_plane(crtc, &ctx->planes[i]);
585
586 pm_runtime_put_sync(ctx->dev);
587
588 ctx->suspended = true;
589 }
590
591 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
592 .enable = decon_enable,
593 .disable = decon_disable,
594 .commit = decon_commit,
595 .enable_vblank = decon_enable_vblank,
596 .disable_vblank = decon_disable_vblank,
597 .wait_for_vblank = decon_wait_for_vblank,
598 .atomic_begin = decon_atomic_begin,
599 .update_plane = decon_update_plane,
600 .disable_plane = decon_disable_plane,
601 .atomic_flush = decon_atomic_flush,
602 };
603
604
605 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
606 {
607 struct decon_context *ctx = (struct decon_context *)dev_id;
608 u32 val, clear_bit;
609 int win;
610
611 val = readl(ctx->regs + VIDINTCON1);
612
613 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
614 if (val & clear_bit)
615 writel(clear_bit, ctx->regs + VIDINTCON1);
616
617 /* check the crtc is detached already from encoder */
618 if (ctx->pipe < 0 || !ctx->drm_dev)
619 goto out;
620
621 if (!ctx->i80_if) {
622 drm_crtc_handle_vblank(&ctx->crtc->base);
623 for (win = 0 ; win < WINDOWS_NR ; win++) {
624 struct exynos_drm_plane *plane = &ctx->planes[win];
625
626 if (!plane->pending_fb)
627 continue;
628
629 exynos_drm_crtc_finish_update(ctx->crtc, plane);
630 }
631
632 /* set wait vsync event to zero and wake up queue. */
633 if (atomic_read(&ctx->wait_vsync_event)) {
634 atomic_set(&ctx->wait_vsync_event, 0);
635 wake_up(&ctx->wait_vsync_queue);
636 }
637 }
638 out:
639 return IRQ_HANDLED;
640 }
641
642 static int decon_bind(struct device *dev, struct device *master, void *data)
643 {
644 struct decon_context *ctx = dev_get_drvdata(dev);
645 struct drm_device *drm_dev = data;
646 struct exynos_drm_plane *exynos_plane;
647 enum drm_plane_type type;
648 unsigned int zpos;
649 int ret;
650
651 ret = decon_ctx_initialize(ctx, drm_dev);
652 if (ret) {
653 DRM_ERROR("decon_ctx_initialize failed.\n");
654 return ret;
655 }
656
657 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
658 type = exynos_plane_get_type(zpos, CURSOR_WIN);
659 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
660 1 << ctx->pipe, type, decon_formats,
661 ARRAY_SIZE(decon_formats), zpos);
662 if (ret)
663 return ret;
664 }
665
666 exynos_plane = &ctx->planes[DEFAULT_WIN];
667 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
668 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
669 &decon_crtc_ops, ctx);
670 if (IS_ERR(ctx->crtc)) {
671 decon_ctx_remove(ctx);
672 return PTR_ERR(ctx->crtc);
673 }
674
675 if (ctx->encoder)
676 exynos_dpi_bind(drm_dev, ctx->encoder);
677
678 return 0;
679
680 }
681
682 static void decon_unbind(struct device *dev, struct device *master,
683 void *data)
684 {
685 struct decon_context *ctx = dev_get_drvdata(dev);
686
687 decon_disable(ctx->crtc);
688
689 if (ctx->encoder)
690 exynos_dpi_remove(ctx->encoder);
691
692 decon_ctx_remove(ctx);
693 }
694
695 static const struct component_ops decon_component_ops = {
696 .bind = decon_bind,
697 .unbind = decon_unbind,
698 };
699
700 static int decon_probe(struct platform_device *pdev)
701 {
702 struct device *dev = &pdev->dev;
703 struct decon_context *ctx;
704 struct device_node *i80_if_timings;
705 struct resource *res;
706 int ret;
707
708 if (!dev->of_node)
709 return -ENODEV;
710
711 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
712 if (!ctx)
713 return -ENOMEM;
714
715 ctx->dev = dev;
716 ctx->suspended = true;
717
718 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
719 if (i80_if_timings)
720 ctx->i80_if = true;
721 of_node_put(i80_if_timings);
722
723 ctx->regs = of_iomap(dev->of_node, 0);
724 if (!ctx->regs)
725 return -ENOMEM;
726
727 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
728 if (IS_ERR(ctx->pclk)) {
729 dev_err(dev, "failed to get bus clock pclk\n");
730 ret = PTR_ERR(ctx->pclk);
731 goto err_iounmap;
732 }
733
734 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
735 if (IS_ERR(ctx->aclk)) {
736 dev_err(dev, "failed to get bus clock aclk\n");
737 ret = PTR_ERR(ctx->aclk);
738 goto err_iounmap;
739 }
740
741 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
742 if (IS_ERR(ctx->eclk)) {
743 dev_err(dev, "failed to get eclock\n");
744 ret = PTR_ERR(ctx->eclk);
745 goto err_iounmap;
746 }
747
748 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
749 if (IS_ERR(ctx->vclk)) {
750 dev_err(dev, "failed to get vclock\n");
751 ret = PTR_ERR(ctx->vclk);
752 goto err_iounmap;
753 }
754
755 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
756 ctx->i80_if ? "lcd_sys" : "vsync");
757 if (!res) {
758 dev_err(dev, "irq request failed.\n");
759 ret = -ENXIO;
760 goto err_iounmap;
761 }
762
763 ret = devm_request_irq(dev, res->start, decon_irq_handler,
764 0, "drm_decon", ctx);
765 if (ret) {
766 dev_err(dev, "irq request failed.\n");
767 goto err_iounmap;
768 }
769
770 init_waitqueue_head(&ctx->wait_vsync_queue);
771 atomic_set(&ctx->wait_vsync_event, 0);
772
773 platform_set_drvdata(pdev, ctx);
774
775 ctx->encoder = exynos_dpi_probe(dev);
776 if (IS_ERR(ctx->encoder)) {
777 ret = PTR_ERR(ctx->encoder);
778 goto err_iounmap;
779 }
780
781 pm_runtime_enable(dev);
782
783 ret = component_add(dev, &decon_component_ops);
784 if (ret)
785 goto err_disable_pm_runtime;
786
787 return ret;
788
789 err_disable_pm_runtime:
790 pm_runtime_disable(dev);
791
792 err_iounmap:
793 iounmap(ctx->regs);
794
795 return ret;
796 }
797
798 static int decon_remove(struct platform_device *pdev)
799 {
800 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
801
802 pm_runtime_disable(&pdev->dev);
803
804 iounmap(ctx->regs);
805
806 component_del(&pdev->dev, &decon_component_ops);
807
808 return 0;
809 }
810
811 #ifdef CONFIG_PM
812 static int exynos7_decon_suspend(struct device *dev)
813 {
814 struct decon_context *ctx = dev_get_drvdata(dev);
815
816 clk_disable_unprepare(ctx->vclk);
817 clk_disable_unprepare(ctx->eclk);
818 clk_disable_unprepare(ctx->aclk);
819 clk_disable_unprepare(ctx->pclk);
820
821 return 0;
822 }
823
824 static int exynos7_decon_resume(struct device *dev)
825 {
826 struct decon_context *ctx = dev_get_drvdata(dev);
827 int ret;
828
829 ret = clk_prepare_enable(ctx->pclk);
830 if (ret < 0) {
831 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
832 return ret;
833 }
834
835 ret = clk_prepare_enable(ctx->aclk);
836 if (ret < 0) {
837 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
838 return ret;
839 }
840
841 ret = clk_prepare_enable(ctx->eclk);
842 if (ret < 0) {
843 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
844 return ret;
845 }
846
847 ret = clk_prepare_enable(ctx->vclk);
848 if (ret < 0) {
849 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
850 return ret;
851 }
852
853 return 0;
854 }
855 #endif
856
857 static const struct dev_pm_ops exynos7_decon_pm_ops = {
858 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
859 NULL)
860 };
861
862 struct platform_driver decon_driver = {
863 .probe = decon_probe,
864 .remove = decon_remove,
865 .driver = {
866 .name = "exynos-decon",
867 .pm = &exynos7_decon_pm_ops,
868 .of_match_table = decon_driver_dt_match,
869 },
870 };
Linux kernel - Deliverables
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