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drm/exynos: introduce exynos_drm_plane_state structure
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_crtc.h"
35 #include "exynos_drm_plane.h"
36 #include "exynos_drm_iommu.h"
37
38 /*
39 * FIMD stands for Fully Interactive Mobile Display and
40 * as a display controller, it transfers contents drawn on memory
41 * to a LCD Panel through Display Interfaces such as RGB or
42 * CPU Interface.
43 */
44
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
65
66 /* color key control register for hardware window 1 ~ 4. */
67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
68 /* color key value register for hardware window 1 ~ 4. */
69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
70
71 /* I80 / RGB trigger control register */
72 #define TRIGCON 0x1A4
73 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
74 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
75
76 /* display mode change control register except exynos4 */
77 #define VIDOUT_CON 0x000
78 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
79
80 /* I80 interface control for main LDI register */
81 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
82 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
83 #define LCD_CS_SETUP(x) ((x) << 16)
84 #define LCD_WR_SETUP(x) ((x) << 12)
85 #define LCD_WR_ACTIVE(x) ((x) << 8)
86 #define LCD_WR_HOLD(x) ((x) << 4)
87 #define I80IFEN_ENABLE (1 << 0)
88
89 /* FIMD has totally five hardware windows. */
90 #define WINDOWS_NR 5
91 #define CURSOR_WIN 4
92
93 struct fimd_driver_data {
94 unsigned int timing_base;
95 unsigned int lcdblk_offset;
96 unsigned int lcdblk_vt_shift;
97 unsigned int lcdblk_bypass_shift;
98
99 unsigned int has_shadowcon:1;
100 unsigned int has_clksel:1;
101 unsigned int has_limited_fmt:1;
102 unsigned int has_vidoutcon:1;
103 unsigned int has_vtsel:1;
104 };
105
106 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
107 .timing_base = 0x0,
108 .has_clksel = 1,
109 .has_limited_fmt = 1,
110 };
111
112 static struct fimd_driver_data exynos3_fimd_driver_data = {
113 .timing_base = 0x20000,
114 .lcdblk_offset = 0x210,
115 .lcdblk_bypass_shift = 1,
116 .has_shadowcon = 1,
117 .has_vidoutcon = 1,
118 };
119
120 static struct fimd_driver_data exynos4_fimd_driver_data = {
121 .timing_base = 0x0,
122 .lcdblk_offset = 0x210,
123 .lcdblk_vt_shift = 10,
124 .lcdblk_bypass_shift = 1,
125 .has_shadowcon = 1,
126 .has_vtsel = 1,
127 };
128
129 static struct fimd_driver_data exynos4415_fimd_driver_data = {
130 .timing_base = 0x20000,
131 .lcdblk_offset = 0x210,
132 .lcdblk_vt_shift = 10,
133 .lcdblk_bypass_shift = 1,
134 .has_shadowcon = 1,
135 .has_vidoutcon = 1,
136 .has_vtsel = 1,
137 };
138
139 static struct fimd_driver_data exynos5_fimd_driver_data = {
140 .timing_base = 0x20000,
141 .lcdblk_offset = 0x214,
142 .lcdblk_vt_shift = 24,
143 .lcdblk_bypass_shift = 15,
144 .has_shadowcon = 1,
145 .has_vidoutcon = 1,
146 .has_vtsel = 1,
147 };
148
149 struct fimd_context {
150 struct device *dev;
151 struct drm_device *drm_dev;
152 struct exynos_drm_crtc *crtc;
153 struct exynos_drm_plane planes[WINDOWS_NR];
154 struct clk *bus_clk;
155 struct clk *lcd_clk;
156 void __iomem *regs;
157 struct regmap *sysreg;
158 unsigned long irq_flags;
159 u32 vidcon0;
160 u32 vidcon1;
161 u32 vidout_con;
162 u32 i80ifcon;
163 bool i80_if;
164 bool suspended;
165 int pipe;
166 wait_queue_head_t wait_vsync_queue;
167 atomic_t wait_vsync_event;
168 atomic_t win_updated;
169 atomic_t triggering;
170
171 struct exynos_drm_panel_info panel;
172 struct fimd_driver_data *driver_data;
173 struct drm_encoder *encoder;
174 };
175
176 static const struct of_device_id fimd_driver_dt_match[] = {
177 { .compatible = "samsung,s3c6400-fimd",
178 .data = &s3c64xx_fimd_driver_data },
179 { .compatible = "samsung,exynos3250-fimd",
180 .data = &exynos3_fimd_driver_data },
181 { .compatible = "samsung,exynos4210-fimd",
182 .data = &exynos4_fimd_driver_data },
183 { .compatible = "samsung,exynos4415-fimd",
184 .data = &exynos4415_fimd_driver_data },
185 { .compatible = "samsung,exynos5250-fimd",
186 .data = &exynos5_fimd_driver_data },
187 {},
188 };
189 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
190
191 static const uint32_t fimd_formats[] = {
192 DRM_FORMAT_C8,
193 DRM_FORMAT_XRGB1555,
194 DRM_FORMAT_RGB565,
195 DRM_FORMAT_XRGB8888,
196 DRM_FORMAT_ARGB8888,
197 };
198
199 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
200 struct platform_device *pdev)
201 {
202 const struct of_device_id *of_id =
203 of_match_device(fimd_driver_dt_match, &pdev->dev);
204
205 return (struct fimd_driver_data *)of_id->data;
206 }
207
208 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
209 {
210 struct fimd_context *ctx = crtc->ctx;
211 u32 val;
212
213 if (ctx->suspended)
214 return -EPERM;
215
216 if (!test_and_set_bit(0, &ctx->irq_flags)) {
217 val = readl(ctx->regs + VIDINTCON0);
218
219 val |= VIDINTCON0_INT_ENABLE;
220
221 if (ctx->i80_if) {
222 val |= VIDINTCON0_INT_I80IFDONE;
223 val |= VIDINTCON0_INT_SYSMAINCON;
224 val &= ~VIDINTCON0_INT_SYSSUBCON;
225 } else {
226 val |= VIDINTCON0_INT_FRAME;
227
228 val &= ~VIDINTCON0_FRAMESEL0_MASK;
229 val |= VIDINTCON0_FRAMESEL0_VSYNC;
230 val &= ~VIDINTCON0_FRAMESEL1_MASK;
231 val |= VIDINTCON0_FRAMESEL1_NONE;
232 }
233
234 writel(val, ctx->regs + VIDINTCON0);
235 }
236
237 return 0;
238 }
239
240 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
241 {
242 struct fimd_context *ctx = crtc->ctx;
243 u32 val;
244
245 if (ctx->suspended)
246 return;
247
248 if (test_and_clear_bit(0, &ctx->irq_flags)) {
249 val = readl(ctx->regs + VIDINTCON0);
250
251 val &= ~VIDINTCON0_INT_ENABLE;
252
253 if (ctx->i80_if) {
254 val &= ~VIDINTCON0_INT_I80IFDONE;
255 val &= ~VIDINTCON0_INT_SYSMAINCON;
256 val &= ~VIDINTCON0_INT_SYSSUBCON;
257 } else
258 val &= ~VIDINTCON0_INT_FRAME;
259
260 writel(val, ctx->regs + VIDINTCON0);
261 }
262 }
263
264 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
265 {
266 struct fimd_context *ctx = crtc->ctx;
267
268 if (ctx->suspended)
269 return;
270
271 atomic_set(&ctx->wait_vsync_event, 1);
272
273 /*
274 * wait for FIMD to signal VSYNC interrupt or return after
275 * timeout which is set to 50ms (refresh rate of 20).
276 */
277 if (!wait_event_timeout(ctx->wait_vsync_queue,
278 !atomic_read(&ctx->wait_vsync_event),
279 HZ/20))
280 DRM_DEBUG_KMS("vblank wait timed out.\n");
281 }
282
283 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
284 bool enable)
285 {
286 u32 val = readl(ctx->regs + WINCON(win));
287
288 if (enable)
289 val |= WINCONx_ENWIN;
290 else
291 val &= ~WINCONx_ENWIN;
292
293 writel(val, ctx->regs + WINCON(win));
294 }
295
296 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
297 unsigned int win,
298 bool enable)
299 {
300 u32 val = readl(ctx->regs + SHADOWCON);
301
302 if (enable)
303 val |= SHADOWCON_CHx_ENABLE(win);
304 else
305 val &= ~SHADOWCON_CHx_ENABLE(win);
306
307 writel(val, ctx->regs + SHADOWCON);
308 }
309
310 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
311 {
312 struct fimd_context *ctx = crtc->ctx;
313 unsigned int win, ch_enabled = 0;
314
315 DRM_DEBUG_KMS("%s\n", __FILE__);
316
317 /* Hardware is in unknown state, so ensure it gets enabled properly */
318 pm_runtime_get_sync(ctx->dev);
319
320 clk_prepare_enable(ctx->bus_clk);
321 clk_prepare_enable(ctx->lcd_clk);
322
323 /* Check if any channel is enabled. */
324 for (win = 0; win < WINDOWS_NR; win++) {
325 u32 val = readl(ctx->regs + WINCON(win));
326
327 if (val & WINCONx_ENWIN) {
328 fimd_enable_video_output(ctx, win, false);
329
330 if (ctx->driver_data->has_shadowcon)
331 fimd_enable_shadow_channel_path(ctx, win,
332 false);
333
334 ch_enabled = 1;
335 }
336 }
337
338 /* Wait for vsync, as disable channel takes effect at next vsync */
339 if (ch_enabled) {
340 int pipe = ctx->pipe;
341
342 /* ensure that vblank interrupt won't be reported to core */
343 ctx->suspended = false;
344 ctx->pipe = -1;
345
346 fimd_enable_vblank(ctx->crtc);
347 fimd_wait_for_vblank(ctx->crtc);
348 fimd_disable_vblank(ctx->crtc);
349
350 ctx->suspended = true;
351 ctx->pipe = pipe;
352 }
353
354 clk_disable_unprepare(ctx->lcd_clk);
355 clk_disable_unprepare(ctx->bus_clk);
356
357 pm_runtime_put(ctx->dev);
358 }
359
360 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
361 const struct drm_display_mode *mode)
362 {
363 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
364 u32 clkdiv;
365
366 if (ctx->i80_if) {
367 /*
368 * The frame done interrupt should be occurred prior to the
369 * next TE signal.
370 */
371 ideal_clk *= 2;
372 }
373
374 /* Find the clock divider value that gets us closest to ideal_clk */
375 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
376
377 return (clkdiv < 0x100) ? clkdiv : 0xff;
378 }
379
380 static void fimd_commit(struct exynos_drm_crtc *crtc)
381 {
382 struct fimd_context *ctx = crtc->ctx;
383 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
384 struct fimd_driver_data *driver_data = ctx->driver_data;
385 void *timing_base = ctx->regs + driver_data->timing_base;
386 u32 val, clkdiv;
387
388 if (ctx->suspended)
389 return;
390
391 /* nothing to do if we haven't set the mode yet */
392 if (mode->htotal == 0 || mode->vtotal == 0)
393 return;
394
395 if (ctx->i80_if) {
396 val = ctx->i80ifcon | I80IFEN_ENABLE;
397 writel(val, timing_base + I80IFCONFAx(0));
398
399 /* disable auto frame rate */
400 writel(0, timing_base + I80IFCONFBx(0));
401
402 /* set video type selection to I80 interface */
403 if (driver_data->has_vtsel && ctx->sysreg &&
404 regmap_update_bits(ctx->sysreg,
405 driver_data->lcdblk_offset,
406 0x3 << driver_data->lcdblk_vt_shift,
407 0x1 << driver_data->lcdblk_vt_shift)) {
408 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
409 return;
410 }
411 } else {
412 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
413 u32 vidcon1;
414
415 /* setup polarity values */
416 vidcon1 = ctx->vidcon1;
417 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
418 vidcon1 |= VIDCON1_INV_VSYNC;
419 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
420 vidcon1 |= VIDCON1_INV_HSYNC;
421 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
422
423 /* setup vertical timing values. */
424 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
425 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
426 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
427
428 val = VIDTCON0_VBPD(vbpd - 1) |
429 VIDTCON0_VFPD(vfpd - 1) |
430 VIDTCON0_VSPW(vsync_len - 1);
431 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
432
433 /* setup horizontal timing values. */
434 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
435 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
436 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
437
438 val = VIDTCON1_HBPD(hbpd - 1) |
439 VIDTCON1_HFPD(hfpd - 1) |
440 VIDTCON1_HSPW(hsync_len - 1);
441 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
442 }
443
444 if (driver_data->has_vidoutcon)
445 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
446
447 /* set bypass selection */
448 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
449 driver_data->lcdblk_offset,
450 0x1 << driver_data->lcdblk_bypass_shift,
451 0x1 << driver_data->lcdblk_bypass_shift)) {
452 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
453 return;
454 }
455
456 /* setup horizontal and vertical display size. */
457 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
458 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
459 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
460 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
461 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
462
463 /*
464 * fields of register with prefix '_F' would be updated
465 * at vsync(same as dma start)
466 */
467 val = ctx->vidcon0;
468 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
469
470 if (ctx->driver_data->has_clksel)
471 val |= VIDCON0_CLKSEL_LCD;
472
473 clkdiv = fimd_calc_clkdiv(ctx, mode);
474 if (clkdiv > 1)
475 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
476
477 writel(val, ctx->regs + VIDCON0);
478 }
479
480
481 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
482 struct drm_framebuffer *fb)
483 {
484 unsigned long val;
485
486 val = WINCONx_ENWIN;
487
488 /*
489 * In case of s3c64xx, window 0 doesn't support alpha channel.
490 * So the request format is ARGB8888 then change it to XRGB8888.
491 */
492 if (ctx->driver_data->has_limited_fmt && !win) {
493 if (fb->pixel_format == DRM_FORMAT_ARGB8888)
494 fb->pixel_format = DRM_FORMAT_XRGB8888;
495 }
496
497 switch (fb->pixel_format) {
498 case DRM_FORMAT_C8:
499 val |= WINCON0_BPPMODE_8BPP_PALETTE;
500 val |= WINCONx_BURSTLEN_8WORD;
501 val |= WINCONx_BYTSWP;
502 break;
503 case DRM_FORMAT_XRGB1555:
504 val |= WINCON0_BPPMODE_16BPP_1555;
505 val |= WINCONx_HAWSWP;
506 val |= WINCONx_BURSTLEN_16WORD;
507 break;
508 case DRM_FORMAT_RGB565:
509 val |= WINCON0_BPPMODE_16BPP_565;
510 val |= WINCONx_HAWSWP;
511 val |= WINCONx_BURSTLEN_16WORD;
512 break;
513 case DRM_FORMAT_XRGB8888:
514 val |= WINCON0_BPPMODE_24BPP_888;
515 val |= WINCONx_WSWP;
516 val |= WINCONx_BURSTLEN_16WORD;
517 break;
518 case DRM_FORMAT_ARGB8888:
519 val |= WINCON1_BPPMODE_25BPP_A1888
520 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
521 val |= WINCONx_WSWP;
522 val |= WINCONx_BURSTLEN_16WORD;
523 break;
524 default:
525 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
526
527 val |= WINCON0_BPPMODE_24BPP_888;
528 val |= WINCONx_WSWP;
529 val |= WINCONx_BURSTLEN_16WORD;
530 break;
531 }
532
533 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
534
535 /*
536 * In case of exynos, setting dma-burst to 16Word causes permanent
537 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
538 * switching which is based on plane size is not recommended as
539 * plane size varies alot towards the end of the screen and rapid
540 * movement causes unstable DMA which results into iommu crash/tear.
541 */
542
543 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
544 val &= ~WINCONx_BURSTLEN_MASK;
545 val |= WINCONx_BURSTLEN_4WORD;
546 }
547
548 writel(val, ctx->regs + WINCON(win));
549
550 /* hardware window 0 doesn't support alpha channel. */
551 if (win != 0) {
552 /* OSD alpha */
553 val = VIDISD14C_ALPHA0_R(0xf) |
554 VIDISD14C_ALPHA0_G(0xf) |
555 VIDISD14C_ALPHA0_B(0xf) |
556 VIDISD14C_ALPHA1_R(0xf) |
557 VIDISD14C_ALPHA1_G(0xf) |
558 VIDISD14C_ALPHA1_B(0xf);
559
560 writel(val, ctx->regs + VIDOSD_C(win));
561
562 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
563 VIDW_ALPHA_G(0xf);
564 writel(val, ctx->regs + VIDWnALPHA0(win));
565 writel(val, ctx->regs + VIDWnALPHA1(win));
566 }
567 }
568
569 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
570 {
571 unsigned int keycon0 = 0, keycon1 = 0;
572
573 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
574 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
575
576 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
577
578 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
579 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
580 }
581
582 /**
583 * shadow_protect_win() - disable updating values from shadow registers at vsync
584 *
585 * @win: window to protect registers for
586 * @protect: 1 to protect (disable updates)
587 */
588 static void fimd_shadow_protect_win(struct fimd_context *ctx,
589 unsigned int win, bool protect)
590 {
591 u32 reg, bits, val;
592
593 /*
594 * SHADOWCON/PRTCON register is used for enabling timing.
595 *
596 * for example, once only width value of a register is set,
597 * if the dma is started then fimd hardware could malfunction so
598 * with protect window setting, the register fields with prefix '_F'
599 * wouldn't be updated at vsync also but updated once unprotect window
600 * is set.
601 */
602
603 if (ctx->driver_data->has_shadowcon) {
604 reg = SHADOWCON;
605 bits = SHADOWCON_WINx_PROTECT(win);
606 } else {
607 reg = PRTCON;
608 bits = PRTCON_PROTECT;
609 }
610
611 val = readl(ctx->regs + reg);
612 if (protect)
613 val |= bits;
614 else
615 val &= ~bits;
616 writel(val, ctx->regs + reg);
617 }
618
619 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc,
620 struct exynos_drm_plane *plane)
621 {
622 struct fimd_context *ctx = crtc->ctx;
623
624 if (ctx->suspended)
625 return;
626
627 fimd_shadow_protect_win(ctx, plane->zpos, true);
628 }
629
630 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc,
631 struct exynos_drm_plane *plane)
632 {
633 struct fimd_context *ctx = crtc->ctx;
634
635 if (ctx->suspended)
636 return;
637
638 fimd_shadow_protect_win(ctx, plane->zpos, false);
639 }
640
641 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
642 struct exynos_drm_plane *plane)
643 {
644 struct exynos_drm_plane_state *state =
645 to_exynos_plane_state(plane->base.state);
646 struct fimd_context *ctx = crtc->ctx;
647 struct drm_framebuffer *fb = state->base.fb;
648 dma_addr_t dma_addr;
649 unsigned long val, size, offset;
650 unsigned int last_x, last_y, buf_offsize, line_size;
651 unsigned int win = plane->zpos;
652 unsigned int bpp = fb->bits_per_pixel >> 3;
653 unsigned int pitch = fb->pitches[0];
654
655 if (ctx->suspended)
656 return;
657
658 offset = state->src.x * bpp;
659 offset += state->src.y * pitch;
660
661 /* buffer start address */
662 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
663 val = (unsigned long)dma_addr;
664 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
665
666 /* buffer end address */
667 size = pitch * state->crtc.h;
668 val = (unsigned long)(dma_addr + size);
669 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
670
671 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
672 (unsigned long)dma_addr, val, size);
673 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
674 state->crtc.w, state->crtc.h);
675
676 /* buffer size */
677 buf_offsize = pitch - (state->crtc.w * bpp);
678 line_size = state->crtc.w * bpp;
679 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
680 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
681 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
682 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
683 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
684
685 /* OSD position */
686 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
687 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
688 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
689 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
690 writel(val, ctx->regs + VIDOSD_A(win));
691
692 last_x = state->crtc.x + state->crtc.w;
693 if (last_x)
694 last_x--;
695 last_y = state->crtc.y + state->crtc.h;
696 if (last_y)
697 last_y--;
698
699 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
700 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
701
702 writel(val, ctx->regs + VIDOSD_B(win));
703
704 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
705 state->crtc.x, state->crtc.y, last_x, last_y);
706
707 /* OSD size */
708 if (win != 3 && win != 4) {
709 u32 offset = VIDOSD_D(win);
710 if (win == 0)
711 offset = VIDOSD_C(win);
712 val = state->crtc.w * state->crtc.h;
713 writel(val, ctx->regs + offset);
714
715 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
716 }
717
718 fimd_win_set_pixfmt(ctx, win, fb);
719
720 /* hardware window 0 doesn't support color key. */
721 if (win != 0)
722 fimd_win_set_colkey(ctx, win);
723
724 fimd_enable_video_output(ctx, win, true);
725
726 if (ctx->driver_data->has_shadowcon)
727 fimd_enable_shadow_channel_path(ctx, win, true);
728
729 if (ctx->i80_if)
730 atomic_set(&ctx->win_updated, 1);
731 }
732
733 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
734 struct exynos_drm_plane *plane)
735 {
736 struct fimd_context *ctx = crtc->ctx;
737 unsigned int win = plane->zpos;
738
739 if (ctx->suspended)
740 return;
741
742 fimd_enable_video_output(ctx, win, false);
743
744 if (ctx->driver_data->has_shadowcon)
745 fimd_enable_shadow_channel_path(ctx, win, false);
746 }
747
748 static void fimd_enable(struct exynos_drm_crtc *crtc)
749 {
750 struct fimd_context *ctx = crtc->ctx;
751
752 if (!ctx->suspended)
753 return;
754
755 ctx->suspended = false;
756
757 pm_runtime_get_sync(ctx->dev);
758
759 /* if vblank was enabled status, enable it again. */
760 if (test_and_clear_bit(0, &ctx->irq_flags))
761 fimd_enable_vblank(ctx->crtc);
762
763 fimd_commit(ctx->crtc);
764 }
765
766 static void fimd_disable(struct exynos_drm_crtc *crtc)
767 {
768 struct fimd_context *ctx = crtc->ctx;
769 int i;
770
771 if (ctx->suspended)
772 return;
773
774 /*
775 * We need to make sure that all windows are disabled before we
776 * suspend that connector. Otherwise we might try to scan from
777 * a destroyed buffer later.
778 */
779 for (i = 0; i < WINDOWS_NR; i++)
780 fimd_disable_plane(crtc, &ctx->planes[i]);
781
782 fimd_enable_vblank(crtc);
783 fimd_wait_for_vblank(crtc);
784 fimd_disable_vblank(crtc);
785
786 writel(0, ctx->regs + VIDCON0);
787
788 pm_runtime_put_sync(ctx->dev);
789 ctx->suspended = true;
790 }
791
792 static void fimd_trigger(struct device *dev)
793 {
794 struct fimd_context *ctx = dev_get_drvdata(dev);
795 struct fimd_driver_data *driver_data = ctx->driver_data;
796 void *timing_base = ctx->regs + driver_data->timing_base;
797 u32 reg;
798
799 /*
800 * Skips triggering if in triggering state, because multiple triggering
801 * requests can cause panel reset.
802 */
803 if (atomic_read(&ctx->triggering))
804 return;
805
806 /* Enters triggering mode */
807 atomic_set(&ctx->triggering, 1);
808
809 reg = readl(timing_base + TRIGCON);
810 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
811 writel(reg, timing_base + TRIGCON);
812
813 /*
814 * Exits triggering mode if vblank is not enabled yet, because when the
815 * VIDINTCON0 register is not set, it can not exit from triggering mode.
816 */
817 if (!test_bit(0, &ctx->irq_flags))
818 atomic_set(&ctx->triggering, 0);
819 }
820
821 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
822 {
823 struct fimd_context *ctx = crtc->ctx;
824
825 /* Checks the crtc is detached already from encoder */
826 if (ctx->pipe < 0 || !ctx->drm_dev)
827 return;
828
829 /*
830 * If there is a page flip request, triggers and handles the page flip
831 * event so that current fb can be updated into panel GRAM.
832 */
833 if (atomic_add_unless(&ctx->win_updated, -1, 0))
834 fimd_trigger(ctx->dev);
835
836 /* Wakes up vsync event queue */
837 if (atomic_read(&ctx->wait_vsync_event)) {
838 atomic_set(&ctx->wait_vsync_event, 0);
839 wake_up(&ctx->wait_vsync_queue);
840 }
841
842 if (test_bit(0, &ctx->irq_flags))
843 drm_crtc_handle_vblank(&ctx->crtc->base);
844 }
845
846 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
847 {
848 struct fimd_context *ctx = crtc->ctx;
849 u32 val;
850
851 /*
852 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
853 * clock. On these SoCs the bootloader may enable it but any
854 * power domain off/on will reset it to disable state.
855 */
856 if (ctx->driver_data != &exynos5_fimd_driver_data)
857 return;
858
859 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
860 writel(val, ctx->regs + DP_MIE_CLKCON);
861 }
862
863 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
864 .enable = fimd_enable,
865 .disable = fimd_disable,
866 .commit = fimd_commit,
867 .enable_vblank = fimd_enable_vblank,
868 .disable_vblank = fimd_disable_vblank,
869 .wait_for_vblank = fimd_wait_for_vblank,
870 .atomic_begin = fimd_atomic_begin,
871 .update_plane = fimd_update_plane,
872 .disable_plane = fimd_disable_plane,
873 .atomic_flush = fimd_atomic_flush,
874 .te_handler = fimd_te_handler,
875 .clock_enable = fimd_dp_clock_enable,
876 };
877
878 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
879 {
880 struct fimd_context *ctx = (struct fimd_context *)dev_id;
881 u32 val, clear_bit, start, start_s;
882 int win;
883
884 val = readl(ctx->regs + VIDINTCON1);
885
886 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
887 if (val & clear_bit)
888 writel(clear_bit, ctx->regs + VIDINTCON1);
889
890 /* check the crtc is detached already from encoder */
891 if (ctx->pipe < 0 || !ctx->drm_dev)
892 goto out;
893
894 if (!ctx->i80_if)
895 drm_crtc_handle_vblank(&ctx->crtc->base);
896
897 for (win = 0 ; win < WINDOWS_NR ; win++) {
898 struct exynos_drm_plane *plane = &ctx->planes[win];
899
900 if (!plane->pending_fb)
901 continue;
902
903 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
904 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
905 if (start == start_s)
906 exynos_drm_crtc_finish_update(ctx->crtc, plane);
907 }
908
909 if (ctx->i80_if) {
910 /* Exits triggering mode */
911 atomic_set(&ctx->triggering, 0);
912 } else {
913 /* set wait vsync event to zero and wake up queue. */
914 if (atomic_read(&ctx->wait_vsync_event)) {
915 atomic_set(&ctx->wait_vsync_event, 0);
916 wake_up(&ctx->wait_vsync_queue);
917 }
918 }
919
920 out:
921 return IRQ_HANDLED;
922 }
923
924 static int fimd_bind(struct device *dev, struct device *master, void *data)
925 {
926 struct fimd_context *ctx = dev_get_drvdata(dev);
927 struct drm_device *drm_dev = data;
928 struct exynos_drm_private *priv = drm_dev->dev_private;
929 struct exynos_drm_plane *exynos_plane;
930 enum drm_plane_type type;
931 unsigned int zpos;
932 int ret;
933
934 ctx->drm_dev = drm_dev;
935 ctx->pipe = priv->pipe++;
936
937 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
938 type = exynos_plane_get_type(zpos, CURSOR_WIN);
939 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
940 1 << ctx->pipe, type, fimd_formats,
941 ARRAY_SIZE(fimd_formats), zpos);
942 if (ret)
943 return ret;
944 }
945
946 exynos_plane = &ctx->planes[DEFAULT_WIN];
947 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
948 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
949 &fimd_crtc_ops, ctx);
950 if (IS_ERR(ctx->crtc))
951 return PTR_ERR(ctx->crtc);
952
953 if (ctx->encoder)
954 exynos_dpi_bind(drm_dev, ctx->encoder);
955
956 if (is_drm_iommu_supported(drm_dev))
957 fimd_clear_channels(ctx->crtc);
958
959 ret = drm_iommu_attach_device(drm_dev, dev);
960 if (ret)
961 priv->pipe--;
962
963 return ret;
964 }
965
966 static void fimd_unbind(struct device *dev, struct device *master,
967 void *data)
968 {
969 struct fimd_context *ctx = dev_get_drvdata(dev);
970
971 fimd_disable(ctx->crtc);
972
973 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
974
975 if (ctx->encoder)
976 exynos_dpi_remove(ctx->encoder);
977 }
978
979 static const struct component_ops fimd_component_ops = {
980 .bind = fimd_bind,
981 .unbind = fimd_unbind,
982 };
983
984 static int fimd_probe(struct platform_device *pdev)
985 {
986 struct device *dev = &pdev->dev;
987 struct fimd_context *ctx;
988 struct device_node *i80_if_timings;
989 struct resource *res;
990 int ret;
991
992 if (!dev->of_node)
993 return -ENODEV;
994
995 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
996 if (!ctx)
997 return -ENOMEM;
998
999 ctx->dev = dev;
1000 ctx->suspended = true;
1001 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1002
1003 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1004 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1005 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1006 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1007
1008 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1009 if (i80_if_timings) {
1010 u32 val;
1011
1012 ctx->i80_if = true;
1013
1014 if (ctx->driver_data->has_vidoutcon)
1015 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1016 else
1017 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1018 /*
1019 * The user manual describes that this "DSI_EN" bit is required
1020 * to enable I80 24-bit data interface.
1021 */
1022 ctx->vidcon0 |= VIDCON0_DSI_EN;
1023
1024 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1025 val = 0;
1026 ctx->i80ifcon = LCD_CS_SETUP(val);
1027 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1028 val = 0;
1029 ctx->i80ifcon |= LCD_WR_SETUP(val);
1030 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1031 val = 1;
1032 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1033 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1034 val = 0;
1035 ctx->i80ifcon |= LCD_WR_HOLD(val);
1036 }
1037 of_node_put(i80_if_timings);
1038
1039 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1040 "samsung,sysreg");
1041 if (IS_ERR(ctx->sysreg)) {
1042 dev_warn(dev, "failed to get system register.\n");
1043 ctx->sysreg = NULL;
1044 }
1045
1046 ctx->bus_clk = devm_clk_get(dev, "fimd");
1047 if (IS_ERR(ctx->bus_clk)) {
1048 dev_err(dev, "failed to get bus clock\n");
1049 return PTR_ERR(ctx->bus_clk);
1050 }
1051
1052 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1053 if (IS_ERR(ctx->lcd_clk)) {
1054 dev_err(dev, "failed to get lcd clock\n");
1055 return PTR_ERR(ctx->lcd_clk);
1056 }
1057
1058 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1059
1060 ctx->regs = devm_ioremap_resource(dev, res);
1061 if (IS_ERR(ctx->regs))
1062 return PTR_ERR(ctx->regs);
1063
1064 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1065 ctx->i80_if ? "lcd_sys" : "vsync");
1066 if (!res) {
1067 dev_err(dev, "irq request failed.\n");
1068 return -ENXIO;
1069 }
1070
1071 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1072 0, "drm_fimd", ctx);
1073 if (ret) {
1074 dev_err(dev, "irq request failed.\n");
1075 return ret;
1076 }
1077
1078 init_waitqueue_head(&ctx->wait_vsync_queue);
1079 atomic_set(&ctx->wait_vsync_event, 0);
1080
1081 platform_set_drvdata(pdev, ctx);
1082
1083 ctx->encoder = exynos_dpi_probe(dev);
1084 if (IS_ERR(ctx->encoder))
1085 return PTR_ERR(ctx->encoder);
1086
1087 pm_runtime_enable(dev);
1088
1089 ret = component_add(dev, &fimd_component_ops);
1090 if (ret)
1091 goto err_disable_pm_runtime;
1092
1093 return ret;
1094
1095 err_disable_pm_runtime:
1096 pm_runtime_disable(dev);
1097
1098 return ret;
1099 }
1100
1101 static int fimd_remove(struct platform_device *pdev)
1102 {
1103 pm_runtime_disable(&pdev->dev);
1104
1105 component_del(&pdev->dev, &fimd_component_ops);
1106
1107 return 0;
1108 }
1109
1110 #ifdef CONFIG_PM
1111 static int exynos_fimd_suspend(struct device *dev)
1112 {
1113 struct fimd_context *ctx = dev_get_drvdata(dev);
1114
1115 clk_disable_unprepare(ctx->lcd_clk);
1116 clk_disable_unprepare(ctx->bus_clk);
1117
1118 return 0;
1119 }
1120
1121 static int exynos_fimd_resume(struct device *dev)
1122 {
1123 struct fimd_context *ctx = dev_get_drvdata(dev);
1124 int ret;
1125
1126 ret = clk_prepare_enable(ctx->bus_clk);
1127 if (ret < 0) {
1128 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1129 return ret;
1130 }
1131
1132 ret = clk_prepare_enable(ctx->lcd_clk);
1133 if (ret < 0) {
1134 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1135 return ret;
1136 }
1137
1138 return 0;
1139 }
1140 #endif
1141
1142 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1143 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1144 };
1145
1146 struct platform_driver fimd_driver = {
1147 .probe = fimd_probe,
1148 .remove = fimd_remove,
1149 .driver = {
1150 .name = "exynos4-fb",
1151 .owner = THIS_MODULE,
1152 .pm = &exynos_fimd_pm_ops,
1153 .of_match_table = fimd_driver_dt_match,
1154 },
1155 };
Linux kernel - Deliverables
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