projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
power: supply: sbs-battery: simplify DT parsing
[deliverable/linux.git] / drivers / gpu / drm / hisilicon / kirin / kirin_drm_ade.c
1 /*
2 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
3 *
4 * Copyright (c) 2016 Linaro Limited.
5 * Copyright (c) 2014-2016 Hisilicon Limited.
6 *
7 * Author:
8 * Xinliang Liu <z.liuxinliang@hisilicon.com>
9 * Xinliang Liu <xinliang.liu@linaro.org>
10 * Xinwei Kong <kong.kongxinwei@hisilicon.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <video/display_timing.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24
25 #include <drm/drmP.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_gem_cma_helper.h>
32 #include <drm/drm_fb_cma_helper.h>
33
34 #include "kirin_drm_drv.h"
35 #include "kirin_ade_reg.h"
36
37 #define PRIMARY_CH ADE_CH1 /* primary plane */
38 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */
39 #define ADE_DEBUG 1
40
41 #define to_ade_crtc(crtc) \
42 container_of(crtc, struct ade_crtc, base)
43
44 #define to_ade_plane(plane) \
45 container_of(plane, struct ade_plane, base)
46
47 struct ade_hw_ctx {
48 void __iomem *base;
49 struct regmap *noc_regmap;
50 struct clk *ade_core_clk;
51 struct clk *media_noc_clk;
52 struct clk *ade_pix_clk;
53 struct reset_control *reset;
54 bool power_on;
55 int irq;
56 };
57
58 struct ade_crtc {
59 struct drm_crtc base;
60 struct ade_hw_ctx *ctx;
61 bool enable;
62 u32 out_format;
63 };
64
65 struct ade_plane {
66 struct drm_plane base;
67 void *ctx;
68 u8 ch; /* channel */
69 };
70
71 struct ade_data {
72 struct ade_crtc acrtc;
73 struct ade_plane aplane[ADE_CH_NUM];
74 struct ade_hw_ctx ctx;
75 };
76
77 /* ade-format info: */
78 struct ade_format {
79 u32 pixel_format;
80 enum ade_fb_format ade_format;
81 };
82
83 static const struct ade_format ade_formats[] = {
84 /* 16bpp RGB: */
85 { DRM_FORMAT_RGB565, ADE_RGB_565 },
86 { DRM_FORMAT_BGR565, ADE_BGR_565 },
87 /* 24bpp RGB: */
88 { DRM_FORMAT_RGB888, ADE_RGB_888 },
89 { DRM_FORMAT_BGR888, ADE_BGR_888 },
90 /* 32bpp [A]RGB: */
91 { DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
92 { DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
93 { DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
94 { DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
95 { DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
96 { DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
97 };
98
99 static const u32 channel_formats1[] = {
100 /* channel 1,2,3,4 */
101 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
102 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
103 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
104 DRM_FORMAT_ABGR8888
105 };
106
107 u32 ade_get_channel_formats(u8 ch, const u32 **formats)
108 {
109 switch (ch) {
110 case ADE_CH1:
111 *formats = channel_formats1;
112 return ARRAY_SIZE(channel_formats1);
113 default:
114 DRM_ERROR("no this channel %d\n", ch);
115 *formats = NULL;
116 return 0;
117 }
118 }
119
120 /* convert from fourcc format to ade format */
121 static u32 ade_get_format(u32 pixel_format)
122 {
123 int i;
124
125 for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
126 if (ade_formats[i].pixel_format == pixel_format)
127 return ade_formats[i].ade_format;
128
129 /* not found */
130 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
131 pixel_format);
132 return ADE_FORMAT_UNSUPPORT;
133 }
134
135 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
136 {
137 u32 bit_ofst, reg_num;
138
139 bit_ofst = bit_num % 32;
140 reg_num = bit_num / 32;
141
142 ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
143 MASK(1), !!val);
144 }
145
146 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
147 {
148 u32 tmp, bit_ofst, reg_num;
149
150 bit_ofst = bit_num % 32;
151 reg_num = bit_num / 32;
152
153 tmp = readl(base + ADE_RELOAD_DIS(reg_num));
154 return !!(BIT(bit_ofst) & tmp);
155 }
156
157 static void ade_init(struct ade_hw_ctx *ctx)
158 {
159 void __iomem *base = ctx->base;
160
161 /* enable clk gate */
162 ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
163 AUTO_CLK_GATE_EN, ADE_ENABLE);
164 /* clear overlay */
165 writel(0, base + ADE_OVLY1_TRANS_CFG);
166 writel(0, base + ADE_OVLY_CTL);
167 writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
168 /* clear reset and reload regs */
169 writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
170 writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
171 writel(MASK(32), base + ADE_RELOAD_DIS(0));
172 writel(MASK(32), base + ADE_RELOAD_DIS(1));
173 /*
174 * for video mode, all the ade registers should
175 * become effective at frame end.
176 */
177 ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
178 FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
179 }
180
181 static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
182 struct drm_display_mode *mode,
183 struct drm_display_mode *adj_mode)
184 {
185 u32 clk_Hz = mode->clock * 1000;
186 int ret;
187
188 /*
189 * Success should be guaranteed in mode_valid call back,
190 * so failure shouldn't happen here
191 */
192 ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz);
193 if (ret)
194 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret);
195 adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
196 }
197
198 static void ade_ldi_set_mode(struct ade_crtc *acrtc,
199 struct drm_display_mode *mode,
200 struct drm_display_mode *adj_mode)
201 {
202 struct ade_hw_ctx *ctx = acrtc->ctx;
203 void __iomem *base = ctx->base;
204 u32 width = mode->hdisplay;
205 u32 height = mode->vdisplay;
206 u32 hfp, hbp, hsw, vfp, vbp, vsw;
207 u32 plr_flags;
208
209 plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0;
210 plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0;
211 hfp = mode->hsync_start - mode->hdisplay;
212 hbp = mode->htotal - mode->hsync_end;
213 hsw = mode->hsync_end - mode->hsync_start;
214 vfp = mode->vsync_start - mode->vdisplay;
215 vbp = mode->vtotal - mode->vsync_end;
216 vsw = mode->vsync_end - mode->vsync_start;
217 if (vsw > 15) {
218 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
219 vsw = 15;
220 }
221
222 writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
223 /* the configured value is actual value - 1 */
224 writel(hsw - 1, base + LDI_HRZ_CTRL1);
225 writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
226 /* the configured value is actual value - 1 */
227 writel(vsw - 1, base + LDI_VRT_CTRL1);
228 /* the configured value is actual value - 1 */
229 writel(((height - 1) << VSIZE_OFST) | (width - 1),
230 base + LDI_DSP_SIZE);
231 writel(plr_flags, base + LDI_PLR_CTRL);
232
233 /* set overlay compositor output size */
234 writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
235 base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
236
237 /* ctran6 setting */
238 writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
239 /* the configured value is actual value - 1 */
240 writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
241 ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
242
243 ade_set_pix_clk(ctx, mode, adj_mode);
244
245 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
246 }
247
248 static int ade_power_up(struct ade_hw_ctx *ctx)
249 {
250 int ret;
251
252 ret = clk_prepare_enable(ctx->media_noc_clk);
253 if (ret) {
254 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
255 return ret;
256 }
257
258 ret = reset_control_deassert(ctx->reset);
259 if (ret) {
260 DRM_ERROR("failed to deassert reset\n");
261 return ret;
262 }
263
264 ret = clk_prepare_enable(ctx->ade_core_clk);
265 if (ret) {
266 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
267 return ret;
268 }
269
270 ade_init(ctx);
271 ctx->power_on = true;
272 return 0;
273 }
274
275 static void ade_power_down(struct ade_hw_ctx *ctx)
276 {
277 void __iomem *base = ctx->base;
278
279 writel(ADE_DISABLE, base + LDI_CTRL);
280 /* dsi pixel off */
281 writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
282
283 clk_disable_unprepare(ctx->ade_core_clk);
284 reset_control_assert(ctx->reset);
285 clk_disable_unprepare(ctx->media_noc_clk);
286 ctx->power_on = false;
287 }
288
289 static void ade_set_medianoc_qos(struct ade_crtc *acrtc)
290 {
291 struct ade_hw_ctx *ctx = acrtc->ctx;
292 struct regmap *map = ctx->noc_regmap;
293
294 regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
295 QOSGENERATOR_MODE_MASK, BYPASS_MODE);
296 regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
297 SOCKET_QOS_EN, SOCKET_QOS_EN);
298
299 regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
300 QOSGENERATOR_MODE_MASK, BYPASS_MODE);
301 regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
302 SOCKET_QOS_EN, SOCKET_QOS_EN);
303 }
304
305 static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe)
306 {
307 struct kirin_drm_private *priv = dev->dev_private;
308 struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
309 struct ade_hw_ctx *ctx = acrtc->ctx;
310 void __iomem *base = ctx->base;
311
312 if (!ctx->power_on)
313 (void)ade_power_up(ctx);
314
315 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
316 MASK(1), 1);
317
318 return 0;
319 }
320
321 static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe)
322 {
323 struct kirin_drm_private *priv = dev->dev_private;
324 struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
325 struct ade_hw_ctx *ctx = acrtc->ctx;
326 void __iomem *base = ctx->base;
327
328 if (!ctx->power_on) {
329 DRM_ERROR("power is down! vblank disable fail\n");
330 return;
331 }
332
333 ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
334 MASK(1), 0);
335 }
336
337 static irqreturn_t ade_irq_handler(int irq, void *data)
338 {
339 struct ade_crtc *acrtc = data;
340 struct ade_hw_ctx *ctx = acrtc->ctx;
341 struct drm_crtc *crtc = &acrtc->base;
342 void __iomem *base = ctx->base;
343 u32 status;
344
345 status = readl(base + LDI_MSK_INT);
346 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
347
348 /* vblank irq */
349 if (status & BIT(FRAME_END_INT_EN_OFST)) {
350 ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
351 MASK(1), 1);
352 drm_crtc_handle_vblank(crtc);
353 }
354
355 return IRQ_HANDLED;
356 }
357
358 static void ade_display_enable(struct ade_crtc *acrtc)
359 {
360 struct ade_hw_ctx *ctx = acrtc->ctx;
361 void __iomem *base = ctx->base;
362 u32 out_fmt = acrtc->out_format;
363
364 /* enable output overlay compositor */
365 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
366 ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
367
368 /* display source setting */
369 writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
370
371 /* enable ade */
372 writel(ADE_ENABLE, base + ADE_EN);
373 /* enable ldi */
374 writel(NORMAL_MODE, base + LDI_WORK_MODE);
375 writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
376 base + LDI_CTRL);
377 /* dsi pixel on */
378 writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
379 }
380
381 #if ADE_DEBUG
382 static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
383 {
384 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
385 u32 val;
386
387 reg_ctrl = RD_CH_CTRL(ch);
388 reg_addr = RD_CH_ADDR(ch);
389 reg_size = RD_CH_SIZE(ch);
390 reg_stride = RD_CH_STRIDE(ch);
391 reg_space = RD_CH_SPACE(ch);
392 reg_en = RD_CH_EN(ch);
393
394 val = ade_read_reload_bit(base, RDMA_OFST + ch);
395 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
396 val = readl(base + reg_ctrl);
397 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
398 val = readl(base + reg_addr);
399 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
400 val = readl(base + reg_size);
401 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
402 val = readl(base + reg_stride);
403 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
404 val = readl(base + reg_space);
405 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
406 val = readl(base + reg_en);
407 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
408 }
409
410 static void ade_clip_dump_regs(void __iomem *base, u32 ch)
411 {
412 u32 val;
413
414 val = ade_read_reload_bit(base, CLIP_OFST + ch);
415 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
416 val = readl(base + ADE_CLIP_DISABLE(ch));
417 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
418 val = readl(base + ADE_CLIP_SIZE0(ch));
419 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
420 val = readl(base + ADE_CLIP_SIZE1(ch));
421 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
422 }
423
424 static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
425 {
426 u8 ovly_ch = 0; /* TODO: Only primary plane now */
427 u32 val;
428
429 val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
430 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
431 val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
432 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
433 val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
434 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
435 }
436
437 static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
438 {
439 u32 val;
440
441 val = ade_read_reload_bit(base, OVLY_OFST + comp);
442 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
443 writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
444 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
445 val = readl(base + ADE_OVLY_CTL);
446 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
447 }
448
449 static void ade_dump_regs(void __iomem *base)
450 {
451 u32 i;
452
453 /* dump channel regs */
454 for (i = 0; i < ADE_CH_NUM; i++) {
455 /* dump rdma regs */
456 ade_rdma_dump_regs(base, i);
457
458 /* dump clip regs */
459 ade_clip_dump_regs(base, i);
460
461 /* dump compositor routing regs */
462 ade_compositor_routing_dump_regs(base, i);
463 }
464
465 /* dump overlay compositor regs */
466 ade_dump_overlay_compositor_regs(base, OUT_OVLY);
467 }
468 #else
469 static void ade_dump_regs(void __iomem *base) { }
470 #endif
471
472 static void ade_crtc_enable(struct drm_crtc *crtc)
473 {
474 struct ade_crtc *acrtc = to_ade_crtc(crtc);
475 struct ade_hw_ctx *ctx = acrtc->ctx;
476 int ret;
477
478 if (acrtc->enable)
479 return;
480
481 if (!ctx->power_on) {
482 ret = ade_power_up(ctx);
483 if (ret)
484 return;
485 }
486
487 ade_set_medianoc_qos(acrtc);
488 ade_display_enable(acrtc);
489 ade_dump_regs(ctx->base);
490 drm_crtc_vblank_on(crtc);
491 acrtc->enable = true;
492 }
493
494 static void ade_crtc_disable(struct drm_crtc *crtc)
495 {
496 struct ade_crtc *acrtc = to_ade_crtc(crtc);
497 struct ade_hw_ctx *ctx = acrtc->ctx;
498
499 if (!acrtc->enable)
500 return;
501
502 drm_crtc_vblank_off(crtc);
503 ade_power_down(ctx);
504 acrtc->enable = false;
505 }
506
507 static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
508 {
509 struct ade_crtc *acrtc = to_ade_crtc(crtc);
510 struct ade_hw_ctx *ctx = acrtc->ctx;
511 struct drm_display_mode *mode = &crtc->state->mode;
512 struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
513
514 if (!ctx->power_on)
515 (void)ade_power_up(ctx);
516 ade_ldi_set_mode(acrtc, mode, adj_mode);
517 }
518
519 static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
520 struct drm_crtc_state *old_state)
521 {
522 struct ade_crtc *acrtc = to_ade_crtc(crtc);
523 struct ade_hw_ctx *ctx = acrtc->ctx;
524
525 if (!ctx->power_on)
526 (void)ade_power_up(ctx);
527 }
528
529 static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
530 struct drm_crtc_state *old_state)
531
532 {
533 struct ade_crtc *acrtc = to_ade_crtc(crtc);
534 struct ade_hw_ctx *ctx = acrtc->ctx;
535 struct drm_pending_vblank_event *event = crtc->state->event;
536 void __iomem *base = ctx->base;
537
538 /* only crtc is enabled regs take effect */
539 if (acrtc->enable) {
540 ade_dump_regs(base);
541 /* flush ade registers */
542 writel(ADE_ENABLE, base + ADE_EN);
543 }
544
545 if (event) {
546 crtc->state->event = NULL;
547
548 spin_lock_irq(&crtc->dev->event_lock);
549 if (drm_crtc_vblank_get(crtc) == 0)
550 drm_crtc_arm_vblank_event(crtc, event);
551 else
552 drm_crtc_send_vblank_event(crtc, event);
553 spin_unlock_irq(&crtc->dev->event_lock);
554 }
555 }
556
557 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {
558 .enable = ade_crtc_enable,
559 .disable = ade_crtc_disable,
560 .mode_set_nofb = ade_crtc_mode_set_nofb,
561 .atomic_begin = ade_crtc_atomic_begin,
562 .atomic_flush = ade_crtc_atomic_flush,
563 };
564
565 static const struct drm_crtc_funcs ade_crtc_funcs = {
566 .destroy = drm_crtc_cleanup,
567 .set_config = drm_atomic_helper_set_config,
568 .page_flip = drm_atomic_helper_page_flip,
569 .reset = drm_atomic_helper_crtc_reset,
570 .set_property = drm_atomic_helper_crtc_set_property,
571 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
572 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
573 };
574
575 static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
576 struct drm_plane *plane)
577 {
578 struct kirin_drm_private *priv = dev->dev_private;
579 struct device_node *port;
580 int ret;
581
582 /* set crtc port so that
583 * drm_of_find_possible_crtcs call works
584 */
585 port = of_get_child_by_name(dev->dev->of_node, "port");
586 if (!port) {
587 DRM_ERROR("no port node found in %s\n",
588 dev->dev->of_node->full_name);
589 return -EINVAL;
590 }
591 of_node_put(port);
592 crtc->port = port;
593
594 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
595 &ade_crtc_funcs, NULL);
596 if (ret) {
597 DRM_ERROR("failed to init crtc.\n");
598 return ret;
599 }
600
601 drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs);
602 priv->crtc[drm_crtc_index(crtc)] = crtc;
603
604 return 0;
605 }
606
607 static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
608 u32 ch, u32 y, u32 in_h, u32 fmt)
609 {
610 struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, 0);
611 u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
612 u32 stride = fb->pitches[0];
613 u32 addr = (u32)obj->paddr + y * stride;
614
615 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
616 ch + 1, y, in_h, stride, (u32)obj->paddr);
617 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
618 addr, fb->width, fb->height, fmt,
619 drm_get_format_name(fb->pixel_format));
620
621 /* get reg offset */
622 reg_ctrl = RD_CH_CTRL(ch);
623 reg_addr = RD_CH_ADDR(ch);
624 reg_size = RD_CH_SIZE(ch);
625 reg_stride = RD_CH_STRIDE(ch);
626 reg_space = RD_CH_SPACE(ch);
627 reg_en = RD_CH_EN(ch);
628
629 /*
630 * TODO: set rotation
631 */
632 writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
633 writel(addr, base + reg_addr);
634 writel((in_h << 16) | stride, base + reg_size);
635 writel(stride, base + reg_stride);
636 writel(in_h * stride, base + reg_space);
637 writel(ADE_ENABLE, base + reg_en);
638 ade_update_reload_bit(base, RDMA_OFST + ch, 0);
639 }
640
641 static void ade_rdma_disable(void __iomem *base, u32 ch)
642 {
643 u32 reg_en;
644
645 /* get reg offset */
646 reg_en = RD_CH_EN(ch);
647 writel(0, base + reg_en);
648 ade_update_reload_bit(base, RDMA_OFST + ch, 1);
649 }
650
651 static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
652 u32 in_w, u32 in_h)
653 {
654 u32 disable_val;
655 u32 clip_left;
656 u32 clip_right;
657
658 /*
659 * clip width, no need to clip height
660 */
661 if (fb_w == in_w) { /* bypass */
662 disable_val = 1;
663 clip_left = 0;
664 clip_right = 0;
665 } else {
666 disable_val = 0;
667 clip_left = x;
668 clip_right = fb_w - (x + in_w) - 1;
669 }
670
671 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
672 ch + 1, clip_left, clip_right);
673
674 writel(disable_val, base + ADE_CLIP_DISABLE(ch));
675 writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
676 writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
677 ade_update_reload_bit(base, CLIP_OFST + ch, 0);
678 }
679
680 static void ade_clip_disable(void __iomem *base, u32 ch)
681 {
682 writel(1, base + ADE_CLIP_DISABLE(ch));
683 ade_update_reload_bit(base, CLIP_OFST + ch, 1);
684 }
685
686 static bool has_Alpha_channel(int format)
687 {
688 switch (format) {
689 case ADE_ARGB_8888:
690 case ADE_ABGR_8888:
691 case ADE_RGBA_8888:
692 case ADE_BGRA_8888:
693 return true;
694 default:
695 return false;
696 }
697 }
698
699 static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
700 u8 *alp_sel, u8 *under_alp_sel)
701 {
702 bool has_alpha = has_Alpha_channel(fmt);
703
704 /*
705 * get alp_mode
706 */
707 if (has_alpha && glb_alpha < 255)
708 *alp_mode = ADE_ALP_PIXEL_AND_GLB;
709 else if (has_alpha)
710 *alp_mode = ADE_ALP_PIXEL;
711 else
712 *alp_mode = ADE_ALP_GLOBAL;
713
714 /*
715 * get alp sel
716 */
717 *alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
718 *under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */
719 }
720
721 static void ade_compositor_routing_set(void __iomem *base, u8 ch,
722 u32 x0, u32 y0,
723 u32 in_w, u32 in_h, u32 fmt)
724 {
725 u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */
726 u8 glb_alpha = 255;
727 u32 x1 = x0 + in_w - 1;
728 u32 y1 = y0 + in_h - 1;
729 u32 val;
730 u8 alp_sel;
731 u8 under_alp_sel;
732 u8 alp_mode;
733
734 ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
735 &under_alp_sel);
736
737 /* overlay routing setting
738 */
739 writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
740 writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
741 val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
742 alp_sel << CH_ALP_SEL_OFST |
743 under_alp_sel << CH_UNDER_ALP_SEL_OFST |
744 glb_alpha << CH_ALP_GBL_OFST |
745 alp_mode << CH_ALP_MODE_OFST;
746 writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
747 /* connect this plane/channel to overlay2 compositor */
748 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
749 CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
750 }
751
752 static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
753 {
754 u8 ovly_ch = 0; /* TODO: Only primary plane now */
755
756 /* disable this plane/channel */
757 ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
758 MASK(1), 0);
759 /* dis-connect this plane/channel of overlay2 compositor */
760 ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
761 CH_OVLY_SEL_MASK, 0);
762 }
763
764 /*
765 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
766 */
767 static void ade_update_channel(struct ade_plane *aplane,
768 struct drm_framebuffer *fb, int crtc_x,
769 int crtc_y, unsigned int crtc_w,
770 unsigned int crtc_h, u32 src_x,
771 u32 src_y, u32 src_w, u32 src_h)
772 {
773 struct ade_hw_ctx *ctx = aplane->ctx;
774 void __iomem *base = ctx->base;
775 u32 fmt = ade_get_format(fb->pixel_format);
776 u32 ch = aplane->ch;
777 u32 in_w;
778 u32 in_h;
779
780 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
781 ch + 1, src_x, src_y, src_w, src_h,
782 crtc_x, crtc_y, crtc_w, crtc_h);
783
784 /* 1) DMA setting */
785 in_w = src_w;
786 in_h = src_h;
787 ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
788
789 /* 2) clip setting */
790 ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
791
792 /* 3) TODO: scale setting for overlay planes */
793
794 /* 4) TODO: ctran/csc setting for overlay planes */
795
796 /* 5) compositor routing setting */
797 ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
798 }
799
800 static void ade_disable_channel(struct ade_plane *aplane)
801 {
802 struct ade_hw_ctx *ctx = aplane->ctx;
803 void __iomem *base = ctx->base;
804 u32 ch = aplane->ch;
805
806 DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
807
808 /* disable read DMA */
809 ade_rdma_disable(base, ch);
810
811 /* disable clip */
812 ade_clip_disable(base, ch);
813
814 /* disable compositor routing */
815 ade_compositor_routing_disable(base, ch);
816 }
817
818 static int ade_plane_prepare_fb(struct drm_plane *plane,
819 const struct drm_plane_state *new_state)
820 {
821 /* do nothing */
822 return 0;
823 }
824
825 static void ade_plane_cleanup_fb(struct drm_plane *plane,
826 const struct drm_plane_state *old_state)
827 {
828 /* do nothing */
829 }
830
831 static int ade_plane_atomic_check(struct drm_plane *plane,
832 struct drm_plane_state *state)
833 {
834 struct drm_framebuffer *fb = state->fb;
835 struct drm_crtc *crtc = state->crtc;
836 struct drm_crtc_state *crtc_state;
837 u32 src_x = state->src_x >> 16;
838 u32 src_y = state->src_y >> 16;
839 u32 src_w = state->src_w >> 16;
840 u32 src_h = state->src_h >> 16;
841 int crtc_x = state->crtc_x;
842 int crtc_y = state->crtc_y;
843 u32 crtc_w = state->crtc_w;
844 u32 crtc_h = state->crtc_h;
845 u32 fmt;
846
847 if (!crtc || !fb)
848 return 0;
849
850 fmt = ade_get_format(fb->pixel_format);
851 if (fmt == ADE_FORMAT_UNSUPPORT)
852 return -EINVAL;
853
854 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
855 if (IS_ERR(crtc_state))
856 return PTR_ERR(crtc_state);
857
858 if (src_w != crtc_w || src_h != crtc_h) {
859 DRM_ERROR("Scale not support!!!\n");
860 return -EINVAL;
861 }
862
863 if (src_x + src_w > fb->width ||
864 src_y + src_h > fb->height)
865 return -EINVAL;
866
867 if (crtc_x < 0 || crtc_y < 0)
868 return -EINVAL;
869
870 if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
871 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
872 return -EINVAL;
873
874 return 0;
875 }
876
877 static void ade_plane_atomic_update(struct drm_plane *plane,
878 struct drm_plane_state *old_state)
879 {
880 struct drm_plane_state *state = plane->state;
881 struct ade_plane *aplane = to_ade_plane(plane);
882
883 ade_update_channel(aplane, state->fb, state->crtc_x, state->crtc_y,
884 state->crtc_w, state->crtc_h,
885 state->src_x >> 16, state->src_y >> 16,
886 state->src_w >> 16, state->src_h >> 16);
887 }
888
889 static void ade_plane_atomic_disable(struct drm_plane *plane,
890 struct drm_plane_state *old_state)
891 {
892 struct ade_plane *aplane = to_ade_plane(plane);
893
894 ade_disable_channel(aplane);
895 }
896
897 static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
898 .prepare_fb = ade_plane_prepare_fb,
899 .cleanup_fb = ade_plane_cleanup_fb,
900 .atomic_check = ade_plane_atomic_check,
901 .atomic_update = ade_plane_atomic_update,
902 .atomic_disable = ade_plane_atomic_disable,
903 };
904
905 static struct drm_plane_funcs ade_plane_funcs = {
906 .update_plane = drm_atomic_helper_update_plane,
907 .disable_plane = drm_atomic_helper_disable_plane,
908 .set_property = drm_atomic_helper_plane_set_property,
909 .destroy = drm_plane_cleanup,
910 .reset = drm_atomic_helper_plane_reset,
911 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
912 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
913 };
914
915 static int ade_plane_init(struct drm_device *dev, struct ade_plane *aplane,
916 enum drm_plane_type type)
917 {
918 const u32 *fmts;
919 u32 fmts_cnt;
920 int ret = 0;
921
922 /* get properties */
923 fmts_cnt = ade_get_channel_formats(aplane->ch, &fmts);
924 if (ret)
925 return ret;
926
927 ret = drm_universal_plane_init(dev, &aplane->base, 1, &ade_plane_funcs,
928 fmts, fmts_cnt, type, NULL);
929 if (ret) {
930 DRM_ERROR("fail to init plane, ch=%d\n", aplane->ch);
931 return ret;
932 }
933
934 drm_plane_helper_add(&aplane->base, &ade_plane_helper_funcs);
935
936 return 0;
937 }
938
939 static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx)
940 {
941 struct resource *res;
942 struct device *dev = &pdev->dev;
943 struct device_node *np = pdev->dev.of_node;
944
945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
946 ctx->base = devm_ioremap_resource(dev, res);
947 if (IS_ERR(ctx->base)) {
948 DRM_ERROR("failed to remap ade io base\n");
949 return PTR_ERR(ctx->base);
950 }
951
952 ctx->reset = devm_reset_control_get(dev, NULL);
953 if (IS_ERR(ctx->reset))
954 return PTR_ERR(ctx->reset);
955
956 ctx->noc_regmap =
957 syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");
958 if (IS_ERR(ctx->noc_regmap)) {
959 DRM_ERROR("failed to get noc regmap\n");
960 return PTR_ERR(ctx->noc_regmap);
961 }
962
963 ctx->irq = platform_get_irq(pdev, 0);
964 if (ctx->irq < 0) {
965 DRM_ERROR("failed to get irq\n");
966 return -ENODEV;
967 }
968
969 ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
970 if (IS_ERR(ctx->ade_core_clk)) {
971 DRM_ERROR("failed to parse clk ADE_CORE\n");
972 return PTR_ERR(ctx->ade_core_clk);
973 }
974
975 ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
976 if (IS_ERR(ctx->media_noc_clk)) {
977 DRM_ERROR("failed to parse clk CODEC_JPEG\n");
978 return PTR_ERR(ctx->media_noc_clk);
979 }
980
981 ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
982 if (IS_ERR(ctx->ade_pix_clk)) {
983 DRM_ERROR("failed to parse clk ADE_PIX\n");
984 return PTR_ERR(ctx->ade_pix_clk);
985 }
986
987 return 0;
988 }
989
990 static int ade_drm_init(struct drm_device *dev)
991 {
992 struct platform_device *pdev = dev->platformdev;
993 struct ade_data *ade;
994 struct ade_hw_ctx *ctx;
995 struct ade_crtc *acrtc;
996 struct ade_plane *aplane;
997 enum drm_plane_type type;
998 int ret;
999 int i;
1000
1001 ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL);
1002 if (!ade) {
1003 DRM_ERROR("failed to alloc ade_data\n");
1004 return -ENOMEM;
1005 }
1006 platform_set_drvdata(pdev, ade);
1007
1008 ctx = &ade->ctx;
1009 acrtc = &ade->acrtc;
1010 acrtc->ctx = ctx;
1011 acrtc->out_format = LDI_OUT_RGB_888;
1012
1013 ret = ade_dts_parse(pdev, ctx);
1014 if (ret)
1015 return ret;
1016
1017 /*
1018 * plane init
1019 * TODO: Now only support primary plane, overlay planes
1020 * need to do.
1021 */
1022 for (i = 0; i < ADE_CH_NUM; i++) {
1023 aplane = &ade->aplane[i];
1024 aplane->ch = i;
1025 aplane->ctx = ctx;
1026 type = i == PRIMARY_CH ? DRM_PLANE_TYPE_PRIMARY :
1027 DRM_PLANE_TYPE_OVERLAY;
1028
1029 ret = ade_plane_init(dev, aplane, type);
1030 if (ret)
1031 return ret;
1032 }
1033
1034 /* crtc init */
1035 ret = ade_crtc_init(dev, &acrtc->base, &ade->aplane[PRIMARY_CH].base);
1036 if (ret)
1037 return ret;
1038
1039 /* vblank irq init */
1040 ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
1041 IRQF_SHARED, dev->driver->name, acrtc);
1042 if (ret)
1043 return ret;
1044 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
1045 dev->driver->enable_vblank = ade_enable_vblank;
1046 dev->driver->disable_vblank = ade_disable_vblank;
1047
1048 return 0;
1049 }
1050
1051 static void ade_drm_cleanup(struct drm_device *dev)
1052 {
1053 struct platform_device *pdev = dev->platformdev;
1054 struct ade_data *ade = platform_get_drvdata(pdev);
1055 struct drm_crtc *crtc = &ade->acrtc.base;
1056
1057 drm_crtc_cleanup(crtc);
1058 }
1059
1060 const struct kirin_dc_ops ade_dc_ops = {
1061 .init = ade_drm_init,
1062 .cleanup = ade_drm_cleanup
1063 };
Linux kernel - Deliverables
This page took 0.073328 seconds and 5 git commands to generate.