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drm/i915: Convert dev_priv->dev backpointers to dev_priv->drm
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static char get_active_flag(struct drm_i915_gem_object *obj)
93 {
94 return obj->active ? '*' : ' ';
95 }
96
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 return obj->pin_display ? 'p' : ' ';
100 }
101
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110 }
111
112 static char get_global_flag(struct drm_i915_gem_object *obj)
113 {
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115 }
116
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->mapping ? 'M' : ' ';
120 }
121
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 {
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133 }
134
135 static void
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 {
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200 }
201
202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
203 {
204 struct drm_info_node *node = m->private;
205 uintptr_t list = (uintptr_t) node->info_ent->data;
206 struct list_head *head;
207 struct drm_device *dev = node->minor->dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 struct i915_ggtt *ggtt = &dev_priv->ggtt;
210 struct i915_vma *vma;
211 u64 total_obj_size, total_gtt_size;
212 int count, ret;
213
214 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 if (ret)
216 return ret;
217
218 /* FIXME: the user of this interface might want more than just GGTT */
219 switch (list) {
220 case ACTIVE_LIST:
221 seq_puts(m, "Active:\n");
222 head = &ggtt->base.active_list;
223 break;
224 case INACTIVE_LIST:
225 seq_puts(m, "Inactive:\n");
226 head = &ggtt->base.inactive_list;
227 break;
228 default:
229 mutex_unlock(&dev->struct_mutex);
230 return -EINVAL;
231 }
232
233 total_obj_size = total_gtt_size = count = 0;
234 list_for_each_entry(vma, head, vm_link) {
235 seq_printf(m, " ");
236 describe_obj(m, vma->obj);
237 seq_printf(m, "\n");
238 total_obj_size += vma->obj->base.size;
239 total_gtt_size += vma->node.size;
240 count++;
241 }
242 mutex_unlock(&dev->struct_mutex);
243
244 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
245 count, total_obj_size, total_gtt_size);
246 return 0;
247 }
248
249 static int obj_rank_by_stolen(void *priv,
250 struct list_head *A, struct list_head *B)
251 {
252 struct drm_i915_gem_object *a =
253 container_of(A, struct drm_i915_gem_object, obj_exec_link);
254 struct drm_i915_gem_object *b =
255 container_of(B, struct drm_i915_gem_object, obj_exec_link);
256
257 if (a->stolen->start < b->stolen->start)
258 return -1;
259 if (a->stolen->start > b->stolen->start)
260 return 1;
261 return 0;
262 }
263
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265 {
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = to_i915(dev);
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
283 list_add(&obj->obj_exec_link, &stolen);
284
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
293 list_add(&obj->obj_exec_link, &stolen);
294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
305 list_del_init(&obj->obj_exec_link);
306 }
307 mutex_unlock(&dev->struct_mutex);
308
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
311 return 0;
312 }
313
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
317 ++count; \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
320 ++mappable_count; \
321 } \
322 } \
323 } while (0)
324
325 struct file_stats {
326 struct drm_i915_file_private *file_priv;
327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
331 };
332
333 static int per_file_stats(int id, void *ptr, void *data)
334 {
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
338
339 stats->count++;
340 stats->total += obj->base.size;
341
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, obj_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (vma->is_ggtt) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
359 continue;
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
368 } else {
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
371 if (obj->active)
372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
377 }
378
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
382 return 0;
383 }
384
385 #define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396 } while (0)
397
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400 {
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *engine;
404 int j;
405
406 memset(&stats, 0, sizeof(stats));
407
408 for_each_engine(engine, dev_priv) {
409 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &engine->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
415 }
416
417 print_file_stats(m, "[k]batch pool", stats);
418 }
419
420 static int per_file_ctx_stats(int id, void *ptr, void *data)
421 {
422 struct i915_gem_context *ctx = ptr;
423 int n;
424
425 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
426 if (ctx->engine[n].state)
427 per_file_stats(0, ctx->engine[n].state, data);
428 if (ctx->engine[n].ringbuf)
429 per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
430 }
431
432 return 0;
433 }
434
435 static void print_context_stats(struct seq_file *m,
436 struct drm_i915_private *dev_priv)
437 {
438 struct file_stats stats;
439 struct drm_file *file;
440
441 memset(&stats, 0, sizeof(stats));
442
443 mutex_lock(&dev_priv->drm.struct_mutex);
444 if (dev_priv->kernel_context)
445 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
446
447 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
448 struct drm_i915_file_private *fpriv = file->driver_priv;
449 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
450 }
451 mutex_unlock(&dev_priv->drm.struct_mutex);
452
453 print_file_stats(m, "[k]contexts", stats);
454 }
455
456 #define count_vmas(list, member) do { \
457 list_for_each_entry(vma, list, member) { \
458 size += i915_gem_obj_total_ggtt_size(vma->obj); \
459 ++count; \
460 if (vma->obj->map_and_fenceable) { \
461 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
462 ++mappable_count; \
463 } \
464 } \
465 } while (0)
466
467 static int i915_gem_object_info(struct seq_file *m, void* data)
468 {
469 struct drm_info_node *node = m->private;
470 struct drm_device *dev = node->minor->dev;
471 struct drm_i915_private *dev_priv = to_i915(dev);
472 struct i915_ggtt *ggtt = &dev_priv->ggtt;
473 u32 count, mappable_count, purgeable_count;
474 u64 size, mappable_size, purgeable_size;
475 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
476 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
477 struct drm_i915_gem_object *obj;
478 struct drm_file *file;
479 struct i915_vma *vma;
480 int ret;
481
482 ret = mutex_lock_interruptible(&dev->struct_mutex);
483 if (ret)
484 return ret;
485
486 seq_printf(m, "%u objects, %zu bytes\n",
487 dev_priv->mm.object_count,
488 dev_priv->mm.object_memory);
489
490 size = count = mappable_size = mappable_count = 0;
491 count_objects(&dev_priv->mm.bound_list, global_list);
492 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
493 count, mappable_count, size, mappable_size);
494
495 size = count = mappable_size = mappable_count = 0;
496 count_vmas(&ggtt->base.active_list, vm_link);
497 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
498 count, mappable_count, size, mappable_size);
499
500 size = count = mappable_size = mappable_count = 0;
501 count_vmas(&ggtt->base.inactive_list, vm_link);
502 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
503 count, mappable_count, size, mappable_size);
504
505 size = count = purgeable_size = purgeable_count = 0;
506 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
507 size += obj->base.size, ++count;
508 if (obj->madv == I915_MADV_DONTNEED)
509 purgeable_size += obj->base.size, ++purgeable_count;
510 if (obj->mapping) {
511 pin_mapped_count++;
512 pin_mapped_size += obj->base.size;
513 if (obj->pages_pin_count == 0) {
514 pin_mapped_purgeable_count++;
515 pin_mapped_purgeable_size += obj->base.size;
516 }
517 }
518 }
519 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
520
521 size = count = mappable_size = mappable_count = 0;
522 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
523 if (obj->fault_mappable) {
524 size += i915_gem_obj_ggtt_size(obj);
525 ++count;
526 }
527 if (obj->pin_display) {
528 mappable_size += i915_gem_obj_ggtt_size(obj);
529 ++mappable_count;
530 }
531 if (obj->madv == I915_MADV_DONTNEED) {
532 purgeable_size += obj->base.size;
533 ++purgeable_count;
534 }
535 if (obj->mapping) {
536 pin_mapped_count++;
537 pin_mapped_size += obj->base.size;
538 if (obj->pages_pin_count == 0) {
539 pin_mapped_purgeable_count++;
540 pin_mapped_purgeable_size += obj->base.size;
541 }
542 }
543 }
544 seq_printf(m, "%u purgeable objects, %llu bytes\n",
545 purgeable_count, purgeable_size);
546 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
547 mappable_count, mappable_size);
548 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
549 count, size);
550 seq_printf(m,
551 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
552 pin_mapped_count, pin_mapped_purgeable_count,
553 pin_mapped_size, pin_mapped_purgeable_size);
554
555 seq_printf(m, "%llu [%llu] gtt total\n",
556 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
557
558 seq_putc(m, '\n');
559 print_batch_pool_stats(m, dev_priv);
560 mutex_unlock(&dev->struct_mutex);
561
562 mutex_lock(&dev->filelist_mutex);
563 print_context_stats(m, dev_priv);
564 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
565 struct file_stats stats;
566 struct task_struct *task;
567
568 memset(&stats, 0, sizeof(stats));
569 stats.file_priv = file->driver_priv;
570 spin_lock(&file->table_lock);
571 idr_for_each(&file->object_idr, per_file_stats, &stats);
572 spin_unlock(&file->table_lock);
573 /*
574 * Although we have a valid reference on file->pid, that does
575 * not guarantee that the task_struct who called get_pid() is
576 * still alive (e.g. get_pid(current) => fork() => exit()).
577 * Therefore, we need to protect this ->comm access using RCU.
578 */
579 rcu_read_lock();
580 task = pid_task(file->pid, PIDTYPE_PID);
581 print_file_stats(m, task ? task->comm : "<unknown>", stats);
582 rcu_read_unlock();
583 }
584 mutex_unlock(&dev->filelist_mutex);
585
586 return 0;
587 }
588
589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
590 {
591 struct drm_info_node *node = m->private;
592 struct drm_device *dev = node->minor->dev;
593 uintptr_t list = (uintptr_t) node->info_ent->data;
594 struct drm_i915_private *dev_priv = to_i915(dev);
595 struct drm_i915_gem_object *obj;
596 u64 total_obj_size, total_gtt_size;
597 int count, ret;
598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
602
603 total_obj_size = total_gtt_size = count = 0;
604 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
605 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
606 continue;
607
608 seq_puts(m, " ");
609 describe_obj(m, obj);
610 seq_putc(m, '\n');
611 total_obj_size += obj->base.size;
612 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 count++;
614 }
615
616 mutex_unlock(&dev->struct_mutex);
617
618 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
619 count, total_obj_size, total_gtt_size);
620
621 return 0;
622 }
623
624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
625 {
626 struct drm_info_node *node = m->private;
627 struct drm_device *dev = node->minor->dev;
628 struct drm_i915_private *dev_priv = to_i915(dev);
629 struct intel_crtc *crtc;
630 int ret;
631
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
633 if (ret)
634 return ret;
635
636 for_each_intel_crtc(dev, crtc) {
637 const char pipe = pipe_name(crtc->pipe);
638 const char plane = plane_name(crtc->plane);
639 struct intel_flip_work *work;
640
641 spin_lock_irq(&dev->event_lock);
642 work = crtc->flip_work;
643 if (work == NULL) {
644 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
645 pipe, plane);
646 } else {
647 u32 pending;
648 u32 addr;
649
650 pending = atomic_read(&work->pending);
651 if (pending) {
652 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
653 pipe, plane);
654 } else {
655 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
656 pipe, plane);
657 }
658 if (work->flip_queued_req) {
659 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
660
661 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
662 engine->name,
663 i915_gem_request_get_seqno(work->flip_queued_req),
664 dev_priv->next_seqno,
665 intel_engine_get_seqno(engine),
666 i915_gem_request_completed(work->flip_queued_req));
667 } else
668 seq_printf(m, "Flip not associated with any ring\n");
669 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
670 work->flip_queued_vblank,
671 work->flip_ready_vblank,
672 intel_crtc_get_vblank_counter(crtc));
673 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
674
675 if (INTEL_INFO(dev)->gen >= 4)
676 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
677 else
678 addr = I915_READ(DSPADDR(crtc->plane));
679 seq_printf(m, "Current scanout address 0x%08x\n", addr);
680
681 if (work->pending_flip_obj) {
682 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
683 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
684 }
685 }
686 spin_unlock_irq(&dev->event_lock);
687 }
688
689 mutex_unlock(&dev->struct_mutex);
690
691 return 0;
692 }
693
694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
695 {
696 struct drm_info_node *node = m->private;
697 struct drm_device *dev = node->minor->dev;
698 struct drm_i915_private *dev_priv = to_i915(dev);
699 struct drm_i915_gem_object *obj;
700 struct intel_engine_cs *engine;
701 int total = 0;
702 int ret, j;
703
704 ret = mutex_lock_interruptible(&dev->struct_mutex);
705 if (ret)
706 return ret;
707
708 for_each_engine(engine, dev_priv) {
709 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
710 int count;
711
712 count = 0;
713 list_for_each_entry(obj,
714 &engine->batch_pool.cache_list[j],
715 batch_pool_link)
716 count++;
717 seq_printf(m, "%s cache[%d]: %d objects\n",
718 engine->name, j, count);
719
720 list_for_each_entry(obj,
721 &engine->batch_pool.cache_list[j],
722 batch_pool_link) {
723 seq_puts(m, " ");
724 describe_obj(m, obj);
725 seq_putc(m, '\n');
726 }
727
728 total += count;
729 }
730 }
731
732 seq_printf(m, "total: %d\n", total);
733
734 mutex_unlock(&dev->struct_mutex);
735
736 return 0;
737 }
738
739 static int i915_gem_request_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = to_i915(dev);
744 struct intel_engine_cs *engine;
745 struct drm_i915_gem_request *req;
746 int ret, any;
747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
751
752 any = 0;
753 for_each_engine(engine, dev_priv) {
754 int count;
755
756 count = 0;
757 list_for_each_entry(req, &engine->request_list, list)
758 count++;
759 if (count == 0)
760 continue;
761
762 seq_printf(m, "%s requests: %d\n", engine->name, count);
763 list_for_each_entry(req, &engine->request_list, list) {
764 struct task_struct *task;
765
766 rcu_read_lock();
767 task = NULL;
768 if (req->pid)
769 task = pid_task(req->pid, PIDTYPE_PID);
770 seq_printf(m, " %x @ %d: %s [%d]\n",
771 req->seqno,
772 (int) (jiffies - req->emitted_jiffies),
773 task ? task->comm : "<unknown>",
774 task ? task->pid : -1);
775 rcu_read_unlock();
776 }
777
778 any++;
779 }
780 mutex_unlock(&dev->struct_mutex);
781
782 if (any == 0)
783 seq_puts(m, "No requests\n");
784
785 return 0;
786 }
787
788 static void i915_ring_seqno_info(struct seq_file *m,
789 struct intel_engine_cs *engine)
790 {
791 struct intel_breadcrumbs *b = &engine->breadcrumbs;
792 struct rb_node *rb;
793
794 seq_printf(m, "Current sequence (%s): %x\n",
795 engine->name, intel_engine_get_seqno(engine));
796 seq_printf(m, "Current user interrupts (%s): %x\n",
797 engine->name, READ_ONCE(engine->user_interrupts));
798
799 spin_lock(&b->lock);
800 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
801 struct intel_wait *w = container_of(rb, typeof(*w), node);
802
803 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
804 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
805 }
806 spin_unlock(&b->lock);
807 }
808
809 static int i915_gem_seqno_info(struct seq_file *m, void *data)
810 {
811 struct drm_info_node *node = m->private;
812 struct drm_device *dev = node->minor->dev;
813 struct drm_i915_private *dev_priv = to_i915(dev);
814 struct intel_engine_cs *engine;
815 int ret;
816
817 ret = mutex_lock_interruptible(&dev->struct_mutex);
818 if (ret)
819 return ret;
820 intel_runtime_pm_get(dev_priv);
821
822 for_each_engine(engine, dev_priv)
823 i915_ring_seqno_info(m, engine);
824
825 intel_runtime_pm_put(dev_priv);
826 mutex_unlock(&dev->struct_mutex);
827
828 return 0;
829 }
830
831
832 static int i915_interrupt_info(struct seq_file *m, void *data)
833 {
834 struct drm_info_node *node = m->private;
835 struct drm_device *dev = node->minor->dev;
836 struct drm_i915_private *dev_priv = to_i915(dev);
837 struct intel_engine_cs *engine;
838 int ret, i, pipe;
839
840 ret = mutex_lock_interruptible(&dev->struct_mutex);
841 if (ret)
842 return ret;
843 intel_runtime_pm_get(dev_priv);
844
845 if (IS_CHERRYVIEW(dev)) {
846 seq_printf(m, "Master Interrupt Control:\t%08x\n",
847 I915_READ(GEN8_MASTER_IRQ));
848
849 seq_printf(m, "Display IER:\t%08x\n",
850 I915_READ(VLV_IER));
851 seq_printf(m, "Display IIR:\t%08x\n",
852 I915_READ(VLV_IIR));
853 seq_printf(m, "Display IIR_RW:\t%08x\n",
854 I915_READ(VLV_IIR_RW));
855 seq_printf(m, "Display IMR:\t%08x\n",
856 I915_READ(VLV_IMR));
857 for_each_pipe(dev_priv, pipe)
858 seq_printf(m, "Pipe %c stat:\t%08x\n",
859 pipe_name(pipe),
860 I915_READ(PIPESTAT(pipe)));
861
862 seq_printf(m, "Port hotplug:\t%08x\n",
863 I915_READ(PORT_HOTPLUG_EN));
864 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
865 I915_READ(VLV_DPFLIPSTAT));
866 seq_printf(m, "DPINVGTT:\t%08x\n",
867 I915_READ(DPINVGTT));
868
869 for (i = 0; i < 4; i++) {
870 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
871 i, I915_READ(GEN8_GT_IMR(i)));
872 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
873 i, I915_READ(GEN8_GT_IIR(i)));
874 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
875 i, I915_READ(GEN8_GT_IER(i)));
876 }
877
878 seq_printf(m, "PCU interrupt mask:\t%08x\n",
879 I915_READ(GEN8_PCU_IMR));
880 seq_printf(m, "PCU interrupt identity:\t%08x\n",
881 I915_READ(GEN8_PCU_IIR));
882 seq_printf(m, "PCU interrupt enable:\t%08x\n",
883 I915_READ(GEN8_PCU_IER));
884 } else if (INTEL_INFO(dev)->gen >= 8) {
885 seq_printf(m, "Master Interrupt Control:\t%08x\n",
886 I915_READ(GEN8_MASTER_IRQ));
887
888 for (i = 0; i < 4; i++) {
889 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
890 i, I915_READ(GEN8_GT_IMR(i)));
891 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
892 i, I915_READ(GEN8_GT_IIR(i)));
893 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
894 i, I915_READ(GEN8_GT_IER(i)));
895 }
896
897 for_each_pipe(dev_priv, pipe) {
898 enum intel_display_power_domain power_domain;
899
900 power_domain = POWER_DOMAIN_PIPE(pipe);
901 if (!intel_display_power_get_if_enabled(dev_priv,
902 power_domain)) {
903 seq_printf(m, "Pipe %c power disabled\n",
904 pipe_name(pipe));
905 continue;
906 }
907 seq_printf(m, "Pipe %c IMR:\t%08x\n",
908 pipe_name(pipe),
909 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
910 seq_printf(m, "Pipe %c IIR:\t%08x\n",
911 pipe_name(pipe),
912 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
913 seq_printf(m, "Pipe %c IER:\t%08x\n",
914 pipe_name(pipe),
915 I915_READ(GEN8_DE_PIPE_IER(pipe)));
916
917 intel_display_power_put(dev_priv, power_domain);
918 }
919
920 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
921 I915_READ(GEN8_DE_PORT_IMR));
922 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
923 I915_READ(GEN8_DE_PORT_IIR));
924 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
925 I915_READ(GEN8_DE_PORT_IER));
926
927 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
928 I915_READ(GEN8_DE_MISC_IMR));
929 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
930 I915_READ(GEN8_DE_MISC_IIR));
931 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
932 I915_READ(GEN8_DE_MISC_IER));
933
934 seq_printf(m, "PCU interrupt mask:\t%08x\n",
935 I915_READ(GEN8_PCU_IMR));
936 seq_printf(m, "PCU interrupt identity:\t%08x\n",
937 I915_READ(GEN8_PCU_IIR));
938 seq_printf(m, "PCU interrupt enable:\t%08x\n",
939 I915_READ(GEN8_PCU_IER));
940 } else if (IS_VALLEYVIEW(dev)) {
941 seq_printf(m, "Display IER:\t%08x\n",
942 I915_READ(VLV_IER));
943 seq_printf(m, "Display IIR:\t%08x\n",
944 I915_READ(VLV_IIR));
945 seq_printf(m, "Display IIR_RW:\t%08x\n",
946 I915_READ(VLV_IIR_RW));
947 seq_printf(m, "Display IMR:\t%08x\n",
948 I915_READ(VLV_IMR));
949 for_each_pipe(dev_priv, pipe)
950 seq_printf(m, "Pipe %c stat:\t%08x\n",
951 pipe_name(pipe),
952 I915_READ(PIPESTAT(pipe)));
953
954 seq_printf(m, "Master IER:\t%08x\n",
955 I915_READ(VLV_MASTER_IER));
956
957 seq_printf(m, "Render IER:\t%08x\n",
958 I915_READ(GTIER));
959 seq_printf(m, "Render IIR:\t%08x\n",
960 I915_READ(GTIIR));
961 seq_printf(m, "Render IMR:\t%08x\n",
962 I915_READ(GTIMR));
963
964 seq_printf(m, "PM IER:\t\t%08x\n",
965 I915_READ(GEN6_PMIER));
966 seq_printf(m, "PM IIR:\t\t%08x\n",
967 I915_READ(GEN6_PMIIR));
968 seq_printf(m, "PM IMR:\t\t%08x\n",
969 I915_READ(GEN6_PMIMR));
970
971 seq_printf(m, "Port hotplug:\t%08x\n",
972 I915_READ(PORT_HOTPLUG_EN));
973 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
974 I915_READ(VLV_DPFLIPSTAT));
975 seq_printf(m, "DPINVGTT:\t%08x\n",
976 I915_READ(DPINVGTT));
977
978 } else if (!HAS_PCH_SPLIT(dev)) {
979 seq_printf(m, "Interrupt enable: %08x\n",
980 I915_READ(IER));
981 seq_printf(m, "Interrupt identity: %08x\n",
982 I915_READ(IIR));
983 seq_printf(m, "Interrupt mask: %08x\n",
984 I915_READ(IMR));
985 for_each_pipe(dev_priv, pipe)
986 seq_printf(m, "Pipe %c stat: %08x\n",
987 pipe_name(pipe),
988 I915_READ(PIPESTAT(pipe)));
989 } else {
990 seq_printf(m, "North Display Interrupt enable: %08x\n",
991 I915_READ(DEIER));
992 seq_printf(m, "North Display Interrupt identity: %08x\n",
993 I915_READ(DEIIR));
994 seq_printf(m, "North Display Interrupt mask: %08x\n",
995 I915_READ(DEIMR));
996 seq_printf(m, "South Display Interrupt enable: %08x\n",
997 I915_READ(SDEIER));
998 seq_printf(m, "South Display Interrupt identity: %08x\n",
999 I915_READ(SDEIIR));
1000 seq_printf(m, "South Display Interrupt mask: %08x\n",
1001 I915_READ(SDEIMR));
1002 seq_printf(m, "Graphics Interrupt enable: %08x\n",
1003 I915_READ(GTIER));
1004 seq_printf(m, "Graphics Interrupt identity: %08x\n",
1005 I915_READ(GTIIR));
1006 seq_printf(m, "Graphics Interrupt mask: %08x\n",
1007 I915_READ(GTIMR));
1008 }
1009 for_each_engine(engine, dev_priv) {
1010 if (INTEL_INFO(dev)->gen >= 6) {
1011 seq_printf(m,
1012 "Graphics Interrupt mask (%s): %08x\n",
1013 engine->name, I915_READ_IMR(engine));
1014 }
1015 i915_ring_seqno_info(m, engine);
1016 }
1017 intel_runtime_pm_put(dev_priv);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return 0;
1021 }
1022
1023 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1024 {
1025 struct drm_info_node *node = m->private;
1026 struct drm_device *dev = node->minor->dev;
1027 struct drm_i915_private *dev_priv = to_i915(dev);
1028 int i, ret;
1029
1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
1032 return ret;
1033
1034 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1035 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1036 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1037
1038 seq_printf(m, "Fence %d, pin count = %d, object = ",
1039 i, dev_priv->fence_regs[i].pin_count);
1040 if (obj == NULL)
1041 seq_puts(m, "unused");
1042 else
1043 describe_obj(m, obj);
1044 seq_putc(m, '\n');
1045 }
1046
1047 mutex_unlock(&dev->struct_mutex);
1048 return 0;
1049 }
1050
1051 static int i915_hws_info(struct seq_file *m, void *data)
1052 {
1053 struct drm_info_node *node = m->private;
1054 struct drm_device *dev = node->minor->dev;
1055 struct drm_i915_private *dev_priv = to_i915(dev);
1056 struct intel_engine_cs *engine;
1057 const u32 *hws;
1058 int i;
1059
1060 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1061 hws = engine->status_page.page_addr;
1062 if (hws == NULL)
1063 return 0;
1064
1065 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1066 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1067 i * 4,
1068 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1069 }
1070 return 0;
1071 }
1072
1073 static ssize_t
1074 i915_error_state_write(struct file *filp,
1075 const char __user *ubuf,
1076 size_t cnt,
1077 loff_t *ppos)
1078 {
1079 struct i915_error_state_file_priv *error_priv = filp->private_data;
1080 struct drm_device *dev = error_priv->dev;
1081 int ret;
1082
1083 DRM_DEBUG_DRIVER("Resetting error state\n");
1084
1085 ret = mutex_lock_interruptible(&dev->struct_mutex);
1086 if (ret)
1087 return ret;
1088
1089 i915_destroy_error_state(dev);
1090 mutex_unlock(&dev->struct_mutex);
1091
1092 return cnt;
1093 }
1094
1095 static int i915_error_state_open(struct inode *inode, struct file *file)
1096 {
1097 struct drm_device *dev = inode->i_private;
1098 struct i915_error_state_file_priv *error_priv;
1099
1100 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1101 if (!error_priv)
1102 return -ENOMEM;
1103
1104 error_priv->dev = dev;
1105
1106 i915_error_state_get(dev, error_priv);
1107
1108 file->private_data = error_priv;
1109
1110 return 0;
1111 }
1112
1113 static int i915_error_state_release(struct inode *inode, struct file *file)
1114 {
1115 struct i915_error_state_file_priv *error_priv = file->private_data;
1116
1117 i915_error_state_put(error_priv);
1118 kfree(error_priv);
1119
1120 return 0;
1121 }
1122
1123 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1124 size_t count, loff_t *pos)
1125 {
1126 struct i915_error_state_file_priv *error_priv = file->private_data;
1127 struct drm_i915_error_state_buf error_str;
1128 loff_t tmp_pos = 0;
1129 ssize_t ret_count = 0;
1130 int ret;
1131
1132 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1133 if (ret)
1134 return ret;
1135
1136 ret = i915_error_state_to_str(&error_str, error_priv);
1137 if (ret)
1138 goto out;
1139
1140 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1141 error_str.buf,
1142 error_str.bytes);
1143
1144 if (ret_count < 0)
1145 ret = ret_count;
1146 else
1147 *pos = error_str.start + ret_count;
1148 out:
1149 i915_error_state_buf_release(&error_str);
1150 return ret ?: ret_count;
1151 }
1152
1153 static const struct file_operations i915_error_state_fops = {
1154 .owner = THIS_MODULE,
1155 .open = i915_error_state_open,
1156 .read = i915_error_state_read,
1157 .write = i915_error_state_write,
1158 .llseek = default_llseek,
1159 .release = i915_error_state_release,
1160 };
1161
1162 static int
1163 i915_next_seqno_get(void *data, u64 *val)
1164 {
1165 struct drm_device *dev = data;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 int ret;
1168
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
1171 return ret;
1172
1173 *val = dev_priv->next_seqno;
1174 mutex_unlock(&dev->struct_mutex);
1175
1176 return 0;
1177 }
1178
1179 static int
1180 i915_next_seqno_set(void *data, u64 val)
1181 {
1182 struct drm_device *dev = data;
1183 int ret;
1184
1185 ret = mutex_lock_interruptible(&dev->struct_mutex);
1186 if (ret)
1187 return ret;
1188
1189 ret = i915_gem_set_seqno(dev, val);
1190 mutex_unlock(&dev->struct_mutex);
1191
1192 return ret;
1193 }
1194
1195 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1196 i915_next_seqno_get, i915_next_seqno_set,
1197 "0x%llx\n");
1198
1199 static int i915_frequency_info(struct seq_file *m, void *unused)
1200 {
1201 struct drm_info_node *node = m->private;
1202 struct drm_device *dev = node->minor->dev;
1203 struct drm_i915_private *dev_priv = to_i915(dev);
1204 int ret = 0;
1205
1206 intel_runtime_pm_get(dev_priv);
1207
1208 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1209
1210 if (IS_GEN5(dev)) {
1211 u16 rgvswctl = I915_READ16(MEMSWCTL);
1212 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1213
1214 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1215 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1216 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1217 MEMSTAT_VID_SHIFT);
1218 seq_printf(m, "Current P-state: %d\n",
1219 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1220 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1221 u32 freq_sts;
1222
1223 mutex_lock(&dev_priv->rps.hw_lock);
1224 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1225 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1226 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1227
1228 seq_printf(m, "actual GPU freq: %d MHz\n",
1229 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1230
1231 seq_printf(m, "current GPU freq: %d MHz\n",
1232 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1233
1234 seq_printf(m, "max GPU freq: %d MHz\n",
1235 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1236
1237 seq_printf(m, "min GPU freq: %d MHz\n",
1238 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1239
1240 seq_printf(m, "idle GPU freq: %d MHz\n",
1241 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1242
1243 seq_printf(m,
1244 "efficient (RPe) frequency: %d MHz\n",
1245 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1246 mutex_unlock(&dev_priv->rps.hw_lock);
1247 } else if (INTEL_INFO(dev)->gen >= 6) {
1248 u32 rp_state_limits;
1249 u32 gt_perf_status;
1250 u32 rp_state_cap;
1251 u32 rpmodectl, rpinclimit, rpdeclimit;
1252 u32 rpstat, cagf, reqf;
1253 u32 rpupei, rpcurup, rpprevup;
1254 u32 rpdownei, rpcurdown, rpprevdown;
1255 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1256 int max_freq;
1257
1258 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1259 if (IS_BROXTON(dev)) {
1260 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1261 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1262 } else {
1263 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1264 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1265 }
1266
1267 /* RPSTAT1 is in the GT power well */
1268 ret = mutex_lock_interruptible(&dev->struct_mutex);
1269 if (ret)
1270 goto out;
1271
1272 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1273
1274 reqf = I915_READ(GEN6_RPNSWREQ);
1275 if (IS_GEN9(dev))
1276 reqf >>= 23;
1277 else {
1278 reqf &= ~GEN6_TURBO_DISABLE;
1279 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1280 reqf >>= 24;
1281 else
1282 reqf >>= 25;
1283 }
1284 reqf = intel_gpu_freq(dev_priv, reqf);
1285
1286 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1287 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1288 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1289
1290 rpstat = I915_READ(GEN6_RPSTAT1);
1291 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1292 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1293 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1294 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1295 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1296 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1297 if (IS_GEN9(dev))
1298 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1299 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1300 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1301 else
1302 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1303 cagf = intel_gpu_freq(dev_priv, cagf);
1304
1305 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1306 mutex_unlock(&dev->struct_mutex);
1307
1308 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1309 pm_ier = I915_READ(GEN6_PMIER);
1310 pm_imr = I915_READ(GEN6_PMIMR);
1311 pm_isr = I915_READ(GEN6_PMISR);
1312 pm_iir = I915_READ(GEN6_PMIIR);
1313 pm_mask = I915_READ(GEN6_PMINTRMSK);
1314 } else {
1315 pm_ier = I915_READ(GEN8_GT_IER(2));
1316 pm_imr = I915_READ(GEN8_GT_IMR(2));
1317 pm_isr = I915_READ(GEN8_GT_ISR(2));
1318 pm_iir = I915_READ(GEN8_GT_IIR(2));
1319 pm_mask = I915_READ(GEN6_PMINTRMSK);
1320 }
1321 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1322 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1323 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1324 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1325 seq_printf(m, "Render p-state ratio: %d\n",
1326 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1327 seq_printf(m, "Render p-state VID: %d\n",
1328 gt_perf_status & 0xff);
1329 seq_printf(m, "Render p-state limit: %d\n",
1330 rp_state_limits & 0xff);
1331 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1332 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1333 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1334 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1335 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1336 seq_printf(m, "CAGF: %dMHz\n", cagf);
1337 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1338 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1339 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1340 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1341 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1342 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1343 seq_printf(m, "Up threshold: %d%%\n",
1344 dev_priv->rps.up_threshold);
1345
1346 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1347 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1348 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1349 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1350 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1351 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1352 seq_printf(m, "Down threshold: %d%%\n",
1353 dev_priv->rps.down_threshold);
1354
1355 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1356 rp_state_cap >> 16) & 0xff;
1357 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1358 GEN9_FREQ_SCALER : 1);
1359 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1360 intel_gpu_freq(dev_priv, max_freq));
1361
1362 max_freq = (rp_state_cap & 0xff00) >> 8;
1363 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1364 GEN9_FREQ_SCALER : 1);
1365 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1366 intel_gpu_freq(dev_priv, max_freq));
1367
1368 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1369 rp_state_cap >> 0) & 0xff;
1370 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1371 GEN9_FREQ_SCALER : 1);
1372 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1373 intel_gpu_freq(dev_priv, max_freq));
1374 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1375 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1376
1377 seq_printf(m, "Current freq: %d MHz\n",
1378 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1379 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1380 seq_printf(m, "Idle freq: %d MHz\n",
1381 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1382 seq_printf(m, "Min freq: %d MHz\n",
1383 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1384 seq_printf(m, "Max freq: %d MHz\n",
1385 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1386 seq_printf(m,
1387 "efficient (RPe) frequency: %d MHz\n",
1388 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1389 } else {
1390 seq_puts(m, "no P-state info available\n");
1391 }
1392
1393 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1394 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1395 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1396
1397 out:
1398 intel_runtime_pm_put(dev_priv);
1399 return ret;
1400 }
1401
1402 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1403 {
1404 struct drm_info_node *node = m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = to_i915(dev);
1407 struct intel_engine_cs *engine;
1408 u64 acthd[I915_NUM_ENGINES];
1409 u32 seqno[I915_NUM_ENGINES];
1410 u32 instdone[I915_NUM_INSTDONE_REG];
1411 enum intel_engine_id id;
1412 int j;
1413
1414 if (!i915.enable_hangcheck) {
1415 seq_printf(m, "Hangcheck disabled\n");
1416 return 0;
1417 }
1418
1419 intel_runtime_pm_get(dev_priv);
1420
1421 for_each_engine_id(engine, dev_priv, id) {
1422 acthd[id] = intel_ring_get_active_head(engine);
1423 seqno[id] = intel_engine_get_seqno(engine);
1424 }
1425
1426 i915_get_extra_instdone(dev_priv, instdone);
1427
1428 intel_runtime_pm_put(dev_priv);
1429
1430 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1431 seq_printf(m, "Hangcheck active, fires in %dms\n",
1432 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1433 jiffies));
1434 } else
1435 seq_printf(m, "Hangcheck inactive\n");
1436
1437 for_each_engine_id(engine, dev_priv, id) {
1438 seq_printf(m, "%s:\n", engine->name);
1439 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1440 engine->hangcheck.seqno,
1441 seqno[id],
1442 engine->last_submitted_seqno);
1443 seq_printf(m, "\twaiters? %d\n",
1444 intel_engine_has_waiter(engine));
1445 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1446 engine->hangcheck.user_interrupts,
1447 READ_ONCE(engine->user_interrupts));
1448 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1449 (long long)engine->hangcheck.acthd,
1450 (long long)acthd[id]);
1451 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1452 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1453
1454 if (engine->id == RCS) {
1455 seq_puts(m, "\tinstdone read =");
1456
1457 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1458 seq_printf(m, " 0x%08x", instdone[j]);
1459
1460 seq_puts(m, "\n\tinstdone accu =");
1461
1462 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1463 seq_printf(m, " 0x%08x",
1464 engine->hangcheck.instdone[j]);
1465
1466 seq_puts(m, "\n");
1467 }
1468 }
1469
1470 return 0;
1471 }
1472
1473 static int ironlake_drpc_info(struct seq_file *m)
1474 {
1475 struct drm_info_node *node = m->private;
1476 struct drm_device *dev = node->minor->dev;
1477 struct drm_i915_private *dev_priv = to_i915(dev);
1478 u32 rgvmodectl, rstdbyctl;
1479 u16 crstandvid;
1480 int ret;
1481
1482 ret = mutex_lock_interruptible(&dev->struct_mutex);
1483 if (ret)
1484 return ret;
1485 intel_runtime_pm_get(dev_priv);
1486
1487 rgvmodectl = I915_READ(MEMMODECTL);
1488 rstdbyctl = I915_READ(RSTDBYCTL);
1489 crstandvid = I915_READ16(CRSTANDVID);
1490
1491 intel_runtime_pm_put(dev_priv);
1492 mutex_unlock(&dev->struct_mutex);
1493
1494 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1495 seq_printf(m, "Boost freq: %d\n",
1496 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1497 MEMMODE_BOOST_FREQ_SHIFT);
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1502 seq_printf(m, "Gated voltage change: %s\n",
1503 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1504 seq_printf(m, "Starting frequency: P%d\n",
1505 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1506 seq_printf(m, "Max P-state: P%d\n",
1507 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1508 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1509 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1510 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1511 seq_printf(m, "Render standby enabled: %s\n",
1512 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1513 seq_puts(m, "Current RS state: ");
1514 switch (rstdbyctl & RSX_STATUS_MASK) {
1515 case RSX_STATUS_ON:
1516 seq_puts(m, "on\n");
1517 break;
1518 case RSX_STATUS_RC1:
1519 seq_puts(m, "RC1\n");
1520 break;
1521 case RSX_STATUS_RC1E:
1522 seq_puts(m, "RC1E\n");
1523 break;
1524 case RSX_STATUS_RS1:
1525 seq_puts(m, "RS1\n");
1526 break;
1527 case RSX_STATUS_RS2:
1528 seq_puts(m, "RS2 (RC6)\n");
1529 break;
1530 case RSX_STATUS_RS3:
1531 seq_puts(m, "RC3 (RC6+)\n");
1532 break;
1533 default:
1534 seq_puts(m, "unknown\n");
1535 break;
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int i915_forcewake_domains(struct seq_file *m, void *data)
1542 {
1543 struct drm_info_node *node = m->private;
1544 struct drm_device *dev = node->minor->dev;
1545 struct drm_i915_private *dev_priv = to_i915(dev);
1546 struct intel_uncore_forcewake_domain *fw_domain;
1547
1548 spin_lock_irq(&dev_priv->uncore.lock);
1549 for_each_fw_domain(fw_domain, dev_priv) {
1550 seq_printf(m, "%s.wake_count = %u\n",
1551 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1552 fw_domain->wake_count);
1553 }
1554 spin_unlock_irq(&dev_priv->uncore.lock);
1555
1556 return 0;
1557 }
1558
1559 static int vlv_drpc_info(struct seq_file *m)
1560 {
1561 struct drm_info_node *node = m->private;
1562 struct drm_device *dev = node->minor->dev;
1563 struct drm_i915_private *dev_priv = to_i915(dev);
1564 u32 rpmodectl1, rcctl1, pw_status;
1565
1566 intel_runtime_pm_get(dev_priv);
1567
1568 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1569 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1570 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1571
1572 intel_runtime_pm_put(dev_priv);
1573
1574 seq_printf(m, "Video Turbo Mode: %s\n",
1575 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1576 seq_printf(m, "Turbo enabled: %s\n",
1577 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1578 seq_printf(m, "HW control enabled: %s\n",
1579 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1580 seq_printf(m, "SW control enabled: %s\n",
1581 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1582 GEN6_RP_MEDIA_SW_MODE));
1583 seq_printf(m, "RC6 Enabled: %s\n",
1584 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1585 GEN6_RC_CTL_EI_MODE(1))));
1586 seq_printf(m, "Render Power Well: %s\n",
1587 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1588 seq_printf(m, "Media Power Well: %s\n",
1589 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1590
1591 seq_printf(m, "Render RC6 residency since boot: %u\n",
1592 I915_READ(VLV_GT_RENDER_RC6));
1593 seq_printf(m, "Media RC6 residency since boot: %u\n",
1594 I915_READ(VLV_GT_MEDIA_RC6));
1595
1596 return i915_forcewake_domains(m, NULL);
1597 }
1598
1599 static int gen6_drpc_info(struct seq_file *m)
1600 {
1601 struct drm_info_node *node = m->private;
1602 struct drm_device *dev = node->minor->dev;
1603 struct drm_i915_private *dev_priv = to_i915(dev);
1604 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1605 unsigned forcewake_count;
1606 int count = 0, ret;
1607
1608 ret = mutex_lock_interruptible(&dev->struct_mutex);
1609 if (ret)
1610 return ret;
1611 intel_runtime_pm_get(dev_priv);
1612
1613 spin_lock_irq(&dev_priv->uncore.lock);
1614 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1615 spin_unlock_irq(&dev_priv->uncore.lock);
1616
1617 if (forcewake_count) {
1618 seq_puts(m, "RC information inaccurate because somebody "
1619 "holds a forcewake reference \n");
1620 } else {
1621 /* NB: we cannot use forcewake, else we read the wrong values */
1622 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1623 udelay(10);
1624 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1625 }
1626
1627 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1628 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1629
1630 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1631 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1632 mutex_unlock(&dev->struct_mutex);
1633 mutex_lock(&dev_priv->rps.hw_lock);
1634 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1635 mutex_unlock(&dev_priv->rps.hw_lock);
1636
1637 intel_runtime_pm_put(dev_priv);
1638
1639 seq_printf(m, "Video Turbo Mode: %s\n",
1640 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1641 seq_printf(m, "HW control enabled: %s\n",
1642 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1643 seq_printf(m, "SW control enabled: %s\n",
1644 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1645 GEN6_RP_MEDIA_SW_MODE));
1646 seq_printf(m, "RC1e Enabled: %s\n",
1647 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1648 seq_printf(m, "RC6 Enabled: %s\n",
1649 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1650 seq_printf(m, "Deep RC6 Enabled: %s\n",
1651 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1652 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1653 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1654 seq_puts(m, "Current RC state: ");
1655 switch (gt_core_status & GEN6_RCn_MASK) {
1656 case GEN6_RC0:
1657 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1658 seq_puts(m, "Core Power Down\n");
1659 else
1660 seq_puts(m, "on\n");
1661 break;
1662 case GEN6_RC3:
1663 seq_puts(m, "RC3\n");
1664 break;
1665 case GEN6_RC6:
1666 seq_puts(m, "RC6\n");
1667 break;
1668 case GEN6_RC7:
1669 seq_puts(m, "RC7\n");
1670 break;
1671 default:
1672 seq_puts(m, "Unknown\n");
1673 break;
1674 }
1675
1676 seq_printf(m, "Core Power Down: %s\n",
1677 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1678
1679 /* Not exactly sure what this is */
1680 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1681 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1682 seq_printf(m, "RC6 residency since boot: %u\n",
1683 I915_READ(GEN6_GT_GFX_RC6));
1684 seq_printf(m, "RC6+ residency since boot: %u\n",
1685 I915_READ(GEN6_GT_GFX_RC6p));
1686 seq_printf(m, "RC6++ residency since boot: %u\n",
1687 I915_READ(GEN6_GT_GFX_RC6pp));
1688
1689 seq_printf(m, "RC6 voltage: %dmV\n",
1690 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1691 seq_printf(m, "RC6+ voltage: %dmV\n",
1692 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1693 seq_printf(m, "RC6++ voltage: %dmV\n",
1694 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1695 return 0;
1696 }
1697
1698 static int i915_drpc_info(struct seq_file *m, void *unused)
1699 {
1700 struct drm_info_node *node = m->private;
1701 struct drm_device *dev = node->minor->dev;
1702
1703 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1704 return vlv_drpc_info(m);
1705 else if (INTEL_INFO(dev)->gen >= 6)
1706 return gen6_drpc_info(m);
1707 else
1708 return ironlake_drpc_info(m);
1709 }
1710
1711 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1712 {
1713 struct drm_info_node *node = m->private;
1714 struct drm_device *dev = node->minor->dev;
1715 struct drm_i915_private *dev_priv = to_i915(dev);
1716
1717 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1718 dev_priv->fb_tracking.busy_bits);
1719
1720 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1721 dev_priv->fb_tracking.flip_bits);
1722
1723 return 0;
1724 }
1725
1726 static int i915_fbc_status(struct seq_file *m, void *unused)
1727 {
1728 struct drm_info_node *node = m->private;
1729 struct drm_device *dev = node->minor->dev;
1730 struct drm_i915_private *dev_priv = to_i915(dev);
1731
1732 if (!HAS_FBC(dev)) {
1733 seq_puts(m, "FBC unsupported on this chipset\n");
1734 return 0;
1735 }
1736
1737 intel_runtime_pm_get(dev_priv);
1738 mutex_lock(&dev_priv->fbc.lock);
1739
1740 if (intel_fbc_is_active(dev_priv))
1741 seq_puts(m, "FBC enabled\n");
1742 else
1743 seq_printf(m, "FBC disabled: %s\n",
1744 dev_priv->fbc.no_fbc_reason);
1745
1746 if (INTEL_INFO(dev_priv)->gen >= 7)
1747 seq_printf(m, "Compressing: %s\n",
1748 yesno(I915_READ(FBC_STATUS2) &
1749 FBC_COMPRESSION_MASK));
1750
1751 mutex_unlock(&dev_priv->fbc.lock);
1752 intel_runtime_pm_put(dev_priv);
1753
1754 return 0;
1755 }
1756
1757 static int i915_fbc_fc_get(void *data, u64 *val)
1758 {
1759 struct drm_device *dev = data;
1760 struct drm_i915_private *dev_priv = to_i915(dev);
1761
1762 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1763 return -ENODEV;
1764
1765 *val = dev_priv->fbc.false_color;
1766
1767 return 0;
1768 }
1769
1770 static int i915_fbc_fc_set(void *data, u64 val)
1771 {
1772 struct drm_device *dev = data;
1773 struct drm_i915_private *dev_priv = to_i915(dev);
1774 u32 reg;
1775
1776 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1777 return -ENODEV;
1778
1779 mutex_lock(&dev_priv->fbc.lock);
1780
1781 reg = I915_READ(ILK_DPFC_CONTROL);
1782 dev_priv->fbc.false_color = val;
1783
1784 I915_WRITE(ILK_DPFC_CONTROL, val ?
1785 (reg | FBC_CTL_FALSE_COLOR) :
1786 (reg & ~FBC_CTL_FALSE_COLOR));
1787
1788 mutex_unlock(&dev_priv->fbc.lock);
1789 return 0;
1790 }
1791
1792 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1793 i915_fbc_fc_get, i915_fbc_fc_set,
1794 "%llu\n");
1795
1796 static int i915_ips_status(struct seq_file *m, void *unused)
1797 {
1798 struct drm_info_node *node = m->private;
1799 struct drm_device *dev = node->minor->dev;
1800 struct drm_i915_private *dev_priv = to_i915(dev);
1801
1802 if (!HAS_IPS(dev)) {
1803 seq_puts(m, "not supported\n");
1804 return 0;
1805 }
1806
1807 intel_runtime_pm_get(dev_priv);
1808
1809 seq_printf(m, "Enabled by kernel parameter: %s\n",
1810 yesno(i915.enable_ips));
1811
1812 if (INTEL_INFO(dev)->gen >= 8) {
1813 seq_puts(m, "Currently: unknown\n");
1814 } else {
1815 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1816 seq_puts(m, "Currently: enabled\n");
1817 else
1818 seq_puts(m, "Currently: disabled\n");
1819 }
1820
1821 intel_runtime_pm_put(dev_priv);
1822
1823 return 0;
1824 }
1825
1826 static int i915_sr_status(struct seq_file *m, void *unused)
1827 {
1828 struct drm_info_node *node = m->private;
1829 struct drm_device *dev = node->minor->dev;
1830 struct drm_i915_private *dev_priv = to_i915(dev);
1831 bool sr_enabled = false;
1832
1833 intel_runtime_pm_get(dev_priv);
1834
1835 if (HAS_PCH_SPLIT(dev))
1836 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1837 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1838 IS_I945G(dev) || IS_I945GM(dev))
1839 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1840 else if (IS_I915GM(dev))
1841 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1842 else if (IS_PINEVIEW(dev))
1843 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1844 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1845 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1846
1847 intel_runtime_pm_put(dev_priv);
1848
1849 seq_printf(m, "self-refresh: %s\n",
1850 sr_enabled ? "enabled" : "disabled");
1851
1852 return 0;
1853 }
1854
1855 static int i915_emon_status(struct seq_file *m, void *unused)
1856 {
1857 struct drm_info_node *node = m->private;
1858 struct drm_device *dev = node->minor->dev;
1859 struct drm_i915_private *dev_priv = to_i915(dev);
1860 unsigned long temp, chipset, gfx;
1861 int ret;
1862
1863 if (!IS_GEN5(dev))
1864 return -ENODEV;
1865
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
1868 return ret;
1869
1870 temp = i915_mch_val(dev_priv);
1871 chipset = i915_chipset_val(dev_priv);
1872 gfx = i915_gfx_val(dev_priv);
1873 mutex_unlock(&dev->struct_mutex);
1874
1875 seq_printf(m, "GMCH temp: %ld\n", temp);
1876 seq_printf(m, "Chipset power: %ld\n", chipset);
1877 seq_printf(m, "GFX power: %ld\n", gfx);
1878 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1879
1880 return 0;
1881 }
1882
1883 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1884 {
1885 struct drm_info_node *node = m->private;
1886 struct drm_device *dev = node->minor->dev;
1887 struct drm_i915_private *dev_priv = to_i915(dev);
1888 int ret = 0;
1889 int gpu_freq, ia_freq;
1890 unsigned int max_gpu_freq, min_gpu_freq;
1891
1892 if (!HAS_CORE_RING_FREQ(dev)) {
1893 seq_puts(m, "unsupported on this chipset\n");
1894 return 0;
1895 }
1896
1897 intel_runtime_pm_get(dev_priv);
1898
1899 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1900
1901 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1902 if (ret)
1903 goto out;
1904
1905 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1906 /* Convert GT frequency to 50 HZ units */
1907 min_gpu_freq =
1908 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1909 max_gpu_freq =
1910 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1911 } else {
1912 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1913 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1914 }
1915
1916 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1917
1918 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1919 ia_freq = gpu_freq;
1920 sandybridge_pcode_read(dev_priv,
1921 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1922 &ia_freq);
1923 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1924 intel_gpu_freq(dev_priv, (gpu_freq *
1925 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1926 GEN9_FREQ_SCALER : 1))),
1927 ((ia_freq >> 0) & 0xff) * 100,
1928 ((ia_freq >> 8) & 0xff) * 100);
1929 }
1930
1931 mutex_unlock(&dev_priv->rps.hw_lock);
1932
1933 out:
1934 intel_runtime_pm_put(dev_priv);
1935 return ret;
1936 }
1937
1938 static int i915_opregion(struct seq_file *m, void *unused)
1939 {
1940 struct drm_info_node *node = m->private;
1941 struct drm_device *dev = node->minor->dev;
1942 struct drm_i915_private *dev_priv = to_i915(dev);
1943 struct intel_opregion *opregion = &dev_priv->opregion;
1944 int ret;
1945
1946 ret = mutex_lock_interruptible(&dev->struct_mutex);
1947 if (ret)
1948 goto out;
1949
1950 if (opregion->header)
1951 seq_write(m, opregion->header, OPREGION_SIZE);
1952
1953 mutex_unlock(&dev->struct_mutex);
1954
1955 out:
1956 return 0;
1957 }
1958
1959 static int i915_vbt(struct seq_file *m, void *unused)
1960 {
1961 struct drm_info_node *node = m->private;
1962 struct drm_device *dev = node->minor->dev;
1963 struct drm_i915_private *dev_priv = to_i915(dev);
1964 struct intel_opregion *opregion = &dev_priv->opregion;
1965
1966 if (opregion->vbt)
1967 seq_write(m, opregion->vbt, opregion->vbt_size);
1968
1969 return 0;
1970 }
1971
1972 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1973 {
1974 struct drm_info_node *node = m->private;
1975 struct drm_device *dev = node->minor->dev;
1976 struct intel_framebuffer *fbdev_fb = NULL;
1977 struct drm_framebuffer *drm_fb;
1978 int ret;
1979
1980 ret = mutex_lock_interruptible(&dev->struct_mutex);
1981 if (ret)
1982 return ret;
1983
1984 #ifdef CONFIG_DRM_FBDEV_EMULATION
1985 if (to_i915(dev)->fbdev) {
1986 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1987
1988 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1989 fbdev_fb->base.width,
1990 fbdev_fb->base.height,
1991 fbdev_fb->base.depth,
1992 fbdev_fb->base.bits_per_pixel,
1993 fbdev_fb->base.modifier[0],
1994 drm_framebuffer_read_refcount(&fbdev_fb->base));
1995 describe_obj(m, fbdev_fb->obj);
1996 seq_putc(m, '\n');
1997 }
1998 #endif
1999
2000 mutex_lock(&dev->mode_config.fb_lock);
2001 drm_for_each_fb(drm_fb, dev) {
2002 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2003 if (fb == fbdev_fb)
2004 continue;
2005
2006 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2007 fb->base.width,
2008 fb->base.height,
2009 fb->base.depth,
2010 fb->base.bits_per_pixel,
2011 fb->base.modifier[0],
2012 drm_framebuffer_read_refcount(&fb->base));
2013 describe_obj(m, fb->obj);
2014 seq_putc(m, '\n');
2015 }
2016 mutex_unlock(&dev->mode_config.fb_lock);
2017 mutex_unlock(&dev->struct_mutex);
2018
2019 return 0;
2020 }
2021
2022 static void describe_ctx_ringbuf(struct seq_file *m,
2023 struct intel_ringbuffer *ringbuf)
2024 {
2025 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2026 ringbuf->space, ringbuf->head, ringbuf->tail,
2027 ringbuf->last_retired_head);
2028 }
2029
2030 static int i915_context_status(struct seq_file *m, void *unused)
2031 {
2032 struct drm_info_node *node = m->private;
2033 struct drm_device *dev = node->minor->dev;
2034 struct drm_i915_private *dev_priv = to_i915(dev);
2035 struct intel_engine_cs *engine;
2036 struct i915_gem_context *ctx;
2037 int ret;
2038
2039 ret = mutex_lock_interruptible(&dev->struct_mutex);
2040 if (ret)
2041 return ret;
2042
2043 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2044 seq_printf(m, "HW context %u ", ctx->hw_id);
2045 if (IS_ERR(ctx->file_priv)) {
2046 seq_puts(m, "(deleted) ");
2047 } else if (ctx->file_priv) {
2048 struct pid *pid = ctx->file_priv->file->pid;
2049 struct task_struct *task;
2050
2051 task = get_pid_task(pid, PIDTYPE_PID);
2052 if (task) {
2053 seq_printf(m, "(%s [%d]) ",
2054 task->comm, task->pid);
2055 put_task_struct(task);
2056 }
2057 } else {
2058 seq_puts(m, "(kernel) ");
2059 }
2060
2061 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2062 seq_putc(m, '\n');
2063
2064 for_each_engine(engine, dev_priv) {
2065 struct intel_context *ce = &ctx->engine[engine->id];
2066
2067 seq_printf(m, "%s: ", engine->name);
2068 seq_putc(m, ce->initialised ? 'I' : 'i');
2069 if (ce->state)
2070 describe_obj(m, ce->state);
2071 if (ce->ringbuf)
2072 describe_ctx_ringbuf(m, ce->ringbuf);
2073 seq_putc(m, '\n');
2074 }
2075
2076 seq_putc(m, '\n');
2077 }
2078
2079 mutex_unlock(&dev->struct_mutex);
2080
2081 return 0;
2082 }
2083
2084 static void i915_dump_lrc_obj(struct seq_file *m,
2085 struct i915_gem_context *ctx,
2086 struct intel_engine_cs *engine)
2087 {
2088 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2089 struct page *page;
2090 uint32_t *reg_state;
2091 int j;
2092 unsigned long ggtt_offset = 0;
2093
2094 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2095
2096 if (ctx_obj == NULL) {
2097 seq_puts(m, "\tNot allocated\n");
2098 return;
2099 }
2100
2101 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2102 seq_puts(m, "\tNot bound in GGTT\n");
2103 else
2104 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2105
2106 if (i915_gem_object_get_pages(ctx_obj)) {
2107 seq_puts(m, "\tFailed to get pages for context object\n");
2108 return;
2109 }
2110
2111 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2112 if (!WARN_ON(page == NULL)) {
2113 reg_state = kmap_atomic(page);
2114
2115 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2116 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2117 ggtt_offset + 4096 + (j * 4),
2118 reg_state[j], reg_state[j + 1],
2119 reg_state[j + 2], reg_state[j + 3]);
2120 }
2121 kunmap_atomic(reg_state);
2122 }
2123
2124 seq_putc(m, '\n');
2125 }
2126
2127 static int i915_dump_lrc(struct seq_file *m, void *unused)
2128 {
2129 struct drm_info_node *node = (struct drm_info_node *) m->private;
2130 struct drm_device *dev = node->minor->dev;
2131 struct drm_i915_private *dev_priv = to_i915(dev);
2132 struct intel_engine_cs *engine;
2133 struct i915_gem_context *ctx;
2134 int ret;
2135
2136 if (!i915.enable_execlists) {
2137 seq_printf(m, "Logical Ring Contexts are disabled\n");
2138 return 0;
2139 }
2140
2141 ret = mutex_lock_interruptible(&dev->struct_mutex);
2142 if (ret)
2143 return ret;
2144
2145 list_for_each_entry(ctx, &dev_priv->context_list, link)
2146 for_each_engine(engine, dev_priv)
2147 i915_dump_lrc_obj(m, ctx, engine);
2148
2149 mutex_unlock(&dev->struct_mutex);
2150
2151 return 0;
2152 }
2153
2154 static int i915_execlists(struct seq_file *m, void *data)
2155 {
2156 struct drm_info_node *node = (struct drm_info_node *)m->private;
2157 struct drm_device *dev = node->minor->dev;
2158 struct drm_i915_private *dev_priv = to_i915(dev);
2159 struct intel_engine_cs *engine;
2160 u32 status_pointer;
2161 u8 read_pointer;
2162 u8 write_pointer;
2163 u32 status;
2164 u32 ctx_id;
2165 struct list_head *cursor;
2166 int i, ret;
2167
2168 if (!i915.enable_execlists) {
2169 seq_puts(m, "Logical Ring Contexts are disabled\n");
2170 return 0;
2171 }
2172
2173 ret = mutex_lock_interruptible(&dev->struct_mutex);
2174 if (ret)
2175 return ret;
2176
2177 intel_runtime_pm_get(dev_priv);
2178
2179 for_each_engine(engine, dev_priv) {
2180 struct drm_i915_gem_request *head_req = NULL;
2181 int count = 0;
2182
2183 seq_printf(m, "%s\n", engine->name);
2184
2185 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2186 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2187 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2188 status, ctx_id);
2189
2190 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2191 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2192
2193 read_pointer = engine->next_context_status_buffer;
2194 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2195 if (read_pointer > write_pointer)
2196 write_pointer += GEN8_CSB_ENTRIES;
2197 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2198 read_pointer, write_pointer);
2199
2200 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2201 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2202 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2203
2204 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2205 i, status, ctx_id);
2206 }
2207
2208 spin_lock_bh(&engine->execlist_lock);
2209 list_for_each(cursor, &engine->execlist_queue)
2210 count++;
2211 head_req = list_first_entry_or_null(&engine->execlist_queue,
2212 struct drm_i915_gem_request,
2213 execlist_link);
2214 spin_unlock_bh(&engine->execlist_lock);
2215
2216 seq_printf(m, "\t%d requests in queue\n", count);
2217 if (head_req) {
2218 seq_printf(m, "\tHead request context: %u\n",
2219 head_req->ctx->hw_id);
2220 seq_printf(m, "\tHead request tail: %u\n",
2221 head_req->tail);
2222 }
2223
2224 seq_putc(m, '\n');
2225 }
2226
2227 intel_runtime_pm_put(dev_priv);
2228 mutex_unlock(&dev->struct_mutex);
2229
2230 return 0;
2231 }
2232
2233 static const char *swizzle_string(unsigned swizzle)
2234 {
2235 switch (swizzle) {
2236 case I915_BIT_6_SWIZZLE_NONE:
2237 return "none";
2238 case I915_BIT_6_SWIZZLE_9:
2239 return "bit9";
2240 case I915_BIT_6_SWIZZLE_9_10:
2241 return "bit9/bit10";
2242 case I915_BIT_6_SWIZZLE_9_11:
2243 return "bit9/bit11";
2244 case I915_BIT_6_SWIZZLE_9_10_11:
2245 return "bit9/bit10/bit11";
2246 case I915_BIT_6_SWIZZLE_9_17:
2247 return "bit9/bit17";
2248 case I915_BIT_6_SWIZZLE_9_10_17:
2249 return "bit9/bit10/bit17";
2250 case I915_BIT_6_SWIZZLE_UNKNOWN:
2251 return "unknown";
2252 }
2253
2254 return "bug";
2255 }
2256
2257 static int i915_swizzle_info(struct seq_file *m, void *data)
2258 {
2259 struct drm_info_node *node = m->private;
2260 struct drm_device *dev = node->minor->dev;
2261 struct drm_i915_private *dev_priv = to_i915(dev);
2262 int ret;
2263
2264 ret = mutex_lock_interruptible(&dev->struct_mutex);
2265 if (ret)
2266 return ret;
2267 intel_runtime_pm_get(dev_priv);
2268
2269 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2270 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2271 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2272 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2273
2274 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2275 seq_printf(m, "DDC = 0x%08x\n",
2276 I915_READ(DCC));
2277 seq_printf(m, "DDC2 = 0x%08x\n",
2278 I915_READ(DCC2));
2279 seq_printf(m, "C0DRB3 = 0x%04x\n",
2280 I915_READ16(C0DRB3));
2281 seq_printf(m, "C1DRB3 = 0x%04x\n",
2282 I915_READ16(C1DRB3));
2283 } else if (INTEL_INFO(dev)->gen >= 6) {
2284 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2285 I915_READ(MAD_DIMM_C0));
2286 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2287 I915_READ(MAD_DIMM_C1));
2288 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2289 I915_READ(MAD_DIMM_C2));
2290 seq_printf(m, "TILECTL = 0x%08x\n",
2291 I915_READ(TILECTL));
2292 if (INTEL_INFO(dev)->gen >= 8)
2293 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2294 I915_READ(GAMTARBMODE));
2295 else
2296 seq_printf(m, "ARB_MODE = 0x%08x\n",
2297 I915_READ(ARB_MODE));
2298 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2299 I915_READ(DISP_ARB_CTL));
2300 }
2301
2302 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2303 seq_puts(m, "L-shaped memory detected\n");
2304
2305 intel_runtime_pm_put(dev_priv);
2306 mutex_unlock(&dev->struct_mutex);
2307
2308 return 0;
2309 }
2310
2311 static int per_file_ctx(int id, void *ptr, void *data)
2312 {
2313 struct i915_gem_context *ctx = ptr;
2314 struct seq_file *m = data;
2315 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2316
2317 if (!ppgtt) {
2318 seq_printf(m, " no ppgtt for context %d\n",
2319 ctx->user_handle);
2320 return 0;
2321 }
2322
2323 if (i915_gem_context_is_default(ctx))
2324 seq_puts(m, " default context:\n");
2325 else
2326 seq_printf(m, " context %d:\n", ctx->user_handle);
2327 ppgtt->debug_dump(ppgtt, m);
2328
2329 return 0;
2330 }
2331
2332 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2333 {
2334 struct drm_i915_private *dev_priv = to_i915(dev);
2335 struct intel_engine_cs *engine;
2336 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2337 int i;
2338
2339 if (!ppgtt)
2340 return;
2341
2342 for_each_engine(engine, dev_priv) {
2343 seq_printf(m, "%s\n", engine->name);
2344 for (i = 0; i < 4; i++) {
2345 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2346 pdp <<= 32;
2347 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2348 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2349 }
2350 }
2351 }
2352
2353 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2354 {
2355 struct drm_i915_private *dev_priv = to_i915(dev);
2356 struct intel_engine_cs *engine;
2357
2358 if (IS_GEN6(dev_priv))
2359 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2360
2361 for_each_engine(engine, dev_priv) {
2362 seq_printf(m, "%s\n", engine->name);
2363 if (IS_GEN7(dev_priv))
2364 seq_printf(m, "GFX_MODE: 0x%08x\n",
2365 I915_READ(RING_MODE_GEN7(engine)));
2366 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2367 I915_READ(RING_PP_DIR_BASE(engine)));
2368 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2369 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2370 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2371 I915_READ(RING_PP_DIR_DCLV(engine)));
2372 }
2373 if (dev_priv->mm.aliasing_ppgtt) {
2374 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2375
2376 seq_puts(m, "aliasing PPGTT:\n");
2377 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2378
2379 ppgtt->debug_dump(ppgtt, m);
2380 }
2381
2382 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2383 }
2384
2385 static int i915_ppgtt_info(struct seq_file *m, void *data)
2386 {
2387 struct drm_info_node *node = m->private;
2388 struct drm_device *dev = node->minor->dev;
2389 struct drm_i915_private *dev_priv = to_i915(dev);
2390 struct drm_file *file;
2391
2392 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2393 if (ret)
2394 return ret;
2395 intel_runtime_pm_get(dev_priv);
2396
2397 if (INTEL_INFO(dev)->gen >= 8)
2398 gen8_ppgtt_info(m, dev);
2399 else if (INTEL_INFO(dev)->gen >= 6)
2400 gen6_ppgtt_info(m, dev);
2401
2402 mutex_lock(&dev->filelist_mutex);
2403 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2404 struct drm_i915_file_private *file_priv = file->driver_priv;
2405 struct task_struct *task;
2406
2407 task = get_pid_task(file->pid, PIDTYPE_PID);
2408 if (!task) {
2409 ret = -ESRCH;
2410 goto out_unlock;
2411 }
2412 seq_printf(m, "\nproc: %s\n", task->comm);
2413 put_task_struct(task);
2414 idr_for_each(&file_priv->context_idr, per_file_ctx,
2415 (void *)(unsigned long)m);
2416 }
2417 out_unlock:
2418 mutex_unlock(&dev->filelist_mutex);
2419
2420 intel_runtime_pm_put(dev_priv);
2421 mutex_unlock(&dev->struct_mutex);
2422
2423 return ret;
2424 }
2425
2426 static int count_irq_waiters(struct drm_i915_private *i915)
2427 {
2428 struct intel_engine_cs *engine;
2429 int count = 0;
2430
2431 for_each_engine(engine, i915)
2432 count += intel_engine_has_waiter(engine);
2433
2434 return count;
2435 }
2436
2437 static int i915_rps_boost_info(struct seq_file *m, void *data)
2438 {
2439 struct drm_info_node *node = m->private;
2440 struct drm_device *dev = node->minor->dev;
2441 struct drm_i915_private *dev_priv = to_i915(dev);
2442 struct drm_file *file;
2443
2444 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2445 seq_printf(m, "GPU busy? %s [%x]\n",
2446 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2447 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2448 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2449 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2450 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2451 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2452 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2453 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2454
2455 mutex_lock(&dev->filelist_mutex);
2456 spin_lock(&dev_priv->rps.client_lock);
2457 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2458 struct drm_i915_file_private *file_priv = file->driver_priv;
2459 struct task_struct *task;
2460
2461 rcu_read_lock();
2462 task = pid_task(file->pid, PIDTYPE_PID);
2463 seq_printf(m, "%s [%d]: %d boosts%s\n",
2464 task ? task->comm : "<unknown>",
2465 task ? task->pid : -1,
2466 file_priv->rps.boosts,
2467 list_empty(&file_priv->rps.link) ? "" : ", active");
2468 rcu_read_unlock();
2469 }
2470 seq_printf(m, "Semaphore boosts: %d%s\n",
2471 dev_priv->rps.semaphores.boosts,
2472 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2473 seq_printf(m, "MMIO flip boosts: %d%s\n",
2474 dev_priv->rps.mmioflips.boosts,
2475 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2476 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2477 spin_unlock(&dev_priv->rps.client_lock);
2478 mutex_unlock(&dev->filelist_mutex);
2479
2480 return 0;
2481 }
2482
2483 static int i915_llc(struct seq_file *m, void *data)
2484 {
2485 struct drm_info_node *node = m->private;
2486 struct drm_device *dev = node->minor->dev;
2487 struct drm_i915_private *dev_priv = to_i915(dev);
2488 const bool edram = INTEL_GEN(dev_priv) > 8;
2489
2490 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2491 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2492 intel_uncore_edram_size(dev_priv)/1024/1024);
2493
2494 return 0;
2495 }
2496
2497 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2498 {
2499 struct drm_info_node *node = m->private;
2500 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2501 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2502 u32 tmp, i;
2503
2504 if (!HAS_GUC_UCODE(dev_priv))
2505 return 0;
2506
2507 seq_printf(m, "GuC firmware status:\n");
2508 seq_printf(m, "\tpath: %s\n",
2509 guc_fw->guc_fw_path);
2510 seq_printf(m, "\tfetch: %s\n",
2511 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2512 seq_printf(m, "\tload: %s\n",
2513 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2514 seq_printf(m, "\tversion wanted: %d.%d\n",
2515 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2516 seq_printf(m, "\tversion found: %d.%d\n",
2517 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2518 seq_printf(m, "\theader: offset is %d; size = %d\n",
2519 guc_fw->header_offset, guc_fw->header_size);
2520 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2521 guc_fw->ucode_offset, guc_fw->ucode_size);
2522 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2523 guc_fw->rsa_offset, guc_fw->rsa_size);
2524
2525 tmp = I915_READ(GUC_STATUS);
2526
2527 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2528 seq_printf(m, "\tBootrom status = 0x%x\n",
2529 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2530 seq_printf(m, "\tuKernel status = 0x%x\n",
2531 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2532 seq_printf(m, "\tMIA Core status = 0x%x\n",
2533 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2534 seq_puts(m, "\nScratch registers:\n");
2535 for (i = 0; i < 16; i++)
2536 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2537
2538 return 0;
2539 }
2540
2541 static void i915_guc_client_info(struct seq_file *m,
2542 struct drm_i915_private *dev_priv,
2543 struct i915_guc_client *client)
2544 {
2545 struct intel_engine_cs *engine;
2546 uint64_t tot = 0;
2547
2548 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2549 client->priority, client->ctx_index, client->proc_desc_offset);
2550 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2551 client->doorbell_id, client->doorbell_offset, client->cookie);
2552 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2553 client->wq_size, client->wq_offset, client->wq_tail);
2554
2555 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2556 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2557 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2558 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2559
2560 for_each_engine(engine, dev_priv) {
2561 seq_printf(m, "\tSubmissions: %llu %s\n",
2562 client->submissions[engine->id],
2563 engine->name);
2564 tot += client->submissions[engine->id];
2565 }
2566 seq_printf(m, "\tTotal: %llu\n", tot);
2567 }
2568
2569 static int i915_guc_info(struct seq_file *m, void *data)
2570 {
2571 struct drm_info_node *node = m->private;
2572 struct drm_device *dev = node->minor->dev;
2573 struct drm_i915_private *dev_priv = to_i915(dev);
2574 struct intel_guc guc;
2575 struct i915_guc_client client = {};
2576 struct intel_engine_cs *engine;
2577 u64 total = 0;
2578
2579 if (!HAS_GUC_SCHED(dev_priv))
2580 return 0;
2581
2582 if (mutex_lock_interruptible(&dev->struct_mutex))
2583 return 0;
2584
2585 /* Take a local copy of the GuC data, so we can dump it at leisure */
2586 guc = dev_priv->guc;
2587 if (guc.execbuf_client)
2588 client = *guc.execbuf_client;
2589
2590 mutex_unlock(&dev->struct_mutex);
2591
2592 seq_printf(m, "Doorbell map:\n");
2593 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2594 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2595
2596 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2597 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2598 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2599 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2600 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2601
2602 seq_printf(m, "\nGuC submissions:\n");
2603 for_each_engine(engine, dev_priv) {
2604 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2605 engine->name, guc.submissions[engine->id],
2606 guc.last_seqno[engine->id]);
2607 total += guc.submissions[engine->id];
2608 }
2609 seq_printf(m, "\t%s: %llu\n", "Total", total);
2610
2611 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2612 i915_guc_client_info(m, dev_priv, &client);
2613
2614 /* Add more as required ... */
2615
2616 return 0;
2617 }
2618
2619 static int i915_guc_log_dump(struct seq_file *m, void *data)
2620 {
2621 struct drm_info_node *node = m->private;
2622 struct drm_device *dev = node->minor->dev;
2623 struct drm_i915_private *dev_priv = to_i915(dev);
2624 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2625 u32 *log;
2626 int i = 0, pg;
2627
2628 if (!log_obj)
2629 return 0;
2630
2631 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2632 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2633
2634 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2635 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2636 *(log + i), *(log + i + 1),
2637 *(log + i + 2), *(log + i + 3));
2638
2639 kunmap_atomic(log);
2640 }
2641
2642 seq_putc(m, '\n');
2643
2644 return 0;
2645 }
2646
2647 static int i915_edp_psr_status(struct seq_file *m, void *data)
2648 {
2649 struct drm_info_node *node = m->private;
2650 struct drm_device *dev = node->minor->dev;
2651 struct drm_i915_private *dev_priv = to_i915(dev);
2652 u32 psrperf = 0;
2653 u32 stat[3];
2654 enum pipe pipe;
2655 bool enabled = false;
2656
2657 if (!HAS_PSR(dev)) {
2658 seq_puts(m, "PSR not supported\n");
2659 return 0;
2660 }
2661
2662 intel_runtime_pm_get(dev_priv);
2663
2664 mutex_lock(&dev_priv->psr.lock);
2665 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2666 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2667 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2668 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2669 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2670 dev_priv->psr.busy_frontbuffer_bits);
2671 seq_printf(m, "Re-enable work scheduled: %s\n",
2672 yesno(work_busy(&dev_priv->psr.work.work)));
2673
2674 if (HAS_DDI(dev))
2675 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2676 else {
2677 for_each_pipe(dev_priv, pipe) {
2678 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2679 VLV_EDP_PSR_CURR_STATE_MASK;
2680 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2681 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2682 enabled = true;
2683 }
2684 }
2685
2686 seq_printf(m, "Main link in standby mode: %s\n",
2687 yesno(dev_priv->psr.link_standby));
2688
2689 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2690
2691 if (!HAS_DDI(dev))
2692 for_each_pipe(dev_priv, pipe) {
2693 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2694 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2695 seq_printf(m, " pipe %c", pipe_name(pipe));
2696 }
2697 seq_puts(m, "\n");
2698
2699 /*
2700 * VLV/CHV PSR has no kind of performance counter
2701 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2702 */
2703 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2704 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2705 EDP_PSR_PERF_CNT_MASK;
2706
2707 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2708 }
2709 mutex_unlock(&dev_priv->psr.lock);
2710
2711 intel_runtime_pm_put(dev_priv);
2712 return 0;
2713 }
2714
2715 static int i915_sink_crc(struct seq_file *m, void *data)
2716 {
2717 struct drm_info_node *node = m->private;
2718 struct drm_device *dev = node->minor->dev;
2719 struct intel_connector *connector;
2720 struct intel_dp *intel_dp = NULL;
2721 int ret;
2722 u8 crc[6];
2723
2724 drm_modeset_lock_all(dev);
2725 for_each_intel_connector(dev, connector) {
2726 struct drm_crtc *crtc;
2727
2728 if (!connector->base.state->best_encoder)
2729 continue;
2730
2731 crtc = connector->base.state->crtc;
2732 if (!crtc->state->active)
2733 continue;
2734
2735 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2736 continue;
2737
2738 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2739
2740 ret = intel_dp_sink_crc(intel_dp, crc);
2741 if (ret)
2742 goto out;
2743
2744 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2745 crc[0], crc[1], crc[2],
2746 crc[3], crc[4], crc[5]);
2747 goto out;
2748 }
2749 ret = -ENODEV;
2750 out:
2751 drm_modeset_unlock_all(dev);
2752 return ret;
2753 }
2754
2755 static int i915_energy_uJ(struct seq_file *m, void *data)
2756 {
2757 struct drm_info_node *node = m->private;
2758 struct drm_device *dev = node->minor->dev;
2759 struct drm_i915_private *dev_priv = to_i915(dev);
2760 u64 power;
2761 u32 units;
2762
2763 if (INTEL_INFO(dev)->gen < 6)
2764 return -ENODEV;
2765
2766 intel_runtime_pm_get(dev_priv);
2767
2768 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2769 power = (power & 0x1f00) >> 8;
2770 units = 1000000 / (1 << power); /* convert to uJ */
2771 power = I915_READ(MCH_SECP_NRG_STTS);
2772 power *= units;
2773
2774 intel_runtime_pm_put(dev_priv);
2775
2776 seq_printf(m, "%llu", (long long unsigned)power);
2777
2778 return 0;
2779 }
2780
2781 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2782 {
2783 struct drm_info_node *node = m->private;
2784 struct drm_device *dev = node->minor->dev;
2785 struct drm_i915_private *dev_priv = to_i915(dev);
2786
2787 if (!HAS_RUNTIME_PM(dev_priv))
2788 seq_puts(m, "Runtime power management not supported\n");
2789
2790 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2791 seq_printf(m, "IRQs disabled: %s\n",
2792 yesno(!intel_irqs_enabled(dev_priv)));
2793 #ifdef CONFIG_PM
2794 seq_printf(m, "Usage count: %d\n",
2795 atomic_read(&dev->dev->power.usage_count));
2796 #else
2797 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2798 #endif
2799 seq_printf(m, "PCI device power state: %s [%d]\n",
2800 pci_power_name(dev_priv->drm.pdev->current_state),
2801 dev_priv->drm.pdev->current_state);
2802
2803 return 0;
2804 }
2805
2806 static int i915_power_domain_info(struct seq_file *m, void *unused)
2807 {
2808 struct drm_info_node *node = m->private;
2809 struct drm_device *dev = node->minor->dev;
2810 struct drm_i915_private *dev_priv = to_i915(dev);
2811 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2812 int i;
2813
2814 mutex_lock(&power_domains->lock);
2815
2816 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2817 for (i = 0; i < power_domains->power_well_count; i++) {
2818 struct i915_power_well *power_well;
2819 enum intel_display_power_domain power_domain;
2820
2821 power_well = &power_domains->power_wells[i];
2822 seq_printf(m, "%-25s %d\n", power_well->name,
2823 power_well->count);
2824
2825 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2826 power_domain++) {
2827 if (!(BIT(power_domain) & power_well->domains))
2828 continue;
2829
2830 seq_printf(m, " %-23s %d\n",
2831 intel_display_power_domain_str(power_domain),
2832 power_domains->domain_use_count[power_domain]);
2833 }
2834 }
2835
2836 mutex_unlock(&power_domains->lock);
2837
2838 return 0;
2839 }
2840
2841 static int i915_dmc_info(struct seq_file *m, void *unused)
2842 {
2843 struct drm_info_node *node = m->private;
2844 struct drm_device *dev = node->minor->dev;
2845 struct drm_i915_private *dev_priv = to_i915(dev);
2846 struct intel_csr *csr;
2847
2848 if (!HAS_CSR(dev)) {
2849 seq_puts(m, "not supported\n");
2850 return 0;
2851 }
2852
2853 csr = &dev_priv->csr;
2854
2855 intel_runtime_pm_get(dev_priv);
2856
2857 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2858 seq_printf(m, "path: %s\n", csr->fw_path);
2859
2860 if (!csr->dmc_payload)
2861 goto out;
2862
2863 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2864 CSR_VERSION_MINOR(csr->version));
2865
2866 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2867 seq_printf(m, "DC3 -> DC5 count: %d\n",
2868 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2869 seq_printf(m, "DC5 -> DC6 count: %d\n",
2870 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2871 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2872 seq_printf(m, "DC3 -> DC5 count: %d\n",
2873 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2874 }
2875
2876 out:
2877 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2878 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2879 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2880
2881 intel_runtime_pm_put(dev_priv);
2882
2883 return 0;
2884 }
2885
2886 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2887 struct drm_display_mode *mode)
2888 {
2889 int i;
2890
2891 for (i = 0; i < tabs; i++)
2892 seq_putc(m, '\t');
2893
2894 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2895 mode->base.id, mode->name,
2896 mode->vrefresh, mode->clock,
2897 mode->hdisplay, mode->hsync_start,
2898 mode->hsync_end, mode->htotal,
2899 mode->vdisplay, mode->vsync_start,
2900 mode->vsync_end, mode->vtotal,
2901 mode->type, mode->flags);
2902 }
2903
2904 static void intel_encoder_info(struct seq_file *m,
2905 struct intel_crtc *intel_crtc,
2906 struct intel_encoder *intel_encoder)
2907 {
2908 struct drm_info_node *node = m->private;
2909 struct drm_device *dev = node->minor->dev;
2910 struct drm_crtc *crtc = &intel_crtc->base;
2911 struct intel_connector *intel_connector;
2912 struct drm_encoder *encoder;
2913
2914 encoder = &intel_encoder->base;
2915 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2916 encoder->base.id, encoder->name);
2917 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2918 struct drm_connector *connector = &intel_connector->base;
2919 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2920 connector->base.id,
2921 connector->name,
2922 drm_get_connector_status_name(connector->status));
2923 if (connector->status == connector_status_connected) {
2924 struct drm_display_mode *mode = &crtc->mode;
2925 seq_printf(m, ", mode:\n");
2926 intel_seq_print_mode(m, 2, mode);
2927 } else {
2928 seq_putc(m, '\n');
2929 }
2930 }
2931 }
2932
2933 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2934 {
2935 struct drm_info_node *node = m->private;
2936 struct drm_device *dev = node->minor->dev;
2937 struct drm_crtc *crtc = &intel_crtc->base;
2938 struct intel_encoder *intel_encoder;
2939 struct drm_plane_state *plane_state = crtc->primary->state;
2940 struct drm_framebuffer *fb = plane_state->fb;
2941
2942 if (fb)
2943 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2944 fb->base.id, plane_state->src_x >> 16,
2945 plane_state->src_y >> 16, fb->width, fb->height);
2946 else
2947 seq_puts(m, "\tprimary plane disabled\n");
2948 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2949 intel_encoder_info(m, intel_crtc, intel_encoder);
2950 }
2951
2952 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2953 {
2954 struct drm_display_mode *mode = panel->fixed_mode;
2955
2956 seq_printf(m, "\tfixed mode:\n");
2957 intel_seq_print_mode(m, 2, mode);
2958 }
2959
2960 static void intel_dp_info(struct seq_file *m,
2961 struct intel_connector *intel_connector)
2962 {
2963 struct intel_encoder *intel_encoder = intel_connector->encoder;
2964 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2965
2966 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2967 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2968 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2969 intel_panel_info(m, &intel_connector->panel);
2970 }
2971
2972 static void intel_hdmi_info(struct seq_file *m,
2973 struct intel_connector *intel_connector)
2974 {
2975 struct intel_encoder *intel_encoder = intel_connector->encoder;
2976 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2977
2978 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2979 }
2980
2981 static void intel_lvds_info(struct seq_file *m,
2982 struct intel_connector *intel_connector)
2983 {
2984 intel_panel_info(m, &intel_connector->panel);
2985 }
2986
2987 static void intel_connector_info(struct seq_file *m,
2988 struct drm_connector *connector)
2989 {
2990 struct intel_connector *intel_connector = to_intel_connector(connector);
2991 struct intel_encoder *intel_encoder = intel_connector->encoder;
2992 struct drm_display_mode *mode;
2993
2994 seq_printf(m, "connector %d: type %s, status: %s\n",
2995 connector->base.id, connector->name,
2996 drm_get_connector_status_name(connector->status));
2997 if (connector->status == connector_status_connected) {
2998 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2999 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3000 connector->display_info.width_mm,
3001 connector->display_info.height_mm);
3002 seq_printf(m, "\tsubpixel order: %s\n",
3003 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3004 seq_printf(m, "\tCEA rev: %d\n",
3005 connector->display_info.cea_rev);
3006 }
3007
3008 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3009 return;
3010
3011 switch (connector->connector_type) {
3012 case DRM_MODE_CONNECTOR_DisplayPort:
3013 case DRM_MODE_CONNECTOR_eDP:
3014 intel_dp_info(m, intel_connector);
3015 break;
3016 case DRM_MODE_CONNECTOR_LVDS:
3017 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3018 intel_lvds_info(m, intel_connector);
3019 break;
3020 case DRM_MODE_CONNECTOR_HDMIA:
3021 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3022 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3023 intel_hdmi_info(m, intel_connector);
3024 break;
3025 default:
3026 break;
3027 }
3028
3029 seq_printf(m, "\tmodes:\n");
3030 list_for_each_entry(mode, &connector->modes, head)
3031 intel_seq_print_mode(m, 2, mode);
3032 }
3033
3034 static bool cursor_active(struct drm_device *dev, int pipe)
3035 {
3036 struct drm_i915_private *dev_priv = to_i915(dev);
3037 u32 state;
3038
3039 if (IS_845G(dev) || IS_I865G(dev))
3040 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3041 else
3042 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3043
3044 return state;
3045 }
3046
3047 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3048 {
3049 struct drm_i915_private *dev_priv = to_i915(dev);
3050 u32 pos;
3051
3052 pos = I915_READ(CURPOS(pipe));
3053
3054 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3055 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3056 *x = -*x;
3057
3058 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3059 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3060 *y = -*y;
3061
3062 return cursor_active(dev, pipe);
3063 }
3064
3065 static const char *plane_type(enum drm_plane_type type)
3066 {
3067 switch (type) {
3068 case DRM_PLANE_TYPE_OVERLAY:
3069 return "OVL";
3070 case DRM_PLANE_TYPE_PRIMARY:
3071 return "PRI";
3072 case DRM_PLANE_TYPE_CURSOR:
3073 return "CUR";
3074 /*
3075 * Deliberately omitting default: to generate compiler warnings
3076 * when a new drm_plane_type gets added.
3077 */
3078 }
3079
3080 return "unknown";
3081 }
3082
3083 static const char *plane_rotation(unsigned int rotation)
3084 {
3085 static char buf[48];
3086 /*
3087 * According to doc only one DRM_ROTATE_ is allowed but this
3088 * will print them all to visualize if the values are misused
3089 */
3090 snprintf(buf, sizeof(buf),
3091 "%s%s%s%s%s%s(0x%08x)",
3092 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3093 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3094 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3095 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3096 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3097 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3098 rotation);
3099
3100 return buf;
3101 }
3102
3103 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3104 {
3105 struct drm_info_node *node = m->private;
3106 struct drm_device *dev = node->minor->dev;
3107 struct intel_plane *intel_plane;
3108
3109 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3110 struct drm_plane_state *state;
3111 struct drm_plane *plane = &intel_plane->base;
3112
3113 if (!plane->state) {
3114 seq_puts(m, "plane->state is NULL!\n");
3115 continue;
3116 }
3117
3118 state = plane->state;
3119
3120 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3121 plane->base.id,
3122 plane_type(intel_plane->base.type),
3123 state->crtc_x, state->crtc_y,
3124 state->crtc_w, state->crtc_h,
3125 (state->src_x >> 16),
3126 ((state->src_x & 0xffff) * 15625) >> 10,
3127 (state->src_y >> 16),
3128 ((state->src_y & 0xffff) * 15625) >> 10,
3129 (state->src_w >> 16),
3130 ((state->src_w & 0xffff) * 15625) >> 10,
3131 (state->src_h >> 16),
3132 ((state->src_h & 0xffff) * 15625) >> 10,
3133 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3134 plane_rotation(state->rotation));
3135 }
3136 }
3137
3138 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3139 {
3140 struct intel_crtc_state *pipe_config;
3141 int num_scalers = intel_crtc->num_scalers;
3142 int i;
3143
3144 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3145
3146 /* Not all platformas have a scaler */
3147 if (num_scalers) {
3148 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3149 num_scalers,
3150 pipe_config->scaler_state.scaler_users,
3151 pipe_config->scaler_state.scaler_id);
3152
3153 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3154 struct intel_scaler *sc =
3155 &pipe_config->scaler_state.scalers[i];
3156
3157 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3158 i, yesno(sc->in_use), sc->mode);
3159 }
3160 seq_puts(m, "\n");
3161 } else {
3162 seq_puts(m, "\tNo scalers available on this platform\n");
3163 }
3164 }
3165
3166 static int i915_display_info(struct seq_file *m, void *unused)
3167 {
3168 struct drm_info_node *node = m->private;
3169 struct drm_device *dev = node->minor->dev;
3170 struct drm_i915_private *dev_priv = to_i915(dev);
3171 struct intel_crtc *crtc;
3172 struct drm_connector *connector;
3173
3174 intel_runtime_pm_get(dev_priv);
3175 drm_modeset_lock_all(dev);
3176 seq_printf(m, "CRTC info\n");
3177 seq_printf(m, "---------\n");
3178 for_each_intel_crtc(dev, crtc) {
3179 bool active;
3180 struct intel_crtc_state *pipe_config;
3181 int x, y;
3182
3183 pipe_config = to_intel_crtc_state(crtc->base.state);
3184
3185 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3186 crtc->base.base.id, pipe_name(crtc->pipe),
3187 yesno(pipe_config->base.active),
3188 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3189 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3190
3191 if (pipe_config->base.active) {
3192 intel_crtc_info(m, crtc);
3193
3194 active = cursor_position(dev, crtc->pipe, &x, &y);
3195 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3196 yesno(crtc->cursor_base),
3197 x, y, crtc->base.cursor->state->crtc_w,
3198 crtc->base.cursor->state->crtc_h,
3199 crtc->cursor_addr, yesno(active));
3200 intel_scaler_info(m, crtc);
3201 intel_plane_info(m, crtc);
3202 }
3203
3204 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3205 yesno(!crtc->cpu_fifo_underrun_disabled),
3206 yesno(!crtc->pch_fifo_underrun_disabled));
3207 }
3208
3209 seq_printf(m, "\n");
3210 seq_printf(m, "Connector info\n");
3211 seq_printf(m, "--------------\n");
3212 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3213 intel_connector_info(m, connector);
3214 }
3215 drm_modeset_unlock_all(dev);
3216 intel_runtime_pm_put(dev_priv);
3217
3218 return 0;
3219 }
3220
3221 static int i915_semaphore_status(struct seq_file *m, void *unused)
3222 {
3223 struct drm_info_node *node = (struct drm_info_node *) m->private;
3224 struct drm_device *dev = node->minor->dev;
3225 struct drm_i915_private *dev_priv = to_i915(dev);
3226 struct intel_engine_cs *engine;
3227 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3228 enum intel_engine_id id;
3229 int j, ret;
3230
3231 if (!i915_semaphore_is_enabled(dev_priv)) {
3232 seq_puts(m, "Semaphores are disabled\n");
3233 return 0;
3234 }
3235
3236 ret = mutex_lock_interruptible(&dev->struct_mutex);
3237 if (ret)
3238 return ret;
3239 intel_runtime_pm_get(dev_priv);
3240
3241 if (IS_BROADWELL(dev)) {
3242 struct page *page;
3243 uint64_t *seqno;
3244
3245 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3246
3247 seqno = (uint64_t *)kmap_atomic(page);
3248 for_each_engine_id(engine, dev_priv, id) {
3249 uint64_t offset;
3250
3251 seq_printf(m, "%s\n", engine->name);
3252
3253 seq_puts(m, " Last signal:");
3254 for (j = 0; j < num_rings; j++) {
3255 offset = id * I915_NUM_ENGINES + j;
3256 seq_printf(m, "0x%08llx (0x%02llx) ",
3257 seqno[offset], offset * 8);
3258 }
3259 seq_putc(m, '\n');
3260
3261 seq_puts(m, " Last wait: ");
3262 for (j = 0; j < num_rings; j++) {
3263 offset = id + (j * I915_NUM_ENGINES);
3264 seq_printf(m, "0x%08llx (0x%02llx) ",
3265 seqno[offset], offset * 8);
3266 }
3267 seq_putc(m, '\n');
3268
3269 }
3270 kunmap_atomic(seqno);
3271 } else {
3272 seq_puts(m, " Last signal:");
3273 for_each_engine(engine, dev_priv)
3274 for (j = 0; j < num_rings; j++)
3275 seq_printf(m, "0x%08x\n",
3276 I915_READ(engine->semaphore.mbox.signal[j]));
3277 seq_putc(m, '\n');
3278 }
3279
3280 seq_puts(m, "\nSync seqno:\n");
3281 for_each_engine(engine, dev_priv) {
3282 for (j = 0; j < num_rings; j++)
3283 seq_printf(m, " 0x%08x ",
3284 engine->semaphore.sync_seqno[j]);
3285 seq_putc(m, '\n');
3286 }
3287 seq_putc(m, '\n');
3288
3289 intel_runtime_pm_put(dev_priv);
3290 mutex_unlock(&dev->struct_mutex);
3291 return 0;
3292 }
3293
3294 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3295 {
3296 struct drm_info_node *node = (struct drm_info_node *) m->private;
3297 struct drm_device *dev = node->minor->dev;
3298 struct drm_i915_private *dev_priv = to_i915(dev);
3299 int i;
3300
3301 drm_modeset_lock_all(dev);
3302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3303 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3304
3305 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3306 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3307 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3308 seq_printf(m, " tracked hardware state:\n");
3309 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3310 seq_printf(m, " dpll_md: 0x%08x\n",
3311 pll->config.hw_state.dpll_md);
3312 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3313 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3314 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3315 }
3316 drm_modeset_unlock_all(dev);
3317
3318 return 0;
3319 }
3320
3321 static int i915_wa_registers(struct seq_file *m, void *unused)
3322 {
3323 int i;
3324 int ret;
3325 struct intel_engine_cs *engine;
3326 struct drm_info_node *node = (struct drm_info_node *) m->private;
3327 struct drm_device *dev = node->minor->dev;
3328 struct drm_i915_private *dev_priv = to_i915(dev);
3329 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3330 enum intel_engine_id id;
3331
3332 ret = mutex_lock_interruptible(&dev->struct_mutex);
3333 if (ret)
3334 return ret;
3335
3336 intel_runtime_pm_get(dev_priv);
3337
3338 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3339 for_each_engine_id(engine, dev_priv, id)
3340 seq_printf(m, "HW whitelist count for %s: %d\n",
3341 engine->name, workarounds->hw_whitelist_count[id]);
3342 for (i = 0; i < workarounds->count; ++i) {
3343 i915_reg_t addr;
3344 u32 mask, value, read;
3345 bool ok;
3346
3347 addr = workarounds->reg[i].addr;
3348 mask = workarounds->reg[i].mask;
3349 value = workarounds->reg[i].value;
3350 read = I915_READ(addr);
3351 ok = (value & mask) == (read & mask);
3352 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3353 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3354 }
3355
3356 intel_runtime_pm_put(dev_priv);
3357 mutex_unlock(&dev->struct_mutex);
3358
3359 return 0;
3360 }
3361
3362 static int i915_ddb_info(struct seq_file *m, void *unused)
3363 {
3364 struct drm_info_node *node = m->private;
3365 struct drm_device *dev = node->minor->dev;
3366 struct drm_i915_private *dev_priv = to_i915(dev);
3367 struct skl_ddb_allocation *ddb;
3368 struct skl_ddb_entry *entry;
3369 enum pipe pipe;
3370 int plane;
3371
3372 if (INTEL_INFO(dev)->gen < 9)
3373 return 0;
3374
3375 drm_modeset_lock_all(dev);
3376
3377 ddb = &dev_priv->wm.skl_hw.ddb;
3378
3379 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3380
3381 for_each_pipe(dev_priv, pipe) {
3382 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3383
3384 for_each_plane(dev_priv, pipe, plane) {
3385 entry = &ddb->plane[pipe][plane];
3386 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3387 entry->start, entry->end,
3388 skl_ddb_entry_size(entry));
3389 }
3390
3391 entry = &ddb->plane[pipe][PLANE_CURSOR];
3392 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3393 entry->end, skl_ddb_entry_size(entry));
3394 }
3395
3396 drm_modeset_unlock_all(dev);
3397
3398 return 0;
3399 }
3400
3401 static void drrs_status_per_crtc(struct seq_file *m,
3402 struct drm_device *dev, struct intel_crtc *intel_crtc)
3403 {
3404 struct drm_i915_private *dev_priv = to_i915(dev);
3405 struct i915_drrs *drrs = &dev_priv->drrs;
3406 int vrefresh = 0;
3407 struct drm_connector *connector;
3408
3409 drm_for_each_connector(connector, dev) {
3410 if (connector->state->crtc != &intel_crtc->base)
3411 continue;
3412
3413 seq_printf(m, "%s:\n", connector->name);
3414 }
3415
3416 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3417 seq_puts(m, "\tVBT: DRRS_type: Static");
3418 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3419 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3420 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3421 seq_puts(m, "\tVBT: DRRS_type: None");
3422 else
3423 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3424
3425 seq_puts(m, "\n\n");
3426
3427 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3428 struct intel_panel *panel;
3429
3430 mutex_lock(&drrs->mutex);
3431 /* DRRS Supported */
3432 seq_puts(m, "\tDRRS Supported: Yes\n");
3433
3434 /* disable_drrs() will make drrs->dp NULL */
3435 if (!drrs->dp) {
3436 seq_puts(m, "Idleness DRRS: Disabled");
3437 mutex_unlock(&drrs->mutex);
3438 return;
3439 }
3440
3441 panel = &drrs->dp->attached_connector->panel;
3442 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3443 drrs->busy_frontbuffer_bits);
3444
3445 seq_puts(m, "\n\t\t");
3446 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3447 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3448 vrefresh = panel->fixed_mode->vrefresh;
3449 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3450 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3451 vrefresh = panel->downclock_mode->vrefresh;
3452 } else {
3453 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3454 drrs->refresh_rate_type);
3455 mutex_unlock(&drrs->mutex);
3456 return;
3457 }
3458 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3459
3460 seq_puts(m, "\n\t\t");
3461 mutex_unlock(&drrs->mutex);
3462 } else {
3463 /* DRRS not supported. Print the VBT parameter*/
3464 seq_puts(m, "\tDRRS Supported : No");
3465 }
3466 seq_puts(m, "\n");
3467 }
3468
3469 static int i915_drrs_status(struct seq_file *m, void *unused)
3470 {
3471 struct drm_info_node *node = m->private;
3472 struct drm_device *dev = node->minor->dev;
3473 struct intel_crtc *intel_crtc;
3474 int active_crtc_cnt = 0;
3475
3476 drm_modeset_lock_all(dev);
3477 for_each_intel_crtc(dev, intel_crtc) {
3478 if (intel_crtc->base.state->active) {
3479 active_crtc_cnt++;
3480 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3481
3482 drrs_status_per_crtc(m, dev, intel_crtc);
3483 }
3484 }
3485 drm_modeset_unlock_all(dev);
3486
3487 if (!active_crtc_cnt)
3488 seq_puts(m, "No active crtc found\n");
3489
3490 return 0;
3491 }
3492
3493 struct pipe_crc_info {
3494 const char *name;
3495 struct drm_device *dev;
3496 enum pipe pipe;
3497 };
3498
3499 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3500 {
3501 struct drm_info_node *node = (struct drm_info_node *) m->private;
3502 struct drm_device *dev = node->minor->dev;
3503 struct intel_encoder *intel_encoder;
3504 struct intel_digital_port *intel_dig_port;
3505 struct drm_connector *connector;
3506
3507 drm_modeset_lock_all(dev);
3508 drm_for_each_connector(connector, dev) {
3509 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3510 continue;
3511
3512 intel_encoder = intel_attached_encoder(connector);
3513 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3514 continue;
3515
3516 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3517 if (!intel_dig_port->dp.can_mst)
3518 continue;
3519
3520 seq_printf(m, "MST Source Port %c\n",
3521 port_name(intel_dig_port->port));
3522 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3523 }
3524 drm_modeset_unlock_all(dev);
3525 return 0;
3526 }
3527
3528 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3529 {
3530 struct pipe_crc_info *info = inode->i_private;
3531 struct drm_i915_private *dev_priv = to_i915(info->dev);
3532 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3533
3534 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3535 return -ENODEV;
3536
3537 spin_lock_irq(&pipe_crc->lock);
3538
3539 if (pipe_crc->opened) {
3540 spin_unlock_irq(&pipe_crc->lock);
3541 return -EBUSY; /* already open */
3542 }
3543
3544 pipe_crc->opened = true;
3545 filep->private_data = inode->i_private;
3546
3547 spin_unlock_irq(&pipe_crc->lock);
3548
3549 return 0;
3550 }
3551
3552 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3553 {
3554 struct pipe_crc_info *info = inode->i_private;
3555 struct drm_i915_private *dev_priv = to_i915(info->dev);
3556 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3557
3558 spin_lock_irq(&pipe_crc->lock);
3559 pipe_crc->opened = false;
3560 spin_unlock_irq(&pipe_crc->lock);
3561
3562 return 0;
3563 }
3564
3565 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3566 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3567 /* account for \'0' */
3568 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3569
3570 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3571 {
3572 assert_spin_locked(&pipe_crc->lock);
3573 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3574 INTEL_PIPE_CRC_ENTRIES_NR);
3575 }
3576
3577 static ssize_t
3578 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3579 loff_t *pos)
3580 {
3581 struct pipe_crc_info *info = filep->private_data;
3582 struct drm_device *dev = info->dev;
3583 struct drm_i915_private *dev_priv = to_i915(dev);
3584 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3585 char buf[PIPE_CRC_BUFFER_LEN];
3586 int n_entries;
3587 ssize_t bytes_read;
3588
3589 /*
3590 * Don't allow user space to provide buffers not big enough to hold
3591 * a line of data.
3592 */
3593 if (count < PIPE_CRC_LINE_LEN)
3594 return -EINVAL;
3595
3596 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3597 return 0;
3598
3599 /* nothing to read */
3600 spin_lock_irq(&pipe_crc->lock);
3601 while (pipe_crc_data_count(pipe_crc) == 0) {
3602 int ret;
3603
3604 if (filep->f_flags & O_NONBLOCK) {
3605 spin_unlock_irq(&pipe_crc->lock);
3606 return -EAGAIN;
3607 }
3608
3609 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3610 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3611 if (ret) {
3612 spin_unlock_irq(&pipe_crc->lock);
3613 return ret;
3614 }
3615 }
3616
3617 /* We now have one or more entries to read */
3618 n_entries = count / PIPE_CRC_LINE_LEN;
3619
3620 bytes_read = 0;
3621 while (n_entries > 0) {
3622 struct intel_pipe_crc_entry *entry =
3623 &pipe_crc->entries[pipe_crc->tail];
3624 int ret;
3625
3626 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3627 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3628 break;
3629
3630 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3631 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3632
3633 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3634 "%8u %8x %8x %8x %8x %8x\n",
3635 entry->frame, entry->crc[0],
3636 entry->crc[1], entry->crc[2],
3637 entry->crc[3], entry->crc[4]);
3638
3639 spin_unlock_irq(&pipe_crc->lock);
3640
3641 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3642 if (ret == PIPE_CRC_LINE_LEN)
3643 return -EFAULT;
3644
3645 user_buf += PIPE_CRC_LINE_LEN;
3646 n_entries--;
3647
3648 spin_lock_irq(&pipe_crc->lock);
3649 }
3650
3651 spin_unlock_irq(&pipe_crc->lock);
3652
3653 return bytes_read;
3654 }
3655
3656 static const struct file_operations i915_pipe_crc_fops = {
3657 .owner = THIS_MODULE,
3658 .open = i915_pipe_crc_open,
3659 .read = i915_pipe_crc_read,
3660 .release = i915_pipe_crc_release,
3661 };
3662
3663 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3664 {
3665 .name = "i915_pipe_A_crc",
3666 .pipe = PIPE_A,
3667 },
3668 {
3669 .name = "i915_pipe_B_crc",
3670 .pipe = PIPE_B,
3671 },
3672 {
3673 .name = "i915_pipe_C_crc",
3674 .pipe = PIPE_C,
3675 },
3676 };
3677
3678 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3679 enum pipe pipe)
3680 {
3681 struct drm_device *dev = minor->dev;
3682 struct dentry *ent;
3683 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3684
3685 info->dev = dev;
3686 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3687 &i915_pipe_crc_fops);
3688 if (!ent)
3689 return -ENOMEM;
3690
3691 return drm_add_fake_info_node(minor, ent, info);
3692 }
3693
3694 static const char * const pipe_crc_sources[] = {
3695 "none",
3696 "plane1",
3697 "plane2",
3698 "pf",
3699 "pipe",
3700 "TV",
3701 "DP-B",
3702 "DP-C",
3703 "DP-D",
3704 "auto",
3705 };
3706
3707 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3708 {
3709 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3710 return pipe_crc_sources[source];
3711 }
3712
3713 static int display_crc_ctl_show(struct seq_file *m, void *data)
3714 {
3715 struct drm_device *dev = m->private;
3716 struct drm_i915_private *dev_priv = to_i915(dev);
3717 int i;
3718
3719 for (i = 0; i < I915_MAX_PIPES; i++)
3720 seq_printf(m, "%c %s\n", pipe_name(i),
3721 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3722
3723 return 0;
3724 }
3725
3726 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3727 {
3728 struct drm_device *dev = inode->i_private;
3729
3730 return single_open(file, display_crc_ctl_show, dev);
3731 }
3732
3733 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3734 uint32_t *val)
3735 {
3736 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3737 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3738
3739 switch (*source) {
3740 case INTEL_PIPE_CRC_SOURCE_PIPE:
3741 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3742 break;
3743 case INTEL_PIPE_CRC_SOURCE_NONE:
3744 *val = 0;
3745 break;
3746 default:
3747 return -EINVAL;
3748 }
3749
3750 return 0;
3751 }
3752
3753 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3754 enum intel_pipe_crc_source *source)
3755 {
3756 struct intel_encoder *encoder;
3757 struct intel_crtc *crtc;
3758 struct intel_digital_port *dig_port;
3759 int ret = 0;
3760
3761 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3762
3763 drm_modeset_lock_all(dev);
3764 for_each_intel_encoder(dev, encoder) {
3765 if (!encoder->base.crtc)
3766 continue;
3767
3768 crtc = to_intel_crtc(encoder->base.crtc);
3769
3770 if (crtc->pipe != pipe)
3771 continue;
3772
3773 switch (encoder->type) {
3774 case INTEL_OUTPUT_TVOUT:
3775 *source = INTEL_PIPE_CRC_SOURCE_TV;
3776 break;
3777 case INTEL_OUTPUT_DISPLAYPORT:
3778 case INTEL_OUTPUT_EDP:
3779 dig_port = enc_to_dig_port(&encoder->base);
3780 switch (dig_port->port) {
3781 case PORT_B:
3782 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3783 break;
3784 case PORT_C:
3785 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3786 break;
3787 case PORT_D:
3788 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3789 break;
3790 default:
3791 WARN(1, "nonexisting DP port %c\n",
3792 port_name(dig_port->port));
3793 break;
3794 }
3795 break;
3796 default:
3797 break;
3798 }
3799 }
3800 drm_modeset_unlock_all(dev);
3801
3802 return ret;
3803 }
3804
3805 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3806 enum pipe pipe,
3807 enum intel_pipe_crc_source *source,
3808 uint32_t *val)
3809 {
3810 struct drm_i915_private *dev_priv = to_i915(dev);
3811 bool need_stable_symbols = false;
3812
3813 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3814 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3815 if (ret)
3816 return ret;
3817 }
3818
3819 switch (*source) {
3820 case INTEL_PIPE_CRC_SOURCE_PIPE:
3821 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3822 break;
3823 case INTEL_PIPE_CRC_SOURCE_DP_B:
3824 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3825 need_stable_symbols = true;
3826 break;
3827 case INTEL_PIPE_CRC_SOURCE_DP_C:
3828 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3829 need_stable_symbols = true;
3830 break;
3831 case INTEL_PIPE_CRC_SOURCE_DP_D:
3832 if (!IS_CHERRYVIEW(dev))
3833 return -EINVAL;
3834 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3835 need_stable_symbols = true;
3836 break;
3837 case INTEL_PIPE_CRC_SOURCE_NONE:
3838 *val = 0;
3839 break;
3840 default:
3841 return -EINVAL;
3842 }
3843
3844 /*
3845 * When the pipe CRC tap point is after the transcoders we need
3846 * to tweak symbol-level features to produce a deterministic series of
3847 * symbols for a given frame. We need to reset those features only once
3848 * a frame (instead of every nth symbol):
3849 * - DC-balance: used to ensure a better clock recovery from the data
3850 * link (SDVO)
3851 * - DisplayPort scrambling: used for EMI reduction
3852 */
3853 if (need_stable_symbols) {
3854 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3855
3856 tmp |= DC_BALANCE_RESET_VLV;
3857 switch (pipe) {
3858 case PIPE_A:
3859 tmp |= PIPE_A_SCRAMBLE_RESET;
3860 break;
3861 case PIPE_B:
3862 tmp |= PIPE_B_SCRAMBLE_RESET;
3863 break;
3864 case PIPE_C:
3865 tmp |= PIPE_C_SCRAMBLE_RESET;
3866 break;
3867 default:
3868 return -EINVAL;
3869 }
3870 I915_WRITE(PORT_DFT2_G4X, tmp);
3871 }
3872
3873 return 0;
3874 }
3875
3876 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3877 enum pipe pipe,
3878 enum intel_pipe_crc_source *source,
3879 uint32_t *val)
3880 {
3881 struct drm_i915_private *dev_priv = to_i915(dev);
3882 bool need_stable_symbols = false;
3883
3884 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3885 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3886 if (ret)
3887 return ret;
3888 }
3889
3890 switch (*source) {
3891 case INTEL_PIPE_CRC_SOURCE_PIPE:
3892 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3893 break;
3894 case INTEL_PIPE_CRC_SOURCE_TV:
3895 if (!SUPPORTS_TV(dev))
3896 return -EINVAL;
3897 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3898 break;
3899 case INTEL_PIPE_CRC_SOURCE_DP_B:
3900 if (!IS_G4X(dev))
3901 return -EINVAL;
3902 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3903 need_stable_symbols = true;
3904 break;
3905 case INTEL_PIPE_CRC_SOURCE_DP_C:
3906 if (!IS_G4X(dev))
3907 return -EINVAL;
3908 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3909 need_stable_symbols = true;
3910 break;
3911 case INTEL_PIPE_CRC_SOURCE_DP_D:
3912 if (!IS_G4X(dev))
3913 return -EINVAL;
3914 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3915 need_stable_symbols = true;
3916 break;
3917 case INTEL_PIPE_CRC_SOURCE_NONE:
3918 *val = 0;
3919 break;
3920 default:
3921 return -EINVAL;
3922 }
3923
3924 /*
3925 * When the pipe CRC tap point is after the transcoders we need
3926 * to tweak symbol-level features to produce a deterministic series of
3927 * symbols for a given frame. We need to reset those features only once
3928 * a frame (instead of every nth symbol):
3929 * - DC-balance: used to ensure a better clock recovery from the data
3930 * link (SDVO)
3931 * - DisplayPort scrambling: used for EMI reduction
3932 */
3933 if (need_stable_symbols) {
3934 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3935
3936 WARN_ON(!IS_G4X(dev));
3937
3938 I915_WRITE(PORT_DFT_I9XX,
3939 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3940
3941 if (pipe == PIPE_A)
3942 tmp |= PIPE_A_SCRAMBLE_RESET;
3943 else
3944 tmp |= PIPE_B_SCRAMBLE_RESET;
3945
3946 I915_WRITE(PORT_DFT2_G4X, tmp);
3947 }
3948
3949 return 0;
3950 }
3951
3952 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3953 enum pipe pipe)
3954 {
3955 struct drm_i915_private *dev_priv = to_i915(dev);
3956 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3957
3958 switch (pipe) {
3959 case PIPE_A:
3960 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3961 break;
3962 case PIPE_B:
3963 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3964 break;
3965 case PIPE_C:
3966 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3967 break;
3968 default:
3969 return;
3970 }
3971 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3972 tmp &= ~DC_BALANCE_RESET_VLV;
3973 I915_WRITE(PORT_DFT2_G4X, tmp);
3974
3975 }
3976
3977 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3978 enum pipe pipe)
3979 {
3980 struct drm_i915_private *dev_priv = to_i915(dev);
3981 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3982
3983 if (pipe == PIPE_A)
3984 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3985 else
3986 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3987 I915_WRITE(PORT_DFT2_G4X, tmp);
3988
3989 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3990 I915_WRITE(PORT_DFT_I9XX,
3991 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3992 }
3993 }
3994
3995 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3996 uint32_t *val)
3997 {
3998 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3999 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4000
4001 switch (*source) {
4002 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4003 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4004 break;
4005 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4006 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4007 break;
4008 case INTEL_PIPE_CRC_SOURCE_PIPE:
4009 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4010 break;
4011 case INTEL_PIPE_CRC_SOURCE_NONE:
4012 *val = 0;
4013 break;
4014 default:
4015 return -EINVAL;
4016 }
4017
4018 return 0;
4019 }
4020
4021 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4022 {
4023 struct drm_i915_private *dev_priv = to_i915(dev);
4024 struct intel_crtc *crtc =
4025 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4026 struct intel_crtc_state *pipe_config;
4027 struct drm_atomic_state *state;
4028 int ret = 0;
4029
4030 drm_modeset_lock_all(dev);
4031 state = drm_atomic_state_alloc(dev);
4032 if (!state) {
4033 ret = -ENOMEM;
4034 goto out;
4035 }
4036
4037 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4038 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4039 if (IS_ERR(pipe_config)) {
4040 ret = PTR_ERR(pipe_config);
4041 goto out;
4042 }
4043
4044 pipe_config->pch_pfit.force_thru = enable;
4045 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4046 pipe_config->pch_pfit.enabled != enable)
4047 pipe_config->base.connectors_changed = true;
4048
4049 ret = drm_atomic_commit(state);
4050 out:
4051 drm_modeset_unlock_all(dev);
4052 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4053 if (ret)
4054 drm_atomic_state_free(state);
4055 }
4056
4057 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4058 enum pipe pipe,
4059 enum intel_pipe_crc_source *source,
4060 uint32_t *val)
4061 {
4062 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4063 *source = INTEL_PIPE_CRC_SOURCE_PF;
4064
4065 switch (*source) {
4066 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4067 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4068 break;
4069 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4070 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4071 break;
4072 case INTEL_PIPE_CRC_SOURCE_PF:
4073 if (IS_HASWELL(dev) && pipe == PIPE_A)
4074 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4075
4076 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4077 break;
4078 case INTEL_PIPE_CRC_SOURCE_NONE:
4079 *val = 0;
4080 break;
4081 default:
4082 return -EINVAL;
4083 }
4084
4085 return 0;
4086 }
4087
4088 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4089 enum intel_pipe_crc_source source)
4090 {
4091 struct drm_i915_private *dev_priv = to_i915(dev);
4092 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4093 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4094 pipe));
4095 enum intel_display_power_domain power_domain;
4096 u32 val = 0; /* shut up gcc */
4097 int ret;
4098
4099 if (pipe_crc->source == source)
4100 return 0;
4101
4102 /* forbid changing the source without going back to 'none' */
4103 if (pipe_crc->source && source)
4104 return -EINVAL;
4105
4106 power_domain = POWER_DOMAIN_PIPE(pipe);
4107 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4108 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4109 return -EIO;
4110 }
4111
4112 if (IS_GEN2(dev))
4113 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4114 else if (INTEL_INFO(dev)->gen < 5)
4115 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4116 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4117 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4118 else if (IS_GEN5(dev) || IS_GEN6(dev))
4119 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4120 else
4121 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4122
4123 if (ret != 0)
4124 goto out;
4125
4126 /* none -> real source transition */
4127 if (source) {
4128 struct intel_pipe_crc_entry *entries;
4129
4130 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4131 pipe_name(pipe), pipe_crc_source_name(source));
4132
4133 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4134 sizeof(pipe_crc->entries[0]),
4135 GFP_KERNEL);
4136 if (!entries) {
4137 ret = -ENOMEM;
4138 goto out;
4139 }
4140
4141 /*
4142 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4143 * enabled and disabled dynamically based on package C states,
4144 * user space can't make reliable use of the CRCs, so let's just
4145 * completely disable it.
4146 */
4147 hsw_disable_ips(crtc);
4148
4149 spin_lock_irq(&pipe_crc->lock);
4150 kfree(pipe_crc->entries);
4151 pipe_crc->entries = entries;
4152 pipe_crc->head = 0;
4153 pipe_crc->tail = 0;
4154 spin_unlock_irq(&pipe_crc->lock);
4155 }
4156
4157 pipe_crc->source = source;
4158
4159 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4160 POSTING_READ(PIPE_CRC_CTL(pipe));
4161
4162 /* real source -> none transition */
4163 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4164 struct intel_pipe_crc_entry *entries;
4165 struct intel_crtc *crtc =
4166 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4167
4168 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4169 pipe_name(pipe));
4170
4171 drm_modeset_lock(&crtc->base.mutex, NULL);
4172 if (crtc->base.state->active)
4173 intel_wait_for_vblank(dev, pipe);
4174 drm_modeset_unlock(&crtc->base.mutex);
4175
4176 spin_lock_irq(&pipe_crc->lock);
4177 entries = pipe_crc->entries;
4178 pipe_crc->entries = NULL;
4179 pipe_crc->head = 0;
4180 pipe_crc->tail = 0;
4181 spin_unlock_irq(&pipe_crc->lock);
4182
4183 kfree(entries);
4184
4185 if (IS_G4X(dev))
4186 g4x_undo_pipe_scramble_reset(dev, pipe);
4187 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4188 vlv_undo_pipe_scramble_reset(dev, pipe);
4189 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4190 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4191
4192 hsw_enable_ips(crtc);
4193 }
4194
4195 ret = 0;
4196
4197 out:
4198 intel_display_power_put(dev_priv, power_domain);
4199
4200 return ret;
4201 }
4202
4203 /*
4204 * Parse pipe CRC command strings:
4205 * command: wsp* object wsp+ name wsp+ source wsp*
4206 * object: 'pipe'
4207 * name: (A | B | C)
4208 * source: (none | plane1 | plane2 | pf)
4209 * wsp: (#0x20 | #0x9 | #0xA)+
4210 *
4211 * eg.:
4212 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4213 * "pipe A none" -> Stop CRC
4214 */
4215 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4216 {
4217 int n_words = 0;
4218
4219 while (*buf) {
4220 char *end;
4221
4222 /* skip leading white space */
4223 buf = skip_spaces(buf);
4224 if (!*buf)
4225 break; /* end of buffer */
4226
4227 /* find end of word */
4228 for (end = buf; *end && !isspace(*end); end++)
4229 ;
4230
4231 if (n_words == max_words) {
4232 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4233 max_words);
4234 return -EINVAL; /* ran out of words[] before bytes */
4235 }
4236
4237 if (*end)
4238 *end++ = '\0';
4239 words[n_words++] = buf;
4240 buf = end;
4241 }
4242
4243 return n_words;
4244 }
4245
4246 enum intel_pipe_crc_object {
4247 PIPE_CRC_OBJECT_PIPE,
4248 };
4249
4250 static const char * const pipe_crc_objects[] = {
4251 "pipe",
4252 };
4253
4254 static int
4255 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4256 {
4257 int i;
4258
4259 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4260 if (!strcmp(buf, pipe_crc_objects[i])) {
4261 *o = i;
4262 return 0;
4263 }
4264
4265 return -EINVAL;
4266 }
4267
4268 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4269 {
4270 const char name = buf[0];
4271
4272 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4273 return -EINVAL;
4274
4275 *pipe = name - 'A';
4276
4277 return 0;
4278 }
4279
4280 static int
4281 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4282 {
4283 int i;
4284
4285 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4286 if (!strcmp(buf, pipe_crc_sources[i])) {
4287 *s = i;
4288 return 0;
4289 }
4290
4291 return -EINVAL;
4292 }
4293
4294 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4295 {
4296 #define N_WORDS 3
4297 int n_words;
4298 char *words[N_WORDS];
4299 enum pipe pipe;
4300 enum intel_pipe_crc_object object;
4301 enum intel_pipe_crc_source source;
4302
4303 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4304 if (n_words != N_WORDS) {
4305 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4306 N_WORDS);
4307 return -EINVAL;
4308 }
4309
4310 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4311 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4312 return -EINVAL;
4313 }
4314
4315 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4316 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4317 return -EINVAL;
4318 }
4319
4320 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4321 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4322 return -EINVAL;
4323 }
4324
4325 return pipe_crc_set_source(dev, pipe, source);
4326 }
4327
4328 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4329 size_t len, loff_t *offp)
4330 {
4331 struct seq_file *m = file->private_data;
4332 struct drm_device *dev = m->private;
4333 char *tmpbuf;
4334 int ret;
4335
4336 if (len == 0)
4337 return 0;
4338
4339 if (len > PAGE_SIZE - 1) {
4340 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4341 PAGE_SIZE);
4342 return -E2BIG;
4343 }
4344
4345 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4346 if (!tmpbuf)
4347 return -ENOMEM;
4348
4349 if (copy_from_user(tmpbuf, ubuf, len)) {
4350 ret = -EFAULT;
4351 goto out;
4352 }
4353 tmpbuf[len] = '\0';
4354
4355 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4356
4357 out:
4358 kfree(tmpbuf);
4359 if (ret < 0)
4360 return ret;
4361
4362 *offp += len;
4363 return len;
4364 }
4365
4366 static const struct file_operations i915_display_crc_ctl_fops = {
4367 .owner = THIS_MODULE,
4368 .open = display_crc_ctl_open,
4369 .read = seq_read,
4370 .llseek = seq_lseek,
4371 .release = single_release,
4372 .write = display_crc_ctl_write
4373 };
4374
4375 static ssize_t i915_displayport_test_active_write(struct file *file,
4376 const char __user *ubuf,
4377 size_t len, loff_t *offp)
4378 {
4379 char *input_buffer;
4380 int status = 0;
4381 struct drm_device *dev;
4382 struct drm_connector *connector;
4383 struct list_head *connector_list;
4384 struct intel_dp *intel_dp;
4385 int val = 0;
4386
4387 dev = ((struct seq_file *)file->private_data)->private;
4388
4389 connector_list = &dev->mode_config.connector_list;
4390
4391 if (len == 0)
4392 return 0;
4393
4394 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4395 if (!input_buffer)
4396 return -ENOMEM;
4397
4398 if (copy_from_user(input_buffer, ubuf, len)) {
4399 status = -EFAULT;
4400 goto out;
4401 }
4402
4403 input_buffer[len] = '\0';
4404 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4405
4406 list_for_each_entry(connector, connector_list, head) {
4407
4408 if (connector->connector_type !=
4409 DRM_MODE_CONNECTOR_DisplayPort)
4410 continue;
4411
4412 if (connector->status == connector_status_connected &&
4413 connector->encoder != NULL) {
4414 intel_dp = enc_to_intel_dp(connector->encoder);
4415 status = kstrtoint(input_buffer, 10, &val);
4416 if (status < 0)
4417 goto out;
4418 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4419 /* To prevent erroneous activation of the compliance
4420 * testing code, only accept an actual value of 1 here
4421 */
4422 if (val == 1)
4423 intel_dp->compliance_test_active = 1;
4424 else
4425 intel_dp->compliance_test_active = 0;
4426 }
4427 }
4428 out:
4429 kfree(input_buffer);
4430 if (status < 0)
4431 return status;
4432
4433 *offp += len;
4434 return len;
4435 }
4436
4437 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4438 {
4439 struct drm_device *dev = m->private;
4440 struct drm_connector *connector;
4441 struct list_head *connector_list = &dev->mode_config.connector_list;
4442 struct intel_dp *intel_dp;
4443
4444 list_for_each_entry(connector, connector_list, head) {
4445
4446 if (connector->connector_type !=
4447 DRM_MODE_CONNECTOR_DisplayPort)
4448 continue;
4449
4450 if (connector->status == connector_status_connected &&
4451 connector->encoder != NULL) {
4452 intel_dp = enc_to_intel_dp(connector->encoder);
4453 if (intel_dp->compliance_test_active)
4454 seq_puts(m, "1");
4455 else
4456 seq_puts(m, "0");
4457 } else
4458 seq_puts(m, "0");
4459 }
4460
4461 return 0;
4462 }
4463
4464 static int i915_displayport_test_active_open(struct inode *inode,
4465 struct file *file)
4466 {
4467 struct drm_device *dev = inode->i_private;
4468
4469 return single_open(file, i915_displayport_test_active_show, dev);
4470 }
4471
4472 static const struct file_operations i915_displayport_test_active_fops = {
4473 .owner = THIS_MODULE,
4474 .open = i915_displayport_test_active_open,
4475 .read = seq_read,
4476 .llseek = seq_lseek,
4477 .release = single_release,
4478 .write = i915_displayport_test_active_write
4479 };
4480
4481 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4482 {
4483 struct drm_device *dev = m->private;
4484 struct drm_connector *connector;
4485 struct list_head *connector_list = &dev->mode_config.connector_list;
4486 struct intel_dp *intel_dp;
4487
4488 list_for_each_entry(connector, connector_list, head) {
4489
4490 if (connector->connector_type !=
4491 DRM_MODE_CONNECTOR_DisplayPort)
4492 continue;
4493
4494 if (connector->status == connector_status_connected &&
4495 connector->encoder != NULL) {
4496 intel_dp = enc_to_intel_dp(connector->encoder);
4497 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4498 } else
4499 seq_puts(m, "0");
4500 }
4501
4502 return 0;
4503 }
4504 static int i915_displayport_test_data_open(struct inode *inode,
4505 struct file *file)
4506 {
4507 struct drm_device *dev = inode->i_private;
4508
4509 return single_open(file, i915_displayport_test_data_show, dev);
4510 }
4511
4512 static const struct file_operations i915_displayport_test_data_fops = {
4513 .owner = THIS_MODULE,
4514 .open = i915_displayport_test_data_open,
4515 .read = seq_read,
4516 .llseek = seq_lseek,
4517 .release = single_release
4518 };
4519
4520 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4521 {
4522 struct drm_device *dev = m->private;
4523 struct drm_connector *connector;
4524 struct list_head *connector_list = &dev->mode_config.connector_list;
4525 struct intel_dp *intel_dp;
4526
4527 list_for_each_entry(connector, connector_list, head) {
4528
4529 if (connector->connector_type !=
4530 DRM_MODE_CONNECTOR_DisplayPort)
4531 continue;
4532
4533 if (connector->status == connector_status_connected &&
4534 connector->encoder != NULL) {
4535 intel_dp = enc_to_intel_dp(connector->encoder);
4536 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4537 } else
4538 seq_puts(m, "0");
4539 }
4540
4541 return 0;
4542 }
4543
4544 static int i915_displayport_test_type_open(struct inode *inode,
4545 struct file *file)
4546 {
4547 struct drm_device *dev = inode->i_private;
4548
4549 return single_open(file, i915_displayport_test_type_show, dev);
4550 }
4551
4552 static const struct file_operations i915_displayport_test_type_fops = {
4553 .owner = THIS_MODULE,
4554 .open = i915_displayport_test_type_open,
4555 .read = seq_read,
4556 .llseek = seq_lseek,
4557 .release = single_release
4558 };
4559
4560 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4561 {
4562 struct drm_device *dev = m->private;
4563 int level;
4564 int num_levels;
4565
4566 if (IS_CHERRYVIEW(dev))
4567 num_levels = 3;
4568 else if (IS_VALLEYVIEW(dev))
4569 num_levels = 1;
4570 else
4571 num_levels = ilk_wm_max_level(dev) + 1;
4572
4573 drm_modeset_lock_all(dev);
4574
4575 for (level = 0; level < num_levels; level++) {
4576 unsigned int latency = wm[level];
4577
4578 /*
4579 * - WM1+ latency values in 0.5us units
4580 * - latencies are in us on gen9/vlv/chv
4581 */
4582 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4583 IS_CHERRYVIEW(dev))
4584 latency *= 10;
4585 else if (level > 0)
4586 latency *= 5;
4587
4588 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4589 level, wm[level], latency / 10, latency % 10);
4590 }
4591
4592 drm_modeset_unlock_all(dev);
4593 }
4594
4595 static int pri_wm_latency_show(struct seq_file *m, void *data)
4596 {
4597 struct drm_device *dev = m->private;
4598 struct drm_i915_private *dev_priv = to_i915(dev);
4599 const uint16_t *latencies;
4600
4601 if (INTEL_INFO(dev)->gen >= 9)
4602 latencies = dev_priv->wm.skl_latency;
4603 else
4604 latencies = to_i915(dev)->wm.pri_latency;
4605
4606 wm_latency_show(m, latencies);
4607
4608 return 0;
4609 }
4610
4611 static int spr_wm_latency_show(struct seq_file *m, void *data)
4612 {
4613 struct drm_device *dev = m->private;
4614 struct drm_i915_private *dev_priv = to_i915(dev);
4615 const uint16_t *latencies;
4616
4617 if (INTEL_INFO(dev)->gen >= 9)
4618 latencies = dev_priv->wm.skl_latency;
4619 else
4620 latencies = to_i915(dev)->wm.spr_latency;
4621
4622 wm_latency_show(m, latencies);
4623
4624 return 0;
4625 }
4626
4627 static int cur_wm_latency_show(struct seq_file *m, void *data)
4628 {
4629 struct drm_device *dev = m->private;
4630 struct drm_i915_private *dev_priv = to_i915(dev);
4631 const uint16_t *latencies;
4632
4633 if (INTEL_INFO(dev)->gen >= 9)
4634 latencies = dev_priv->wm.skl_latency;
4635 else
4636 latencies = to_i915(dev)->wm.cur_latency;
4637
4638 wm_latency_show(m, latencies);
4639
4640 return 0;
4641 }
4642
4643 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4644 {
4645 struct drm_device *dev = inode->i_private;
4646
4647 if (INTEL_INFO(dev)->gen < 5)
4648 return -ENODEV;
4649
4650 return single_open(file, pri_wm_latency_show, dev);
4651 }
4652
4653 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4654 {
4655 struct drm_device *dev = inode->i_private;
4656
4657 if (HAS_GMCH_DISPLAY(dev))
4658 return -ENODEV;
4659
4660 return single_open(file, spr_wm_latency_show, dev);
4661 }
4662
4663 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4664 {
4665 struct drm_device *dev = inode->i_private;
4666
4667 if (HAS_GMCH_DISPLAY(dev))
4668 return -ENODEV;
4669
4670 return single_open(file, cur_wm_latency_show, dev);
4671 }
4672
4673 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4674 size_t len, loff_t *offp, uint16_t wm[8])
4675 {
4676 struct seq_file *m = file->private_data;
4677 struct drm_device *dev = m->private;
4678 uint16_t new[8] = { 0 };
4679 int num_levels;
4680 int level;
4681 int ret;
4682 char tmp[32];
4683
4684 if (IS_CHERRYVIEW(dev))
4685 num_levels = 3;
4686 else if (IS_VALLEYVIEW(dev))
4687 num_levels = 1;
4688 else
4689 num_levels = ilk_wm_max_level(dev) + 1;
4690
4691 if (len >= sizeof(tmp))
4692 return -EINVAL;
4693
4694 if (copy_from_user(tmp, ubuf, len))
4695 return -EFAULT;
4696
4697 tmp[len] = '\0';
4698
4699 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4700 &new[0], &new[1], &new[2], &new[3],
4701 &new[4], &new[5], &new[6], &new[7]);
4702 if (ret != num_levels)
4703 return -EINVAL;
4704
4705 drm_modeset_lock_all(dev);
4706
4707 for (level = 0; level < num_levels; level++)
4708 wm[level] = new[level];
4709
4710 drm_modeset_unlock_all(dev);
4711
4712 return len;
4713 }
4714
4715
4716 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4717 size_t len, loff_t *offp)
4718 {
4719 struct seq_file *m = file->private_data;
4720 struct drm_device *dev = m->private;
4721 struct drm_i915_private *dev_priv = to_i915(dev);
4722 uint16_t *latencies;
4723
4724 if (INTEL_INFO(dev)->gen >= 9)
4725 latencies = dev_priv->wm.skl_latency;
4726 else
4727 latencies = to_i915(dev)->wm.pri_latency;
4728
4729 return wm_latency_write(file, ubuf, len, offp, latencies);
4730 }
4731
4732 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4733 size_t len, loff_t *offp)
4734 {
4735 struct seq_file *m = file->private_data;
4736 struct drm_device *dev = m->private;
4737 struct drm_i915_private *dev_priv = to_i915(dev);
4738 uint16_t *latencies;
4739
4740 if (INTEL_INFO(dev)->gen >= 9)
4741 latencies = dev_priv->wm.skl_latency;
4742 else
4743 latencies = to_i915(dev)->wm.spr_latency;
4744
4745 return wm_latency_write(file, ubuf, len, offp, latencies);
4746 }
4747
4748 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4749 size_t len, loff_t *offp)
4750 {
4751 struct seq_file *m = file->private_data;
4752 struct drm_device *dev = m->private;
4753 struct drm_i915_private *dev_priv = to_i915(dev);
4754 uint16_t *latencies;
4755
4756 if (INTEL_INFO(dev)->gen >= 9)
4757 latencies = dev_priv->wm.skl_latency;
4758 else
4759 latencies = to_i915(dev)->wm.cur_latency;
4760
4761 return wm_latency_write(file, ubuf, len, offp, latencies);
4762 }
4763
4764 static const struct file_operations i915_pri_wm_latency_fops = {
4765 .owner = THIS_MODULE,
4766 .open = pri_wm_latency_open,
4767 .read = seq_read,
4768 .llseek = seq_lseek,
4769 .release = single_release,
4770 .write = pri_wm_latency_write
4771 };
4772
4773 static const struct file_operations i915_spr_wm_latency_fops = {
4774 .owner = THIS_MODULE,
4775 .open = spr_wm_latency_open,
4776 .read = seq_read,
4777 .llseek = seq_lseek,
4778 .release = single_release,
4779 .write = spr_wm_latency_write
4780 };
4781
4782 static const struct file_operations i915_cur_wm_latency_fops = {
4783 .owner = THIS_MODULE,
4784 .open = cur_wm_latency_open,
4785 .read = seq_read,
4786 .llseek = seq_lseek,
4787 .release = single_release,
4788 .write = cur_wm_latency_write
4789 };
4790
4791 static int
4792 i915_wedged_get(void *data, u64 *val)
4793 {
4794 struct drm_device *dev = data;
4795 struct drm_i915_private *dev_priv = to_i915(dev);
4796
4797 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4798
4799 return 0;
4800 }
4801
4802 static int
4803 i915_wedged_set(void *data, u64 val)
4804 {
4805 struct drm_device *dev = data;
4806 struct drm_i915_private *dev_priv = to_i915(dev);
4807
4808 /*
4809 * There is no safeguard against this debugfs entry colliding
4810 * with the hangcheck calling same i915_handle_error() in
4811 * parallel, causing an explosion. For now we assume that the
4812 * test harness is responsible enough not to inject gpu hangs
4813 * while it is writing to 'i915_wedged'
4814 */
4815
4816 if (i915_reset_in_progress(&dev_priv->gpu_error))
4817 return -EAGAIN;
4818
4819 intel_runtime_pm_get(dev_priv);
4820
4821 i915_handle_error(dev_priv, val,
4822 "Manually setting wedged to %llu", val);
4823
4824 intel_runtime_pm_put(dev_priv);
4825
4826 return 0;
4827 }
4828
4829 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4830 i915_wedged_get, i915_wedged_set,
4831 "%llu\n");
4832
4833 static int
4834 i915_ring_missed_irq_get(void *data, u64 *val)
4835 {
4836 struct drm_device *dev = data;
4837 struct drm_i915_private *dev_priv = to_i915(dev);
4838
4839 *val = dev_priv->gpu_error.missed_irq_rings;
4840 return 0;
4841 }
4842
4843 static int
4844 i915_ring_missed_irq_set(void *data, u64 val)
4845 {
4846 struct drm_device *dev = data;
4847 struct drm_i915_private *dev_priv = to_i915(dev);
4848 int ret;
4849
4850 /* Lock against concurrent debugfs callers */
4851 ret = mutex_lock_interruptible(&dev->struct_mutex);
4852 if (ret)
4853 return ret;
4854 dev_priv->gpu_error.missed_irq_rings = val;
4855 mutex_unlock(&dev->struct_mutex);
4856
4857 return 0;
4858 }
4859
4860 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4861 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4862 "0x%08llx\n");
4863
4864 static int
4865 i915_ring_test_irq_get(void *data, u64 *val)
4866 {
4867 struct drm_device *dev = data;
4868 struct drm_i915_private *dev_priv = to_i915(dev);
4869
4870 *val = dev_priv->gpu_error.test_irq_rings;
4871
4872 return 0;
4873 }
4874
4875 static int
4876 i915_ring_test_irq_set(void *data, u64 val)
4877 {
4878 struct drm_device *dev = data;
4879 struct drm_i915_private *dev_priv = to_i915(dev);
4880
4881 val &= INTEL_INFO(dev_priv)->ring_mask;
4882 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4883 dev_priv->gpu_error.test_irq_rings = val;
4884
4885 return 0;
4886 }
4887
4888 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4889 i915_ring_test_irq_get, i915_ring_test_irq_set,
4890 "0x%08llx\n");
4891
4892 #define DROP_UNBOUND 0x1
4893 #define DROP_BOUND 0x2
4894 #define DROP_RETIRE 0x4
4895 #define DROP_ACTIVE 0x8
4896 #define DROP_ALL (DROP_UNBOUND | \
4897 DROP_BOUND | \
4898 DROP_RETIRE | \
4899 DROP_ACTIVE)
4900 static int
4901 i915_drop_caches_get(void *data, u64 *val)
4902 {
4903 *val = DROP_ALL;
4904
4905 return 0;
4906 }
4907
4908 static int
4909 i915_drop_caches_set(void *data, u64 val)
4910 {
4911 struct drm_device *dev = data;
4912 struct drm_i915_private *dev_priv = to_i915(dev);
4913 int ret;
4914
4915 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4916
4917 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4918 * on ioctls on -EAGAIN. */
4919 ret = mutex_lock_interruptible(&dev->struct_mutex);
4920 if (ret)
4921 return ret;
4922
4923 if (val & DROP_ACTIVE) {
4924 ret = i915_gem_wait_for_idle(dev_priv);
4925 if (ret)
4926 goto unlock;
4927 }
4928
4929 if (val & (DROP_RETIRE | DROP_ACTIVE))
4930 i915_gem_retire_requests(dev_priv);
4931
4932 if (val & DROP_BOUND)
4933 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4934
4935 if (val & DROP_UNBOUND)
4936 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4937
4938 unlock:
4939 mutex_unlock(&dev->struct_mutex);
4940
4941 return ret;
4942 }
4943
4944 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4945 i915_drop_caches_get, i915_drop_caches_set,
4946 "0x%08llx\n");
4947
4948 static int
4949 i915_max_freq_get(void *data, u64 *val)
4950 {
4951 struct drm_device *dev = data;
4952 struct drm_i915_private *dev_priv = to_i915(dev);
4953 int ret;
4954
4955 if (INTEL_INFO(dev)->gen < 6)
4956 return -ENODEV;
4957
4958 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4959
4960 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4961 if (ret)
4962 return ret;
4963
4964 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4965 mutex_unlock(&dev_priv->rps.hw_lock);
4966
4967 return 0;
4968 }
4969
4970 static int
4971 i915_max_freq_set(void *data, u64 val)
4972 {
4973 struct drm_device *dev = data;
4974 struct drm_i915_private *dev_priv = to_i915(dev);
4975 u32 hw_max, hw_min;
4976 int ret;
4977
4978 if (INTEL_INFO(dev)->gen < 6)
4979 return -ENODEV;
4980
4981 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4982
4983 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4984
4985 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4986 if (ret)
4987 return ret;
4988
4989 /*
4990 * Turbo will still be enabled, but won't go above the set value.
4991 */
4992 val = intel_freq_opcode(dev_priv, val);
4993
4994 hw_max = dev_priv->rps.max_freq;
4995 hw_min = dev_priv->rps.min_freq;
4996
4997 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4998 mutex_unlock(&dev_priv->rps.hw_lock);
4999 return -EINVAL;
5000 }
5001
5002 dev_priv->rps.max_freq_softlimit = val;
5003
5004 intel_set_rps(dev_priv, val);
5005
5006 mutex_unlock(&dev_priv->rps.hw_lock);
5007
5008 return 0;
5009 }
5010
5011 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5012 i915_max_freq_get, i915_max_freq_set,
5013 "%llu\n");
5014
5015 static int
5016 i915_min_freq_get(void *data, u64 *val)
5017 {
5018 struct drm_device *dev = data;
5019 struct drm_i915_private *dev_priv = to_i915(dev);
5020 int ret;
5021
5022 if (INTEL_INFO(dev)->gen < 6)
5023 return -ENODEV;
5024
5025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5026
5027 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5028 if (ret)
5029 return ret;
5030
5031 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5032 mutex_unlock(&dev_priv->rps.hw_lock);
5033
5034 return 0;
5035 }
5036
5037 static int
5038 i915_min_freq_set(void *data, u64 val)
5039 {
5040 struct drm_device *dev = data;
5041 struct drm_i915_private *dev_priv = to_i915(dev);
5042 u32 hw_max, hw_min;
5043 int ret;
5044
5045 if (INTEL_INFO(dev)->gen < 6)
5046 return -ENODEV;
5047
5048 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5049
5050 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5051
5052 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5053 if (ret)
5054 return ret;
5055
5056 /*
5057 * Turbo will still be enabled, but won't go below the set value.
5058 */
5059 val = intel_freq_opcode(dev_priv, val);
5060
5061 hw_max = dev_priv->rps.max_freq;
5062 hw_min = dev_priv->rps.min_freq;
5063
5064 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5065 mutex_unlock(&dev_priv->rps.hw_lock);
5066 return -EINVAL;
5067 }
5068
5069 dev_priv->rps.min_freq_softlimit = val;
5070
5071 intel_set_rps(dev_priv, val);
5072
5073 mutex_unlock(&dev_priv->rps.hw_lock);
5074
5075 return 0;
5076 }
5077
5078 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5079 i915_min_freq_get, i915_min_freq_set,
5080 "%llu\n");
5081
5082 static int
5083 i915_cache_sharing_get(void *data, u64 *val)
5084 {
5085 struct drm_device *dev = data;
5086 struct drm_i915_private *dev_priv = to_i915(dev);
5087 u32 snpcr;
5088 int ret;
5089
5090 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5091 return -ENODEV;
5092
5093 ret = mutex_lock_interruptible(&dev->struct_mutex);
5094 if (ret)
5095 return ret;
5096 intel_runtime_pm_get(dev_priv);
5097
5098 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5099
5100 intel_runtime_pm_put(dev_priv);
5101 mutex_unlock(&dev_priv->drm.struct_mutex);
5102
5103 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5104
5105 return 0;
5106 }
5107
5108 static int
5109 i915_cache_sharing_set(void *data, u64 val)
5110 {
5111 struct drm_device *dev = data;
5112 struct drm_i915_private *dev_priv = to_i915(dev);
5113 u32 snpcr;
5114
5115 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5116 return -ENODEV;
5117
5118 if (val > 3)
5119 return -EINVAL;
5120
5121 intel_runtime_pm_get(dev_priv);
5122 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5123
5124 /* Update the cache sharing policy here as well */
5125 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5126 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5127 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5128 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5129
5130 intel_runtime_pm_put(dev_priv);
5131 return 0;
5132 }
5133
5134 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5135 i915_cache_sharing_get, i915_cache_sharing_set,
5136 "%llu\n");
5137
5138 struct sseu_dev_status {
5139 unsigned int slice_total;
5140 unsigned int subslice_total;
5141 unsigned int subslice_per_slice;
5142 unsigned int eu_total;
5143 unsigned int eu_per_subslice;
5144 };
5145
5146 static void cherryview_sseu_device_status(struct drm_device *dev,
5147 struct sseu_dev_status *stat)
5148 {
5149 struct drm_i915_private *dev_priv = to_i915(dev);
5150 int ss_max = 2;
5151 int ss;
5152 u32 sig1[ss_max], sig2[ss_max];
5153
5154 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5155 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5156 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5157 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5158
5159 for (ss = 0; ss < ss_max; ss++) {
5160 unsigned int eu_cnt;
5161
5162 if (sig1[ss] & CHV_SS_PG_ENABLE)
5163 /* skip disabled subslice */
5164 continue;
5165
5166 stat->slice_total = 1;
5167 stat->subslice_per_slice++;
5168 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5169 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5170 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5171 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5172 stat->eu_total += eu_cnt;
5173 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5174 }
5175 stat->subslice_total = stat->subslice_per_slice;
5176 }
5177
5178 static void gen9_sseu_device_status(struct drm_device *dev,
5179 struct sseu_dev_status *stat)
5180 {
5181 struct drm_i915_private *dev_priv = to_i915(dev);
5182 int s_max = 3, ss_max = 4;
5183 int s, ss;
5184 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5185
5186 /* BXT has a single slice and at most 3 subslices. */
5187 if (IS_BROXTON(dev)) {
5188 s_max = 1;
5189 ss_max = 3;
5190 }
5191
5192 for (s = 0; s < s_max; s++) {
5193 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5194 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5195 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5196 }
5197
5198 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5199 GEN9_PGCTL_SSA_EU19_ACK |
5200 GEN9_PGCTL_SSA_EU210_ACK |
5201 GEN9_PGCTL_SSA_EU311_ACK;
5202 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5203 GEN9_PGCTL_SSB_EU19_ACK |
5204 GEN9_PGCTL_SSB_EU210_ACK |
5205 GEN9_PGCTL_SSB_EU311_ACK;
5206
5207 for (s = 0; s < s_max; s++) {
5208 unsigned int ss_cnt = 0;
5209
5210 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5211 /* skip disabled slice */
5212 continue;
5213
5214 stat->slice_total++;
5215
5216 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5217 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5218
5219 for (ss = 0; ss < ss_max; ss++) {
5220 unsigned int eu_cnt;
5221
5222 if (IS_BROXTON(dev) &&
5223 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5224 /* skip disabled subslice */
5225 continue;
5226
5227 if (IS_BROXTON(dev))
5228 ss_cnt++;
5229
5230 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5231 eu_mask[ss%2]);
5232 stat->eu_total += eu_cnt;
5233 stat->eu_per_subslice = max(stat->eu_per_subslice,
5234 eu_cnt);
5235 }
5236
5237 stat->subslice_total += ss_cnt;
5238 stat->subslice_per_slice = max(stat->subslice_per_slice,
5239 ss_cnt);
5240 }
5241 }
5242
5243 static void broadwell_sseu_device_status(struct drm_device *dev,
5244 struct sseu_dev_status *stat)
5245 {
5246 struct drm_i915_private *dev_priv = to_i915(dev);
5247 int s;
5248 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5249
5250 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5251
5252 if (stat->slice_total) {
5253 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5254 stat->subslice_total = stat->slice_total *
5255 stat->subslice_per_slice;
5256 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5257 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5258
5259 /* subtract fused off EU(s) from enabled slice(s) */
5260 for (s = 0; s < stat->slice_total; s++) {
5261 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5262
5263 stat->eu_total -= hweight8(subslice_7eu);
5264 }
5265 }
5266 }
5267
5268 static int i915_sseu_status(struct seq_file *m, void *unused)
5269 {
5270 struct drm_info_node *node = (struct drm_info_node *) m->private;
5271 struct drm_device *dev = node->minor->dev;
5272 struct sseu_dev_status stat;
5273
5274 if (INTEL_INFO(dev)->gen < 8)
5275 return -ENODEV;
5276
5277 seq_puts(m, "SSEU Device Info\n");
5278 seq_printf(m, " Available Slice Total: %u\n",
5279 INTEL_INFO(dev)->slice_total);
5280 seq_printf(m, " Available Subslice Total: %u\n",
5281 INTEL_INFO(dev)->subslice_total);
5282 seq_printf(m, " Available Subslice Per Slice: %u\n",
5283 INTEL_INFO(dev)->subslice_per_slice);
5284 seq_printf(m, " Available EU Total: %u\n",
5285 INTEL_INFO(dev)->eu_total);
5286 seq_printf(m, " Available EU Per Subslice: %u\n",
5287 INTEL_INFO(dev)->eu_per_subslice);
5288 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5289 if (HAS_POOLED_EU(dev))
5290 seq_printf(m, " Min EU in pool: %u\n",
5291 INTEL_INFO(dev)->min_eu_in_pool);
5292 seq_printf(m, " Has Slice Power Gating: %s\n",
5293 yesno(INTEL_INFO(dev)->has_slice_pg));
5294 seq_printf(m, " Has Subslice Power Gating: %s\n",
5295 yesno(INTEL_INFO(dev)->has_subslice_pg));
5296 seq_printf(m, " Has EU Power Gating: %s\n",
5297 yesno(INTEL_INFO(dev)->has_eu_pg));
5298
5299 seq_puts(m, "SSEU Device Status\n");
5300 memset(&stat, 0, sizeof(stat));
5301 if (IS_CHERRYVIEW(dev)) {
5302 cherryview_sseu_device_status(dev, &stat);
5303 } else if (IS_BROADWELL(dev)) {
5304 broadwell_sseu_device_status(dev, &stat);
5305 } else if (INTEL_INFO(dev)->gen >= 9) {
5306 gen9_sseu_device_status(dev, &stat);
5307 }
5308 seq_printf(m, " Enabled Slice Total: %u\n",
5309 stat.slice_total);
5310 seq_printf(m, " Enabled Subslice Total: %u\n",
5311 stat.subslice_total);
5312 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5313 stat.subslice_per_slice);
5314 seq_printf(m, " Enabled EU Total: %u\n",
5315 stat.eu_total);
5316 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5317 stat.eu_per_subslice);
5318
5319 return 0;
5320 }
5321
5322 static int i915_forcewake_open(struct inode *inode, struct file *file)
5323 {
5324 struct drm_device *dev = inode->i_private;
5325 struct drm_i915_private *dev_priv = to_i915(dev);
5326
5327 if (INTEL_INFO(dev)->gen < 6)
5328 return 0;
5329
5330 intel_runtime_pm_get(dev_priv);
5331 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5332
5333 return 0;
5334 }
5335
5336 static int i915_forcewake_release(struct inode *inode, struct file *file)
5337 {
5338 struct drm_device *dev = inode->i_private;
5339 struct drm_i915_private *dev_priv = to_i915(dev);
5340
5341 if (INTEL_INFO(dev)->gen < 6)
5342 return 0;
5343
5344 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5345 intel_runtime_pm_put(dev_priv);
5346
5347 return 0;
5348 }
5349
5350 static const struct file_operations i915_forcewake_fops = {
5351 .owner = THIS_MODULE,
5352 .open = i915_forcewake_open,
5353 .release = i915_forcewake_release,
5354 };
5355
5356 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5357 {
5358 struct drm_device *dev = minor->dev;
5359 struct dentry *ent;
5360
5361 ent = debugfs_create_file("i915_forcewake_user",
5362 S_IRUSR,
5363 root, dev,
5364 &i915_forcewake_fops);
5365 if (!ent)
5366 return -ENOMEM;
5367
5368 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5369 }
5370
5371 static int i915_debugfs_create(struct dentry *root,
5372 struct drm_minor *minor,
5373 const char *name,
5374 const struct file_operations *fops)
5375 {
5376 struct drm_device *dev = minor->dev;
5377 struct dentry *ent;
5378
5379 ent = debugfs_create_file(name,
5380 S_IRUGO | S_IWUSR,
5381 root, dev,
5382 fops);
5383 if (!ent)
5384 return -ENOMEM;
5385
5386 return drm_add_fake_info_node(minor, ent, fops);
5387 }
5388
5389 static const struct drm_info_list i915_debugfs_list[] = {
5390 {"i915_capabilities", i915_capabilities, 0},
5391 {"i915_gem_objects", i915_gem_object_info, 0},
5392 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5393 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5394 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5395 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5396 {"i915_gem_stolen", i915_gem_stolen_list_info },
5397 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5398 {"i915_gem_request", i915_gem_request_info, 0},
5399 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5400 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5401 {"i915_gem_interrupt", i915_interrupt_info, 0},
5402 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5403 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5404 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5405 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5406 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5407 {"i915_guc_info", i915_guc_info, 0},
5408 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5409 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5410 {"i915_frequency_info", i915_frequency_info, 0},
5411 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5412 {"i915_drpc_info", i915_drpc_info, 0},
5413 {"i915_emon_status", i915_emon_status, 0},
5414 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5415 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5416 {"i915_fbc_status", i915_fbc_status, 0},
5417 {"i915_ips_status", i915_ips_status, 0},
5418 {"i915_sr_status", i915_sr_status, 0},
5419 {"i915_opregion", i915_opregion, 0},
5420 {"i915_vbt", i915_vbt, 0},
5421 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5422 {"i915_context_status", i915_context_status, 0},
5423 {"i915_dump_lrc", i915_dump_lrc, 0},
5424 {"i915_execlists", i915_execlists, 0},
5425 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5426 {"i915_swizzle_info", i915_swizzle_info, 0},
5427 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5428 {"i915_llc", i915_llc, 0},
5429 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5430 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5431 {"i915_energy_uJ", i915_energy_uJ, 0},
5432 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5433 {"i915_power_domain_info", i915_power_domain_info, 0},
5434 {"i915_dmc_info", i915_dmc_info, 0},
5435 {"i915_display_info", i915_display_info, 0},
5436 {"i915_semaphore_status", i915_semaphore_status, 0},
5437 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5438 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5439 {"i915_wa_registers", i915_wa_registers, 0},
5440 {"i915_ddb_info", i915_ddb_info, 0},
5441 {"i915_sseu_status", i915_sseu_status, 0},
5442 {"i915_drrs_status", i915_drrs_status, 0},
5443 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5444 };
5445 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5446
5447 static const struct i915_debugfs_files {
5448 const char *name;
5449 const struct file_operations *fops;
5450 } i915_debugfs_files[] = {
5451 {"i915_wedged", &i915_wedged_fops},
5452 {"i915_max_freq", &i915_max_freq_fops},
5453 {"i915_min_freq", &i915_min_freq_fops},
5454 {"i915_cache_sharing", &i915_cache_sharing_fops},
5455 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5456 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5457 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5458 {"i915_error_state", &i915_error_state_fops},
5459 {"i915_next_seqno", &i915_next_seqno_fops},
5460 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5461 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5462 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5463 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5464 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5465 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5466 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5467 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5468 };
5469
5470 void intel_display_crc_init(struct drm_device *dev)
5471 {
5472 struct drm_i915_private *dev_priv = to_i915(dev);
5473 enum pipe pipe;
5474
5475 for_each_pipe(dev_priv, pipe) {
5476 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5477
5478 pipe_crc->opened = false;
5479 spin_lock_init(&pipe_crc->lock);
5480 init_waitqueue_head(&pipe_crc->wq);
5481 }
5482 }
5483
5484 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5485 {
5486 struct drm_minor *minor = dev_priv->drm.primary;
5487 int ret, i;
5488
5489 ret = i915_forcewake_create(minor->debugfs_root, minor);
5490 if (ret)
5491 return ret;
5492
5493 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5494 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5495 if (ret)
5496 return ret;
5497 }
5498
5499 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5500 ret = i915_debugfs_create(minor->debugfs_root, minor,
5501 i915_debugfs_files[i].name,
5502 i915_debugfs_files[i].fops);
5503 if (ret)
5504 return ret;
5505 }
5506
5507 return drm_debugfs_create_files(i915_debugfs_list,
5508 I915_DEBUGFS_ENTRIES,
5509 minor->debugfs_root, minor);
5510 }
5511
5512 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5513 {
5514 struct drm_minor *minor = dev_priv->drm.primary;
5515 int i;
5516
5517 drm_debugfs_remove_files(i915_debugfs_list,
5518 I915_DEBUGFS_ENTRIES, minor);
5519
5520 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5521 1, minor);
5522
5523 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5524 struct drm_info_list *info_list =
5525 (struct drm_info_list *)&i915_pipe_crc_data[i];
5526
5527 drm_debugfs_remove_files(info_list, 1, minor);
5528 }
5529
5530 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5531 struct drm_info_list *info_list =
5532 (struct drm_info_list *) i915_debugfs_files[i].fops;
5533
5534 drm_debugfs_remove_files(info_list, 1, minor);
5535 }
5536 }
5537
5538 struct dpcd_block {
5539 /* DPCD dump start address. */
5540 unsigned int offset;
5541 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5542 unsigned int end;
5543 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5544 size_t size;
5545 /* Only valid for eDP. */
5546 bool edp;
5547 };
5548
5549 static const struct dpcd_block i915_dpcd_debug[] = {
5550 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5551 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5552 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5553 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5554 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5555 { .offset = DP_SET_POWER },
5556 { .offset = DP_EDP_DPCD_REV },
5557 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5558 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5559 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5560 };
5561
5562 static int i915_dpcd_show(struct seq_file *m, void *data)
5563 {
5564 struct drm_connector *connector = m->private;
5565 struct intel_dp *intel_dp =
5566 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5567 uint8_t buf[16];
5568 ssize_t err;
5569 int i;
5570
5571 if (connector->status != connector_status_connected)
5572 return -ENODEV;
5573
5574 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5575 const struct dpcd_block *b = &i915_dpcd_debug[i];
5576 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5577
5578 if (b->edp &&
5579 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5580 continue;
5581
5582 /* low tech for now */
5583 if (WARN_ON(size > sizeof(buf)))
5584 continue;
5585
5586 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5587 if (err <= 0) {
5588 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5589 size, b->offset, err);
5590 continue;
5591 }
5592
5593 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5594 }
5595
5596 return 0;
5597 }
5598
5599 static int i915_dpcd_open(struct inode *inode, struct file *file)
5600 {
5601 return single_open(file, i915_dpcd_show, inode->i_private);
5602 }
5603
5604 static const struct file_operations i915_dpcd_fops = {
5605 .owner = THIS_MODULE,
5606 .open = i915_dpcd_open,
5607 .read = seq_read,
5608 .llseek = seq_lseek,
5609 .release = single_release,
5610 };
5611
5612 /**
5613 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5614 * @connector: pointer to a registered drm_connector
5615 *
5616 * Cleanup will be done by drm_connector_unregister() through a call to
5617 * drm_debugfs_connector_remove().
5618 *
5619 * Returns 0 on success, negative error codes on error.
5620 */
5621 int i915_debugfs_connector_add(struct drm_connector *connector)
5622 {
5623 struct dentry *root = connector->debugfs_entry;
5624
5625 /* The connector must have been registered beforehands. */
5626 if (!root)
5627 return -ENODEV;
5628
5629 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5630 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5631 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5632 &i915_dpcd_fops);
5633
5634 return 0;
5635 }
Linux kernel - Deliverables
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