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Merge tag 'drm-intel-fixes-2016-03-11' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
1 /*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
35 #include <linux/uaccess.h>
36
37 #define __EXEC_OBJECT_HAS_PIN (1<<31)
38 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
41
42 #define BATCH_OFFSET_BIAS (256*1024)
43
44 struct eb_vmas {
45 struct list_head vmas;
46 int and;
47 union {
48 struct i915_vma *lut[0];
49 struct hlist_head buckets[0];
50 };
51 };
52
53 static struct eb_vmas *
54 eb_create(struct drm_i915_gem_execbuffer2 *args)
55 {
56 struct eb_vmas *eb = NULL;
57
58 if (args->flags & I915_EXEC_HANDLE_LUT) {
59 unsigned size = args->buffer_count;
60 size *= sizeof(struct i915_vma *);
61 size += sizeof(struct eb_vmas);
62 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
63 }
64
65 if (eb == NULL) {
66 unsigned size = args->buffer_count;
67 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
69 while (count > 2*size)
70 count >>= 1;
71 eb = kzalloc(count*sizeof(struct hlist_head) +
72 sizeof(struct eb_vmas),
73 GFP_TEMPORARY);
74 if (eb == NULL)
75 return eb;
76
77 eb->and = count - 1;
78 } else
79 eb->and = -args->buffer_count;
80
81 INIT_LIST_HEAD(&eb->vmas);
82 return eb;
83 }
84
85 static void
86 eb_reset(struct eb_vmas *eb)
87 {
88 if (eb->and >= 0)
89 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
90 }
91
92 static int
93 eb_lookup_vmas(struct eb_vmas *eb,
94 struct drm_i915_gem_exec_object2 *exec,
95 const struct drm_i915_gem_execbuffer2 *args,
96 struct i915_address_space *vm,
97 struct drm_file *file)
98 {
99 struct drm_i915_gem_object *obj;
100 struct list_head objects;
101 int i, ret;
102
103 INIT_LIST_HEAD(&objects);
104 spin_lock(&file->table_lock);
105 /* Grab a reference to the object and release the lock so we can lookup
106 * or create the VMA without using GFP_ATOMIC */
107 for (i = 0; i < args->buffer_count; i++) {
108 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
109 if (obj == NULL) {
110 spin_unlock(&file->table_lock);
111 DRM_DEBUG("Invalid object handle %d at index %d\n",
112 exec[i].handle, i);
113 ret = -ENOENT;
114 goto err;
115 }
116
117 if (!list_empty(&obj->obj_exec_link)) {
118 spin_unlock(&file->table_lock);
119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
120 obj, exec[i].handle, i);
121 ret = -EINVAL;
122 goto err;
123 }
124
125 drm_gem_object_reference(&obj->base);
126 list_add_tail(&obj->obj_exec_link, &objects);
127 }
128 spin_unlock(&file->table_lock);
129
130 i = 0;
131 while (!list_empty(&objects)) {
132 struct i915_vma *vma;
133
134 obj = list_first_entry(&objects,
135 struct drm_i915_gem_object,
136 obj_exec_link);
137
138 /*
139 * NOTE: We can leak any vmas created here when something fails
140 * later on. But that's no issue since vma_unbind can deal with
141 * vmas which are not actually bound. And since only
142 * lookup_or_create exists as an interface to get at the vma
143 * from the (obj, vm) we don't run the risk of creating
144 * duplicated vmas for the same vm.
145 */
146 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
147 if (IS_ERR(vma)) {
148 DRM_DEBUG("Failed to lookup VMA\n");
149 ret = PTR_ERR(vma);
150 goto err;
151 }
152
153 /* Transfer ownership from the objects list to the vmas list. */
154 list_add_tail(&vma->exec_list, &eb->vmas);
155 list_del_init(&obj->obj_exec_link);
156
157 vma->exec_entry = &exec[i];
158 if (eb->and < 0) {
159 eb->lut[i] = vma;
160 } else {
161 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
162 vma->exec_handle = handle;
163 hlist_add_head(&vma->exec_node,
164 &eb->buckets[handle & eb->and]);
165 }
166 ++i;
167 }
168
169 return 0;
170
171
172 err:
173 while (!list_empty(&objects)) {
174 obj = list_first_entry(&objects,
175 struct drm_i915_gem_object,
176 obj_exec_link);
177 list_del_init(&obj->obj_exec_link);
178 drm_gem_object_unreference(&obj->base);
179 }
180 /*
181 * Objects already transfered to the vmas list will be unreferenced by
182 * eb_destroy.
183 */
184
185 return ret;
186 }
187
188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
189 {
190 if (eb->and < 0) {
191 if (handle >= -eb->and)
192 return NULL;
193 return eb->lut[handle];
194 } else {
195 struct hlist_head *head;
196 struct hlist_node *node;
197
198 head = &eb->buckets[handle & eb->and];
199 hlist_for_each(node, head) {
200 struct i915_vma *vma;
201
202 vma = hlist_entry(node, struct i915_vma, exec_node);
203 if (vma->exec_handle == handle)
204 return vma;
205 }
206 return NULL;
207 }
208 }
209
210 static void
211 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
212 {
213 struct drm_i915_gem_exec_object2 *entry;
214 struct drm_i915_gem_object *obj = vma->obj;
215
216 if (!drm_mm_node_allocated(&vma->node))
217 return;
218
219 entry = vma->exec_entry;
220
221 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
222 i915_gem_object_unpin_fence(obj);
223
224 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
225 vma->pin_count--;
226
227 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
228 }
229
230 static void eb_destroy(struct eb_vmas *eb)
231 {
232 while (!list_empty(&eb->vmas)) {
233 struct i915_vma *vma;
234
235 vma = list_first_entry(&eb->vmas,
236 struct i915_vma,
237 exec_list);
238 list_del_init(&vma->exec_list);
239 i915_gem_execbuffer_unreserve_vma(vma);
240 drm_gem_object_unreference(&vma->obj->base);
241 }
242 kfree(eb);
243 }
244
245 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
246 {
247 return (HAS_LLC(obj->base.dev) ||
248 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
249 obj->cache_level != I915_CACHE_NONE);
250 }
251
252 /* Used to convert any address to canonical form.
253 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
254 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
255 * addresses to be in a canonical form:
256 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
257 * canonical form [63:48] == [47]."
258 */
259 #define GEN8_HIGH_ADDRESS_BIT 47
260 static inline uint64_t gen8_canonical_addr(uint64_t address)
261 {
262 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
263 }
264
265 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
266 {
267 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
268 }
269
270 static inline uint64_t
271 relocation_target(struct drm_i915_gem_relocation_entry *reloc,
272 uint64_t target_offset)
273 {
274 return gen8_canonical_addr((int)reloc->delta + target_offset);
275 }
276
277 static int
278 relocate_entry_cpu(struct drm_i915_gem_object *obj,
279 struct drm_i915_gem_relocation_entry *reloc,
280 uint64_t target_offset)
281 {
282 struct drm_device *dev = obj->base.dev;
283 uint32_t page_offset = offset_in_page(reloc->offset);
284 uint64_t delta = relocation_target(reloc, target_offset);
285 char *vaddr;
286 int ret;
287
288 ret = i915_gem_object_set_to_cpu_domain(obj, true);
289 if (ret)
290 return ret;
291
292 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
293 reloc->offset >> PAGE_SHIFT));
294 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
295
296 if (INTEL_INFO(dev)->gen >= 8) {
297 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
298
299 if (page_offset == 0) {
300 kunmap_atomic(vaddr);
301 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
302 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
303 }
304
305 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
306 }
307
308 kunmap_atomic(vaddr);
309
310 return 0;
311 }
312
313 static int
314 relocate_entry_gtt(struct drm_i915_gem_object *obj,
315 struct drm_i915_gem_relocation_entry *reloc,
316 uint64_t target_offset)
317 {
318 struct drm_device *dev = obj->base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320 uint64_t delta = relocation_target(reloc, target_offset);
321 uint64_t offset;
322 void __iomem *reloc_page;
323 int ret;
324
325 ret = i915_gem_object_set_to_gtt_domain(obj, true);
326 if (ret)
327 return ret;
328
329 ret = i915_gem_object_put_fence(obj);
330 if (ret)
331 return ret;
332
333 /* Map the page containing the relocation we're going to perform. */
334 offset = i915_gem_obj_ggtt_offset(obj);
335 offset += reloc->offset;
336 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
337 offset & PAGE_MASK);
338 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
339
340 if (INTEL_INFO(dev)->gen >= 8) {
341 offset += sizeof(uint32_t);
342
343 if (offset_in_page(offset) == 0) {
344 io_mapping_unmap_atomic(reloc_page);
345 reloc_page =
346 io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
347 offset);
348 }
349
350 iowrite32(upper_32_bits(delta),
351 reloc_page + offset_in_page(offset));
352 }
353
354 io_mapping_unmap_atomic(reloc_page);
355
356 return 0;
357 }
358
359 static void
360 clflush_write32(void *addr, uint32_t value)
361 {
362 /* This is not a fast path, so KISS. */
363 drm_clflush_virt_range(addr, sizeof(uint32_t));
364 *(uint32_t *)addr = value;
365 drm_clflush_virt_range(addr, sizeof(uint32_t));
366 }
367
368 static int
369 relocate_entry_clflush(struct drm_i915_gem_object *obj,
370 struct drm_i915_gem_relocation_entry *reloc,
371 uint64_t target_offset)
372 {
373 struct drm_device *dev = obj->base.dev;
374 uint32_t page_offset = offset_in_page(reloc->offset);
375 uint64_t delta = relocation_target(reloc, target_offset);
376 char *vaddr;
377 int ret;
378
379 ret = i915_gem_object_set_to_gtt_domain(obj, true);
380 if (ret)
381 return ret;
382
383 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
384 reloc->offset >> PAGE_SHIFT));
385 clflush_write32(vaddr + page_offset, lower_32_bits(delta));
386
387 if (INTEL_INFO(dev)->gen >= 8) {
388 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
389
390 if (page_offset == 0) {
391 kunmap_atomic(vaddr);
392 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
393 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
394 }
395
396 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
397 }
398
399 kunmap_atomic(vaddr);
400
401 return 0;
402 }
403
404 static int
405 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
406 struct eb_vmas *eb,
407 struct drm_i915_gem_relocation_entry *reloc)
408 {
409 struct drm_device *dev = obj->base.dev;
410 struct drm_gem_object *target_obj;
411 struct drm_i915_gem_object *target_i915_obj;
412 struct i915_vma *target_vma;
413 uint64_t target_offset;
414 int ret;
415
416 /* we've already hold a reference to all valid objects */
417 target_vma = eb_get_vma(eb, reloc->target_handle);
418 if (unlikely(target_vma == NULL))
419 return -ENOENT;
420 target_i915_obj = target_vma->obj;
421 target_obj = &target_vma->obj->base;
422
423 target_offset = gen8_canonical_addr(target_vma->node.start);
424
425 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
426 * pipe_control writes because the gpu doesn't properly redirect them
427 * through the ppgtt for non_secure batchbuffers. */
428 if (unlikely(IS_GEN6(dev) &&
429 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
430 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
431 PIN_GLOBAL);
432 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
433 return ret;
434 }
435
436 /* Validate that the target is in a valid r/w GPU domain */
437 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
438 DRM_DEBUG("reloc with multiple write domains: "
439 "obj %p target %d offset %d "
440 "read %08x write %08x",
441 obj, reloc->target_handle,
442 (int) reloc->offset,
443 reloc->read_domains,
444 reloc->write_domain);
445 return -EINVAL;
446 }
447 if (unlikely((reloc->write_domain | reloc->read_domains)
448 & ~I915_GEM_GPU_DOMAINS)) {
449 DRM_DEBUG("reloc with read/write non-GPU domains: "
450 "obj %p target %d offset %d "
451 "read %08x write %08x",
452 obj, reloc->target_handle,
453 (int) reloc->offset,
454 reloc->read_domains,
455 reloc->write_domain);
456 return -EINVAL;
457 }
458
459 target_obj->pending_read_domains |= reloc->read_domains;
460 target_obj->pending_write_domain |= reloc->write_domain;
461
462 /* If the relocation already has the right value in it, no
463 * more work needs to be done.
464 */
465 if (target_offset == reloc->presumed_offset)
466 return 0;
467
468 /* Check that the relocation address is valid... */
469 if (unlikely(reloc->offset >
470 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
471 DRM_DEBUG("Relocation beyond object bounds: "
472 "obj %p target %d offset %d size %d.\n",
473 obj, reloc->target_handle,
474 (int) reloc->offset,
475 (int) obj->base.size);
476 return -EINVAL;
477 }
478 if (unlikely(reloc->offset & 3)) {
479 DRM_DEBUG("Relocation not 4-byte aligned: "
480 "obj %p target %d offset %d.\n",
481 obj, reloc->target_handle,
482 (int) reloc->offset);
483 return -EINVAL;
484 }
485
486 /* We can't wait for rendering with pagefaults disabled */
487 if (obj->active && pagefault_disabled())
488 return -EFAULT;
489
490 if (use_cpu_reloc(obj))
491 ret = relocate_entry_cpu(obj, reloc, target_offset);
492 else if (obj->map_and_fenceable)
493 ret = relocate_entry_gtt(obj, reloc, target_offset);
494 else if (cpu_has_clflush)
495 ret = relocate_entry_clflush(obj, reloc, target_offset);
496 else {
497 WARN_ONCE(1, "Impossible case in relocation handling\n");
498 ret = -ENODEV;
499 }
500
501 if (ret)
502 return ret;
503
504 /* and update the user's relocation entry */
505 reloc->presumed_offset = target_offset;
506
507 return 0;
508 }
509
510 static int
511 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
512 struct eb_vmas *eb)
513 {
514 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
515 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
516 struct drm_i915_gem_relocation_entry __user *user_relocs;
517 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
518 int remain, ret;
519
520 user_relocs = to_user_ptr(entry->relocs_ptr);
521
522 remain = entry->relocation_count;
523 while (remain) {
524 struct drm_i915_gem_relocation_entry *r = stack_reloc;
525 int count = remain;
526 if (count > ARRAY_SIZE(stack_reloc))
527 count = ARRAY_SIZE(stack_reloc);
528 remain -= count;
529
530 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
531 return -EFAULT;
532
533 do {
534 u64 offset = r->presumed_offset;
535
536 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
537 if (ret)
538 return ret;
539
540 if (r->presumed_offset != offset &&
541 __copy_to_user_inatomic(&user_relocs->presumed_offset,
542 &r->presumed_offset,
543 sizeof(r->presumed_offset))) {
544 return -EFAULT;
545 }
546
547 user_relocs++;
548 r++;
549 } while (--count);
550 }
551
552 return 0;
553 #undef N_RELOC
554 }
555
556 static int
557 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
558 struct eb_vmas *eb,
559 struct drm_i915_gem_relocation_entry *relocs)
560 {
561 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
562 int i, ret;
563
564 for (i = 0; i < entry->relocation_count; i++) {
565 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
566 if (ret)
567 return ret;
568 }
569
570 return 0;
571 }
572
573 static int
574 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
575 {
576 struct i915_vma *vma;
577 int ret = 0;
578
579 /* This is the fast path and we cannot handle a pagefault whilst
580 * holding the struct mutex lest the user pass in the relocations
581 * contained within a mmaped bo. For in such a case we, the page
582 * fault handler would call i915_gem_fault() and we would try to
583 * acquire the struct mutex again. Obviously this is bad and so
584 * lockdep complains vehemently.
585 */
586 pagefault_disable();
587 list_for_each_entry(vma, &eb->vmas, exec_list) {
588 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
589 if (ret)
590 break;
591 }
592 pagefault_enable();
593
594 return ret;
595 }
596
597 static bool only_mappable_for_reloc(unsigned int flags)
598 {
599 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
600 __EXEC_OBJECT_NEEDS_MAP;
601 }
602
603 static int
604 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
605 struct intel_engine_cs *ring,
606 bool *need_reloc)
607 {
608 struct drm_i915_gem_object *obj = vma->obj;
609 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
610 uint64_t flags;
611 int ret;
612
613 flags = PIN_USER;
614 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
615 flags |= PIN_GLOBAL;
616
617 if (!drm_mm_node_allocated(&vma->node)) {
618 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
619 * limit address to the first 4GBs for unflagged objects.
620 */
621 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
622 flags |= PIN_ZONE_4G;
623 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
624 flags |= PIN_GLOBAL | PIN_MAPPABLE;
625 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
626 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
627 if (entry->flags & EXEC_OBJECT_PINNED)
628 flags |= entry->offset | PIN_OFFSET_FIXED;
629 if ((flags & PIN_MAPPABLE) == 0)
630 flags |= PIN_HIGH;
631 }
632
633 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
634 if ((ret == -ENOSPC || ret == -E2BIG) &&
635 only_mappable_for_reloc(entry->flags))
636 ret = i915_gem_object_pin(obj, vma->vm,
637 entry->alignment,
638 flags & ~PIN_MAPPABLE);
639 if (ret)
640 return ret;
641
642 entry->flags |= __EXEC_OBJECT_HAS_PIN;
643
644 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
645 ret = i915_gem_object_get_fence(obj);
646 if (ret)
647 return ret;
648
649 if (i915_gem_object_pin_fence(obj))
650 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
651 }
652
653 if (entry->offset != vma->node.start) {
654 entry->offset = vma->node.start;
655 *need_reloc = true;
656 }
657
658 if (entry->flags & EXEC_OBJECT_WRITE) {
659 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
660 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
661 }
662
663 return 0;
664 }
665
666 static bool
667 need_reloc_mappable(struct i915_vma *vma)
668 {
669 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
670
671 if (entry->relocation_count == 0)
672 return false;
673
674 if (!i915_is_ggtt(vma->vm))
675 return false;
676
677 /* See also use_cpu_reloc() */
678 if (HAS_LLC(vma->obj->base.dev))
679 return false;
680
681 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
682 return false;
683
684 return true;
685 }
686
687 static bool
688 eb_vma_misplaced(struct i915_vma *vma)
689 {
690 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
691 struct drm_i915_gem_object *obj = vma->obj;
692
693 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
694 !i915_is_ggtt(vma->vm));
695
696 if (entry->alignment &&
697 vma->node.start & (entry->alignment - 1))
698 return true;
699
700 if (entry->flags & EXEC_OBJECT_PINNED &&
701 vma->node.start != entry->offset)
702 return true;
703
704 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
705 vma->node.start < BATCH_OFFSET_BIAS)
706 return true;
707
708 /* avoid costly ping-pong once a batch bo ended up non-mappable */
709 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
710 return !only_mappable_for_reloc(entry->flags);
711
712 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
713 (vma->node.start + vma->node.size - 1) >> 32)
714 return true;
715
716 return false;
717 }
718
719 static int
720 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
721 struct list_head *vmas,
722 struct intel_context *ctx,
723 bool *need_relocs)
724 {
725 struct drm_i915_gem_object *obj;
726 struct i915_vma *vma;
727 struct i915_address_space *vm;
728 struct list_head ordered_vmas;
729 struct list_head pinned_vmas;
730 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
731 int retry;
732
733 i915_gem_retire_requests_ring(ring);
734
735 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
736
737 INIT_LIST_HEAD(&ordered_vmas);
738 INIT_LIST_HEAD(&pinned_vmas);
739 while (!list_empty(vmas)) {
740 struct drm_i915_gem_exec_object2 *entry;
741 bool need_fence, need_mappable;
742
743 vma = list_first_entry(vmas, struct i915_vma, exec_list);
744 obj = vma->obj;
745 entry = vma->exec_entry;
746
747 if (ctx->flags & CONTEXT_NO_ZEROMAP)
748 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
749
750 if (!has_fenced_gpu_access)
751 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
752 need_fence =
753 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
754 obj->tiling_mode != I915_TILING_NONE;
755 need_mappable = need_fence || need_reloc_mappable(vma);
756
757 if (entry->flags & EXEC_OBJECT_PINNED)
758 list_move_tail(&vma->exec_list, &pinned_vmas);
759 else if (need_mappable) {
760 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
761 list_move(&vma->exec_list, &ordered_vmas);
762 } else
763 list_move_tail(&vma->exec_list, &ordered_vmas);
764
765 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
766 obj->base.pending_write_domain = 0;
767 }
768 list_splice(&ordered_vmas, vmas);
769 list_splice(&pinned_vmas, vmas);
770
771 /* Attempt to pin all of the buffers into the GTT.
772 * This is done in 3 phases:
773 *
774 * 1a. Unbind all objects that do not match the GTT constraints for
775 * the execbuffer (fenceable, mappable, alignment etc).
776 * 1b. Increment pin count for already bound objects.
777 * 2. Bind new objects.
778 * 3. Decrement pin count.
779 *
780 * This avoid unnecessary unbinding of later objects in order to make
781 * room for the earlier objects *unless* we need to defragment.
782 */
783 retry = 0;
784 do {
785 int ret = 0;
786
787 /* Unbind any ill-fitting objects or pin. */
788 list_for_each_entry(vma, vmas, exec_list) {
789 if (!drm_mm_node_allocated(&vma->node))
790 continue;
791
792 if (eb_vma_misplaced(vma))
793 ret = i915_vma_unbind(vma);
794 else
795 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
796 if (ret)
797 goto err;
798 }
799
800 /* Bind fresh objects */
801 list_for_each_entry(vma, vmas, exec_list) {
802 if (drm_mm_node_allocated(&vma->node))
803 continue;
804
805 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
806 if (ret)
807 goto err;
808 }
809
810 err:
811 if (ret != -ENOSPC || retry++)
812 return ret;
813
814 /* Decrement pin count for bound objects */
815 list_for_each_entry(vma, vmas, exec_list)
816 i915_gem_execbuffer_unreserve_vma(vma);
817
818 ret = i915_gem_evict_vm(vm, true);
819 if (ret)
820 return ret;
821 } while (1);
822 }
823
824 static int
825 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
826 struct drm_i915_gem_execbuffer2 *args,
827 struct drm_file *file,
828 struct intel_engine_cs *ring,
829 struct eb_vmas *eb,
830 struct drm_i915_gem_exec_object2 *exec,
831 struct intel_context *ctx)
832 {
833 struct drm_i915_gem_relocation_entry *reloc;
834 struct i915_address_space *vm;
835 struct i915_vma *vma;
836 bool need_relocs;
837 int *reloc_offset;
838 int i, total, ret;
839 unsigned count = args->buffer_count;
840
841 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
842
843 /* We may process another execbuffer during the unlock... */
844 while (!list_empty(&eb->vmas)) {
845 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
846 list_del_init(&vma->exec_list);
847 i915_gem_execbuffer_unreserve_vma(vma);
848 drm_gem_object_unreference(&vma->obj->base);
849 }
850
851 mutex_unlock(&dev->struct_mutex);
852
853 total = 0;
854 for (i = 0; i < count; i++)
855 total += exec[i].relocation_count;
856
857 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
858 reloc = drm_malloc_ab(total, sizeof(*reloc));
859 if (reloc == NULL || reloc_offset == NULL) {
860 drm_free_large(reloc);
861 drm_free_large(reloc_offset);
862 mutex_lock(&dev->struct_mutex);
863 return -ENOMEM;
864 }
865
866 total = 0;
867 for (i = 0; i < count; i++) {
868 struct drm_i915_gem_relocation_entry __user *user_relocs;
869 u64 invalid_offset = (u64)-1;
870 int j;
871
872 user_relocs = to_user_ptr(exec[i].relocs_ptr);
873
874 if (copy_from_user(reloc+total, user_relocs,
875 exec[i].relocation_count * sizeof(*reloc))) {
876 ret = -EFAULT;
877 mutex_lock(&dev->struct_mutex);
878 goto err;
879 }
880
881 /* As we do not update the known relocation offsets after
882 * relocating (due to the complexities in lock handling),
883 * we need to mark them as invalid now so that we force the
884 * relocation processing next time. Just in case the target
885 * object is evicted and then rebound into its old
886 * presumed_offset before the next execbuffer - if that
887 * happened we would make the mistake of assuming that the
888 * relocations were valid.
889 */
890 for (j = 0; j < exec[i].relocation_count; j++) {
891 if (__copy_to_user(&user_relocs[j].presumed_offset,
892 &invalid_offset,
893 sizeof(invalid_offset))) {
894 ret = -EFAULT;
895 mutex_lock(&dev->struct_mutex);
896 goto err;
897 }
898 }
899
900 reloc_offset[i] = total;
901 total += exec[i].relocation_count;
902 }
903
904 ret = i915_mutex_lock_interruptible(dev);
905 if (ret) {
906 mutex_lock(&dev->struct_mutex);
907 goto err;
908 }
909
910 /* reacquire the objects */
911 eb_reset(eb);
912 ret = eb_lookup_vmas(eb, exec, args, vm, file);
913 if (ret)
914 goto err;
915
916 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
917 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
918 if (ret)
919 goto err;
920
921 list_for_each_entry(vma, &eb->vmas, exec_list) {
922 int offset = vma->exec_entry - exec;
923 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
924 reloc + reloc_offset[offset]);
925 if (ret)
926 goto err;
927 }
928
929 /* Leave the user relocations as are, this is the painfully slow path,
930 * and we want to avoid the complication of dropping the lock whilst
931 * having buffers reserved in the aperture and so causing spurious
932 * ENOSPC for random operations.
933 */
934
935 err:
936 drm_free_large(reloc);
937 drm_free_large(reloc_offset);
938 return ret;
939 }
940
941 static int
942 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
943 struct list_head *vmas)
944 {
945 const unsigned other_rings = ~intel_ring_flag(req->ring);
946 struct i915_vma *vma;
947 uint32_t flush_domains = 0;
948 bool flush_chipset = false;
949 int ret;
950
951 list_for_each_entry(vma, vmas, exec_list) {
952 struct drm_i915_gem_object *obj = vma->obj;
953
954 if (obj->active & other_rings) {
955 ret = i915_gem_object_sync(obj, req->ring, &req);
956 if (ret)
957 return ret;
958 }
959
960 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
961 flush_chipset |= i915_gem_clflush_object(obj, false);
962
963 flush_domains |= obj->base.write_domain;
964 }
965
966 if (flush_chipset)
967 i915_gem_chipset_flush(req->ring->dev);
968
969 if (flush_domains & I915_GEM_DOMAIN_GTT)
970 wmb();
971
972 /* Unconditionally invalidate gpu caches and ensure that we do flush
973 * any residual writes from the previous batch.
974 */
975 return intel_ring_invalidate_all_caches(req);
976 }
977
978 static bool
979 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
980 {
981 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
982 return false;
983
984 /* Kernel clipping was a DRI1 misfeature */
985 if (exec->num_cliprects || exec->cliprects_ptr)
986 return false;
987
988 if (exec->DR4 == 0xffffffff) {
989 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
990 exec->DR4 = 0;
991 }
992 if (exec->DR1 || exec->DR4)
993 return false;
994
995 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
996 return false;
997
998 return true;
999 }
1000
1001 static int
1002 validate_exec_list(struct drm_device *dev,
1003 struct drm_i915_gem_exec_object2 *exec,
1004 int count)
1005 {
1006 unsigned relocs_total = 0;
1007 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1008 unsigned invalid_flags;
1009 int i;
1010
1011 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1012 if (USES_FULL_PPGTT(dev))
1013 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1014
1015 for (i = 0; i < count; i++) {
1016 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
1017 int length; /* limited by fault_in_pages_readable() */
1018
1019 if (exec[i].flags & invalid_flags)
1020 return -EINVAL;
1021
1022 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1023 * any non-page-aligned or non-canonical addresses.
1024 */
1025 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1026 if (exec[i].offset !=
1027 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1028 return -EINVAL;
1029
1030 /* From drm_mm perspective address space is continuous,
1031 * so from this point we're always using non-canonical
1032 * form internally.
1033 */
1034 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1035 }
1036
1037 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1038 return -EINVAL;
1039
1040 /* First check for malicious input causing overflow in
1041 * the worst case where we need to allocate the entire
1042 * relocation tree as a single array.
1043 */
1044 if (exec[i].relocation_count > relocs_max - relocs_total)
1045 return -EINVAL;
1046 relocs_total += exec[i].relocation_count;
1047
1048 length = exec[i].relocation_count *
1049 sizeof(struct drm_i915_gem_relocation_entry);
1050 /*
1051 * We must check that the entire relocation array is safe
1052 * to read, but since we may need to update the presumed
1053 * offsets during execution, check for full write access.
1054 */
1055 if (!access_ok(VERIFY_WRITE, ptr, length))
1056 return -EFAULT;
1057
1058 if (likely(!i915.prefault_disable)) {
1059 if (fault_in_multipages_readable(ptr, length))
1060 return -EFAULT;
1061 }
1062 }
1063
1064 return 0;
1065 }
1066
1067 static struct intel_context *
1068 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1069 struct intel_engine_cs *ring, const u32 ctx_id)
1070 {
1071 struct intel_context *ctx = NULL;
1072 struct i915_ctx_hang_stats *hs;
1073
1074 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1075 return ERR_PTR(-EINVAL);
1076
1077 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
1078 if (IS_ERR(ctx))
1079 return ctx;
1080
1081 hs = &ctx->hang_stats;
1082 if (hs->banned) {
1083 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1084 return ERR_PTR(-EIO);
1085 }
1086
1087 if (i915.enable_execlists && !ctx->engine[ring->id].state) {
1088 int ret = intel_lr_context_deferred_alloc(ctx, ring);
1089 if (ret) {
1090 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
1091 return ERR_PTR(ret);
1092 }
1093 }
1094
1095 return ctx;
1096 }
1097
1098 void
1099 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1100 struct drm_i915_gem_request *req)
1101 {
1102 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1103 struct i915_vma *vma;
1104
1105 list_for_each_entry(vma, vmas, exec_list) {
1106 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1107 struct drm_i915_gem_object *obj = vma->obj;
1108 u32 old_read = obj->base.read_domains;
1109 u32 old_write = obj->base.write_domain;
1110
1111 obj->dirty = 1; /* be paranoid */
1112 obj->base.write_domain = obj->base.pending_write_domain;
1113 if (obj->base.write_domain == 0)
1114 obj->base.pending_read_domains |= obj->base.read_domains;
1115 obj->base.read_domains = obj->base.pending_read_domains;
1116
1117 i915_vma_move_to_active(vma, req);
1118 if (obj->base.write_domain) {
1119 i915_gem_request_assign(&obj->last_write_req, req);
1120
1121 intel_fb_obj_invalidate(obj, ORIGIN_CS);
1122
1123 /* update for the implicit flush after a batch */
1124 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125 }
1126 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1127 i915_gem_request_assign(&obj->last_fenced_req, req);
1128 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1129 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1130 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1131 &dev_priv->mm.fence_list);
1132 }
1133 }
1134
1135 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1136 }
1137 }
1138
1139 void
1140 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1141 {
1142 /* Unconditionally force add_request to emit a full flush. */
1143 params->ring->gpu_caches_dirty = true;
1144
1145 /* Add a breadcrumb for the completion of the batch buffer */
1146 __i915_add_request(params->request, params->batch_obj, true);
1147 }
1148
1149 static int
1150 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1151 struct drm_i915_gem_request *req)
1152 {
1153 struct intel_engine_cs *ring = req->ring;
1154 struct drm_i915_private *dev_priv = dev->dev_private;
1155 int ret, i;
1156
1157 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
1158 DRM_DEBUG("sol reset is gen7/rcs only\n");
1159 return -EINVAL;
1160 }
1161
1162 ret = intel_ring_begin(req, 4 * 3);
1163 if (ret)
1164 return ret;
1165
1166 for (i = 0; i < 4; i++) {
1167 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1168 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1169 intel_ring_emit(ring, 0);
1170 }
1171
1172 intel_ring_advance(ring);
1173
1174 return 0;
1175 }
1176
1177 static struct drm_i915_gem_object*
1178 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
1179 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1180 struct eb_vmas *eb,
1181 struct drm_i915_gem_object *batch_obj,
1182 u32 batch_start_offset,
1183 u32 batch_len,
1184 bool is_master)
1185 {
1186 struct drm_i915_gem_object *shadow_batch_obj;
1187 struct i915_vma *vma;
1188 int ret;
1189
1190 shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
1191 PAGE_ALIGN(batch_len));
1192 if (IS_ERR(shadow_batch_obj))
1193 return shadow_batch_obj;
1194
1195 ret = i915_parse_cmds(ring,
1196 batch_obj,
1197 shadow_batch_obj,
1198 batch_start_offset,
1199 batch_len,
1200 is_master);
1201 if (ret)
1202 goto err;
1203
1204 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1205 if (ret)
1206 goto err;
1207
1208 i915_gem_object_unpin_pages(shadow_batch_obj);
1209
1210 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1211
1212 vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1213 vma->exec_entry = shadow_exec_entry;
1214 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1215 drm_gem_object_reference(&shadow_batch_obj->base);
1216 list_add_tail(&vma->exec_list, &eb->vmas);
1217
1218 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1219
1220 return shadow_batch_obj;
1221
1222 err:
1223 i915_gem_object_unpin_pages(shadow_batch_obj);
1224 if (ret == -EACCES) /* unhandled chained batch */
1225 return batch_obj;
1226 else
1227 return ERR_PTR(ret);
1228 }
1229
1230 int
1231 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
1232 struct drm_i915_gem_execbuffer2 *args,
1233 struct list_head *vmas)
1234 {
1235 struct drm_device *dev = params->dev;
1236 struct intel_engine_cs *ring = params->ring;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 u64 exec_start, exec_len;
1239 int instp_mode;
1240 u32 instp_mask;
1241 int ret;
1242
1243 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1244 if (ret)
1245 return ret;
1246
1247 ret = i915_switch_context(params->request);
1248 if (ret)
1249 return ret;
1250
1251 WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
1252 "%s didn't clear reload\n", ring->name);
1253
1254 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1255 instp_mask = I915_EXEC_CONSTANTS_MASK;
1256 switch (instp_mode) {
1257 case I915_EXEC_CONSTANTS_REL_GENERAL:
1258 case I915_EXEC_CONSTANTS_ABSOLUTE:
1259 case I915_EXEC_CONSTANTS_REL_SURFACE:
1260 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
1261 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1262 return -EINVAL;
1263 }
1264
1265 if (instp_mode != dev_priv->relative_constants_mode) {
1266 if (INTEL_INFO(dev)->gen < 4) {
1267 DRM_DEBUG("no rel constants on pre-gen4\n");
1268 return -EINVAL;
1269 }
1270
1271 if (INTEL_INFO(dev)->gen > 5 &&
1272 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1273 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1274 return -EINVAL;
1275 }
1276
1277 /* The HW changed the meaning on this bit on gen6 */
1278 if (INTEL_INFO(dev)->gen >= 6)
1279 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1280 }
1281 break;
1282 default:
1283 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1284 return -EINVAL;
1285 }
1286
1287 if (ring == &dev_priv->ring[RCS] &&
1288 instp_mode != dev_priv->relative_constants_mode) {
1289 ret = intel_ring_begin(params->request, 4);
1290 if (ret)
1291 return ret;
1292
1293 intel_ring_emit(ring, MI_NOOP);
1294 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1295 intel_ring_emit_reg(ring, INSTPM);
1296 intel_ring_emit(ring, instp_mask << 16 | instp_mode);
1297 intel_ring_advance(ring);
1298
1299 dev_priv->relative_constants_mode = instp_mode;
1300 }
1301
1302 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1303 ret = i915_reset_gen7_sol_offsets(dev, params->request);
1304 if (ret)
1305 return ret;
1306 }
1307
1308 exec_len = args->batch_len;
1309 exec_start = params->batch_obj_vm_offset +
1310 params->args_batch_start_offset;
1311
1312 ret = ring->dispatch_execbuffer(params->request,
1313 exec_start, exec_len,
1314 params->dispatch_flags);
1315 if (ret)
1316 return ret;
1317
1318 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1319
1320 i915_gem_execbuffer_move_to_active(vmas, params->request);
1321 i915_gem_execbuffer_retire_commands(params);
1322
1323 return 0;
1324 }
1325
1326 /**
1327 * Find one BSD ring to dispatch the corresponding BSD command.
1328 * The Ring ID is returned.
1329 */
1330 static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1331 struct drm_file *file)
1332 {
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct drm_i915_file_private *file_priv = file->driver_priv;
1335
1336 /* Check whether the file_priv is using one ring */
1337 if (file_priv->bsd_ring)
1338 return file_priv->bsd_ring->id;
1339 else {
1340 /* If no, use the ping-pong mechanism to select one ring */
1341 int ring_id;
1342
1343 mutex_lock(&dev->struct_mutex);
1344 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1345 ring_id = VCS;
1346 dev_priv->mm.bsd_ring_dispatch_index = 1;
1347 } else {
1348 ring_id = VCS2;
1349 dev_priv->mm.bsd_ring_dispatch_index = 0;
1350 }
1351 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1352 mutex_unlock(&dev->struct_mutex);
1353 return ring_id;
1354 }
1355 }
1356
1357 static struct drm_i915_gem_object *
1358 eb_get_batch(struct eb_vmas *eb)
1359 {
1360 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1361
1362 /*
1363 * SNA is doing fancy tricks with compressing batch buffers, which leads
1364 * to negative relocation deltas. Usually that works out ok since the
1365 * relocate address is still positive, except when the batch is placed
1366 * very low in the GTT. Ensure this doesn't happen.
1367 *
1368 * Note that actual hangs have only been observed on gen7, but for
1369 * paranoia do it everywhere.
1370 */
1371 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
1372 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1373
1374 return vma->obj;
1375 }
1376
1377 static int
1378 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1379 struct drm_file *file,
1380 struct drm_i915_gem_execbuffer2 *args,
1381 struct drm_i915_gem_exec_object2 *exec)
1382 {
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 struct eb_vmas *eb;
1385 struct drm_i915_gem_object *batch_obj;
1386 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1387 struct intel_engine_cs *ring;
1388 struct intel_context *ctx;
1389 struct i915_address_space *vm;
1390 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1391 struct i915_execbuffer_params *params = &params_master;
1392 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1393 u32 dispatch_flags;
1394 int ret;
1395 bool need_relocs;
1396
1397 if (!i915_gem_check_execbuffer(args))
1398 return -EINVAL;
1399
1400 ret = validate_exec_list(dev, exec, args->buffer_count);
1401 if (ret)
1402 return ret;
1403
1404 dispatch_flags = 0;
1405 if (args->flags & I915_EXEC_SECURE) {
1406 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1407 return -EPERM;
1408
1409 dispatch_flags |= I915_DISPATCH_SECURE;
1410 }
1411 if (args->flags & I915_EXEC_IS_PINNED)
1412 dispatch_flags |= I915_DISPATCH_PINNED;
1413
1414 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1415 DRM_DEBUG("execbuf with unknown ring: %d\n",
1416 (int)(args->flags & I915_EXEC_RING_MASK));
1417 return -EINVAL;
1418 }
1419
1420 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1421 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1422 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1423 "bsd dispatch flags: %d\n", (int)(args->flags));
1424 return -EINVAL;
1425 }
1426
1427 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1428 ring = &dev_priv->ring[RCS];
1429 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1430 if (HAS_BSD2(dev)) {
1431 int ring_id;
1432
1433 switch (args->flags & I915_EXEC_BSD_MASK) {
1434 case I915_EXEC_BSD_DEFAULT:
1435 ring_id = gen8_dispatch_bsd_ring(dev, file);
1436 ring = &dev_priv->ring[ring_id];
1437 break;
1438 case I915_EXEC_BSD_RING1:
1439 ring = &dev_priv->ring[VCS];
1440 break;
1441 case I915_EXEC_BSD_RING2:
1442 ring = &dev_priv->ring[VCS2];
1443 break;
1444 default:
1445 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1446 (int)(args->flags & I915_EXEC_BSD_MASK));
1447 return -EINVAL;
1448 }
1449 } else
1450 ring = &dev_priv->ring[VCS];
1451 } else
1452 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1453
1454 if (!intel_ring_initialized(ring)) {
1455 DRM_DEBUG("execbuf with invalid ring: %d\n",
1456 (int)(args->flags & I915_EXEC_RING_MASK));
1457 return -EINVAL;
1458 }
1459
1460 if (args->buffer_count < 1) {
1461 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1462 return -EINVAL;
1463 }
1464
1465 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1466 if (!HAS_RESOURCE_STREAMER(dev)) {
1467 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1468 return -EINVAL;
1469 }
1470 if (ring->id != RCS) {
1471 DRM_DEBUG("RS is not available on %s\n",
1472 ring->name);
1473 return -EINVAL;
1474 }
1475
1476 dispatch_flags |= I915_DISPATCH_RS;
1477 }
1478
1479 intel_runtime_pm_get(dev_priv);
1480
1481 ret = i915_mutex_lock_interruptible(dev);
1482 if (ret)
1483 goto pre_mutex_err;
1484
1485 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1486 if (IS_ERR(ctx)) {
1487 mutex_unlock(&dev->struct_mutex);
1488 ret = PTR_ERR(ctx);
1489 goto pre_mutex_err;
1490 }
1491
1492 i915_gem_context_reference(ctx);
1493
1494 if (ctx->ppgtt)
1495 vm = &ctx->ppgtt->base;
1496 else
1497 vm = &dev_priv->gtt.base;
1498
1499 memset(&params_master, 0x00, sizeof(params_master));
1500
1501 eb = eb_create(args);
1502 if (eb == NULL) {
1503 i915_gem_context_unreference(ctx);
1504 mutex_unlock(&dev->struct_mutex);
1505 ret = -ENOMEM;
1506 goto pre_mutex_err;
1507 }
1508
1509 /* Look up object handles */
1510 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1511 if (ret)
1512 goto err;
1513
1514 /* take note of the batch buffer before we might reorder the lists */
1515 batch_obj = eb_get_batch(eb);
1516
1517 /* Move the objects en-masse into the GTT, evicting if necessary. */
1518 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1519 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
1520 if (ret)
1521 goto err;
1522
1523 /* The objects are in their final locations, apply the relocations. */
1524 if (need_relocs)
1525 ret = i915_gem_execbuffer_relocate(eb);
1526 if (ret) {
1527 if (ret == -EFAULT) {
1528 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1529 eb, exec, ctx);
1530 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1531 }
1532 if (ret)
1533 goto err;
1534 }
1535
1536 /* Set the pending read domains for the batch buffer to COMMAND */
1537 if (batch_obj->base.pending_write_domain) {
1538 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1539 ret = -EINVAL;
1540 goto err;
1541 }
1542
1543 params->args_batch_start_offset = args->batch_start_offset;
1544 if (i915_needs_cmd_parser(ring) && args->batch_len) {
1545 struct drm_i915_gem_object *parsed_batch_obj;
1546
1547 parsed_batch_obj = i915_gem_execbuffer_parse(ring,
1548 &shadow_exec_entry,
1549 eb,
1550 batch_obj,
1551 args->batch_start_offset,
1552 args->batch_len,
1553 file->is_master);
1554 if (IS_ERR(parsed_batch_obj)) {
1555 ret = PTR_ERR(parsed_batch_obj);
1556 goto err;
1557 }
1558
1559 /*
1560 * parsed_batch_obj == batch_obj means batch not fully parsed:
1561 * Accept, but don't promote to secure.
1562 */
1563
1564 if (parsed_batch_obj != batch_obj) {
1565 /*
1566 * Batch parsed and accepted:
1567 *
1568 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1569 * bit from MI_BATCH_BUFFER_START commands issued in
1570 * the dispatch_execbuffer implementations. We
1571 * specifically don't want that set on batches the
1572 * command parser has accepted.
1573 */
1574 dispatch_flags |= I915_DISPATCH_SECURE;
1575 params->args_batch_start_offset = 0;
1576 batch_obj = parsed_batch_obj;
1577 }
1578 }
1579
1580 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1581
1582 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1583 * batch" bit. Hence we need to pin secure batches into the global gtt.
1584 * hsw should have this fixed, but bdw mucks it up again. */
1585 if (dispatch_flags & I915_DISPATCH_SECURE) {
1586 /*
1587 * So on first glance it looks freaky that we pin the batch here
1588 * outside of the reservation loop. But:
1589 * - The batch is already pinned into the relevant ppgtt, so we
1590 * already have the backing storage fully allocated.
1591 * - No other BO uses the global gtt (well contexts, but meh),
1592 * so we don't really have issues with multiple objects not
1593 * fitting due to fragmentation.
1594 * So this is actually safe.
1595 */
1596 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1597 if (ret)
1598 goto err;
1599
1600 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1601 } else
1602 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1603
1604 /* Allocate a request for this batch buffer nice and early. */
1605 ret = i915_gem_request_alloc(ring, ctx, &params->request);
1606 if (ret)
1607 goto err_batch_unpin;
1608
1609 ret = i915_gem_request_add_to_client(params->request, file);
1610 if (ret)
1611 goto err_batch_unpin;
1612
1613 /*
1614 * Save assorted stuff away to pass through to *_submission().
1615 * NB: This data should be 'persistent' and not local as it will
1616 * kept around beyond the duration of the IOCTL once the GPU
1617 * scheduler arrives.
1618 */
1619 params->dev = dev;
1620 params->file = file;
1621 params->ring = ring;
1622 params->dispatch_flags = dispatch_flags;
1623 params->batch_obj = batch_obj;
1624 params->ctx = ctx;
1625
1626 ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
1627
1628 err_batch_unpin:
1629 /*
1630 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1631 * batch vma for correctness. For less ugly and less fragility this
1632 * needs to be adjusted to also track the ggtt batch vma properly as
1633 * active.
1634 */
1635 if (dispatch_flags & I915_DISPATCH_SECURE)
1636 i915_gem_object_ggtt_unpin(batch_obj);
1637
1638 err:
1639 /* the request owns the ref now */
1640 i915_gem_context_unreference(ctx);
1641 eb_destroy(eb);
1642
1643 /*
1644 * If the request was created but not successfully submitted then it
1645 * must be freed again. If it was submitted then it is being tracked
1646 * on the active request list and no clean up is required here.
1647 */
1648 if (ret && params->request)
1649 i915_gem_request_cancel(params->request);
1650
1651 mutex_unlock(&dev->struct_mutex);
1652
1653 pre_mutex_err:
1654 /* intel_gpu_busy should also get a ref, so it will free when the device
1655 * is really idle. */
1656 intel_runtime_pm_put(dev_priv);
1657 return ret;
1658 }
1659
1660 /*
1661 * Legacy execbuffer just creates an exec2 list from the original exec object
1662 * list array and passes it to the real function.
1663 */
1664 int
1665 i915_gem_execbuffer(struct drm_device *dev, void *data,
1666 struct drm_file *file)
1667 {
1668 struct drm_i915_gem_execbuffer *args = data;
1669 struct drm_i915_gem_execbuffer2 exec2;
1670 struct drm_i915_gem_exec_object *exec_list = NULL;
1671 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1672 int ret, i;
1673
1674 if (args->buffer_count < 1) {
1675 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1676 return -EINVAL;
1677 }
1678
1679 /* Copy in the exec list from userland */
1680 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1681 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1682 if (exec_list == NULL || exec2_list == NULL) {
1683 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1684 args->buffer_count);
1685 drm_free_large(exec_list);
1686 drm_free_large(exec2_list);
1687 return -ENOMEM;
1688 }
1689 ret = copy_from_user(exec_list,
1690 to_user_ptr(args->buffers_ptr),
1691 sizeof(*exec_list) * args->buffer_count);
1692 if (ret != 0) {
1693 DRM_DEBUG("copy %d exec entries failed %d\n",
1694 args->buffer_count, ret);
1695 drm_free_large(exec_list);
1696 drm_free_large(exec2_list);
1697 return -EFAULT;
1698 }
1699
1700 for (i = 0; i < args->buffer_count; i++) {
1701 exec2_list[i].handle = exec_list[i].handle;
1702 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1703 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1704 exec2_list[i].alignment = exec_list[i].alignment;
1705 exec2_list[i].offset = exec_list[i].offset;
1706 if (INTEL_INFO(dev)->gen < 4)
1707 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1708 else
1709 exec2_list[i].flags = 0;
1710 }
1711
1712 exec2.buffers_ptr = args->buffers_ptr;
1713 exec2.buffer_count = args->buffer_count;
1714 exec2.batch_start_offset = args->batch_start_offset;
1715 exec2.batch_len = args->batch_len;
1716 exec2.DR1 = args->DR1;
1717 exec2.DR4 = args->DR4;
1718 exec2.num_cliprects = args->num_cliprects;
1719 exec2.cliprects_ptr = args->cliprects_ptr;
1720 exec2.flags = I915_EXEC_RENDER;
1721 i915_execbuffer2_set_context_id(exec2, 0);
1722
1723 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1724 if (!ret) {
1725 struct drm_i915_gem_exec_object __user *user_exec_list =
1726 to_user_ptr(args->buffers_ptr);
1727
1728 /* Copy the new buffer offsets back to the user's exec list. */
1729 for (i = 0; i < args->buffer_count; i++) {
1730 exec2_list[i].offset =
1731 gen8_canonical_addr(exec2_list[i].offset);
1732 ret = __copy_to_user(&user_exec_list[i].offset,
1733 &exec2_list[i].offset,
1734 sizeof(user_exec_list[i].offset));
1735 if (ret) {
1736 ret = -EFAULT;
1737 DRM_DEBUG("failed to copy %d exec entries "
1738 "back to user (%d)\n",
1739 args->buffer_count, ret);
1740 break;
1741 }
1742 }
1743 }
1744
1745 drm_free_large(exec_list);
1746 drm_free_large(exec2_list);
1747 return ret;
1748 }
1749
1750 int
1751 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1752 struct drm_file *file)
1753 {
1754 struct drm_i915_gem_execbuffer2 *args = data;
1755 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1756 int ret;
1757
1758 if (args->buffer_count < 1 ||
1759 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1760 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1761 return -EINVAL;
1762 }
1763
1764 if (args->rsvd2 != 0) {
1765 DRM_DEBUG("dirty rvsd2 field\n");
1766 return -EINVAL;
1767 }
1768
1769 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1770 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1771 if (exec2_list == NULL)
1772 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1773 args->buffer_count);
1774 if (exec2_list == NULL) {
1775 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1776 args->buffer_count);
1777 return -ENOMEM;
1778 }
1779 ret = copy_from_user(exec2_list,
1780 to_user_ptr(args->buffers_ptr),
1781 sizeof(*exec2_list) * args->buffer_count);
1782 if (ret != 0) {
1783 DRM_DEBUG("copy %d exec entries failed %d\n",
1784 args->buffer_count, ret);
1785 drm_free_large(exec2_list);
1786 return -EFAULT;
1787 }
1788
1789 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1790 if (!ret) {
1791 /* Copy the new buffer offsets back to the user's exec list. */
1792 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1793 to_user_ptr(args->buffers_ptr);
1794 int i;
1795
1796 for (i = 0; i < args->buffer_count; i++) {
1797 exec2_list[i].offset =
1798 gen8_canonical_addr(exec2_list[i].offset);
1799 ret = __copy_to_user(&user_exec_list[i].offset,
1800 &exec2_list[i].offset,
1801 sizeof(user_exec_list[i].offset));
1802 if (ret) {
1803 ret = -EFAULT;
1804 DRM_DEBUG("failed to copy %d exec entries "
1805 "back to user\n",
1806 args->buffer_count);
1807 break;
1808 }
1809 }
1810 }
1811
1812 drm_free_large(exec2_list);
1813 return ret;
1814 }
Linux kernel - Deliverables
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