Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_request.c
1 /*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/prefetch.h>
26
27 #include "i915_drv.h"
28
29 static const char *i915_fence_get_driver_name(struct fence *fence)
30 {
31 return "i915";
32 }
33
34 static const char *i915_fence_get_timeline_name(struct fence *fence)
35 {
36 /* Timelines are bound by eviction to a VM. However, since
37 * we only have a global seqno at the moment, we only have
38 * a single timeline. Note that each timeline will have
39 * multiple execution contexts (fence contexts) as we allow
40 * engines within a single timeline to execute in parallel.
41 */
42 return "global";
43 }
44
45 static bool i915_fence_signaled(struct fence *fence)
46 {
47 return i915_gem_request_completed(to_request(fence));
48 }
49
50 static bool i915_fence_enable_signaling(struct fence *fence)
51 {
52 if (i915_fence_signaled(fence))
53 return false;
54
55 intel_engine_enable_signaling(to_request(fence));
56 return true;
57 }
58
59 static signed long i915_fence_wait(struct fence *fence,
60 bool interruptible,
61 signed long timeout_jiffies)
62 {
63 s64 timeout_ns, *timeout;
64 int ret;
65
66 if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) {
67 timeout_ns = jiffies_to_nsecs(timeout_jiffies);
68 timeout = &timeout_ns;
69 } else {
70 timeout = NULL;
71 }
72
73 ret = i915_wait_request(to_request(fence),
74 interruptible, timeout,
75 NO_WAITBOOST);
76 if (ret == -ETIME)
77 return 0;
78
79 if (ret < 0)
80 return ret;
81
82 if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT)
83 timeout_jiffies = nsecs_to_jiffies(timeout_ns);
84
85 return timeout_jiffies;
86 }
87
88 static void i915_fence_value_str(struct fence *fence, char *str, int size)
89 {
90 snprintf(str, size, "%u", fence->seqno);
91 }
92
93 static void i915_fence_timeline_value_str(struct fence *fence, char *str,
94 int size)
95 {
96 snprintf(str, size, "%u",
97 intel_engine_get_seqno(to_request(fence)->engine));
98 }
99
100 static void i915_fence_release(struct fence *fence)
101 {
102 struct drm_i915_gem_request *req = to_request(fence);
103
104 kmem_cache_free(req->i915->requests, req);
105 }
106
107 const struct fence_ops i915_fence_ops = {
108 .get_driver_name = i915_fence_get_driver_name,
109 .get_timeline_name = i915_fence_get_timeline_name,
110 .enable_signaling = i915_fence_enable_signaling,
111 .signaled = i915_fence_signaled,
112 .wait = i915_fence_wait,
113 .release = i915_fence_release,
114 .fence_value_str = i915_fence_value_str,
115 .timeline_value_str = i915_fence_timeline_value_str,
116 };
117
118 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
119 struct drm_file *file)
120 {
121 struct drm_i915_private *dev_private;
122 struct drm_i915_file_private *file_priv;
123
124 WARN_ON(!req || !file || req->file_priv);
125
126 if (!req || !file)
127 return -EINVAL;
128
129 if (req->file_priv)
130 return -EINVAL;
131
132 dev_private = req->i915;
133 file_priv = file->driver_priv;
134
135 spin_lock(&file_priv->mm.lock);
136 req->file_priv = file_priv;
137 list_add_tail(&req->client_list, &file_priv->mm.request_list);
138 spin_unlock(&file_priv->mm.lock);
139
140 return 0;
141 }
142
143 static inline void
144 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
145 {
146 struct drm_i915_file_private *file_priv = request->file_priv;
147
148 if (!file_priv)
149 return;
150
151 spin_lock(&file_priv->mm.lock);
152 list_del(&request->client_list);
153 request->file_priv = NULL;
154 spin_unlock(&file_priv->mm.lock);
155 }
156
157 void i915_gem_retire_noop(struct i915_gem_active *active,
158 struct drm_i915_gem_request *request)
159 {
160 /* Space left intentionally blank */
161 }
162
163 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
164 {
165 struct i915_gem_active *active, *next;
166
167 trace_i915_gem_request_retire(request);
168 list_del(&request->link);
169
170 /* We know the GPU must have read the request to have
171 * sent us the seqno + interrupt, so use the position
172 * of tail of the request to update the last known position
173 * of the GPU head.
174 *
175 * Note this requires that we are always called in request
176 * completion order.
177 */
178 list_del(&request->ring_link);
179 request->ring->last_retired_head = request->postfix;
180
181 /* Walk through the active list, calling retire on each. This allows
182 * objects to track their GPU activity and mark themselves as idle
183 * when their *last* active request is completed (updating state
184 * tracking lists for eviction, active references for GEM, etc).
185 *
186 * As the ->retire() may free the node, we decouple it first and
187 * pass along the auxiliary information (to avoid dereferencing
188 * the node after the callback).
189 */
190 list_for_each_entry_safe(active, next, &request->active_list, link) {
191 /* In microbenchmarks or focusing upon time inside the kernel,
192 * we may spend an inordinate amount of time simply handling
193 * the retirement of requests and processing their callbacks.
194 * Of which, this loop itself is particularly hot due to the
195 * cache misses when jumping around the list of i915_gem_active.
196 * So we try to keep this loop as streamlined as possible and
197 * also prefetch the next i915_gem_active to try and hide
198 * the likely cache miss.
199 */
200 prefetchw(next);
201
202 INIT_LIST_HEAD(&active->link);
203 RCU_INIT_POINTER(active->request, NULL);
204
205 active->retire(active, request);
206 }
207
208 i915_gem_request_remove_from_client(request);
209
210 if (request->previous_context) {
211 if (i915.enable_execlists)
212 intel_lr_context_unpin(request->previous_context,
213 request->engine);
214 }
215
216 i915_gem_context_put(request->ctx);
217 i915_gem_request_put(request);
218 }
219
220 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
221 {
222 struct intel_engine_cs *engine = req->engine;
223 struct drm_i915_gem_request *tmp;
224
225 lockdep_assert_held(&req->i915->drm.struct_mutex);
226 GEM_BUG_ON(list_empty(&req->link));
227
228 do {
229 tmp = list_first_entry(&engine->request_list,
230 typeof(*tmp), link);
231
232 i915_gem_request_retire(tmp);
233 } while (tmp != req);
234 }
235
236 static int i915_gem_check_wedge(struct drm_i915_private *dev_priv)
237 {
238 struct i915_gpu_error *error = &dev_priv->gpu_error;
239
240 if (i915_terminally_wedged(error))
241 return -EIO;
242
243 if (i915_reset_in_progress(error)) {
244 /* Non-interruptible callers can't handle -EAGAIN, hence return
245 * -EIO unconditionally for these.
246 */
247 if (!dev_priv->mm.interruptible)
248 return -EIO;
249
250 return -EAGAIN;
251 }
252
253 return 0;
254 }
255
256 static int i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
257 {
258 struct intel_engine_cs *engine;
259 int ret;
260
261 /* Carefully retire all requests without writing to the rings */
262 for_each_engine(engine, dev_priv) {
263 ret = intel_engine_idle(engine,
264 I915_WAIT_INTERRUPTIBLE |
265 I915_WAIT_LOCKED);
266 if (ret)
267 return ret;
268 }
269 i915_gem_retire_requests(dev_priv);
270
271 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
272 if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) {
273 while (intel_kick_waiters(dev_priv) ||
274 intel_kick_signalers(dev_priv))
275 yield();
276 }
277
278 /* Finally reset hw state */
279 for_each_engine(engine, dev_priv)
280 intel_engine_init_seqno(engine, seqno);
281
282 return 0;
283 }
284
285 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
286 {
287 struct drm_i915_private *dev_priv = to_i915(dev);
288 int ret;
289
290 if (seqno == 0)
291 return -EINVAL;
292
293 /* HWS page needs to be set less than what we
294 * will inject to ring
295 */
296 ret = i915_gem_init_seqno(dev_priv, seqno - 1);
297 if (ret)
298 return ret;
299
300 dev_priv->next_seqno = seqno;
301 return 0;
302 }
303
304 static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
305 {
306 /* reserve 0 for non-seqno */
307 if (unlikely(dev_priv->next_seqno == 0)) {
308 int ret;
309
310 ret = i915_gem_init_seqno(dev_priv, 0);
311 if (ret)
312 return ret;
313
314 dev_priv->next_seqno = 1;
315 }
316
317 *seqno = dev_priv->next_seqno++;
318 return 0;
319 }
320
321 static int __i915_sw_fence_call
322 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
323 {
324 struct drm_i915_gem_request *request =
325 container_of(fence, typeof(*request), submit);
326
327 /* Will be called from irq-context when using foreign DMA fences */
328
329 switch (state) {
330 case FENCE_COMPLETE:
331 request->engine->submit_request(request);
332 break;
333
334 case FENCE_FREE:
335 break;
336 }
337
338 return NOTIFY_DONE;
339 }
340
341 /**
342 * i915_gem_request_alloc - allocate a request structure
343 *
344 * @engine: engine that we wish to issue the request on.
345 * @ctx: context that the request will be associated with.
346 * This can be NULL if the request is not directly related to
347 * any specific user context, in which case this function will
348 * choose an appropriate context to use.
349 *
350 * Returns a pointer to the allocated request if successful,
351 * or an error code if not.
352 */
353 struct drm_i915_gem_request *
354 i915_gem_request_alloc(struct intel_engine_cs *engine,
355 struct i915_gem_context *ctx)
356 {
357 struct drm_i915_private *dev_priv = engine->i915;
358 struct drm_i915_gem_request *req;
359 u32 seqno;
360 int ret;
361
362 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
363 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
364 * and restart.
365 */
366 ret = i915_gem_check_wedge(dev_priv);
367 if (ret)
368 return ERR_PTR(ret);
369
370 /* Move the oldest request to the slab-cache (if not in use!) */
371 req = list_first_entry_or_null(&engine->request_list,
372 typeof(*req), link);
373 if (req && i915_gem_request_completed(req))
374 i915_gem_request_retire(req);
375
376 /* Beware: Dragons be flying overhead.
377 *
378 * We use RCU to look up requests in flight. The lookups may
379 * race with the request being allocated from the slab freelist.
380 * That is the request we are writing to here, may be in the process
381 * of being read by __i915_gem_active_get_rcu(). As such,
382 * we have to be very careful when overwriting the contents. During
383 * the RCU lookup, we change chase the request->engine pointer,
384 * read the request->fence.seqno and increment the reference count.
385 *
386 * The reference count is incremented atomically. If it is zero,
387 * the lookup knows the request is unallocated and complete. Otherwise,
388 * it is either still in use, or has been reallocated and reset
389 * with fence_init(). This increment is safe for release as we check
390 * that the request we have a reference to and matches the active
391 * request.
392 *
393 * Before we increment the refcount, we chase the request->engine
394 * pointer. We must not call kmem_cache_zalloc() or else we set
395 * that pointer to NULL and cause a crash during the lookup. If
396 * we see the request is completed (based on the value of the
397 * old engine and seqno), the lookup is complete and reports NULL.
398 * If we decide the request is not completed (new engine or seqno),
399 * then we grab a reference and double check that it is still the
400 * active request - which it won't be and restart the lookup.
401 *
402 * Do not use kmem_cache_zalloc() here!
403 */
404 req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
405 if (!req)
406 return ERR_PTR(-ENOMEM);
407
408 ret = i915_gem_get_seqno(dev_priv, &seqno);
409 if (ret)
410 goto err;
411
412 spin_lock_init(&req->lock);
413 fence_init(&req->fence,
414 &i915_fence_ops,
415 &req->lock,
416 engine->fence_context,
417 seqno);
418
419 i915_sw_fence_init(&req->submit, submit_notify);
420
421 INIT_LIST_HEAD(&req->active_list);
422 req->i915 = dev_priv;
423 req->engine = engine;
424 req->ctx = i915_gem_context_get(ctx);
425
426 /* No zalloc, must clear what we need by hand */
427 req->previous_context = NULL;
428 req->file_priv = NULL;
429 req->batch = NULL;
430
431 /*
432 * Reserve space in the ring buffer for all the commands required to
433 * eventually emit this request. This is to guarantee that the
434 * i915_add_request() call can't fail. Note that the reserve may need
435 * to be redone if the request is not actually submitted straight
436 * away, e.g. because a GPU scheduler has deferred it.
437 */
438 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
439
440 if (i915.enable_execlists)
441 ret = intel_logical_ring_alloc_request_extras(req);
442 else
443 ret = intel_ring_alloc_request_extras(req);
444 if (ret)
445 goto err_ctx;
446
447 /* Record the position of the start of the request so that
448 * should we detect the updated seqno part-way through the
449 * GPU processing the request, we never over-estimate the
450 * position of the head.
451 */
452 req->head = req->ring->tail;
453
454 return req;
455
456 err_ctx:
457 i915_gem_context_put(ctx);
458 err:
459 kmem_cache_free(dev_priv->requests, req);
460 return ERR_PTR(ret);
461 }
462
463 static int
464 i915_gem_request_await_request(struct drm_i915_gem_request *to,
465 struct drm_i915_gem_request *from)
466 {
467 int idx, ret;
468
469 GEM_BUG_ON(to == from);
470
471 if (to->engine == from->engine)
472 return 0;
473
474 idx = intel_engine_sync_index(from->engine, to->engine);
475 if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx])
476 return 0;
477
478 trace_i915_gem_ring_sync_to(to, from);
479 if (!i915.semaphores) {
480 if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
481 ret = i915_sw_fence_await_dma_fence(&to->submit,
482 &from->fence, 0,
483 GFP_KERNEL);
484 if (ret < 0)
485 return ret;
486 }
487 } else {
488 ret = to->engine->semaphore.sync_to(to, from);
489 if (ret)
490 return ret;
491 }
492
493 from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
494 return 0;
495 }
496
497 /**
498 * i915_gem_request_await_object - set this request to (async) wait upon a bo
499 *
500 * @to: request we are wishing to use
501 * @obj: object which may be in use on another ring.
502 *
503 * This code is meant to abstract object synchronization with the GPU.
504 * Conceptually we serialise writes between engines inside the GPU.
505 * We only allow one engine to write into a buffer at any time, but
506 * multiple readers. To ensure each has a coherent view of memory, we must:
507 *
508 * - If there is an outstanding write request to the object, the new
509 * request must wait for it to complete (either CPU or in hw, requests
510 * on the same ring will be naturally ordered).
511 *
512 * - If we are a write request (pending_write_domain is set), the new
513 * request must wait for outstanding read requests to complete.
514 *
515 * Returns 0 if successful, else propagates up the lower layer error.
516 */
517 int
518 i915_gem_request_await_object(struct drm_i915_gem_request *to,
519 struct drm_i915_gem_object *obj,
520 bool write)
521 {
522 struct i915_gem_active *active;
523 unsigned long active_mask;
524 int idx;
525
526 if (write) {
527 active_mask = i915_gem_object_get_active(obj);
528 active = obj->last_read;
529 } else {
530 active_mask = 1;
531 active = &obj->last_write;
532 }
533
534 for_each_active(active_mask, idx) {
535 struct drm_i915_gem_request *request;
536 int ret;
537
538 request = i915_gem_active_peek(&active[idx],
539 &obj->base.dev->struct_mutex);
540 if (!request)
541 continue;
542
543 ret = i915_gem_request_await_request(to, request);
544 if (ret)
545 return ret;
546 }
547
548 return 0;
549 }
550
551 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
552 {
553 struct drm_i915_private *dev_priv = engine->i915;
554
555 dev_priv->gt.active_engines |= intel_engine_flag(engine);
556 if (dev_priv->gt.awake)
557 return;
558
559 intel_runtime_pm_get_noresume(dev_priv);
560 dev_priv->gt.awake = true;
561
562 intel_enable_gt_powersave(dev_priv);
563 i915_update_gfx_val(dev_priv);
564 if (INTEL_GEN(dev_priv) >= 6)
565 gen6_rps_busy(dev_priv);
566
567 queue_delayed_work(dev_priv->wq,
568 &dev_priv->gt.retire_work,
569 round_jiffies_up_relative(HZ));
570 }
571
572 /*
573 * NB: This function is not allowed to fail. Doing so would mean the the
574 * request is not being tracked for completion but the work itself is
575 * going to happen on the hardware. This would be a Bad Thing(tm).
576 */
577 void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
578 {
579 struct intel_engine_cs *engine = request->engine;
580 struct intel_ring *ring = request->ring;
581 struct drm_i915_gem_request *prev;
582 u32 request_start;
583 u32 reserved_tail;
584 int ret;
585
586 trace_i915_gem_request_add(request);
587
588 /*
589 * To ensure that this call will not fail, space for its emissions
590 * should already have been reserved in the ring buffer. Let the ring
591 * know that it is time to use that space up.
592 */
593 request_start = ring->tail;
594 reserved_tail = request->reserved_space;
595 request->reserved_space = 0;
596
597 /*
598 * Emit any outstanding flushes - execbuf can fail to emit the flush
599 * after having emitted the batchbuffer command. Hence we need to fix
600 * things up similar to emitting the lazy request. The difference here
601 * is that the flush _must_ happen before the next request, no matter
602 * what.
603 */
604 if (flush_caches) {
605 ret = engine->emit_flush(request, EMIT_FLUSH);
606
607 /* Not allowed to fail! */
608 WARN(ret, "engine->emit_flush() failed: %d!\n", ret);
609 }
610
611 /* Record the position of the start of the breadcrumb so that
612 * should we detect the updated seqno part-way through the
613 * GPU processing the request, we never over-estimate the
614 * position of the ring's HEAD.
615 */
616 request->postfix = ring->tail;
617
618 /* Not allowed to fail! */
619 ret = engine->emit_request(request);
620 WARN(ret, "(%s)->emit_request failed: %d!\n", engine->name, ret);
621
622 /* Sanity check that the reserved size was large enough. */
623 ret = ring->tail - request_start;
624 if (ret < 0)
625 ret += ring->size;
626 WARN_ONCE(ret > reserved_tail,
627 "Not enough space reserved (%d bytes) "
628 "for adding the request (%d bytes)\n",
629 reserved_tail, ret);
630
631 /* Seal the request and mark it as pending execution. Note that
632 * we may inspect this state, without holding any locks, during
633 * hangcheck. Hence we apply the barrier to ensure that we do not
634 * see a more recent value in the hws than we are tracking.
635 */
636
637 prev = i915_gem_active_raw(&engine->last_request,
638 &request->i915->drm.struct_mutex);
639 if (prev)
640 i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
641 &request->submitq);
642
643 request->emitted_jiffies = jiffies;
644 request->previous_seqno = engine->last_submitted_seqno;
645 engine->last_submitted_seqno = request->fence.seqno;
646 i915_gem_active_set(&engine->last_request, request);
647 list_add_tail(&request->link, &engine->request_list);
648 list_add_tail(&request->ring_link, &ring->request_list);
649
650 i915_gem_mark_busy(engine);
651
652 local_bh_disable();
653 i915_sw_fence_commit(&request->submit);
654 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
655 }
656
657 static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
658 {
659 unsigned long flags;
660
661 spin_lock_irqsave(&q->lock, flags);
662 if (list_empty(&wait->task_list))
663 __add_wait_queue(q, wait);
664 spin_unlock_irqrestore(&q->lock, flags);
665 }
666
667 static unsigned long local_clock_us(unsigned int *cpu)
668 {
669 unsigned long t;
670
671 /* Cheaply and approximately convert from nanoseconds to microseconds.
672 * The result and subsequent calculations are also defined in the same
673 * approximate microseconds units. The principal source of timing
674 * error here is from the simple truncation.
675 *
676 * Note that local_clock() is only defined wrt to the current CPU;
677 * the comparisons are no longer valid if we switch CPUs. Instead of
678 * blocking preemption for the entire busywait, we can detect the CPU
679 * switch and use that as indicator of system load and a reason to
680 * stop busywaiting, see busywait_stop().
681 */
682 *cpu = get_cpu();
683 t = local_clock() >> 10;
684 put_cpu();
685
686 return t;
687 }
688
689 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
690 {
691 unsigned int this_cpu;
692
693 if (time_after(local_clock_us(&this_cpu), timeout))
694 return true;
695
696 return this_cpu != cpu;
697 }
698
699 bool __i915_spin_request(const struct drm_i915_gem_request *req,
700 int state, unsigned long timeout_us)
701 {
702 unsigned int cpu;
703
704 /* When waiting for high frequency requests, e.g. during synchronous
705 * rendering split between the CPU and GPU, the finite amount of time
706 * required to set up the irq and wait upon it limits the response
707 * rate. By busywaiting on the request completion for a short while we
708 * can service the high frequency waits as quick as possible. However,
709 * if it is a slow request, we want to sleep as quickly as possible.
710 * The tradeoff between waiting and sleeping is roughly the time it
711 * takes to sleep on a request, on the order of a microsecond.
712 */
713
714 timeout_us += local_clock_us(&cpu);
715 do {
716 if (i915_gem_request_completed(req))
717 return true;
718
719 if (signal_pending_state(state, current))
720 break;
721
722 if (busywait_stop(timeout_us, cpu))
723 break;
724
725 cpu_relax_lowlatency();
726 } while (!need_resched());
727
728 return false;
729 }
730
731 /**
732 * i915_wait_request - wait until execution of request has finished
733 * @req: duh!
734 * @flags: how to wait
735 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
736 * @rps: client to charge for RPS boosting
737 *
738 * Note: It is of utmost importance that the passed in seqno and reset_counter
739 * values have been read by the caller in an smp safe manner. Where read-side
740 * locks are involved, it is sufficient to read the reset_counter before
741 * unlocking the lock that protects the seqno. For lockless tricks, the
742 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
743 * inserted.
744 *
745 * Returns 0 if the request was found within the alloted time. Else returns the
746 * errno with remaining time filled in timeout argument.
747 */
748 int i915_wait_request(struct drm_i915_gem_request *req,
749 unsigned int flags,
750 s64 *timeout,
751 struct intel_rps_client *rps)
752 {
753 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
754 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
755 DEFINE_WAIT(reset);
756 struct intel_wait wait;
757 unsigned long timeout_remain;
758 int ret = 0;
759
760 might_sleep();
761 #if IS_ENABLED(CONFIG_LOCKDEP)
762 GEM_BUG_ON(!!lockdep_is_held(&req->i915->drm.struct_mutex) !=
763 !!(flags & I915_WAIT_LOCKED));
764 #endif
765
766 if (i915_gem_request_completed(req))
767 return 0;
768
769 timeout_remain = MAX_SCHEDULE_TIMEOUT;
770 if (timeout) {
771 if (WARN_ON(*timeout < 0))
772 return -EINVAL;
773
774 if (*timeout == 0)
775 return -ETIME;
776
777 /* Record current time in case interrupted, or wedged */
778 timeout_remain = nsecs_to_jiffies_timeout(*timeout);
779 *timeout += ktime_get_raw_ns();
780 }
781
782 trace_i915_gem_request_wait_begin(req);
783
784 /* This client is about to stall waiting for the GPU. In many cases
785 * this is undesirable and limits the throughput of the system, as
786 * many clients cannot continue processing user input/output whilst
787 * blocked. RPS autotuning may take tens of milliseconds to respond
788 * to the GPU load and thus incurs additional latency for the client.
789 * We can circumvent that by promoting the GPU frequency to maximum
790 * before we wait. This makes the GPU throttle up much more quickly
791 * (good for benchmarks and user experience, e.g. window animations),
792 * but at a cost of spending more power processing the workload
793 * (bad for battery). Not all clients even want their results
794 * immediately and for them we should just let the GPU select its own
795 * frequency to maximise efficiency. To prevent a single client from
796 * forcing the clocks too high for the whole system, we only allow
797 * each client to waitboost once in a busy period.
798 */
799 if (IS_RPS_CLIENT(rps) && INTEL_GEN(req->i915) >= 6)
800 gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
801
802 /* Optimistic short spin before touching IRQs */
803 if (i915_spin_request(req, state, 5))
804 goto complete;
805
806 set_current_state(state);
807 if (flags & I915_WAIT_LOCKED)
808 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
809
810 intel_wait_init(&wait, req->fence.seqno);
811 if (intel_engine_add_wait(req->engine, &wait))
812 /* In order to check that we haven't missed the interrupt
813 * as we enabled it, we need to kick ourselves to do a
814 * coherent check on the seqno before we sleep.
815 */
816 goto wakeup;
817
818 for (;;) {
819 if (signal_pending_state(state, current)) {
820 ret = -ERESTARTSYS;
821 break;
822 }
823
824 timeout_remain = io_schedule_timeout(timeout_remain);
825 if (timeout_remain == 0) {
826 ret = -ETIME;
827 break;
828 }
829
830 if (intel_wait_complete(&wait))
831 break;
832
833 set_current_state(state);
834
835 wakeup:
836 /* Carefully check if the request is complete, giving time
837 * for the seqno to be visible following the interrupt.
838 * We also have to check in case we are kicked by the GPU
839 * reset in order to drop the struct_mutex.
840 */
841 if (__i915_request_irq_complete(req))
842 break;
843
844 /* If the GPU is hung, and we hold the lock, reset the GPU
845 * and then check for completion. On a full reset, the engine's
846 * HW seqno will be advanced passed us and we are complete.
847 * If we do a partial reset, we have to wait for the GPU to
848 * resume and update the breadcrumb.
849 *
850 * If we don't hold the mutex, we can just wait for the worker
851 * to come along and update the breadcrumb (either directly
852 * itself, or indirectly by recovering the GPU).
853 */
854 if (flags & I915_WAIT_LOCKED &&
855 i915_reset_in_progress(&req->i915->gpu_error)) {
856 __set_current_state(TASK_RUNNING);
857 i915_reset(req->i915);
858 reset_wait_queue(&req->i915->gpu_error.wait_queue,
859 &reset);
860 continue;
861 }
862
863 /* Only spin if we know the GPU is processing this request */
864 if (i915_spin_request(req, state, 2))
865 break;
866 }
867
868 intel_engine_remove_wait(req->engine, &wait);
869 if (flags & I915_WAIT_LOCKED)
870 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
871 __set_current_state(TASK_RUNNING);
872
873 complete:
874 trace_i915_gem_request_wait_end(req);
875
876 if (timeout) {
877 *timeout -= ktime_get_raw_ns();
878 if (*timeout < 0)
879 *timeout = 0;
880
881 /*
882 * Apparently ktime isn't accurate enough and occasionally has a
883 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
884 * things up to make the test happy. We allow up to 1 jiffy.
885 *
886 * This is a regrssion from the timespec->ktime conversion.
887 */
888 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
889 *timeout = 0;
890 }
891
892 if (IS_RPS_USER(rps) &&
893 req->fence.seqno == req->engine->last_submitted_seqno) {
894 /* The GPU is now idle and this client has stalled.
895 * Since no other client has submitted a request in the
896 * meantime, assume that this client is the only one
897 * supplying work to the GPU but is unable to keep that
898 * work supplied because it is waiting. Since the GPU is
899 * then never kept fully busy, RPS autoclocking will
900 * keep the clocks relatively low, causing further delays.
901 * Compensate by giving the synchronous client credit for
902 * a waitboost next time.
903 */
904 spin_lock(&req->i915->rps.client_lock);
905 list_del_init(&rps->link);
906 spin_unlock(&req->i915->rps.client_lock);
907 }
908
909 return ret;
910 }
911
912 static bool engine_retire_requests(struct intel_engine_cs *engine)
913 {
914 struct drm_i915_gem_request *request, *next;
915
916 list_for_each_entry_safe(request, next, &engine->request_list, link) {
917 if (!i915_gem_request_completed(request))
918 return false;
919
920 i915_gem_request_retire(request);
921 }
922
923 return true;
924 }
925
926 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
927 {
928 struct intel_engine_cs *engine;
929 unsigned int tmp;
930
931 lockdep_assert_held(&dev_priv->drm.struct_mutex);
932
933 if (dev_priv->gt.active_engines == 0)
934 return;
935
936 GEM_BUG_ON(!dev_priv->gt.awake);
937
938 for_each_engine_masked(engine, dev_priv, dev_priv->gt.active_engines, tmp)
939 if (engine_retire_requests(engine))
940 dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
941
942 if (dev_priv->gt.active_engines == 0)
943 queue_delayed_work(dev_priv->wq,
944 &dev_priv->gt.idle_work,
945 msecs_to_jiffies(100));
946 }
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