2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
25 #include <linux/circ_buf.h>
27 #include "intel_guc.h"
30 * DOC: GuC-based command submission
33 * We use the term client to avoid confusion with contexts. A i915_guc_client is
34 * equivalent to GuC object guc_context_desc. This context descriptor is
35 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
36 * and workqueue for it. Also the process descriptor (guc_process_desc), which
37 * is mapped to client space. So the client can write Work Item then ring the
40 * To simplify the implementation, we allocate one gem object that contains all
41 * pages for doorbell, process descriptor and workqueue.
43 * The Scratch registers:
44 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
45 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
46 * triggers an interrupt on the GuC via another register write (0xC4C8).
47 * Firmware writes a success/fail code back to the action register after
48 * processes the request. The kernel driver polls waiting for this update and
50 * See host2guc_action()
53 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
54 * mapped into process space.
57 * There are several types of work items that the host may place into a
58 * workqueue, each with its own requirements and limitations. Currently only
59 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
60 * represents in-order queue. The kernel driver packs ring tail pointer and an
61 * ELSP context descriptor dword into Work Item.
62 * See guc_add_workqueue_item()
67 * Read GuC command/status register (SOFT_SCRATCH_0)
68 * Return true if it contains a response rather than a command
70 static inline bool host2guc_action_response(struct drm_i915_private
*dev_priv
,
73 u32 val
= I915_READ(SOFT_SCRATCH(0));
75 return GUC2HOST_IS_RESPONSE(val
);
78 static int host2guc_action(struct intel_guc
*guc
, u32
*data
, u32 len
)
80 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
85 if (WARN_ON(len
< 1 || len
> 15))
88 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
90 dev_priv
->guc
.action_count
+= 1;
91 dev_priv
->guc
.action_cmd
= data
[0];
93 for (i
= 0; i
< len
; i
++)
94 I915_WRITE(SOFT_SCRATCH(i
), data
[i
]);
96 POSTING_READ(SOFT_SCRATCH(i
- 1));
98 I915_WRITE(HOST2GUC_INTERRUPT
, HOST2GUC_TRIGGER
);
101 * Fast commands should complete in less than 10us, so sample quickly
102 * up to that length of time, then switch to a slower sleep-wait loop.
103 * No HOST2GUC command should ever take longer than 10ms.
105 ret
= wait_for_us(host2guc_action_response(dev_priv
, &status
), 10);
107 ret
= wait_for(host2guc_action_response(dev_priv
, &status
), 10);
108 if (status
!= GUC2HOST_STATUS_SUCCESS
) {
110 * Either the GuC explicitly returned an error (which
111 * we convert to -EIO here) or no response at all was
112 * received within the timeout limit (-ETIMEDOUT)
114 if (ret
!= -ETIMEDOUT
)
117 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n",
118 data
[0], ret
, status
, I915_READ(SOFT_SCRATCH(15)));
120 dev_priv
->guc
.action_fail
+= 1;
121 dev_priv
->guc
.action_err
= ret
;
123 dev_priv
->guc
.action_status
= status
;
125 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
131 * Tell the GuC to allocate or deallocate a specific doorbell
134 static int host2guc_allocate_doorbell(struct intel_guc
*guc
,
135 struct i915_guc_client
*client
)
139 data
[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL
;
140 data
[1] = client
->ctx_index
;
142 return host2guc_action(guc
, data
, 2);
145 static int host2guc_release_doorbell(struct intel_guc
*guc
,
146 struct i915_guc_client
*client
)
150 data
[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL
;
151 data
[1] = client
->ctx_index
;
153 return host2guc_action(guc
, data
, 2);
156 static int host2guc_sample_forcewake(struct intel_guc
*guc
,
157 struct i915_guc_client
*client
)
159 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
162 data
[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE
;
163 /* WaRsDisableCoarsePowerGating:skl,bxt */
164 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
167 /* bit 0 and 1 are for Render and Media domain separately */
168 data
[1] = GUC_FORCEWAKE_RENDER
| GUC_FORCEWAKE_MEDIA
;
170 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
174 * Initialise, update, or clear doorbell data shared with the GuC
176 * These functions modify shared data and so need access to the mapped
177 * client object which contains the page being used for the doorbell
180 static int guc_update_doorbell_id(struct intel_guc
*guc
,
181 struct i915_guc_client
*client
,
184 struct sg_table
*sg
= guc
->ctx_pool_vma
->pages
;
185 void *doorbell_bitmap
= guc
->doorbell_bitmap
;
186 struct guc_doorbell_info
*doorbell
;
187 struct guc_context_desc desc
;
190 doorbell
= client
->client_base
+ client
->doorbell_offset
;
192 if (client
->doorbell_id
!= GUC_INVALID_DOORBELL_ID
&&
193 test_bit(client
->doorbell_id
, doorbell_bitmap
)) {
194 /* Deactivate the old doorbell */
195 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
196 (void)host2guc_release_doorbell(guc
, client
);
197 __clear_bit(client
->doorbell_id
, doorbell_bitmap
);
200 /* Update the GuC's idea of the doorbell ID */
201 len
= sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
202 sizeof(desc
) * client
->ctx_index
);
203 if (len
!= sizeof(desc
))
206 len
= sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
207 sizeof(desc
) * client
->ctx_index
);
208 if (len
!= sizeof(desc
))
211 client
->doorbell_id
= new_id
;
212 if (new_id
== GUC_INVALID_DOORBELL_ID
)
215 /* Activate the new doorbell */
216 __set_bit(new_id
, doorbell_bitmap
);
217 doorbell
->cookie
= 0;
218 doorbell
->db_status
= GUC_DOORBELL_ENABLED
;
219 return host2guc_allocate_doorbell(guc
, client
);
222 static int guc_init_doorbell(struct intel_guc
*guc
,
223 struct i915_guc_client
*client
,
226 return guc_update_doorbell_id(guc
, client
, db_id
);
229 static void guc_disable_doorbell(struct intel_guc
*guc
,
230 struct i915_guc_client
*client
)
232 (void)guc_update_doorbell_id(guc
, client
, GUC_INVALID_DOORBELL_ID
);
234 /* XXX: wait for any interrupts */
235 /* XXX: wait for workqueue to drain */
239 select_doorbell_register(struct intel_guc
*guc
, uint32_t priority
)
242 * The bitmap tracks which doorbell registers are currently in use.
243 * It is split into two halves; the first half is used for normal
244 * priority contexts, the second half for high-priority ones.
245 * Note that logically higher priorities are numerically less than
246 * normal ones, so the test below means "is it high-priority?"
248 const bool hi_pri
= (priority
<= GUC_CTX_PRIORITY_HIGH
);
249 const uint16_t half
= GUC_MAX_DOORBELLS
/ 2;
250 const uint16_t start
= hi_pri
? half
: 0;
251 const uint16_t end
= start
+ half
;
254 id
= find_next_zero_bit(guc
->doorbell_bitmap
, end
, start
);
256 id
= GUC_INVALID_DOORBELL_ID
;
258 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
259 hi_pri
? "high" : "normal", id
);
265 * Select, assign and relase doorbell cachelines
267 * These functions track which doorbell cachelines are in use.
268 * The data they manipulate is protected by the host2guc lock.
271 static uint32_t select_doorbell_cacheline(struct intel_guc
*guc
)
273 const uint32_t cacheline_size
= cache_line_size();
276 /* Doorbell uses a single cache line within a page */
277 offset
= offset_in_page(guc
->db_cacheline
);
279 /* Moving to next cache line to reduce contention */
280 guc
->db_cacheline
+= cacheline_size
;
282 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
283 offset
, guc
->db_cacheline
, cacheline_size
);
289 * Initialise the process descriptor shared with the GuC firmware.
291 static void guc_init_proc_desc(struct intel_guc
*guc
,
292 struct i915_guc_client
*client
)
294 struct guc_process_desc
*desc
;
296 desc
= client
->client_base
+ client
->proc_desc_offset
;
298 memset(desc
, 0, sizeof(*desc
));
301 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
302 * space for ring3 clients (set them as in mmap_ioctl) or kernel
303 * space for kernel clients (map on demand instead? May make debug
304 * easier to have it mapped).
306 desc
->wq_base_addr
= 0;
307 desc
->db_base_addr
= 0;
309 desc
->context_id
= client
->ctx_index
;
310 desc
->wq_size_bytes
= client
->wq_size
;
311 desc
->wq_status
= WQ_STATUS_ACTIVE
;
312 desc
->priority
= client
->priority
;
316 * Initialise/clear the context descriptor shared with the GuC firmware.
318 * This descriptor tells the GuC where (in GGTT space) to find the important
319 * data structures relating to this client (doorbell, process descriptor,
323 static void guc_init_ctx_desc(struct intel_guc
*guc
,
324 struct i915_guc_client
*client
)
326 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
327 struct intel_engine_cs
*engine
;
328 struct i915_gem_context
*ctx
= client
->owner
;
329 struct guc_context_desc desc
;
334 memset(&desc
, 0, sizeof(desc
));
336 desc
.attribute
= GUC_CTX_DESC_ATTR_ACTIVE
| GUC_CTX_DESC_ATTR_KERNEL
;
337 desc
.context_id
= client
->ctx_index
;
338 desc
.priority
= client
->priority
;
339 desc
.db_id
= client
->doorbell_id
;
341 for_each_engine_masked(engine
, dev_priv
, client
->engines
, tmp
) {
342 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
343 uint32_t guc_engine_id
= engine
->guc_id
;
344 struct guc_execlist_context
*lrc
= &desc
.lrc
[guc_engine_id
];
346 /* TODO: We have a design issue to be solved here. Only when we
347 * receive the first batch, we know which engine is used by the
348 * user. But here GuC expects the lrc and ring to be pinned. It
349 * is not an issue for default context, which is the only one
350 * for now who owns a GuC client. But for future owner of GuC
351 * client, need to make sure lrc is pinned prior to enter here.
354 break; /* XXX: continue? */
356 lrc
->context_desc
= lower_32_bits(ce
->lrc_desc
);
358 /* The state page is after PPHWSP */
360 i915_ggtt_offset(ce
->state
) + LRC_STATE_PN
* PAGE_SIZE
;
361 lrc
->context_id
= (client
->ctx_index
<< GUC_ELC_CTXID_OFFSET
) |
362 (guc_engine_id
<< GUC_ELC_ENGINE_OFFSET
);
364 lrc
->ring_begin
= i915_ggtt_offset(ce
->ring
->vma
);
365 lrc
->ring_end
= lrc
->ring_begin
+ ce
->ring
->size
- 1;
366 lrc
->ring_next_free_location
= lrc
->ring_begin
;
367 lrc
->ring_current_tail_pointer_value
= 0;
369 desc
.engines_used
|= (1 << guc_engine_id
);
372 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
373 client
->engines
, desc
.engines_used
);
374 WARN_ON(desc
.engines_used
== 0);
377 * The doorbell, process descriptor, and workqueue are all parts
378 * of the client object, which the GuC will reference via the GGTT
380 gfx_addr
= i915_ggtt_offset(client
->vma
);
381 desc
.db_trigger_phy
= sg_dma_address(client
->vma
->pages
->sgl
) +
382 client
->doorbell_offset
;
383 desc
.db_trigger_cpu
= (uintptr_t)client
->client_base
+
384 client
->doorbell_offset
;
385 desc
.db_trigger_uk
= gfx_addr
+ client
->doorbell_offset
;
386 desc
.process_desc
= gfx_addr
+ client
->proc_desc_offset
;
387 desc
.wq_addr
= gfx_addr
+ client
->wq_offset
;
388 desc
.wq_size
= client
->wq_size
;
391 * XXX: Take LRCs from an existing context if this is not an
392 * IsKMDCreatedContext client
394 desc
.desc_private
= (uintptr_t)client
;
396 /* Pool context is pinned already */
397 sg
= guc
->ctx_pool_vma
->pages
;
398 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
399 sizeof(desc
) * client
->ctx_index
);
402 static void guc_fini_ctx_desc(struct intel_guc
*guc
,
403 struct i915_guc_client
*client
)
405 struct guc_context_desc desc
;
408 memset(&desc
, 0, sizeof(desc
));
410 sg
= guc
->ctx_pool_vma
->pages
;
411 sg_pcopy_from_buffer(sg
->sgl
, sg
->nents
, &desc
, sizeof(desc
),
412 sizeof(desc
) * client
->ctx_index
);
416 * i915_guc_wq_check_space() - check that the GuC can accept a request
417 * @request: request associated with the commands
419 * Return: 0 if space is available
420 * -EAGAIN if space is not currently available
422 * This function must be called (and must return 0) before a request
423 * is submitted to the GuC via i915_guc_submit() below. Once a result
424 * of 0 has been returned, it remains valid until (but only until)
425 * the next call to submit().
427 * This precheck allows the caller to determine in advance that space
428 * will be available for the next submission before committing resources
429 * to it, and helps avoid late failures with complicated recovery paths.
431 int i915_guc_wq_check_space(struct drm_i915_gem_request
*request
)
433 const size_t wqi_size
= sizeof(struct guc_wq_item
);
434 struct i915_guc_client
*gc
= request
->i915
->guc
.execbuf_client
;
435 struct guc_process_desc
*desc
= gc
->client_base
+ gc
->proc_desc_offset
;
439 spin_lock(&gc
->wq_lock
);
440 freespace
= CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
);
441 freespace
-= gc
->wq_rsvd
;
442 if (likely(freespace
>= wqi_size
)) {
443 gc
->wq_rsvd
+= wqi_size
;
449 spin_unlock(&gc
->wq_lock
);
454 static void guc_add_workqueue_item(struct i915_guc_client
*gc
,
455 struct drm_i915_gem_request
*rq
)
457 /* wqi_len is in DWords, and does not include the one-word header */
458 const size_t wqi_size
= sizeof(struct guc_wq_item
);
459 const u32 wqi_len
= wqi_size
/sizeof(u32
) - 1;
460 struct intel_engine_cs
*engine
= rq
->engine
;
461 struct guc_process_desc
*desc
;
462 struct guc_wq_item
*wqi
;
464 u32 freespace
, tail
, wq_off
, wq_page
;
466 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
468 /* Free space is guaranteed, see i915_guc_wq_check_space() above */
469 freespace
= CIRC_SPACE(gc
->wq_tail
, desc
->head
, gc
->wq_size
);
470 GEM_BUG_ON(freespace
< wqi_size
);
472 /* The GuC firmware wants the tail index in QWords, not bytes */
474 GEM_BUG_ON(tail
& 7);
476 GEM_BUG_ON(tail
> WQ_RING_TAIL_MAX
);
478 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
479 * should not have the case where structure wqi is across page, neither
480 * wrapped to the beginning. This simplifies the implementation below.
482 * XXX: if not the case, we need save data to a temp wqi and copy it to
483 * workqueue buffer dw by dw.
485 BUILD_BUG_ON(wqi_size
!= 16);
486 GEM_BUG_ON(gc
->wq_rsvd
< wqi_size
);
488 /* postincrement WQ tail for next time */
489 wq_off
= gc
->wq_tail
;
490 GEM_BUG_ON(wq_off
& (wqi_size
- 1));
491 gc
->wq_tail
+= wqi_size
;
492 gc
->wq_tail
&= gc
->wq_size
- 1;
493 gc
->wq_rsvd
-= wqi_size
;
495 /* WQ starts from the page after doorbell / process_desc */
496 wq_page
= (wq_off
+ GUC_DB_SIZE
) >> PAGE_SHIFT
;
497 wq_off
&= PAGE_SIZE
- 1;
498 base
= kmap_atomic(i915_gem_object_get_page(gc
->vma
->obj
, wq_page
));
499 wqi
= (struct guc_wq_item
*)((char *)base
+ wq_off
);
501 /* Now fill in the 4-word work queue item */
502 wqi
->header
= WQ_TYPE_INORDER
|
503 (wqi_len
<< WQ_LEN_SHIFT
) |
504 (engine
->guc_id
<< WQ_TARGET_SHIFT
) |
507 /* The GuC wants only the low-order word of the context descriptor */
508 wqi
->context_desc
= (u32
)intel_lr_context_descriptor(rq
->ctx
, engine
);
510 wqi
->ring_tail
= tail
<< WQ_RING_TAIL_SHIFT
;
511 wqi
->fence_id
= rq
->fence
.seqno
;
516 static int guc_ring_doorbell(struct i915_guc_client
*gc
)
518 struct guc_process_desc
*desc
;
519 union guc_doorbell_qw db_cmp
, db_exc
, db_ret
;
520 union guc_doorbell_qw
*db
;
521 int attempt
= 2, ret
= -EAGAIN
;
523 desc
= gc
->client_base
+ gc
->proc_desc_offset
;
525 /* Update the tail so it is visible to GuC */
526 desc
->tail
= gc
->wq_tail
;
529 db_cmp
.db_status
= GUC_DOORBELL_ENABLED
;
530 db_cmp
.cookie
= gc
->cookie
;
532 /* cookie to be updated */
533 db_exc
.db_status
= GUC_DOORBELL_ENABLED
;
534 db_exc
.cookie
= gc
->cookie
+ 1;
535 if (db_exc
.cookie
== 0)
538 /* pointer of current doorbell cacheline */
539 db
= gc
->client_base
+ gc
->doorbell_offset
;
542 /* lets ring the doorbell */
543 db_ret
.value_qw
= atomic64_cmpxchg((atomic64_t
*)db
,
544 db_cmp
.value_qw
, db_exc
.value_qw
);
546 /* if the exchange was successfully executed */
547 if (db_ret
.value_qw
== db_cmp
.value_qw
) {
548 /* db was successfully rung */
549 gc
->cookie
= db_exc
.cookie
;
554 /* XXX: doorbell was lost and need to acquire it again */
555 if (db_ret
.db_status
== GUC_DOORBELL_DISABLED
)
558 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
559 db_cmp
.cookie
, db_ret
.cookie
);
561 /* update the cookie to newly read cookie from GuC */
562 db_cmp
.cookie
= db_ret
.cookie
;
563 db_exc
.cookie
= db_ret
.cookie
+ 1;
564 if (db_exc
.cookie
== 0)
572 * i915_guc_submit() - Submit commands through GuC
573 * @rq: request associated with the commands
575 * Return: 0 on success, otherwise an errno.
576 * (Note: nonzero really shouldn't happen!)
578 * The caller must have already called i915_guc_wq_check_space() above
579 * with a result of 0 (success) since the last request submission. This
580 * guarantees that there is space in the work queue for the new request,
581 * so enqueuing the item cannot fail.
583 * Bad Things Will Happen if the caller violates this protocol e.g. calls
584 * submit() when check() says there's no space, or calls submit() multiple
585 * times with no intervening check().
587 * The only error here arises if the doorbell hardware isn't functioning
588 * as expected, which really shouln't happen.
590 static void i915_guc_submit(struct drm_i915_gem_request
*rq
)
592 unsigned int engine_id
= rq
->engine
->id
;
593 struct intel_guc
*guc
= &rq
->i915
->guc
;
594 struct i915_guc_client
*client
= guc
->execbuf_client
;
597 spin_lock(&client
->wq_lock
);
598 guc_add_workqueue_item(client
, rq
);
599 b_ret
= guc_ring_doorbell(client
);
601 client
->submissions
[engine_id
] += 1;
602 client
->retcode
= b_ret
;
606 guc
->submissions
[engine_id
] += 1;
607 guc
->last_seqno
[engine_id
] = rq
->fence
.seqno
;
608 spin_unlock(&client
->wq_lock
);
612 * Everything below here is concerned with setup & teardown, and is
613 * therefore not part of the somewhat time-critical batch-submission
614 * path of i915_guc_submit() above.
618 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
620 * @size: size of area to allocate (both virtual space and memory)
622 * This is a wrapper to create an object for use with the GuC. In order to
623 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
624 * both some backing storage and a range inside the Global GTT. We must pin
625 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
626 * range is reserved inside GuC.
628 * Return: A i915_vma if successful, otherwise an ERR_PTR.
630 static struct i915_vma
*guc_allocate_vma(struct intel_guc
*guc
, u32 size
)
632 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
633 struct drm_i915_gem_object
*obj
;
634 struct i915_vma
*vma
;
637 obj
= i915_gem_object_create(&dev_priv
->drm
, size
);
639 return ERR_CAST(obj
);
641 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
645 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
,
646 PIN_GLOBAL
| PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
652 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
653 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
658 i915_gem_object_put(obj
);
663 guc_client_free(struct drm_i915_private
*dev_priv
,
664 struct i915_guc_client
*client
)
666 struct intel_guc
*guc
= &dev_priv
->guc
;
672 * XXX: wait for any outstanding submissions before freeing memory.
673 * Be sure to drop any locks
676 if (client
->client_base
) {
678 * If we got as far as setting up a doorbell, make sure we
679 * shut it down before unmapping & deallocating the memory.
681 guc_disable_doorbell(guc
, client
);
683 kunmap(kmap_to_page(client
->client_base
));
686 i915_vma_unpin_and_release(&client
->vma
);
688 if (client
->ctx_index
!= GUC_INVALID_CTX_ID
) {
689 guc_fini_ctx_desc(guc
, client
);
690 ida_simple_remove(&guc
->ctx_ids
, client
->ctx_index
);
696 /* Check that a doorbell register is in the expected state */
697 static bool guc_doorbell_check(struct intel_guc
*guc
, uint16_t db_id
)
699 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
700 i915_reg_t drbreg
= GEN8_DRBREGL(db_id
);
701 uint32_t value
= I915_READ(drbreg
);
702 bool enabled
= (value
& GUC_DOORBELL_ENABLED
) != 0;
703 bool expected
= test_bit(db_id
, guc
->doorbell_bitmap
);
705 if (enabled
== expected
)
708 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
709 db_id
, drbreg
.reg
, value
,
710 expected
? "active" : "inactive");
716 * Borrow the first client to set up & tear down each unused doorbell
717 * in turn, to ensure that all doorbell h/w is (re)initialised.
719 static void guc_init_doorbell_hw(struct intel_guc
*guc
)
721 struct i915_guc_client
*client
= guc
->execbuf_client
;
725 /* Save client's original doorbell selection */
726 db_id
= client
->doorbell_id
;
728 for (i
= 0; i
< GUC_MAX_DOORBELLS
; ++i
) {
729 /* Skip if doorbell is OK */
730 if (guc_doorbell_check(guc
, i
))
733 err
= guc_update_doorbell_id(guc
, client
, i
);
735 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
739 /* Restore to original value */
740 err
= guc_update_doorbell_id(guc
, client
, db_id
);
742 DRM_WARN("Failed to restore doorbell to %d, err %d\n",
745 /* Read back & verify all doorbell registers */
746 for (i
= 0; i
< GUC_MAX_DOORBELLS
; ++i
)
747 (void)guc_doorbell_check(guc
, i
);
751 * guc_client_alloc() - Allocate an i915_guc_client
752 * @dev_priv: driver private data structure
753 * @engines: The set of engines to enable for this client
754 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
755 * The kernel client to replace ExecList submission is created with
756 * NORMAL priority. Priority of a client for scheduler can be HIGH,
757 * while a preemption context can use CRITICAL.
758 * @ctx: the context that owns the client (we use the default render
761 * Return: An i915_guc_client object if success, else NULL.
763 static struct i915_guc_client
*
764 guc_client_alloc(struct drm_i915_private
*dev_priv
,
767 struct i915_gem_context
*ctx
)
769 struct i915_guc_client
*client
;
770 struct intel_guc
*guc
= &dev_priv
->guc
;
771 struct i915_vma
*vma
;
774 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
780 client
->engines
= engines
;
781 client
->priority
= priority
;
782 client
->doorbell_id
= GUC_INVALID_DOORBELL_ID
;
784 client
->ctx_index
= (uint32_t)ida_simple_get(&guc
->ctx_ids
, 0,
785 GUC_MAX_GPU_CONTEXTS
, GFP_KERNEL
);
786 if (client
->ctx_index
>= GUC_MAX_GPU_CONTEXTS
) {
787 client
->ctx_index
= GUC_INVALID_CTX_ID
;
791 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
792 vma
= guc_allocate_vma(guc
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
796 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
798 client
->client_base
= kmap(i915_vma_first_page(vma
));
800 spin_lock_init(&client
->wq_lock
);
801 client
->wq_offset
= GUC_DB_SIZE
;
802 client
->wq_size
= GUC_WQ_SIZE
;
804 db_id
= select_doorbell_register(guc
, client
->priority
);
805 if (db_id
== GUC_INVALID_DOORBELL_ID
)
806 /* XXX: evict a doorbell instead? */
809 client
->doorbell_offset
= select_doorbell_cacheline(guc
);
812 * Since the doorbell only requires a single cacheline, we can save
813 * space by putting the application process descriptor in the same
814 * page. Use the half of the page that doesn't include the doorbell.
816 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
817 client
->proc_desc_offset
= 0;
819 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
821 guc_init_proc_desc(guc
, client
);
822 guc_init_ctx_desc(guc
, client
);
823 if (guc_init_doorbell(guc
, client
, db_id
))
826 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
827 priority
, client
, client
->engines
, client
->ctx_index
);
828 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
829 client
->doorbell_id
, client
->doorbell_offset
);
834 guc_client_free(dev_priv
, client
);
838 static void guc_create_log(struct intel_guc
*guc
)
840 struct i915_vma
*vma
;
841 unsigned long offset
;
842 uint32_t size
, flags
;
844 if (i915
.guc_log_level
< GUC_LOG_VERBOSITY_MIN
)
847 if (i915
.guc_log_level
> GUC_LOG_VERBOSITY_MAX
)
848 i915
.guc_log_level
= GUC_LOG_VERBOSITY_MAX
;
850 /* The first page is to save log buffer state. Allocate one
851 * extra page for others in case for overlap */
852 size
= (1 + GUC_LOG_DPC_PAGES
+ 1 +
853 GUC_LOG_ISR_PAGES
+ 1 +
854 GUC_LOG_CRASH_PAGES
+ 1) << PAGE_SHIFT
;
858 vma
= guc_allocate_vma(guc
, size
);
860 /* logging will be off */
861 i915
.guc_log_level
= -1;
868 /* each allocated unit is a page */
869 flags
= GUC_LOG_VALID
| GUC_LOG_NOTIFY_ON_HALF_FULL
|
870 (GUC_LOG_DPC_PAGES
<< GUC_LOG_DPC_SHIFT
) |
871 (GUC_LOG_ISR_PAGES
<< GUC_LOG_ISR_SHIFT
) |
872 (GUC_LOG_CRASH_PAGES
<< GUC_LOG_CRASH_SHIFT
);
874 offset
= i915_ggtt_offset(vma
) >> PAGE_SHIFT
; /* in pages */
875 guc
->log_flags
= (offset
<< GUC_LOG_BUF_ADDR_SHIFT
) | flags
;
878 static void init_guc_policies(struct guc_policies
*policies
)
880 struct guc_policy
*policy
;
883 policies
->dpc_promote_time
= 500000;
884 policies
->max_num_work_items
= POLICY_MAX_NUM_WI
;
886 for (p
= 0; p
< GUC_CTX_PRIORITY_NUM
; p
++) {
887 for (i
= GUC_RENDER_ENGINE
; i
< GUC_MAX_ENGINES_NUM
; i
++) {
888 policy
= &policies
->policy
[p
][i
];
890 policy
->execution_quantum
= 1000000;
891 policy
->preemption_time
= 500000;
892 policy
->fault_time
= 250000;
893 policy
->policy_flags
= 0;
897 policies
->is_valid
= 1;
900 static void guc_create_ads(struct intel_guc
*guc
)
902 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
903 struct i915_vma
*vma
;
905 struct guc_policies
*policies
;
906 struct guc_mmio_reg_state
*reg_state
;
907 struct intel_engine_cs
*engine
;
911 /* The ads obj includes the struct itself and buffers passed to GuC */
912 size
= sizeof(struct guc_ads
) + sizeof(struct guc_policies
) +
913 sizeof(struct guc_mmio_reg_state
) +
914 GUC_S3_SAVE_SPACE_PAGES
* PAGE_SIZE
;
918 vma
= guc_allocate_vma(guc
, PAGE_ALIGN(size
));
925 page
= i915_vma_first_page(vma
);
929 * The GuC requires a "Golden Context" when it reinitialises
930 * engines after a reset. Here we use the Render ring default
931 * context, which must already exist and be pinned in the GGTT,
932 * so its address won't change after we've told the GuC where
935 engine
= &dev_priv
->engine
[RCS
];
936 ads
->golden_context_lrca
= engine
->status_page
.ggtt_offset
;
938 for_each_engine(engine
, dev_priv
)
939 ads
->eng_state_size
[engine
->guc_id
] = intel_lr_context_size(engine
);
941 /* GuC scheduling policies */
942 policies
= (void *)ads
+ sizeof(struct guc_ads
);
943 init_guc_policies(policies
);
945 ads
->scheduler_policies
=
946 i915_ggtt_offset(vma
) + sizeof(struct guc_ads
);
949 reg_state
= (void *)policies
+ sizeof(struct guc_policies
);
951 for_each_engine(engine
, dev_priv
) {
952 reg_state
->mmio_white_list
[engine
->guc_id
].mmio_start
=
953 engine
->mmio_base
+ GUC_MMIO_WHITE_LIST_START
;
955 /* Nothing to be saved or restored for now. */
956 reg_state
->mmio_white_list
[engine
->guc_id
].count
= 0;
959 ads
->reg_state_addr
= ads
->scheduler_policies
+
960 sizeof(struct guc_policies
);
962 ads
->reg_state_buffer
= ads
->reg_state_addr
+
963 sizeof(struct guc_mmio_reg_state
);
969 * Set up the memory resources to be shared with the GuC. At this point,
970 * we require just one object that can be mapped through the GGTT.
972 int i915_guc_submission_init(struct drm_i915_private
*dev_priv
)
974 struct intel_guc
*guc
= &dev_priv
->guc
;
975 struct i915_vma
*vma
;
978 /* Wipe bitmap & delete client in case of reinitialisation */
979 bitmap_clear(guc
->doorbell_bitmap
, 0, GUC_MAX_DOORBELLS
);
980 i915_guc_submission_disable(dev_priv
);
982 if (!i915
.enable_guc_submission
)
983 return 0; /* not enabled */
985 if (guc
->ctx_pool_vma
)
986 return 0; /* already allocated */
988 size
= PAGE_ALIGN(GUC_MAX_GPU_CONTEXTS
*sizeof(struct guc_context_desc
));
989 vma
= guc_allocate_vma(guc
, size
);
993 guc
->ctx_pool_vma
= vma
;
994 ida_init(&guc
->ctx_ids
);
1001 int i915_guc_submission_enable(struct drm_i915_private
*dev_priv
)
1003 struct intel_guc
*guc
= &dev_priv
->guc
;
1004 struct i915_guc_client
*client
;
1005 struct intel_engine_cs
*engine
;
1006 struct drm_i915_gem_request
*request
;
1008 /* client for execbuf submission */
1009 client
= guc_client_alloc(dev_priv
,
1010 INTEL_INFO(dev_priv
)->ring_mask
,
1011 GUC_CTX_PRIORITY_KMD_NORMAL
,
1012 dev_priv
->kernel_context
);
1014 DRM_ERROR("Failed to create normal GuC client!\n");
1018 guc
->execbuf_client
= client
;
1019 host2guc_sample_forcewake(guc
, client
);
1020 guc_init_doorbell_hw(guc
);
1022 /* Take over from manual control of ELSP (execlists) */
1023 for_each_engine(engine
, dev_priv
) {
1024 engine
->submit_request
= i915_guc_submit
;
1026 /* Replay the current set of previously submitted requests */
1027 list_for_each_entry(request
, &engine
->request_list
, link
) {
1028 client
->wq_rsvd
+= sizeof(struct guc_wq_item
);
1029 if (i915_sw_fence_done(&request
->submit
))
1030 i915_guc_submit(request
);
1037 void i915_guc_submission_disable(struct drm_i915_private
*dev_priv
)
1039 struct intel_guc
*guc
= &dev_priv
->guc
;
1041 if (!guc
->execbuf_client
)
1044 /* Revert back to manual ELSP submission */
1045 intel_execlists_enable_submission(dev_priv
);
1047 guc_client_free(dev_priv
, guc
->execbuf_client
);
1048 guc
->execbuf_client
= NULL
;
1051 void i915_guc_submission_fini(struct drm_i915_private
*dev_priv
)
1053 struct intel_guc
*guc
= &dev_priv
->guc
;
1055 i915_vma_unpin_and_release(&guc
->ads_vma
);
1056 i915_vma_unpin_and_release(&guc
->log_vma
);
1058 if (guc
->ctx_pool_vma
)
1059 ida_destroy(&guc
->ctx_ids
);
1060 i915_vma_unpin_and_release(&guc
->ctx_pool_vma
);
1064 * intel_guc_suspend() - notify GuC entering suspend state
1067 int intel_guc_suspend(struct drm_device
*dev
)
1069 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1070 struct intel_guc
*guc
= &dev_priv
->guc
;
1071 struct i915_gem_context
*ctx
;
1074 if (guc
->guc_fw
.guc_fw_load_status
!= GUC_FIRMWARE_SUCCESS
)
1077 ctx
= dev_priv
->kernel_context
;
1079 data
[0] = HOST2GUC_ACTION_ENTER_S_STATE
;
1080 /* any value greater than GUC_POWER_D0 */
1081 data
[1] = GUC_POWER_D1
;
1082 /* first page is shared data with GuC */
1083 data
[2] = i915_ggtt_offset(ctx
->engine
[RCS
].state
);
1085 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));
1090 * intel_guc_resume() - notify GuC resuming from suspend state
1093 int intel_guc_resume(struct drm_device
*dev
)
1095 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1096 struct intel_guc
*guc
= &dev_priv
->guc
;
1097 struct i915_gem_context
*ctx
;
1100 if (guc
->guc_fw
.guc_fw_load_status
!= GUC_FIRMWARE_SUCCESS
)
1103 ctx
= dev_priv
->kernel_context
;
1105 data
[0] = HOST2GUC_ACTION_EXIT_S_STATE
;
1106 data
[1] = GUC_POWER_D0
;
1107 /* first page is shared data with GuC */
1108 data
[2] = i915_ggtt_offset(ctx
->engine
[RCS
].state
);
1110 return host2guc_action(guc
, data
, ARRAY_SIZE(data
));