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drm/i915: Make queueing the hangcheck work inline
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50 };
51
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54 };
55
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58 };
59
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66 };
67
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74 };
75
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82 };
83
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91 };
92
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100 };
101
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109 };
110
111 /* BXT hpd list */
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116 };
117
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127 } while (0)
128
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
137 } while (0)
138
139 /*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143 i915_reg_t reg)
144 {
145 u32 val = I915_READ(reg);
146
147 if (val == 0)
148 return;
149
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
153 POSTING_READ(reg);
154 I915_WRITE(reg, 0xffffffff);
155 POSTING_READ(reg);
156 }
157
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
163 } while (0)
164
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
170 } while (0)
171
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173
174 /* For display hotplug interrupt */
175 static inline void
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
177 uint32_t mask,
178 uint32_t bits)
179 {
180 uint32_t val;
181
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
184
185 val = I915_READ(PORT_HOTPLUG_EN);
186 val &= ~mask;
187 val |= bits;
188 I915_WRITE(PORT_HOTPLUG_EN, val);
189 }
190
191 /**
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
202 */
203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
204 uint32_t mask,
205 uint32_t bits)
206 {
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
210 }
211
212 /**
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
217 */
218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
221 {
222 uint32_t new_val;
223
224 assert_spin_locked(&dev_priv->irq_lock);
225
226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
227
228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
229 return;
230
231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
234
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
237 I915_WRITE(DEIMR, dev_priv->irq_mask);
238 POSTING_READ(DEIMR);
239 }
240 }
241
242 /**
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
247 */
248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
251 {
252 assert_spin_locked(&dev_priv->irq_lock);
253
254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
255
256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
257 return;
258
259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262 POSTING_READ(GTIMR);
263 }
264
265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266 {
267 ilk_update_gt_irq(dev_priv, mask, mask);
268 }
269
270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
271 {
272 ilk_update_gt_irq(dev_priv, mask, 0);
273 }
274
275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
276 {
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
278 }
279
280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
281 {
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
283 }
284
285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
286 {
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
288 }
289
290 /**
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
295 */
296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
299 {
300 uint32_t new_val;
301
302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
303
304 assert_spin_locked(&dev_priv->irq_lock);
305
306 new_val = dev_priv->pm_irq_mask;
307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
309
310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
314 }
315 }
316
317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
318 {
319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
320 return;
321
322 snb_update_pm_irq(dev_priv, mask, mask);
323 }
324
325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
326 uint32_t mask)
327 {
328 snb_update_pm_irq(dev_priv, mask, 0);
329 }
330
331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
332 {
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334 return;
335
336 __gen6_disable_pm_irq(dev_priv, mask);
337 }
338
339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
340 {
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
342
343 spin_lock_irq(&dev_priv->irq_lock);
344 I915_WRITE(reg, dev_priv->pm_rps_events);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
346 POSTING_READ(reg);
347 dev_priv->rps.pm_iir = 0;
348 spin_unlock_irq(&dev_priv->irq_lock);
349 }
350
351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
352 {
353 spin_lock_irq(&dev_priv->irq_lock);
354
355 WARN_ON(dev_priv->rps.pm_iir);
356 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
357 dev_priv->rps.interrupts_enabled = true;
358 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
359 dev_priv->pm_rps_events);
360 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
361
362 spin_unlock_irq(&dev_priv->irq_lock);
363 }
364
365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
366 {
367 return (mask & ~dev_priv->rps.pm_intr_keep);
368 }
369
370 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
371 {
372 spin_lock_irq(&dev_priv->irq_lock);
373 dev_priv->rps.interrupts_enabled = false;
374 spin_unlock_irq(&dev_priv->irq_lock);
375
376 cancel_work_sync(&dev_priv->rps.work);
377
378 spin_lock_irq(&dev_priv->irq_lock);
379
380 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
381
382 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
383 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
384 ~dev_priv->pm_rps_events);
385
386 spin_unlock_irq(&dev_priv->irq_lock);
387
388 synchronize_irq(dev_priv->dev->irq);
389 }
390
391 /**
392 * bdw_update_port_irq - update DE port interrupt
393 * @dev_priv: driver private
394 * @interrupt_mask: mask of interrupt bits to update
395 * @enabled_irq_mask: mask of interrupt bits to enable
396 */
397 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
398 uint32_t interrupt_mask,
399 uint32_t enabled_irq_mask)
400 {
401 uint32_t new_val;
402 uint32_t old_val;
403
404 assert_spin_locked(&dev_priv->irq_lock);
405
406 WARN_ON(enabled_irq_mask & ~interrupt_mask);
407
408 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
409 return;
410
411 old_val = I915_READ(GEN8_DE_PORT_IMR);
412
413 new_val = old_val;
414 new_val &= ~interrupt_mask;
415 new_val |= (~enabled_irq_mask & interrupt_mask);
416
417 if (new_val != old_val) {
418 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
419 POSTING_READ(GEN8_DE_PORT_IMR);
420 }
421 }
422
423 /**
424 * bdw_update_pipe_irq - update DE pipe interrupt
425 * @dev_priv: driver private
426 * @pipe: pipe whose interrupt to update
427 * @interrupt_mask: mask of interrupt bits to update
428 * @enabled_irq_mask: mask of interrupt bits to enable
429 */
430 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
431 enum pipe pipe,
432 uint32_t interrupt_mask,
433 uint32_t enabled_irq_mask)
434 {
435 uint32_t new_val;
436
437 assert_spin_locked(&dev_priv->irq_lock);
438
439 WARN_ON(enabled_irq_mask & ~interrupt_mask);
440
441 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
442 return;
443
444 new_val = dev_priv->de_irq_mask[pipe];
445 new_val &= ~interrupt_mask;
446 new_val |= (~enabled_irq_mask & interrupt_mask);
447
448 if (new_val != dev_priv->de_irq_mask[pipe]) {
449 dev_priv->de_irq_mask[pipe] = new_val;
450 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
451 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
452 }
453 }
454
455 /**
456 * ibx_display_interrupt_update - update SDEIMR
457 * @dev_priv: driver private
458 * @interrupt_mask: mask of interrupt bits to update
459 * @enabled_irq_mask: mask of interrupt bits to enable
460 */
461 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
462 uint32_t interrupt_mask,
463 uint32_t enabled_irq_mask)
464 {
465 uint32_t sdeimr = I915_READ(SDEIMR);
466 sdeimr &= ~interrupt_mask;
467 sdeimr |= (~enabled_irq_mask & interrupt_mask);
468
469 WARN_ON(enabled_irq_mask & ~interrupt_mask);
470
471 assert_spin_locked(&dev_priv->irq_lock);
472
473 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
474 return;
475
476 I915_WRITE(SDEIMR, sdeimr);
477 POSTING_READ(SDEIMR);
478 }
479
480 static void
481 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
482 u32 enable_mask, u32 status_mask)
483 {
484 i915_reg_t reg = PIPESTAT(pipe);
485 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
486
487 assert_spin_locked(&dev_priv->irq_lock);
488 WARN_ON(!intel_irqs_enabled(dev_priv));
489
490 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
491 status_mask & ~PIPESTAT_INT_STATUS_MASK,
492 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
493 pipe_name(pipe), enable_mask, status_mask))
494 return;
495
496 if ((pipestat & enable_mask) == enable_mask)
497 return;
498
499 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
500
501 /* Enable the interrupt, clear any pending status */
502 pipestat |= enable_mask | status_mask;
503 I915_WRITE(reg, pipestat);
504 POSTING_READ(reg);
505 }
506
507 static void
508 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
509 u32 enable_mask, u32 status_mask)
510 {
511 i915_reg_t reg = PIPESTAT(pipe);
512 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
513
514 assert_spin_locked(&dev_priv->irq_lock);
515 WARN_ON(!intel_irqs_enabled(dev_priv));
516
517 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
518 status_mask & ~PIPESTAT_INT_STATUS_MASK,
519 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
520 pipe_name(pipe), enable_mask, status_mask))
521 return;
522
523 if ((pipestat & enable_mask) == 0)
524 return;
525
526 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
527
528 pipestat &= ~enable_mask;
529 I915_WRITE(reg, pipestat);
530 POSTING_READ(reg);
531 }
532
533 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
534 {
535 u32 enable_mask = status_mask << 16;
536
537 /*
538 * On pipe A we don't support the PSR interrupt yet,
539 * on pipe B and C the same bit MBZ.
540 */
541 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
542 return 0;
543 /*
544 * On pipe B and C we don't support the PSR interrupt yet, on pipe
545 * A the same bit is for perf counters which we don't use either.
546 */
547 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
548 return 0;
549
550 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
551 SPRITE0_FLIP_DONE_INT_EN_VLV |
552 SPRITE1_FLIP_DONE_INT_EN_VLV);
553 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
554 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
555 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
556 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
557
558 return enable_mask;
559 }
560
561 void
562 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
563 u32 status_mask)
564 {
565 u32 enable_mask;
566
567 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
568 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
569 status_mask);
570 else
571 enable_mask = status_mask << 16;
572 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
573 }
574
575 void
576 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
577 u32 status_mask)
578 {
579 u32 enable_mask;
580
581 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
582 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
583 status_mask);
584 else
585 enable_mask = status_mask << 16;
586 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
587 }
588
589 /**
590 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
591 * @dev_priv: i915 device private
592 */
593 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
594 {
595 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
596 return;
597
598 spin_lock_irq(&dev_priv->irq_lock);
599
600 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
601 if (INTEL_GEN(dev_priv) >= 4)
602 i915_enable_pipestat(dev_priv, PIPE_A,
603 PIPE_LEGACY_BLC_EVENT_STATUS);
604
605 spin_unlock_irq(&dev_priv->irq_lock);
606 }
607
608 /*
609 * This timing diagram depicts the video signal in and
610 * around the vertical blanking period.
611 *
612 * Assumptions about the fictitious mode used in this example:
613 * vblank_start >= 3
614 * vsync_start = vblank_start + 1
615 * vsync_end = vblank_start + 2
616 * vtotal = vblank_start + 3
617 *
618 * start of vblank:
619 * latch double buffered registers
620 * increment frame counter (ctg+)
621 * generate start of vblank interrupt (gen4+)
622 * |
623 * | frame start:
624 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
625 * | may be shifted forward 1-3 extra lines via PIPECONF
626 * | |
627 * | | start of vsync:
628 * | | generate vsync interrupt
629 * | | |
630 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
631 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
632 * ----va---> <-----------------vb--------------------> <--------va-------------
633 * | | <----vs-----> |
634 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
635 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
636 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
637 * | | |
638 * last visible pixel first visible pixel
639 * | increment frame counter (gen3/4)
640 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
641 *
642 * x = horizontal active
643 * _ = horizontal blanking
644 * hs = horizontal sync
645 * va = vertical active
646 * vb = vertical blanking
647 * vs = vertical sync
648 * vbs = vblank_start (number)
649 *
650 * Summary:
651 * - most events happen at the start of horizontal sync
652 * - frame start happens at the start of horizontal blank, 1-4 lines
653 * (depending on PIPECONF settings) after the start of vblank
654 * - gen3/4 pixel and frame counter are synchronized with the start
655 * of horizontal active on the first line of vertical active
656 */
657
658 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
659 {
660 /* Gen2 doesn't have a hardware frame counter */
661 return 0;
662 }
663
664 /* Called from drm generic code, passed a 'crtc', which
665 * we use as a pipe index
666 */
667 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
668 {
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 i915_reg_t high_frame, low_frame;
671 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
672 struct intel_crtc *intel_crtc =
673 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
674 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
675
676 htotal = mode->crtc_htotal;
677 hsync_start = mode->crtc_hsync_start;
678 vbl_start = mode->crtc_vblank_start;
679 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
680 vbl_start = DIV_ROUND_UP(vbl_start, 2);
681
682 /* Convert to pixel count */
683 vbl_start *= htotal;
684
685 /* Start of vblank event occurs at start of hsync */
686 vbl_start -= htotal - hsync_start;
687
688 high_frame = PIPEFRAME(pipe);
689 low_frame = PIPEFRAMEPIXEL(pipe);
690
691 /*
692 * High & low register fields aren't synchronized, so make sure
693 * we get a low value that's stable across two reads of the high
694 * register.
695 */
696 do {
697 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
698 low = I915_READ(low_frame);
699 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
700 } while (high1 != high2);
701
702 high1 >>= PIPE_FRAME_HIGH_SHIFT;
703 pixel = low & PIPE_PIXEL_MASK;
704 low >>= PIPE_FRAME_LOW_SHIFT;
705
706 /*
707 * The frame counter increments at beginning of active.
708 * Cook up a vblank counter by also checking the pixel
709 * counter against vblank start.
710 */
711 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
712 }
713
714 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
715 {
716 struct drm_i915_private *dev_priv = dev->dev_private;
717
718 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
719 }
720
721 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
722 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
723 {
724 struct drm_device *dev = crtc->base.dev;
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 const struct drm_display_mode *mode = &crtc->base.hwmode;
727 enum pipe pipe = crtc->pipe;
728 int position, vtotal;
729
730 vtotal = mode->crtc_vtotal;
731 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
732 vtotal /= 2;
733
734 if (IS_GEN2(dev_priv))
735 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
736 else
737 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
738
739 /*
740 * On HSW, the DSL reg (0x70000) appears to return 0 if we
741 * read it just before the start of vblank. So try it again
742 * so we don't accidentally end up spanning a vblank frame
743 * increment, causing the pipe_update_end() code to squak at us.
744 *
745 * The nature of this problem means we can't simply check the ISR
746 * bit and return the vblank start value; nor can we use the scanline
747 * debug register in the transcoder as it appears to have the same
748 * problem. We may need to extend this to include other platforms,
749 * but so far testing only shows the problem on HSW.
750 */
751 if (HAS_DDI(dev_priv) && !position) {
752 int i, temp;
753
754 for (i = 0; i < 100; i++) {
755 udelay(1);
756 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
757 DSL_LINEMASK_GEN3;
758 if (temp != position) {
759 position = temp;
760 break;
761 }
762 }
763 }
764
765 /*
766 * See update_scanline_offset() for the details on the
767 * scanline_offset adjustment.
768 */
769 return (position + crtc->scanline_offset) % vtotal;
770 }
771
772 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
773 unsigned int flags, int *vpos, int *hpos,
774 ktime_t *stime, ktime_t *etime,
775 const struct drm_display_mode *mode)
776 {
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
780 int position;
781 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
782 bool in_vbl = true;
783 int ret = 0;
784 unsigned long irqflags;
785
786 if (WARN_ON(!mode->crtc_clock)) {
787 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
788 "pipe %c\n", pipe_name(pipe));
789 return 0;
790 }
791
792 htotal = mode->crtc_htotal;
793 hsync_start = mode->crtc_hsync_start;
794 vtotal = mode->crtc_vtotal;
795 vbl_start = mode->crtc_vblank_start;
796 vbl_end = mode->crtc_vblank_end;
797
798 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
799 vbl_start = DIV_ROUND_UP(vbl_start, 2);
800 vbl_end /= 2;
801 vtotal /= 2;
802 }
803
804 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
805
806 /*
807 * Lock uncore.lock, as we will do multiple timing critical raw
808 * register reads, potentially with preemption disabled, so the
809 * following code must not block on uncore.lock.
810 */
811 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
812
813 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
814
815 /* Get optional system timestamp before query. */
816 if (stime)
817 *stime = ktime_get();
818
819 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
820 /* No obvious pixelcount register. Only query vertical
821 * scanout position from Display scan line register.
822 */
823 position = __intel_get_crtc_scanline(intel_crtc);
824 } else {
825 /* Have access to pixelcount since start of frame.
826 * We can split this into vertical and horizontal
827 * scanout position.
828 */
829 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
830
831 /* convert to pixel counts */
832 vbl_start *= htotal;
833 vbl_end *= htotal;
834 vtotal *= htotal;
835
836 /*
837 * In interlaced modes, the pixel counter counts all pixels,
838 * so one field will have htotal more pixels. In order to avoid
839 * the reported position from jumping backwards when the pixel
840 * counter is beyond the length of the shorter field, just
841 * clamp the position the length of the shorter field. This
842 * matches how the scanline counter based position works since
843 * the scanline counter doesn't count the two half lines.
844 */
845 if (position >= vtotal)
846 position = vtotal - 1;
847
848 /*
849 * Start of vblank interrupt is triggered at start of hsync,
850 * just prior to the first active line of vblank. However we
851 * consider lines to start at the leading edge of horizontal
852 * active. So, should we get here before we've crossed into
853 * the horizontal active of the first line in vblank, we would
854 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
855 * always add htotal-hsync_start to the current pixel position.
856 */
857 position = (position + htotal - hsync_start) % vtotal;
858 }
859
860 /* Get optional system timestamp after query. */
861 if (etime)
862 *etime = ktime_get();
863
864 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
865
866 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
867
868 in_vbl = position >= vbl_start && position < vbl_end;
869
870 /*
871 * While in vblank, position will be negative
872 * counting up towards 0 at vbl_end. And outside
873 * vblank, position will be positive counting
874 * up since vbl_end.
875 */
876 if (position >= vbl_start)
877 position -= vbl_end;
878 else
879 position += vtotal - vbl_end;
880
881 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
882 *vpos = position;
883 *hpos = 0;
884 } else {
885 *vpos = position / htotal;
886 *hpos = position - (*vpos * htotal);
887 }
888
889 /* In vblank? */
890 if (in_vbl)
891 ret |= DRM_SCANOUTPOS_IN_VBLANK;
892
893 return ret;
894 }
895
896 int intel_get_crtc_scanline(struct intel_crtc *crtc)
897 {
898 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
899 unsigned long irqflags;
900 int position;
901
902 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
903 position = __intel_get_crtc_scanline(crtc);
904 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
905
906 return position;
907 }
908
909 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
910 int *max_error,
911 struct timeval *vblank_time,
912 unsigned flags)
913 {
914 struct drm_crtc *crtc;
915
916 if (pipe >= INTEL_INFO(dev)->num_pipes) {
917 DRM_ERROR("Invalid crtc %u\n", pipe);
918 return -EINVAL;
919 }
920
921 /* Get drm_crtc to timestamp: */
922 crtc = intel_get_crtc_for_pipe(dev, pipe);
923 if (crtc == NULL) {
924 DRM_ERROR("Invalid crtc %u\n", pipe);
925 return -EINVAL;
926 }
927
928 if (!crtc->hwmode.crtc_clock) {
929 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
930 return -EBUSY;
931 }
932
933 /* Helper routine in DRM core does all the work: */
934 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
935 vblank_time, flags,
936 &crtc->hwmode);
937 }
938
939 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
940 {
941 u32 busy_up, busy_down, max_avg, min_avg;
942 u8 new_delay;
943
944 spin_lock(&mchdev_lock);
945
946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947
948 new_delay = dev_priv->ips.cur_delay;
949
950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
955
956 /* Handle RCS change request from hw */
957 if (busy_up > max_avg) {
958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
962 } else if (busy_down < min_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
967 }
968
969 if (ironlake_set_drps(dev_priv, new_delay))
970 dev_priv->ips.cur_delay = new_delay;
971
972 spin_unlock(&mchdev_lock);
973
974 return;
975 }
976
977 static void notify_ring(struct intel_engine_cs *engine)
978 {
979 if (!intel_engine_initialized(engine))
980 return;
981
982 trace_i915_gem_request_notify(engine);
983 engine->user_interrupts++;
984
985 wake_up_all(&engine->irq_queue);
986 }
987
988 static void vlv_c0_read(struct drm_i915_private *dev_priv,
989 struct intel_rps_ei *ei)
990 {
991 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
992 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
993 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
994 }
995
996 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
997 const struct intel_rps_ei *old,
998 const struct intel_rps_ei *now,
999 int threshold)
1000 {
1001 u64 time, c0;
1002 unsigned int mul = 100;
1003
1004 if (old->cz_clock == 0)
1005 return false;
1006
1007 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1008 mul <<= 8;
1009
1010 time = now->cz_clock - old->cz_clock;
1011 time *= threshold * dev_priv->czclk_freq;
1012
1013 /* Workload can be split between render + media, e.g. SwapBuffers
1014 * being blitted in X after being rendered in mesa. To account for
1015 * this we need to combine both engines into our activity counter.
1016 */
1017 c0 = now->render_c0 - old->render_c0;
1018 c0 += now->media_c0 - old->media_c0;
1019 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1020
1021 return c0 >= time;
1022 }
1023
1024 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1025 {
1026 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1027 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1028 }
1029
1030 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1031 {
1032 struct intel_rps_ei now;
1033 u32 events = 0;
1034
1035 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1036 return 0;
1037
1038 vlv_c0_read(dev_priv, &now);
1039 if (now.cz_clock == 0)
1040 return 0;
1041
1042 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1043 if (!vlv_c0_above(dev_priv,
1044 &dev_priv->rps.down_ei, &now,
1045 dev_priv->rps.down_threshold))
1046 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1047 dev_priv->rps.down_ei = now;
1048 }
1049
1050 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1051 if (vlv_c0_above(dev_priv,
1052 &dev_priv->rps.up_ei, &now,
1053 dev_priv->rps.up_threshold))
1054 events |= GEN6_PM_RP_UP_THRESHOLD;
1055 dev_priv->rps.up_ei = now;
1056 }
1057
1058 return events;
1059 }
1060
1061 static bool any_waiters(struct drm_i915_private *dev_priv)
1062 {
1063 struct intel_engine_cs *engine;
1064
1065 for_each_engine(engine, dev_priv)
1066 if (engine->irq_refcount)
1067 return true;
1068
1069 return false;
1070 }
1071
1072 static void gen6_pm_rps_work(struct work_struct *work)
1073 {
1074 struct drm_i915_private *dev_priv =
1075 container_of(work, struct drm_i915_private, rps.work);
1076 bool client_boost;
1077 int new_delay, adj, min, max;
1078 u32 pm_iir;
1079
1080 spin_lock_irq(&dev_priv->irq_lock);
1081 /* Speed up work cancelation during disabling rps interrupts. */
1082 if (!dev_priv->rps.interrupts_enabled) {
1083 spin_unlock_irq(&dev_priv->irq_lock);
1084 return;
1085 }
1086
1087 /*
1088 * The RPS work is synced during runtime suspend, we don't require a
1089 * wakeref. TODO: instead of disabling the asserts make sure that we
1090 * always hold an RPM reference while the work is running.
1091 */
1092 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1093
1094 pm_iir = dev_priv->rps.pm_iir;
1095 dev_priv->rps.pm_iir = 0;
1096 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1097 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1098 client_boost = dev_priv->rps.client_boost;
1099 dev_priv->rps.client_boost = false;
1100 spin_unlock_irq(&dev_priv->irq_lock);
1101
1102 /* Make sure we didn't queue anything we're not going to process. */
1103 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1104
1105 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1106 goto out;
1107
1108 mutex_lock(&dev_priv->rps.hw_lock);
1109
1110 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1111
1112 adj = dev_priv->rps.last_adj;
1113 new_delay = dev_priv->rps.cur_freq;
1114 min = dev_priv->rps.min_freq_softlimit;
1115 max = dev_priv->rps.max_freq_softlimit;
1116
1117 if (client_boost) {
1118 new_delay = dev_priv->rps.max_freq_softlimit;
1119 adj = 0;
1120 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1121 if (adj > 0)
1122 adj *= 2;
1123 else /* CHV needs even encode values */
1124 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1125 /*
1126 * For better performance, jump directly
1127 * to RPe if we're below it.
1128 */
1129 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1130 new_delay = dev_priv->rps.efficient_freq;
1131 adj = 0;
1132 }
1133 } else if (any_waiters(dev_priv)) {
1134 adj = 0;
1135 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1136 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1137 new_delay = dev_priv->rps.efficient_freq;
1138 else
1139 new_delay = dev_priv->rps.min_freq_softlimit;
1140 adj = 0;
1141 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1142 if (adj < 0)
1143 adj *= 2;
1144 else /* CHV needs even encode values */
1145 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1146 } else { /* unknown event */
1147 adj = 0;
1148 }
1149
1150 dev_priv->rps.last_adj = adj;
1151
1152 /* sysfs frequency interfaces may have snuck in while servicing the
1153 * interrupt
1154 */
1155 new_delay += adj;
1156 new_delay = clamp_t(int, new_delay, min, max);
1157
1158 intel_set_rps(dev_priv, new_delay);
1159
1160 mutex_unlock(&dev_priv->rps.hw_lock);
1161 out:
1162 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1163 }
1164
1165
1166 /**
1167 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1168 * occurred.
1169 * @work: workqueue struct
1170 *
1171 * Doesn't actually do anything except notify userspace. As a consequence of
1172 * this event, userspace should try to remap the bad rows since statistically
1173 * it is likely the same row is more likely to go bad again.
1174 */
1175 static void ivybridge_parity_work(struct work_struct *work)
1176 {
1177 struct drm_i915_private *dev_priv =
1178 container_of(work, struct drm_i915_private, l3_parity.error_work);
1179 u32 error_status, row, bank, subbank;
1180 char *parity_event[6];
1181 uint32_t misccpctl;
1182 uint8_t slice = 0;
1183
1184 /* We must turn off DOP level clock gating to access the L3 registers.
1185 * In order to prevent a get/put style interface, acquire struct mutex
1186 * any time we access those registers.
1187 */
1188 mutex_lock(&dev_priv->dev->struct_mutex);
1189
1190 /* If we've screwed up tracking, just let the interrupt fire again */
1191 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1192 goto out;
1193
1194 misccpctl = I915_READ(GEN7_MISCCPCTL);
1195 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1196 POSTING_READ(GEN7_MISCCPCTL);
1197
1198 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1199 i915_reg_t reg;
1200
1201 slice--;
1202 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1203 break;
1204
1205 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1206
1207 reg = GEN7_L3CDERRST1(slice);
1208
1209 error_status = I915_READ(reg);
1210 row = GEN7_PARITY_ERROR_ROW(error_status);
1211 bank = GEN7_PARITY_ERROR_BANK(error_status);
1212 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1213
1214 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1215 POSTING_READ(reg);
1216
1217 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1218 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1219 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1220 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1221 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1222 parity_event[5] = NULL;
1223
1224 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1225 KOBJ_CHANGE, parity_event);
1226
1227 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1228 slice, row, bank, subbank);
1229
1230 kfree(parity_event[4]);
1231 kfree(parity_event[3]);
1232 kfree(parity_event[2]);
1233 kfree(parity_event[1]);
1234 }
1235
1236 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1237
1238 out:
1239 WARN_ON(dev_priv->l3_parity.which_slice);
1240 spin_lock_irq(&dev_priv->irq_lock);
1241 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1242 spin_unlock_irq(&dev_priv->irq_lock);
1243
1244 mutex_unlock(&dev_priv->dev->struct_mutex);
1245 }
1246
1247 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1248 u32 iir)
1249 {
1250 if (!HAS_L3_DPF(dev_priv))
1251 return;
1252
1253 spin_lock(&dev_priv->irq_lock);
1254 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1255 spin_unlock(&dev_priv->irq_lock);
1256
1257 iir &= GT_PARITY_ERROR(dev_priv);
1258 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1259 dev_priv->l3_parity.which_slice |= 1 << 1;
1260
1261 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1262 dev_priv->l3_parity.which_slice |= 1 << 0;
1263
1264 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1265 }
1266
1267 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1268 u32 gt_iir)
1269 {
1270 if (gt_iir &
1271 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1272 notify_ring(&dev_priv->engine[RCS]);
1273 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1274 notify_ring(&dev_priv->engine[VCS]);
1275 }
1276
1277 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1278 u32 gt_iir)
1279 {
1280
1281 if (gt_iir &
1282 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1283 notify_ring(&dev_priv->engine[RCS]);
1284 if (gt_iir & GT_BSD_USER_INTERRUPT)
1285 notify_ring(&dev_priv->engine[VCS]);
1286 if (gt_iir & GT_BLT_USER_INTERRUPT)
1287 notify_ring(&dev_priv->engine[BCS]);
1288
1289 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1290 GT_BSD_CS_ERROR_INTERRUPT |
1291 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1292 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1293
1294 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1295 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1296 }
1297
1298 static __always_inline void
1299 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1300 {
1301 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1302 notify_ring(engine);
1303 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1304 tasklet_schedule(&engine->irq_tasklet);
1305 }
1306
1307 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1308 u32 master_ctl,
1309 u32 gt_iir[4])
1310 {
1311 irqreturn_t ret = IRQ_NONE;
1312
1313 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1314 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1315 if (gt_iir[0]) {
1316 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1317 ret = IRQ_HANDLED;
1318 } else
1319 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1320 }
1321
1322 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1323 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1324 if (gt_iir[1]) {
1325 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1326 ret = IRQ_HANDLED;
1327 } else
1328 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1329 }
1330
1331 if (master_ctl & GEN8_GT_VECS_IRQ) {
1332 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1333 if (gt_iir[3]) {
1334 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1335 ret = IRQ_HANDLED;
1336 } else
1337 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1338 }
1339
1340 if (master_ctl & GEN8_GT_PM_IRQ) {
1341 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1342 if (gt_iir[2] & dev_priv->pm_rps_events) {
1343 I915_WRITE_FW(GEN8_GT_IIR(2),
1344 gt_iir[2] & dev_priv->pm_rps_events);
1345 ret = IRQ_HANDLED;
1346 } else
1347 DRM_ERROR("The master control interrupt lied (PM)!\n");
1348 }
1349
1350 return ret;
1351 }
1352
1353 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1354 u32 gt_iir[4])
1355 {
1356 if (gt_iir[0]) {
1357 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1358 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1359 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1360 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1361 }
1362
1363 if (gt_iir[1]) {
1364 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1365 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1366 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1367 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1368 }
1369
1370 if (gt_iir[3])
1371 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1372 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1373
1374 if (gt_iir[2] & dev_priv->pm_rps_events)
1375 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1376 }
1377
1378 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1379 {
1380 switch (port) {
1381 case PORT_A:
1382 return val & PORTA_HOTPLUG_LONG_DETECT;
1383 case PORT_B:
1384 return val & PORTB_HOTPLUG_LONG_DETECT;
1385 case PORT_C:
1386 return val & PORTC_HOTPLUG_LONG_DETECT;
1387 default:
1388 return false;
1389 }
1390 }
1391
1392 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1393 {
1394 switch (port) {
1395 case PORT_E:
1396 return val & PORTE_HOTPLUG_LONG_DETECT;
1397 default:
1398 return false;
1399 }
1400 }
1401
1402 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1403 {
1404 switch (port) {
1405 case PORT_A:
1406 return val & PORTA_HOTPLUG_LONG_DETECT;
1407 case PORT_B:
1408 return val & PORTB_HOTPLUG_LONG_DETECT;
1409 case PORT_C:
1410 return val & PORTC_HOTPLUG_LONG_DETECT;
1411 case PORT_D:
1412 return val & PORTD_HOTPLUG_LONG_DETECT;
1413 default:
1414 return false;
1415 }
1416 }
1417
1418 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1419 {
1420 switch (port) {
1421 case PORT_A:
1422 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1423 default:
1424 return false;
1425 }
1426 }
1427
1428 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1429 {
1430 switch (port) {
1431 case PORT_B:
1432 return val & PORTB_HOTPLUG_LONG_DETECT;
1433 case PORT_C:
1434 return val & PORTC_HOTPLUG_LONG_DETECT;
1435 case PORT_D:
1436 return val & PORTD_HOTPLUG_LONG_DETECT;
1437 default:
1438 return false;
1439 }
1440 }
1441
1442 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1443 {
1444 switch (port) {
1445 case PORT_B:
1446 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1447 case PORT_C:
1448 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1449 case PORT_D:
1450 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1451 default:
1452 return false;
1453 }
1454 }
1455
1456 /*
1457 * Get a bit mask of pins that have triggered, and which ones may be long.
1458 * This can be called multiple times with the same masks to accumulate
1459 * hotplug detection results from several registers.
1460 *
1461 * Note that the caller is expected to zero out the masks initially.
1462 */
1463 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1464 u32 hotplug_trigger, u32 dig_hotplug_reg,
1465 const u32 hpd[HPD_NUM_PINS],
1466 bool long_pulse_detect(enum port port, u32 val))
1467 {
1468 enum port port;
1469 int i;
1470
1471 for_each_hpd_pin(i) {
1472 if ((hpd[i] & hotplug_trigger) == 0)
1473 continue;
1474
1475 *pin_mask |= BIT(i);
1476
1477 if (!intel_hpd_pin_to_port(i, &port))
1478 continue;
1479
1480 if (long_pulse_detect(port, dig_hotplug_reg))
1481 *long_mask |= BIT(i);
1482 }
1483
1484 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1485 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1486
1487 }
1488
1489 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1490 {
1491 wake_up_all(&dev_priv->gmbus_wait_queue);
1492 }
1493
1494 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1495 {
1496 wake_up_all(&dev_priv->gmbus_wait_queue);
1497 }
1498
1499 #if defined(CONFIG_DEBUG_FS)
1500 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1501 enum pipe pipe,
1502 uint32_t crc0, uint32_t crc1,
1503 uint32_t crc2, uint32_t crc3,
1504 uint32_t crc4)
1505 {
1506 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1507 struct intel_pipe_crc_entry *entry;
1508 int head, tail;
1509
1510 spin_lock(&pipe_crc->lock);
1511
1512 if (!pipe_crc->entries) {
1513 spin_unlock(&pipe_crc->lock);
1514 DRM_DEBUG_KMS("spurious interrupt\n");
1515 return;
1516 }
1517
1518 head = pipe_crc->head;
1519 tail = pipe_crc->tail;
1520
1521 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1522 spin_unlock(&pipe_crc->lock);
1523 DRM_ERROR("CRC buffer overflowing\n");
1524 return;
1525 }
1526
1527 entry = &pipe_crc->entries[head];
1528
1529 entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1530 pipe);
1531 entry->crc[0] = crc0;
1532 entry->crc[1] = crc1;
1533 entry->crc[2] = crc2;
1534 entry->crc[3] = crc3;
1535 entry->crc[4] = crc4;
1536
1537 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1538 pipe_crc->head = head;
1539
1540 spin_unlock(&pipe_crc->lock);
1541
1542 wake_up_interruptible(&pipe_crc->wq);
1543 }
1544 #else
1545 static inline void
1546 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1547 enum pipe pipe,
1548 uint32_t crc0, uint32_t crc1,
1549 uint32_t crc2, uint32_t crc3,
1550 uint32_t crc4) {}
1551 #endif
1552
1553
1554 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1555 enum pipe pipe)
1556 {
1557 display_pipe_crc_irq_handler(dev_priv, pipe,
1558 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1559 0, 0, 0, 0);
1560 }
1561
1562 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1563 enum pipe pipe)
1564 {
1565 display_pipe_crc_irq_handler(dev_priv, pipe,
1566 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1567 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1568 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1569 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1570 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1571 }
1572
1573 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 uint32_t res1, res2;
1577
1578 if (INTEL_GEN(dev_priv) >= 3)
1579 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1580 else
1581 res1 = 0;
1582
1583 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1584 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1585 else
1586 res2 = 0;
1587
1588 display_pipe_crc_irq_handler(dev_priv, pipe,
1589 I915_READ(PIPE_CRC_RES_RED(pipe)),
1590 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1591 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1592 res1, res2);
1593 }
1594
1595 /* The RPS events need forcewake, so we add them to a work queue and mask their
1596 * IMR bits until the work is done. Other interrupts can be processed without
1597 * the work queue. */
1598 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1599 {
1600 if (pm_iir & dev_priv->pm_rps_events) {
1601 spin_lock(&dev_priv->irq_lock);
1602 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1603 if (dev_priv->rps.interrupts_enabled) {
1604 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1605 queue_work(dev_priv->wq, &dev_priv->rps.work);
1606 }
1607 spin_unlock(&dev_priv->irq_lock);
1608 }
1609
1610 if (INTEL_INFO(dev_priv)->gen >= 8)
1611 return;
1612
1613 if (HAS_VEBOX(dev_priv)) {
1614 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1615 notify_ring(&dev_priv->engine[VECS]);
1616
1617 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1618 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1619 }
1620 }
1621
1622 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
1624 {
1625 bool ret;
1626
1627 ret = drm_handle_vblank(dev_priv->dev, pipe);
1628 if (ret)
1629 intel_finish_page_flip_mmio(dev_priv, pipe);
1630
1631 return ret;
1632 }
1633
1634 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1635 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1636 {
1637 int pipe;
1638
1639 spin_lock(&dev_priv->irq_lock);
1640
1641 if (!dev_priv->display_irqs_enabled) {
1642 spin_unlock(&dev_priv->irq_lock);
1643 return;
1644 }
1645
1646 for_each_pipe(dev_priv, pipe) {
1647 i915_reg_t reg;
1648 u32 mask, iir_bit = 0;
1649
1650 /*
1651 * PIPESTAT bits get signalled even when the interrupt is
1652 * disabled with the mask bits, and some of the status bits do
1653 * not generate interrupts at all (like the underrun bit). Hence
1654 * we need to be careful that we only handle what we want to
1655 * handle.
1656 */
1657
1658 /* fifo underruns are filterered in the underrun handler. */
1659 mask = PIPE_FIFO_UNDERRUN_STATUS;
1660
1661 switch (pipe) {
1662 case PIPE_A:
1663 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1664 break;
1665 case PIPE_B:
1666 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1667 break;
1668 case PIPE_C:
1669 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1670 break;
1671 }
1672 if (iir & iir_bit)
1673 mask |= dev_priv->pipestat_irq_mask[pipe];
1674
1675 if (!mask)
1676 continue;
1677
1678 reg = PIPESTAT(pipe);
1679 mask |= PIPESTAT_INT_ENABLE_MASK;
1680 pipe_stats[pipe] = I915_READ(reg) & mask;
1681
1682 /*
1683 * Clear the PIPE*STAT regs before the IIR
1684 */
1685 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1686 PIPESTAT_INT_STATUS_MASK))
1687 I915_WRITE(reg, pipe_stats[pipe]);
1688 }
1689 spin_unlock(&dev_priv->irq_lock);
1690 }
1691
1692 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1693 u32 pipe_stats[I915_MAX_PIPES])
1694 {
1695 enum pipe pipe;
1696
1697 for_each_pipe(dev_priv, pipe) {
1698 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1699 intel_pipe_handle_vblank(dev_priv, pipe))
1700 intel_check_page_flip(dev_priv, pipe);
1701
1702 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1703 intel_finish_page_flip_cs(dev_priv, pipe);
1704
1705 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1706 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1707
1708 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1709 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1710 }
1711
1712 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1713 gmbus_irq_handler(dev_priv);
1714 }
1715
1716 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1717 {
1718 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1719
1720 if (hotplug_status)
1721 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1722
1723 return hotplug_status;
1724 }
1725
1726 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1727 u32 hotplug_status)
1728 {
1729 u32 pin_mask = 0, long_mask = 0;
1730
1731 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1732 IS_CHERRYVIEW(dev_priv)) {
1733 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1734
1735 if (hotplug_trigger) {
1736 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1737 hotplug_trigger, hpd_status_g4x,
1738 i9xx_port_hotplug_long_detect);
1739
1740 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1741 }
1742
1743 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1744 dp_aux_irq_handler(dev_priv);
1745 } else {
1746 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1747
1748 if (hotplug_trigger) {
1749 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1750 hotplug_trigger, hpd_status_i915,
1751 i9xx_port_hotplug_long_detect);
1752 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1753 }
1754 }
1755 }
1756
1757 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1758 {
1759 struct drm_device *dev = arg;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 irqreturn_t ret = IRQ_NONE;
1762
1763 if (!intel_irqs_enabled(dev_priv))
1764 return IRQ_NONE;
1765
1766 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1767 disable_rpm_wakeref_asserts(dev_priv);
1768
1769 do {
1770 u32 iir, gt_iir, pm_iir;
1771 u32 pipe_stats[I915_MAX_PIPES] = {};
1772 u32 hotplug_status = 0;
1773 u32 ier = 0;
1774
1775 gt_iir = I915_READ(GTIIR);
1776 pm_iir = I915_READ(GEN6_PMIIR);
1777 iir = I915_READ(VLV_IIR);
1778
1779 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1780 break;
1781
1782 ret = IRQ_HANDLED;
1783
1784 /*
1785 * Theory on interrupt generation, based on empirical evidence:
1786 *
1787 * x = ((VLV_IIR & VLV_IER) ||
1788 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1789 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1790 *
1791 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1792 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1793 * guarantee the CPU interrupt will be raised again even if we
1794 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1795 * bits this time around.
1796 */
1797 I915_WRITE(VLV_MASTER_IER, 0);
1798 ier = I915_READ(VLV_IER);
1799 I915_WRITE(VLV_IER, 0);
1800
1801 if (gt_iir)
1802 I915_WRITE(GTIIR, gt_iir);
1803 if (pm_iir)
1804 I915_WRITE(GEN6_PMIIR, pm_iir);
1805
1806 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1807 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1808
1809 /* Call regardless, as some status bits might not be
1810 * signalled in iir */
1811 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1812
1813 /*
1814 * VLV_IIR is single buffered, and reflects the level
1815 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1816 */
1817 if (iir)
1818 I915_WRITE(VLV_IIR, iir);
1819
1820 I915_WRITE(VLV_IER, ier);
1821 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1822 POSTING_READ(VLV_MASTER_IER);
1823
1824 if (gt_iir)
1825 snb_gt_irq_handler(dev_priv, gt_iir);
1826 if (pm_iir)
1827 gen6_rps_irq_handler(dev_priv, pm_iir);
1828
1829 if (hotplug_status)
1830 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1831
1832 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1833 } while (0);
1834
1835 enable_rpm_wakeref_asserts(dev_priv);
1836
1837 return ret;
1838 }
1839
1840 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1841 {
1842 struct drm_device *dev = arg;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 irqreturn_t ret = IRQ_NONE;
1845
1846 if (!intel_irqs_enabled(dev_priv))
1847 return IRQ_NONE;
1848
1849 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1850 disable_rpm_wakeref_asserts(dev_priv);
1851
1852 do {
1853 u32 master_ctl, iir;
1854 u32 gt_iir[4] = {};
1855 u32 pipe_stats[I915_MAX_PIPES] = {};
1856 u32 hotplug_status = 0;
1857 u32 ier = 0;
1858
1859 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1860 iir = I915_READ(VLV_IIR);
1861
1862 if (master_ctl == 0 && iir == 0)
1863 break;
1864
1865 ret = IRQ_HANDLED;
1866
1867 /*
1868 * Theory on interrupt generation, based on empirical evidence:
1869 *
1870 * x = ((VLV_IIR & VLV_IER) ||
1871 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1872 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1873 *
1874 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1875 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1876 * guarantee the CPU interrupt will be raised again even if we
1877 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1878 * bits this time around.
1879 */
1880 I915_WRITE(GEN8_MASTER_IRQ, 0);
1881 ier = I915_READ(VLV_IER);
1882 I915_WRITE(VLV_IER, 0);
1883
1884 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1885
1886 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1887 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1888
1889 /* Call regardless, as some status bits might not be
1890 * signalled in iir */
1891 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1892
1893 /*
1894 * VLV_IIR is single buffered, and reflects the level
1895 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1896 */
1897 if (iir)
1898 I915_WRITE(VLV_IIR, iir);
1899
1900 I915_WRITE(VLV_IER, ier);
1901 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1902 POSTING_READ(GEN8_MASTER_IRQ);
1903
1904 gen8_gt_irq_handler(dev_priv, gt_iir);
1905
1906 if (hotplug_status)
1907 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1908
1909 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1910 } while (0);
1911
1912 enable_rpm_wakeref_asserts(dev_priv);
1913
1914 return ret;
1915 }
1916
1917 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1918 u32 hotplug_trigger,
1919 const u32 hpd[HPD_NUM_PINS])
1920 {
1921 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1922
1923 /*
1924 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1925 * unless we touch the hotplug register, even if hotplug_trigger is
1926 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1927 * errors.
1928 */
1929 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1930 if (!hotplug_trigger) {
1931 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1932 PORTD_HOTPLUG_STATUS_MASK |
1933 PORTC_HOTPLUG_STATUS_MASK |
1934 PORTB_HOTPLUG_STATUS_MASK;
1935 dig_hotplug_reg &= ~mask;
1936 }
1937
1938 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1939 if (!hotplug_trigger)
1940 return;
1941
1942 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1943 dig_hotplug_reg, hpd,
1944 pch_port_hotplug_long_detect);
1945
1946 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1947 }
1948
1949 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1950 {
1951 int pipe;
1952 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1953
1954 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1955
1956 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1957 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1958 SDE_AUDIO_POWER_SHIFT);
1959 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1960 port_name(port));
1961 }
1962
1963 if (pch_iir & SDE_AUX_MASK)
1964 dp_aux_irq_handler(dev_priv);
1965
1966 if (pch_iir & SDE_GMBUS)
1967 gmbus_irq_handler(dev_priv);
1968
1969 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1970 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1971
1972 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1973 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1974
1975 if (pch_iir & SDE_POISON)
1976 DRM_ERROR("PCH poison interrupt\n");
1977
1978 if (pch_iir & SDE_FDI_MASK)
1979 for_each_pipe(dev_priv, pipe)
1980 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1981 pipe_name(pipe),
1982 I915_READ(FDI_RX_IIR(pipe)));
1983
1984 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1985 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1986
1987 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1988 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1989
1990 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1991 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1992
1993 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1994 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1995 }
1996
1997 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1998 {
1999 u32 err_int = I915_READ(GEN7_ERR_INT);
2000 enum pipe pipe;
2001
2002 if (err_int & ERR_INT_POISON)
2003 DRM_ERROR("Poison interrupt\n");
2004
2005 for_each_pipe(dev_priv, pipe) {
2006 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2007 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2008
2009 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2010 if (IS_IVYBRIDGE(dev_priv))
2011 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2012 else
2013 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2014 }
2015 }
2016
2017 I915_WRITE(GEN7_ERR_INT, err_int);
2018 }
2019
2020 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2021 {
2022 u32 serr_int = I915_READ(SERR_INT);
2023
2024 if (serr_int & SERR_INT_POISON)
2025 DRM_ERROR("PCH poison interrupt\n");
2026
2027 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2028 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2029
2030 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2031 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2032
2033 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2034 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2035
2036 I915_WRITE(SERR_INT, serr_int);
2037 }
2038
2039 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2040 {
2041 int pipe;
2042 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2043
2044 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2045
2046 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2047 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2048 SDE_AUDIO_POWER_SHIFT_CPT);
2049 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2050 port_name(port));
2051 }
2052
2053 if (pch_iir & SDE_AUX_MASK_CPT)
2054 dp_aux_irq_handler(dev_priv);
2055
2056 if (pch_iir & SDE_GMBUS_CPT)
2057 gmbus_irq_handler(dev_priv);
2058
2059 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2060 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2061
2062 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2063 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2064
2065 if (pch_iir & SDE_FDI_MASK_CPT)
2066 for_each_pipe(dev_priv, pipe)
2067 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2068 pipe_name(pipe),
2069 I915_READ(FDI_RX_IIR(pipe)));
2070
2071 if (pch_iir & SDE_ERROR_CPT)
2072 cpt_serr_int_handler(dev_priv);
2073 }
2074
2075 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2076 {
2077 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2078 ~SDE_PORTE_HOTPLUG_SPT;
2079 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2080 u32 pin_mask = 0, long_mask = 0;
2081
2082 if (hotplug_trigger) {
2083 u32 dig_hotplug_reg;
2084
2085 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2086 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2087
2088 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2089 dig_hotplug_reg, hpd_spt,
2090 spt_port_hotplug_long_detect);
2091 }
2092
2093 if (hotplug2_trigger) {
2094 u32 dig_hotplug_reg;
2095
2096 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2097 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2098
2099 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2100 dig_hotplug_reg, hpd_spt,
2101 spt_port_hotplug2_long_detect);
2102 }
2103
2104 if (pin_mask)
2105 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2106
2107 if (pch_iir & SDE_GMBUS_CPT)
2108 gmbus_irq_handler(dev_priv);
2109 }
2110
2111 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2112 u32 hotplug_trigger,
2113 const u32 hpd[HPD_NUM_PINS])
2114 {
2115 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2116
2117 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2118 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2119
2120 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2121 dig_hotplug_reg, hpd,
2122 ilk_port_hotplug_long_detect);
2123
2124 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2125 }
2126
2127 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2128 u32 de_iir)
2129 {
2130 enum pipe pipe;
2131 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2132
2133 if (hotplug_trigger)
2134 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2135
2136 if (de_iir & DE_AUX_CHANNEL_A)
2137 dp_aux_irq_handler(dev_priv);
2138
2139 if (de_iir & DE_GSE)
2140 intel_opregion_asle_intr(dev_priv);
2141
2142 if (de_iir & DE_POISON)
2143 DRM_ERROR("Poison interrupt\n");
2144
2145 for_each_pipe(dev_priv, pipe) {
2146 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2147 intel_pipe_handle_vblank(dev_priv, pipe))
2148 intel_check_page_flip(dev_priv, pipe);
2149
2150 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2151 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2152
2153 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2154 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2155
2156 /* plane/pipes map 1:1 on ilk+ */
2157 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2158 intel_finish_page_flip_cs(dev_priv, pipe);
2159 }
2160
2161 /* check event from PCH */
2162 if (de_iir & DE_PCH_EVENT) {
2163 u32 pch_iir = I915_READ(SDEIIR);
2164
2165 if (HAS_PCH_CPT(dev_priv))
2166 cpt_irq_handler(dev_priv, pch_iir);
2167 else
2168 ibx_irq_handler(dev_priv, pch_iir);
2169
2170 /* should clear PCH hotplug event before clear CPU irq */
2171 I915_WRITE(SDEIIR, pch_iir);
2172 }
2173
2174 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2175 ironlake_rps_change_irq_handler(dev_priv);
2176 }
2177
2178 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2179 u32 de_iir)
2180 {
2181 enum pipe pipe;
2182 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2183
2184 if (hotplug_trigger)
2185 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2186
2187 if (de_iir & DE_ERR_INT_IVB)
2188 ivb_err_int_handler(dev_priv);
2189
2190 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2191 dp_aux_irq_handler(dev_priv);
2192
2193 if (de_iir & DE_GSE_IVB)
2194 intel_opregion_asle_intr(dev_priv);
2195
2196 for_each_pipe(dev_priv, pipe) {
2197 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2198 intel_pipe_handle_vblank(dev_priv, pipe))
2199 intel_check_page_flip(dev_priv, pipe);
2200
2201 /* plane/pipes map 1:1 on ilk+ */
2202 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2203 intel_finish_page_flip_cs(dev_priv, pipe);
2204 }
2205
2206 /* check event from PCH */
2207 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2208 u32 pch_iir = I915_READ(SDEIIR);
2209
2210 cpt_irq_handler(dev_priv, pch_iir);
2211
2212 /* clear PCH hotplug event before clear CPU irq */
2213 I915_WRITE(SDEIIR, pch_iir);
2214 }
2215 }
2216
2217 /*
2218 * To handle irqs with the minimum potential races with fresh interrupts, we:
2219 * 1 - Disable Master Interrupt Control.
2220 * 2 - Find the source(s) of the interrupt.
2221 * 3 - Clear the Interrupt Identity bits (IIR).
2222 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2223 * 5 - Re-enable Master Interrupt Control.
2224 */
2225 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2226 {
2227 struct drm_device *dev = arg;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2230 irqreturn_t ret = IRQ_NONE;
2231
2232 if (!intel_irqs_enabled(dev_priv))
2233 return IRQ_NONE;
2234
2235 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2236 disable_rpm_wakeref_asserts(dev_priv);
2237
2238 /* disable master interrupt before clearing iir */
2239 de_ier = I915_READ(DEIER);
2240 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2241 POSTING_READ(DEIER);
2242
2243 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2244 * interrupts will will be stored on its back queue, and then we'll be
2245 * able to process them after we restore SDEIER (as soon as we restore
2246 * it, we'll get an interrupt if SDEIIR still has something to process
2247 * due to its back queue). */
2248 if (!HAS_PCH_NOP(dev_priv)) {
2249 sde_ier = I915_READ(SDEIER);
2250 I915_WRITE(SDEIER, 0);
2251 POSTING_READ(SDEIER);
2252 }
2253
2254 /* Find, clear, then process each source of interrupt */
2255
2256 gt_iir = I915_READ(GTIIR);
2257 if (gt_iir) {
2258 I915_WRITE(GTIIR, gt_iir);
2259 ret = IRQ_HANDLED;
2260 if (INTEL_GEN(dev_priv) >= 6)
2261 snb_gt_irq_handler(dev_priv, gt_iir);
2262 else
2263 ilk_gt_irq_handler(dev_priv, gt_iir);
2264 }
2265
2266 de_iir = I915_READ(DEIIR);
2267 if (de_iir) {
2268 I915_WRITE(DEIIR, de_iir);
2269 ret = IRQ_HANDLED;
2270 if (INTEL_GEN(dev_priv) >= 7)
2271 ivb_display_irq_handler(dev_priv, de_iir);
2272 else
2273 ilk_display_irq_handler(dev_priv, de_iir);
2274 }
2275
2276 if (INTEL_GEN(dev_priv) >= 6) {
2277 u32 pm_iir = I915_READ(GEN6_PMIIR);
2278 if (pm_iir) {
2279 I915_WRITE(GEN6_PMIIR, pm_iir);
2280 ret = IRQ_HANDLED;
2281 gen6_rps_irq_handler(dev_priv, pm_iir);
2282 }
2283 }
2284
2285 I915_WRITE(DEIER, de_ier);
2286 POSTING_READ(DEIER);
2287 if (!HAS_PCH_NOP(dev_priv)) {
2288 I915_WRITE(SDEIER, sde_ier);
2289 POSTING_READ(SDEIER);
2290 }
2291
2292 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2293 enable_rpm_wakeref_asserts(dev_priv);
2294
2295 return ret;
2296 }
2297
2298 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2299 u32 hotplug_trigger,
2300 const u32 hpd[HPD_NUM_PINS])
2301 {
2302 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2303
2304 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2305 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2306
2307 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2308 dig_hotplug_reg, hpd,
2309 bxt_port_hotplug_long_detect);
2310
2311 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2312 }
2313
2314 static irqreturn_t
2315 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2316 {
2317 irqreturn_t ret = IRQ_NONE;
2318 u32 iir;
2319 enum pipe pipe;
2320
2321 if (master_ctl & GEN8_DE_MISC_IRQ) {
2322 iir = I915_READ(GEN8_DE_MISC_IIR);
2323 if (iir) {
2324 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2325 ret = IRQ_HANDLED;
2326 if (iir & GEN8_DE_MISC_GSE)
2327 intel_opregion_asle_intr(dev_priv);
2328 else
2329 DRM_ERROR("Unexpected DE Misc interrupt\n");
2330 }
2331 else
2332 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2333 }
2334
2335 if (master_ctl & GEN8_DE_PORT_IRQ) {
2336 iir = I915_READ(GEN8_DE_PORT_IIR);
2337 if (iir) {
2338 u32 tmp_mask;
2339 bool found = false;
2340
2341 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2342 ret = IRQ_HANDLED;
2343
2344 tmp_mask = GEN8_AUX_CHANNEL_A;
2345 if (INTEL_INFO(dev_priv)->gen >= 9)
2346 tmp_mask |= GEN9_AUX_CHANNEL_B |
2347 GEN9_AUX_CHANNEL_C |
2348 GEN9_AUX_CHANNEL_D;
2349
2350 if (iir & tmp_mask) {
2351 dp_aux_irq_handler(dev_priv);
2352 found = true;
2353 }
2354
2355 if (IS_BROXTON(dev_priv)) {
2356 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2357 if (tmp_mask) {
2358 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2359 hpd_bxt);
2360 found = true;
2361 }
2362 } else if (IS_BROADWELL(dev_priv)) {
2363 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2364 if (tmp_mask) {
2365 ilk_hpd_irq_handler(dev_priv,
2366 tmp_mask, hpd_bdw);
2367 found = true;
2368 }
2369 }
2370
2371 if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2372 gmbus_irq_handler(dev_priv);
2373 found = true;
2374 }
2375
2376 if (!found)
2377 DRM_ERROR("Unexpected DE Port interrupt\n");
2378 }
2379 else
2380 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2381 }
2382
2383 for_each_pipe(dev_priv, pipe) {
2384 u32 flip_done, fault_errors;
2385
2386 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2387 continue;
2388
2389 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2390 if (!iir) {
2391 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2392 continue;
2393 }
2394
2395 ret = IRQ_HANDLED;
2396 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2397
2398 if (iir & GEN8_PIPE_VBLANK &&
2399 intel_pipe_handle_vblank(dev_priv, pipe))
2400 intel_check_page_flip(dev_priv, pipe);
2401
2402 flip_done = iir;
2403 if (INTEL_INFO(dev_priv)->gen >= 9)
2404 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2405 else
2406 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2407
2408 if (flip_done)
2409 intel_finish_page_flip_cs(dev_priv, pipe);
2410
2411 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2412 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2413
2414 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2415 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2416
2417 fault_errors = iir;
2418 if (INTEL_INFO(dev_priv)->gen >= 9)
2419 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2420 else
2421 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2422
2423 if (fault_errors)
2424 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2425 pipe_name(pipe),
2426 fault_errors);
2427 }
2428
2429 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2430 master_ctl & GEN8_DE_PCH_IRQ) {
2431 /*
2432 * FIXME(BDW): Assume for now that the new interrupt handling
2433 * scheme also closed the SDE interrupt handling race we've seen
2434 * on older pch-split platforms. But this needs testing.
2435 */
2436 iir = I915_READ(SDEIIR);
2437 if (iir) {
2438 I915_WRITE(SDEIIR, iir);
2439 ret = IRQ_HANDLED;
2440
2441 if (HAS_PCH_SPT(dev_priv))
2442 spt_irq_handler(dev_priv, iir);
2443 else
2444 cpt_irq_handler(dev_priv, iir);
2445 } else {
2446 /*
2447 * Like on previous PCH there seems to be something
2448 * fishy going on with forwarding PCH interrupts.
2449 */
2450 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2451 }
2452 }
2453
2454 return ret;
2455 }
2456
2457 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2458 {
2459 struct drm_device *dev = arg;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 u32 master_ctl;
2462 u32 gt_iir[4] = {};
2463 irqreturn_t ret;
2464
2465 if (!intel_irqs_enabled(dev_priv))
2466 return IRQ_NONE;
2467
2468 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2469 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2470 if (!master_ctl)
2471 return IRQ_NONE;
2472
2473 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2474
2475 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2476 disable_rpm_wakeref_asserts(dev_priv);
2477
2478 /* Find, clear, then process each source of interrupt */
2479 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2480 gen8_gt_irq_handler(dev_priv, gt_iir);
2481 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2482
2483 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2484 POSTING_READ_FW(GEN8_MASTER_IRQ);
2485
2486 enable_rpm_wakeref_asserts(dev_priv);
2487
2488 return ret;
2489 }
2490
2491 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2492 bool reset_completed)
2493 {
2494 struct intel_engine_cs *engine;
2495
2496 /*
2497 * Notify all waiters for GPU completion events that reset state has
2498 * been changed, and that they need to restart their wait after
2499 * checking for potential errors (and bail out to drop locks if there is
2500 * a gpu reset pending so that i915_error_work_func can acquire them).
2501 */
2502
2503 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2504 for_each_engine(engine, dev_priv)
2505 wake_up_all(&engine->irq_queue);
2506
2507 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2508 wake_up_all(&dev_priv->pending_flip_queue);
2509
2510 /*
2511 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2512 * reset state is cleared.
2513 */
2514 if (reset_completed)
2515 wake_up_all(&dev_priv->gpu_error.reset_queue);
2516 }
2517
2518 /**
2519 * i915_reset_and_wakeup - do process context error handling work
2520 * @dev_priv: i915 device private
2521 *
2522 * Fire an error uevent so userspace can see that a hang or error
2523 * was detected.
2524 */
2525 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2526 {
2527 struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2528 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2529 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2530 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2531 int ret;
2532
2533 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2534
2535 /*
2536 * Note that there's only one work item which does gpu resets, so we
2537 * need not worry about concurrent gpu resets potentially incrementing
2538 * error->reset_counter twice. We only need to take care of another
2539 * racing irq/hangcheck declaring the gpu dead for a second time. A
2540 * quick check for that is good enough: schedule_work ensures the
2541 * correct ordering between hang detection and this work item, and since
2542 * the reset in-progress bit is only ever set by code outside of this
2543 * work we don't need to worry about any other races.
2544 */
2545 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2546 DRM_DEBUG_DRIVER("resetting chip\n");
2547 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2548
2549 /*
2550 * In most cases it's guaranteed that we get here with an RPM
2551 * reference held, for example because there is a pending GPU
2552 * request that won't finish until the reset is done. This
2553 * isn't the case at least when we get here by doing a
2554 * simulated reset via debugs, so get an RPM reference.
2555 */
2556 intel_runtime_pm_get(dev_priv);
2557
2558 intel_prepare_reset(dev_priv);
2559
2560 /*
2561 * All state reset _must_ be completed before we update the
2562 * reset counter, for otherwise waiters might miss the reset
2563 * pending state and not properly drop locks, resulting in
2564 * deadlocks with the reset work.
2565 */
2566 ret = i915_reset(dev_priv);
2567
2568 intel_finish_reset(dev_priv);
2569
2570 intel_runtime_pm_put(dev_priv);
2571
2572 if (ret == 0)
2573 kobject_uevent_env(kobj,
2574 KOBJ_CHANGE, reset_done_event);
2575
2576 /*
2577 * Note: The wake_up also serves as a memory barrier so that
2578 * waiters see the update value of the reset counter atomic_t.
2579 */
2580 i915_error_wake_up(dev_priv, true);
2581 }
2582 }
2583
2584 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2585 {
2586 uint32_t instdone[I915_NUM_INSTDONE_REG];
2587 u32 eir = I915_READ(EIR);
2588 int pipe, i;
2589
2590 if (!eir)
2591 return;
2592
2593 pr_err("render error detected, EIR: 0x%08x\n", eir);
2594
2595 i915_get_extra_instdone(dev_priv, instdone);
2596
2597 if (IS_G4X(dev_priv)) {
2598 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2599 u32 ipeir = I915_READ(IPEIR_I965);
2600
2601 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2602 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2603 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2604 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2605 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2606 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2607 I915_WRITE(IPEIR_I965, ipeir);
2608 POSTING_READ(IPEIR_I965);
2609 }
2610 if (eir & GM45_ERROR_PAGE_TABLE) {
2611 u32 pgtbl_err = I915_READ(PGTBL_ER);
2612 pr_err("page table error\n");
2613 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2614 I915_WRITE(PGTBL_ER, pgtbl_err);
2615 POSTING_READ(PGTBL_ER);
2616 }
2617 }
2618
2619 if (!IS_GEN2(dev_priv)) {
2620 if (eir & I915_ERROR_PAGE_TABLE) {
2621 u32 pgtbl_err = I915_READ(PGTBL_ER);
2622 pr_err("page table error\n");
2623 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2624 I915_WRITE(PGTBL_ER, pgtbl_err);
2625 POSTING_READ(PGTBL_ER);
2626 }
2627 }
2628
2629 if (eir & I915_ERROR_MEMORY_REFRESH) {
2630 pr_err("memory refresh error:\n");
2631 for_each_pipe(dev_priv, pipe)
2632 pr_err("pipe %c stat: 0x%08x\n",
2633 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2634 /* pipestat has already been acked */
2635 }
2636 if (eir & I915_ERROR_INSTRUCTION) {
2637 pr_err("instruction error\n");
2638 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2639 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2640 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2641 if (INTEL_GEN(dev_priv) < 4) {
2642 u32 ipeir = I915_READ(IPEIR);
2643
2644 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2645 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2646 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2647 I915_WRITE(IPEIR, ipeir);
2648 POSTING_READ(IPEIR);
2649 } else {
2650 u32 ipeir = I915_READ(IPEIR_I965);
2651
2652 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2653 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2654 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2655 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2656 I915_WRITE(IPEIR_I965, ipeir);
2657 POSTING_READ(IPEIR_I965);
2658 }
2659 }
2660
2661 I915_WRITE(EIR, eir);
2662 POSTING_READ(EIR);
2663 eir = I915_READ(EIR);
2664 if (eir) {
2665 /*
2666 * some errors might have become stuck,
2667 * mask them.
2668 */
2669 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2670 I915_WRITE(EMR, I915_READ(EMR) | eir);
2671 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2672 }
2673 }
2674
2675 /**
2676 * i915_handle_error - handle a gpu error
2677 * @dev_priv: i915 device private
2678 * @engine_mask: mask representing engines that are hung
2679 * Do some basic checking of register state at error time and
2680 * dump it to the syslog. Also call i915_capture_error_state() to make
2681 * sure we get a record and make it available in debugfs. Fire a uevent
2682 * so userspace knows something bad happened (should trigger collection
2683 * of a ring dump etc.).
2684 * @fmt: Error message format string
2685 */
2686 void i915_handle_error(struct drm_i915_private *dev_priv,
2687 u32 engine_mask,
2688 const char *fmt, ...)
2689 {
2690 va_list args;
2691 char error_msg[80];
2692
2693 va_start(args, fmt);
2694 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2695 va_end(args);
2696
2697 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2698 i915_report_and_clear_eir(dev_priv);
2699
2700 if (engine_mask) {
2701 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2702 &dev_priv->gpu_error.reset_counter);
2703
2704 /*
2705 * Wakeup waiting processes so that the reset function
2706 * i915_reset_and_wakeup doesn't deadlock trying to grab
2707 * various locks. By bumping the reset counter first, the woken
2708 * processes will see a reset in progress and back off,
2709 * releasing their locks and then wait for the reset completion.
2710 * We must do this for _all_ gpu waiters that might hold locks
2711 * that the reset work needs to acquire.
2712 *
2713 * Note: The wake_up serves as the required memory barrier to
2714 * ensure that the waiters see the updated value of the reset
2715 * counter atomic_t.
2716 */
2717 i915_error_wake_up(dev_priv, false);
2718 }
2719
2720 i915_reset_and_wakeup(dev_priv);
2721 }
2722
2723 /* Called from drm generic code, passed 'crtc' which
2724 * we use as a pipe index
2725 */
2726 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2727 {
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 unsigned long irqflags;
2730
2731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732 if (INTEL_INFO(dev)->gen >= 4)
2733 i915_enable_pipestat(dev_priv, pipe,
2734 PIPE_START_VBLANK_INTERRUPT_STATUS);
2735 else
2736 i915_enable_pipestat(dev_priv, pipe,
2737 PIPE_VBLANK_INTERRUPT_STATUS);
2738 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2739
2740 return 0;
2741 }
2742
2743 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2744 {
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2746 unsigned long irqflags;
2747 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2748 DE_PIPE_VBLANK(pipe);
2749
2750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2751 ilk_enable_display_irq(dev_priv, bit);
2752 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2753
2754 return 0;
2755 }
2756
2757 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2758 {
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 unsigned long irqflags;
2761
2762 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2763 i915_enable_pipestat(dev_priv, pipe,
2764 PIPE_START_VBLANK_INTERRUPT_STATUS);
2765 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2766
2767 return 0;
2768 }
2769
2770 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2771 {
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 unsigned long irqflags;
2774
2775 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2776 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2777 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778
2779 return 0;
2780 }
2781
2782 /* Called from drm generic code, passed 'crtc' which
2783 * we use as a pipe index
2784 */
2785 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2786 {
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 unsigned long irqflags;
2789
2790 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2791 i915_disable_pipestat(dev_priv, pipe,
2792 PIPE_VBLANK_INTERRUPT_STATUS |
2793 PIPE_START_VBLANK_INTERRUPT_STATUS);
2794 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2795 }
2796
2797 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2798 {
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 unsigned long irqflags;
2801 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2802 DE_PIPE_VBLANK(pipe);
2803
2804 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2805 ilk_disable_display_irq(dev_priv, bit);
2806 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2807 }
2808
2809 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2810 {
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 unsigned long irqflags;
2813
2814 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2815 i915_disable_pipestat(dev_priv, pipe,
2816 PIPE_START_VBLANK_INTERRUPT_STATUS);
2817 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2818 }
2819
2820 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2821 {
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 unsigned long irqflags;
2824
2825 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2826 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2827 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2828 }
2829
2830 static bool
2831 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2832 {
2833 return i915_seqno_passed(seqno,
2834 READ_ONCE(engine->last_submitted_seqno));
2835 }
2836
2837 static bool
2838 ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
2839 {
2840 if (INTEL_GEN(dev_priv) >= 8) {
2841 return (ipehr >> 23) == 0x1c;
2842 } else {
2843 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2844 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2845 MI_SEMAPHORE_REGISTER);
2846 }
2847 }
2848
2849 static struct intel_engine_cs *
2850 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2851 u64 offset)
2852 {
2853 struct drm_i915_private *dev_priv = engine->i915;
2854 struct intel_engine_cs *signaller;
2855
2856 if (INTEL_GEN(dev_priv) >= 8) {
2857 for_each_engine(signaller, dev_priv) {
2858 if (engine == signaller)
2859 continue;
2860
2861 if (offset == signaller->semaphore.signal_ggtt[engine->id])
2862 return signaller;
2863 }
2864 } else {
2865 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2866
2867 for_each_engine(signaller, dev_priv) {
2868 if(engine == signaller)
2869 continue;
2870
2871 if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2872 return signaller;
2873 }
2874 }
2875
2876 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2877 engine->id, ipehr, offset);
2878
2879 return NULL;
2880 }
2881
2882 static struct intel_engine_cs *
2883 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2884 {
2885 struct drm_i915_private *dev_priv = engine->i915;
2886 u32 cmd, ipehr, head;
2887 u64 offset = 0;
2888 int i, backwards;
2889
2890 /*
2891 * This function does not support execlist mode - any attempt to
2892 * proceed further into this function will result in a kernel panic
2893 * when dereferencing ring->buffer, which is not set up in execlist
2894 * mode.
2895 *
2896 * The correct way of doing it would be to derive the currently
2897 * executing ring buffer from the current context, which is derived
2898 * from the currently running request. Unfortunately, to get the
2899 * current request we would have to grab the struct_mutex before doing
2900 * anything else, which would be ill-advised since some other thread
2901 * might have grabbed it already and managed to hang itself, causing
2902 * the hang checker to deadlock.
2903 *
2904 * Therefore, this function does not support execlist mode in its
2905 * current form. Just return NULL and move on.
2906 */
2907 if (engine->buffer == NULL)
2908 return NULL;
2909
2910 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2911 if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
2912 return NULL;
2913
2914 /*
2915 * HEAD is likely pointing to the dword after the actual command,
2916 * so scan backwards until we find the MBOX. But limit it to just 3
2917 * or 4 dwords depending on the semaphore wait command size.
2918 * Note that we don't care about ACTHD here since that might
2919 * point at at batch, and semaphores are always emitted into the
2920 * ringbuffer itself.
2921 */
2922 head = I915_READ_HEAD(engine) & HEAD_ADDR;
2923 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2924
2925 for (i = backwards; i; --i) {
2926 /*
2927 * Be paranoid and presume the hw has gone off into the wild -
2928 * our ring is smaller than what the hardware (and hence
2929 * HEAD_ADDR) allows. Also handles wrap-around.
2930 */
2931 head &= engine->buffer->size - 1;
2932
2933 /* This here seems to blow up */
2934 cmd = ioread32(engine->buffer->virtual_start + head);
2935 if (cmd == ipehr)
2936 break;
2937
2938 head -= 4;
2939 }
2940
2941 if (!i)
2942 return NULL;
2943
2944 *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2945 if (INTEL_GEN(dev_priv) >= 8) {
2946 offset = ioread32(engine->buffer->virtual_start + head + 12);
2947 offset <<= 32;
2948 offset = ioread32(engine->buffer->virtual_start + head + 8);
2949 }
2950 return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2951 }
2952
2953 static int semaphore_passed(struct intel_engine_cs *engine)
2954 {
2955 struct drm_i915_private *dev_priv = engine->i915;
2956 struct intel_engine_cs *signaller;
2957 u32 seqno;
2958
2959 engine->hangcheck.deadlock++;
2960
2961 signaller = semaphore_waits_for(engine, &seqno);
2962 if (signaller == NULL)
2963 return -1;
2964
2965 /* Prevent pathological recursion due to driver bugs */
2966 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2967 return -1;
2968
2969 if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
2970 return 1;
2971
2972 /* cursory check for an unkickable deadlock */
2973 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2974 semaphore_passed(signaller) < 0)
2975 return -1;
2976
2977 return 0;
2978 }
2979
2980 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2981 {
2982 struct intel_engine_cs *engine;
2983
2984 for_each_engine(engine, dev_priv)
2985 engine->hangcheck.deadlock = 0;
2986 }
2987
2988 static bool subunits_stuck(struct intel_engine_cs *engine)
2989 {
2990 u32 instdone[I915_NUM_INSTDONE_REG];
2991 bool stuck;
2992 int i;
2993
2994 if (engine->id != RCS)
2995 return true;
2996
2997 i915_get_extra_instdone(engine->i915, instdone);
2998
2999 /* There might be unstable subunit states even when
3000 * actual head is not moving. Filter out the unstable ones by
3001 * accumulating the undone -> done transitions and only
3002 * consider those as progress.
3003 */
3004 stuck = true;
3005 for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
3006 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
3007
3008 if (tmp != engine->hangcheck.instdone[i])
3009 stuck = false;
3010
3011 engine->hangcheck.instdone[i] |= tmp;
3012 }
3013
3014 return stuck;
3015 }
3016
3017 static enum intel_ring_hangcheck_action
3018 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3019 {
3020 if (acthd != engine->hangcheck.acthd) {
3021
3022 /* Clear subunit states on head movement */
3023 memset(engine->hangcheck.instdone, 0,
3024 sizeof(engine->hangcheck.instdone));
3025
3026 return HANGCHECK_ACTIVE;
3027 }
3028
3029 if (!subunits_stuck(engine))
3030 return HANGCHECK_ACTIVE;
3031
3032 return HANGCHECK_HUNG;
3033 }
3034
3035 static enum intel_ring_hangcheck_action
3036 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3037 {
3038 struct drm_i915_private *dev_priv = engine->i915;
3039 enum intel_ring_hangcheck_action ha;
3040 u32 tmp;
3041
3042 ha = head_stuck(engine, acthd);
3043 if (ha != HANGCHECK_HUNG)
3044 return ha;
3045
3046 if (IS_GEN2(dev_priv))
3047 return HANGCHECK_HUNG;
3048
3049 /* Is the chip hanging on a WAIT_FOR_EVENT?
3050 * If so we can simply poke the RB_WAIT bit
3051 * and break the hang. This should work on
3052 * all but the second generation chipsets.
3053 */
3054 tmp = I915_READ_CTL(engine);
3055 if (tmp & RING_WAIT) {
3056 i915_handle_error(dev_priv, 0,
3057 "Kicking stuck wait on %s",
3058 engine->name);
3059 I915_WRITE_CTL(engine, tmp);
3060 return HANGCHECK_KICK;
3061 }
3062
3063 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3064 switch (semaphore_passed(engine)) {
3065 default:
3066 return HANGCHECK_HUNG;
3067 case 1:
3068 i915_handle_error(dev_priv, 0,
3069 "Kicking stuck semaphore on %s",
3070 engine->name);
3071 I915_WRITE_CTL(engine, tmp);
3072 return HANGCHECK_KICK;
3073 case 0:
3074 return HANGCHECK_WAIT;
3075 }
3076 }
3077
3078 return HANGCHECK_HUNG;
3079 }
3080
3081 static unsigned kick_waiters(struct intel_engine_cs *engine)
3082 {
3083 struct drm_i915_private *i915 = engine->i915;
3084 unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3085
3086 if (engine->hangcheck.user_interrupts == user_interrupts &&
3087 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3088 if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine)))
3089 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3090 engine->name);
3091 else
3092 DRM_INFO("Fake missed irq on %s\n",
3093 engine->name);
3094 wake_up_all(&engine->irq_queue);
3095 }
3096
3097 return user_interrupts;
3098 }
3099 /*
3100 * This is called when the chip hasn't reported back with completed
3101 * batchbuffers in a long time. We keep track per ring seqno progress and
3102 * if there are no progress, hangcheck score for that ring is increased.
3103 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3104 * we kick the ring. If we see no progress on three subsequent calls
3105 * we assume chip is wedged and try to fix it by resetting the chip.
3106 */
3107 static void i915_hangcheck_elapsed(struct work_struct *work)
3108 {
3109 struct drm_i915_private *dev_priv =
3110 container_of(work, typeof(*dev_priv),
3111 gpu_error.hangcheck_work.work);
3112 struct intel_engine_cs *engine;
3113 enum intel_engine_id id;
3114 int busy_count = 0, rings_hung = 0;
3115 bool stuck[I915_NUM_ENGINES] = { 0 };
3116 #define BUSY 1
3117 #define KICK 5
3118 #define HUNG 20
3119 #define ACTIVE_DECAY 15
3120
3121 if (!i915.enable_hangcheck)
3122 return;
3123
3124 /*
3125 * The hangcheck work is synced during runtime suspend, we don't
3126 * require a wakeref. TODO: instead of disabling the asserts make
3127 * sure that we hold a reference when this work is running.
3128 */
3129 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3130
3131 /* As enabling the GPU requires fairly extensive mmio access,
3132 * periodically arm the mmio checker to see if we are triggering
3133 * any invalid access.
3134 */
3135 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3136
3137 for_each_engine_id(engine, dev_priv, id) {
3138 bool busy = waitqueue_active(&engine->irq_queue);
3139 u64 acthd;
3140 u32 seqno;
3141 unsigned user_interrupts;
3142
3143 semaphore_clear_deadlocks(dev_priv);
3144
3145 /* We don't strictly need an irq-barrier here, as we are not
3146 * serving an interrupt request, be paranoid in case the
3147 * barrier has side-effects (such as preventing a broken
3148 * cacheline snoop) and so be sure that we can see the seqno
3149 * advance. If the seqno should stick, due to a stale
3150 * cacheline, we would erroneously declare the GPU hung.
3151 */
3152 if (engine->irq_seqno_barrier)
3153 engine->irq_seqno_barrier(engine);
3154
3155 acthd = intel_ring_get_active_head(engine);
3156 seqno = engine->get_seqno(engine);
3157
3158 /* Reset stuck interrupts between batch advances */
3159 user_interrupts = 0;
3160
3161 if (engine->hangcheck.seqno == seqno) {
3162 if (ring_idle(engine, seqno)) {
3163 engine->hangcheck.action = HANGCHECK_IDLE;
3164 if (busy) {
3165 /* Safeguard against driver failure */
3166 user_interrupts = kick_waiters(engine);
3167 engine->hangcheck.score += BUSY;
3168 }
3169 } else {
3170 /* We always increment the hangcheck score
3171 * if the ring is busy and still processing
3172 * the same request, so that no single request
3173 * can run indefinitely (such as a chain of
3174 * batches). The only time we do not increment
3175 * the hangcheck score on this ring, if this
3176 * ring is in a legitimate wait for another
3177 * ring. In that case the waiting ring is a
3178 * victim and we want to be sure we catch the
3179 * right culprit. Then every time we do kick
3180 * the ring, add a small increment to the
3181 * score so that we can catch a batch that is
3182 * being repeatedly kicked and so responsible
3183 * for stalling the machine.
3184 */
3185 engine->hangcheck.action = ring_stuck(engine,
3186 acthd);
3187
3188 switch (engine->hangcheck.action) {
3189 case HANGCHECK_IDLE:
3190 case HANGCHECK_WAIT:
3191 break;
3192 case HANGCHECK_ACTIVE:
3193 engine->hangcheck.score += BUSY;
3194 break;
3195 case HANGCHECK_KICK:
3196 engine->hangcheck.score += KICK;
3197 break;
3198 case HANGCHECK_HUNG:
3199 engine->hangcheck.score += HUNG;
3200 stuck[id] = true;
3201 break;
3202 }
3203 }
3204 } else {
3205 engine->hangcheck.action = HANGCHECK_ACTIVE;
3206
3207 /* Gradually reduce the count so that we catch DoS
3208 * attempts across multiple batches.
3209 */
3210 if (engine->hangcheck.score > 0)
3211 engine->hangcheck.score -= ACTIVE_DECAY;
3212 if (engine->hangcheck.score < 0)
3213 engine->hangcheck.score = 0;
3214
3215 /* Clear head and subunit states on seqno movement */
3216 acthd = 0;
3217
3218 memset(engine->hangcheck.instdone, 0,
3219 sizeof(engine->hangcheck.instdone));
3220 }
3221
3222 engine->hangcheck.seqno = seqno;
3223 engine->hangcheck.acthd = acthd;
3224 engine->hangcheck.user_interrupts = user_interrupts;
3225 busy_count += busy;
3226 }
3227
3228 for_each_engine_id(engine, dev_priv, id) {
3229 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3230 DRM_INFO("%s on %s\n",
3231 stuck[id] ? "stuck" : "no progress",
3232 engine->name);
3233 rings_hung |= intel_engine_flag(engine);
3234 }
3235 }
3236
3237 if (rings_hung) {
3238 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3239 goto out;
3240 }
3241
3242 /* Reset timer in case GPU hangs without another request being added */
3243 if (busy_count)
3244 i915_queue_hangcheck(dev_priv);
3245
3246 out:
3247 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3248 }
3249
3250 static void ibx_irq_reset(struct drm_device *dev)
3251 {
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253
3254 if (HAS_PCH_NOP(dev))
3255 return;
3256
3257 GEN5_IRQ_RESET(SDE);
3258
3259 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3260 I915_WRITE(SERR_INT, 0xffffffff);
3261 }
3262
3263 /*
3264 * SDEIER is also touched by the interrupt handler to work around missed PCH
3265 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3266 * instead we unconditionally enable all PCH interrupt sources here, but then
3267 * only unmask them as needed with SDEIMR.
3268 *
3269 * This function needs to be called before interrupts are enabled.
3270 */
3271 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3272 {
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275 if (HAS_PCH_NOP(dev))
3276 return;
3277
3278 WARN_ON(I915_READ(SDEIER) != 0);
3279 I915_WRITE(SDEIER, 0xffffffff);
3280 POSTING_READ(SDEIER);
3281 }
3282
3283 static void gen5_gt_irq_reset(struct drm_device *dev)
3284 {
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286
3287 GEN5_IRQ_RESET(GT);
3288 if (INTEL_INFO(dev)->gen >= 6)
3289 GEN5_IRQ_RESET(GEN6_PM);
3290 }
3291
3292 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3293 {
3294 enum pipe pipe;
3295
3296 if (IS_CHERRYVIEW(dev_priv))
3297 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3298 else
3299 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3300
3301 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3302 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3303
3304 for_each_pipe(dev_priv, pipe) {
3305 I915_WRITE(PIPESTAT(pipe),
3306 PIPE_FIFO_UNDERRUN_STATUS |
3307 PIPESTAT_INT_STATUS_MASK);
3308 dev_priv->pipestat_irq_mask[pipe] = 0;
3309 }
3310
3311 GEN5_IRQ_RESET(VLV_);
3312 dev_priv->irq_mask = ~0;
3313 }
3314
3315 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3316 {
3317 u32 pipestat_mask;
3318 u32 enable_mask;
3319 enum pipe pipe;
3320
3321 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3322 PIPE_CRC_DONE_INTERRUPT_STATUS;
3323
3324 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3325 for_each_pipe(dev_priv, pipe)
3326 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3327
3328 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3329 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3330 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3331 if (IS_CHERRYVIEW(dev_priv))
3332 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3333
3334 WARN_ON(dev_priv->irq_mask != ~0);
3335
3336 dev_priv->irq_mask = ~enable_mask;
3337
3338 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3339 }
3340
3341 /* drm_dma.h hooks
3342 */
3343 static void ironlake_irq_reset(struct drm_device *dev)
3344 {
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346
3347 I915_WRITE(HWSTAM, 0xffffffff);
3348
3349 GEN5_IRQ_RESET(DE);
3350 if (IS_GEN7(dev))
3351 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3352
3353 gen5_gt_irq_reset(dev);
3354
3355 ibx_irq_reset(dev);
3356 }
3357
3358 static void valleyview_irq_preinstall(struct drm_device *dev)
3359 {
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361
3362 I915_WRITE(VLV_MASTER_IER, 0);
3363 POSTING_READ(VLV_MASTER_IER);
3364
3365 gen5_gt_irq_reset(dev);
3366
3367 spin_lock_irq(&dev_priv->irq_lock);
3368 if (dev_priv->display_irqs_enabled)
3369 vlv_display_irq_reset(dev_priv);
3370 spin_unlock_irq(&dev_priv->irq_lock);
3371 }
3372
3373 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3374 {
3375 GEN8_IRQ_RESET_NDX(GT, 0);
3376 GEN8_IRQ_RESET_NDX(GT, 1);
3377 GEN8_IRQ_RESET_NDX(GT, 2);
3378 GEN8_IRQ_RESET_NDX(GT, 3);
3379 }
3380
3381 static void gen8_irq_reset(struct drm_device *dev)
3382 {
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 int pipe;
3385
3386 I915_WRITE(GEN8_MASTER_IRQ, 0);
3387 POSTING_READ(GEN8_MASTER_IRQ);
3388
3389 gen8_gt_irq_reset(dev_priv);
3390
3391 for_each_pipe(dev_priv, pipe)
3392 if (intel_display_power_is_enabled(dev_priv,
3393 POWER_DOMAIN_PIPE(pipe)))
3394 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3395
3396 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3397 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3398 GEN5_IRQ_RESET(GEN8_PCU_);
3399
3400 if (HAS_PCH_SPLIT(dev))
3401 ibx_irq_reset(dev);
3402 }
3403
3404 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3405 unsigned int pipe_mask)
3406 {
3407 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3408 enum pipe pipe;
3409
3410 spin_lock_irq(&dev_priv->irq_lock);
3411 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3412 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3413 dev_priv->de_irq_mask[pipe],
3414 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3415 spin_unlock_irq(&dev_priv->irq_lock);
3416 }
3417
3418 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3419 unsigned int pipe_mask)
3420 {
3421 enum pipe pipe;
3422
3423 spin_lock_irq(&dev_priv->irq_lock);
3424 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3425 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3426 spin_unlock_irq(&dev_priv->irq_lock);
3427
3428 /* make sure we're done processing display irqs */
3429 synchronize_irq(dev_priv->dev->irq);
3430 }
3431
3432 static void cherryview_irq_preinstall(struct drm_device *dev)
3433 {
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435
3436 I915_WRITE(GEN8_MASTER_IRQ, 0);
3437 POSTING_READ(GEN8_MASTER_IRQ);
3438
3439 gen8_gt_irq_reset(dev_priv);
3440
3441 GEN5_IRQ_RESET(GEN8_PCU_);
3442
3443 spin_lock_irq(&dev_priv->irq_lock);
3444 if (dev_priv->display_irqs_enabled)
3445 vlv_display_irq_reset(dev_priv);
3446 spin_unlock_irq(&dev_priv->irq_lock);
3447 }
3448
3449 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3450 const u32 hpd[HPD_NUM_PINS])
3451 {
3452 struct intel_encoder *encoder;
3453 u32 enabled_irqs = 0;
3454
3455 for_each_intel_encoder(dev_priv->dev, encoder)
3456 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3457 enabled_irqs |= hpd[encoder->hpd_pin];
3458
3459 return enabled_irqs;
3460 }
3461
3462 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3463 {
3464 u32 hotplug_irqs, hotplug, enabled_irqs;
3465
3466 if (HAS_PCH_IBX(dev_priv)) {
3467 hotplug_irqs = SDE_HOTPLUG_MASK;
3468 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3469 } else {
3470 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3471 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3472 }
3473
3474 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3475
3476 /*
3477 * Enable digital hotplug on the PCH, and configure the DP short pulse
3478 * duration to 2ms (which is the minimum in the Display Port spec).
3479 * The pulse duration bits are reserved on LPT+.
3480 */
3481 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3482 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3483 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3484 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3485 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3486 /*
3487 * When CPU and PCH are on the same package, port A
3488 * HPD must be enabled in both north and south.
3489 */
3490 if (HAS_PCH_LPT_LP(dev_priv))
3491 hotplug |= PORTA_HOTPLUG_ENABLE;
3492 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3493 }
3494
3495 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3496 {
3497 u32 hotplug_irqs, hotplug, enabled_irqs;
3498
3499 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3500 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3501
3502 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3503
3504 /* Enable digital hotplug on the PCH */
3505 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3506 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3507 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3508 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3509
3510 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3511 hotplug |= PORTE_HOTPLUG_ENABLE;
3512 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3513 }
3514
3515 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3516 {
3517 u32 hotplug_irqs, hotplug, enabled_irqs;
3518
3519 if (INTEL_GEN(dev_priv) >= 8) {
3520 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3521 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3522
3523 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3524 } else if (INTEL_GEN(dev_priv) >= 7) {
3525 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3526 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3527
3528 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3529 } else {
3530 hotplug_irqs = DE_DP_A_HOTPLUG;
3531 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3532
3533 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3534 }
3535
3536 /*
3537 * Enable digital hotplug on the CPU, and configure the DP short pulse
3538 * duration to 2ms (which is the minimum in the Display Port spec)
3539 * The pulse duration bits are reserved on HSW+.
3540 */
3541 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3542 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3543 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3544 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3545
3546 ibx_hpd_irq_setup(dev_priv);
3547 }
3548
3549 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3550 {
3551 u32 hotplug_irqs, hotplug, enabled_irqs;
3552
3553 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3554 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3555
3556 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3557
3558 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3559 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3560 PORTA_HOTPLUG_ENABLE;
3561
3562 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3563 hotplug, enabled_irqs);
3564 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3565
3566 /*
3567 * For BXT invert bit has to be set based on AOB design
3568 * for HPD detection logic, update it based on VBT fields.
3569 */
3570
3571 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3572 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3573 hotplug |= BXT_DDIA_HPD_INVERT;
3574 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3575 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3576 hotplug |= BXT_DDIB_HPD_INVERT;
3577 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3578 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3579 hotplug |= BXT_DDIC_HPD_INVERT;
3580
3581 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3582 }
3583
3584 static void ibx_irq_postinstall(struct drm_device *dev)
3585 {
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 u32 mask;
3588
3589 if (HAS_PCH_NOP(dev))
3590 return;
3591
3592 if (HAS_PCH_IBX(dev))
3593 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3594 else
3595 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3596
3597 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3598 I915_WRITE(SDEIMR, ~mask);
3599 }
3600
3601 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3602 {
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 u32 pm_irqs, gt_irqs;
3605
3606 pm_irqs = gt_irqs = 0;
3607
3608 dev_priv->gt_irq_mask = ~0;
3609 if (HAS_L3_DPF(dev)) {
3610 /* L3 parity interrupt is always unmasked. */
3611 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3612 gt_irqs |= GT_PARITY_ERROR(dev);
3613 }
3614
3615 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3616 if (IS_GEN5(dev)) {
3617 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3618 ILK_BSD_USER_INTERRUPT;
3619 } else {
3620 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3621 }
3622
3623 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3624
3625 if (INTEL_INFO(dev)->gen >= 6) {
3626 /*
3627 * RPS interrupts will get enabled/disabled on demand when RPS
3628 * itself is enabled/disabled.
3629 */
3630 if (HAS_VEBOX(dev))
3631 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3632
3633 dev_priv->pm_irq_mask = 0xffffffff;
3634 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3635 }
3636 }
3637
3638 static int ironlake_irq_postinstall(struct drm_device *dev)
3639 {
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 u32 display_mask, extra_mask;
3642
3643 if (INTEL_INFO(dev)->gen >= 7) {
3644 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3645 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3646 DE_PLANEB_FLIP_DONE_IVB |
3647 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3648 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3649 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3650 DE_DP_A_HOTPLUG_IVB);
3651 } else {
3652 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3653 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3654 DE_AUX_CHANNEL_A |
3655 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3656 DE_POISON);
3657 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3658 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3659 DE_DP_A_HOTPLUG);
3660 }
3661
3662 dev_priv->irq_mask = ~display_mask;
3663
3664 I915_WRITE(HWSTAM, 0xeffe);
3665
3666 ibx_irq_pre_postinstall(dev);
3667
3668 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3669
3670 gen5_gt_irq_postinstall(dev);
3671
3672 ibx_irq_postinstall(dev);
3673
3674 if (IS_IRONLAKE_M(dev)) {
3675 /* Enable PCU event interrupts
3676 *
3677 * spinlocking not required here for correctness since interrupt
3678 * setup is guaranteed to run in single-threaded context. But we
3679 * need it to make the assert_spin_locked happy. */
3680 spin_lock_irq(&dev_priv->irq_lock);
3681 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3682 spin_unlock_irq(&dev_priv->irq_lock);
3683 }
3684
3685 return 0;
3686 }
3687
3688 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3689 {
3690 assert_spin_locked(&dev_priv->irq_lock);
3691
3692 if (dev_priv->display_irqs_enabled)
3693 return;
3694
3695 dev_priv->display_irqs_enabled = true;
3696
3697 if (intel_irqs_enabled(dev_priv)) {
3698 vlv_display_irq_reset(dev_priv);
3699 vlv_display_irq_postinstall(dev_priv);
3700 }
3701 }
3702
3703 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3704 {
3705 assert_spin_locked(&dev_priv->irq_lock);
3706
3707 if (!dev_priv->display_irqs_enabled)
3708 return;
3709
3710 dev_priv->display_irqs_enabled = false;
3711
3712 if (intel_irqs_enabled(dev_priv))
3713 vlv_display_irq_reset(dev_priv);
3714 }
3715
3716
3717 static int valleyview_irq_postinstall(struct drm_device *dev)
3718 {
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720
3721 gen5_gt_irq_postinstall(dev);
3722
3723 spin_lock_irq(&dev_priv->irq_lock);
3724 if (dev_priv->display_irqs_enabled)
3725 vlv_display_irq_postinstall(dev_priv);
3726 spin_unlock_irq(&dev_priv->irq_lock);
3727
3728 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3729 POSTING_READ(VLV_MASTER_IER);
3730
3731 return 0;
3732 }
3733
3734 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3735 {
3736 /* These are interrupts we'll toggle with the ring mask register */
3737 uint32_t gt_interrupts[] = {
3738 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3739 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3740 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3741 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3742 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3743 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3744 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3745 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3746 0,
3747 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3748 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3749 };
3750
3751 if (HAS_L3_DPF(dev_priv))
3752 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3753
3754 dev_priv->pm_irq_mask = 0xffffffff;
3755 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3756 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3757 /*
3758 * RPS interrupts will get enabled/disabled on demand when RPS itself
3759 * is enabled/disabled.
3760 */
3761 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3762 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3763 }
3764
3765 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3766 {
3767 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3768 uint32_t de_pipe_enables;
3769 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3770 u32 de_port_enables;
3771 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3772 enum pipe pipe;
3773
3774 if (INTEL_INFO(dev_priv)->gen >= 9) {
3775 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3776 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3777 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3778 GEN9_AUX_CHANNEL_D;
3779 if (IS_BROXTON(dev_priv))
3780 de_port_masked |= BXT_DE_PORT_GMBUS;
3781 } else {
3782 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3783 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3784 }
3785
3786 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3787 GEN8_PIPE_FIFO_UNDERRUN;
3788
3789 de_port_enables = de_port_masked;
3790 if (IS_BROXTON(dev_priv))
3791 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3792 else if (IS_BROADWELL(dev_priv))
3793 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3794
3795 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3796 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3797 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3798
3799 for_each_pipe(dev_priv, pipe)
3800 if (intel_display_power_is_enabled(dev_priv,
3801 POWER_DOMAIN_PIPE(pipe)))
3802 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3803 dev_priv->de_irq_mask[pipe],
3804 de_pipe_enables);
3805
3806 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3807 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3808 }
3809
3810 static int gen8_irq_postinstall(struct drm_device *dev)
3811 {
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814 if (HAS_PCH_SPLIT(dev))
3815 ibx_irq_pre_postinstall(dev);
3816
3817 gen8_gt_irq_postinstall(dev_priv);
3818 gen8_de_irq_postinstall(dev_priv);
3819
3820 if (HAS_PCH_SPLIT(dev))
3821 ibx_irq_postinstall(dev);
3822
3823 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3824 POSTING_READ(GEN8_MASTER_IRQ);
3825
3826 return 0;
3827 }
3828
3829 static int cherryview_irq_postinstall(struct drm_device *dev)
3830 {
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832
3833 gen8_gt_irq_postinstall(dev_priv);
3834
3835 spin_lock_irq(&dev_priv->irq_lock);
3836 if (dev_priv->display_irqs_enabled)
3837 vlv_display_irq_postinstall(dev_priv);
3838 spin_unlock_irq(&dev_priv->irq_lock);
3839
3840 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3841 POSTING_READ(GEN8_MASTER_IRQ);
3842
3843 return 0;
3844 }
3845
3846 static void gen8_irq_uninstall(struct drm_device *dev)
3847 {
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849
3850 if (!dev_priv)
3851 return;
3852
3853 gen8_irq_reset(dev);
3854 }
3855
3856 static void valleyview_irq_uninstall(struct drm_device *dev)
3857 {
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859
3860 if (!dev_priv)
3861 return;
3862
3863 I915_WRITE(VLV_MASTER_IER, 0);
3864 POSTING_READ(VLV_MASTER_IER);
3865
3866 gen5_gt_irq_reset(dev);
3867
3868 I915_WRITE(HWSTAM, 0xffffffff);
3869
3870 spin_lock_irq(&dev_priv->irq_lock);
3871 if (dev_priv->display_irqs_enabled)
3872 vlv_display_irq_reset(dev_priv);
3873 spin_unlock_irq(&dev_priv->irq_lock);
3874 }
3875
3876 static void cherryview_irq_uninstall(struct drm_device *dev)
3877 {
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880 if (!dev_priv)
3881 return;
3882
3883 I915_WRITE(GEN8_MASTER_IRQ, 0);
3884 POSTING_READ(GEN8_MASTER_IRQ);
3885
3886 gen8_gt_irq_reset(dev_priv);
3887
3888 GEN5_IRQ_RESET(GEN8_PCU_);
3889
3890 spin_lock_irq(&dev_priv->irq_lock);
3891 if (dev_priv->display_irqs_enabled)
3892 vlv_display_irq_reset(dev_priv);
3893 spin_unlock_irq(&dev_priv->irq_lock);
3894 }
3895
3896 static void ironlake_irq_uninstall(struct drm_device *dev)
3897 {
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899
3900 if (!dev_priv)
3901 return;
3902
3903 ironlake_irq_reset(dev);
3904 }
3905
3906 static void i8xx_irq_preinstall(struct drm_device * dev)
3907 {
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909 int pipe;
3910
3911 for_each_pipe(dev_priv, pipe)
3912 I915_WRITE(PIPESTAT(pipe), 0);
3913 I915_WRITE16(IMR, 0xffff);
3914 I915_WRITE16(IER, 0x0);
3915 POSTING_READ16(IER);
3916 }
3917
3918 static int i8xx_irq_postinstall(struct drm_device *dev)
3919 {
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921
3922 I915_WRITE16(EMR,
3923 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3924
3925 /* Unmask the interrupts that we always want on. */
3926 dev_priv->irq_mask =
3927 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3928 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3929 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3930 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3931 I915_WRITE16(IMR, dev_priv->irq_mask);
3932
3933 I915_WRITE16(IER,
3934 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3935 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3936 I915_USER_INTERRUPT);
3937 POSTING_READ16(IER);
3938
3939 /* Interrupt setup is already guaranteed to be single-threaded, this is
3940 * just to make the assert_spin_locked check happy. */
3941 spin_lock_irq(&dev_priv->irq_lock);
3942 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3943 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3944 spin_unlock_irq(&dev_priv->irq_lock);
3945
3946 return 0;
3947 }
3948
3949 /*
3950 * Returns true when a page flip has completed.
3951 */
3952 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3953 int plane, int pipe, u32 iir)
3954 {
3955 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3956
3957 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3958 return false;
3959
3960 if ((iir & flip_pending) == 0)
3961 goto check_page_flip;
3962
3963 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3964 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3965 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3966 * the flip is completed (no longer pending). Since this doesn't raise
3967 * an interrupt per se, we watch for the change at vblank.
3968 */
3969 if (I915_READ16(ISR) & flip_pending)
3970 goto check_page_flip;
3971
3972 intel_finish_page_flip_cs(dev_priv, pipe);
3973 return true;
3974
3975 check_page_flip:
3976 intel_check_page_flip(dev_priv, pipe);
3977 return false;
3978 }
3979
3980 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3981 {
3982 struct drm_device *dev = arg;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 u16 iir, new_iir;
3985 u32 pipe_stats[2];
3986 int pipe;
3987 u16 flip_mask =
3988 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3989 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3990 irqreturn_t ret;
3991
3992 if (!intel_irqs_enabled(dev_priv))
3993 return IRQ_NONE;
3994
3995 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3996 disable_rpm_wakeref_asserts(dev_priv);
3997
3998 ret = IRQ_NONE;
3999 iir = I915_READ16(IIR);
4000 if (iir == 0)
4001 goto out;
4002
4003 while (iir & ~flip_mask) {
4004 /* Can't rely on pipestat interrupt bit in iir as it might
4005 * have been cleared after the pipestat interrupt was received.
4006 * It doesn't set the bit in iir again, but it still produces
4007 * interrupts (for non-MSI).
4008 */
4009 spin_lock(&dev_priv->irq_lock);
4010 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4011 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4012
4013 for_each_pipe(dev_priv, pipe) {
4014 i915_reg_t reg = PIPESTAT(pipe);
4015 pipe_stats[pipe] = I915_READ(reg);
4016
4017 /*
4018 * Clear the PIPE*STAT regs before the IIR
4019 */
4020 if (pipe_stats[pipe] & 0x8000ffff)
4021 I915_WRITE(reg, pipe_stats[pipe]);
4022 }
4023 spin_unlock(&dev_priv->irq_lock);
4024
4025 I915_WRITE16(IIR, iir & ~flip_mask);
4026 new_iir = I915_READ16(IIR); /* Flush posted writes */
4027
4028 if (iir & I915_USER_INTERRUPT)
4029 notify_ring(&dev_priv->engine[RCS]);
4030
4031 for_each_pipe(dev_priv, pipe) {
4032 int plane = pipe;
4033 if (HAS_FBC(dev_priv))
4034 plane = !plane;
4035
4036 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4037 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4038 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4039
4040 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4041 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4042
4043 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4044 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4045 pipe);
4046 }
4047
4048 iir = new_iir;
4049 }
4050 ret = IRQ_HANDLED;
4051
4052 out:
4053 enable_rpm_wakeref_asserts(dev_priv);
4054
4055 return ret;
4056 }
4057
4058 static void i8xx_irq_uninstall(struct drm_device * dev)
4059 {
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 int pipe;
4062
4063 for_each_pipe(dev_priv, pipe) {
4064 /* Clear enable bits; then clear status bits */
4065 I915_WRITE(PIPESTAT(pipe), 0);
4066 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4067 }
4068 I915_WRITE16(IMR, 0xffff);
4069 I915_WRITE16(IER, 0x0);
4070 I915_WRITE16(IIR, I915_READ16(IIR));
4071 }
4072
4073 static void i915_irq_preinstall(struct drm_device * dev)
4074 {
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 int pipe;
4077
4078 if (I915_HAS_HOTPLUG(dev)) {
4079 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4080 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4081 }
4082
4083 I915_WRITE16(HWSTAM, 0xeffe);
4084 for_each_pipe(dev_priv, pipe)
4085 I915_WRITE(PIPESTAT(pipe), 0);
4086 I915_WRITE(IMR, 0xffffffff);
4087 I915_WRITE(IER, 0x0);
4088 POSTING_READ(IER);
4089 }
4090
4091 static int i915_irq_postinstall(struct drm_device *dev)
4092 {
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 u32 enable_mask;
4095
4096 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4097
4098 /* Unmask the interrupts that we always want on. */
4099 dev_priv->irq_mask =
4100 ~(I915_ASLE_INTERRUPT |
4101 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4102 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4103 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4104 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4105
4106 enable_mask =
4107 I915_ASLE_INTERRUPT |
4108 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4109 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4110 I915_USER_INTERRUPT;
4111
4112 if (I915_HAS_HOTPLUG(dev)) {
4113 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4114 POSTING_READ(PORT_HOTPLUG_EN);
4115
4116 /* Enable in IER... */
4117 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4118 /* and unmask in IMR */
4119 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4120 }
4121
4122 I915_WRITE(IMR, dev_priv->irq_mask);
4123 I915_WRITE(IER, enable_mask);
4124 POSTING_READ(IER);
4125
4126 i915_enable_asle_pipestat(dev_priv);
4127
4128 /* Interrupt setup is already guaranteed to be single-threaded, this is
4129 * just to make the assert_spin_locked check happy. */
4130 spin_lock_irq(&dev_priv->irq_lock);
4131 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4132 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4133 spin_unlock_irq(&dev_priv->irq_lock);
4134
4135 return 0;
4136 }
4137
4138 /*
4139 * Returns true when a page flip has completed.
4140 */
4141 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4142 int plane, int pipe, u32 iir)
4143 {
4144 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4145
4146 if (!intel_pipe_handle_vblank(dev_priv, pipe))
4147 return false;
4148
4149 if ((iir & flip_pending) == 0)
4150 goto check_page_flip;
4151
4152 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4153 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4154 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4155 * the flip is completed (no longer pending). Since this doesn't raise
4156 * an interrupt per se, we watch for the change at vblank.
4157 */
4158 if (I915_READ(ISR) & flip_pending)
4159 goto check_page_flip;
4160
4161 intel_finish_page_flip_cs(dev_priv, pipe);
4162 return true;
4163
4164 check_page_flip:
4165 intel_check_page_flip(dev_priv, pipe);
4166 return false;
4167 }
4168
4169 static irqreturn_t i915_irq_handler(int irq, void *arg)
4170 {
4171 struct drm_device *dev = arg;
4172 struct drm_i915_private *dev_priv = dev->dev_private;
4173 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4174 u32 flip_mask =
4175 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4176 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4177 int pipe, ret = IRQ_NONE;
4178
4179 if (!intel_irqs_enabled(dev_priv))
4180 return IRQ_NONE;
4181
4182 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4183 disable_rpm_wakeref_asserts(dev_priv);
4184
4185 iir = I915_READ(IIR);
4186 do {
4187 bool irq_received = (iir & ~flip_mask) != 0;
4188 bool blc_event = false;
4189
4190 /* Can't rely on pipestat interrupt bit in iir as it might
4191 * have been cleared after the pipestat interrupt was received.
4192 * It doesn't set the bit in iir again, but it still produces
4193 * interrupts (for non-MSI).
4194 */
4195 spin_lock(&dev_priv->irq_lock);
4196 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4197 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4198
4199 for_each_pipe(dev_priv, pipe) {
4200 i915_reg_t reg = PIPESTAT(pipe);
4201 pipe_stats[pipe] = I915_READ(reg);
4202
4203 /* Clear the PIPE*STAT regs before the IIR */
4204 if (pipe_stats[pipe] & 0x8000ffff) {
4205 I915_WRITE(reg, pipe_stats[pipe]);
4206 irq_received = true;
4207 }
4208 }
4209 spin_unlock(&dev_priv->irq_lock);
4210
4211 if (!irq_received)
4212 break;
4213
4214 /* Consume port. Then clear IIR or we'll miss events */
4215 if (I915_HAS_HOTPLUG(dev_priv) &&
4216 iir & I915_DISPLAY_PORT_INTERRUPT) {
4217 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4218 if (hotplug_status)
4219 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4220 }
4221
4222 I915_WRITE(IIR, iir & ~flip_mask);
4223 new_iir = I915_READ(IIR); /* Flush posted writes */
4224
4225 if (iir & I915_USER_INTERRUPT)
4226 notify_ring(&dev_priv->engine[RCS]);
4227
4228 for_each_pipe(dev_priv, pipe) {
4229 int plane = pipe;
4230 if (HAS_FBC(dev_priv))
4231 plane = !plane;
4232
4233 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4234 i915_handle_vblank(dev_priv, plane, pipe, iir))
4235 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4236
4237 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4238 blc_event = true;
4239
4240 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4241 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4242
4243 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4244 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4245 pipe);
4246 }
4247
4248 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4249 intel_opregion_asle_intr(dev_priv);
4250
4251 /* With MSI, interrupts are only generated when iir
4252 * transitions from zero to nonzero. If another bit got
4253 * set while we were handling the existing iir bits, then
4254 * we would never get another interrupt.
4255 *
4256 * This is fine on non-MSI as well, as if we hit this path
4257 * we avoid exiting the interrupt handler only to generate
4258 * another one.
4259 *
4260 * Note that for MSI this could cause a stray interrupt report
4261 * if an interrupt landed in the time between writing IIR and
4262 * the posting read. This should be rare enough to never
4263 * trigger the 99% of 100,000 interrupts test for disabling
4264 * stray interrupts.
4265 */
4266 ret = IRQ_HANDLED;
4267 iir = new_iir;
4268 } while (iir & ~flip_mask);
4269
4270 enable_rpm_wakeref_asserts(dev_priv);
4271
4272 return ret;
4273 }
4274
4275 static void i915_irq_uninstall(struct drm_device * dev)
4276 {
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 int pipe;
4279
4280 if (I915_HAS_HOTPLUG(dev)) {
4281 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4282 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4283 }
4284
4285 I915_WRITE16(HWSTAM, 0xffff);
4286 for_each_pipe(dev_priv, pipe) {
4287 /* Clear enable bits; then clear status bits */
4288 I915_WRITE(PIPESTAT(pipe), 0);
4289 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4290 }
4291 I915_WRITE(IMR, 0xffffffff);
4292 I915_WRITE(IER, 0x0);
4293
4294 I915_WRITE(IIR, I915_READ(IIR));
4295 }
4296
4297 static void i965_irq_preinstall(struct drm_device * dev)
4298 {
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 int pipe;
4301
4302 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4303 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4304
4305 I915_WRITE(HWSTAM, 0xeffe);
4306 for_each_pipe(dev_priv, pipe)
4307 I915_WRITE(PIPESTAT(pipe), 0);
4308 I915_WRITE(IMR, 0xffffffff);
4309 I915_WRITE(IER, 0x0);
4310 POSTING_READ(IER);
4311 }
4312
4313 static int i965_irq_postinstall(struct drm_device *dev)
4314 {
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 u32 enable_mask;
4317 u32 error_mask;
4318
4319 /* Unmask the interrupts that we always want on. */
4320 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4321 I915_DISPLAY_PORT_INTERRUPT |
4322 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4323 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4324 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4325 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4326 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4327
4328 enable_mask = ~dev_priv->irq_mask;
4329 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4330 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4331 enable_mask |= I915_USER_INTERRUPT;
4332
4333 if (IS_G4X(dev_priv))
4334 enable_mask |= I915_BSD_USER_INTERRUPT;
4335
4336 /* Interrupt setup is already guaranteed to be single-threaded, this is
4337 * just to make the assert_spin_locked check happy. */
4338 spin_lock_irq(&dev_priv->irq_lock);
4339 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4340 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4341 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4342 spin_unlock_irq(&dev_priv->irq_lock);
4343
4344 /*
4345 * Enable some error detection, note the instruction error mask
4346 * bit is reserved, so we leave it masked.
4347 */
4348 if (IS_G4X(dev_priv)) {
4349 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4350 GM45_ERROR_MEM_PRIV |
4351 GM45_ERROR_CP_PRIV |
4352 I915_ERROR_MEMORY_REFRESH);
4353 } else {
4354 error_mask = ~(I915_ERROR_PAGE_TABLE |
4355 I915_ERROR_MEMORY_REFRESH);
4356 }
4357 I915_WRITE(EMR, error_mask);
4358
4359 I915_WRITE(IMR, dev_priv->irq_mask);
4360 I915_WRITE(IER, enable_mask);
4361 POSTING_READ(IER);
4362
4363 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4364 POSTING_READ(PORT_HOTPLUG_EN);
4365
4366 i915_enable_asle_pipestat(dev_priv);
4367
4368 return 0;
4369 }
4370
4371 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4372 {
4373 u32 hotplug_en;
4374
4375 assert_spin_locked(&dev_priv->irq_lock);
4376
4377 /* Note HDMI and DP share hotplug bits */
4378 /* enable bits are the same for all generations */
4379 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4380 /* Programming the CRT detection parameters tends
4381 to generate a spurious hotplug event about three
4382 seconds later. So just do it once.
4383 */
4384 if (IS_G4X(dev_priv))
4385 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4386 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4387
4388 /* Ignore TV since it's buggy */
4389 i915_hotplug_interrupt_update_locked(dev_priv,
4390 HOTPLUG_INT_EN_MASK |
4391 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4392 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4393 hotplug_en);
4394 }
4395
4396 static irqreturn_t i965_irq_handler(int irq, void *arg)
4397 {
4398 struct drm_device *dev = arg;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 u32 iir, new_iir;
4401 u32 pipe_stats[I915_MAX_PIPES];
4402 int ret = IRQ_NONE, pipe;
4403 u32 flip_mask =
4404 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4405 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4406
4407 if (!intel_irqs_enabled(dev_priv))
4408 return IRQ_NONE;
4409
4410 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4411 disable_rpm_wakeref_asserts(dev_priv);
4412
4413 iir = I915_READ(IIR);
4414
4415 for (;;) {
4416 bool irq_received = (iir & ~flip_mask) != 0;
4417 bool blc_event = false;
4418
4419 /* Can't rely on pipestat interrupt bit in iir as it might
4420 * have been cleared after the pipestat interrupt was received.
4421 * It doesn't set the bit in iir again, but it still produces
4422 * interrupts (for non-MSI).
4423 */
4424 spin_lock(&dev_priv->irq_lock);
4425 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4426 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4427
4428 for_each_pipe(dev_priv, pipe) {
4429 i915_reg_t reg = PIPESTAT(pipe);
4430 pipe_stats[pipe] = I915_READ(reg);
4431
4432 /*
4433 * Clear the PIPE*STAT regs before the IIR
4434 */
4435 if (pipe_stats[pipe] & 0x8000ffff) {
4436 I915_WRITE(reg, pipe_stats[pipe]);
4437 irq_received = true;
4438 }
4439 }
4440 spin_unlock(&dev_priv->irq_lock);
4441
4442 if (!irq_received)
4443 break;
4444
4445 ret = IRQ_HANDLED;
4446
4447 /* Consume port. Then clear IIR or we'll miss events */
4448 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4449 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4450 if (hotplug_status)
4451 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4452 }
4453
4454 I915_WRITE(IIR, iir & ~flip_mask);
4455 new_iir = I915_READ(IIR); /* Flush posted writes */
4456
4457 if (iir & I915_USER_INTERRUPT)
4458 notify_ring(&dev_priv->engine[RCS]);
4459 if (iir & I915_BSD_USER_INTERRUPT)
4460 notify_ring(&dev_priv->engine[VCS]);
4461
4462 for_each_pipe(dev_priv, pipe) {
4463 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4464 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4465 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4466
4467 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4468 blc_event = true;
4469
4470 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4471 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4472
4473 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4474 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4475 }
4476
4477 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4478 intel_opregion_asle_intr(dev_priv);
4479
4480 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4481 gmbus_irq_handler(dev_priv);
4482
4483 /* With MSI, interrupts are only generated when iir
4484 * transitions from zero to nonzero. If another bit got
4485 * set while we were handling the existing iir bits, then
4486 * we would never get another interrupt.
4487 *
4488 * This is fine on non-MSI as well, as if we hit this path
4489 * we avoid exiting the interrupt handler only to generate
4490 * another one.
4491 *
4492 * Note that for MSI this could cause a stray interrupt report
4493 * if an interrupt landed in the time between writing IIR and
4494 * the posting read. This should be rare enough to never
4495 * trigger the 99% of 100,000 interrupts test for disabling
4496 * stray interrupts.
4497 */
4498 iir = new_iir;
4499 }
4500
4501 enable_rpm_wakeref_asserts(dev_priv);
4502
4503 return ret;
4504 }
4505
4506 static void i965_irq_uninstall(struct drm_device * dev)
4507 {
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 int pipe;
4510
4511 if (!dev_priv)
4512 return;
4513
4514 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4515 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4516
4517 I915_WRITE(HWSTAM, 0xffffffff);
4518 for_each_pipe(dev_priv, pipe)
4519 I915_WRITE(PIPESTAT(pipe), 0);
4520 I915_WRITE(IMR, 0xffffffff);
4521 I915_WRITE(IER, 0x0);
4522
4523 for_each_pipe(dev_priv, pipe)
4524 I915_WRITE(PIPESTAT(pipe),
4525 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4526 I915_WRITE(IIR, I915_READ(IIR));
4527 }
4528
4529 /**
4530 * intel_irq_init - initializes irq support
4531 * @dev_priv: i915 device instance
4532 *
4533 * This function initializes all the irq support including work items, timers
4534 * and all the vtables. It does not setup the interrupt itself though.
4535 */
4536 void intel_irq_init(struct drm_i915_private *dev_priv)
4537 {
4538 struct drm_device *dev = dev_priv->dev;
4539
4540 intel_hpd_init_work(dev_priv);
4541
4542 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4543 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4544
4545 /* Let's track the enabled rps events */
4546 if (IS_VALLEYVIEW(dev_priv))
4547 /* WaGsvRC0ResidencyMethod:vlv */
4548 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4549 else
4550 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4551
4552 dev_priv->rps.pm_intr_keep = 0;
4553
4554 /*
4555 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4556 * if GEN6_PM_UP_EI_EXPIRED is masked.
4557 *
4558 * TODO: verify if this can be reproduced on VLV,CHV.
4559 */
4560 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4561 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4562
4563 if (INTEL_INFO(dev_priv)->gen >= 8)
4564 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4565
4566 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4567 i915_hangcheck_elapsed);
4568
4569 if (IS_GEN2(dev_priv)) {
4570 dev->max_vblank_count = 0;
4571 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4572 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4573 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4574 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4575 } else {
4576 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4577 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4578 }
4579
4580 /*
4581 * Opt out of the vblank disable timer on everything except gen2.
4582 * Gen2 doesn't have a hardware frame counter and so depends on
4583 * vblank interrupts to produce sane vblank seuquence numbers.
4584 */
4585 if (!IS_GEN2(dev_priv))
4586 dev->vblank_disable_immediate = true;
4587
4588 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4589 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4590
4591 if (IS_CHERRYVIEW(dev_priv)) {
4592 dev->driver->irq_handler = cherryview_irq_handler;
4593 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4594 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4595 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4596 dev->driver->enable_vblank = valleyview_enable_vblank;
4597 dev->driver->disable_vblank = valleyview_disable_vblank;
4598 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4599 } else if (IS_VALLEYVIEW(dev_priv)) {
4600 dev->driver->irq_handler = valleyview_irq_handler;
4601 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4602 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4603 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4604 dev->driver->enable_vblank = valleyview_enable_vblank;
4605 dev->driver->disable_vblank = valleyview_disable_vblank;
4606 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4607 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4608 dev->driver->irq_handler = gen8_irq_handler;
4609 dev->driver->irq_preinstall = gen8_irq_reset;
4610 dev->driver->irq_postinstall = gen8_irq_postinstall;
4611 dev->driver->irq_uninstall = gen8_irq_uninstall;
4612 dev->driver->enable_vblank = gen8_enable_vblank;
4613 dev->driver->disable_vblank = gen8_disable_vblank;
4614 if (IS_BROXTON(dev))
4615 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4616 else if (HAS_PCH_SPT(dev))
4617 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4618 else
4619 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4620 } else if (HAS_PCH_SPLIT(dev)) {
4621 dev->driver->irq_handler = ironlake_irq_handler;
4622 dev->driver->irq_preinstall = ironlake_irq_reset;
4623 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4624 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4625 dev->driver->enable_vblank = ironlake_enable_vblank;
4626 dev->driver->disable_vblank = ironlake_disable_vblank;
4627 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4628 } else {
4629 if (IS_GEN2(dev_priv)) {
4630 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4631 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4632 dev->driver->irq_handler = i8xx_irq_handler;
4633 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4634 } else if (IS_GEN3(dev_priv)) {
4635 dev->driver->irq_preinstall = i915_irq_preinstall;
4636 dev->driver->irq_postinstall = i915_irq_postinstall;
4637 dev->driver->irq_uninstall = i915_irq_uninstall;
4638 dev->driver->irq_handler = i915_irq_handler;
4639 } else {
4640 dev->driver->irq_preinstall = i965_irq_preinstall;
4641 dev->driver->irq_postinstall = i965_irq_postinstall;
4642 dev->driver->irq_uninstall = i965_irq_uninstall;
4643 dev->driver->irq_handler = i965_irq_handler;
4644 }
4645 if (I915_HAS_HOTPLUG(dev_priv))
4646 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4647 dev->driver->enable_vblank = i915_enable_vblank;
4648 dev->driver->disable_vblank = i915_disable_vblank;
4649 }
4650 }
4651
4652 /**
4653 * intel_irq_install - enables the hardware interrupt
4654 * @dev_priv: i915 device instance
4655 *
4656 * This function enables the hardware interrupt handling, but leaves the hotplug
4657 * handling still disabled. It is called after intel_irq_init().
4658 *
4659 * In the driver load and resume code we need working interrupts in a few places
4660 * but don't want to deal with the hassle of concurrent probe and hotplug
4661 * workers. Hence the split into this two-stage approach.
4662 */
4663 int intel_irq_install(struct drm_i915_private *dev_priv)
4664 {
4665 /*
4666 * We enable some interrupt sources in our postinstall hooks, so mark
4667 * interrupts as enabled _before_ actually enabling them to avoid
4668 * special cases in our ordering checks.
4669 */
4670 dev_priv->pm.irqs_enabled = true;
4671
4672 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4673 }
4674
4675 /**
4676 * intel_irq_uninstall - finilizes all irq handling
4677 * @dev_priv: i915 device instance
4678 *
4679 * This stops interrupt and hotplug handling and unregisters and frees all
4680 * resources acquired in the init functions.
4681 */
4682 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4683 {
4684 drm_irq_uninstall(dev_priv->dev);
4685 intel_hpd_cancel_work(dev_priv);
4686 dev_priv->pm.irqs_enabled = false;
4687 }
4688
4689 /**
4690 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4691 * @dev_priv: i915 device instance
4692 *
4693 * This function is used to disable interrupts at runtime, both in the runtime
4694 * pm and the system suspend/resume code.
4695 */
4696 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4697 {
4698 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4699 dev_priv->pm.irqs_enabled = false;
4700 synchronize_irq(dev_priv->dev->irq);
4701 }
4702
4703 /**
4704 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4705 * @dev_priv: i915 device instance
4706 *
4707 * This function is used to enable interrupts at runtime, both in the runtime
4708 * pm and the system suspend/resume code.
4709 */
4710 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4711 {
4712 dev_priv->pm.irqs_enabled = true;
4713 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4714 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4715 }
Linux kernel - Deliverables
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