Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27
28 typedef struct {
29 uint32_t reg;
30 } i915_reg_t;
31
32 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
33
34 #define INVALID_MMIO_REG _MMIO(0)
35
36 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
37 {
38 return reg.reg;
39 }
40
41 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
42 {
43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
44 }
45
46 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
47 {
48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
49 }
50
51 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
52 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
53 #define _PLANE(plane, a, b) _PIPE(plane, a, b)
54 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
55 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
56 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
57 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
58 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
59 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
60 (pipe) == PIPE_B ? (b) : (c))
61 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
62 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
63 (port) == PORT_B ? (b) : (c))
64 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
65
66 #define _MASKED_FIELD(mask, value) ({ \
67 if (__builtin_constant_p(mask)) \
68 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
69 if (__builtin_constant_p(value)) \
70 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
71 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
72 BUILD_BUG_ON_MSG((value) & ~(mask), \
73 "Incorrect value for mask"); \
74 (mask) << 16 | (value); })
75 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
76 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
77
78
79
80 /* PCI config space */
81
82 #define MCHBAR_I915 0x44
83 #define MCHBAR_I965 0x48
84 #define MCHBAR_SIZE (4 * 4096)
85
86 #define DEVEN 0x54
87 #define DEVEN_MCHBAR_EN (1 << 28)
88
89 #define BSM 0x5c
90 #define BSM_MASK (0xFFFF << 20)
91
92 #define HPLLCC 0xc0 /* 85x only */
93 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
94 #define GC_CLOCK_133_200 (0 << 0)
95 #define GC_CLOCK_100_200 (1 << 0)
96 #define GC_CLOCK_100_133 (2 << 0)
97 #define GC_CLOCK_133_266 (3 << 0)
98 #define GC_CLOCK_133_200_2 (4 << 0)
99 #define GC_CLOCK_133_266_2 (5 << 0)
100 #define GC_CLOCK_166_266 (6 << 0)
101 #define GC_CLOCK_166_250 (7 << 0)
102
103 #define I915_GDRST 0xc0 /* PCI config register */
104 #define GRDOM_FULL (0 << 2)
105 #define GRDOM_RENDER (1 << 2)
106 #define GRDOM_MEDIA (3 << 2)
107 #define GRDOM_MASK (3 << 2)
108 #define GRDOM_RESET_STATUS (1 << 1)
109 #define GRDOM_RESET_ENABLE (1 << 0)
110
111 #define GCDGMBUS 0xcc
112
113 #define GCFGC2 0xda
114 #define GCFGC 0xf0 /* 915+ only */
115 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
116 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
117 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
118 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
119 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
120 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
121 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
122 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
123 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
124 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
125 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
126 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
127 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
128 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
129 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
130 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
131 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
132 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
133 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
134 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
135 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
136 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
137 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
138 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
139 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
140 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
141 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
142 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
143 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
144
145 #define ASLE 0xe4
146 #define ASLS 0xfc
147
148 #define SWSCI 0xe8
149 #define SWSCI_SCISEL (1 << 15)
150 #define SWSCI_GSSCIE (1 << 0)
151
152 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
153
154
155 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
156 #define ILK_GRDOM_FULL (0<<1)
157 #define ILK_GRDOM_RENDER (1<<1)
158 #define ILK_GRDOM_MEDIA (3<<1)
159 #define ILK_GRDOM_MASK (3<<1)
160 #define ILK_GRDOM_RESET_ENABLE (1<<0)
161
162 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
163 #define GEN6_MBC_SNPCR_SHIFT 21
164 #define GEN6_MBC_SNPCR_MASK (3<<21)
165 #define GEN6_MBC_SNPCR_MAX (0<<21)
166 #define GEN6_MBC_SNPCR_MED (1<<21)
167 #define GEN6_MBC_SNPCR_LOW (2<<21)
168 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
169
170 #define VLV_G3DCTL _MMIO(0x9024)
171 #define VLV_GSCKGCTL _MMIO(0x9028)
172
173 #define GEN6_MBCTL _MMIO(0x0907c)
174 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
175 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
176 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
177 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
178 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
179
180 #define GEN6_GDRST _MMIO(0x941c)
181 #define GEN6_GRDOM_FULL (1 << 0)
182 #define GEN6_GRDOM_RENDER (1 << 1)
183 #define GEN6_GRDOM_MEDIA (1 << 2)
184 #define GEN6_GRDOM_BLT (1 << 3)
185 #define GEN6_GRDOM_VECS (1 << 4)
186 #define GEN9_GRDOM_GUC (1 << 5)
187 #define GEN8_GRDOM_MEDIA2 (1 << 7)
188
189 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
190 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
191 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
192 #define PP_DIR_DCLV_2G 0xffffffff
193
194 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
195 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8)
196
197 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
198 #define GEN8_RPCS_ENABLE (1 << 31)
199 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
200 #define GEN8_RPCS_S_CNT_SHIFT 15
201 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
202 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
203 #define GEN8_RPCS_SS_CNT_SHIFT 8
204 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
205 #define GEN8_RPCS_EU_MAX_SHIFT 4
206 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
207 #define GEN8_RPCS_EU_MIN_SHIFT 0
208 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
209
210 #define GAM_ECOCHK _MMIO(0x4090)
211 #define BDW_DISABLE_HDC_INVALIDATION (1<<25)
212 #define ECOCHK_SNB_BIT (1<<10)
213 #define ECOCHK_DIS_TLB (1<<8)
214 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
215 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
216 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
217 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
218 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
219 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
220 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
221 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
222
223 #define GEN8_CONFIG0 _MMIO(0xD00)
224 #define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
225
226 #define GAC_ECO_BITS _MMIO(0x14090)
227 #define ECOBITS_SNB_BIT (1<<13)
228 #define ECOBITS_PPGTT_CACHE64B (3<<8)
229 #define ECOBITS_PPGTT_CACHE4B (0<<8)
230
231 #define GAB_CTL _MMIO(0x24000)
232 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
233
234 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
235 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
236 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
237 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
238 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
239 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
240 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
241 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
242 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
243 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
244 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
245 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
246 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
247 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
248 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
249 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
250
251 /* VGA stuff */
252
253 #define VGA_ST01_MDA 0x3ba
254 #define VGA_ST01_CGA 0x3da
255
256 #define _VGA_MSR_WRITE _MMIO(0x3c2)
257 #define VGA_MSR_WRITE 0x3c2
258 #define VGA_MSR_READ 0x3cc
259 #define VGA_MSR_MEM_EN (1<<1)
260 #define VGA_MSR_CGA_MODE (1<<0)
261
262 #define VGA_SR_INDEX 0x3c4
263 #define SR01 1
264 #define VGA_SR_DATA 0x3c5
265
266 #define VGA_AR_INDEX 0x3c0
267 #define VGA_AR_VID_EN (1<<5)
268 #define VGA_AR_DATA_WRITE 0x3c0
269 #define VGA_AR_DATA_READ 0x3c1
270
271 #define VGA_GR_INDEX 0x3ce
272 #define VGA_GR_DATA 0x3cf
273 /* GR05 */
274 #define VGA_GR_MEM_READ_MODE_SHIFT 3
275 #define VGA_GR_MEM_READ_MODE_PLANE 1
276 /* GR06 */
277 #define VGA_GR_MEM_MODE_MASK 0xc
278 #define VGA_GR_MEM_MODE_SHIFT 2
279 #define VGA_GR_MEM_A0000_AFFFF 0
280 #define VGA_GR_MEM_A0000_BFFFF 1
281 #define VGA_GR_MEM_B0000_B7FFF 2
282 #define VGA_GR_MEM_B0000_BFFFF 3
283
284 #define VGA_DACMASK 0x3c6
285 #define VGA_DACRX 0x3c7
286 #define VGA_DACWX 0x3c8
287 #define VGA_DACDATA 0x3c9
288
289 #define VGA_CR_INDEX_MDA 0x3b4
290 #define VGA_CR_DATA_MDA 0x3b5
291 #define VGA_CR_INDEX_CGA 0x3d4
292 #define VGA_CR_DATA_CGA 0x3d5
293
294 /*
295 * Instruction field definitions used by the command parser
296 */
297 #define INSTR_CLIENT_SHIFT 29
298 #define INSTR_CLIENT_MASK 0xE0000000
299 #define INSTR_MI_CLIENT 0x0
300 #define INSTR_BC_CLIENT 0x2
301 #define INSTR_RC_CLIENT 0x3
302 #define INSTR_SUBCLIENT_SHIFT 27
303 #define INSTR_SUBCLIENT_MASK 0x18000000
304 #define INSTR_MEDIA_SUBCLIENT 0x2
305 #define INSTR_26_TO_24_MASK 0x7000000
306 #define INSTR_26_TO_24_SHIFT 24
307
308 /*
309 * Memory interface instructions used by the kernel
310 */
311 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
312 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
313 #define MI_GLOBAL_GTT (1<<22)
314
315 #define MI_NOOP MI_INSTR(0, 0)
316 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
317 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
318 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
319 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
320 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
321 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
322 #define MI_FLUSH MI_INSTR(0x04, 0)
323 #define MI_READ_FLUSH (1 << 0)
324 #define MI_EXE_FLUSH (1 << 1)
325 #define MI_NO_WRITE_FLUSH (1 << 2)
326 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
327 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
328 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
329 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
330 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
331 #define MI_ARB_ENABLE (1<<0)
332 #define MI_ARB_DISABLE (0<<0)
333 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
334 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
335 #define MI_SUSPEND_FLUSH_EN (1<<0)
336 #define MI_SET_APPID MI_INSTR(0x0e, 0)
337 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
338 #define MI_OVERLAY_CONTINUE (0x0<<21)
339 #define MI_OVERLAY_ON (0x1<<21)
340 #define MI_OVERLAY_OFF (0x2<<21)
341 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
342 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
343 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
344 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
345 /* IVB has funny definitions for which plane to flip. */
346 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
347 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
348 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
349 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
350 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
351 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
352 /* SKL ones */
353 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
354 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
355 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
356 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
357 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
358 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
359 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
360 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
361 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
362 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
363 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
364 #define MI_SEMAPHORE_UPDATE (1<<21)
365 #define MI_SEMAPHORE_COMPARE (1<<20)
366 #define MI_SEMAPHORE_REGISTER (1<<18)
367 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
368 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
369 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
370 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
371 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
372 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
373 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
374 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
375 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
376 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
377 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
378 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
379 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
380 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
381 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
382 #define MI_MM_SPACE_GTT (1<<8)
383 #define MI_MM_SPACE_PHYSICAL (0<<8)
384 #define MI_SAVE_EXT_STATE_EN (1<<3)
385 #define MI_RESTORE_EXT_STATE_EN (1<<2)
386 #define MI_FORCE_RESTORE (1<<1)
387 #define MI_RESTORE_INHIBIT (1<<0)
388 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
389 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
390 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
391 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
392 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
393 #define MI_SEMAPHORE_POLL (1<<15)
394 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
395 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
396 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
397 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
398 #define MI_USE_GGTT (1 << 22) /* g4x+ */
399 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
400 #define MI_STORE_DWORD_INDEX_SHIFT 2
401 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
402 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
403 * simply ignores the register load under certain conditions.
404 * - One can actually load arbitrary many arbitrary registers: Simply issue x
405 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
406 */
407 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
408 #define MI_LRI_FORCE_POSTED (1<<12)
409 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
410 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
411 #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
412 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
413 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
414 #define MI_INVALIDATE_TLB (1<<18)
415 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
416 #define MI_FLUSH_DW_OP_MASK (3<<14)
417 #define MI_FLUSH_DW_NOTIFY (1<<8)
418 #define MI_INVALIDATE_BSD (1<<7)
419 #define MI_FLUSH_DW_USE_GTT (1<<2)
420 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
421 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
422 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
423 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
424 #define MI_BATCH_NON_SECURE (1)
425 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
426 #define MI_BATCH_NON_SECURE_I965 (1<<8)
427 #define MI_BATCH_PPGTT_HSW (1<<8)
428 #define MI_BATCH_NON_SECURE_HSW (1<<13)
429 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
430 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
431 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
432 #define MI_BATCH_RESOURCE_STREAMER (1<<10)
433
434 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
435 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
436 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
437 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
438
439 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
440 #define LOWER_SLICE_ENABLED (1<<0)
441 #define LOWER_SLICE_DISABLED (0<<0)
442
443 /*
444 * 3D instructions used by the kernel
445 */
446 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
447
448 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
449 #define GEN9_MEDIA_POOL_ENABLE (1 << 31)
450 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
451 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
452 #define SC_UPDATE_SCISSOR (0x1<<1)
453 #define SC_ENABLE_MASK (0x1<<0)
454 #define SC_ENABLE (0x1<<0)
455 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
456 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
457 #define SCI_YMIN_MASK (0xffff<<16)
458 #define SCI_XMIN_MASK (0xffff<<0)
459 #define SCI_YMAX_MASK (0xffff<<16)
460 #define SCI_XMAX_MASK (0xffff<<0)
461 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
462 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
463 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
464 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
465 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
466 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
467 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
468 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
469 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
470
471 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
472 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
473 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
474 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
475 #define BLT_WRITE_A (2<<20)
476 #define BLT_WRITE_RGB (1<<20)
477 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
478 #define BLT_DEPTH_8 (0<<24)
479 #define BLT_DEPTH_16_565 (1<<24)
480 #define BLT_DEPTH_16_1555 (2<<24)
481 #define BLT_DEPTH_32 (3<<24)
482 #define BLT_ROP_SRC_COPY (0xcc<<16)
483 #define BLT_ROP_COLOR_COPY (0xf0<<16)
484 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
485 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
486 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
487 #define ASYNC_FLIP (1<<22)
488 #define DISPLAY_PLANE_A (0<<20)
489 #define DISPLAY_PLANE_B (1<<20)
490 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
491 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
492 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
493 #define PIPE_CONTROL_MMIO_WRITE (1<<23)
494 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
495 #define PIPE_CONTROL_CS_STALL (1<<20)
496 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
497 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
498 #define PIPE_CONTROL_QW_WRITE (1<<14)
499 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
500 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
501 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
502 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
503 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
504 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
505 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
506 #define PIPE_CONTROL_NOTIFY (1<<8)
507 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
508 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
509 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
510 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
511 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
512 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
513 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
514 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
515
516 /*
517 * Commands used only by the command parser
518 */
519 #define MI_SET_PREDICATE MI_INSTR(0x01, 0)
520 #define MI_ARB_CHECK MI_INSTR(0x05, 0)
521 #define MI_RS_CONTROL MI_INSTR(0x06, 0)
522 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
523 #define MI_PREDICATE MI_INSTR(0x0C, 0)
524 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
525 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
526 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
527 #define MI_URB_CLEAR MI_INSTR(0x19, 0)
528 #define MI_UPDATE_GTT MI_INSTR(0x23, 0)
529 #define MI_CLFLUSH MI_INSTR(0x27, 0)
530 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
531 #define MI_REPORT_PERF_COUNT_GGTT (1<<0)
532 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
533 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
534 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
535 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
536 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
537
538 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
539 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
540 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
541 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
542 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
543 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
544 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
545 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
546 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
547 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
548 #define GFX_OP_3DSTATE_SO_DECL_LIST \
549 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
550
551 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
552 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
553 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
554 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
555 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
556 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
557 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
558 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
559 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
560 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
561
562 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
563
564 #define COLOR_BLT ((0x2<<29)|(0x40<<22))
565 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
566
567 /*
568 * Registers used only by the command parser
569 */
570 #define BCS_SWCTRL _MMIO(0x22200)
571
572 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
573 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
574 #define HS_INVOCATION_COUNT _MMIO(0x2300)
575 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
576 #define DS_INVOCATION_COUNT _MMIO(0x2308)
577 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
578 #define IA_VERTICES_COUNT _MMIO(0x2310)
579 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
580 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
581 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
582 #define VS_INVOCATION_COUNT _MMIO(0x2320)
583 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
584 #define GS_INVOCATION_COUNT _MMIO(0x2328)
585 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
586 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
587 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
588 #define CL_INVOCATION_COUNT _MMIO(0x2338)
589 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
590 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
591 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
592 #define PS_INVOCATION_COUNT _MMIO(0x2348)
593 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
594 #define PS_DEPTH_COUNT _MMIO(0x2350)
595 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
596
597 /* There are the 4 64-bit counter registers, one for each stream output */
598 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
599 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
600
601 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
602 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
603
604 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
605 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
606 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
607 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
608 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
609 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
610
611 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
612 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
613 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
614
615 /* There are the 16 64-bit CS General Purpose Registers */
616 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
617 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
618
619 #define OACONTROL _MMIO(0x2360)
620
621 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
622 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
623 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
624
625 /*
626 * Reset registers
627 */
628 #define DEBUG_RESET_I830 _MMIO(0x6070)
629 #define DEBUG_RESET_FULL (1<<7)
630 #define DEBUG_RESET_RENDER (1<<8)
631 #define DEBUG_RESET_DISPLAY (1<<9)
632
633 /*
634 * IOSF sideband
635 */
636 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
637 #define IOSF_DEVFN_SHIFT 24
638 #define IOSF_OPCODE_SHIFT 16
639 #define IOSF_PORT_SHIFT 8
640 #define IOSF_BYTE_ENABLES_SHIFT 4
641 #define IOSF_BAR_SHIFT 1
642 #define IOSF_SB_BUSY (1<<0)
643 #define IOSF_PORT_BUNIT 0x03
644 #define IOSF_PORT_PUNIT 0x04
645 #define IOSF_PORT_NC 0x11
646 #define IOSF_PORT_DPIO 0x12
647 #define IOSF_PORT_GPIO_NC 0x13
648 #define IOSF_PORT_CCK 0x14
649 #define IOSF_PORT_DPIO_2 0x1a
650 #define IOSF_PORT_FLISDSI 0x1b
651 #define IOSF_PORT_GPIO_SC 0x48
652 #define IOSF_PORT_GPIO_SUS 0xa8
653 #define IOSF_PORT_CCU 0xa9
654 #define CHV_IOSF_PORT_GPIO_N 0x13
655 #define CHV_IOSF_PORT_GPIO_SE 0x48
656 #define CHV_IOSF_PORT_GPIO_E 0xa8
657 #define CHV_IOSF_PORT_GPIO_SW 0xb2
658 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
659 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
660
661 /* See configdb bunit SB addr map */
662 #define BUNIT_REG_BISOC 0x11
663
664 #define PUNIT_REG_DSPFREQ 0x36
665 #define DSPFREQSTAT_SHIFT_CHV 24
666 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
667 #define DSPFREQGUAR_SHIFT_CHV 8
668 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
669 #define DSPFREQSTAT_SHIFT 30
670 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
671 #define DSPFREQGUAR_SHIFT 14
672 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
673 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
674 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
675 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
676 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
677 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
678 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
679 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
680 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
681 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
682 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
683 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
684 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
685 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
686 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
687 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
688
689 /* See the PUNIT HAS v0.8 for the below bits */
690 enum punit_power_well {
691 /* These numbers are fixed and must match the position of the pw bits */
692 PUNIT_POWER_WELL_RENDER = 0,
693 PUNIT_POWER_WELL_MEDIA = 1,
694 PUNIT_POWER_WELL_DISP2D = 3,
695 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
696 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
697 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
698 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
699 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
700 PUNIT_POWER_WELL_DPIO_RX0 = 10,
701 PUNIT_POWER_WELL_DPIO_RX1 = 11,
702 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
703
704 /* Not actual bit groups. Used as IDs for lookup_power_well() */
705 PUNIT_POWER_WELL_ALWAYS_ON,
706 };
707
708 enum skl_disp_power_wells {
709 /* These numbers are fixed and must match the position of the pw bits */
710 SKL_DISP_PW_MISC_IO,
711 SKL_DISP_PW_DDI_A_E,
712 SKL_DISP_PW_DDI_B,
713 SKL_DISP_PW_DDI_C,
714 SKL_DISP_PW_DDI_D,
715 SKL_DISP_PW_1 = 14,
716 SKL_DISP_PW_2,
717
718 /* Not actual bit groups. Used as IDs for lookup_power_well() */
719 SKL_DISP_PW_ALWAYS_ON,
720 SKL_DISP_PW_DC_OFF,
721
722 BXT_DPIO_CMN_A,
723 BXT_DPIO_CMN_BC,
724 };
725
726 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
727 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
728
729 #define PUNIT_REG_PWRGT_CTRL 0x60
730 #define PUNIT_REG_PWRGT_STATUS 0x61
731 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
732 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
733 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
734 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
735 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
736
737 #define PUNIT_REG_GPU_LFM 0xd3
738 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
739 #define PUNIT_REG_GPU_FREQ_STS 0xd8
740 #define GPLLENABLE (1<<4)
741 #define GENFREQSTATUS (1<<0)
742 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
743 #define PUNIT_REG_CZ_TIMESTAMP 0xce
744
745 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
746 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
747
748 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
749 #define FB_GFX_FREQ_FUSE_MASK 0xff
750 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
751 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
752 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
753
754 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
755 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
756
757 #define PUNIT_REG_DDR_SETUP2 0x139
758 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
759 #define FORCE_DDR_LOW_FREQ (1 << 1)
760 #define FORCE_DDR_HIGH_FREQ (1 << 0)
761
762 #define PUNIT_GPU_STATUS_REG 0xdb
763 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
764 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
765 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
766 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
767
768 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
769 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
770 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
771
772 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
773 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
774 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
775 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
776 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
777 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
778 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
779 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
780 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
781 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
782
783 #define VLV_TURBO_SOC_OVERRIDE 0x04
784 #define VLV_OVERRIDE_EN 1
785 #define VLV_SOC_TDP_EN (1 << 1)
786 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
787 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
788
789 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
790
791 /* vlv2 north clock has */
792 #define CCK_FUSE_REG 0x8
793 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
794 #define CCK_REG_DSI_PLL_FUSE 0x44
795 #define CCK_REG_DSI_PLL_CONTROL 0x48
796 #define DSI_PLL_VCO_EN (1 << 31)
797 #define DSI_PLL_LDO_GATE (1 << 30)
798 #define DSI_PLL_P1_POST_DIV_SHIFT 17
799 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
800 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
801 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
802 #define DSI_PLL_MUX_MASK (3 << 9)
803 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
804 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
805 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
806 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
807 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
808 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
809 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
810 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
811 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
812 #define DSI_PLL_LOCK (1 << 0)
813 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
814 #define DSI_PLL_LFSR (1 << 31)
815 #define DSI_PLL_FRACTION_EN (1 << 30)
816 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
817 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
818 #define DSI_PLL_USYNC_CNT_SHIFT 18
819 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
820 #define DSI_PLL_N1_DIV_SHIFT 16
821 #define DSI_PLL_N1_DIV_MASK (3 << 16)
822 #define DSI_PLL_M1_DIV_SHIFT 0
823 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
824 #define CCK_CZ_CLOCK_CONTROL 0x62
825 #define CCK_GPLL_CLOCK_CONTROL 0x67
826 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
827 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
828 #define CCK_TRUNK_FORCE_ON (1 << 17)
829 #define CCK_TRUNK_FORCE_OFF (1 << 16)
830 #define CCK_FREQUENCY_STATUS (0x1f << 8)
831 #define CCK_FREQUENCY_STATUS_SHIFT 8
832 #define CCK_FREQUENCY_VALUES (0x1f << 0)
833
834 /**
835 * DOC: DPIO
836 *
837 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
838 * ports. DPIO is the name given to such a display PHY. These PHYs
839 * don't follow the standard programming model using direct MMIO
840 * registers, and instead their registers must be accessed trough IOSF
841 * sideband. VLV has one such PHY for driving ports B and C, and CHV
842 * adds another PHY for driving port D. Each PHY responds to specific
843 * IOSF-SB port.
844 *
845 * Each display PHY is made up of one or two channels. Each channel
846 * houses a common lane part which contains the PLL and other common
847 * logic. CH0 common lane also contains the IOSF-SB logic for the
848 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
849 * must be running when any DPIO registers are accessed.
850 *
851 * In addition to having their own registers, the PHYs are also
852 * controlled through some dedicated signals from the display
853 * controller. These include PLL reference clock enable, PLL enable,
854 * and CRI clock selection, for example.
855 *
856 * Eeach channel also has two splines (also called data lanes), and
857 * each spline is made up of one Physical Access Coding Sub-Layer
858 * (PCS) block and two TX lanes. So each channel has two PCS blocks
859 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
860 * data/clock pairs depending on the output type.
861 *
862 * Additionally the PHY also contains an AUX lane with AUX blocks
863 * for each channel. This is used for DP AUX communication, but
864 * this fact isn't really relevant for the driver since AUX is
865 * controlled from the display controller side. No DPIO registers
866 * need to be accessed during AUX communication,
867 *
868 * Generally on VLV/CHV the common lane corresponds to the pipe and
869 * the spline (PCS/TX) corresponds to the port.
870 *
871 * For dual channel PHY (VLV/CHV):
872 *
873 * pipe A == CMN/PLL/REF CH0
874 *
875 * pipe B == CMN/PLL/REF CH1
876 *
877 * port B == PCS/TX CH0
878 *
879 * port C == PCS/TX CH1
880 *
881 * This is especially important when we cross the streams
882 * ie. drive port B with pipe B, or port C with pipe A.
883 *
884 * For single channel PHY (CHV):
885 *
886 * pipe C == CMN/PLL/REF CH0
887 *
888 * port D == PCS/TX CH0
889 *
890 * On BXT the entire PHY channel corresponds to the port. That means
891 * the PLL is also now associated with the port rather than the pipe,
892 * and so the clock needs to be routed to the appropriate transcoder.
893 * Port A PLL is directly connected to transcoder EDP and port B/C
894 * PLLs can be routed to any transcoder A/B/C.
895 *
896 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
897 * digital port D (CHV) or port A (BXT). ::
898 *
899 *
900 * Dual channel PHY (VLV/CHV/BXT)
901 * ---------------------------------
902 * | CH0 | CH1 |
903 * | CMN/PLL/REF | CMN/PLL/REF |
904 * |---------------|---------------| Display PHY
905 * | PCS01 | PCS23 | PCS01 | PCS23 |
906 * |-------|-------|-------|-------|
907 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
908 * ---------------------------------
909 * | DDI0 | DDI1 | DP/HDMI ports
910 * ---------------------------------
911 *
912 * Single channel PHY (CHV/BXT)
913 * -----------------
914 * | CH0 |
915 * | CMN/PLL/REF |
916 * |---------------| Display PHY
917 * | PCS01 | PCS23 |
918 * |-------|-------|
919 * |TX0|TX1|TX2|TX3|
920 * -----------------
921 * | DDI2 | DP/HDMI port
922 * -----------------
923 */
924 #define DPIO_DEVFN 0
925
926 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
927 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
928 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
929 #define DPIO_SFR_BYPASS (1<<1)
930 #define DPIO_CMNRST (1<<0)
931
932 #define DPIO_PHY(pipe) ((pipe) >> 1)
933 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
934
935 /*
936 * Per pipe/PLL DPIO regs
937 */
938 #define _VLV_PLL_DW3_CH0 0x800c
939 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
940 #define DPIO_POST_DIV_DAC 0
941 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
942 #define DPIO_POST_DIV_LVDS1 2
943 #define DPIO_POST_DIV_LVDS2 3
944 #define DPIO_K_SHIFT (24) /* 4 bits */
945 #define DPIO_P1_SHIFT (21) /* 3 bits */
946 #define DPIO_P2_SHIFT (16) /* 5 bits */
947 #define DPIO_N_SHIFT (12) /* 4 bits */
948 #define DPIO_ENABLE_CALIBRATION (1<<11)
949 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
950 #define DPIO_M2DIV_MASK 0xff
951 #define _VLV_PLL_DW3_CH1 0x802c
952 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
953
954 #define _VLV_PLL_DW5_CH0 0x8014
955 #define DPIO_REFSEL_OVERRIDE 27
956 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
957 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
958 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
959 #define DPIO_PLL_REFCLK_SEL_MASK 3
960 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
961 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
962 #define _VLV_PLL_DW5_CH1 0x8034
963 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
964
965 #define _VLV_PLL_DW7_CH0 0x801c
966 #define _VLV_PLL_DW7_CH1 0x803c
967 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
968
969 #define _VLV_PLL_DW8_CH0 0x8040
970 #define _VLV_PLL_DW8_CH1 0x8060
971 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
972
973 #define VLV_PLL_DW9_BCAST 0xc044
974 #define _VLV_PLL_DW9_CH0 0x8044
975 #define _VLV_PLL_DW9_CH1 0x8064
976 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
977
978 #define _VLV_PLL_DW10_CH0 0x8048
979 #define _VLV_PLL_DW10_CH1 0x8068
980 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
981
982 #define _VLV_PLL_DW11_CH0 0x804c
983 #define _VLV_PLL_DW11_CH1 0x806c
984 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
985
986 /* Spec for ref block start counts at DW10 */
987 #define VLV_REF_DW13 0x80ac
988
989 #define VLV_CMN_DW0 0x8100
990
991 /*
992 * Per DDI channel DPIO regs
993 */
994
995 #define _VLV_PCS_DW0_CH0 0x8200
996 #define _VLV_PCS_DW0_CH1 0x8400
997 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
998 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
999 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
1000 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
1001 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1002
1003 #define _VLV_PCS01_DW0_CH0 0x200
1004 #define _VLV_PCS23_DW0_CH0 0x400
1005 #define _VLV_PCS01_DW0_CH1 0x2600
1006 #define _VLV_PCS23_DW0_CH1 0x2800
1007 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1008 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1009
1010 #define _VLV_PCS_DW1_CH0 0x8204
1011 #define _VLV_PCS_DW1_CH1 0x8404
1012 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
1013 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1014 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1015 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1016 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
1017 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1018
1019 #define _VLV_PCS01_DW1_CH0 0x204
1020 #define _VLV_PCS23_DW1_CH0 0x404
1021 #define _VLV_PCS01_DW1_CH1 0x2604
1022 #define _VLV_PCS23_DW1_CH1 0x2804
1023 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1024 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1025
1026 #define _VLV_PCS_DW8_CH0 0x8220
1027 #define _VLV_PCS_DW8_CH1 0x8420
1028 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1029 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1030 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1031
1032 #define _VLV_PCS01_DW8_CH0 0x0220
1033 #define _VLV_PCS23_DW8_CH0 0x0420
1034 #define _VLV_PCS01_DW8_CH1 0x2620
1035 #define _VLV_PCS23_DW8_CH1 0x2820
1036 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1037 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1038
1039 #define _VLV_PCS_DW9_CH0 0x8224
1040 #define _VLV_PCS_DW9_CH1 0x8424
1041 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1042 #define DPIO_PCS_TX2MARGIN_000 (0<<13)
1043 #define DPIO_PCS_TX2MARGIN_101 (1<<13)
1044 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1045 #define DPIO_PCS_TX1MARGIN_000 (0<<10)
1046 #define DPIO_PCS_TX1MARGIN_101 (1<<10)
1047 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1048
1049 #define _VLV_PCS01_DW9_CH0 0x224
1050 #define _VLV_PCS23_DW9_CH0 0x424
1051 #define _VLV_PCS01_DW9_CH1 0x2624
1052 #define _VLV_PCS23_DW9_CH1 0x2824
1053 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1054 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1055
1056 #define _CHV_PCS_DW10_CH0 0x8228
1057 #define _CHV_PCS_DW10_CH1 0x8428
1058 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1059 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
1060 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1061 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1062 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1063 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1064 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1065 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
1066 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1067
1068 #define _VLV_PCS01_DW10_CH0 0x0228
1069 #define _VLV_PCS23_DW10_CH0 0x0428
1070 #define _VLV_PCS01_DW10_CH1 0x2628
1071 #define _VLV_PCS23_DW10_CH1 0x2828
1072 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1073 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1074
1075 #define _VLV_PCS_DW11_CH0 0x822c
1076 #define _VLV_PCS_DW11_CH1 0x842c
1077 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
1078 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1079 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1080 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
1081 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1082
1083 #define _VLV_PCS01_DW11_CH0 0x022c
1084 #define _VLV_PCS23_DW11_CH0 0x042c
1085 #define _VLV_PCS01_DW11_CH1 0x262c
1086 #define _VLV_PCS23_DW11_CH1 0x282c
1087 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1088 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1089
1090 #define _VLV_PCS01_DW12_CH0 0x0230
1091 #define _VLV_PCS23_DW12_CH0 0x0430
1092 #define _VLV_PCS01_DW12_CH1 0x2630
1093 #define _VLV_PCS23_DW12_CH1 0x2830
1094 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1095 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1096
1097 #define _VLV_PCS_DW12_CH0 0x8230
1098 #define _VLV_PCS_DW12_CH1 0x8430
1099 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1100 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1101 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1102 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1103 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1104 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1105
1106 #define _VLV_PCS_DW14_CH0 0x8238
1107 #define _VLV_PCS_DW14_CH1 0x8438
1108 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1109
1110 #define _VLV_PCS_DW23_CH0 0x825c
1111 #define _VLV_PCS_DW23_CH1 0x845c
1112 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1113
1114 #define _VLV_TX_DW2_CH0 0x8288
1115 #define _VLV_TX_DW2_CH1 0x8488
1116 #define DPIO_SWING_MARGIN000_SHIFT 16
1117 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1118 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1119 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1120
1121 #define _VLV_TX_DW3_CH0 0x828c
1122 #define _VLV_TX_DW3_CH1 0x848c
1123 /* The following bit for CHV phy */
1124 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1125 #define DPIO_SWING_MARGIN101_SHIFT 16
1126 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1127 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1128
1129 #define _VLV_TX_DW4_CH0 0x8290
1130 #define _VLV_TX_DW4_CH1 0x8490
1131 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1132 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1133 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1134 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1135 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1136
1137 #define _VLV_TX3_DW4_CH0 0x690
1138 #define _VLV_TX3_DW4_CH1 0x2a90
1139 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1140
1141 #define _VLV_TX_DW5_CH0 0x8294
1142 #define _VLV_TX_DW5_CH1 0x8494
1143 #define DPIO_TX_OCALINIT_EN (1<<31)
1144 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1145
1146 #define _VLV_TX_DW11_CH0 0x82ac
1147 #define _VLV_TX_DW11_CH1 0x84ac
1148 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1149
1150 #define _VLV_TX_DW14_CH0 0x82b8
1151 #define _VLV_TX_DW14_CH1 0x84b8
1152 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1153
1154 /* CHV dpPhy registers */
1155 #define _CHV_PLL_DW0_CH0 0x8000
1156 #define _CHV_PLL_DW0_CH1 0x8180
1157 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1158
1159 #define _CHV_PLL_DW1_CH0 0x8004
1160 #define _CHV_PLL_DW1_CH1 0x8184
1161 #define DPIO_CHV_N_DIV_SHIFT 8
1162 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1163 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1164
1165 #define _CHV_PLL_DW2_CH0 0x8008
1166 #define _CHV_PLL_DW2_CH1 0x8188
1167 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1168
1169 #define _CHV_PLL_DW3_CH0 0x800c
1170 #define _CHV_PLL_DW3_CH1 0x818c
1171 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1172 #define DPIO_CHV_FIRST_MOD (0 << 8)
1173 #define DPIO_CHV_SECOND_MOD (1 << 8)
1174 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1175 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1176 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1177
1178 #define _CHV_PLL_DW6_CH0 0x8018
1179 #define _CHV_PLL_DW6_CH1 0x8198
1180 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1181 #define DPIO_CHV_INT_COEFF_SHIFT 8
1182 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1183 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1184
1185 #define _CHV_PLL_DW8_CH0 0x8020
1186 #define _CHV_PLL_DW8_CH1 0x81A0
1187 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1188 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1189 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1190
1191 #define _CHV_PLL_DW9_CH0 0x8024
1192 #define _CHV_PLL_DW9_CH1 0x81A4
1193 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1194 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1195 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1196 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1197
1198 #define _CHV_CMN_DW0_CH0 0x8100
1199 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1200 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1201 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1202 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1203
1204 #define _CHV_CMN_DW5_CH0 0x8114
1205 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1206 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1207 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1208 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1209 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1210 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1211 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1212 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1213
1214 #define _CHV_CMN_DW13_CH0 0x8134
1215 #define _CHV_CMN_DW0_CH1 0x8080
1216 #define DPIO_CHV_S1_DIV_SHIFT 21
1217 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1218 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1219 #define DPIO_CHV_K_DIV_SHIFT 4
1220 #define DPIO_PLL_FREQLOCK (1 << 1)
1221 #define DPIO_PLL_LOCK (1 << 0)
1222 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1223
1224 #define _CHV_CMN_DW14_CH0 0x8138
1225 #define _CHV_CMN_DW1_CH1 0x8084
1226 #define DPIO_AFC_RECAL (1 << 14)
1227 #define DPIO_DCLKP_EN (1 << 13)
1228 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1229 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1230 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1231 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1232 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1233 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1234 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1235 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1236 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1237
1238 #define _CHV_CMN_DW19_CH0 0x814c
1239 #define _CHV_CMN_DW6_CH1 0x8098
1240 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1241 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1242 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1243 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1244
1245 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1246
1247 #define CHV_CMN_DW28 0x8170
1248 #define DPIO_CL1POWERDOWNEN (1 << 23)
1249 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1250 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1251 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1252 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1253 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1254
1255 #define CHV_CMN_DW30 0x8178
1256 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1257 #define DPIO_LRC_BYPASS (1 << 3)
1258
1259 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1260 (lane) * 0x200 + (offset))
1261
1262 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1263 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1264 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1265 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1266 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1267 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1268 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1269 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1270 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1271 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1272 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1273 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1274 #define DPIO_FRC_LATENCY_SHFIT 8
1275 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1276 #define DPIO_UPAR_SHIFT 30
1277
1278 /* BXT PHY registers */
1279 #define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b))
1280
1281 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1282 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1283
1284 #define _BXT_PHY_CTL_DDI_A 0x64C00
1285 #define _BXT_PHY_CTL_DDI_B 0x64C10
1286 #define _BXT_PHY_CTL_DDI_C 0x64C20
1287 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1288 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1289 #define BXT_PHY_LANE_ENABLED (1 << 8)
1290 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1291 _BXT_PHY_CTL_DDI_B)
1292
1293 #define _PHY_CTL_FAMILY_EDP 0x64C80
1294 #define _PHY_CTL_FAMILY_DDI 0x64C90
1295 #define COMMON_RESET_DIS (1 << 31)
1296 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1297 _PHY_CTL_FAMILY_EDP)
1298
1299 /* BXT PHY PLL registers */
1300 #define _PORT_PLL_A 0x46074
1301 #define _PORT_PLL_B 0x46078
1302 #define _PORT_PLL_C 0x4607c
1303 #define PORT_PLL_ENABLE (1 << 31)
1304 #define PORT_PLL_LOCK (1 << 30)
1305 #define PORT_PLL_REF_SEL (1 << 27)
1306 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1307
1308 #define _PORT_PLL_EBB_0_A 0x162034
1309 #define _PORT_PLL_EBB_0_B 0x6C034
1310 #define _PORT_PLL_EBB_0_C 0x6C340
1311 #define PORT_PLL_P1_SHIFT 13
1312 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1313 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1314 #define PORT_PLL_P2_SHIFT 8
1315 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1316 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1317 #define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
1318 _PORT_PLL_EBB_0_B, \
1319 _PORT_PLL_EBB_0_C)
1320
1321 #define _PORT_PLL_EBB_4_A 0x162038
1322 #define _PORT_PLL_EBB_4_B 0x6C038
1323 #define _PORT_PLL_EBB_4_C 0x6C344
1324 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1325 #define PORT_PLL_RECALIBRATE (1 << 14)
1326 #define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
1327 _PORT_PLL_EBB_4_B, \
1328 _PORT_PLL_EBB_4_C)
1329
1330 #define _PORT_PLL_0_A 0x162100
1331 #define _PORT_PLL_0_B 0x6C100
1332 #define _PORT_PLL_0_C 0x6C380
1333 /* PORT_PLL_0_A */
1334 #define PORT_PLL_M2_MASK 0xFF
1335 /* PORT_PLL_1_A */
1336 #define PORT_PLL_N_SHIFT 8
1337 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1338 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1339 /* PORT_PLL_2_A */
1340 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1341 /* PORT_PLL_3_A */
1342 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1343 /* PORT_PLL_6_A */
1344 #define PORT_PLL_PROP_COEFF_MASK 0xF
1345 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1346 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1347 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1348 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1349 /* PORT_PLL_8_A */
1350 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1351 /* PORT_PLL_9_A */
1352 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1353 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1354 /* PORT_PLL_10_A */
1355 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1356 #define PORT_PLL_DCO_AMP_DEFAULT 15
1357 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1358 #define PORT_PLL_DCO_AMP(x) ((x)<<10)
1359 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1360 _PORT_PLL_0_B, \
1361 _PORT_PLL_0_C)
1362 #define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
1363
1364 /* BXT PHY common lane registers */
1365 #define _PORT_CL1CM_DW0_A 0x162000
1366 #define _PORT_CL1CM_DW0_BC 0x6C000
1367 #define PHY_POWER_GOOD (1 << 16)
1368 #define PHY_RESERVED (1 << 7)
1369 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1370 _PORT_CL1CM_DW0_A)
1371
1372 #define _PORT_CL1CM_DW9_A 0x162024
1373 #define _PORT_CL1CM_DW9_BC 0x6C024
1374 #define IREF0RC_OFFSET_SHIFT 8
1375 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1376 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1377 _PORT_CL1CM_DW9_A)
1378
1379 #define _PORT_CL1CM_DW10_A 0x162028
1380 #define _PORT_CL1CM_DW10_BC 0x6C028
1381 #define IREF1RC_OFFSET_SHIFT 8
1382 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1383 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1384 _PORT_CL1CM_DW10_A)
1385
1386 #define _PORT_CL1CM_DW28_A 0x162070
1387 #define _PORT_CL1CM_DW28_BC 0x6C070
1388 #define OCL1_POWER_DOWN_EN (1 << 23)
1389 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1390 #define SUS_CLK_CONFIG 0x3
1391 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1392 _PORT_CL1CM_DW28_A)
1393
1394 #define _PORT_CL1CM_DW30_A 0x162078
1395 #define _PORT_CL1CM_DW30_BC 0x6C078
1396 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1397 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1398 _PORT_CL1CM_DW30_A)
1399
1400 /* Defined for PHY0 only */
1401 #define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358)
1402 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1403
1404 /* BXT PHY Ref registers */
1405 #define _PORT_REF_DW3_A 0x16218C
1406 #define _PORT_REF_DW3_BC 0x6C18C
1407 #define GRC_DONE (1 << 22)
1408 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1409 _PORT_REF_DW3_A)
1410
1411 #define _PORT_REF_DW6_A 0x162198
1412 #define _PORT_REF_DW6_BC 0x6C198
1413 #define GRC_CODE_SHIFT 24
1414 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
1415 #define GRC_CODE_FAST_SHIFT 16
1416 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
1417 #define GRC_CODE_SLOW_SHIFT 8
1418 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1419 #define GRC_CODE_NOM_MASK 0xFF
1420 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1421 _PORT_REF_DW6_A)
1422
1423 #define _PORT_REF_DW8_A 0x1621A0
1424 #define _PORT_REF_DW8_BC 0x6C1A0
1425 #define GRC_DIS (1 << 15)
1426 #define GRC_RDY_OVRD (1 << 1)
1427 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1428 _PORT_REF_DW8_A)
1429
1430 /* BXT PHY PCS registers */
1431 #define _PORT_PCS_DW10_LN01_A 0x162428
1432 #define _PORT_PCS_DW10_LN01_B 0x6C428
1433 #define _PORT_PCS_DW10_LN01_C 0x6C828
1434 #define _PORT_PCS_DW10_GRP_A 0x162C28
1435 #define _PORT_PCS_DW10_GRP_B 0x6CC28
1436 #define _PORT_PCS_DW10_GRP_C 0x6CE28
1437 #define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
1438 _PORT_PCS_DW10_LN01_B, \
1439 _PORT_PCS_DW10_LN01_C)
1440 #define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \
1441 _PORT_PCS_DW10_GRP_B, \
1442 _PORT_PCS_DW10_GRP_C)
1443 #define TX2_SWING_CALC_INIT (1 << 31)
1444 #define TX1_SWING_CALC_INIT (1 << 30)
1445
1446 #define _PORT_PCS_DW12_LN01_A 0x162430
1447 #define _PORT_PCS_DW12_LN01_B 0x6C430
1448 #define _PORT_PCS_DW12_LN01_C 0x6C830
1449 #define _PORT_PCS_DW12_LN23_A 0x162630
1450 #define _PORT_PCS_DW12_LN23_B 0x6C630
1451 #define _PORT_PCS_DW12_LN23_C 0x6CA30
1452 #define _PORT_PCS_DW12_GRP_A 0x162c30
1453 #define _PORT_PCS_DW12_GRP_B 0x6CC30
1454 #define _PORT_PCS_DW12_GRP_C 0x6CE30
1455 #define LANESTAGGER_STRAP_OVRD (1 << 6)
1456 #define LANE_STAGGER_MASK 0x1F
1457 #define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
1458 _PORT_PCS_DW12_LN01_B, \
1459 _PORT_PCS_DW12_LN01_C)
1460 #define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
1461 _PORT_PCS_DW12_LN23_B, \
1462 _PORT_PCS_DW12_LN23_C)
1463 #define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
1464 _PORT_PCS_DW12_GRP_B, \
1465 _PORT_PCS_DW12_GRP_C)
1466
1467 /* BXT PHY TX registers */
1468 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1469 ((lane) & 1) * 0x80)
1470
1471 #define _PORT_TX_DW2_LN0_A 0x162508
1472 #define _PORT_TX_DW2_LN0_B 0x6C508
1473 #define _PORT_TX_DW2_LN0_C 0x6C908
1474 #define _PORT_TX_DW2_GRP_A 0x162D08
1475 #define _PORT_TX_DW2_GRP_B 0x6CD08
1476 #define _PORT_TX_DW2_GRP_C 0x6CF08
1477 #define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \
1478 _PORT_TX_DW2_GRP_B, \
1479 _PORT_TX_DW2_GRP_C)
1480 #define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \
1481 _PORT_TX_DW2_LN0_B, \
1482 _PORT_TX_DW2_LN0_C)
1483 #define MARGIN_000_SHIFT 16
1484 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1485 #define UNIQ_TRANS_SCALE_SHIFT 8
1486 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1487
1488 #define _PORT_TX_DW3_LN0_A 0x16250C
1489 #define _PORT_TX_DW3_LN0_B 0x6C50C
1490 #define _PORT_TX_DW3_LN0_C 0x6C90C
1491 #define _PORT_TX_DW3_GRP_A 0x162D0C
1492 #define _PORT_TX_DW3_GRP_B 0x6CD0C
1493 #define _PORT_TX_DW3_GRP_C 0x6CF0C
1494 #define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \
1495 _PORT_TX_DW3_GRP_B, \
1496 _PORT_TX_DW3_GRP_C)
1497 #define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \
1498 _PORT_TX_DW3_LN0_B, \
1499 _PORT_TX_DW3_LN0_C)
1500 #define SCALE_DCOMP_METHOD (1 << 26)
1501 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
1502
1503 #define _PORT_TX_DW4_LN0_A 0x162510
1504 #define _PORT_TX_DW4_LN0_B 0x6C510
1505 #define _PORT_TX_DW4_LN0_C 0x6C910
1506 #define _PORT_TX_DW4_GRP_A 0x162D10
1507 #define _PORT_TX_DW4_GRP_B 0x6CD10
1508 #define _PORT_TX_DW4_GRP_C 0x6CF10
1509 #define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \
1510 _PORT_TX_DW4_LN0_B, \
1511 _PORT_TX_DW4_LN0_C)
1512 #define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \
1513 _PORT_TX_DW4_GRP_B, \
1514 _PORT_TX_DW4_GRP_C)
1515 #define DEEMPH_SHIFT 24
1516 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1517
1518 #define _PORT_TX_DW14_LN0_A 0x162538
1519 #define _PORT_TX_DW14_LN0_B 0x6C538
1520 #define _PORT_TX_DW14_LN0_C 0x6C938
1521 #define LATENCY_OPTIM_SHIFT 30
1522 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1523 #define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \
1524 _PORT_TX_DW14_LN0_B, \
1525 _PORT_TX_DW14_LN0_C) + \
1526 _BXT_LANE_OFFSET(lane))
1527
1528 /* UAIMI scratch pad register 1 */
1529 #define UAIMI_SPR1 _MMIO(0x4F074)
1530 /* SKL VccIO mask */
1531 #define SKL_VCCIO_MASK 0x1
1532 /* SKL balance leg register */
1533 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
1534 /* I_boost values */
1535 #define BALANCE_LEG_SHIFT(port) (8+3*(port))
1536 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1537 /* Balance leg disable bits */
1538 #define BALANCE_LEG_DISABLE_SHIFT 23
1539 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
1540
1541 /*
1542 * Fence registers
1543 * [0-7] @ 0x2000 gen2,gen3
1544 * [8-15] @ 0x3000 945,g33,pnv
1545 *
1546 * [0-15] @ 0x3000 gen4,gen5
1547 *
1548 * [0-15] @ 0x100000 gen6,vlv,chv
1549 * [0-31] @ 0x100000 gen7+
1550 */
1551 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
1552 #define I830_FENCE_START_MASK 0x07f80000
1553 #define I830_FENCE_TILING_Y_SHIFT 12
1554 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1555 #define I830_FENCE_PITCH_SHIFT 4
1556 #define I830_FENCE_REG_VALID (1<<0)
1557 #define I915_FENCE_MAX_PITCH_VAL 4
1558 #define I830_FENCE_MAX_PITCH_VAL 6
1559 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
1560
1561 #define I915_FENCE_START_MASK 0x0ff00000
1562 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1563
1564 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
1565 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
1566 #define I965_FENCE_PITCH_SHIFT 2
1567 #define I965_FENCE_TILING_Y_SHIFT 1
1568 #define I965_FENCE_REG_VALID (1<<0)
1569 #define I965_FENCE_MAX_PITCH_VAL 0x0400
1570
1571 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
1572 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
1573 #define GEN6_FENCE_PITCH_SHIFT 32
1574 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1575
1576
1577 /* control register for cpu gtt access */
1578 #define TILECTL _MMIO(0x101000)
1579 #define TILECTL_SWZCTL (1 << 0)
1580 #define TILECTL_TLBPF (1 << 1)
1581 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1582 #define TILECTL_BACKSNOOP_DIS (1 << 3)
1583
1584 /*
1585 * Instruction and interrupt control regs
1586 */
1587 #define PGTBL_CTL _MMIO(0x02020)
1588 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1589 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1590 #define PGTBL_ER _MMIO(0x02024)
1591 #define PRB0_BASE (0x2030-0x30)
1592 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1593 #define PRB2_BASE (0x2050-0x30) /* gen3 */
1594 #define SRB0_BASE (0x2100-0x30) /* gen2 */
1595 #define SRB1_BASE (0x2110-0x30) /* gen2 */
1596 #define SRB2_BASE (0x2120-0x30) /* 830 */
1597 #define SRB3_BASE (0x2130-0x30) /* 830 */
1598 #define RENDER_RING_BASE 0x02000
1599 #define BSD_RING_BASE 0x04000
1600 #define GEN6_BSD_RING_BASE 0x12000
1601 #define GEN8_BSD2_RING_BASE 0x1c000
1602 #define VEBOX_RING_BASE 0x1a000
1603 #define BLT_RING_BASE 0x22000
1604 #define RING_TAIL(base) _MMIO((base)+0x30)
1605 #define RING_HEAD(base) _MMIO((base)+0x34)
1606 #define RING_START(base) _MMIO((base)+0x38)
1607 #define RING_CTL(base) _MMIO((base)+0x3c)
1608 #define RING_SYNC_0(base) _MMIO((base)+0x40)
1609 #define RING_SYNC_1(base) _MMIO((base)+0x44)
1610 #define RING_SYNC_2(base) _MMIO((base)+0x48)
1611 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1612 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1613 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1614 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1615 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1616 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1617 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1618 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1619 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1620 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1621 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1622 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1623 #define GEN6_NOSYNC INVALID_MMIO_REG
1624 #define RING_PSMI_CTL(base) _MMIO((base)+0x50)
1625 #define RING_MAX_IDLE(base) _MMIO((base)+0x54)
1626 #define RING_HWS_PGA(base) _MMIO((base)+0x80)
1627 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
1628 #define RING_RESET_CTL(base) _MMIO((base)+0xd0)
1629 #define RESET_CTL_REQUEST_RESET (1 << 0)
1630 #define RESET_CTL_READY_TO_RESET (1 << 1)
1631
1632 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
1633 #define GTT_CACHE_EN_ALL 0xF0007FFF
1634 #define GEN7_WR_WATERMARK _MMIO(0x4028)
1635 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
1636 #define ARB_MODE _MMIO(0x4030)
1637 #define ARB_MODE_SWIZZLE_SNB (1<<4)
1638 #define ARB_MODE_SWIZZLE_IVB (1<<5)
1639 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
1640 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
1641 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1642 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
1643 #define GEN7_LRA_LIMITS_REG_NUM 13
1644 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
1645 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
1646
1647 #define GAMTARBMODE _MMIO(0x04a08)
1648 #define ARB_MODE_BWGTLB_DISABLE (1<<9)
1649 #define ARB_MODE_SWIZZLE_BDW (1<<1)
1650 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
1651 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
1652 #define RING_FAULT_GTTSEL_MASK (1<<11)
1653 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1654 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1655 #define RING_FAULT_VALID (1<<0)
1656 #define DONE_REG _MMIO(0x40b0)
1657 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
1658 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
1659 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
1660 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
1661 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
1662 #define RING_ACTHD(base) _MMIO((base)+0x74)
1663 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
1664 #define RING_NOPID(base) _MMIO((base)+0x94)
1665 #define RING_IMR(base) _MMIO((base)+0xa8)
1666 #define RING_HWSTAM(base) _MMIO((base)+0x98)
1667 #define RING_TIMESTAMP(base) _MMIO((base)+0x358)
1668 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
1669 #define TAIL_ADDR 0x001FFFF8
1670 #define HEAD_WRAP_COUNT 0xFFE00000
1671 #define HEAD_WRAP_ONE 0x00200000
1672 #define HEAD_ADDR 0x001FFFFC
1673 #define RING_NR_PAGES 0x001FF000
1674 #define RING_REPORT_MASK 0x00000006
1675 #define RING_REPORT_64K 0x00000002
1676 #define RING_REPORT_128K 0x00000004
1677 #define RING_NO_REPORT 0x00000000
1678 #define RING_VALID_MASK 0x00000001
1679 #define RING_VALID 0x00000001
1680 #define RING_INVALID 0x00000000
1681 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1682 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1683 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1684
1685 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
1686 #define RING_MAX_NONPRIV_SLOTS 12
1687
1688 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
1689
1690 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
1691 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
1692
1693 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
1694 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
1695
1696 #if 0
1697 #define PRB0_TAIL _MMIO(0x2030)
1698 #define PRB0_HEAD _MMIO(0x2034)
1699 #define PRB0_START _MMIO(0x2038)
1700 #define PRB0_CTL _MMIO(0x203c)
1701 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
1702 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
1703 #define PRB1_START _MMIO(0x2048) /* 915+ only */
1704 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
1705 #endif
1706 #define IPEIR_I965 _MMIO(0x2064)
1707 #define IPEHR_I965 _MMIO(0x2068)
1708 #define GEN7_SC_INSTDONE _MMIO(0x7100)
1709 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1710 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
1711 #define I915_NUM_INSTDONE_REG 4
1712 #define RING_IPEIR(base) _MMIO((base)+0x64)
1713 #define RING_IPEHR(base) _MMIO((base)+0x68)
1714 /*
1715 * On GEN4, only the render ring INSTDONE exists and has a different
1716 * layout than the GEN7+ version.
1717 * The GEN2 counterpart of this register is GEN2_INSTDONE.
1718 */
1719 #define RING_INSTDONE(base) _MMIO((base)+0x6c)
1720 #define RING_INSTPS(base) _MMIO((base)+0x70)
1721 #define RING_DMA_FADD(base) _MMIO((base)+0x78)
1722 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
1723 #define RING_INSTPM(base) _MMIO((base)+0xc0)
1724 #define RING_MI_MODE(base) _MMIO((base)+0x9c)
1725 #define INSTPS _MMIO(0x2070) /* 965+ only */
1726 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
1727 #define ACTHD_I965 _MMIO(0x2074)
1728 #define HWS_PGA _MMIO(0x2080)
1729 #define HWS_ADDRESS_MASK 0xfffff000
1730 #define HWS_START_ADDRESS_SHIFT 4
1731 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
1732 #define PWRCTX_EN (1<<0)
1733 #define IPEIR _MMIO(0x2088)
1734 #define IPEHR _MMIO(0x208c)
1735 #define GEN2_INSTDONE _MMIO(0x2090)
1736 #define NOPID _MMIO(0x2094)
1737 #define HWSTAM _MMIO(0x2098)
1738 #define DMA_FADD_I8XX _MMIO(0x20d0)
1739 #define RING_BBSTATE(base) _MMIO((base)+0x110)
1740 #define RING_BB_PPGTT (1 << 5)
1741 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
1742 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
1743 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
1744 #define RING_BBADDR(base) _MMIO((base)+0x140)
1745 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
1746 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
1747 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
1748 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
1749 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
1750
1751 #define ERROR_GEN6 _MMIO(0x40a0)
1752 #define GEN7_ERR_INT _MMIO(0x44040)
1753 #define ERR_INT_POISON (1<<31)
1754 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
1755 #define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1756 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1757 #define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1758 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1759 #define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1760 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
1761 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1762 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
1763
1764 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
1765 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
1766
1767 #define FPGA_DBG _MMIO(0x42300)
1768 #define FPGA_DBG_RM_NOCLAIM (1<<31)
1769
1770 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
1771 #define CLAIM_ER_CLR (1 << 31)
1772 #define CLAIM_ER_OVERFLOW (1 << 16)
1773 #define CLAIM_ER_CTR_MASK 0xffff
1774
1775 #define DERRMR _MMIO(0x44050)
1776 /* Note that HBLANK events are reserved on bdw+ */
1777 #define DERRMR_PIPEA_SCANLINE (1<<0)
1778 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1779 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1780 #define DERRMR_PIPEA_VBLANK (1<<3)
1781 #define DERRMR_PIPEA_HBLANK (1<<5)
1782 #define DERRMR_PIPEB_SCANLINE (1<<8)
1783 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1784 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1785 #define DERRMR_PIPEB_VBLANK (1<<11)
1786 #define DERRMR_PIPEB_HBLANK (1<<13)
1787 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1788 #define DERRMR_PIPEC_SCANLINE (1<<14)
1789 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1790 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1791 #define DERRMR_PIPEC_VBLANK (1<<21)
1792 #define DERRMR_PIPEC_HBLANK (1<<22)
1793
1794
1795 /* GM45+ chicken bits -- debug workaround bits that may be required
1796 * for various sorts of correct behavior. The top 16 bits of each are
1797 * the enables for writing to the corresponding low bit.
1798 */
1799 #define _3D_CHICKEN _MMIO(0x2084)
1800 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1801 #define _3D_CHICKEN2 _MMIO(0x208c)
1802 /* Disables pipelining of read flushes past the SF-WIZ interface.
1803 * Required on all Ironlake steppings according to the B-Spec, but the
1804 * particular danger of not doing so is not specified.
1805 */
1806 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1807 #define _3D_CHICKEN3 _MMIO(0x2090)
1808 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1809 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1810 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1811 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1812
1813 #define MI_MODE _MMIO(0x209c)
1814 # define VS_TIMER_DISPATCH (1 << 6)
1815 # define MI_FLUSH_ENABLE (1 << 12)
1816 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1817 # define MODE_IDLE (1 << 9)
1818 # define STOP_RING (1 << 8)
1819
1820 #define GEN6_GT_MODE _MMIO(0x20d0)
1821 #define GEN7_GT_MODE _MMIO(0x7008)
1822 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1823 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1824 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1825 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1826 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
1827 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1828 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1829 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
1830
1831 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
1832 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
1833 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
1834
1835 /* WaClearTdlStateAckDirtyBits */
1836 #define GEN8_STATE_ACK _MMIO(0x20F0)
1837 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
1838 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
1839 #define GEN9_STATE_ACK_TDL0 (1 << 12)
1840 #define GEN9_STATE_ACK_TDL1 (1 << 13)
1841 #define GEN9_STATE_ACK_TDL2 (1 << 14)
1842 #define GEN9_STATE_ACK_TDL3 (1 << 15)
1843 #define GEN9_SUBSLICE_TDL_ACK_BITS \
1844 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
1845 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
1846
1847 #define GFX_MODE _MMIO(0x2520)
1848 #define GFX_MODE_GEN7 _MMIO(0x229c)
1849 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
1850 #define GFX_RUN_LIST_ENABLE (1<<15)
1851 #define GFX_INTERRUPT_STEERING (1<<14)
1852 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1853 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
1854 #define GFX_REPLAY_MODE (1<<11)
1855 #define GFX_PSMI_GRANULARITY (1<<10)
1856 #define GFX_PPGTT_ENABLE (1<<9)
1857 #define GEN8_GFX_PPGTT_48B (1<<7)
1858
1859 #define GFX_FORWARD_VBLANK_MASK (3<<5)
1860 #define GFX_FORWARD_VBLANK_NEVER (0<<5)
1861 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
1862 #define GFX_FORWARD_VBLANK_COND (2<<5)
1863
1864 #define VLV_DISPLAY_BASE 0x180000
1865 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1866 #define BXT_MIPI_BASE 0x60000
1867
1868 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1869 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1870 #define SCPD0 _MMIO(0x209c) /* 915+ only */
1871 #define IER _MMIO(0x20a0)
1872 #define IIR _MMIO(0x20a4)
1873 #define IMR _MMIO(0x20a8)
1874 #define ISR _MMIO(0x20ac)
1875 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1876 #define GINT_DIS (1<<22)
1877 #define GCFG_DIS (1<<8)
1878 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1879 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1880 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1881 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1882 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1883 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1884 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1885 #define VLV_PCBR_ADDR_SHIFT 12
1886
1887 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1888 #define EIR _MMIO(0x20b0)
1889 #define EMR _MMIO(0x20b4)
1890 #define ESR _MMIO(0x20b8)
1891 #define GM45_ERROR_PAGE_TABLE (1<<5)
1892 #define GM45_ERROR_MEM_PRIV (1<<4)
1893 #define I915_ERROR_PAGE_TABLE (1<<4)
1894 #define GM45_ERROR_CP_PRIV (1<<3)
1895 #define I915_ERROR_MEMORY_REFRESH (1<<1)
1896 #define I915_ERROR_INSTRUCTION (1<<0)
1897 #define INSTPM _MMIO(0x20c0)
1898 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
1899 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1900 will not assert AGPBUSY# and will only
1901 be delivered when out of C3. */
1902 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1903 #define INSTPM_TLB_INVALIDATE (1<<9)
1904 #define INSTPM_SYNC_FLUSH (1<<5)
1905 #define ACTHD _MMIO(0x20c8)
1906 #define MEM_MODE _MMIO(0x20cc)
1907 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1908 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1909 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1910 #define FW_BLC _MMIO(0x20d8)
1911 #define FW_BLC2 _MMIO(0x20dc)
1912 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1913 #define FW_BLC_SELF_EN_MASK (1<<31)
1914 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1915 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
1916 #define MM_BURST_LENGTH 0x00700000
1917 #define MM_FIFO_WATERMARK 0x0001F000
1918 #define LM_BURST_LENGTH 0x00000700
1919 #define LM_FIFO_WATERMARK 0x0000001F
1920 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1921
1922 /* Make render/texture TLB fetches lower priorty than associated data
1923 * fetches. This is not turned on by default
1924 */
1925 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1926
1927 /* Isoch request wait on GTT enable (Display A/B/C streams).
1928 * Make isoch requests stall on the TLB update. May cause
1929 * display underruns (test mode only)
1930 */
1931 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1932
1933 /* Block grant count for isoch requests when block count is
1934 * set to a finite value.
1935 */
1936 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1937 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1938 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1939 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1940 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1941
1942 /* Enable render writes to complete in C2/C3/C4 power states.
1943 * If this isn't enabled, render writes are prevented in low
1944 * power states. That seems bad to me.
1945 */
1946 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1947
1948 /* This acknowledges an async flip immediately instead
1949 * of waiting for 2TLB fetches.
1950 */
1951 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1952
1953 /* Enables non-sequential data reads through arbiter
1954 */
1955 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1956
1957 /* Disable FSB snooping of cacheable write cycles from binner/render
1958 * command stream
1959 */
1960 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1961
1962 /* Arbiter time slice for non-isoch streams */
1963 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1964 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1965 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1966 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1967 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1968 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1969 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1970 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1971 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1972
1973 /* Low priority grace period page size */
1974 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1975 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1976
1977 /* Disable display A/B trickle feed */
1978 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1979
1980 /* Set display plane priority */
1981 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1982 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1983
1984 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
1985 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1986 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1987
1988 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
1989 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1990 #define CM0_IZ_OPT_DISABLE (1<<6)
1991 #define CM0_ZR_OPT_DISABLE (1<<5)
1992 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1993 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
1994 #define CM0_COLOR_EVICT_DISABLE (1<<3)
1995 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
1996 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1997 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
1998 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1999 #define GFX_FLSH_CNTL_EN (1<<0)
2000 #define ECOSKPD _MMIO(0x21d0)
2001 #define ECO_GATING_CX_ONLY (1<<3)
2002 #define ECO_FLIP_DONE (1<<0)
2003
2004 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2005 #define RC_OP_FLUSH_ENABLE (1<<0)
2006 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
2007 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2008 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
2009 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
2010 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
2011
2012 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2013 #define GEN6_BLITTER_LOCK_SHIFT 16
2014 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2015
2016 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2017 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2018 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2019 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
2020
2021 /* Fuse readout registers for GT */
2022 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2023 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2024 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2025 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2026 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2027 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2028 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2029 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2030 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2031 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2032 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2033
2034 #define GEN8_FUSE2 _MMIO(0x9120)
2035 #define GEN8_F2_SS_DIS_SHIFT 21
2036 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2037 #define GEN8_F2_S_ENA_SHIFT 25
2038 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2039
2040 #define GEN9_F2_SS_DIS_SHIFT 20
2041 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2042
2043 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2044 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2045 #define GEN8_EU_DIS0_S1_SHIFT 24
2046 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2047
2048 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2049 #define GEN8_EU_DIS1_S1_MASK 0xffff
2050 #define GEN8_EU_DIS1_S2_SHIFT 16
2051 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2052
2053 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2054 #define GEN8_EU_DIS2_S2_MASK 0xff
2055
2056 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
2057
2058 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2059 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2060 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2061 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2062 #define GEN6_BSD_GO_INDICATOR (1 << 4)
2063
2064 /* On modern GEN architectures interrupt control consists of two sets
2065 * of registers. The first set pertains to the ring generating the
2066 * interrupt. The second control is for the functional block generating the
2067 * interrupt. These are PM, GT, DE, etc.
2068 *
2069 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2070 * GT interrupt bits, so we don't need to duplicate the defines.
2071 *
2072 * These defines should cover us well from SNB->HSW with minor exceptions
2073 * it can also work on ILK.
2074 */
2075 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2076 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2077 #define GT_BLT_USER_INTERRUPT (1 << 22)
2078 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2079 #define GT_BSD_USER_INTERRUPT (1 << 12)
2080 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2081 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2082 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2083 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2084 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2085 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2086 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2087 #define GT_RENDER_USER_INTERRUPT (1 << 0)
2088
2089 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2090 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2091
2092 #define GT_PARITY_ERROR(dev) \
2093 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2094 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2095
2096 /* These are all the "old" interrupts */
2097 #define ILK_BSD_USER_INTERRUPT (1<<5)
2098
2099 #define I915_PM_INTERRUPT (1<<31)
2100 #define I915_ISP_INTERRUPT (1<<22)
2101 #define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2102 #define I915_LPE_PIPE_A_INTERRUPT (1<<20)
2103 #define I915_MIPIC_INTERRUPT (1<<19)
2104 #define I915_MIPIA_INTERRUPT (1<<18)
2105 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2106 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
2107 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2108 #define I915_MASTER_ERROR_INTERRUPT (1<<15)
2109 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
2110 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
2111 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
2112 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
2113 #define I915_HWB_OOM_INTERRUPT (1<<13)
2114 #define I915_LPE_PIPE_C_INTERRUPT (1<<12)
2115 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
2116 #define I915_MISC_INTERRUPT (1<<11)
2117 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
2118 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
2119 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
2120 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
2121 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
2122 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
2123 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2124 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2125 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2126 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2127 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
2128 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2129 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
2130 #define I915_DEBUG_INTERRUPT (1<<2)
2131 #define I915_WINVALID_INTERRUPT (1<<1)
2132 #define I915_USER_INTERRUPT (1<<1)
2133 #define I915_ASLE_INTERRUPT (1<<0)
2134 #define I915_BSD_USER_INTERRUPT (1<<25)
2135
2136 #define GEN6_BSD_RNCID _MMIO(0x12198)
2137
2138 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2139 #define GEN7_FF_SCHED_MASK 0x0077070
2140 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2141 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2142 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2143 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2144 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2145 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2146 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2147 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2148 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2149 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
2150 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2151 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2152 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2153 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
2154
2155 /*
2156 * Framebuffer compression (915+ only)
2157 */
2158
2159 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2160 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2161 #define FBC_CONTROL _MMIO(0x3208)
2162 #define FBC_CTL_EN (1<<31)
2163 #define FBC_CTL_PERIODIC (1<<30)
2164 #define FBC_CTL_INTERVAL_SHIFT (16)
2165 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2166 #define FBC_CTL_C3_IDLE (1<<13)
2167 #define FBC_CTL_STRIDE_SHIFT (5)
2168 #define FBC_CTL_FENCENO_SHIFT (0)
2169 #define FBC_COMMAND _MMIO(0x320c)
2170 #define FBC_CMD_COMPRESS (1<<0)
2171 #define FBC_STATUS _MMIO(0x3210)
2172 #define FBC_STAT_COMPRESSING (1<<31)
2173 #define FBC_STAT_COMPRESSED (1<<30)
2174 #define FBC_STAT_MODIFIED (1<<29)
2175 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
2176 #define FBC_CONTROL2 _MMIO(0x3214)
2177 #define FBC_CTL_FENCE_DBL (0<<4)
2178 #define FBC_CTL_IDLE_IMM (0<<2)
2179 #define FBC_CTL_IDLE_FULL (1<<2)
2180 #define FBC_CTL_IDLE_LINE (2<<2)
2181 #define FBC_CTL_IDLE_DEBUG (3<<2)
2182 #define FBC_CTL_CPU_FENCE (1<<1)
2183 #define FBC_CTL_PLANE(plane) ((plane)<<0)
2184 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2185 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
2186
2187 #define FBC_STATUS2 _MMIO(0x43214)
2188 #define FBC_COMPRESSION_MASK 0x7ff
2189
2190 #define FBC_LL_SIZE (1536)
2191
2192 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
2193 #define FBC_LLC_FULLY_OPEN (1<<30)
2194
2195 /* Framebuffer compression for GM45+ */
2196 #define DPFC_CB_BASE _MMIO(0x3200)
2197 #define DPFC_CONTROL _MMIO(0x3208)
2198 #define DPFC_CTL_EN (1<<31)
2199 #define DPFC_CTL_PLANE(plane) ((plane)<<30)
2200 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
2201 #define DPFC_CTL_FENCE_EN (1<<29)
2202 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
2203 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
2204 #define DPFC_SR_EN (1<<10)
2205 #define DPFC_CTL_LIMIT_1X (0<<6)
2206 #define DPFC_CTL_LIMIT_2X (1<<6)
2207 #define DPFC_CTL_LIMIT_4X (2<<6)
2208 #define DPFC_RECOMP_CTL _MMIO(0x320c)
2209 #define DPFC_RECOMP_STALL_EN (1<<27)
2210 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
2211 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2212 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2213 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2214 #define DPFC_STATUS _MMIO(0x3210)
2215 #define DPFC_INVAL_SEG_SHIFT (16)
2216 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
2217 #define DPFC_COMP_SEG_SHIFT (0)
2218 #define DPFC_COMP_SEG_MASK (0x000003ff)
2219 #define DPFC_STATUS2 _MMIO(0x3214)
2220 #define DPFC_FENCE_YOFF _MMIO(0x3218)
2221 #define DPFC_CHICKEN _MMIO(0x3224)
2222 #define DPFC_HT_MODIFY (1<<31)
2223
2224 /* Framebuffer compression for Ironlake */
2225 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
2226 #define ILK_DPFC_CONTROL _MMIO(0x43208)
2227 #define FBC_CTL_FALSE_COLOR (1<<10)
2228 /* The bit 28-8 is reserved */
2229 #define DPFC_RESERVED (0x1FFFFF00)
2230 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
2231 #define ILK_DPFC_STATUS _MMIO(0x43210)
2232 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2233 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
2234 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
2235 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
2236 #define ILK_FBC_RT_BASE _MMIO(0x2128)
2237 #define ILK_FBC_RT_VALID (1<<0)
2238 #define SNB_FBC_FRONT_BUFFER (1<<1)
2239
2240 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
2241 #define ILK_FBCQ_DIS (1<<22)
2242 #define ILK_PABSTRETCH_DIS (1<<21)
2243
2244
2245 /*
2246 * Framebuffer compression for Sandybridge
2247 *
2248 * The following two registers are of type GTTMMADR
2249 */
2250 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
2251 #define SNB_CPU_FENCE_ENABLE (1<<29)
2252 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
2253
2254 /* Framebuffer compression for Ivybridge */
2255 #define IVB_FBC_RT_BASE _MMIO(0x7020)
2256
2257 #define IPS_CTL _MMIO(0x43408)
2258 #define IPS_ENABLE (1 << 31)
2259
2260 #define MSG_FBC_REND_STATE _MMIO(0x50380)
2261 #define FBC_REND_NUKE (1<<2)
2262 #define FBC_REND_CACHE_CLEAN (1<<1)
2263
2264 /*
2265 * GPIO regs
2266 */
2267 #define GPIOA _MMIO(0x5010)
2268 #define GPIOB _MMIO(0x5014)
2269 #define GPIOC _MMIO(0x5018)
2270 #define GPIOD _MMIO(0x501c)
2271 #define GPIOE _MMIO(0x5020)
2272 #define GPIOF _MMIO(0x5024)
2273 #define GPIOG _MMIO(0x5028)
2274 #define GPIOH _MMIO(0x502c)
2275 # define GPIO_CLOCK_DIR_MASK (1 << 0)
2276 # define GPIO_CLOCK_DIR_IN (0 << 1)
2277 # define GPIO_CLOCK_DIR_OUT (1 << 1)
2278 # define GPIO_CLOCK_VAL_MASK (1 << 2)
2279 # define GPIO_CLOCK_VAL_OUT (1 << 3)
2280 # define GPIO_CLOCK_VAL_IN (1 << 4)
2281 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2282 # define GPIO_DATA_DIR_MASK (1 << 8)
2283 # define GPIO_DATA_DIR_IN (0 << 9)
2284 # define GPIO_DATA_DIR_OUT (1 << 9)
2285 # define GPIO_DATA_VAL_MASK (1 << 10)
2286 # define GPIO_DATA_VAL_OUT (1 << 11)
2287 # define GPIO_DATA_VAL_IN (1 << 12)
2288 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2289
2290 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2291 #define GMBUS_RATE_100KHZ (0<<8)
2292 #define GMBUS_RATE_50KHZ (1<<8)
2293 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2294 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2295 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
2296 #define GMBUS_PIN_DISABLED 0
2297 #define GMBUS_PIN_SSC 1
2298 #define GMBUS_PIN_VGADDC 2
2299 #define GMBUS_PIN_PANEL 3
2300 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2301 #define GMBUS_PIN_DPC 4 /* HDMIC */
2302 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2303 #define GMBUS_PIN_DPD 6 /* HDMID */
2304 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
2305 #define GMBUS_PIN_1_BXT 1
2306 #define GMBUS_PIN_2_BXT 2
2307 #define GMBUS_PIN_3_BXT 3
2308 #define GMBUS_NUM_PINS 7 /* including 0 */
2309 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2310 #define GMBUS_SW_CLR_INT (1<<31)
2311 #define GMBUS_SW_RDY (1<<30)
2312 #define GMBUS_ENT (1<<29) /* enable timeout */
2313 #define GMBUS_CYCLE_NONE (0<<25)
2314 #define GMBUS_CYCLE_WAIT (1<<25)
2315 #define GMBUS_CYCLE_INDEX (2<<25)
2316 #define GMBUS_CYCLE_STOP (4<<25)
2317 #define GMBUS_BYTE_COUNT_SHIFT 16
2318 #define GMBUS_BYTE_COUNT_MAX 256U
2319 #define GMBUS_SLAVE_INDEX_SHIFT 8
2320 #define GMBUS_SLAVE_ADDR_SHIFT 1
2321 #define GMBUS_SLAVE_READ (1<<0)
2322 #define GMBUS_SLAVE_WRITE (0<<0)
2323 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
2324 #define GMBUS_INUSE (1<<15)
2325 #define GMBUS_HW_WAIT_PHASE (1<<14)
2326 #define GMBUS_STALL_TIMEOUT (1<<13)
2327 #define GMBUS_INT (1<<12)
2328 #define GMBUS_HW_RDY (1<<11)
2329 #define GMBUS_SATOER (1<<10)
2330 #define GMBUS_ACTIVE (1<<9)
2331 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2332 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2333 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2334 #define GMBUS_NAK_EN (1<<3)
2335 #define GMBUS_IDLE_EN (1<<2)
2336 #define GMBUS_HW_WAIT_EN (1<<1)
2337 #define GMBUS_HW_RDY_EN (1<<0)
2338 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2339 #define GMBUS_2BYTE_INDEX_EN (1<<31)
2340
2341 /*
2342 * Clock control & power management
2343 */
2344 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2345 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2346 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2347 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2348
2349 #define VGA0 _MMIO(0x6000)
2350 #define VGA1 _MMIO(0x6004)
2351 #define VGA_PD _MMIO(0x6010)
2352 #define VGA0_PD_P2_DIV_4 (1 << 7)
2353 #define VGA0_PD_P1_DIV_2 (1 << 5)
2354 #define VGA0_PD_P1_SHIFT 0
2355 #define VGA0_PD_P1_MASK (0x1f << 0)
2356 #define VGA1_PD_P2_DIV_4 (1 << 15)
2357 #define VGA1_PD_P1_DIV_2 (1 << 13)
2358 #define VGA1_PD_P1_SHIFT 8
2359 #define VGA1_PD_P1_MASK (0x1f << 8)
2360 #define DPLL_VCO_ENABLE (1 << 31)
2361 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
2362 #define DPLL_DVO_2X_MODE (1 << 30)
2363 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
2364 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
2365 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
2366 #define DPLL_VGA_MODE_DIS (1 << 28)
2367 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2368 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2369 #define DPLL_MODE_MASK (3 << 26)
2370 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2371 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2372 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2373 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2374 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2375 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
2376 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
2377 #define DPLL_LOCK_VLV (1<<15)
2378 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
2379 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2380 #define DPLL_SSC_REF_CLK_CHV (1<<13)
2381 #define DPLL_PORTC_READY_MASK (0xf << 4)
2382 #define DPLL_PORTB_READY_MASK (0xf)
2383
2384 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
2385
2386 /* Additional CHV pll/phy registers */
2387 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
2388 #define DPLL_PORTD_READY_MASK (0xf)
2389 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
2390 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
2391 #define PHY_LDO_DELAY_0NS 0x0
2392 #define PHY_LDO_DELAY_200NS 0x1
2393 #define PHY_LDO_DELAY_600NS 0x2
2394 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
2395 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
2396 #define PHY_CH_SU_PSR 0x1
2397 #define PHY_CH_DEEP_PSR 0x7
2398 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2399 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
2400 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
2401 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2402 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
2403 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
2404
2405 /*
2406 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2407 * this field (only one bit may be set).
2408 */
2409 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2410 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
2411 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2412 /* i830, required in DVO non-gang */
2413 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
2414 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2415 #define PLL_REF_INPUT_DREFCLK (0 << 13)
2416 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2417 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2418 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2419 #define PLL_REF_INPUT_MASK (3 << 13)
2420 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
2421 /* Ironlake */
2422 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2423 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2424 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2425 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2426 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2427
2428 /*
2429 * Parallel to Serial Load Pulse phase selection.
2430 * Selects the phase for the 10X DPLL clock for the PCIe
2431 * digital display port. The range is 4 to 13; 10 or more
2432 * is just a flip delay. The default is 6
2433 */
2434 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2435 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2436 /*
2437 * SDVO multiplier for 945G/GM. Not used on 965.
2438 */
2439 #define SDVO_MULTIPLIER_MASK 0x000000ff
2440 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
2441 #define SDVO_MULTIPLIER_SHIFT_VGA 0
2442
2443 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2444 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2445 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2446 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2447
2448 /*
2449 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2450 *
2451 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2452 */
2453 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2454 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
2455 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2456 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2457 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2458 /*
2459 * SDVO/UDI pixel multiplier.
2460 *
2461 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2462 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2463 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2464 * dummy bytes in the datastream at an increased clock rate, with both sides of
2465 * the link knowing how many bytes are fill.
2466 *
2467 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2468 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2469 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2470 * through an SDVO command.
2471 *
2472 * This register field has values of multiplication factor minus 1, with
2473 * a maximum multiplier of 5 for SDVO.
2474 */
2475 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2476 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2477 /*
2478 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2479 * This best be set to the default value (3) or the CRT won't work. No,
2480 * I don't entirely understand what this does...
2481 */
2482 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2483 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
2484
2485 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
2486
2487 #define _FPA0 0x6040
2488 #define _FPA1 0x6044
2489 #define _FPB0 0x6048
2490 #define _FPB1 0x604c
2491 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
2492 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
2493 #define FP_N_DIV_MASK 0x003f0000
2494 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
2495 #define FP_N_DIV_SHIFT 16
2496 #define FP_M1_DIV_MASK 0x00003f00
2497 #define FP_M1_DIV_SHIFT 8
2498 #define FP_M2_DIV_MASK 0x0000003f
2499 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
2500 #define FP_M2_DIV_SHIFT 0
2501 #define DPLL_TEST _MMIO(0x606c)
2502 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2503 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2504 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2505 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2506 #define DPLLB_TEST_N_BYPASS (1 << 19)
2507 #define DPLLB_TEST_M_BYPASS (1 << 18)
2508 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2509 #define DPLLA_TEST_N_BYPASS (1 << 3)
2510 #define DPLLA_TEST_M_BYPASS (1 << 2)
2511 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2512 #define D_STATE _MMIO(0x6104)
2513 #define DSTATE_GFX_RESET_I830 (1<<6)
2514 #define DSTATE_PLL_D3_OFF (1<<3)
2515 #define DSTATE_GFX_CLOCK_GATING (1<<1)
2516 #define DSTATE_DOT_CLOCK_GATING (1<<0)
2517 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
2518 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2519 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2520 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2521 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2522 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2523 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2524 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2525 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2526 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2527 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2528 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2529 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2530 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2531 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2532 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2533 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2534 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2535 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2536 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2537 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2538 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2539 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2540 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2541 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2542 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2543 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2544 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2545 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
2546 /*
2547 * This bit must be set on the 830 to prevent hangs when turning off the
2548 * overlay scaler.
2549 */
2550 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2551 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2552 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2553 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2554 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2555
2556 #define RENCLK_GATE_D1 _MMIO(0x6204)
2557 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2558 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2559 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2560 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2561 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2562 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2563 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2564 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2565 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
2566 /* This bit must be unset on 855,865 */
2567 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
2568 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2569 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
2570 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
2571 /* This bit must be set on 855,865. */
2572 # define SV_CLOCK_GATE_DISABLE (1 << 0)
2573 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2574 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2575 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2576 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2577 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2578 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2579 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2580 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2581 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2582 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2583 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2584 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2585 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2586 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2587 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2588 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2589 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2590
2591 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
2592 /* This bit must always be set on 965G/965GM */
2593 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2594 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2595 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2596 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2597 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2598 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
2599 /* This bit must always be set on 965G */
2600 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2601 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2602 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2603 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2604 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2605 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2606 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2607 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2608 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2609 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2610 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2611 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2612 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2613 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2614 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2615 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2616 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2617 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2618 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2619
2620 #define RENCLK_GATE_D2 _MMIO(0x6208)
2621 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2622 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2623 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2624
2625 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
2626 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2627
2628 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
2629 #define DEUC _MMIO(0x6214) /* CRL only */
2630
2631 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
2632 #define FW_CSPWRDWNEN (1<<15)
2633
2634 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
2635
2636 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
2637 #define CDCLK_FREQ_SHIFT 4
2638 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2639 #define CZCLK_FREQ_MASK 0xf
2640
2641 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
2642 #define PFI_CREDIT_63 (9 << 28) /* chv only */
2643 #define PFI_CREDIT_31 (8 << 28) /* chv only */
2644 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2645 #define PFI_CREDIT_RESEND (1 << 27)
2646 #define VGA_FAST_MODE_DISABLE (1 << 14)
2647
2648 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
2649
2650 /*
2651 * Palette regs
2652 */
2653 #define PALETTE_A_OFFSET 0xa000
2654 #define PALETTE_B_OFFSET 0xa800
2655 #define CHV_PALETTE_C_OFFSET 0xc000
2656 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
2657 dev_priv->info.display_mmio_offset + (i) * 4)
2658
2659 /* MCH MMIO space */
2660
2661 /*
2662 * MCHBAR mirror.
2663 *
2664 * This mirrors the MCHBAR MMIO space whose location is determined by
2665 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2666 * every way. It is not accessible from the CP register read instructions.
2667 *
2668 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2669 * just read.
2670 */
2671 #define MCHBAR_MIRROR_BASE 0x10000
2672
2673 #define MCHBAR_MIRROR_BASE_SNB 0x140000
2674
2675 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
2676 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
2677 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
2678 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
2679
2680 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2681 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2682
2683 /* 915-945 and GM965 MCH register controlling DRAM channel access */
2684 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
2685 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2686 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2687 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2688 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
2689 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2690 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2691 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
2692 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2693
2694 /* Pineview MCH register contains DDR3 setting */
2695 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
2696 #define CSHRDDR3CTL_DDR3 (1 << 2)
2697
2698 /* 965 MCH register controlling DRAM channel configuration */
2699 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
2700 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
2701
2702 /* snb MCH registers for reading the DRAM channel configuration */
2703 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2704 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2705 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
2706 #define MAD_DIMM_ECC_MASK (0x3 << 24)
2707 #define MAD_DIMM_ECC_OFF (0x0 << 24)
2708 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2709 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2710 #define MAD_DIMM_ECC_ON (0x3 << 24)
2711 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2712 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2713 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2714 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2715 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2716 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2717 #define MAD_DIMM_A_SELECT (0x1 << 16)
2718 /* DIMM sizes are in multiples of 256mb. */
2719 #define MAD_DIMM_B_SIZE_SHIFT 8
2720 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2721 #define MAD_DIMM_A_SIZE_SHIFT 0
2722 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2723
2724 /* snb MCH registers for priority tuning */
2725 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2726 #define MCH_SSKPD_WM0_MASK 0x3f
2727 #define MCH_SSKPD_WM0_VAL 0xc
2728
2729 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
2730
2731 /* Clocking configuration register */
2732 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
2733 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2734 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2735 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2736 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2737 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2738 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2739 /* Note, below two are guess */
2740 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2741 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2742 #define CLKCFG_FSB_MASK (7 << 0)
2743 #define CLKCFG_MEM_533 (1 << 4)
2744 #define CLKCFG_MEM_667 (2 << 4)
2745 #define CLKCFG_MEM_800 (3 << 4)
2746 #define CLKCFG_MEM_MASK (7 << 4)
2747
2748 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
2749 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
2750
2751 #define TSC1 _MMIO(0x11001)
2752 #define TSE (1<<0)
2753 #define TR1 _MMIO(0x11006)
2754 #define TSFS _MMIO(0x11020)
2755 #define TSFS_SLOPE_MASK 0x0000ff00
2756 #define TSFS_SLOPE_SHIFT 8
2757 #define TSFS_INTR_MASK 0x000000ff
2758
2759 #define CRSTANDVID _MMIO(0x11100)
2760 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2761 #define PXVFREQ_PX_MASK 0x7f000000
2762 #define PXVFREQ_PX_SHIFT 24
2763 #define VIDFREQ_BASE _MMIO(0x11110)
2764 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2765 #define VIDFREQ2 _MMIO(0x11114)
2766 #define VIDFREQ3 _MMIO(0x11118)
2767 #define VIDFREQ4 _MMIO(0x1111c)
2768 #define VIDFREQ_P0_MASK 0x1f000000
2769 #define VIDFREQ_P0_SHIFT 24
2770 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2771 #define VIDFREQ_P0_CSCLK_SHIFT 20
2772 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2773 #define VIDFREQ_P0_CRCLK_SHIFT 16
2774 #define VIDFREQ_P1_MASK 0x00001f00
2775 #define VIDFREQ_P1_SHIFT 8
2776 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2777 #define VIDFREQ_P1_CSCLK_SHIFT 4
2778 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2779 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
2780 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
2781 #define INTTOEXT_MAP3_SHIFT 24
2782 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2783 #define INTTOEXT_MAP2_SHIFT 16
2784 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2785 #define INTTOEXT_MAP1_SHIFT 8
2786 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2787 #define INTTOEXT_MAP0_SHIFT 0
2788 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2789 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
2790 #define MEMCTL_CMD_MASK 0xe000
2791 #define MEMCTL_CMD_SHIFT 13
2792 #define MEMCTL_CMD_RCLK_OFF 0
2793 #define MEMCTL_CMD_RCLK_ON 1
2794 #define MEMCTL_CMD_CHFREQ 2
2795 #define MEMCTL_CMD_CHVID 3
2796 #define MEMCTL_CMD_VMMOFF 4
2797 #define MEMCTL_CMD_VMMON 5
2798 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2799 when command complete */
2800 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2801 #define MEMCTL_FREQ_SHIFT 8
2802 #define MEMCTL_SFCAVM (1<<7)
2803 #define MEMCTL_TGT_VID_MASK 0x007f
2804 #define MEMIHYST _MMIO(0x1117c)
2805 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
2806 #define MEMINT_RSEXIT_EN (1<<8)
2807 #define MEMINT_CX_SUPR_EN (1<<7)
2808 #define MEMINT_CONT_BUSY_EN (1<<6)
2809 #define MEMINT_AVG_BUSY_EN (1<<5)
2810 #define MEMINT_EVAL_CHG_EN (1<<4)
2811 #define MEMINT_MON_IDLE_EN (1<<3)
2812 #define MEMINT_UP_EVAL_EN (1<<2)
2813 #define MEMINT_DOWN_EVAL_EN (1<<1)
2814 #define MEMINT_SW_CMD_EN (1<<0)
2815 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
2816 #define MEM_RSEXIT_MASK 0xc000
2817 #define MEM_RSEXIT_SHIFT 14
2818 #define MEM_CONT_BUSY_MASK 0x3000
2819 #define MEM_CONT_BUSY_SHIFT 12
2820 #define MEM_AVG_BUSY_MASK 0x0c00
2821 #define MEM_AVG_BUSY_SHIFT 10
2822 #define MEM_EVAL_CHG_MASK 0x0300
2823 #define MEM_EVAL_BUSY_SHIFT 8
2824 #define MEM_MON_IDLE_MASK 0x00c0
2825 #define MEM_MON_IDLE_SHIFT 6
2826 #define MEM_UP_EVAL_MASK 0x0030
2827 #define MEM_UP_EVAL_SHIFT 4
2828 #define MEM_DOWN_EVAL_MASK 0x000c
2829 #define MEM_DOWN_EVAL_SHIFT 2
2830 #define MEM_SW_CMD_MASK 0x0003
2831 #define MEM_INT_STEER_GFX 0
2832 #define MEM_INT_STEER_CMR 1
2833 #define MEM_INT_STEER_SMI 2
2834 #define MEM_INT_STEER_SCI 3
2835 #define MEMINTRSTS _MMIO(0x11184)
2836 #define MEMINT_RSEXIT (1<<7)
2837 #define MEMINT_CONT_BUSY (1<<6)
2838 #define MEMINT_AVG_BUSY (1<<5)
2839 #define MEMINT_EVAL_CHG (1<<4)
2840 #define MEMINT_MON_IDLE (1<<3)
2841 #define MEMINT_UP_EVAL (1<<2)
2842 #define MEMINT_DOWN_EVAL (1<<1)
2843 #define MEMINT_SW_CMD (1<<0)
2844 #define MEMMODECTL _MMIO(0x11190)
2845 #define MEMMODE_BOOST_EN (1<<31)
2846 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2847 #define MEMMODE_BOOST_FREQ_SHIFT 24
2848 #define MEMMODE_IDLE_MODE_MASK 0x00030000
2849 #define MEMMODE_IDLE_MODE_SHIFT 16
2850 #define MEMMODE_IDLE_MODE_EVAL 0
2851 #define MEMMODE_IDLE_MODE_CONT 1
2852 #define MEMMODE_HWIDLE_EN (1<<15)
2853 #define MEMMODE_SWMODE_EN (1<<14)
2854 #define MEMMODE_RCLK_GATE (1<<13)
2855 #define MEMMODE_HW_UPDATE (1<<12)
2856 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2857 #define MEMMODE_FSTART_SHIFT 8
2858 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2859 #define MEMMODE_FMAX_SHIFT 4
2860 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2861 #define RCBMAXAVG _MMIO(0x1119c)
2862 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
2863 #define SWMEMCMD_RENDER_OFF (0 << 13)
2864 #define SWMEMCMD_RENDER_ON (1 << 13)
2865 #define SWMEMCMD_SWFREQ (2 << 13)
2866 #define SWMEMCMD_TARVID (3 << 13)
2867 #define SWMEMCMD_VRM_OFF (4 << 13)
2868 #define SWMEMCMD_VRM_ON (5 << 13)
2869 #define CMDSTS (1<<12)
2870 #define SFCAVM (1<<11)
2871 #define SWFREQ_MASK 0x0380 /* P0-7 */
2872 #define SWFREQ_SHIFT 7
2873 #define TARVID_MASK 0x001f
2874 #define MEMSTAT_CTG _MMIO(0x111a0)
2875 #define RCBMINAVG _MMIO(0x111a0)
2876 #define RCUPEI _MMIO(0x111b0)
2877 #define RCDNEI _MMIO(0x111b4)
2878 #define RSTDBYCTL _MMIO(0x111b8)
2879 #define RS1EN (1<<31)
2880 #define RS2EN (1<<30)
2881 #define RS3EN (1<<29)
2882 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2883 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2884 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2885 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2886 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2887 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2888 #define RSX_STATUS_MASK (7<<20)
2889 #define RSX_STATUS_ON (0<<20)
2890 #define RSX_STATUS_RC1 (1<<20)
2891 #define RSX_STATUS_RC1E (2<<20)
2892 #define RSX_STATUS_RS1 (3<<20)
2893 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2894 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2895 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2896 #define RSX_STATUS_RSVD2 (7<<20)
2897 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2898 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2899 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
2900 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2901 #define RS1CONTSAV_MASK (3<<14)
2902 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2903 #define RS1CONTSAV_RSVD (1<<14)
2904 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2905 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2906 #define NORMSLEXLAT_MASK (3<<12)
2907 #define SLOW_RS123 (0<<12)
2908 #define SLOW_RS23 (1<<12)
2909 #define SLOW_RS3 (2<<12)
2910 #define NORMAL_RS123 (3<<12)
2911 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2912 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2913 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2914 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2915 #define RS_CSTATE_MASK (3<<4)
2916 #define RS_CSTATE_C367_RS1 (0<<4)
2917 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2918 #define RS_CSTATE_RSVD (2<<4)
2919 #define RS_CSTATE_C367_RS2 (3<<4)
2920 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2921 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2922 #define VIDCTL _MMIO(0x111c0)
2923 #define VIDSTS _MMIO(0x111c8)
2924 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
2925 #define MEMSTAT_ILK _MMIO(0x111f8)
2926 #define MEMSTAT_VID_MASK 0x7f00
2927 #define MEMSTAT_VID_SHIFT 8
2928 #define MEMSTAT_PSTATE_MASK 0x00f8
2929 #define MEMSTAT_PSTATE_SHIFT 3
2930 #define MEMSTAT_MON_ACTV (1<<2)
2931 #define MEMSTAT_SRC_CTL_MASK 0x0003
2932 #define MEMSTAT_SRC_CTL_CORE 0
2933 #define MEMSTAT_SRC_CTL_TRB 1
2934 #define MEMSTAT_SRC_CTL_THM 2
2935 #define MEMSTAT_SRC_CTL_STDBY 3
2936 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
2937 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
2938 #define PMMISC _MMIO(0x11214)
2939 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2940 #define SDEW _MMIO(0x1124c)
2941 #define CSIEW0 _MMIO(0x11250)
2942 #define CSIEW1 _MMIO(0x11254)
2943 #define CSIEW2 _MMIO(0x11258)
2944 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
2945 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
2946 #define MCHAFE _MMIO(0x112c0)
2947 #define CSIEC _MMIO(0x112e0)
2948 #define DMIEC _MMIO(0x112e4)
2949 #define DDREC _MMIO(0x112e8)
2950 #define PEG0EC _MMIO(0x112ec)
2951 #define PEG1EC _MMIO(0x112f0)
2952 #define GFXEC _MMIO(0x112f4)
2953 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
2954 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
2955 #define ECR _MMIO(0x11600)
2956 #define ECR_GPFE (1<<31)
2957 #define ECR_IMONE (1<<30)
2958 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2959 #define OGW0 _MMIO(0x11608)
2960 #define OGW1 _MMIO(0x1160c)
2961 #define EG0 _MMIO(0x11610)
2962 #define EG1 _MMIO(0x11614)
2963 #define EG2 _MMIO(0x11618)
2964 #define EG3 _MMIO(0x1161c)
2965 #define EG4 _MMIO(0x11620)
2966 #define EG5 _MMIO(0x11624)
2967 #define EG6 _MMIO(0x11628)
2968 #define EG7 _MMIO(0x1162c)
2969 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
2970 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
2971 #define LCFUSE02 _MMIO(0x116c0)
2972 #define LCFUSE_HIV_MASK 0x000000ff
2973 #define CSIPLL0 _MMIO(0x12c10)
2974 #define DDRMPLL1 _MMIO(0X12c20)
2975 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
2976
2977 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
2978 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2979
2980 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2981 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
2982 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2983 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2984 #define BXT_RP_STATE_CAP _MMIO(0x138170)
2985
2986 /*
2987 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2988 * 8300) freezing up around GPU hangs. Looks as if even
2989 * scheduling/timer interrupts start misbehaving if the RPS
2990 * EI/thresholds are "bad", leading to a very sluggish or even
2991 * frozen machine.
2992 */
2993 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
2994 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2995 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
2996 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2997 (IS_BROXTON(dev_priv) ? \
2998 INTERVAL_0_833_US(us) : \
2999 INTERVAL_1_33_US(us)) : \
3000 INTERVAL_1_28_US(us))
3001
3002 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3003 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3004 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3005 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
3006 (IS_BROXTON(dev_priv) ? \
3007 INTERVAL_0_833_TO_US(interval) : \
3008 INTERVAL_1_33_TO_US(interval)) : \
3009 INTERVAL_1_28_TO_US(interval))
3010
3011 /*
3012 * Logical Context regs
3013 */
3014 #define CCID _MMIO(0x2180)
3015 #define CCID_EN (1<<0)
3016 /*
3017 * Notes on SNB/IVB/VLV context size:
3018 * - Power context is saved elsewhere (LLC or stolen)
3019 * - Ring/execlist context is saved on SNB, not on IVB
3020 * - Extended context size already includes render context size
3021 * - We always need to follow the extended context size.
3022 * SNB BSpec has comments indicating that we should use the
3023 * render context size instead if execlists are disabled, but
3024 * based on empirical testing that's just nonsense.
3025 * - Pipelined/VF state is saved on SNB/IVB respectively
3026 * - GT1 size just indicates how much of render context
3027 * doesn't need saving on GT1
3028 */
3029 #define CXT_SIZE _MMIO(0x21a0)
3030 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3031 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3032 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3033 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3034 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3035 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3036 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3037 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3038 #define GEN7_CXT_SIZE _MMIO(0x21a8)
3039 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3040 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3041 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3042 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3043 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3044 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3045 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3046 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3047 /* Haswell does have the CXT_SIZE register however it does not appear to be
3048 * valid. Now, docs explain in dwords what is in the context object. The full
3049 * size is 70720 bytes, however, the power context and execlist context will
3050 * never be saved (power context is stored elsewhere, and execlists don't work
3051 * on HSW) - so the final size, including the extra state required for the
3052 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
3053 */
3054 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
3055 /* Same as Haswell, but 72064 bytes now. */
3056 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
3057
3058 enum {
3059 INTEL_ADVANCED_CONTEXT = 0,
3060 INTEL_LEGACY_32B_CONTEXT,
3061 INTEL_ADVANCED_AD_CONTEXT,
3062 INTEL_LEGACY_64B_CONTEXT
3063 };
3064
3065 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3066 #define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\
3067 INTEL_LEGACY_64B_CONTEXT : \
3068 INTEL_LEGACY_32B_CONTEXT)
3069
3070 #define CHV_CLK_CTL1 _MMIO(0x101100)
3071 #define VLV_CLK_CTL2 _MMIO(0x101104)
3072 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3073
3074 /*
3075 * Overlay regs
3076 */
3077
3078 #define OVADD _MMIO(0x30000)
3079 #define DOVSTA _MMIO(0x30008)
3080 #define OC_BUF (0x3<<20)
3081 #define OGAMC5 _MMIO(0x30010)
3082 #define OGAMC4 _MMIO(0x30014)
3083 #define OGAMC3 _MMIO(0x30018)
3084 #define OGAMC2 _MMIO(0x3001c)
3085 #define OGAMC1 _MMIO(0x30020)
3086 #define OGAMC0 _MMIO(0x30024)
3087
3088 /*
3089 * GEN9 clock gating regs
3090 */
3091 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3092 #define PWM2_GATING_DIS (1 << 14)
3093 #define PWM1_GATING_DIS (1 << 13)
3094
3095 /*
3096 * Display engine regs
3097 */
3098
3099 /* Pipe A CRC regs */
3100 #define _PIPE_CRC_CTL_A 0x60050
3101 #define PIPE_CRC_ENABLE (1 << 31)
3102 /* ivb+ source selection */
3103 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3104 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3105 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3106 /* ilk+ source selection */
3107 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3108 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3109 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3110 /* embedded DP port on the north display block, reserved on ivb */
3111 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3112 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3113 /* vlv source selection */
3114 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3115 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3116 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3117 /* with DP port the pipe source is invalid */
3118 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3119 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3120 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3121 /* gen3+ source selection */
3122 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3123 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3124 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3125 /* with DP/TV port the pipe source is invalid */
3126 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3127 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3128 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3129 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3130 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3131 /* gen2 doesn't have source selection bits */
3132 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
3133
3134 #define _PIPE_CRC_RES_1_A_IVB 0x60064
3135 #define _PIPE_CRC_RES_2_A_IVB 0x60068
3136 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
3137 #define _PIPE_CRC_RES_4_A_IVB 0x60070
3138 #define _PIPE_CRC_RES_5_A_IVB 0x60074
3139
3140 #define _PIPE_CRC_RES_RED_A 0x60060
3141 #define _PIPE_CRC_RES_GREEN_A 0x60064
3142 #define _PIPE_CRC_RES_BLUE_A 0x60068
3143 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
3144 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
3145
3146 /* Pipe B CRC regs */
3147 #define _PIPE_CRC_RES_1_B_IVB 0x61064
3148 #define _PIPE_CRC_RES_2_B_IVB 0x61068
3149 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
3150 #define _PIPE_CRC_RES_4_B_IVB 0x61070
3151 #define _PIPE_CRC_RES_5_B_IVB 0x61074
3152
3153 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3154 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3155 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3156 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3157 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3158 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
3159
3160 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3161 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3162 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3163 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3164 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
3165
3166 /* Pipe A timing regs */
3167 #define _HTOTAL_A 0x60000
3168 #define _HBLANK_A 0x60004
3169 #define _HSYNC_A 0x60008
3170 #define _VTOTAL_A 0x6000c
3171 #define _VBLANK_A 0x60010
3172 #define _VSYNC_A 0x60014
3173 #define _PIPEASRC 0x6001c
3174 #define _BCLRPAT_A 0x60020
3175 #define _VSYNCSHIFT_A 0x60028
3176 #define _PIPE_MULT_A 0x6002c
3177
3178 /* Pipe B timing regs */
3179 #define _HTOTAL_B 0x61000
3180 #define _HBLANK_B 0x61004
3181 #define _HSYNC_B 0x61008
3182 #define _VTOTAL_B 0x6100c
3183 #define _VBLANK_B 0x61010
3184 #define _VSYNC_B 0x61014
3185 #define _PIPEBSRC 0x6101c
3186 #define _BCLRPAT_B 0x61020
3187 #define _VSYNCSHIFT_B 0x61028
3188 #define _PIPE_MULT_B 0x6102c
3189
3190 #define TRANSCODER_A_OFFSET 0x60000
3191 #define TRANSCODER_B_OFFSET 0x61000
3192 #define TRANSCODER_C_OFFSET 0x62000
3193 #define CHV_TRANSCODER_C_OFFSET 0x63000
3194 #define TRANSCODER_EDP_OFFSET 0x6f000
3195
3196 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
3197 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3198 dev_priv->info.display_mmio_offset)
3199
3200 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
3201 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
3202 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
3203 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
3204 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
3205 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
3206 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
3207 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
3208 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
3209 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
3210
3211 /* VLV eDP PSR registers */
3212 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
3213 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
3214 #define VLV_EDP_PSR_ENABLE (1<<0)
3215 #define VLV_EDP_PSR_RESET (1<<1)
3216 #define VLV_EDP_PSR_MODE_MASK (7<<2)
3217 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
3218 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
3219 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
3220 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
3221 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
3222 #define VLV_EDP_PSR_DBL_FRAME (1<<10)
3223 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
3224 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
3225 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
3226
3227 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3228 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3229 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
3230 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
3231 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
3232 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
3233
3234 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3235 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
3236 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
3237 #define VLV_EDP_PSR_CURR_STATE_MASK 7
3238 #define VLV_EDP_PSR_DISABLED (0<<0)
3239 #define VLV_EDP_PSR_INACTIVE (1<<0)
3240 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
3241 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
3242 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
3243 #define VLV_EDP_PSR_EXIT (5<<0)
3244 #define VLV_EDP_PSR_IN_TRANS (1<<7)
3245 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
3246
3247 /* HSW+ eDP PSR registers */
3248 #define HSW_EDP_PSR_BASE 0x64800
3249 #define BDW_EDP_PSR_BASE 0x6f800
3250 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
3251 #define EDP_PSR_ENABLE (1<<31)
3252 #define BDW_PSR_SINGLE_FRAME (1<<30)
3253 #define EDP_PSR_LINK_STANDBY (1<<27)
3254 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3255 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3256 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3257 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3258 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3259 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3260 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3261 #define EDP_PSR_TP1_TP2_SEL (0<<11)
3262 #define EDP_PSR_TP1_TP3_SEL (1<<11)
3263 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3264 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3265 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3266 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3267 #define EDP_PSR_TP1_TIME_500us (0<<4)
3268 #define EDP_PSR_TP1_TIME_100us (1<<4)
3269 #define EDP_PSR_TP1_TIME_2500us (2<<4)
3270 #define EDP_PSR_TP1_TIME_0us (3<<4)
3271 #define EDP_PSR_IDLE_FRAME_SHIFT 0
3272
3273 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
3274 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
3275
3276 #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
3277 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
3278 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3279 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3280 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3281 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3282 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3283 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3284 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3285 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
3286 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3287 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3288 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3289 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3290 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3291 #define EDP_PSR_STATUS_COUNT_SHIFT 16
3292 #define EDP_PSR_STATUS_COUNT_MASK 0xf
3293 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3294 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3295 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3296 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3297 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3298 #define EDP_PSR_STATUS_IDLE_MASK 0xf
3299
3300 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
3301 #define EDP_PSR_PERF_CNT_MASK 0xffffff
3302
3303 #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
3304 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3305 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3306 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3307
3308 #define EDP_PSR2_CTL _MMIO(0x6f900)
3309 #define EDP_PSR2_ENABLE (1<<31)
3310 #define EDP_SU_TRACK_ENABLE (1<<30)
3311 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3312 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3313 #define EDP_PSR2_TP2_TIME_500 (0<<8)
3314 #define EDP_PSR2_TP2_TIME_100 (1<<8)
3315 #define EDP_PSR2_TP2_TIME_2500 (2<<8)
3316 #define EDP_PSR2_TP2_TIME_50 (3<<8)
3317 #define EDP_PSR2_TP2_TIME_MASK (3<<8)
3318 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3319 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3320 #define EDP_PSR2_IDLE_MASK 0xf
3321
3322 /* VGA port control */
3323 #define ADPA _MMIO(0x61100)
3324 #define PCH_ADPA _MMIO(0xe1100)
3325 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
3326
3327 #define ADPA_DAC_ENABLE (1<<31)
3328 #define ADPA_DAC_DISABLE 0
3329 #define ADPA_PIPE_SELECT_MASK (1<<30)
3330 #define ADPA_PIPE_A_SELECT 0
3331 #define ADPA_PIPE_B_SELECT (1<<30)
3332 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3333 /* CPT uses bits 29:30 for pch transcoder select */
3334 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3335 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3336 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3337 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3338 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3339 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3340 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3341 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3342 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3343 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3344 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3345 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3346 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3347 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3348 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3349 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3350 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3351 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3352 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3353 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
3354 #define ADPA_SETS_HVPOLARITY 0
3355 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
3356 #define ADPA_VSYNC_CNTL_ENABLE 0
3357 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
3358 #define ADPA_HSYNC_CNTL_ENABLE 0
3359 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3360 #define ADPA_VSYNC_ACTIVE_LOW 0
3361 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3362 #define ADPA_HSYNC_ACTIVE_LOW 0
3363 #define ADPA_DPMS_MASK (~(3<<10))
3364 #define ADPA_DPMS_ON (0<<10)
3365 #define ADPA_DPMS_SUSPEND (1<<10)
3366 #define ADPA_DPMS_STANDBY (2<<10)
3367 #define ADPA_DPMS_OFF (3<<10)
3368
3369
3370 /* Hotplug control (945+ only) */
3371 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
3372 #define PORTB_HOTPLUG_INT_EN (1 << 29)
3373 #define PORTC_HOTPLUG_INT_EN (1 << 28)
3374 #define PORTD_HOTPLUG_INT_EN (1 << 27)
3375 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
3376 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
3377 #define TV_HOTPLUG_INT_EN (1 << 18)
3378 #define CRT_HOTPLUG_INT_EN (1 << 9)
3379 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3380 PORTC_HOTPLUG_INT_EN | \
3381 PORTD_HOTPLUG_INT_EN | \
3382 SDVOC_HOTPLUG_INT_EN | \
3383 SDVOB_HOTPLUG_INT_EN | \
3384 CRT_HOTPLUG_INT_EN)
3385 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
3386 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3387 /* must use period 64 on GM45 according to docs */
3388 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3389 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3390 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3391 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3392 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3393 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3394 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3395 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3396 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3397 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3398 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3399 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
3400
3401 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
3402 /*
3403 * HDMI/DP bits are g4x+
3404 *
3405 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3406 * Please check the detailed lore in the commit message for for experimental
3407 * evidence.
3408 */
3409 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3410 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
3411 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
3412 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
3413 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3414 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
3415 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
3416 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
3417 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
3418 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3419 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
3420 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
3421 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3422 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
3423 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
3424 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3425 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
3426 /* CRT/TV common between gen3+ */
3427 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
3428 #define TV_HOTPLUG_INT_STATUS (1 << 10)
3429 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3430 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3431 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3432 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
3433 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3434 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3435 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
3436 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3437
3438 /* SDVO is different across gen3/4 */
3439 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3440 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
3441 /*
3442 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3443 * since reality corrobates that they're the same as on gen3. But keep these
3444 * bits here (and the comment!) to help any other lost wanderers back onto the
3445 * right tracks.
3446 */
3447 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3448 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3449 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3450 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
3451 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3452 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3453 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3454 PORTB_HOTPLUG_INT_STATUS | \
3455 PORTC_HOTPLUG_INT_STATUS | \
3456 PORTD_HOTPLUG_INT_STATUS)
3457
3458 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3459 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3460 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3461 PORTB_HOTPLUG_INT_STATUS | \
3462 PORTC_HOTPLUG_INT_STATUS | \
3463 PORTD_HOTPLUG_INT_STATUS)
3464
3465 /* SDVO and HDMI port control.
3466 * The same register may be used for SDVO or HDMI */
3467 #define _GEN3_SDVOB 0x61140
3468 #define _GEN3_SDVOC 0x61160
3469 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
3470 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
3471 #define GEN4_HDMIB GEN3_SDVOB
3472 #define GEN4_HDMIC GEN3_SDVOC
3473 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
3474 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
3475 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
3476 #define PCH_SDVOB _MMIO(0xe1140)
3477 #define PCH_HDMIB PCH_SDVOB
3478 #define PCH_HDMIC _MMIO(0xe1150)
3479 #define PCH_HDMID _MMIO(0xe1160)
3480
3481 #define PORT_DFT_I9XX _MMIO(0x61150)
3482 #define DC_BALANCE_RESET (1 << 25)
3483 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
3484 #define DC_BALANCE_RESET_VLV (1 << 31)
3485 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3486 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
3487 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
3488 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
3489
3490 /* Gen 3 SDVO bits: */
3491 #define SDVO_ENABLE (1 << 31)
3492 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3493 #define SDVO_PIPE_SEL_MASK (1 << 30)
3494 #define SDVO_PIPE_B_SELECT (1 << 30)
3495 #define SDVO_STALL_SELECT (1 << 29)
3496 #define SDVO_INTERRUPT_ENABLE (1 << 26)
3497 /*
3498 * 915G/GM SDVO pixel multiplier.
3499 * Programmed value is multiplier - 1, up to 5x.
3500 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3501 */
3502 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
3503 #define SDVO_PORT_MULTIPLY_SHIFT 23
3504 #define SDVO_PHASE_SELECT_MASK (15 << 19)
3505 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3506 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3507 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3508 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3509 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3510 #define SDVO_DETECTED (1 << 2)
3511 /* Bits to be preserved when writing */
3512 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3513 SDVO_INTERRUPT_ENABLE)
3514 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3515
3516 /* Gen 4 SDVO/HDMI bits: */
3517 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
3518 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
3519 #define SDVO_ENCODING_SDVO (0 << 10)
3520 #define SDVO_ENCODING_HDMI (2 << 10)
3521 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3522 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
3523 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
3524 #define SDVO_AUDIO_ENABLE (1 << 6)
3525 /* VSYNC/HSYNC bits new with 965, default is to be set */
3526 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3527 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3528
3529 /* Gen 5 (IBX) SDVO/HDMI bits: */
3530 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
3531 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3532
3533 /* Gen 6 (CPT) SDVO/HDMI bits: */
3534 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3535 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
3536
3537 /* CHV SDVO/HDMI bits: */
3538 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3539 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3540
3541
3542 /* DVO port control */
3543 #define _DVOA 0x61120
3544 #define DVOA _MMIO(_DVOA)
3545 #define _DVOB 0x61140
3546 #define DVOB _MMIO(_DVOB)
3547 #define _DVOC 0x61160
3548 #define DVOC _MMIO(_DVOC)
3549 #define DVO_ENABLE (1 << 31)
3550 #define DVO_PIPE_B_SELECT (1 << 30)
3551 #define DVO_PIPE_STALL_UNUSED (0 << 28)
3552 #define DVO_PIPE_STALL (1 << 28)
3553 #define DVO_PIPE_STALL_TV (2 << 28)
3554 #define DVO_PIPE_STALL_MASK (3 << 28)
3555 #define DVO_USE_VGA_SYNC (1 << 15)
3556 #define DVO_DATA_ORDER_I740 (0 << 14)
3557 #define DVO_DATA_ORDER_FP (1 << 14)
3558 #define DVO_VSYNC_DISABLE (1 << 11)
3559 #define DVO_HSYNC_DISABLE (1 << 10)
3560 #define DVO_VSYNC_TRISTATE (1 << 9)
3561 #define DVO_HSYNC_TRISTATE (1 << 8)
3562 #define DVO_BORDER_ENABLE (1 << 7)
3563 #define DVO_DATA_ORDER_GBRG (1 << 6)
3564 #define DVO_DATA_ORDER_RGGB (0 << 6)
3565 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3566 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3567 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3568 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3569 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3570 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3571 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3572 #define DVO_PRESERVE_MASK (0x7<<24)
3573 #define DVOA_SRCDIM _MMIO(0x61124)
3574 #define DVOB_SRCDIM _MMIO(0x61144)
3575 #define DVOC_SRCDIM _MMIO(0x61164)
3576 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3577 #define DVO_SRCDIM_VERTICAL_SHIFT 0
3578
3579 /* LVDS port control */
3580 #define LVDS _MMIO(0x61180)
3581 /*
3582 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3583 * the DPLL semantics change when the LVDS is assigned to that pipe.
3584 */
3585 #define LVDS_PORT_EN (1 << 31)
3586 /* Selects pipe B for LVDS data. Must be set on pre-965. */
3587 #define LVDS_PIPEB_SELECT (1 << 30)
3588 #define LVDS_PIPE_MASK (1 << 30)
3589 #define LVDS_PIPE(pipe) ((pipe) << 30)
3590 /* LVDS dithering flag on 965/g4x platform */
3591 #define LVDS_ENABLE_DITHER (1 << 25)
3592 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
3593 #define LVDS_VSYNC_POLARITY (1 << 21)
3594 #define LVDS_HSYNC_POLARITY (1 << 20)
3595
3596 /* Enable border for unscaled (or aspect-scaled) display */
3597 #define LVDS_BORDER_ENABLE (1 << 15)
3598 /*
3599 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3600 * pixel.
3601 */
3602 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3603 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3604 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3605 /*
3606 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3607 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3608 * on.
3609 */
3610 #define LVDS_A3_POWER_MASK (3 << 6)
3611 #define LVDS_A3_POWER_DOWN (0 << 6)
3612 #define LVDS_A3_POWER_UP (3 << 6)
3613 /*
3614 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3615 * is set.
3616 */
3617 #define LVDS_CLKB_POWER_MASK (3 << 4)
3618 #define LVDS_CLKB_POWER_DOWN (0 << 4)
3619 #define LVDS_CLKB_POWER_UP (3 << 4)
3620 /*
3621 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3622 * setting for whether we are in dual-channel mode. The B3 pair will
3623 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3624 */
3625 #define LVDS_B0B3_POWER_MASK (3 << 2)
3626 #define LVDS_B0B3_POWER_DOWN (0 << 2)
3627 #define LVDS_B0B3_POWER_UP (3 << 2)
3628
3629 /* Video Data Island Packet control */
3630 #define VIDEO_DIP_DATA _MMIO(0x61178)
3631 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3632 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3633 * of the infoframe structure specified by CEA-861. */
3634 #define VIDEO_DIP_DATA_SIZE 32
3635 #define VIDEO_DIP_VSC_DATA_SIZE 36
3636 #define VIDEO_DIP_CTL _MMIO(0x61170)
3637 /* Pre HSW: */
3638 #define VIDEO_DIP_ENABLE (1 << 31)
3639 #define VIDEO_DIP_PORT(port) ((port) << 29)
3640 #define VIDEO_DIP_PORT_MASK (3 << 29)
3641 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
3642 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
3643 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
3644 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
3645 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
3646 #define VIDEO_DIP_SELECT_AVI (0 << 19)
3647 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3648 #define VIDEO_DIP_SELECT_SPD (3 << 19)
3649 #define VIDEO_DIP_SELECT_MASK (3 << 19)
3650 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
3651 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3652 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
3653 #define VIDEO_DIP_FREQ_MASK (3 << 16)
3654 /* HSW and later: */
3655 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3656 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
3657 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
3658 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3659 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
3660 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3661
3662 /* Panel power sequencing */
3663 #define PPS_BASE 0x61200
3664 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
3665 #define PCH_PPS_BASE 0xC7200
3666
3667 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
3668 PPS_BASE + (reg) + \
3669 (pps_idx) * 0x100)
3670
3671 #define _PP_STATUS 0x61200
3672 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
3673 #define PP_ON (1 << 31)
3674 /*
3675 * Indicates that all dependencies of the panel are on:
3676 *
3677 * - PLL enabled
3678 * - pipe enabled
3679 * - LVDS/DVOB/DVOC on
3680 */
3681 #define PP_READY (1 << 30)
3682 #define PP_SEQUENCE_NONE (0 << 28)
3683 #define PP_SEQUENCE_POWER_UP (1 << 28)
3684 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
3685 #define PP_SEQUENCE_MASK (3 << 28)
3686 #define PP_SEQUENCE_SHIFT 28
3687 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
3688 #define PP_SEQUENCE_STATE_MASK 0x0000000f
3689 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3690 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3691 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3692 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3693 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3694 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3695 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3696 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3697 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
3698
3699 #define _PP_CONTROL 0x61204
3700 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
3701 #define PANEL_UNLOCK_REGS (0xabcd << 16)
3702 #define PANEL_UNLOCK_MASK (0xffff << 16)
3703 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
3704 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
3705 #define EDP_FORCE_VDD (1 << 3)
3706 #define EDP_BLC_ENABLE (1 << 2)
3707 #define PANEL_POWER_RESET (1 << 1)
3708 #define PANEL_POWER_OFF (0 << 0)
3709 #define PANEL_POWER_ON (1 << 0)
3710
3711 #define _PP_ON_DELAYS 0x61208
3712 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
3713 #define PANEL_PORT_SELECT_SHIFT 30
3714 #define PANEL_PORT_SELECT_MASK (3 << 30)
3715 #define PANEL_PORT_SELECT_LVDS (0 << 30)
3716 #define PANEL_PORT_SELECT_DPA (1 << 30)
3717 #define PANEL_PORT_SELECT_DPC (2 << 30)
3718 #define PANEL_PORT_SELECT_DPD (3 << 30)
3719 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
3720 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
3721 #define PANEL_POWER_UP_DELAY_SHIFT 16
3722 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
3723 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
3724
3725 #define _PP_OFF_DELAYS 0x6120C
3726 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
3727 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
3728 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
3729 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
3730 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
3731
3732 #define _PP_DIVISOR 0x61210
3733 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
3734 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00
3735 #define PP_REFERENCE_DIVIDER_SHIFT 8
3736 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
3737 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
3738
3739 /* Panel fitting */
3740 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
3741 #define PFIT_ENABLE (1 << 31)
3742 #define PFIT_PIPE_MASK (3 << 29)
3743 #define PFIT_PIPE_SHIFT 29
3744 #define VERT_INTERP_DISABLE (0 << 10)
3745 #define VERT_INTERP_BILINEAR (1 << 10)
3746 #define VERT_INTERP_MASK (3 << 10)
3747 #define VERT_AUTO_SCALE (1 << 9)
3748 #define HORIZ_INTERP_DISABLE (0 << 6)
3749 #define HORIZ_INTERP_BILINEAR (1 << 6)
3750 #define HORIZ_INTERP_MASK (3 << 6)
3751 #define HORIZ_AUTO_SCALE (1 << 5)
3752 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3753 #define PFIT_FILTER_FUZZY (0 << 24)
3754 #define PFIT_SCALING_AUTO (0 << 26)
3755 #define PFIT_SCALING_PROGRAMMED (1 << 26)
3756 #define PFIT_SCALING_PILLAR (2 << 26)
3757 #define PFIT_SCALING_LETTER (3 << 26)
3758 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
3759 /* Pre-965 */
3760 #define PFIT_VERT_SCALE_SHIFT 20
3761 #define PFIT_VERT_SCALE_MASK 0xfff00000
3762 #define PFIT_HORIZ_SCALE_SHIFT 4
3763 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3764 /* 965+ */
3765 #define PFIT_VERT_SCALE_SHIFT_965 16
3766 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3767 #define PFIT_HORIZ_SCALE_SHIFT_965 0
3768 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3769
3770 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
3771
3772 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3773 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3774 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3775 _VLV_BLC_PWM_CTL2_B)
3776
3777 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3778 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3779 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3780 _VLV_BLC_PWM_CTL_B)
3781
3782 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3783 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3784 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3785 _VLV_BLC_HIST_CTL_B)
3786
3787 /* Backlight control */
3788 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3789 #define BLM_PWM_ENABLE (1 << 31)
3790 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3791 #define BLM_PIPE_SELECT (1 << 29)
3792 #define BLM_PIPE_SELECT_IVB (3 << 29)
3793 #define BLM_PIPE_A (0 << 29)
3794 #define BLM_PIPE_B (1 << 29)
3795 #define BLM_PIPE_C (2 << 29) /* ivb + */
3796 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3797 #define BLM_TRANSCODER_B BLM_PIPE_B
3798 #define BLM_TRANSCODER_C BLM_PIPE_C
3799 #define BLM_TRANSCODER_EDP (3 << 29)
3800 #define BLM_PIPE(pipe) ((pipe) << 29)
3801 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3802 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3803 #define BLM_PHASE_IN_ENABLE (1 << 25)
3804 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3805 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3806 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3807 #define BLM_PHASE_IN_COUNT_SHIFT (8)
3808 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3809 #define BLM_PHASE_IN_INCR_SHIFT (0)
3810 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3811 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
3812 /*
3813 * This is the most significant 15 bits of the number of backlight cycles in a
3814 * complete cycle of the modulated backlight control.
3815 *
3816 * The actual value is this field multiplied by two.
3817 */
3818 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3819 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3820 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3821 /*
3822 * This is the number of cycles out of the backlight modulation cycle for which
3823 * the backlight is on.
3824 *
3825 * This field must be no greater than the number of cycles in the complete
3826 * backlight modulation cycle.
3827 */
3828 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3829 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3830 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3831 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3832
3833 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
3834 #define BLM_HISTOGRAM_ENABLE (1 << 31)
3835
3836 /* New registers for PCH-split platforms. Safe where new bits show up, the
3837 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3838 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
3839 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
3840
3841 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
3842
3843 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3844 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3845 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
3846 #define BLM_PCH_PWM_ENABLE (1 << 31)
3847 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3848 #define BLM_PCH_POLARITY (1 << 29)
3849 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
3850
3851 #define UTIL_PIN_CTL _MMIO(0x48400)
3852 #define UTIL_PIN_ENABLE (1 << 31)
3853
3854 #define UTIL_PIN_PIPE(x) ((x) << 29)
3855 #define UTIL_PIN_PIPE_MASK (3 << 29)
3856 #define UTIL_PIN_MODE_PWM (1 << 24)
3857 #define UTIL_PIN_MODE_MASK (0xf << 24)
3858 #define UTIL_PIN_POLARITY (1 << 22)
3859
3860 /* BXT backlight register definition. */
3861 #define _BXT_BLC_PWM_CTL1 0xC8250
3862 #define BXT_BLC_PWM_ENABLE (1 << 31)
3863 #define BXT_BLC_PWM_POLARITY (1 << 29)
3864 #define _BXT_BLC_PWM_FREQ1 0xC8254
3865 #define _BXT_BLC_PWM_DUTY1 0xC8258
3866
3867 #define _BXT_BLC_PWM_CTL2 0xC8350
3868 #define _BXT_BLC_PWM_FREQ2 0xC8354
3869 #define _BXT_BLC_PWM_DUTY2 0xC8358
3870
3871 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
3872 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
3873 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
3874 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
3875 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
3876 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3877
3878 #define PCH_GTC_CTL _MMIO(0xe7000)
3879 #define PCH_GTC_ENABLE (1 << 31)
3880
3881 /* TV port control */
3882 #define TV_CTL _MMIO(0x68000)
3883 /* Enables the TV encoder */
3884 # define TV_ENC_ENABLE (1 << 31)
3885 /* Sources the TV encoder input from pipe B instead of A. */
3886 # define TV_ENC_PIPEB_SELECT (1 << 30)
3887 /* Outputs composite video (DAC A only) */
3888 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3889 /* Outputs SVideo video (DAC B/C) */
3890 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3891 /* Outputs Component video (DAC A/B/C) */
3892 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3893 /* Outputs Composite and SVideo (DAC A/B/C) */
3894 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3895 # define TV_TRILEVEL_SYNC (1 << 21)
3896 /* Enables slow sync generation (945GM only) */
3897 # define TV_SLOW_SYNC (1 << 20)
3898 /* Selects 4x oversampling for 480i and 576p */
3899 # define TV_OVERSAMPLE_4X (0 << 18)
3900 /* Selects 2x oversampling for 720p and 1080i */
3901 # define TV_OVERSAMPLE_2X (1 << 18)
3902 /* Selects no oversampling for 1080p */
3903 # define TV_OVERSAMPLE_NONE (2 << 18)
3904 /* Selects 8x oversampling */
3905 # define TV_OVERSAMPLE_8X (3 << 18)
3906 /* Selects progressive mode rather than interlaced */
3907 # define TV_PROGRESSIVE (1 << 17)
3908 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3909 # define TV_PAL_BURST (1 << 16)
3910 /* Field for setting delay of Y compared to C */
3911 # define TV_YC_SKEW_MASK (7 << 12)
3912 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3913 # define TV_ENC_SDP_FIX (1 << 11)
3914 /*
3915 * Enables a fix for the 915GM only.
3916 *
3917 * Not sure what it does.
3918 */
3919 # define TV_ENC_C0_FIX (1 << 10)
3920 /* Bits that must be preserved by software */
3921 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3922 # define TV_FUSE_STATE_MASK (3 << 4)
3923 /* Read-only state that reports all features enabled */
3924 # define TV_FUSE_STATE_ENABLED (0 << 4)
3925 /* Read-only state that reports that Macrovision is disabled in hardware*/
3926 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3927 /* Read-only state that reports that TV-out is disabled in hardware. */
3928 # define TV_FUSE_STATE_DISABLED (2 << 4)
3929 /* Normal operation */
3930 # define TV_TEST_MODE_NORMAL (0 << 0)
3931 /* Encoder test pattern 1 - combo pattern */
3932 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
3933 /* Encoder test pattern 2 - full screen vertical 75% color bars */
3934 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
3935 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
3936 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
3937 /* Encoder test pattern 4 - random noise */
3938 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
3939 /* Encoder test pattern 5 - linear color ramps */
3940 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
3941 /*
3942 * This test mode forces the DACs to 50% of full output.
3943 *
3944 * This is used for load detection in combination with TVDAC_SENSE_MASK
3945 */
3946 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3947 # define TV_TEST_MODE_MASK (7 << 0)
3948
3949 #define TV_DAC _MMIO(0x68004)
3950 # define TV_DAC_SAVE 0x00ffff00
3951 /*
3952 * Reports that DAC state change logic has reported change (RO).
3953 *
3954 * This gets cleared when TV_DAC_STATE_EN is cleared
3955 */
3956 # define TVDAC_STATE_CHG (1 << 31)
3957 # define TVDAC_SENSE_MASK (7 << 28)
3958 /* Reports that DAC A voltage is above the detect threshold */
3959 # define TVDAC_A_SENSE (1 << 30)
3960 /* Reports that DAC B voltage is above the detect threshold */
3961 # define TVDAC_B_SENSE (1 << 29)
3962 /* Reports that DAC C voltage is above the detect threshold */
3963 # define TVDAC_C_SENSE (1 << 28)
3964 /*
3965 * Enables DAC state detection logic, for load-based TV detection.
3966 *
3967 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3968 * to off, for load detection to work.
3969 */
3970 # define TVDAC_STATE_CHG_EN (1 << 27)
3971 /* Sets the DAC A sense value to high */
3972 # define TVDAC_A_SENSE_CTL (1 << 26)
3973 /* Sets the DAC B sense value to high */
3974 # define TVDAC_B_SENSE_CTL (1 << 25)
3975 /* Sets the DAC C sense value to high */
3976 # define TVDAC_C_SENSE_CTL (1 << 24)
3977 /* Overrides the ENC_ENABLE and DAC voltage levels */
3978 # define DAC_CTL_OVERRIDE (1 << 7)
3979 /* Sets the slew rate. Must be preserved in software */
3980 # define ENC_TVDAC_SLEW_FAST (1 << 6)
3981 # define DAC_A_1_3_V (0 << 4)
3982 # define DAC_A_1_1_V (1 << 4)
3983 # define DAC_A_0_7_V (2 << 4)
3984 # define DAC_A_MASK (3 << 4)
3985 # define DAC_B_1_3_V (0 << 2)
3986 # define DAC_B_1_1_V (1 << 2)
3987 # define DAC_B_0_7_V (2 << 2)
3988 # define DAC_B_MASK (3 << 2)
3989 # define DAC_C_1_3_V (0 << 0)
3990 # define DAC_C_1_1_V (1 << 0)
3991 # define DAC_C_0_7_V (2 << 0)
3992 # define DAC_C_MASK (3 << 0)
3993
3994 /*
3995 * CSC coefficients are stored in a floating point format with 9 bits of
3996 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3997 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3998 * -1 (0x3) being the only legal negative value.
3999 */
4000 #define TV_CSC_Y _MMIO(0x68010)
4001 # define TV_RY_MASK 0x07ff0000
4002 # define TV_RY_SHIFT 16
4003 # define TV_GY_MASK 0x00000fff
4004 # define TV_GY_SHIFT 0
4005
4006 #define TV_CSC_Y2 _MMIO(0x68014)
4007 # define TV_BY_MASK 0x07ff0000
4008 # define TV_BY_SHIFT 16
4009 /*
4010 * Y attenuation for component video.
4011 *
4012 * Stored in 1.9 fixed point.
4013 */
4014 # define TV_AY_MASK 0x000003ff
4015 # define TV_AY_SHIFT 0
4016
4017 #define TV_CSC_U _MMIO(0x68018)
4018 # define TV_RU_MASK 0x07ff0000
4019 # define TV_RU_SHIFT 16
4020 # define TV_GU_MASK 0x000007ff
4021 # define TV_GU_SHIFT 0
4022
4023 #define TV_CSC_U2 _MMIO(0x6801c)
4024 # define TV_BU_MASK 0x07ff0000
4025 # define TV_BU_SHIFT 16
4026 /*
4027 * U attenuation for component video.
4028 *
4029 * Stored in 1.9 fixed point.
4030 */
4031 # define TV_AU_MASK 0x000003ff
4032 # define TV_AU_SHIFT 0
4033
4034 #define TV_CSC_V _MMIO(0x68020)
4035 # define TV_RV_MASK 0x0fff0000
4036 # define TV_RV_SHIFT 16
4037 # define TV_GV_MASK 0x000007ff
4038 # define TV_GV_SHIFT 0
4039
4040 #define TV_CSC_V2 _MMIO(0x68024)
4041 # define TV_BV_MASK 0x07ff0000
4042 # define TV_BV_SHIFT 16
4043 /*
4044 * V attenuation for component video.
4045 *
4046 * Stored in 1.9 fixed point.
4047 */
4048 # define TV_AV_MASK 0x000007ff
4049 # define TV_AV_SHIFT 0
4050
4051 #define TV_CLR_KNOBS _MMIO(0x68028)
4052 /* 2s-complement brightness adjustment */
4053 # define TV_BRIGHTNESS_MASK 0xff000000
4054 # define TV_BRIGHTNESS_SHIFT 24
4055 /* Contrast adjustment, as a 2.6 unsigned floating point number */
4056 # define TV_CONTRAST_MASK 0x00ff0000
4057 # define TV_CONTRAST_SHIFT 16
4058 /* Saturation adjustment, as a 2.6 unsigned floating point number */
4059 # define TV_SATURATION_MASK 0x0000ff00
4060 # define TV_SATURATION_SHIFT 8
4061 /* Hue adjustment, as an integer phase angle in degrees */
4062 # define TV_HUE_MASK 0x000000ff
4063 # define TV_HUE_SHIFT 0
4064
4065 #define TV_CLR_LEVEL _MMIO(0x6802c)
4066 /* Controls the DAC level for black */
4067 # define TV_BLACK_LEVEL_MASK 0x01ff0000
4068 # define TV_BLACK_LEVEL_SHIFT 16
4069 /* Controls the DAC level for blanking */
4070 # define TV_BLANK_LEVEL_MASK 0x000001ff
4071 # define TV_BLANK_LEVEL_SHIFT 0
4072
4073 #define TV_H_CTL_1 _MMIO(0x68030)
4074 /* Number of pixels in the hsync. */
4075 # define TV_HSYNC_END_MASK 0x1fff0000
4076 # define TV_HSYNC_END_SHIFT 16
4077 /* Total number of pixels minus one in the line (display and blanking). */
4078 # define TV_HTOTAL_MASK 0x00001fff
4079 # define TV_HTOTAL_SHIFT 0
4080
4081 #define TV_H_CTL_2 _MMIO(0x68034)
4082 /* Enables the colorburst (needed for non-component color) */
4083 # define TV_BURST_ENA (1 << 31)
4084 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
4085 # define TV_HBURST_START_SHIFT 16
4086 # define TV_HBURST_START_MASK 0x1fff0000
4087 /* Length of the colorburst */
4088 # define TV_HBURST_LEN_SHIFT 0
4089 # define TV_HBURST_LEN_MASK 0x0001fff
4090
4091 #define TV_H_CTL_3 _MMIO(0x68038)
4092 /* End of hblank, measured in pixels minus one from start of hsync */
4093 # define TV_HBLANK_END_SHIFT 16
4094 # define TV_HBLANK_END_MASK 0x1fff0000
4095 /* Start of hblank, measured in pixels minus one from start of hsync */
4096 # define TV_HBLANK_START_SHIFT 0
4097 # define TV_HBLANK_START_MASK 0x0001fff
4098
4099 #define TV_V_CTL_1 _MMIO(0x6803c)
4100 /* XXX */
4101 # define TV_NBR_END_SHIFT 16
4102 # define TV_NBR_END_MASK 0x07ff0000
4103 /* XXX */
4104 # define TV_VI_END_F1_SHIFT 8
4105 # define TV_VI_END_F1_MASK 0x00003f00
4106 /* XXX */
4107 # define TV_VI_END_F2_SHIFT 0
4108 # define TV_VI_END_F2_MASK 0x0000003f
4109
4110 #define TV_V_CTL_2 _MMIO(0x68040)
4111 /* Length of vsync, in half lines */
4112 # define TV_VSYNC_LEN_MASK 0x07ff0000
4113 # define TV_VSYNC_LEN_SHIFT 16
4114 /* Offset of the start of vsync in field 1, measured in one less than the
4115 * number of half lines.
4116 */
4117 # define TV_VSYNC_START_F1_MASK 0x00007f00
4118 # define TV_VSYNC_START_F1_SHIFT 8
4119 /*
4120 * Offset of the start of vsync in field 2, measured in one less than the
4121 * number of half lines.
4122 */
4123 # define TV_VSYNC_START_F2_MASK 0x0000007f
4124 # define TV_VSYNC_START_F2_SHIFT 0
4125
4126 #define TV_V_CTL_3 _MMIO(0x68044)
4127 /* Enables generation of the equalization signal */
4128 # define TV_EQUAL_ENA (1 << 31)
4129 /* Length of vsync, in half lines */
4130 # define TV_VEQ_LEN_MASK 0x007f0000
4131 # define TV_VEQ_LEN_SHIFT 16
4132 /* Offset of the start of equalization in field 1, measured in one less than
4133 * the number of half lines.
4134 */
4135 # define TV_VEQ_START_F1_MASK 0x0007f00
4136 # define TV_VEQ_START_F1_SHIFT 8
4137 /*
4138 * Offset of the start of equalization in field 2, measured in one less than
4139 * the number of half lines.
4140 */
4141 # define TV_VEQ_START_F2_MASK 0x000007f
4142 # define TV_VEQ_START_F2_SHIFT 0
4143
4144 #define TV_V_CTL_4 _MMIO(0x68048)
4145 /*
4146 * Offset to start of vertical colorburst, measured in one less than the
4147 * number of lines from vertical start.
4148 */
4149 # define TV_VBURST_START_F1_MASK 0x003f0000
4150 # define TV_VBURST_START_F1_SHIFT 16
4151 /*
4152 * Offset to the end of vertical colorburst, measured in one less than the
4153 * number of lines from the start of NBR.
4154 */
4155 # define TV_VBURST_END_F1_MASK 0x000000ff
4156 # define TV_VBURST_END_F1_SHIFT 0
4157
4158 #define TV_V_CTL_5 _MMIO(0x6804c)
4159 /*
4160 * Offset to start of vertical colorburst, measured in one less than the
4161 * number of lines from vertical start.
4162 */
4163 # define TV_VBURST_START_F2_MASK 0x003f0000
4164 # define TV_VBURST_START_F2_SHIFT 16
4165 /*
4166 * Offset to the end of vertical colorburst, measured in one less than the
4167 * number of lines from the start of NBR.
4168 */
4169 # define TV_VBURST_END_F2_MASK 0x000000ff
4170 # define TV_VBURST_END_F2_SHIFT 0
4171
4172 #define TV_V_CTL_6 _MMIO(0x68050)
4173 /*
4174 * Offset to start of vertical colorburst, measured in one less than the
4175 * number of lines from vertical start.
4176 */
4177 # define TV_VBURST_START_F3_MASK 0x003f0000
4178 # define TV_VBURST_START_F3_SHIFT 16
4179 /*
4180 * Offset to the end of vertical colorburst, measured in one less than the
4181 * number of lines from the start of NBR.
4182 */
4183 # define TV_VBURST_END_F3_MASK 0x000000ff
4184 # define TV_VBURST_END_F3_SHIFT 0
4185
4186 #define TV_V_CTL_7 _MMIO(0x68054)
4187 /*
4188 * Offset to start of vertical colorburst, measured in one less than the
4189 * number of lines from vertical start.
4190 */
4191 # define TV_VBURST_START_F4_MASK 0x003f0000
4192 # define TV_VBURST_START_F4_SHIFT 16
4193 /*
4194 * Offset to the end of vertical colorburst, measured in one less than the
4195 * number of lines from the start of NBR.
4196 */
4197 # define TV_VBURST_END_F4_MASK 0x000000ff
4198 # define TV_VBURST_END_F4_SHIFT 0
4199
4200 #define TV_SC_CTL_1 _MMIO(0x68060)
4201 /* Turns on the first subcarrier phase generation DDA */
4202 # define TV_SC_DDA1_EN (1 << 31)
4203 /* Turns on the first subcarrier phase generation DDA */
4204 # define TV_SC_DDA2_EN (1 << 30)
4205 /* Turns on the first subcarrier phase generation DDA */
4206 # define TV_SC_DDA3_EN (1 << 29)
4207 /* Sets the subcarrier DDA to reset frequency every other field */
4208 # define TV_SC_RESET_EVERY_2 (0 << 24)
4209 /* Sets the subcarrier DDA to reset frequency every fourth field */
4210 # define TV_SC_RESET_EVERY_4 (1 << 24)
4211 /* Sets the subcarrier DDA to reset frequency every eighth field */
4212 # define TV_SC_RESET_EVERY_8 (2 << 24)
4213 /* Sets the subcarrier DDA to never reset the frequency */
4214 # define TV_SC_RESET_NEVER (3 << 24)
4215 /* Sets the peak amplitude of the colorburst.*/
4216 # define TV_BURST_LEVEL_MASK 0x00ff0000
4217 # define TV_BURST_LEVEL_SHIFT 16
4218 /* Sets the increment of the first subcarrier phase generation DDA */
4219 # define TV_SCDDA1_INC_MASK 0x00000fff
4220 # define TV_SCDDA1_INC_SHIFT 0
4221
4222 #define TV_SC_CTL_2 _MMIO(0x68064)
4223 /* Sets the rollover for the second subcarrier phase generation DDA */
4224 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
4225 # define TV_SCDDA2_SIZE_SHIFT 16
4226 /* Sets the increent of the second subcarrier phase generation DDA */
4227 # define TV_SCDDA2_INC_MASK 0x00007fff
4228 # define TV_SCDDA2_INC_SHIFT 0
4229
4230 #define TV_SC_CTL_3 _MMIO(0x68068)
4231 /* Sets the rollover for the third subcarrier phase generation DDA */
4232 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
4233 # define TV_SCDDA3_SIZE_SHIFT 16
4234 /* Sets the increent of the third subcarrier phase generation DDA */
4235 # define TV_SCDDA3_INC_MASK 0x00007fff
4236 # define TV_SCDDA3_INC_SHIFT 0
4237
4238 #define TV_WIN_POS _MMIO(0x68070)
4239 /* X coordinate of the display from the start of horizontal active */
4240 # define TV_XPOS_MASK 0x1fff0000
4241 # define TV_XPOS_SHIFT 16
4242 /* Y coordinate of the display from the start of vertical active (NBR) */
4243 # define TV_YPOS_MASK 0x00000fff
4244 # define TV_YPOS_SHIFT 0
4245
4246 #define TV_WIN_SIZE _MMIO(0x68074)
4247 /* Horizontal size of the display window, measured in pixels*/
4248 # define TV_XSIZE_MASK 0x1fff0000
4249 # define TV_XSIZE_SHIFT 16
4250 /*
4251 * Vertical size of the display window, measured in pixels.
4252 *
4253 * Must be even for interlaced modes.
4254 */
4255 # define TV_YSIZE_MASK 0x00000fff
4256 # define TV_YSIZE_SHIFT 0
4257
4258 #define TV_FILTER_CTL_1 _MMIO(0x68080)
4259 /*
4260 * Enables automatic scaling calculation.
4261 *
4262 * If set, the rest of the registers are ignored, and the calculated values can
4263 * be read back from the register.
4264 */
4265 # define TV_AUTO_SCALE (1 << 31)
4266 /*
4267 * Disables the vertical filter.
4268 *
4269 * This is required on modes more than 1024 pixels wide */
4270 # define TV_V_FILTER_BYPASS (1 << 29)
4271 /* Enables adaptive vertical filtering */
4272 # define TV_VADAPT (1 << 28)
4273 # define TV_VADAPT_MODE_MASK (3 << 26)
4274 /* Selects the least adaptive vertical filtering mode */
4275 # define TV_VADAPT_MODE_LEAST (0 << 26)
4276 /* Selects the moderately adaptive vertical filtering mode */
4277 # define TV_VADAPT_MODE_MODERATE (1 << 26)
4278 /* Selects the most adaptive vertical filtering mode */
4279 # define TV_VADAPT_MODE_MOST (3 << 26)
4280 /*
4281 * Sets the horizontal scaling factor.
4282 *
4283 * This should be the fractional part of the horizontal scaling factor divided
4284 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
4285 *
4286 * (src width - 1) / ((oversample * dest width) - 1)
4287 */
4288 # define TV_HSCALE_FRAC_MASK 0x00003fff
4289 # define TV_HSCALE_FRAC_SHIFT 0
4290
4291 #define TV_FILTER_CTL_2 _MMIO(0x68084)
4292 /*
4293 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4294 *
4295 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4296 */
4297 # define TV_VSCALE_INT_MASK 0x00038000
4298 # define TV_VSCALE_INT_SHIFT 15
4299 /*
4300 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4301 *
4302 * \sa TV_VSCALE_INT_MASK
4303 */
4304 # define TV_VSCALE_FRAC_MASK 0x00007fff
4305 # define TV_VSCALE_FRAC_SHIFT 0
4306
4307 #define TV_FILTER_CTL_3 _MMIO(0x68088)
4308 /*
4309 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4310 *
4311 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4312 *
4313 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4314 */
4315 # define TV_VSCALE_IP_INT_MASK 0x00038000
4316 # define TV_VSCALE_IP_INT_SHIFT 15
4317 /*
4318 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4319 *
4320 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4321 *
4322 * \sa TV_VSCALE_IP_INT_MASK
4323 */
4324 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4325 # define TV_VSCALE_IP_FRAC_SHIFT 0
4326
4327 #define TV_CC_CONTROL _MMIO(0x68090)
4328 # define TV_CC_ENABLE (1 << 31)
4329 /*
4330 * Specifies which field to send the CC data in.
4331 *
4332 * CC data is usually sent in field 0.
4333 */
4334 # define TV_CC_FID_MASK (1 << 27)
4335 # define TV_CC_FID_SHIFT 27
4336 /* Sets the horizontal position of the CC data. Usually 135. */
4337 # define TV_CC_HOFF_MASK 0x03ff0000
4338 # define TV_CC_HOFF_SHIFT 16
4339 /* Sets the vertical position of the CC data. Usually 21 */
4340 # define TV_CC_LINE_MASK 0x0000003f
4341 # define TV_CC_LINE_SHIFT 0
4342
4343 #define TV_CC_DATA _MMIO(0x68094)
4344 # define TV_CC_RDY (1 << 31)
4345 /* Second word of CC data to be transmitted. */
4346 # define TV_CC_DATA_2_MASK 0x007f0000
4347 # define TV_CC_DATA_2_SHIFT 16
4348 /* First word of CC data to be transmitted. */
4349 # define TV_CC_DATA_1_MASK 0x0000007f
4350 # define TV_CC_DATA_1_SHIFT 0
4351
4352 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
4353 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
4354 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
4355 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
4356
4357 /* Display Port */
4358 #define DP_A _MMIO(0x64000) /* eDP */
4359 #define DP_B _MMIO(0x64100)
4360 #define DP_C _MMIO(0x64200)
4361 #define DP_D _MMIO(0x64300)
4362
4363 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
4364 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
4365 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
4366
4367 #define DP_PORT_EN (1 << 31)
4368 #define DP_PIPEB_SELECT (1 << 30)
4369 #define DP_PIPE_MASK (1 << 30)
4370 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4371 #define DP_PIPE_MASK_CHV (3 << 16)
4372
4373 /* Link training mode - select a suitable mode for each stage */
4374 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
4375 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
4376 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4377 #define DP_LINK_TRAIN_OFF (3 << 28)
4378 #define DP_LINK_TRAIN_MASK (3 << 28)
4379 #define DP_LINK_TRAIN_SHIFT 28
4380 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4381 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
4382
4383 /* CPT Link training mode */
4384 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4385 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4386 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4387 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4388 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4389 #define DP_LINK_TRAIN_SHIFT_CPT 8
4390
4391 /* Signal voltages. These are mostly controlled by the other end */
4392 #define DP_VOLTAGE_0_4 (0 << 25)
4393 #define DP_VOLTAGE_0_6 (1 << 25)
4394 #define DP_VOLTAGE_0_8 (2 << 25)
4395 #define DP_VOLTAGE_1_2 (3 << 25)
4396 #define DP_VOLTAGE_MASK (7 << 25)
4397 #define DP_VOLTAGE_SHIFT 25
4398
4399 /* Signal pre-emphasis levels, like voltages, the other end tells us what
4400 * they want
4401 */
4402 #define DP_PRE_EMPHASIS_0 (0 << 22)
4403 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
4404 #define DP_PRE_EMPHASIS_6 (2 << 22)
4405 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
4406 #define DP_PRE_EMPHASIS_MASK (7 << 22)
4407 #define DP_PRE_EMPHASIS_SHIFT 22
4408
4409 /* How many wires to use. I guess 3 was too hard */
4410 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
4411 #define DP_PORT_WIDTH_MASK (7 << 19)
4412 #define DP_PORT_WIDTH_SHIFT 19
4413
4414 /* Mystic DPCD version 1.1 special mode */
4415 #define DP_ENHANCED_FRAMING (1 << 18)
4416
4417 /* eDP */
4418 #define DP_PLL_FREQ_270MHZ (0 << 16)
4419 #define DP_PLL_FREQ_162MHZ (1 << 16)
4420 #define DP_PLL_FREQ_MASK (3 << 16)
4421
4422 /* locked once port is enabled */
4423 #define DP_PORT_REVERSAL (1 << 15)
4424
4425 /* eDP */
4426 #define DP_PLL_ENABLE (1 << 14)
4427
4428 /* sends the clock on lane 15 of the PEG for debug */
4429 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4430
4431 #define DP_SCRAMBLING_DISABLE (1 << 12)
4432 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
4433
4434 /* limit RGB values to avoid confusing TVs */
4435 #define DP_COLOR_RANGE_16_235 (1 << 8)
4436
4437 /* Turn on the audio link */
4438 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4439
4440 /* vs and hs sync polarity */
4441 #define DP_SYNC_VS_HIGH (1 << 4)
4442 #define DP_SYNC_HS_HIGH (1 << 3)
4443
4444 /* A fantasy */
4445 #define DP_DETECTED (1 << 2)
4446
4447 /* The aux channel provides a way to talk to the
4448 * signal sink for DDC etc. Max packet size supported
4449 * is 20 bytes in each direction, hence the 5 fixed
4450 * data registers
4451 */
4452 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
4453 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
4454 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
4455 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
4456 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
4457 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
4458
4459 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
4460 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
4461 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
4462 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
4463 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
4464 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
4465
4466 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
4467 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
4468 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
4469 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
4470 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
4471 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
4472
4473 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
4474 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
4475 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
4476 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
4477 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
4478 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
4479
4480 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
4481 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
4482
4483 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4484 #define DP_AUX_CH_CTL_DONE (1 << 30)
4485 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4486 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4487 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4488 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4489 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4490 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4491 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4492 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4493 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4494 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4495 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4496 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4497 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4498 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4499 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4500 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4501 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4502 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4503 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
4504 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4505 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4506 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
4507 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
4508 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
4509 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
4510
4511 /*
4512 * Computing GMCH M and N values for the Display Port link
4513 *
4514 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4515 *
4516 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4517 *
4518 * The GMCH value is used internally
4519 *
4520 * bytes_per_pixel is the number of bytes coming out of the plane,
4521 * which is after the LUTs, so we want the bytes for our color format.
4522 * For our current usage, this is always 3, one byte for R, G and B.
4523 */
4524 #define _PIPEA_DATA_M_G4X 0x70050
4525 #define _PIPEB_DATA_M_G4X 0x71050
4526
4527 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
4528 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
4529 #define TU_SIZE_SHIFT 25
4530 #define TU_SIZE_MASK (0x3f << 25)
4531
4532 #define DATA_LINK_M_N_MASK (0xffffff)
4533 #define DATA_LINK_N_MAX (0x800000)
4534
4535 #define _PIPEA_DATA_N_G4X 0x70054
4536 #define _PIPEB_DATA_N_G4X 0x71054
4537 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
4538
4539 /*
4540 * Computing Link M and N values for the Display Port link
4541 *
4542 * Link M / N = pixel_clock / ls_clk
4543 *
4544 * (the DP spec calls pixel_clock the 'strm_clk')
4545 *
4546 * The Link value is transmitted in the Main Stream
4547 * Attributes and VB-ID.
4548 */
4549
4550 #define _PIPEA_LINK_M_G4X 0x70060
4551 #define _PIPEB_LINK_M_G4X 0x71060
4552 #define PIPEA_DP_LINK_M_MASK (0xffffff)
4553
4554 #define _PIPEA_LINK_N_G4X 0x70064
4555 #define _PIPEB_LINK_N_G4X 0x71064
4556 #define PIPEA_DP_LINK_N_MASK (0xffffff)
4557
4558 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4559 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4560 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4561 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4562
4563 /* Display & cursor control */
4564
4565 /* Pipe A */
4566 #define _PIPEADSL 0x70000
4567 #define DSL_LINEMASK_GEN2 0x00000fff
4568 #define DSL_LINEMASK_GEN3 0x00001fff
4569 #define _PIPEACONF 0x70008
4570 #define PIPECONF_ENABLE (1<<31)
4571 #define PIPECONF_DISABLE 0
4572 #define PIPECONF_DOUBLE_WIDE (1<<30)
4573 #define I965_PIPECONF_ACTIVE (1<<30)
4574 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
4575 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
4576 #define PIPECONF_SINGLE_WIDE 0
4577 #define PIPECONF_PIPE_UNLOCKED 0
4578 #define PIPECONF_PIPE_LOCKED (1<<25)
4579 #define PIPECONF_PALETTE 0
4580 #define PIPECONF_GAMMA (1<<24)
4581 #define PIPECONF_FORCE_BORDER (1<<25)
4582 #define PIPECONF_INTERLACE_MASK (7 << 21)
4583 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
4584 /* Note that pre-gen3 does not support interlaced display directly. Panel
4585 * fitting must be disabled on pre-ilk for interlaced. */
4586 #define PIPECONF_PROGRESSIVE (0 << 21)
4587 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4588 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4589 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4590 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4591 /* Ironlake and later have a complete new set of values for interlaced. PFIT
4592 * means panel fitter required, PF means progressive fetch, DBL means power
4593 * saving pixel doubling. */
4594 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4595 #define PIPECONF_INTERLACED_ILK (3 << 21)
4596 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4597 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
4598 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
4599 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
4600 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
4601 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
4602 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
4603 #define PIPECONF_BPC_MASK (0x7 << 5)
4604 #define PIPECONF_8BPC (0<<5)
4605 #define PIPECONF_10BPC (1<<5)
4606 #define PIPECONF_6BPC (2<<5)
4607 #define PIPECONF_12BPC (3<<5)
4608 #define PIPECONF_DITHER_EN (1<<4)
4609 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4610 #define PIPECONF_DITHER_TYPE_SP (0<<2)
4611 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4612 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4613 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
4614 #define _PIPEASTAT 0x70024
4615 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
4616 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
4617 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4618 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
4619 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
4620 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
4621 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
4622 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4623 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4624 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4625 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
4626 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
4627 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4628 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4629 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
4630 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
4631 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
4632 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4633 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
4634 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
4635 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
4636 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
4637 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
4638 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4639 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
4640 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4641 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
4642 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
4643 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
4644 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
4645 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4646 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4647 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4648 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
4649 #define PIPE_A_PSR_STATUS_VLV (1UL<<6)
4650 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
4651 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4652 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
4653 #define PIPE_B_PSR_STATUS_VLV (1UL<<3)
4654 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
4655 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4656 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
4657 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
4658 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
4659 #define PIPE_HBLANK_INT_STATUS (1UL<<0)
4660 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4661
4662 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4663 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4664
4665 #define PIPE_A_OFFSET 0x70000
4666 #define PIPE_B_OFFSET 0x71000
4667 #define PIPE_C_OFFSET 0x72000
4668 #define CHV_PIPE_C_OFFSET 0x74000
4669 /*
4670 * There's actually no pipe EDP. Some pipe registers have
4671 * simply shifted from the pipe to the transcoder, while
4672 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4673 * to access such registers in transcoder EDP.
4674 */
4675 #define PIPE_EDP_OFFSET 0x7f000
4676
4677 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
4678 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4679 dev_priv->info.display_mmio_offset)
4680
4681 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
4682 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
4683 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
4684 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
4685 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
4686
4687 #define _PIPE_MISC_A 0x70030
4688 #define _PIPE_MISC_B 0x71030
4689 #define PIPEMISC_DITHER_BPC_MASK (7<<5)
4690 #define PIPEMISC_DITHER_8_BPC (0<<5)
4691 #define PIPEMISC_DITHER_10_BPC (1<<5)
4692 #define PIPEMISC_DITHER_6_BPC (2<<5)
4693 #define PIPEMISC_DITHER_12_BPC (3<<5)
4694 #define PIPEMISC_DITHER_ENABLE (1<<4)
4695 #define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4696 #define PIPEMISC_DITHER_TYPE_SP (0<<2)
4697 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
4698
4699 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
4700 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
4701 #define PIPEB_HLINE_INT_EN (1<<28)
4702 #define PIPEB_VBLANK_INT_EN (1<<27)
4703 #define SPRITED_FLIP_DONE_INT_EN (1<<26)
4704 #define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4705 #define PLANEB_FLIP_DONE_INT_EN (1<<24)
4706 #define PIPE_PSR_INT_EN (1<<22)
4707 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
4708 #define PIPEA_HLINE_INT_EN (1<<20)
4709 #define PIPEA_VBLANK_INT_EN (1<<19)
4710 #define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4711 #define SPRITEA_FLIP_DONE_INT_EN (1<<17)
4712 #define PLANEA_FLIPDONE_INT_EN (1<<16)
4713 #define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4714 #define PIPEC_HLINE_INT_EN (1<<12)
4715 #define PIPEC_VBLANK_INT_EN (1<<11)
4716 #define SPRITEF_FLIPDONE_INT_EN (1<<10)
4717 #define SPRITEE_FLIPDONE_INT_EN (1<<9)
4718 #define PLANEC_FLIPDONE_INT_EN (1<<8)
4719
4720 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4721 #define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4722 #define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4723 #define PLANEC_INVALID_GTT_INT_EN (1<<25)
4724 #define CURSORC_INVALID_GTT_INT_EN (1<<24)
4725 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
4726 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
4727 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
4728 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4729 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
4730 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4731 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4732 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
4733 #define DPINVGTT_EN_MASK 0xff0000
4734 #define DPINVGTT_EN_MASK_CHV 0xfff0000
4735 #define SPRITEF_INVALID_GTT_STATUS (1<<11)
4736 #define SPRITEE_INVALID_GTT_STATUS (1<<10)
4737 #define PLANEC_INVALID_GTT_STATUS (1<<9)
4738 #define CURSORC_INVALID_GTT_STATUS (1<<8)
4739 #define CURSORB_INVALID_GTT_STATUS (1<<7)
4740 #define CURSORA_INVALID_GTT_STATUS (1<<6)
4741 #define SPRITED_INVALID_GTT_STATUS (1<<5)
4742 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
4743 #define PLANEB_INVALID_GTT_STATUS (1<<3)
4744 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
4745 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
4746 #define PLANEA_INVALID_GTT_STATUS (1<<0)
4747 #define DPINVGTT_STATUS_MASK 0xff
4748 #define DPINVGTT_STATUS_MASK_CHV 0xfff
4749
4750 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
4751 #define DSPARB_CSTART_MASK (0x7f << 7)
4752 #define DSPARB_CSTART_SHIFT 7
4753 #define DSPARB_BSTART_MASK (0x7f)
4754 #define DSPARB_BSTART_SHIFT 0
4755 #define DSPARB_BEND_SHIFT 9 /* on 855 */
4756 #define DSPARB_AEND_SHIFT 0
4757 #define DSPARB_SPRITEA_SHIFT_VLV 0
4758 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4759 #define DSPARB_SPRITEB_SHIFT_VLV 8
4760 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4761 #define DSPARB_SPRITEC_SHIFT_VLV 16
4762 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4763 #define DSPARB_SPRITED_SHIFT_VLV 24
4764 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
4765 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4766 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4767 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4768 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4769 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4770 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4771 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4772 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
4773 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4774 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4775 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4776 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4777 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
4778 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
4779 #define DSPARB_SPRITEE_SHIFT_VLV 0
4780 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4781 #define DSPARB_SPRITEF_SHIFT_VLV 8
4782 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
4783
4784 /* pnv/gen4/g4x/vlv/chv */
4785 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
4786 #define DSPFW_SR_SHIFT 23
4787 #define DSPFW_SR_MASK (0x1ff<<23)
4788 #define DSPFW_CURSORB_SHIFT 16
4789 #define DSPFW_CURSORB_MASK (0x3f<<16)
4790 #define DSPFW_PLANEB_SHIFT 8
4791 #define DSPFW_PLANEB_MASK (0x7f<<8)
4792 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4793 #define DSPFW_PLANEA_SHIFT 0
4794 #define DSPFW_PLANEA_MASK (0x7f<<0)
4795 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4796 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
4797 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4798 #define DSPFW_FBC_SR_SHIFT 28
4799 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4800 #define DSPFW_FBC_HPLL_SR_SHIFT 24
4801 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4802 #define DSPFW_SPRITEB_SHIFT (16)
4803 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4804 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4805 #define DSPFW_CURSORA_SHIFT 8
4806 #define DSPFW_CURSORA_MASK (0x3f<<8)
4807 #define DSPFW_PLANEC_OLD_SHIFT 0
4808 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
4809 #define DSPFW_SPRITEA_SHIFT 0
4810 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4811 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4812 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
4813 #define DSPFW_HPLL_SR_EN (1<<31)
4814 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
4815 #define DSPFW_CURSOR_SR_SHIFT 24
4816 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4817 #define DSPFW_HPLL_CURSOR_SHIFT 16
4818 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
4819 #define DSPFW_HPLL_SR_SHIFT 0
4820 #define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4821
4822 /* vlv/chv */
4823 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
4824 #define DSPFW_SPRITEB_WM1_SHIFT 16
4825 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4826 #define DSPFW_CURSORA_WM1_SHIFT 8
4827 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4828 #define DSPFW_SPRITEA_WM1_SHIFT 0
4829 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4830 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
4831 #define DSPFW_PLANEB_WM1_SHIFT 24
4832 #define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4833 #define DSPFW_PLANEA_WM1_SHIFT 16
4834 #define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4835 #define DSPFW_CURSORB_WM1_SHIFT 8
4836 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4837 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
4838 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4839 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
4840 #define DSPFW_SR_WM1_SHIFT 0
4841 #define DSPFW_SR_WM1_MASK (0x1ff<<0)
4842 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
4843 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4844 #define DSPFW_SPRITED_WM1_SHIFT 24
4845 #define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4846 #define DSPFW_SPRITED_SHIFT 16
4847 #define DSPFW_SPRITED_MASK_VLV (0xff<<16)
4848 #define DSPFW_SPRITEC_WM1_SHIFT 8
4849 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4850 #define DSPFW_SPRITEC_SHIFT 0
4851 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
4852 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
4853 #define DSPFW_SPRITEF_WM1_SHIFT 24
4854 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4855 #define DSPFW_SPRITEF_SHIFT 16
4856 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
4857 #define DSPFW_SPRITEE_WM1_SHIFT 8
4858 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4859 #define DSPFW_SPRITEE_SHIFT 0
4860 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
4861 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4862 #define DSPFW_PLANEC_WM1_SHIFT 24
4863 #define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4864 #define DSPFW_PLANEC_SHIFT 16
4865 #define DSPFW_PLANEC_MASK_VLV (0xff<<16)
4866 #define DSPFW_CURSORC_WM1_SHIFT 8
4867 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4868 #define DSPFW_CURSORC_SHIFT 0
4869 #define DSPFW_CURSORC_MASK (0x3f<<0)
4870
4871 /* vlv/chv high order bits */
4872 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
4873 #define DSPFW_SR_HI_SHIFT 24
4874 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4875 #define DSPFW_SPRITEF_HI_SHIFT 23
4876 #define DSPFW_SPRITEF_HI_MASK (1<<23)
4877 #define DSPFW_SPRITEE_HI_SHIFT 22
4878 #define DSPFW_SPRITEE_HI_MASK (1<<22)
4879 #define DSPFW_PLANEC_HI_SHIFT 21
4880 #define DSPFW_PLANEC_HI_MASK (1<<21)
4881 #define DSPFW_SPRITED_HI_SHIFT 20
4882 #define DSPFW_SPRITED_HI_MASK (1<<20)
4883 #define DSPFW_SPRITEC_HI_SHIFT 16
4884 #define DSPFW_SPRITEC_HI_MASK (1<<16)
4885 #define DSPFW_PLANEB_HI_SHIFT 12
4886 #define DSPFW_PLANEB_HI_MASK (1<<12)
4887 #define DSPFW_SPRITEB_HI_SHIFT 8
4888 #define DSPFW_SPRITEB_HI_MASK (1<<8)
4889 #define DSPFW_SPRITEA_HI_SHIFT 4
4890 #define DSPFW_SPRITEA_HI_MASK (1<<4)
4891 #define DSPFW_PLANEA_HI_SHIFT 0
4892 #define DSPFW_PLANEA_HI_MASK (1<<0)
4893 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
4894 #define DSPFW_SR_WM1_HI_SHIFT 24
4895 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4896 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4897 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4898 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4899 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4900 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
4901 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4902 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
4903 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4904 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4905 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4906 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
4907 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4908 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4909 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4910 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4911 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4912 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
4913 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4914
4915 /* drain latency register values*/
4916 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4917 #define DDL_CURSOR_SHIFT 24
4918 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4919 #define DDL_PLANE_SHIFT 0
4920 #define DDL_PRECISION_HIGH (1<<7)
4921 #define DDL_PRECISION_LOW (0<<7)
4922 #define DRAIN_LATENCY_MASK 0x7f
4923
4924 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
4925 #define CBR_PND_DEADLINE_DISABLE (1<<31)
4926 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
4927
4928 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
4929 #define CBR_DPLLBMD_PIPE_C (1<<29)
4930 #define CBR_DPLLBMD_PIPE_B (1<<18)
4931
4932 /* FIFO watermark sizes etc */
4933 #define G4X_FIFO_LINE_SIZE 64
4934 #define I915_FIFO_LINE_SIZE 64
4935 #define I830_FIFO_LINE_SIZE 32
4936
4937 #define VALLEYVIEW_FIFO_SIZE 255
4938 #define G4X_FIFO_SIZE 127
4939 #define I965_FIFO_SIZE 512
4940 #define I945_FIFO_SIZE 127
4941 #define I915_FIFO_SIZE 95
4942 #define I855GM_FIFO_SIZE 127 /* In cachelines */
4943 #define I830_FIFO_SIZE 95
4944
4945 #define VALLEYVIEW_MAX_WM 0xff
4946 #define G4X_MAX_WM 0x3f
4947 #define I915_MAX_WM 0x3f
4948
4949 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4950 #define PINEVIEW_FIFO_LINE_SIZE 64
4951 #define PINEVIEW_MAX_WM 0x1ff
4952 #define PINEVIEW_DFT_WM 0x3f
4953 #define PINEVIEW_DFT_HPLLOFF_WM 0
4954 #define PINEVIEW_GUARD_WM 10
4955 #define PINEVIEW_CURSOR_FIFO 64
4956 #define PINEVIEW_CURSOR_MAX_WM 0x3f
4957 #define PINEVIEW_CURSOR_DFT_WM 0
4958 #define PINEVIEW_CURSOR_GUARD_WM 5
4959
4960 #define VALLEYVIEW_CURSOR_MAX_WM 64
4961 #define I965_CURSOR_FIFO 64
4962 #define I965_CURSOR_MAX_WM 32
4963 #define I965_CURSOR_DFT_WM 8
4964
4965 /* Watermark register definitions for SKL */
4966 #define _CUR_WM_A_0 0x70140
4967 #define _CUR_WM_B_0 0x71140
4968 #define _PLANE_WM_1_A_0 0x70240
4969 #define _PLANE_WM_1_B_0 0x71240
4970 #define _PLANE_WM_2_A_0 0x70340
4971 #define _PLANE_WM_2_B_0 0x71340
4972 #define _PLANE_WM_TRANS_1_A_0 0x70268
4973 #define _PLANE_WM_TRANS_1_B_0 0x71268
4974 #define _PLANE_WM_TRANS_2_A_0 0x70368
4975 #define _PLANE_WM_TRANS_2_B_0 0x71368
4976 #define _CUR_WM_TRANS_A_0 0x70168
4977 #define _CUR_WM_TRANS_B_0 0x71168
4978 #define PLANE_WM_EN (1 << 31)
4979 #define PLANE_WM_LINES_SHIFT 14
4980 #define PLANE_WM_LINES_MASK 0x1f
4981 #define PLANE_WM_BLOCKS_MASK 0x3ff
4982
4983 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
4984 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4985 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
4986
4987 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4988 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
4989 #define _PLANE_WM_BASE(pipe, plane) \
4990 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4991 #define PLANE_WM(pipe, plane, level) \
4992 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4993 #define _PLANE_WM_TRANS_1(pipe) \
4994 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
4995 #define _PLANE_WM_TRANS_2(pipe) \
4996 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
4997 #define PLANE_WM_TRANS(pipe, plane) \
4998 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
4999
5000 /* define the Watermark register on Ironlake */
5001 #define WM0_PIPEA_ILK _MMIO(0x45100)
5002 #define WM0_PIPE_PLANE_MASK (0xffff<<16)
5003 #define WM0_PIPE_PLANE_SHIFT 16
5004 #define WM0_PIPE_SPRITE_MASK (0xff<<8)
5005 #define WM0_PIPE_SPRITE_SHIFT 8
5006 #define WM0_PIPE_CURSOR_MASK (0xff)
5007
5008 #define WM0_PIPEB_ILK _MMIO(0x45104)
5009 #define WM0_PIPEC_IVB _MMIO(0x45200)
5010 #define WM1_LP_ILK _MMIO(0x45108)
5011 #define WM1_LP_SR_EN (1<<31)
5012 #define WM1_LP_LATENCY_SHIFT 24
5013 #define WM1_LP_LATENCY_MASK (0x7f<<24)
5014 #define WM1_LP_FBC_MASK (0xf<<20)
5015 #define WM1_LP_FBC_SHIFT 20
5016 #define WM1_LP_FBC_SHIFT_BDW 19
5017 #define WM1_LP_SR_MASK (0x7ff<<8)
5018 #define WM1_LP_SR_SHIFT 8
5019 #define WM1_LP_CURSOR_MASK (0xff)
5020 #define WM2_LP_ILK _MMIO(0x4510c)
5021 #define WM2_LP_EN (1<<31)
5022 #define WM3_LP_ILK _MMIO(0x45110)
5023 #define WM3_LP_EN (1<<31)
5024 #define WM1S_LP_ILK _MMIO(0x45120)
5025 #define WM2S_LP_IVB _MMIO(0x45124)
5026 #define WM3S_LP_IVB _MMIO(0x45128)
5027 #define WM1S_LP_EN (1<<31)
5028
5029 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5030 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5031 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5032
5033 /* Memory latency timer register */
5034 #define MLTR_ILK _MMIO(0x11222)
5035 #define MLTR_WM1_SHIFT 0
5036 #define MLTR_WM2_SHIFT 8
5037 /* the unit of memory self-refresh latency time is 0.5us */
5038 #define ILK_SRLT_MASK 0x3f
5039
5040
5041 /* the address where we get all kinds of latency value */
5042 #define SSKPD _MMIO(0x5d10)
5043 #define SSKPD_WM_MASK 0x3f
5044 #define SSKPD_WM0_SHIFT 0
5045 #define SSKPD_WM1_SHIFT 8
5046 #define SSKPD_WM2_SHIFT 16
5047 #define SSKPD_WM3_SHIFT 24
5048
5049 /*
5050 * The two pipe frame counter registers are not synchronized, so
5051 * reading a stable value is somewhat tricky. The following code
5052 * should work:
5053 *
5054 * do {
5055 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5056 * PIPE_FRAME_HIGH_SHIFT;
5057 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
5058 * PIPE_FRAME_LOW_SHIFT);
5059 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5060 * PIPE_FRAME_HIGH_SHIFT);
5061 * } while (high1 != high2);
5062 * frame = (high1 << 8) | low1;
5063 */
5064 #define _PIPEAFRAMEHIGH 0x70040
5065 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
5066 #define PIPE_FRAME_HIGH_SHIFT 0
5067 #define _PIPEAFRAMEPIXEL 0x70044
5068 #define PIPE_FRAME_LOW_MASK 0xff000000
5069 #define PIPE_FRAME_LOW_SHIFT 24
5070 #define PIPE_PIXEL_MASK 0x00ffffff
5071 #define PIPE_PIXEL_SHIFT 0
5072 /* GM45+ just has to be different */
5073 #define _PIPEA_FRMCOUNT_G4X 0x70040
5074 #define _PIPEA_FLIPCOUNT_G4X 0x70044
5075 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5076 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
5077
5078 /* Cursor A & B regs */
5079 #define _CURACNTR 0x70080
5080 /* Old style CUR*CNTR flags (desktop 8xx) */
5081 #define CURSOR_ENABLE 0x80000000
5082 #define CURSOR_GAMMA_ENABLE 0x40000000
5083 #define CURSOR_STRIDE_SHIFT 28
5084 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
5085 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
5086 #define CURSOR_FORMAT_SHIFT 24
5087 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5088 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5089 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5090 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5091 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5092 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5093 /* New style CUR*CNTR flags */
5094 #define CURSOR_MODE 0x27
5095 #define CURSOR_MODE_DISABLE 0x00
5096 #define CURSOR_MODE_128_32B_AX 0x02
5097 #define CURSOR_MODE_256_32B_AX 0x03
5098 #define CURSOR_MODE_64_32B_AX 0x07
5099 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5100 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
5101 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
5102 #define MCURSOR_PIPE_SELECT (1 << 28)
5103 #define MCURSOR_PIPE_A 0x00
5104 #define MCURSOR_PIPE_B (1 << 28)
5105 #define MCURSOR_GAMMA_ENABLE (1 << 26)
5106 #define CURSOR_ROTATE_180 (1<<15)
5107 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
5108 #define _CURABASE 0x70084
5109 #define _CURAPOS 0x70088
5110 #define CURSOR_POS_MASK 0x007FF
5111 #define CURSOR_POS_SIGN 0x8000
5112 #define CURSOR_X_SHIFT 0
5113 #define CURSOR_Y_SHIFT 16
5114 #define CURSIZE _MMIO(0x700a0)
5115 #define _CURBCNTR 0x700c0
5116 #define _CURBBASE 0x700c4
5117 #define _CURBPOS 0x700c8
5118
5119 #define _CURBCNTR_IVB 0x71080
5120 #define _CURBBASE_IVB 0x71084
5121 #define _CURBPOS_IVB 0x71088
5122
5123 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
5124 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
5125 dev_priv->info.display_mmio_offset)
5126
5127 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
5128 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
5129 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
5130
5131 #define CURSOR_A_OFFSET 0x70080
5132 #define CURSOR_B_OFFSET 0x700c0
5133 #define CHV_CURSOR_C_OFFSET 0x700e0
5134 #define IVB_CURSOR_B_OFFSET 0x71080
5135 #define IVB_CURSOR_C_OFFSET 0x72080
5136
5137 /* Display A control */
5138 #define _DSPACNTR 0x70180
5139 #define DISPLAY_PLANE_ENABLE (1<<31)
5140 #define DISPLAY_PLANE_DISABLE 0
5141 #define DISPPLANE_GAMMA_ENABLE (1<<30)
5142 #define DISPPLANE_GAMMA_DISABLE 0
5143 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
5144 #define DISPPLANE_YUV422 (0x0<<26)
5145 #define DISPPLANE_8BPP (0x2<<26)
5146 #define DISPPLANE_BGRA555 (0x3<<26)
5147 #define DISPPLANE_BGRX555 (0x4<<26)
5148 #define DISPPLANE_BGRX565 (0x5<<26)
5149 #define DISPPLANE_BGRX888 (0x6<<26)
5150 #define DISPPLANE_BGRA888 (0x7<<26)
5151 #define DISPPLANE_RGBX101010 (0x8<<26)
5152 #define DISPPLANE_RGBA101010 (0x9<<26)
5153 #define DISPPLANE_BGRX101010 (0xa<<26)
5154 #define DISPPLANE_RGBX161616 (0xc<<26)
5155 #define DISPPLANE_RGBX888 (0xe<<26)
5156 #define DISPPLANE_RGBA888 (0xf<<26)
5157 #define DISPPLANE_STEREO_ENABLE (1<<25)
5158 #define DISPPLANE_STEREO_DISABLE 0
5159 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
5160 #define DISPPLANE_SEL_PIPE_SHIFT 24
5161 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
5162 #define DISPPLANE_SEL_PIPE_A 0
5163 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
5164 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
5165 #define DISPPLANE_SRC_KEY_DISABLE 0
5166 #define DISPPLANE_LINE_DOUBLE (1<<20)
5167 #define DISPPLANE_NO_LINE_DOUBLE 0
5168 #define DISPPLANE_STEREO_POLARITY_FIRST 0
5169 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
5170 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
5171 #define DISPPLANE_ROTATE_180 (1<<15)
5172 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
5173 #define DISPPLANE_TILED (1<<10)
5174 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
5175 #define _DSPAADDR 0x70184
5176 #define _DSPASTRIDE 0x70188
5177 #define _DSPAPOS 0x7018C /* reserved */
5178 #define _DSPASIZE 0x70190
5179 #define _DSPASURF 0x7019C /* 965+ only */
5180 #define _DSPATILEOFF 0x701A4 /* 965+ only */
5181 #define _DSPAOFFSET 0x701A4 /* HSW */
5182 #define _DSPASURFLIVE 0x701AC
5183
5184 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
5185 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
5186 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
5187 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
5188 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
5189 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
5190 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
5191 #define DSPLINOFF(plane) DSPADDR(plane)
5192 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
5193 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
5194
5195 /* CHV pipe B blender and primary plane */
5196 #define _CHV_BLEND_A 0x60a00
5197 #define CHV_BLEND_LEGACY (0<<30)
5198 #define CHV_BLEND_ANDROID (1<<30)
5199 #define CHV_BLEND_MPO (2<<30)
5200 #define CHV_BLEND_MASK (3<<30)
5201 #define _CHV_CANVAS_A 0x60a04
5202 #define _PRIMPOS_A 0x60a08
5203 #define _PRIMSIZE_A 0x60a0c
5204 #define _PRIMCNSTALPHA_A 0x60a10
5205 #define PRIM_CONST_ALPHA_ENABLE (1<<31)
5206
5207 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
5208 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
5209 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
5210 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
5211 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
5212
5213 /* Display/Sprite base address macros */
5214 #define DISP_BASEADDR_MASK (0xfffff000)
5215 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
5216 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
5217
5218 /*
5219 * VBIOS flags
5220 * gen2:
5221 * [00:06] alm,mgm
5222 * [10:16] all
5223 * [30:32] alm,mgm
5224 * gen3+:
5225 * [00:0f] all
5226 * [10:1f] all
5227 * [30:32] all
5228 */
5229 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5230 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5231 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5232 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
5233
5234 /* Pipe B */
5235 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
5236 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
5237 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
5238 #define _PIPEBFRAMEHIGH 0x71040
5239 #define _PIPEBFRAMEPIXEL 0x71044
5240 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
5241 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
5242
5243
5244 /* Display B control */
5245 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
5246 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
5247 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
5248 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
5249 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
5250 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
5251 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
5252 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
5253 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
5254 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
5255 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
5256 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
5257 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
5258
5259 /* Sprite A control */
5260 #define _DVSACNTR 0x72180
5261 #define DVS_ENABLE (1<<31)
5262 #define DVS_GAMMA_ENABLE (1<<30)
5263 #define DVS_PIXFORMAT_MASK (3<<25)
5264 #define DVS_FORMAT_YUV422 (0<<25)
5265 #define DVS_FORMAT_RGBX101010 (1<<25)
5266 #define DVS_FORMAT_RGBX888 (2<<25)
5267 #define DVS_FORMAT_RGBX161616 (3<<25)
5268 #define DVS_PIPE_CSC_ENABLE (1<<24)
5269 #define DVS_SOURCE_KEY (1<<22)
5270 #define DVS_RGB_ORDER_XBGR (1<<20)
5271 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
5272 #define DVS_YUV_ORDER_YUYV (0<<16)
5273 #define DVS_YUV_ORDER_UYVY (1<<16)
5274 #define DVS_YUV_ORDER_YVYU (2<<16)
5275 #define DVS_YUV_ORDER_VYUY (3<<16)
5276 #define DVS_ROTATE_180 (1<<15)
5277 #define DVS_DEST_KEY (1<<2)
5278 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
5279 #define DVS_TILED (1<<10)
5280 #define _DVSALINOFF 0x72184
5281 #define _DVSASTRIDE 0x72188
5282 #define _DVSAPOS 0x7218c
5283 #define _DVSASIZE 0x72190
5284 #define _DVSAKEYVAL 0x72194
5285 #define _DVSAKEYMSK 0x72198
5286 #define _DVSASURF 0x7219c
5287 #define _DVSAKEYMAXVAL 0x721a0
5288 #define _DVSATILEOFF 0x721a4
5289 #define _DVSASURFLIVE 0x721ac
5290 #define _DVSASCALE 0x72204
5291 #define DVS_SCALE_ENABLE (1<<31)
5292 #define DVS_FILTER_MASK (3<<29)
5293 #define DVS_FILTER_MEDIUM (0<<29)
5294 #define DVS_FILTER_ENHANCING (1<<29)
5295 #define DVS_FILTER_SOFTENING (2<<29)
5296 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5297 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5298 #define _DVSAGAMC 0x72300
5299
5300 #define _DVSBCNTR 0x73180
5301 #define _DVSBLINOFF 0x73184
5302 #define _DVSBSTRIDE 0x73188
5303 #define _DVSBPOS 0x7318c
5304 #define _DVSBSIZE 0x73190
5305 #define _DVSBKEYVAL 0x73194
5306 #define _DVSBKEYMSK 0x73198
5307 #define _DVSBSURF 0x7319c
5308 #define _DVSBKEYMAXVAL 0x731a0
5309 #define _DVSBTILEOFF 0x731a4
5310 #define _DVSBSURFLIVE 0x731ac
5311 #define _DVSBSCALE 0x73204
5312 #define _DVSBGAMC 0x73300
5313
5314 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5315 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5316 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5317 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
5318 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
5319 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5320 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5321 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5322 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5323 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5324 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5325 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5326
5327 #define _SPRA_CTL 0x70280
5328 #define SPRITE_ENABLE (1<<31)
5329 #define SPRITE_GAMMA_ENABLE (1<<30)
5330 #define SPRITE_PIXFORMAT_MASK (7<<25)
5331 #define SPRITE_FORMAT_YUV422 (0<<25)
5332 #define SPRITE_FORMAT_RGBX101010 (1<<25)
5333 #define SPRITE_FORMAT_RGBX888 (2<<25)
5334 #define SPRITE_FORMAT_RGBX161616 (3<<25)
5335 #define SPRITE_FORMAT_YUV444 (4<<25)
5336 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
5337 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
5338 #define SPRITE_SOURCE_KEY (1<<22)
5339 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5340 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5341 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5342 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5343 #define SPRITE_YUV_ORDER_YUYV (0<<16)
5344 #define SPRITE_YUV_ORDER_UYVY (1<<16)
5345 #define SPRITE_YUV_ORDER_YVYU (2<<16)
5346 #define SPRITE_YUV_ORDER_VYUY (3<<16)
5347 #define SPRITE_ROTATE_180 (1<<15)
5348 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5349 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
5350 #define SPRITE_TILED (1<<10)
5351 #define SPRITE_DEST_KEY (1<<2)
5352 #define _SPRA_LINOFF 0x70284
5353 #define _SPRA_STRIDE 0x70288
5354 #define _SPRA_POS 0x7028c
5355 #define _SPRA_SIZE 0x70290
5356 #define _SPRA_KEYVAL 0x70294
5357 #define _SPRA_KEYMSK 0x70298
5358 #define _SPRA_SURF 0x7029c
5359 #define _SPRA_KEYMAX 0x702a0
5360 #define _SPRA_TILEOFF 0x702a4
5361 #define _SPRA_OFFSET 0x702a4
5362 #define _SPRA_SURFLIVE 0x702ac
5363 #define _SPRA_SCALE 0x70304
5364 #define SPRITE_SCALE_ENABLE (1<<31)
5365 #define SPRITE_FILTER_MASK (3<<29)
5366 #define SPRITE_FILTER_MEDIUM (0<<29)
5367 #define SPRITE_FILTER_ENHANCING (1<<29)
5368 #define SPRITE_FILTER_SOFTENING (2<<29)
5369 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5370 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5371 #define _SPRA_GAMC 0x70400
5372
5373 #define _SPRB_CTL 0x71280
5374 #define _SPRB_LINOFF 0x71284
5375 #define _SPRB_STRIDE 0x71288
5376 #define _SPRB_POS 0x7128c
5377 #define _SPRB_SIZE 0x71290
5378 #define _SPRB_KEYVAL 0x71294
5379 #define _SPRB_KEYMSK 0x71298
5380 #define _SPRB_SURF 0x7129c
5381 #define _SPRB_KEYMAX 0x712a0
5382 #define _SPRB_TILEOFF 0x712a4
5383 #define _SPRB_OFFSET 0x712a4
5384 #define _SPRB_SURFLIVE 0x712ac
5385 #define _SPRB_SCALE 0x71304
5386 #define _SPRB_GAMC 0x71400
5387
5388 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5389 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5390 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5391 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
5392 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5393 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5394 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5395 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5396 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5397 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5398 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5399 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5400 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5401 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5402
5403 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5404 #define SP_ENABLE (1<<31)
5405 #define SP_GAMMA_ENABLE (1<<30)
5406 #define SP_PIXFORMAT_MASK (0xf<<26)
5407 #define SP_FORMAT_YUV422 (0<<26)
5408 #define SP_FORMAT_BGR565 (5<<26)
5409 #define SP_FORMAT_BGRX8888 (6<<26)
5410 #define SP_FORMAT_BGRA8888 (7<<26)
5411 #define SP_FORMAT_RGBX1010102 (8<<26)
5412 #define SP_FORMAT_RGBA1010102 (9<<26)
5413 #define SP_FORMAT_RGBX8888 (0xe<<26)
5414 #define SP_FORMAT_RGBA8888 (0xf<<26)
5415 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
5416 #define SP_SOURCE_KEY (1<<22)
5417 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
5418 #define SP_YUV_ORDER_YUYV (0<<16)
5419 #define SP_YUV_ORDER_UYVY (1<<16)
5420 #define SP_YUV_ORDER_YVYU (2<<16)
5421 #define SP_YUV_ORDER_VYUY (3<<16)
5422 #define SP_ROTATE_180 (1<<15)
5423 #define SP_TILED (1<<10)
5424 #define SP_MIRROR (1<<8) /* CHV pipe B */
5425 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5426 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5427 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5428 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5429 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5430 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5431 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5432 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5433 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5434 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
5435 #define SP_CONST_ALPHA_ENABLE (1<<31)
5436 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
5437
5438 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5439 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5440 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5441 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5442 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5443 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5444 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5445 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5446 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5447 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5448 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5449 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5450
5451 #define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5452 #define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5453 #define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5454 #define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5455 #define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5456 #define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5457 #define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5458 #define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5459 #define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5460 #define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5461 #define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5462 #define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
5463
5464 /*
5465 * CHV pipe B sprite CSC
5466 *
5467 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5468 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5469 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5470 */
5471 #define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5472 #define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5473 #define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5474 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5475 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5476
5477 #define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5478 #define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5479 #define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5480 #define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5481 #define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5482 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5483 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5484
5485 #define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5486 #define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5487 #define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5488 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5489 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5490
5491 #define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5492 #define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5493 #define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5494 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5495 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5496
5497 /* Skylake plane registers */
5498
5499 #define _PLANE_CTL_1_A 0x70180
5500 #define _PLANE_CTL_2_A 0x70280
5501 #define _PLANE_CTL_3_A 0x70380
5502 #define PLANE_CTL_ENABLE (1 << 31)
5503 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5504 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
5505 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5506 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5507 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5508 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5509 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5510 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5511 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5512 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5513 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
5514 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5515 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5516 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
5517 #define PLANE_CTL_ORDER_BGRX (0 << 20)
5518 #define PLANE_CTL_ORDER_RGBX (1 << 20)
5519 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5520 #define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5521 #define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5522 #define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5523 #define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5524 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5525 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5526 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5527 #define PLANE_CTL_TILED_MASK (0x7 << 10)
5528 #define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5529 #define PLANE_CTL_TILED_X ( 1 << 10)
5530 #define PLANE_CTL_TILED_Y ( 4 << 10)
5531 #define PLANE_CTL_TILED_YF ( 5 << 10)
5532 #define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5533 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5534 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5535 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
5536 #define PLANE_CTL_ROTATE_MASK 0x3
5537 #define PLANE_CTL_ROTATE_0 0x0
5538 #define PLANE_CTL_ROTATE_90 0x1
5539 #define PLANE_CTL_ROTATE_180 0x2
5540 #define PLANE_CTL_ROTATE_270 0x3
5541 #define _PLANE_STRIDE_1_A 0x70188
5542 #define _PLANE_STRIDE_2_A 0x70288
5543 #define _PLANE_STRIDE_3_A 0x70388
5544 #define _PLANE_POS_1_A 0x7018c
5545 #define _PLANE_POS_2_A 0x7028c
5546 #define _PLANE_POS_3_A 0x7038c
5547 #define _PLANE_SIZE_1_A 0x70190
5548 #define _PLANE_SIZE_2_A 0x70290
5549 #define _PLANE_SIZE_3_A 0x70390
5550 #define _PLANE_SURF_1_A 0x7019c
5551 #define _PLANE_SURF_2_A 0x7029c
5552 #define _PLANE_SURF_3_A 0x7039c
5553 #define _PLANE_OFFSET_1_A 0x701a4
5554 #define _PLANE_OFFSET_2_A 0x702a4
5555 #define _PLANE_OFFSET_3_A 0x703a4
5556 #define _PLANE_KEYVAL_1_A 0x70194
5557 #define _PLANE_KEYVAL_2_A 0x70294
5558 #define _PLANE_KEYMSK_1_A 0x70198
5559 #define _PLANE_KEYMSK_2_A 0x70298
5560 #define _PLANE_KEYMAX_1_A 0x701a0
5561 #define _PLANE_KEYMAX_2_A 0x702a0
5562 #define _PLANE_BUF_CFG_1_A 0x7027c
5563 #define _PLANE_BUF_CFG_2_A 0x7037c
5564 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
5565 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
5566
5567 #define _PLANE_CTL_1_B 0x71180
5568 #define _PLANE_CTL_2_B 0x71280
5569 #define _PLANE_CTL_3_B 0x71380
5570 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5571 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5572 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5573 #define PLANE_CTL(pipe, plane) \
5574 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5575
5576 #define _PLANE_STRIDE_1_B 0x71188
5577 #define _PLANE_STRIDE_2_B 0x71288
5578 #define _PLANE_STRIDE_3_B 0x71388
5579 #define _PLANE_STRIDE_1(pipe) \
5580 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5581 #define _PLANE_STRIDE_2(pipe) \
5582 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5583 #define _PLANE_STRIDE_3(pipe) \
5584 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5585 #define PLANE_STRIDE(pipe, plane) \
5586 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5587
5588 #define _PLANE_POS_1_B 0x7118c
5589 #define _PLANE_POS_2_B 0x7128c
5590 #define _PLANE_POS_3_B 0x7138c
5591 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5592 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5593 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5594 #define PLANE_POS(pipe, plane) \
5595 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5596
5597 #define _PLANE_SIZE_1_B 0x71190
5598 #define _PLANE_SIZE_2_B 0x71290
5599 #define _PLANE_SIZE_3_B 0x71390
5600 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5601 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5602 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5603 #define PLANE_SIZE(pipe, plane) \
5604 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5605
5606 #define _PLANE_SURF_1_B 0x7119c
5607 #define _PLANE_SURF_2_B 0x7129c
5608 #define _PLANE_SURF_3_B 0x7139c
5609 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5610 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5611 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5612 #define PLANE_SURF(pipe, plane) \
5613 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5614
5615 #define _PLANE_OFFSET_1_B 0x711a4
5616 #define _PLANE_OFFSET_2_B 0x712a4
5617 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5618 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5619 #define PLANE_OFFSET(pipe, plane) \
5620 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5621
5622 #define _PLANE_KEYVAL_1_B 0x71194
5623 #define _PLANE_KEYVAL_2_B 0x71294
5624 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5625 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5626 #define PLANE_KEYVAL(pipe, plane) \
5627 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5628
5629 #define _PLANE_KEYMSK_1_B 0x71198
5630 #define _PLANE_KEYMSK_2_B 0x71298
5631 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5632 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5633 #define PLANE_KEYMSK(pipe, plane) \
5634 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5635
5636 #define _PLANE_KEYMAX_1_B 0x711a0
5637 #define _PLANE_KEYMAX_2_B 0x712a0
5638 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5639 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5640 #define PLANE_KEYMAX(pipe, plane) \
5641 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5642
5643 #define _PLANE_BUF_CFG_1_B 0x7127c
5644 #define _PLANE_BUF_CFG_2_B 0x7137c
5645 #define _PLANE_BUF_CFG_1(pipe) \
5646 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5647 #define _PLANE_BUF_CFG_2(pipe) \
5648 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5649 #define PLANE_BUF_CFG(pipe, plane) \
5650 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5651
5652 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
5653 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
5654 #define _PLANE_NV12_BUF_CFG_1(pipe) \
5655 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5656 #define _PLANE_NV12_BUF_CFG_2(pipe) \
5657 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5658 #define PLANE_NV12_BUF_CFG(pipe, plane) \
5659 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5660
5661 /* SKL new cursor registers */
5662 #define _CUR_BUF_CFG_A 0x7017c
5663 #define _CUR_BUF_CFG_B 0x7117c
5664 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5665
5666 /* VBIOS regs */
5667 #define VGACNTRL _MMIO(0x71400)
5668 # define VGA_DISP_DISABLE (1 << 31)
5669 # define VGA_2X_MODE (1 << 30)
5670 # define VGA_PIPE_B_SELECT (1 << 29)
5671
5672 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
5673
5674 /* Ironlake */
5675
5676 #define CPU_VGACNTRL _MMIO(0x41000)
5677
5678 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
5679 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5680 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5681 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5682 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5683 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5684 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5685 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5686 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5687 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5688 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5689
5690 /* refresh rate hardware control */
5691 #define RR_HW_CTL _MMIO(0x45300)
5692 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5693 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5694
5695 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
5696 #define FDI_PLL_FB_CLOCK_MASK 0xff
5697 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
5698 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
5699 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5700 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5701 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
5702
5703 #define PCH_3DCGDIS0 _MMIO(0x46020)
5704 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5705 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5706
5707 #define PCH_3DCGDIS1 _MMIO(0x46024)
5708 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5709
5710 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
5711 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5712 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5713 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5714
5715
5716 #define _PIPEA_DATA_M1 0x60030
5717 #define PIPE_DATA_M1_OFFSET 0
5718 #define _PIPEA_DATA_N1 0x60034
5719 #define PIPE_DATA_N1_OFFSET 0
5720
5721 #define _PIPEA_DATA_M2 0x60038
5722 #define PIPE_DATA_M2_OFFSET 0
5723 #define _PIPEA_DATA_N2 0x6003c
5724 #define PIPE_DATA_N2_OFFSET 0
5725
5726 #define _PIPEA_LINK_M1 0x60040
5727 #define PIPE_LINK_M1_OFFSET 0
5728 #define _PIPEA_LINK_N1 0x60044
5729 #define PIPE_LINK_N1_OFFSET 0
5730
5731 #define _PIPEA_LINK_M2 0x60048
5732 #define PIPE_LINK_M2_OFFSET 0
5733 #define _PIPEA_LINK_N2 0x6004c
5734 #define PIPE_LINK_N2_OFFSET 0
5735
5736 /* PIPEB timing regs are same start from 0x61000 */
5737
5738 #define _PIPEB_DATA_M1 0x61030
5739 #define _PIPEB_DATA_N1 0x61034
5740 #define _PIPEB_DATA_M2 0x61038
5741 #define _PIPEB_DATA_N2 0x6103c
5742 #define _PIPEB_LINK_M1 0x61040
5743 #define _PIPEB_LINK_N1 0x61044
5744 #define _PIPEB_LINK_M2 0x61048
5745 #define _PIPEB_LINK_N2 0x6104c
5746
5747 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5748 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5749 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5750 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5751 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5752 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5753 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5754 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
5755
5756 /* CPU panel fitter */
5757 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5758 #define _PFA_CTL_1 0x68080
5759 #define _PFB_CTL_1 0x68880
5760 #define PF_ENABLE (1<<31)
5761 #define PF_PIPE_SEL_MASK_IVB (3<<29)
5762 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
5763 #define PF_FILTER_MASK (3<<23)
5764 #define PF_FILTER_PROGRAMMED (0<<23)
5765 #define PF_FILTER_MED_3x3 (1<<23)
5766 #define PF_FILTER_EDGE_ENHANCE (2<<23)
5767 #define PF_FILTER_EDGE_SOFTEN (3<<23)
5768 #define _PFA_WIN_SZ 0x68074
5769 #define _PFB_WIN_SZ 0x68874
5770 #define _PFA_WIN_POS 0x68070
5771 #define _PFB_WIN_POS 0x68870
5772 #define _PFA_VSCALE 0x68084
5773 #define _PFB_VSCALE 0x68884
5774 #define _PFA_HSCALE 0x68090
5775 #define _PFB_HSCALE 0x68890
5776
5777 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5778 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5779 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5780 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5781 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5782
5783 #define _PSA_CTL 0x68180
5784 #define _PSB_CTL 0x68980
5785 #define PS_ENABLE (1<<31)
5786 #define _PSA_WIN_SZ 0x68174
5787 #define _PSB_WIN_SZ 0x68974
5788 #define _PSA_WIN_POS 0x68170
5789 #define _PSB_WIN_POS 0x68970
5790
5791 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5792 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5793 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5794
5795 /*
5796 * Skylake scalers
5797 */
5798 #define _PS_1A_CTRL 0x68180
5799 #define _PS_2A_CTRL 0x68280
5800 #define _PS_1B_CTRL 0x68980
5801 #define _PS_2B_CTRL 0x68A80
5802 #define _PS_1C_CTRL 0x69180
5803 #define PS_SCALER_EN (1 << 31)
5804 #define PS_SCALER_MODE_MASK (3 << 28)
5805 #define PS_SCALER_MODE_DYN (0 << 28)
5806 #define PS_SCALER_MODE_HQ (1 << 28)
5807 #define PS_PLANE_SEL_MASK (7 << 25)
5808 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5809 #define PS_FILTER_MASK (3 << 23)
5810 #define PS_FILTER_MEDIUM (0 << 23)
5811 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
5812 #define PS_FILTER_BILINEAR (3 << 23)
5813 #define PS_VERT3TAP (1 << 21)
5814 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5815 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5816 #define PS_PWRUP_PROGRESS (1 << 17)
5817 #define PS_V_FILTER_BYPASS (1 << 8)
5818 #define PS_VADAPT_EN (1 << 7)
5819 #define PS_VADAPT_MODE_MASK (3 << 5)
5820 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5821 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5822 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5823
5824 #define _PS_PWR_GATE_1A 0x68160
5825 #define _PS_PWR_GATE_2A 0x68260
5826 #define _PS_PWR_GATE_1B 0x68960
5827 #define _PS_PWR_GATE_2B 0x68A60
5828 #define _PS_PWR_GATE_1C 0x69160
5829 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5830 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5831 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5832 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5833 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5834 #define PS_PWR_GATE_SLPEN_8 0
5835 #define PS_PWR_GATE_SLPEN_16 1
5836 #define PS_PWR_GATE_SLPEN_24 2
5837 #define PS_PWR_GATE_SLPEN_32 3
5838
5839 #define _PS_WIN_POS_1A 0x68170
5840 #define _PS_WIN_POS_2A 0x68270
5841 #define _PS_WIN_POS_1B 0x68970
5842 #define _PS_WIN_POS_2B 0x68A70
5843 #define _PS_WIN_POS_1C 0x69170
5844
5845 #define _PS_WIN_SZ_1A 0x68174
5846 #define _PS_WIN_SZ_2A 0x68274
5847 #define _PS_WIN_SZ_1B 0x68974
5848 #define _PS_WIN_SZ_2B 0x68A74
5849 #define _PS_WIN_SZ_1C 0x69174
5850
5851 #define _PS_VSCALE_1A 0x68184
5852 #define _PS_VSCALE_2A 0x68284
5853 #define _PS_VSCALE_1B 0x68984
5854 #define _PS_VSCALE_2B 0x68A84
5855 #define _PS_VSCALE_1C 0x69184
5856
5857 #define _PS_HSCALE_1A 0x68190
5858 #define _PS_HSCALE_2A 0x68290
5859 #define _PS_HSCALE_1B 0x68990
5860 #define _PS_HSCALE_2B 0x68A90
5861 #define _PS_HSCALE_1C 0x69190
5862
5863 #define _PS_VPHASE_1A 0x68188
5864 #define _PS_VPHASE_2A 0x68288
5865 #define _PS_VPHASE_1B 0x68988
5866 #define _PS_VPHASE_2B 0x68A88
5867 #define _PS_VPHASE_1C 0x69188
5868
5869 #define _PS_HPHASE_1A 0x68194
5870 #define _PS_HPHASE_2A 0x68294
5871 #define _PS_HPHASE_1B 0x68994
5872 #define _PS_HPHASE_2B 0x68A94
5873 #define _PS_HPHASE_1C 0x69194
5874
5875 #define _PS_ECC_STAT_1A 0x681D0
5876 #define _PS_ECC_STAT_2A 0x682D0
5877 #define _PS_ECC_STAT_1B 0x689D0
5878 #define _PS_ECC_STAT_2B 0x68AD0
5879 #define _PS_ECC_STAT_1C 0x691D0
5880
5881 #define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5882 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
5883 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5884 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5885 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
5886 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5887 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5888 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
5889 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5890 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5891 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
5892 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5893 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5894 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
5895 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5896 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5897 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
5898 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5899 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5900 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
5901 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5902 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5903 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
5904 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5905 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5906 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
5907 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5908 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
5909
5910 /* legacy palette */
5911 #define _LGC_PALETTE_A 0x4a000
5912 #define _LGC_PALETTE_B 0x4a800
5913 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5914
5915 #define _GAMMA_MODE_A 0x4a480
5916 #define _GAMMA_MODE_B 0x4ac80
5917 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5918 #define GAMMA_MODE_MODE_MASK (3 << 0)
5919 #define GAMMA_MODE_MODE_8BIT (0 << 0)
5920 #define GAMMA_MODE_MODE_10BIT (1 << 0)
5921 #define GAMMA_MODE_MODE_12BIT (2 << 0)
5922 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
5923
5924 /* DMC/CSR */
5925 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
5926 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
5927 #define CSR_HTP_ADDR_SKL 0x00500034
5928 #define CSR_SSP_BASE _MMIO(0x8F074)
5929 #define CSR_HTP_SKL _MMIO(0x8F004)
5930 #define CSR_LAST_WRITE _MMIO(0x8F034)
5931 #define CSR_LAST_WRITE_VALUE 0xc003b400
5932 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
5933 #define CSR_MMIO_START_RANGE 0x80000
5934 #define CSR_MMIO_END_RANGE 0x8FFFF
5935 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
5936 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
5937 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
5938
5939 /* interrupts */
5940 #define DE_MASTER_IRQ_CONTROL (1 << 31)
5941 #define DE_SPRITEB_FLIP_DONE (1 << 29)
5942 #define DE_SPRITEA_FLIP_DONE (1 << 28)
5943 #define DE_PLANEB_FLIP_DONE (1 << 27)
5944 #define DE_PLANEA_FLIP_DONE (1 << 26)
5945 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5946 #define DE_PCU_EVENT (1 << 25)
5947 #define DE_GTT_FAULT (1 << 24)
5948 #define DE_POISON (1 << 23)
5949 #define DE_PERFORM_COUNTER (1 << 22)
5950 #define DE_PCH_EVENT (1 << 21)
5951 #define DE_AUX_CHANNEL_A (1 << 20)
5952 #define DE_DP_A_HOTPLUG (1 << 19)
5953 #define DE_GSE (1 << 18)
5954 #define DE_PIPEB_VBLANK (1 << 15)
5955 #define DE_PIPEB_EVEN_FIELD (1 << 14)
5956 #define DE_PIPEB_ODD_FIELD (1 << 13)
5957 #define DE_PIPEB_LINE_COMPARE (1 << 12)
5958 #define DE_PIPEB_VSYNC (1 << 11)
5959 #define DE_PIPEB_CRC_DONE (1 << 10)
5960 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5961 #define DE_PIPEA_VBLANK (1 << 7)
5962 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
5963 #define DE_PIPEA_EVEN_FIELD (1 << 6)
5964 #define DE_PIPEA_ODD_FIELD (1 << 5)
5965 #define DE_PIPEA_LINE_COMPARE (1 << 4)
5966 #define DE_PIPEA_VSYNC (1 << 3)
5967 #define DE_PIPEA_CRC_DONE (1 << 2)
5968 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
5969 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5970 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
5971
5972 /* More Ivybridge lolz */
5973 #define DE_ERR_INT_IVB (1<<30)
5974 #define DE_GSE_IVB (1<<29)
5975 #define DE_PCH_EVENT_IVB (1<<28)
5976 #define DE_DP_A_HOTPLUG_IVB (1<<27)
5977 #define DE_AUX_CHANNEL_A_IVB (1<<26)
5978 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5979 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5980 #define DE_PIPEC_VBLANK_IVB (1<<10)
5981 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
5982 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
5983 #define DE_PIPEB_VBLANK_IVB (1<<5)
5984 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5985 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
5986 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
5987 #define DE_PIPEA_VBLANK_IVB (1<<0)
5988 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5989
5990 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
5991 #define MASTER_INTERRUPT_ENABLE (1<<31)
5992
5993 #define DEISR _MMIO(0x44000)
5994 #define DEIMR _MMIO(0x44004)
5995 #define DEIIR _MMIO(0x44008)
5996 #define DEIER _MMIO(0x4400c)
5997
5998 #define GTISR _MMIO(0x44010)
5999 #define GTIMR _MMIO(0x44014)
6000 #define GTIIR _MMIO(0x44018)
6001 #define GTIER _MMIO(0x4401c)
6002
6003 #define GEN8_MASTER_IRQ _MMIO(0x44200)
6004 #define GEN8_MASTER_IRQ_CONTROL (1<<31)
6005 #define GEN8_PCU_IRQ (1<<30)
6006 #define GEN8_DE_PCH_IRQ (1<<23)
6007 #define GEN8_DE_MISC_IRQ (1<<22)
6008 #define GEN8_DE_PORT_IRQ (1<<20)
6009 #define GEN8_DE_PIPE_C_IRQ (1<<18)
6010 #define GEN8_DE_PIPE_B_IRQ (1<<17)
6011 #define GEN8_DE_PIPE_A_IRQ (1<<16)
6012 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
6013 #define GEN8_GT_VECS_IRQ (1<<6)
6014 #define GEN8_GT_PM_IRQ (1<<4)
6015 #define GEN8_GT_VCS2_IRQ (1<<3)
6016 #define GEN8_GT_VCS1_IRQ (1<<2)
6017 #define GEN8_GT_BCS_IRQ (1<<1)
6018 #define GEN8_GT_RCS_IRQ (1<<0)
6019
6020 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
6021 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
6022 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
6023 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
6024
6025 #define GEN8_RCS_IRQ_SHIFT 0
6026 #define GEN8_BCS_IRQ_SHIFT 16
6027 #define GEN8_VCS1_IRQ_SHIFT 0
6028 #define GEN8_VCS2_IRQ_SHIFT 16
6029 #define GEN8_VECS_IRQ_SHIFT 0
6030 #define GEN8_WD_IRQ_SHIFT 16
6031
6032 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
6033 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
6034 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
6035 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
6036 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
6037 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
6038 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
6039 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
6040 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
6041 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
6042 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
6043 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
6044 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
6045 #define GEN8_PIPE_VSYNC (1 << 1)
6046 #define GEN8_PIPE_VBLANK (1 << 0)
6047 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
6048 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
6049 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
6050 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
6051 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
6052 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
6053 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
6054 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
6055 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
6056 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
6057 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
6058 (GEN8_PIPE_CURSOR_FAULT | \
6059 GEN8_PIPE_SPRITE_FAULT | \
6060 GEN8_PIPE_PRIMARY_FAULT)
6061 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
6062 (GEN9_PIPE_CURSOR_FAULT | \
6063 GEN9_PIPE_PLANE4_FAULT | \
6064 GEN9_PIPE_PLANE3_FAULT | \
6065 GEN9_PIPE_PLANE2_FAULT | \
6066 GEN9_PIPE_PLANE1_FAULT)
6067
6068 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
6069 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
6070 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
6071 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
6072 #define GEN9_AUX_CHANNEL_D (1 << 27)
6073 #define GEN9_AUX_CHANNEL_C (1 << 26)
6074 #define GEN9_AUX_CHANNEL_B (1 << 25)
6075 #define BXT_DE_PORT_HP_DDIC (1 << 5)
6076 #define BXT_DE_PORT_HP_DDIB (1 << 4)
6077 #define BXT_DE_PORT_HP_DDIA (1 << 3)
6078 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
6079 BXT_DE_PORT_HP_DDIB | \
6080 BXT_DE_PORT_HP_DDIC)
6081 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
6082 #define BXT_DE_PORT_GMBUS (1 << 1)
6083 #define GEN8_AUX_CHANNEL_A (1 << 0)
6084
6085 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
6086 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
6087 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
6088 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
6089 #define GEN8_DE_MISC_GSE (1 << 27)
6090
6091 #define GEN8_PCU_ISR _MMIO(0x444e0)
6092 #define GEN8_PCU_IMR _MMIO(0x444e4)
6093 #define GEN8_PCU_IIR _MMIO(0x444e8)
6094 #define GEN8_PCU_IER _MMIO(0x444ec)
6095
6096 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
6097 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
6098 #define ILK_ELPIN_409_SELECT (1 << 25)
6099 #define ILK_DPARB_GATE (1<<22)
6100 #define ILK_VSDPFD_FULL (1<<21)
6101 #define FUSE_STRAP _MMIO(0x42014)
6102 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
6103 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
6104 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
6105 #define IVB_PIPE_C_DISABLE (1 << 28)
6106 #define ILK_HDCP_DISABLE (1 << 25)
6107 #define ILK_eDP_A_DISABLE (1 << 24)
6108 #define HSW_CDCLK_LIMIT (1 << 24)
6109 #define ILK_DESKTOP (1 << 23)
6110
6111 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
6112 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
6113 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
6114 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
6115 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
6116 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
6117
6118 #define IVB_CHICKEN3 _MMIO(0x4200c)
6119 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
6120 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
6121
6122 #define CHICKEN_PAR1_1 _MMIO(0x42080)
6123 #define DPA_MASK_VBLANK_SRD (1 << 15)
6124 #define FORCE_ARB_IDLE_PLANES (1 << 14)
6125 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
6126
6127 #define CHICKEN_PAR2_1 _MMIO(0x42090)
6128 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
6129
6130 #define _CHICKEN_PIPESL_1_A 0x420b0
6131 #define _CHICKEN_PIPESL_1_B 0x420b4
6132 #define HSW_FBCQ_DIS (1 << 22)
6133 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
6134 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
6135
6136 #define DISP_ARB_CTL _MMIO(0x45000)
6137 #define DISP_FBC_MEMORY_WAKE (1<<31)
6138 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
6139 #define DISP_FBC_WM_DIS (1<<15)
6140 #define DISP_ARB_CTL2 _MMIO(0x45004)
6141 #define DISP_DATA_PARTITION_5_6 (1<<6)
6142 #define DBUF_CTL _MMIO(0x45008)
6143 #define DBUF_POWER_REQUEST (1<<31)
6144 #define DBUF_POWER_STATE (1<<30)
6145 #define GEN7_MSG_CTL _MMIO(0x45010)
6146 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
6147 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
6148 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
6149 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
6150
6151 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6152 #define MASK_WAKEMEM (1<<13)
6153
6154 #define SKL_DFSM _MMIO(0x51000)
6155 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
6156 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
6157 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
6158 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
6159 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
6160 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
6161 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
6162 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
6163
6164 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
6165 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
6166
6167 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
6168 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
6169 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10)
6170
6171 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
6172 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
6173 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
6174
6175 /* GEN7 chicken */
6176 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
6177 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
6178 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
6179 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
6180 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
6181 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
6182 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
6183
6184 #define HIZ_CHICKEN _MMIO(0x7018)
6185 # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
6186 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
6187
6188 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
6189 #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
6190
6191 #define GEN7_L3SQCREG1 _MMIO(0xB010)
6192 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
6193
6194 #define GEN8_L3SQCREG1 _MMIO(0xB100)
6195 /*
6196 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
6197 * Using the formula in BSpec leads to a hang, while the formula here works
6198 * fine and matches the formulas for all other platforms. A BSpec change
6199 * request has been filed to clarify this.
6200 */
6201 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
6202 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
6203
6204 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
6205 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
6206 #define GEN7_L3AGDIS (1<<19)
6207 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
6208 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
6209
6210 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
6211 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
6212
6213 #define GEN7_L3SQCREG4 _MMIO(0xb034)
6214 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
6215
6216 #define GEN8_L3SQCREG4 _MMIO(0xb118)
6217 #define GEN8_LQSC_RO_PERF_DIS (1<<27)
6218 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
6219
6220 /* GEN8 chicken */
6221 #define HDC_CHICKEN0 _MMIO(0x7300)
6222 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
6223 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
6224 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
6225 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
6226 #define HDC_FORCE_NON_COHERENT (1<<4)
6227 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
6228
6229 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
6230
6231 /* GEN9 chicken */
6232 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
6233 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
6234
6235 /* WaCatErrorRejectionIssue */
6236 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
6237 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
6238
6239 #define HSW_SCRATCH1 _MMIO(0xb038)
6240 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
6241
6242 #define BDW_SCRATCH1 _MMIO(0xb11c)
6243 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
6244
6245 /* PCH */
6246
6247 /* south display engine interrupt: IBX */
6248 #define SDE_AUDIO_POWER_D (1 << 27)
6249 #define SDE_AUDIO_POWER_C (1 << 26)
6250 #define SDE_AUDIO_POWER_B (1 << 25)
6251 #define SDE_AUDIO_POWER_SHIFT (25)
6252 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
6253 #define SDE_GMBUS (1 << 24)
6254 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
6255 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
6256 #define SDE_AUDIO_HDCP_MASK (3 << 22)
6257 #define SDE_AUDIO_TRANSB (1 << 21)
6258 #define SDE_AUDIO_TRANSA (1 << 20)
6259 #define SDE_AUDIO_TRANS_MASK (3 << 20)
6260 #define SDE_POISON (1 << 19)
6261 /* 18 reserved */
6262 #define SDE_FDI_RXB (1 << 17)
6263 #define SDE_FDI_RXA (1 << 16)
6264 #define SDE_FDI_MASK (3 << 16)
6265 #define SDE_AUXD (1 << 15)
6266 #define SDE_AUXC (1 << 14)
6267 #define SDE_AUXB (1 << 13)
6268 #define SDE_AUX_MASK (7 << 13)
6269 /* 12 reserved */
6270 #define SDE_CRT_HOTPLUG (1 << 11)
6271 #define SDE_PORTD_HOTPLUG (1 << 10)
6272 #define SDE_PORTC_HOTPLUG (1 << 9)
6273 #define SDE_PORTB_HOTPLUG (1 << 8)
6274 #define SDE_SDVOB_HOTPLUG (1 << 6)
6275 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
6276 SDE_SDVOB_HOTPLUG | \
6277 SDE_PORTB_HOTPLUG | \
6278 SDE_PORTC_HOTPLUG | \
6279 SDE_PORTD_HOTPLUG)
6280 #define SDE_TRANSB_CRC_DONE (1 << 5)
6281 #define SDE_TRANSB_CRC_ERR (1 << 4)
6282 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
6283 #define SDE_TRANSA_CRC_DONE (1 << 2)
6284 #define SDE_TRANSA_CRC_ERR (1 << 1)
6285 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
6286 #define SDE_TRANS_MASK (0x3f)
6287
6288 /* south display engine interrupt: CPT/PPT */
6289 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
6290 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
6291 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
6292 #define SDE_AUDIO_POWER_SHIFT_CPT 29
6293 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
6294 #define SDE_AUXD_CPT (1 << 27)
6295 #define SDE_AUXC_CPT (1 << 26)
6296 #define SDE_AUXB_CPT (1 << 25)
6297 #define SDE_AUX_MASK_CPT (7 << 25)
6298 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
6299 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
6300 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
6301 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
6302 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
6303 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
6304 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
6305 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
6306 SDE_SDVOB_HOTPLUG_CPT | \
6307 SDE_PORTD_HOTPLUG_CPT | \
6308 SDE_PORTC_HOTPLUG_CPT | \
6309 SDE_PORTB_HOTPLUG_CPT)
6310 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
6311 SDE_PORTD_HOTPLUG_CPT | \
6312 SDE_PORTC_HOTPLUG_CPT | \
6313 SDE_PORTB_HOTPLUG_CPT | \
6314 SDE_PORTA_HOTPLUG_SPT)
6315 #define SDE_GMBUS_CPT (1 << 17)
6316 #define SDE_ERROR_CPT (1 << 16)
6317 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
6318 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
6319 #define SDE_FDI_RXC_CPT (1 << 8)
6320 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
6321 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
6322 #define SDE_FDI_RXB_CPT (1 << 4)
6323 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
6324 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
6325 #define SDE_FDI_RXA_CPT (1 << 0)
6326 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
6327 SDE_AUDIO_CP_REQ_B_CPT | \
6328 SDE_AUDIO_CP_REQ_A_CPT)
6329 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
6330 SDE_AUDIO_CP_CHG_B_CPT | \
6331 SDE_AUDIO_CP_CHG_A_CPT)
6332 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
6333 SDE_FDI_RXB_CPT | \
6334 SDE_FDI_RXA_CPT)
6335
6336 #define SDEISR _MMIO(0xc4000)
6337 #define SDEIMR _MMIO(0xc4004)
6338 #define SDEIIR _MMIO(0xc4008)
6339 #define SDEIER _MMIO(0xc400c)
6340
6341 #define SERR_INT _MMIO(0xc4040)
6342 #define SERR_INT_POISON (1<<31)
6343 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
6344 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
6345 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
6346 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
6347
6348 /* digital port hotplug */
6349 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
6350 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
6351 #define BXT_DDIA_HPD_INVERT (1 << 27)
6352 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
6353 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
6354 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
6355 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
6356 #define PORTD_HOTPLUG_ENABLE (1 << 20)
6357 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
6358 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
6359 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
6360 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
6361 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
6362 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
6363 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
6364 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
6365 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
6366 #define PORTC_HOTPLUG_ENABLE (1 << 12)
6367 #define BXT_DDIC_HPD_INVERT (1 << 11)
6368 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
6369 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
6370 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
6371 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
6372 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
6373 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
6374 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6375 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6376 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
6377 #define PORTB_HOTPLUG_ENABLE (1 << 4)
6378 #define BXT_DDIB_HPD_INVERT (1 << 3)
6379 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
6380 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
6381 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
6382 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
6383 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
6384 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
6385 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6386 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6387 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
6388 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
6389 BXT_DDIB_HPD_INVERT | \
6390 BXT_DDIC_HPD_INVERT)
6391
6392 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
6393 #define PORTE_HOTPLUG_ENABLE (1 << 4)
6394 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
6395 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
6396 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
6397 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
6398
6399 #define PCH_GPIOA _MMIO(0xc5010)
6400 #define PCH_GPIOB _MMIO(0xc5014)
6401 #define PCH_GPIOC _MMIO(0xc5018)
6402 #define PCH_GPIOD _MMIO(0xc501c)
6403 #define PCH_GPIOE _MMIO(0xc5020)
6404 #define PCH_GPIOF _MMIO(0xc5024)
6405
6406 #define PCH_GMBUS0 _MMIO(0xc5100)
6407 #define PCH_GMBUS1 _MMIO(0xc5104)
6408 #define PCH_GMBUS2 _MMIO(0xc5108)
6409 #define PCH_GMBUS3 _MMIO(0xc510c)
6410 #define PCH_GMBUS4 _MMIO(0xc5110)
6411 #define PCH_GMBUS5 _MMIO(0xc5120)
6412
6413 #define _PCH_DPLL_A 0xc6014
6414 #define _PCH_DPLL_B 0xc6018
6415 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6416
6417 #define _PCH_FPA0 0xc6040
6418 #define FP_CB_TUNE (0x3<<22)
6419 #define _PCH_FPA1 0xc6044
6420 #define _PCH_FPB0 0xc6048
6421 #define _PCH_FPB1 0xc604c
6422 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6423 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6424
6425 #define PCH_DPLL_TEST _MMIO(0xc606c)
6426
6427 #define PCH_DREF_CONTROL _MMIO(0xC6200)
6428 #define DREF_CONTROL_MASK 0x7fc3
6429 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6430 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6431 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6432 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6433 #define DREF_SSC_SOURCE_DISABLE (0<<11)
6434 #define DREF_SSC_SOURCE_ENABLE (2<<11)
6435 #define DREF_SSC_SOURCE_MASK (3<<11)
6436 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6437 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6438 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
6439 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
6440 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6441 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
6442 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
6443 #define DREF_SSC4_DOWNSPREAD (0<<6)
6444 #define DREF_SSC4_CENTERSPREAD (1<<6)
6445 #define DREF_SSC1_DISABLE (0<<1)
6446 #define DREF_SSC1_ENABLE (1<<1)
6447 #define DREF_SSC4_DISABLE (0)
6448 #define DREF_SSC4_ENABLE (1)
6449
6450 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
6451 #define FDL_TP1_TIMER_SHIFT 12
6452 #define FDL_TP1_TIMER_MASK (3<<12)
6453 #define FDL_TP2_TIMER_SHIFT 10
6454 #define FDL_TP2_TIMER_MASK (3<<10)
6455 #define RAWCLK_FREQ_MASK 0x3ff
6456
6457 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
6458
6459 #define PCH_SSC4_PARMS _MMIO(0xc6210)
6460 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
6461
6462 #define PCH_DPLL_SEL _MMIO(0xc7000)
6463 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6464 #define TRANS_DPLLA_SEL(pipe) 0
6465 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
6466
6467 /* transcoder */
6468
6469 #define _PCH_TRANS_HTOTAL_A 0xe0000
6470 #define TRANS_HTOTAL_SHIFT 16
6471 #define TRANS_HACTIVE_SHIFT 0
6472 #define _PCH_TRANS_HBLANK_A 0xe0004
6473 #define TRANS_HBLANK_END_SHIFT 16
6474 #define TRANS_HBLANK_START_SHIFT 0
6475 #define _PCH_TRANS_HSYNC_A 0xe0008
6476 #define TRANS_HSYNC_END_SHIFT 16
6477 #define TRANS_HSYNC_START_SHIFT 0
6478 #define _PCH_TRANS_VTOTAL_A 0xe000c
6479 #define TRANS_VTOTAL_SHIFT 16
6480 #define TRANS_VACTIVE_SHIFT 0
6481 #define _PCH_TRANS_VBLANK_A 0xe0010
6482 #define TRANS_VBLANK_END_SHIFT 16
6483 #define TRANS_VBLANK_START_SHIFT 0
6484 #define _PCH_TRANS_VSYNC_A 0xe0014
6485 #define TRANS_VSYNC_END_SHIFT 16
6486 #define TRANS_VSYNC_START_SHIFT 0
6487 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6488
6489 #define _PCH_TRANSA_DATA_M1 0xe0030
6490 #define _PCH_TRANSA_DATA_N1 0xe0034
6491 #define _PCH_TRANSA_DATA_M2 0xe0038
6492 #define _PCH_TRANSA_DATA_N2 0xe003c
6493 #define _PCH_TRANSA_LINK_M1 0xe0040
6494 #define _PCH_TRANSA_LINK_N1 0xe0044
6495 #define _PCH_TRANSA_LINK_M2 0xe0048
6496 #define _PCH_TRANSA_LINK_N2 0xe004c
6497
6498 /* Per-transcoder DIP controls (PCH) */
6499 #define _VIDEO_DIP_CTL_A 0xe0200
6500 #define _VIDEO_DIP_DATA_A 0xe0208
6501 #define _VIDEO_DIP_GCP_A 0xe0210
6502 #define GCP_COLOR_INDICATION (1 << 2)
6503 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6504 #define GCP_AV_MUTE (1 << 0)
6505
6506 #define _VIDEO_DIP_CTL_B 0xe1200
6507 #define _VIDEO_DIP_DATA_B 0xe1208
6508 #define _VIDEO_DIP_GCP_B 0xe1210
6509
6510 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6511 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6512 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6513
6514 /* Per-transcoder DIP controls (VLV) */
6515 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6516 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6517 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6518
6519 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6520 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6521 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6522
6523 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6524 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6525 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6526
6527 #define VLV_TVIDEO_DIP_CTL(pipe) \
6528 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6529 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
6530 #define VLV_TVIDEO_DIP_DATA(pipe) \
6531 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6532 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
6533 #define VLV_TVIDEO_DIP_GCP(pipe) \
6534 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6535 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6536
6537 /* Haswell DIP controls */
6538
6539 #define _HSW_VIDEO_DIP_CTL_A 0x60200
6540 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6541 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6542 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6543 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6544 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6545 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6546 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6547 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6548 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6549 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6550 #define _HSW_VIDEO_DIP_GCP_A 0x60210
6551
6552 #define _HSW_VIDEO_DIP_CTL_B 0x61200
6553 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6554 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6555 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6556 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6557 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6558 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6559 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6560 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6561 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6562 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6563 #define _HSW_VIDEO_DIP_GCP_B 0x61210
6564
6565 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6566 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6567 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6568 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6569 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6570 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6571
6572 #define _HSW_STEREO_3D_CTL_A 0x70020
6573 #define S3D_ENABLE (1<<31)
6574 #define _HSW_STEREO_3D_CTL_B 0x71020
6575
6576 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
6577
6578 #define _PCH_TRANS_HTOTAL_B 0xe1000
6579 #define _PCH_TRANS_HBLANK_B 0xe1004
6580 #define _PCH_TRANS_HSYNC_B 0xe1008
6581 #define _PCH_TRANS_VTOTAL_B 0xe100c
6582 #define _PCH_TRANS_VBLANK_B 0xe1010
6583 #define _PCH_TRANS_VSYNC_B 0xe1014
6584 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6585
6586 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6587 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6588 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6589 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6590 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6591 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6592 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
6593
6594 #define _PCH_TRANSB_DATA_M1 0xe1030
6595 #define _PCH_TRANSB_DATA_N1 0xe1034
6596 #define _PCH_TRANSB_DATA_M2 0xe1038
6597 #define _PCH_TRANSB_DATA_N2 0xe103c
6598 #define _PCH_TRANSB_LINK_M1 0xe1040
6599 #define _PCH_TRANSB_LINK_N1 0xe1044
6600 #define _PCH_TRANSB_LINK_M2 0xe1048
6601 #define _PCH_TRANSB_LINK_N2 0xe104c
6602
6603 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6604 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6605 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6606 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6607 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6608 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6609 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6610 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6611
6612 #define _PCH_TRANSACONF 0xf0008
6613 #define _PCH_TRANSBCONF 0xf1008
6614 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6615 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
6616 #define TRANS_DISABLE (0<<31)
6617 #define TRANS_ENABLE (1<<31)
6618 #define TRANS_STATE_MASK (1<<30)
6619 #define TRANS_STATE_DISABLE (0<<30)
6620 #define TRANS_STATE_ENABLE (1<<30)
6621 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
6622 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
6623 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
6624 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
6625 #define TRANS_INTERLACE_MASK (7<<21)
6626 #define TRANS_PROGRESSIVE (0<<21)
6627 #define TRANS_INTERLACED (3<<21)
6628 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
6629 #define TRANS_8BPC (0<<5)
6630 #define TRANS_10BPC (1<<5)
6631 #define TRANS_6BPC (2<<5)
6632 #define TRANS_12BPC (3<<5)
6633
6634 #define _TRANSA_CHICKEN1 0xf0060
6635 #define _TRANSB_CHICKEN1 0xf1060
6636 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6637 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
6638 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
6639 #define _TRANSA_CHICKEN2 0xf0064
6640 #define _TRANSB_CHICKEN2 0xf1064
6641 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6642 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6643 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6644 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6645 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6646 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
6647
6648 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
6649 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
6650 #define FDIA_PHASE_SYNC_SHIFT_EN 18
6651 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6652 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6653 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
6654 #define SPT_PWM_GRANULARITY (1<<0)
6655 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
6656 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6657 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6658 #define LPT_PWM_GRANULARITY (1<<5)
6659 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
6660
6661 #define _FDI_RXA_CHICKEN 0xc200c
6662 #define _FDI_RXB_CHICKEN 0xc2010
6663 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6664 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
6665 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6666
6667 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
6668 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6669 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6670 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6671 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
6672
6673 /* CPU: FDI_TX */
6674 #define _FDI_TXA_CTL 0x60100
6675 #define _FDI_TXB_CTL 0x61100
6676 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6677 #define FDI_TX_DISABLE (0<<31)
6678 #define FDI_TX_ENABLE (1<<31)
6679 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6680 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6681 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6682 #define FDI_LINK_TRAIN_NONE (3<<28)
6683 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6684 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6685 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6686 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6687 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6688 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6689 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6690 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
6691 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6692 SNB has different settings. */
6693 /* SNB A-stepping */
6694 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6695 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6696 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6697 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6698 /* SNB B-stepping */
6699 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6700 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6701 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6702 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6703 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
6704 #define FDI_DP_PORT_WIDTH_SHIFT 19
6705 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6706 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6707 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
6708 /* Ironlake: hardwired to 1 */
6709 #define FDI_TX_PLL_ENABLE (1<<14)
6710
6711 /* Ivybridge has different bits for lolz */
6712 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6713 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6714 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6715 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6716
6717 /* both Tx and Rx */
6718 #define FDI_COMPOSITE_SYNC (1<<11)
6719 #define FDI_LINK_TRAIN_AUTO (1<<10)
6720 #define FDI_SCRAMBLING_ENABLE (0<<7)
6721 #define FDI_SCRAMBLING_DISABLE (1<<7)
6722
6723 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6724 #define _FDI_RXA_CTL 0xf000c
6725 #define _FDI_RXB_CTL 0xf100c
6726 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6727 #define FDI_RX_ENABLE (1<<31)
6728 /* train, dp width same as FDI_TX */
6729 #define FDI_FS_ERRC_ENABLE (1<<27)
6730 #define FDI_FE_ERRC_ENABLE (1<<26)
6731 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
6732 #define FDI_8BPC (0<<16)
6733 #define FDI_10BPC (1<<16)
6734 #define FDI_6BPC (2<<16)
6735 #define FDI_12BPC (3<<16)
6736 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
6737 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6738 #define FDI_RX_PLL_ENABLE (1<<13)
6739 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6740 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6741 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6742 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6743 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
6744 #define FDI_PCDCLK (1<<4)
6745 /* CPT */
6746 #define FDI_AUTO_TRAINING (1<<10)
6747 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6748 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6749 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6750 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6751 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
6752
6753 #define _FDI_RXA_MISC 0xf0010
6754 #define _FDI_RXB_MISC 0xf1010
6755 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6756 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6757 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6758 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6759 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
6760 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
6761 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
6762 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6763
6764 #define _FDI_RXA_TUSIZE1 0xf0030
6765 #define _FDI_RXA_TUSIZE2 0xf0038
6766 #define _FDI_RXB_TUSIZE1 0xf1030
6767 #define _FDI_RXB_TUSIZE2 0xf1038
6768 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6769 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6770
6771 /* FDI_RX interrupt register format */
6772 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
6773 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6774 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6775 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6776 #define FDI_RX_FS_CODE_ERR (1<<6)
6777 #define FDI_RX_FE_CODE_ERR (1<<5)
6778 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6779 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
6780 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6781 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6782 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6783
6784 #define _FDI_RXA_IIR 0xf0014
6785 #define _FDI_RXA_IMR 0xf0018
6786 #define _FDI_RXB_IIR 0xf1014
6787 #define _FDI_RXB_IMR 0xf1018
6788 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6789 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6790
6791 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
6792 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
6793
6794 #define PCH_LVDS _MMIO(0xe1180)
6795 #define LVDS_DETECTED (1 << 1)
6796
6797 #define _PCH_DP_B 0xe4100
6798 #define PCH_DP_B _MMIO(_PCH_DP_B)
6799 #define _PCH_DPB_AUX_CH_CTL 0xe4110
6800 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
6801 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
6802 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
6803 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
6804 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
6805
6806 #define _PCH_DP_C 0xe4200
6807 #define PCH_DP_C _MMIO(_PCH_DP_C)
6808 #define _PCH_DPC_AUX_CH_CTL 0xe4210
6809 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
6810 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
6811 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
6812 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
6813 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
6814
6815 #define _PCH_DP_D 0xe4300
6816 #define PCH_DP_D _MMIO(_PCH_DP_D)
6817 #define _PCH_DPD_AUX_CH_CTL 0xe4310
6818 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
6819 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
6820 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
6821 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
6822 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
6823
6824 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6825 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6826
6827 /* CPT */
6828 #define PORT_TRANS_A_SEL_CPT 0
6829 #define PORT_TRANS_B_SEL_CPT (1<<29)
6830 #define PORT_TRANS_C_SEL_CPT (2<<29)
6831 #define PORT_TRANS_SEL_MASK (3<<29)
6832 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
6833 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6834 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
6835 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6836 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
6837
6838 #define _TRANS_DP_CTL_A 0xe0300
6839 #define _TRANS_DP_CTL_B 0xe1300
6840 #define _TRANS_DP_CTL_C 0xe2300
6841 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
6842 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
6843 #define TRANS_DP_PORT_SEL_B (0<<29)
6844 #define TRANS_DP_PORT_SEL_C (1<<29)
6845 #define TRANS_DP_PORT_SEL_D (2<<29)
6846 #define TRANS_DP_PORT_SEL_NONE (3<<29)
6847 #define TRANS_DP_PORT_SEL_MASK (3<<29)
6848 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
6849 #define TRANS_DP_AUDIO_ONLY (1<<26)
6850 #define TRANS_DP_ENH_FRAMING (1<<18)
6851 #define TRANS_DP_8BPC (0<<9)
6852 #define TRANS_DP_10BPC (1<<9)
6853 #define TRANS_DP_6BPC (2<<9)
6854 #define TRANS_DP_12BPC (3<<9)
6855 #define TRANS_DP_BPC_MASK (3<<9)
6856 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6857 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
6858 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6859 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
6860 #define TRANS_DP_SYNC_MASK (3<<3)
6861
6862 /* SNB eDP training params */
6863 /* SNB A-stepping */
6864 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6865 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6866 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6867 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6868 /* SNB B-stepping */
6869 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6870 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6871 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6872 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6873 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
6874 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6875
6876 /* IVB */
6877 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6878 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6879 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6880 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6881 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6882 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
6883 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
6884
6885 /* legacy values */
6886 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6887 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6888 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6889 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6890 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6891
6892 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6893
6894 #define VLV_PMWGICZ _MMIO(0x1300a4)
6895
6896 #define RC6_LOCATION _MMIO(0xD40)
6897 #define RC6_CTX_IN_DRAM (1 << 0)
6898 #define RC6_CTX_BASE _MMIO(0xD48)
6899 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
6900 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
6901 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
6902 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
6903 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
6904 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
6905 #define IDLE_TIME_MASK 0xFFFFF
6906 #define FORCEWAKE _MMIO(0xA18C)
6907 #define FORCEWAKE_VLV _MMIO(0x1300b0)
6908 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
6909 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
6910 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
6911 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
6912 #define FORCEWAKE_ACK _MMIO(0x130090)
6913 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
6914 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6915 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6916 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6917
6918 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
6919 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6920 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6921 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6922 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
6923 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
6924 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
6925 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
6926 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
6927 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
6928 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
6929 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
6930 #define FORCEWAKE_KERNEL 0x1
6931 #define FORCEWAKE_USER 0x2
6932 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
6933 #define ECOBUS _MMIO(0xa180)
6934 #define FORCEWAKE_MT_ENABLE (1<<5)
6935 #define VLV_SPAREG2H _MMIO(0xA194)
6936 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
6937 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
6938 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
6939
6940 #define GTFIFODBG _MMIO(0x120000)
6941 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
6942 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
6943 #define GT_FIFO_SBDROPERR (1<<6)
6944 #define GT_FIFO_BLOBDROPERR (1<<5)
6945 #define GT_FIFO_SB_READ_ABORTERR (1<<4)
6946 #define GT_FIFO_DROPERR (1<<3)
6947 #define GT_FIFO_OVFERR (1<<2)
6948 #define GT_FIFO_IAWRERR (1<<1)
6949 #define GT_FIFO_IARDERR (1<<0)
6950
6951 #define GTFIFOCTL _MMIO(0x120008)
6952 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
6953 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
6954 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6955 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
6956
6957 #define HSW_IDICR _MMIO(0x9008)
6958 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6959 #define HSW_EDRAM_CAP _MMIO(0x120010)
6960 #define EDRAM_ENABLED 0x1
6961 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
6962 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
6963 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
6964
6965 #define GEN6_UCGCTL1 _MMIO(0x9400)
6966 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
6967 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6968 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6969 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
6970
6971 #define GEN6_UCGCTL2 _MMIO(0x9404)
6972 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
6973 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6974 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
6975 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
6976 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
6977 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
6978
6979 #define GEN6_UCGCTL3 _MMIO(0x9408)
6980
6981 #define GEN7_UCGCTL4 _MMIO(0x940c)
6982 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6983 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
6984
6985 #define GEN6_RCGCTL1 _MMIO(0x9410)
6986 #define GEN6_RCGCTL2 _MMIO(0x9414)
6987 #define GEN6_RSTCTL _MMIO(0x9420)
6988
6989 #define GEN8_UCGCTL6 _MMIO(0x9430)
6990 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
6991 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6992 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6993
6994 #define GEN6_GFXPAUSE _MMIO(0xA000)
6995 #define GEN6_RPNSWREQ _MMIO(0xA008)
6996 #define GEN6_TURBO_DISABLE (1<<31)
6997 #define GEN6_FREQUENCY(x) ((x)<<25)
6998 #define HSW_FREQUENCY(x) ((x)<<24)
6999 #define GEN9_FREQUENCY(x) ((x)<<23)
7000 #define GEN6_OFFSET(x) ((x)<<19)
7001 #define GEN6_AGGRESSIVE_TURBO (0<<15)
7002 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
7003 #define GEN6_RC_CONTROL _MMIO(0xA090)
7004 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
7005 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
7006 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
7007 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
7008 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
7009 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
7010 #define GEN7_RC_CTL_TO_MODE (1<<28)
7011 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
7012 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
7013 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
7014 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
7015 #define GEN6_RPSTAT1 _MMIO(0xA01C)
7016 #define GEN6_CAGF_SHIFT 8
7017 #define HSW_CAGF_SHIFT 7
7018 #define GEN9_CAGF_SHIFT 23
7019 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
7020 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
7021 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
7022 #define GEN6_RP_CONTROL _MMIO(0xA024)
7023 #define GEN6_RP_MEDIA_TURBO (1<<11)
7024 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
7025 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
7026 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
7027 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
7028 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
7029 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
7030 #define GEN6_RP_ENABLE (1<<7)
7031 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
7032 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
7033 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
7034 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
7035 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
7036 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
7037 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
7038 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
7039 #define GEN6_RP_EI_MASK 0xffffff
7040 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
7041 #define GEN6_RP_CUR_UP _MMIO(0xA054)
7042 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
7043 #define GEN6_RP_PREV_UP _MMIO(0xA058)
7044 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
7045 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
7046 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
7047 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
7048 #define GEN6_RP_UP_EI _MMIO(0xA068)
7049 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
7050 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
7051 #define GEN6_RPDEUHWTC _MMIO(0xA080)
7052 #define GEN6_RPDEUC _MMIO(0xA084)
7053 #define GEN6_RPDEUCSW _MMIO(0xA088)
7054 #define GEN6_RC_STATE _MMIO(0xA094)
7055 #define RC_SW_TARGET_STATE_SHIFT 16
7056 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
7057 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
7058 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
7059 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
7060 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
7061 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
7062 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
7063 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
7064 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
7065 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
7066 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
7067 #define VLV_RCEDATA _MMIO(0xA0BC)
7068 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
7069 #define GEN6_PMINTRMSK _MMIO(0xA168)
7070 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
7071 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
7072 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
7073 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
7074 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
7075 #define GEN9_PG_ENABLE _MMIO(0xA210)
7076 #define GEN9_RENDER_PG_ENABLE (1<<0)
7077 #define GEN9_MEDIA_PG_ENABLE (1<<1)
7078 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
7079 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
7080 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
7081
7082 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
7083 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
7084 #define PIXEL_OVERLAP_CNT_SHIFT 30
7085
7086 #define GEN6_PMISR _MMIO(0x44020)
7087 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
7088 #define GEN6_PMIIR _MMIO(0x44028)
7089 #define GEN6_PMIER _MMIO(0x4402C)
7090 #define GEN6_PM_MBOX_EVENT (1<<25)
7091 #define GEN6_PM_THERMAL_EVENT (1<<24)
7092 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
7093 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
7094 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
7095 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
7096 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
7097 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
7098 GEN6_PM_RP_DOWN_THRESHOLD | \
7099 GEN6_PM_RP_DOWN_TIMEOUT)
7100
7101 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
7102 #define GEN7_GT_SCRATCH_REG_NUM 8
7103
7104 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
7105 #define VLV_GFX_CLK_STATUS_BIT (1<<3)
7106 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
7107
7108 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
7109 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
7110 #define VLV_COUNT_RANGE_HIGH (1<<15)
7111 #define VLV_MEDIA_RC0_COUNT_EN (1<<5)
7112 #define VLV_RENDER_RC0_COUNT_EN (1<<4)
7113 #define VLV_MEDIA_RC6_COUNT_EN (1<<1)
7114 #define VLV_RENDER_RC6_COUNT_EN (1<<0)
7115 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
7116 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
7117 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
7118
7119 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
7120 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
7121 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
7122 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
7123
7124 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
7125 #define GEN6_PCODE_READY (1<<31)
7126 #define GEN6_PCODE_ERROR_MASK 0xFF
7127 #define GEN6_PCODE_SUCCESS 0x0
7128 #define GEN6_PCODE_ILLEGAL_CMD 0x1
7129 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
7130 #define GEN6_PCODE_TIMEOUT 0x3
7131 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
7132 #define GEN7_PCODE_TIMEOUT 0x2
7133 #define GEN7_PCODE_ILLEGAL_DATA 0x3
7134 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
7135 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
7136 #define GEN6_PCODE_READ_RC6VIDS 0x5
7137 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
7138 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
7139 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
7140 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
7141 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
7142 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
7143 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
7144 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
7145 #define SKL_PCODE_CDCLK_CONTROL 0x7
7146 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
7147 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
7148 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
7149 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
7150 #define GEN6_READ_OC_PARAMS 0xc
7151 #define GEN6_PCODE_READ_D_COMP 0x10
7152 #define GEN6_PCODE_WRITE_D_COMP 0x11
7153 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
7154 #define DISPLAY_IPS_CONTROL 0x19
7155 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
7156 #define GEN9_PCODE_SAGV_CONTROL 0x21
7157 #define GEN9_SAGV_DISABLE 0x0
7158 #define GEN9_SAGV_IS_DISABLED 0x1
7159 #define GEN9_SAGV_ENABLE 0x3
7160 #define GEN6_PCODE_DATA _MMIO(0x138128)
7161 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
7162 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
7163 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
7164
7165 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
7166 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
7167 #define GEN6_RCn_MASK 7
7168 #define GEN6_RC0 0
7169 #define GEN6_RC3 2
7170 #define GEN6_RC6 3
7171 #define GEN6_RC7 4
7172
7173 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
7174 #define GEN8_LSLICESTAT_MASK 0x7
7175
7176 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
7177 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
7178 #define CHV_SS_PG_ENABLE (1<<1)
7179 #define CHV_EU08_PG_ENABLE (1<<9)
7180 #define CHV_EU19_PG_ENABLE (1<<17)
7181 #define CHV_EU210_PG_ENABLE (1<<25)
7182
7183 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
7184 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
7185 #define CHV_EU311_PG_ENABLE (1<<1)
7186
7187 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
7188 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
7189 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
7190
7191 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
7192 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
7193 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
7194 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
7195 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
7196 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
7197 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
7198 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
7199 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
7200 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
7201
7202 #define GEN7_MISCCPCTL _MMIO(0x9424)
7203 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
7204 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
7205 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
7206 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
7207
7208 #define GEN8_GARBCNTL _MMIO(0xB004)
7209 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
7210
7211 /* IVYBRIDGE DPF */
7212 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
7213 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
7214 #define GEN7_PARITY_ERROR_VALID (1<<13)
7215 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
7216 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
7217 #define GEN7_PARITY_ERROR_ROW(reg) \
7218 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
7219 #define GEN7_PARITY_ERROR_BANK(reg) \
7220 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
7221 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
7222 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
7223 #define GEN7_L3CDERRST1_ENABLE (1<<7)
7224
7225 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
7226 #define GEN7_L3LOG_SIZE 0x80
7227
7228 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
7229 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
7230 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
7231 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
7232 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
7233 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
7234
7235 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
7236 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
7237 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
7238
7239 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
7240 #define FLOW_CONTROL_ENABLE (1<<15)
7241 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
7242 #define STALL_DOP_GATING_DISABLE (1<<5)
7243
7244 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
7245 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
7246 #define DOP_CLOCK_GATING_DISABLE (1<<0)
7247
7248 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
7249 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
7250
7251 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
7252 #define GEN8_ST_PO_DISABLE (1<<13)
7253
7254 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
7255 #define HSW_SAMPLE_C_PERFORMANCE (1<<9)
7256 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
7257 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
7258 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
7259
7260 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
7261 #define GEN9_ENABLE_YV12_BUGFIX (1<<4)
7262 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
7263
7264 /* Audio */
7265 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
7266 #define INTEL_AUDIO_DEVCL 0x808629FB
7267 #define INTEL_AUDIO_DEVBLC 0x80862801
7268 #define INTEL_AUDIO_DEVCTG 0x80862802
7269
7270 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
7271 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
7272 #define G4X_ELDV_DEVCTG (1 << 14)
7273 #define G4X_ELD_ADDR_MASK (0xf << 5)
7274 #define G4X_ELD_ACK (1 << 4)
7275 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
7276
7277 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
7278 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
7279 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
7280 _IBX_HDMIW_HDMIEDID_B)
7281 #define _IBX_AUD_CNTL_ST_A 0xE20B4
7282 #define _IBX_AUD_CNTL_ST_B 0xE21B4
7283 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
7284 _IBX_AUD_CNTL_ST_B)
7285 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
7286 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
7287 #define IBX_ELD_ACK (1 << 4)
7288 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
7289 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
7290 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
7291
7292 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
7293 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
7294 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
7295 #define _CPT_AUD_CNTL_ST_A 0xE50B4
7296 #define _CPT_AUD_CNTL_ST_B 0xE51B4
7297 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
7298 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
7299
7300 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7301 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
7302 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
7303 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7304 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
7305 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
7306 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
7307
7308 /* These are the 4 32-bit write offset registers for each stream
7309 * output buffer. It determines the offset from the
7310 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7311 */
7312 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
7313
7314 #define _IBX_AUD_CONFIG_A 0xe2000
7315 #define _IBX_AUD_CONFIG_B 0xe2100
7316 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
7317 #define _CPT_AUD_CONFIG_A 0xe5000
7318 #define _CPT_AUD_CONFIG_B 0xe5100
7319 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
7320 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7321 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
7322 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
7323
7324 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
7325 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
7326 #define AUD_CONFIG_UPPER_N_SHIFT 20
7327 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
7328 #define AUD_CONFIG_LOWER_N_SHIFT 4
7329 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
7330 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
7331 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
7332 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
7333 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
7334 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
7335 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
7336 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
7337 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
7338 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
7339 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
7340 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
7341 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
7342 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
7343
7344 /* HSW Audio */
7345 #define _HSW_AUD_CONFIG_A 0x65000
7346 #define _HSW_AUD_CONFIG_B 0x65100
7347 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
7348
7349 #define _HSW_AUD_MISC_CTRL_A 0x65010
7350 #define _HSW_AUD_MISC_CTRL_B 0x65110
7351 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
7352
7353 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7354 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7355 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
7356
7357 /* Audio Digital Converter */
7358 #define _HSW_AUD_DIG_CNVT_1 0x65080
7359 #define _HSW_AUD_DIG_CNVT_2 0x65180
7360 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
7361 #define DIP_PORT_SEL_MASK 0x3
7362
7363 #define _HSW_AUD_EDID_DATA_A 0x65050
7364 #define _HSW_AUD_EDID_DATA_B 0x65150
7365 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
7366
7367 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
7368 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
7369 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7370 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7371 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7372 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
7373
7374 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
7375 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7376
7377 /* HSW Power Wells */
7378 #define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */
7379 #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */
7380 #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */
7381 #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */
7382 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7383 #define HSW_PWR_WELL_STATE_ENABLED (1<<30)
7384 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
7385 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7386 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
7387 #define HSW_PWR_WELL_FORCE_ON (1<<19)
7388 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
7389
7390 /* SKL Fuse Status */
7391 #define SKL_FUSE_STATUS _MMIO(0x42000)
7392 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7393 #define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7394 #define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7395 #define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7396
7397 /* Per-pipe DDI Function Control */
7398 #define _TRANS_DDI_FUNC_CTL_A 0x60400
7399 #define _TRANS_DDI_FUNC_CTL_B 0x61400
7400 #define _TRANS_DDI_FUNC_CTL_C 0x62400
7401 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
7402 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
7403
7404 #define TRANS_DDI_FUNC_ENABLE (1<<31)
7405 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
7406 #define TRANS_DDI_PORT_MASK (7<<28)
7407 #define TRANS_DDI_PORT_SHIFT 28
7408 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7409 #define TRANS_DDI_PORT_NONE (0<<28)
7410 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7411 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7412 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7413 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7414 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7415 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7416 #define TRANS_DDI_BPC_MASK (7<<20)
7417 #define TRANS_DDI_BPC_8 (0<<20)
7418 #define TRANS_DDI_BPC_10 (1<<20)
7419 #define TRANS_DDI_BPC_6 (2<<20)
7420 #define TRANS_DDI_BPC_12 (3<<20)
7421 #define TRANS_DDI_PVSYNC (1<<17)
7422 #define TRANS_DDI_PHSYNC (1<<16)
7423 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7424 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7425 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7426 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7427 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
7428 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
7429 #define TRANS_DDI_BFI_ENABLE (1<<4)
7430
7431 /* DisplayPort Transport Control */
7432 #define _DP_TP_CTL_A 0x64040
7433 #define _DP_TP_CTL_B 0x64140
7434 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
7435 #define DP_TP_CTL_ENABLE (1<<31)
7436 #define DP_TP_CTL_MODE_SST (0<<27)
7437 #define DP_TP_CTL_MODE_MST (1<<27)
7438 #define DP_TP_CTL_FORCE_ACT (1<<25)
7439 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
7440 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
7441 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7442 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7443 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
7444 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7445 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
7446 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
7447 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
7448
7449 /* DisplayPort Transport Status */
7450 #define _DP_TP_STATUS_A 0x64044
7451 #define _DP_TP_STATUS_B 0x64144
7452 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
7453 #define DP_TP_STATUS_IDLE_DONE (1<<25)
7454 #define DP_TP_STATUS_ACT_SENT (1<<24)
7455 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7456 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7457 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7458 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7459 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
7460
7461 /* DDI Buffer Control */
7462 #define _DDI_BUF_CTL_A 0x64000
7463 #define _DDI_BUF_CTL_B 0x64100
7464 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
7465 #define DDI_BUF_CTL_ENABLE (1<<31)
7466 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
7467 #define DDI_BUF_EMP_MASK (0xf<<24)
7468 #define DDI_BUF_PORT_REVERSAL (1<<16)
7469 #define DDI_BUF_IS_IDLE (1<<7)
7470 #define DDI_A_4_LANES (1<<4)
7471 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
7472 #define DDI_PORT_WIDTH_MASK (7 << 1)
7473 #define DDI_PORT_WIDTH_SHIFT 1
7474 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
7475
7476 /* DDI Buffer Translations */
7477 #define _DDI_BUF_TRANS_A 0x64E00
7478 #define _DDI_BUF_TRANS_B 0x64E60
7479 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
7480 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
7481 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
7482
7483 /* Sideband Interface (SBI) is programmed indirectly, via
7484 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7485 * which contains the payload */
7486 #define SBI_ADDR _MMIO(0xC6000)
7487 #define SBI_DATA _MMIO(0xC6004)
7488 #define SBI_CTL_STAT _MMIO(0xC6008)
7489 #define SBI_CTL_DEST_ICLK (0x0<<16)
7490 #define SBI_CTL_DEST_MPHY (0x1<<16)
7491 #define SBI_CTL_OP_IORD (0x2<<8)
7492 #define SBI_CTL_OP_IOWR (0x3<<8)
7493 #define SBI_CTL_OP_CRRD (0x6<<8)
7494 #define SBI_CTL_OP_CRWR (0x7<<8)
7495 #define SBI_RESPONSE_FAIL (0x1<<1)
7496 #define SBI_RESPONSE_SUCCESS (0x0<<1)
7497 #define SBI_BUSY (0x1<<0)
7498 #define SBI_READY (0x0<<0)
7499
7500 /* SBI offsets */
7501 #define SBI_SSCDIVINTPHASE 0x0200
7502 #define SBI_SSCDIVINTPHASE6 0x0600
7503 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
7504 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
7505 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
7506 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
7507 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
7508 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
7509 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
7510 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
7511 #define SBI_SSCDITHPHASE 0x0204
7512 #define SBI_SSCCTL 0x020c
7513 #define SBI_SSCCTL6 0x060C
7514 #define SBI_SSCCTL_PATHALT (1<<3)
7515 #define SBI_SSCCTL_DISABLE (1<<0)
7516 #define SBI_SSCAUXDIV6 0x0610
7517 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
7518 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
7519 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
7520 #define SBI_DBUFF0 0x2a00
7521 #define SBI_GEN0 0x1f00
7522 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
7523
7524 /* LPT PIXCLK_GATE */
7525 #define PIXCLK_GATE _MMIO(0xC6020)
7526 #define PIXCLK_GATE_UNGATE (1<<0)
7527 #define PIXCLK_GATE_GATE (0<<0)
7528
7529 /* SPLL */
7530 #define SPLL_CTL _MMIO(0x46020)
7531 #define SPLL_PLL_ENABLE (1<<31)
7532 #define SPLL_PLL_SSC (1<<28)
7533 #define SPLL_PLL_NON_SSC (2<<28)
7534 #define SPLL_PLL_LCPLL (3<<28)
7535 #define SPLL_PLL_REF_MASK (3<<28)
7536 #define SPLL_PLL_FREQ_810MHz (0<<26)
7537 #define SPLL_PLL_FREQ_1350MHz (1<<26)
7538 #define SPLL_PLL_FREQ_2700MHz (2<<26)
7539 #define SPLL_PLL_FREQ_MASK (3<<26)
7540
7541 /* WRPLL */
7542 #define _WRPLL_CTL1 0x46040
7543 #define _WRPLL_CTL2 0x46060
7544 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
7545 #define WRPLL_PLL_ENABLE (1<<31)
7546 #define WRPLL_PLL_SSC (1<<28)
7547 #define WRPLL_PLL_NON_SSC (2<<28)
7548 #define WRPLL_PLL_LCPLL (3<<28)
7549 #define WRPLL_PLL_REF_MASK (3<<28)
7550 /* WRPLL divider programming */
7551 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
7552 #define WRPLL_DIVIDER_REF_MASK (0xff)
7553 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
7554 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7555 #define WRPLL_DIVIDER_POST_SHIFT 8
7556 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
7557 #define WRPLL_DIVIDER_FB_SHIFT 16
7558 #define WRPLL_DIVIDER_FB_MASK (0xff<<16)
7559
7560 /* Port clock selection */
7561 #define _PORT_CLK_SEL_A 0x46100
7562 #define _PORT_CLK_SEL_B 0x46104
7563 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
7564 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7565 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7566 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
7567 #define PORT_CLK_SEL_SPLL (3<<29)
7568 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
7569 #define PORT_CLK_SEL_WRPLL1 (4<<29)
7570 #define PORT_CLK_SEL_WRPLL2 (5<<29)
7571 #define PORT_CLK_SEL_NONE (7<<29)
7572 #define PORT_CLK_SEL_MASK (7<<29)
7573
7574 /* Transcoder clock selection */
7575 #define _TRANS_CLK_SEL_A 0x46140
7576 #define _TRANS_CLK_SEL_B 0x46144
7577 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
7578 /* For each transcoder, we need to select the corresponding port clock */
7579 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
7580 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
7581
7582 #define CDCLK_FREQ _MMIO(0x46200)
7583
7584 #define _TRANSA_MSA_MISC 0x60410
7585 #define _TRANSB_MSA_MISC 0x61410
7586 #define _TRANSC_MSA_MISC 0x62410
7587 #define _TRANS_EDP_MSA_MISC 0x6f410
7588 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
7589
7590 #define TRANS_MSA_SYNC_CLK (1<<0)
7591 #define TRANS_MSA_6_BPC (0<<5)
7592 #define TRANS_MSA_8_BPC (1<<5)
7593 #define TRANS_MSA_10_BPC (2<<5)
7594 #define TRANS_MSA_12_BPC (3<<5)
7595 #define TRANS_MSA_16_BPC (4<<5)
7596
7597 /* LCPLL Control */
7598 #define LCPLL_CTL _MMIO(0x130040)
7599 #define LCPLL_PLL_DISABLE (1<<31)
7600 #define LCPLL_PLL_LOCK (1<<30)
7601 #define LCPLL_CLK_FREQ_MASK (3<<26)
7602 #define LCPLL_CLK_FREQ_450 (0<<26)
7603 #define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7604 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7605 #define LCPLL_CLK_FREQ_675_BDW (3<<26)
7606 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
7607 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
7608 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
7609 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
7610 #define LCPLL_CD_SOURCE_FCLK (1<<21)
7611 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7612
7613 /*
7614 * SKL Clocks
7615 */
7616
7617 /* CDCLK_CTL */
7618 #define CDCLK_CTL _MMIO(0x46000)
7619 #define CDCLK_FREQ_SEL_MASK (3<<26)
7620 #define CDCLK_FREQ_450_432 (0<<26)
7621 #define CDCLK_FREQ_540 (1<<26)
7622 #define CDCLK_FREQ_337_308 (2<<26)
7623 #define CDCLK_FREQ_675_617 (3<<26)
7624 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7625 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7626 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7627 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7628 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
7629 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
7630 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
7631 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7632 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7633
7634 /* LCPLL_CTL */
7635 #define LCPLL1_CTL _MMIO(0x46010)
7636 #define LCPLL2_CTL _MMIO(0x46014)
7637 #define LCPLL_PLL_ENABLE (1<<31)
7638
7639 /* DPLL control1 */
7640 #define DPLL_CTRL1 _MMIO(0x6C058)
7641 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7642 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
7643 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7644 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7645 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
7646 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
7647 #define DPLL_CTRL1_LINK_RATE_2700 0
7648 #define DPLL_CTRL1_LINK_RATE_1350 1
7649 #define DPLL_CTRL1_LINK_RATE_810 2
7650 #define DPLL_CTRL1_LINK_RATE_1620 3
7651 #define DPLL_CTRL1_LINK_RATE_1080 4
7652 #define DPLL_CTRL1_LINK_RATE_2160 5
7653
7654 /* DPLL control2 */
7655 #define DPLL_CTRL2 _MMIO(0x6C05C)
7656 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
7657 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
7658 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
7659 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
7660 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7661
7662 /* DPLL Status */
7663 #define DPLL_STATUS _MMIO(0x6C060)
7664 #define DPLL_LOCK(id) (1<<((id)*8))
7665
7666 /* DPLL cfg */
7667 #define _DPLL1_CFGCR1 0x6C040
7668 #define _DPLL2_CFGCR1 0x6C048
7669 #define _DPLL3_CFGCR1 0x6C050
7670 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7671 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7672 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
7673 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7674
7675 #define _DPLL1_CFGCR2 0x6C044
7676 #define _DPLL2_CFGCR2 0x6C04C
7677 #define _DPLL3_CFGCR2 0x6C054
7678 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7679 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
7680 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
7681 #define DPLL_CFGCR2_KDIV_MASK (3<<5)
7682 #define DPLL_CFGCR2_KDIV(x) ((x)<<5)
7683 #define DPLL_CFGCR2_KDIV_5 (0<<5)
7684 #define DPLL_CFGCR2_KDIV_2 (1<<5)
7685 #define DPLL_CFGCR2_KDIV_3 (2<<5)
7686 #define DPLL_CFGCR2_KDIV_1 (3<<5)
7687 #define DPLL_CFGCR2_PDIV_MASK (7<<2)
7688 #define DPLL_CFGCR2_PDIV(x) ((x)<<2)
7689 #define DPLL_CFGCR2_PDIV_1 (0<<2)
7690 #define DPLL_CFGCR2_PDIV_2 (1<<2)
7691 #define DPLL_CFGCR2_PDIV_3 (2<<2)
7692 #define DPLL_CFGCR2_PDIV_7 (4<<2)
7693 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7694
7695 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7696 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7697
7698 /* BXT display engine PLL */
7699 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
7700 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7701 #define BXT_DE_PLL_RATIO_MASK 0xff
7702
7703 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
7704 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7705 #define BXT_DE_PLL_LOCK (1 << 30)
7706
7707 /* GEN9 DC */
7708 #define DC_STATE_EN _MMIO(0x45504)
7709 #define DC_STATE_DISABLE 0
7710 #define DC_STATE_EN_UPTO_DC5 (1<<0)
7711 #define DC_STATE_EN_DC9 (1<<3)
7712 #define DC_STATE_EN_UPTO_DC6 (2<<0)
7713 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7714
7715 #define DC_STATE_DEBUG _MMIO(0x45520)
7716 #define DC_STATE_DEBUG_MASK_CORES (1<<0)
7717 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7718
7719 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7720 * since on HSW we can't write to it using I915_WRITE. */
7721 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7722 #define D_COMP_BDW _MMIO(0x138144)
7723 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7724 #define D_COMP_COMP_FORCE (1<<8)
7725 #define D_COMP_COMP_DISABLE (1<<0)
7726
7727 /* Pipe WM_LINETIME - watermark line time */
7728 #define _PIPE_WM_LINETIME_A 0x45270
7729 #define _PIPE_WM_LINETIME_B 0x45274
7730 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
7731 #define PIPE_WM_LINETIME_MASK (0x1ff)
7732 #define PIPE_WM_LINETIME_TIME(x) ((x))
7733 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
7734 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
7735
7736 /* SFUSE_STRAP */
7737 #define SFUSE_STRAP _MMIO(0xc2014)
7738 #define SFUSE_STRAP_FUSE_LOCK (1<<13)
7739 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
7740 #define SFUSE_STRAP_CRT_DISABLED (1<<6)
7741 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7742 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7743 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
7744
7745 #define WM_MISC _MMIO(0x45260)
7746 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7747
7748 #define WM_DBG _MMIO(0x45280)
7749 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7750 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7751 #define WM_DBG_DISALLOW_SPRITE (1<<2)
7752
7753 /* pipe CSC */
7754 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7755 #define _PIPE_A_CSC_COEFF_BY 0x49014
7756 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7757 #define _PIPE_A_CSC_COEFF_BU 0x4901c
7758 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7759 #define _PIPE_A_CSC_COEFF_BV 0x49024
7760 #define _PIPE_A_CSC_MODE 0x49028
7761 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7762 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7763 #define CSC_MODE_YUV_TO_RGB (1 << 0)
7764 #define _PIPE_A_CSC_PREOFF_HI 0x49030
7765 #define _PIPE_A_CSC_PREOFF_ME 0x49034
7766 #define _PIPE_A_CSC_PREOFF_LO 0x49038
7767 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
7768 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
7769 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
7770
7771 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7772 #define _PIPE_B_CSC_COEFF_BY 0x49114
7773 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7774 #define _PIPE_B_CSC_COEFF_BU 0x4911c
7775 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7776 #define _PIPE_B_CSC_COEFF_BV 0x49124
7777 #define _PIPE_B_CSC_MODE 0x49128
7778 #define _PIPE_B_CSC_PREOFF_HI 0x49130
7779 #define _PIPE_B_CSC_PREOFF_ME 0x49134
7780 #define _PIPE_B_CSC_PREOFF_LO 0x49138
7781 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
7782 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
7783 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
7784
7785 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7786 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7787 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7788 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7789 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7790 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7791 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7792 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7793 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7794 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7795 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7796 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7797 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7798
7799 /* pipe degamma/gamma LUTs on IVB+ */
7800 #define _PAL_PREC_INDEX_A 0x4A400
7801 #define _PAL_PREC_INDEX_B 0x4AC00
7802 #define _PAL_PREC_INDEX_C 0x4B400
7803 #define PAL_PREC_10_12_BIT (0 << 31)
7804 #define PAL_PREC_SPLIT_MODE (1 << 31)
7805 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
7806 #define _PAL_PREC_DATA_A 0x4A404
7807 #define _PAL_PREC_DATA_B 0x4AC04
7808 #define _PAL_PREC_DATA_C 0x4B404
7809 #define _PAL_PREC_GC_MAX_A 0x4A410
7810 #define _PAL_PREC_GC_MAX_B 0x4AC10
7811 #define _PAL_PREC_GC_MAX_C 0x4B410
7812 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
7813 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
7814 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
7815
7816 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
7817 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
7818 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
7819 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
7820
7821 /* pipe CSC & degamma/gamma LUTs on CHV */
7822 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
7823 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
7824 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
7825 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
7826 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
7827 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
7828 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
7829 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
7830 #define CGM_PIPE_MODE_GAMMA (1 << 2)
7831 #define CGM_PIPE_MODE_CSC (1 << 1)
7832 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
7833
7834 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
7835 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
7836 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
7837 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
7838 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
7839 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
7840 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
7841 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
7842
7843 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
7844 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
7845 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
7846 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
7847 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
7848 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
7849 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
7850 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
7851
7852 /* MIPI DSI registers */
7853
7854 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
7855 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
7856
7857 /* BXT MIPI clock controls */
7858 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
7859
7860 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
7861 #define BXT_MIPI1_DIV_SHIFT 26
7862 #define BXT_MIPI2_DIV_SHIFT 10
7863 #define BXT_MIPI_DIV_SHIFT(port) \
7864 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7865 BXT_MIPI2_DIV_SHIFT)
7866
7867 /* TX control divider to select actual TX clock output from (8x/var) */
7868 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
7869 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
7870 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
7871 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7872 BXT_MIPI2_TX_ESCLK_SHIFT)
7873 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
7874 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
7875 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
7876 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
7877 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7878 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
7879 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
7880 /* RX upper control divider to select actual RX clock output from 8x */
7881 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
7882 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
7883 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
7884 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
7885 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
7886 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
7887 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
7888 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
7889 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
7890 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
7891 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
7892 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
7893 /* 8/3X divider to select the actual 8/3X clock output from 8x */
7894 #define BXT_MIPI1_8X_BY3_SHIFT 19
7895 #define BXT_MIPI2_8X_BY3_SHIFT 3
7896 #define BXT_MIPI_8X_BY3_SHIFT(port) \
7897 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
7898 BXT_MIPI2_8X_BY3_SHIFT)
7899 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
7900 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
7901 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
7902 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
7903 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
7904 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
7905 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
7906 /* RX lower control divider to select actual RX clock output from 8x */
7907 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
7908 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
7909 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
7910 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
7911 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
7912 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
7913 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
7914 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
7915 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
7916 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
7917 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
7918 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
7919
7920 #define RX_DIVIDER_BIT_1_2 0x3
7921 #define RX_DIVIDER_BIT_3_4 0xC
7922
7923 /* BXT MIPI mode configure */
7924 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
7925 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
7926 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
7927 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7928
7929 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
7930 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
7931 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
7932 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7933
7934 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
7935 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
7936 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
7937 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7938
7939 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
7940 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
7941 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7942 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7943 #define BXT_DSIC_16X_BY2 (1 << 10)
7944 #define BXT_DSIC_16X_BY3 (2 << 10)
7945 #define BXT_DSIC_16X_BY4 (3 << 10)
7946 #define BXT_DSIC_16X_MASK (3 << 10)
7947 #define BXT_DSIA_16X_BY2 (1 << 8)
7948 #define BXT_DSIA_16X_BY3 (2 << 8)
7949 #define BXT_DSIA_16X_BY4 (3 << 8)
7950 #define BXT_DSIA_16X_MASK (3 << 8)
7951 #define BXT_DSI_FREQ_SEL_SHIFT 8
7952 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
7953
7954 #define BXT_DSI_PLL_RATIO_MAX 0x7D
7955 #define BXT_DSI_PLL_RATIO_MIN 0x22
7956 #define BXT_DSI_PLL_RATIO_MASK 0xFF
7957 #define BXT_REF_CLOCK_KHZ 19200
7958
7959 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
7960 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
7961 #define BXT_DSI_PLL_LOCKED (1 << 30)
7962
7963 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
7964 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7965 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7966
7967 /* BXT port control */
7968 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
7969 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
7970 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
7971
7972 #define DPI_ENABLE (1 << 31) /* A + C */
7973 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7974 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
7975 #define DUAL_LINK_MODE_SHIFT 26
7976 #define DUAL_LINK_MODE_MASK (1 << 26)
7977 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7978 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
7979 #define DITHERING_ENABLE (1 << 25) /* A + C */
7980 #define FLOPPED_HSTX (1 << 23)
7981 #define DE_INVERT (1 << 19) /* XXX */
7982 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7983 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7984 #define AFE_LATCHOUT (1 << 17)
7985 #define LP_OUTPUT_HOLD (1 << 16)
7986 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7987 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7988 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7989 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
7990 #define CSB_SHIFT 9
7991 #define CSB_MASK (3 << 9)
7992 #define CSB_20MHZ (0 << 9)
7993 #define CSB_10MHZ (1 << 9)
7994 #define CSB_40MHZ (2 << 9)
7995 #define BANDGAP_MASK (1 << 8)
7996 #define BANDGAP_PNW_CIRCUIT (0 << 8)
7997 #define BANDGAP_LNC_CIRCUIT (1 << 8)
7998 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7999 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
8000 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
8001 #define TEARING_EFFECT_SHIFT 2 /* A + C */
8002 #define TEARING_EFFECT_MASK (3 << 2)
8003 #define TEARING_EFFECT_OFF (0 << 2)
8004 #define TEARING_EFFECT_DSI (1 << 2)
8005 #define TEARING_EFFECT_GPIO (2 << 2)
8006 #define LANE_CONFIGURATION_SHIFT 0
8007 #define LANE_CONFIGURATION_MASK (3 << 0)
8008 #define LANE_CONFIGURATION_4LANE (0 << 0)
8009 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
8010 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
8011
8012 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
8013 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
8014 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
8015 #define TEARING_EFFECT_DELAY_SHIFT 0
8016 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
8017
8018 /* XXX: all bits reserved */
8019 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
8020
8021 /* MIPI DSI Controller and D-PHY registers */
8022
8023 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
8024 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
8025 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
8026 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
8027 #define ULPS_STATE_MASK (3 << 1)
8028 #define ULPS_STATE_ENTER (2 << 1)
8029 #define ULPS_STATE_EXIT (1 << 1)
8030 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
8031 #define DEVICE_READY (1 << 0)
8032
8033 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
8034 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
8035 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
8036 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
8037 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
8038 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
8039 #define TEARING_EFFECT (1 << 31)
8040 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
8041 #define GEN_READ_DATA_AVAIL (1 << 29)
8042 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
8043 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
8044 #define RX_PROT_VIOLATION (1 << 26)
8045 #define RX_INVALID_TX_LENGTH (1 << 25)
8046 #define ACK_WITH_NO_ERROR (1 << 24)
8047 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
8048 #define LP_RX_TIMEOUT (1 << 22)
8049 #define HS_TX_TIMEOUT (1 << 21)
8050 #define DPI_FIFO_UNDERRUN (1 << 20)
8051 #define LOW_CONTENTION (1 << 19)
8052 #define HIGH_CONTENTION (1 << 18)
8053 #define TXDSI_VC_ID_INVALID (1 << 17)
8054 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
8055 #define TXCHECKSUM_ERROR (1 << 15)
8056 #define TXECC_MULTIBIT_ERROR (1 << 14)
8057 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
8058 #define TXFALSE_CONTROL_ERROR (1 << 12)
8059 #define RXDSI_VC_ID_INVALID (1 << 11)
8060 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
8061 #define RXCHECKSUM_ERROR (1 << 9)
8062 #define RXECC_MULTIBIT_ERROR (1 << 8)
8063 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
8064 #define RXFALSE_CONTROL_ERROR (1 << 6)
8065 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
8066 #define RX_LP_TX_SYNC_ERROR (1 << 4)
8067 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
8068 #define RXEOT_SYNC_ERROR (1 << 2)
8069 #define RXSOT_SYNC_ERROR (1 << 1)
8070 #define RXSOT_ERROR (1 << 0)
8071
8072 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
8073 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
8074 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
8075 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
8076 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
8077 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
8078 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
8079 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
8080 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
8081 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
8082 #define VID_MODE_FORMAT_MASK (0xf << 7)
8083 #define VID_MODE_NOT_SUPPORTED (0 << 7)
8084 #define VID_MODE_FORMAT_RGB565 (1 << 7)
8085 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
8086 #define VID_MODE_FORMAT_RGB666 (3 << 7)
8087 #define VID_MODE_FORMAT_RGB888 (4 << 7)
8088 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
8089 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
8090 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
8091 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
8092 #define DATA_LANES_PRG_REG_SHIFT 0
8093 #define DATA_LANES_PRG_REG_MASK (7 << 0)
8094
8095 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
8096 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
8097 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
8098 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
8099
8100 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
8101 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
8102 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
8103 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
8104
8105 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
8106 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
8107 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
8108 #define TURN_AROUND_TIMEOUT_MASK 0x3f
8109
8110 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
8111 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
8112 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
8113 #define DEVICE_RESET_TIMER_MASK 0xffff
8114
8115 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
8116 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
8117 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
8118 #define VERTICAL_ADDRESS_SHIFT 16
8119 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
8120 #define HORIZONTAL_ADDRESS_SHIFT 0
8121 #define HORIZONTAL_ADDRESS_MASK 0xffff
8122
8123 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
8124 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
8125 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
8126 #define DBI_FIFO_EMPTY_HALF (0 << 0)
8127 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
8128 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
8129
8130 /* regs below are bits 15:0 */
8131 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
8132 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
8133 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
8134
8135 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
8136 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
8137 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
8138
8139 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
8140 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
8141 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
8142
8143 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
8144 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
8145 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
8146
8147 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
8148 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
8149 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
8150
8151 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
8152 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
8153 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
8154
8155 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
8156 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
8157 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
8158
8159 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
8160 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
8161 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
8162
8163 /* regs above are bits 15:0 */
8164
8165 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
8166 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
8167 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
8168 #define DPI_LP_MODE (1 << 6)
8169 #define BACKLIGHT_OFF (1 << 5)
8170 #define BACKLIGHT_ON (1 << 4)
8171 #define COLOR_MODE_OFF (1 << 3)
8172 #define COLOR_MODE_ON (1 << 2)
8173 #define TURN_ON (1 << 1)
8174 #define SHUTDOWN (1 << 0)
8175
8176 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
8177 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
8178 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
8179 #define COMMAND_BYTE_SHIFT 0
8180 #define COMMAND_BYTE_MASK (0x3f << 0)
8181
8182 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
8183 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
8184 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
8185 #define MASTER_INIT_TIMER_SHIFT 0
8186 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
8187
8188 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
8189 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
8190 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
8191 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
8192 #define MAX_RETURN_PKT_SIZE_SHIFT 0
8193 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
8194
8195 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
8196 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
8197 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
8198 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
8199 #define DISABLE_VIDEO_BTA (1 << 3)
8200 #define IP_TG_CONFIG (1 << 2)
8201 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
8202 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
8203 #define VIDEO_MODE_BURST (3 << 0)
8204
8205 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
8206 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
8207 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
8208 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
8209 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
8210 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
8211 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
8212 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
8213 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
8214 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
8215 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
8216 #define CLOCKSTOP (1 << 1)
8217 #define EOT_DISABLE (1 << 0)
8218
8219 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
8220 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
8221 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
8222 #define LP_BYTECLK_SHIFT 0
8223 #define LP_BYTECLK_MASK (0xffff << 0)
8224
8225 /* bits 31:0 */
8226 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
8227 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
8228 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
8229
8230 /* bits 31:0 */
8231 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
8232 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
8233 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
8234
8235 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
8236 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
8237 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
8238 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
8239 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
8240 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
8241 #define LONG_PACKET_WORD_COUNT_SHIFT 8
8242 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
8243 #define SHORT_PACKET_PARAM_SHIFT 8
8244 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
8245 #define VIRTUAL_CHANNEL_SHIFT 6
8246 #define VIRTUAL_CHANNEL_MASK (3 << 6)
8247 #define DATA_TYPE_SHIFT 0
8248 #define DATA_TYPE_MASK (0x3f << 0)
8249 /* data type values, see include/video/mipi_display.h */
8250
8251 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
8252 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
8253 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
8254 #define DPI_FIFO_EMPTY (1 << 28)
8255 #define DBI_FIFO_EMPTY (1 << 27)
8256 #define LP_CTRL_FIFO_EMPTY (1 << 26)
8257 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
8258 #define LP_CTRL_FIFO_FULL (1 << 24)
8259 #define HS_CTRL_FIFO_EMPTY (1 << 18)
8260 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
8261 #define HS_CTRL_FIFO_FULL (1 << 16)
8262 #define LP_DATA_FIFO_EMPTY (1 << 10)
8263 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
8264 #define LP_DATA_FIFO_FULL (1 << 8)
8265 #define HS_DATA_FIFO_EMPTY (1 << 2)
8266 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
8267 #define HS_DATA_FIFO_FULL (1 << 0)
8268
8269 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
8270 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
8271 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
8272 #define DBI_HS_LP_MODE_MASK (1 << 0)
8273 #define DBI_LP_MODE (1 << 0)
8274 #define DBI_HS_MODE (0 << 0)
8275
8276 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
8277 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
8278 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
8279 #define EXIT_ZERO_COUNT_SHIFT 24
8280 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
8281 #define TRAIL_COUNT_SHIFT 16
8282 #define TRAIL_COUNT_MASK (0x1f << 16)
8283 #define CLK_ZERO_COUNT_SHIFT 8
8284 #define CLK_ZERO_COUNT_MASK (0xff << 8)
8285 #define PREPARE_COUNT_SHIFT 0
8286 #define PREPARE_COUNT_MASK (0x3f << 0)
8287
8288 /* bits 31:0 */
8289 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
8290 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
8291 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
8292
8293 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
8294 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
8295 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
8296 #define LP_HS_SSW_CNT_SHIFT 16
8297 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
8298 #define HS_LP_PWR_SW_CNT_SHIFT 0
8299 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
8300
8301 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
8302 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
8303 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
8304 #define STOP_STATE_STALL_COUNTER_SHIFT 0
8305 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
8306
8307 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
8308 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
8309 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
8310 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
8311 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
8312 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
8313 #define RX_CONTENTION_DETECTED (1 << 0)
8314
8315 /* XXX: only pipe A ?!? */
8316 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
8317 #define DBI_TYPEC_ENABLE (1 << 31)
8318 #define DBI_TYPEC_WIP (1 << 30)
8319 #define DBI_TYPEC_OPTION_SHIFT 28
8320 #define DBI_TYPEC_OPTION_MASK (3 << 28)
8321 #define DBI_TYPEC_FREQ_SHIFT 24
8322 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
8323 #define DBI_TYPEC_OVERRIDE (1 << 8)
8324 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
8325 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
8326
8327
8328 /* MIPI adapter registers */
8329
8330 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
8331 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
8332 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
8333 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
8334 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
8335 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
8336 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
8337 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
8338 #define READ_REQUEST_PRIORITY_SHIFT 3
8339 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
8340 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
8341 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
8342 #define RGB_FLIP_TO_BGR (1 << 2)
8343
8344 #define BXT_PIPE_SELECT_SHIFT 7
8345 #define BXT_PIPE_SELECT_MASK (7 << 7)
8346 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
8347
8348 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
8349 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
8350 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
8351 #define DATA_MEM_ADDRESS_SHIFT 5
8352 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
8353 #define DATA_VALID (1 << 0)
8354
8355 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
8356 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
8357 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
8358 #define DATA_LENGTH_SHIFT 0
8359 #define DATA_LENGTH_MASK (0xfffff << 0)
8360
8361 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
8362 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
8363 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
8364 #define COMMAND_MEM_ADDRESS_SHIFT 5
8365 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
8366 #define AUTO_PWG_ENABLE (1 << 2)
8367 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
8368 #define COMMAND_VALID (1 << 0)
8369
8370 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
8371 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
8372 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
8373 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
8374 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
8375
8376 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
8377 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
8378 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
8379
8380 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
8381 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
8382 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
8383 #define READ_DATA_VALID(n) (1 << (n))
8384
8385 /* For UMS only (deprecated): */
8386 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8387 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
8388
8389 /* MOCS (Memory Object Control State) registers */
8390 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
8391
8392 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
8393 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
8394 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
8395 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
8396 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
8397
8398 /* gamt regs */
8399 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
8400 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
8401 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
8402 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
8403 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
8404
8405 #endif /* _I915_REG_H_ */
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