drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/component.h>
  26 #include <drm/i915_component.h>
  27 #include "intel_drv.h"
  28
  29 #include <drm/drmP.h>
  30 #include <drm/drm_edid.h>
  31 #include "i915_drv.h"
  32
  33 /**
  34  * DOC: High Definition Audio over HDMI and Display Port
  35  *
  36  * The graphics and audio drivers together support High Definition Audio over
  37  * HDMI and Display Port. The audio programming sequences are divided into audio
  38  * codec and controller enable and disable sequences. The graphics driver
  39  * handles the audio codec sequences, while the audio driver handles the audio
  40  * controller sequences.
  41  *
  42  * The disable sequences must be performed before disabling the transcoder or
  43  * port. The enable sequences may only be performed after enabling the
  44  * transcoder and port, and after completed link training. Therefore the audio
  45  * enable/disable sequences are part of the modeset sequence.
  46  *
  47  * The codec and controller sequences could be done either parallel or serial,
  48  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  49  * driver that the controller sequence should start. Indeed, most of the
  50  * co-operation between the graphics and audio drivers is handled via audio
  51  * related registers. (The notable exception is the power management, not
  52  * covered here.)
  53  *
  54  * The struct i915_audio_component is used to interact between the graphics
  55  * and audio drivers. The struct i915_audio_component_ops *ops in it is
  56  * defined in graphics driver and called in audio driver. The
  57  * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver.
  58  */
  59
  60 static const struct {
  61         int clock;
  62         u32 config;
  63 } hdmi_audio_clock[] = {
  64         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  65         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  66         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  67         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  68         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  69         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  70         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  71         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  72         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  73         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  74 };
  75
  76 /* HDMI N/CTS table */
  77 #define TMDS_297M 297000
  78 #define TMDS_296M 296703
  79 static const struct {
  80         int sample_rate;
  81         int clock;
  82         int n;
  83         int cts;
  84 } aud_ncts[] = {
  85         { 44100, TMDS_296M, 4459, 234375 },
  86         { 44100, TMDS_297M, 4704, 247500 },
  87         { 48000, TMDS_296M, 5824, 281250 },
  88         { 48000, TMDS_297M, 5120, 247500 },
  89         { 32000, TMDS_296M, 5824, 421875 },
  90         { 32000, TMDS_297M, 3072, 222750 },
  91         { 88200, TMDS_296M, 8918, 234375 },
  92         { 88200, TMDS_297M, 9408, 247500 },
  93         { 96000, TMDS_296M, 11648, 281250 },
  94         { 96000, TMDS_297M, 10240, 247500 },
  95         { 176400, TMDS_296M, 17836, 234375 },
  96         { 176400, TMDS_297M, 18816, 247500 },
  97         { 192000, TMDS_296M, 23296, 281250 },
  98         { 192000, TMDS_297M, 20480, 247500 },
  99 };
 100
 101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 102 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
 103 {
 104         int i;
 105
 106         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 107                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 108                         break;
 109         }
 110
 111         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 112                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 113                               adjusted_mode->crtc_clock);
 114                 i = 1;
 115         }
 116
 117         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 118                       hdmi_audio_clock[i].clock,
 119                       hdmi_audio_clock[i].config);
 120
 121         return hdmi_audio_clock[i].config;
 122 }
 123
 124 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
 125 {
 126         int i;
 127
 128         for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
 129                 if ((rate == aud_ncts[i].sample_rate) &&
 130                         (mode->clock == aud_ncts[i].clock)) {
 131                         return aud_ncts[i].n;
 132                 }
 133         }
 134         return 0;
 135 }
 136
 137 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
 138 {
 139         int n_low, n_up;
 140         uint32_t tmp = val;
 141
 142         n_low = n & 0xfff;
 143         n_up = (n >> 12) & 0xff;
 144         tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
 145         tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
 146                         (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
 147                         AUD_CONFIG_N_PROG_ENABLE);
 148         return tmp;
 149 }
 150
 151 /* check whether N/CTS/M need be set manually */
 152 static bool audio_rate_need_prog(struct intel_crtc *crtc,
 153                                  const struct drm_display_mode *mode)
 154 {
 155         if (((mode->clock == TMDS_297M) ||
 156                  (mode->clock == TMDS_296M)) &&
 157                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 158                 return true;
 159         else
 160                 return false;
 161 }
 162
 163 static bool intel_eld_uptodate(struct drm_connector *connector,
 164                                i915_reg_t reg_eldv, uint32_t bits_eldv,
 165                                i915_reg_t reg_elda, uint32_t bits_elda,
 166                                i915_reg_t reg_edid)
 167 {
 168         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 169         uint8_t *eld = connector->eld;
 170         uint32_t tmp;
 171         int i;
 172
 173         tmp = I915_READ(reg_eldv);
 174         tmp &= bits_eldv;
 175
 176         if (!tmp)
 177                 return false;
 178
 179         tmp = I915_READ(reg_elda);
 180         tmp &= ~bits_elda;
 181         I915_WRITE(reg_elda, tmp);
 182
 183         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 184                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
 185                         return false;
 186
 187         return true;
 188 }
 189
 190 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
 191 {
 192         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 193         uint32_t eldv, tmp;
 194
 195         DRM_DEBUG_KMS("Disable audio codec\n");
 196
 197         tmp = I915_READ(G4X_AUD_VID_DID);
 198         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 199                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 200         else
 201                 eldv = G4X_ELDV_DEVCTG;
 202
 203         /* Invalidate ELD */
 204         tmp = I915_READ(G4X_AUD_CNTL_ST);
 205         tmp &= ~eldv;
 206         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 207 }
 208
 209 static void g4x_audio_codec_enable(struct drm_connector *connector,
 210                                    struct intel_encoder *encoder,
 211                                    const struct drm_display_mode *adjusted_mode)
 212 {
 213         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 214         uint8_t *eld = connector->eld;
 215         uint32_t eldv;
 216         uint32_t tmp;
 217         int len, i;
 218
 219         DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
 220
 221         tmp = I915_READ(G4X_AUD_VID_DID);
 222         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 223                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 224         else
 225                 eldv = G4X_ELDV_DEVCTG;
 226
 227         if (intel_eld_uptodate(connector,
 228                                G4X_AUD_CNTL_ST, eldv,
 229                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 230                                G4X_HDMIW_HDMIEDID))
 231                 return;
 232
 233         tmp = I915_READ(G4X_AUD_CNTL_ST);
 234         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 235         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 236         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 237
 238         len = min(drm_eld_size(eld) / 4, len);
 239         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 240         for (i = 0; i < len; i++)
 241                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 242
 243         tmp = I915_READ(G4X_AUD_CNTL_ST);
 244         tmp |= eldv;
 245         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 246 }
 247
 248 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
 249 {
 250         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 251         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 252         enum pipe pipe = intel_crtc->pipe;
 253         uint32_t tmp;
 254
 255         DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
 256
 257         mutex_lock(&dev_priv->av_mutex);
 258
 259         /* Disable timestamps */
 260         tmp = I915_READ(HSW_AUD_CFG(pipe));
 261         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 262         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 263         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 264         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 265         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 266             intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
 267                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 268         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 269
 270         /* Invalidate ELD */
 271         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 272         tmp &= ~AUDIO_ELD_VALID(pipe);
 273         tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
 274         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 275
 276         mutex_unlock(&dev_priv->av_mutex);
 277 }
 278
 279 static void hsw_audio_codec_enable(struct drm_connector *connector,
 280                                    struct intel_encoder *encoder,
 281                                    const struct drm_display_mode *adjusted_mode)
 282 {
 283         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 285         enum pipe pipe = intel_crtc->pipe;
 286         struct i915_audio_component *acomp = dev_priv->audio_component;
 287         const uint8_t *eld = connector->eld;
 288         struct intel_digital_port *intel_dig_port =
 289                 enc_to_dig_port(&encoder->base);
 290         enum port port = intel_dig_port->port;
 291         uint32_t tmp;
 292         int len, i;
 293         int n, rate;
 294
 295         DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
 296                       pipe_name(pipe), drm_eld_size(eld));
 297
 298         mutex_lock(&dev_priv->av_mutex);
 299
 300         /* Enable audio presence detect, invalidate ELD */
 301         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 302         tmp |= AUDIO_OUTPUT_ENABLE(pipe);
 303         tmp &= ~AUDIO_ELD_VALID(pipe);
 304         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 305
 306         /*
 307          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 308          * disabled during the mode set. The proper fix would be to push the
 309          * rest of the setup into a vblank work item, queued here, but the
 310          * infrastructure is not there yet.
 311          */
 312
 313         /* Reset ELD write address */
 314         tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
 315         tmp &= ~IBX_ELD_ADDRESS_MASK;
 316         I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
 317
 318         /* Up to 84 bytes of hw ELD buffer */
 319         len = min(drm_eld_size(eld), 84);
 320         for (i = 0; i < len / 4; i++)
 321                 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
 322
 323         /* ELD valid */
 324         tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
 325         tmp |= AUDIO_ELD_VALID(pipe);
 326         I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
 327
 328         /* Enable timestamps */
 329         tmp = I915_READ(HSW_AUD_CFG(pipe));
 330         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 331         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 332         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 333                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 334         else
 335                 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
 336
 337         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 338         if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
 339                 if (!acomp)
 340                         rate = 0;
 341                 else if (port >= PORT_A && port <= PORT_E)
 342                         rate = acomp->aud_sample_rate[port];
 343                 else {
 344                         DRM_ERROR("invalid port: %d\n", port);
 345                         rate = 0;
 346                 }
 347                 n = audio_config_get_n(adjusted_mode, rate);
 348                 if (n != 0)
 349                         tmp = audio_config_setup_n_reg(n, tmp);
 350                 else
 351                         DRM_DEBUG_KMS("no suitable N value is found\n");
 352         }
 353
 354         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 355
 356         mutex_unlock(&dev_priv->av_mutex);
 357 }
 358
 359 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
 360 {
 361         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 362         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 363         struct intel_digital_port *intel_dig_port =
 364                 enc_to_dig_port(&encoder->base);
 365         enum port port = intel_dig_port->port;
 366         enum pipe pipe = intel_crtc->pipe;
 367         uint32_t tmp, eldv;
 368         i915_reg_t aud_config, aud_cntrl_st2;
 369
 370         DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
 371                       port_name(port), pipe_name(pipe));
 372
 373         if (WARN_ON(port == PORT_A))
 374                 return;
 375
 376         if (HAS_PCH_IBX(dev_priv->dev)) {
 377                 aud_config = IBX_AUD_CFG(pipe);
 378                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 379         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 380                 aud_config = VLV_AUD_CFG(pipe);
 381                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 382         } else {
 383                 aud_config = CPT_AUD_CFG(pipe);
 384                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 385         }
 386
 387         /* Disable timestamps */
 388         tmp = I915_READ(aud_config);
 389         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 390         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 391         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 392         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 393         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 394                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 395         I915_WRITE(aud_config, tmp);
 396
 397         eldv = IBX_ELD_VALID(port);
 398
 399         /* Invalidate ELD */
 400         tmp = I915_READ(aud_cntrl_st2);
 401         tmp &= ~eldv;
 402         I915_WRITE(aud_cntrl_st2, tmp);
 403 }
 404
 405 static void ilk_audio_codec_enable(struct drm_connector *connector,
 406                                    struct intel_encoder *encoder,
 407                                    const struct drm_display_mode *adjusted_mode)
 408 {
 409         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 410         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 411         struct intel_digital_port *intel_dig_port =
 412                 enc_to_dig_port(&encoder->base);
 413         enum port port = intel_dig_port->port;
 414         enum pipe pipe = intel_crtc->pipe;
 415         uint8_t *eld = connector->eld;
 416         uint32_t eldv;
 417         uint32_t tmp;
 418         int len, i;
 419         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 420
 421         DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
 422                       port_name(port), pipe_name(pipe), drm_eld_size(eld));
 423
 424         if (WARN_ON(port == PORT_A))
 425                 return;
 426
 427         /*
 428          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 429          * disabled during the mode set. The proper fix would be to push the
 430          * rest of the setup into a vblank work item, queued here, but the
 431          * infrastructure is not there yet.
 432          */
 433
 434         if (HAS_PCH_IBX(connector->dev)) {
 435                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 436                 aud_config = IBX_AUD_CFG(pipe);
 437                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 438                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 439         } else if (IS_VALLEYVIEW(connector->dev) ||
 440                    IS_CHERRYVIEW(connector->dev)) {
 441                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 442                 aud_config = VLV_AUD_CFG(pipe);
 443                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 444                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 445         } else {
 446                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 447                 aud_config = CPT_AUD_CFG(pipe);
 448                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 449                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 450         }
 451
 452         eldv = IBX_ELD_VALID(port);
 453
 454         /* Invalidate ELD */
 455         tmp = I915_READ(aud_cntrl_st2);
 456         tmp &= ~eldv;
 457         I915_WRITE(aud_cntrl_st2, tmp);
 458
 459         /* Reset ELD write address */
 460         tmp = I915_READ(aud_cntl_st);
 461         tmp &= ~IBX_ELD_ADDRESS_MASK;
 462         I915_WRITE(aud_cntl_st, tmp);
 463
 464         /* Up to 84 bytes of hw ELD buffer */
 465         len = min(drm_eld_size(eld), 84);
 466         for (i = 0; i < len / 4; i++)
 467                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 468
 469         /* ELD valid */
 470         tmp = I915_READ(aud_cntrl_st2);
 471         tmp |= eldv;
 472         I915_WRITE(aud_cntrl_st2, tmp);
 473
 474         /* Enable timestamps */
 475         tmp = I915_READ(aud_config);
 476         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 477         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 478         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 479         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 480             intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
 481                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 482         else
 483                 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
 484         I915_WRITE(aud_config, tmp);
 485 }
 486
 487 /**
 488  * intel_audio_codec_enable - Enable the audio codec for HD audio
 489  * @intel_encoder: encoder on which to enable audio
 490  *
 491  * The enable sequences may only be performed after enabling the transcoder and
 492  * port, and after completed link training.
 493  */
 494 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
 495 {
 496         struct drm_encoder *encoder = &intel_encoder->base;
 497         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 498         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 499         struct drm_connector *connector;
 500         struct drm_device *dev = encoder->dev;
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         struct i915_audio_component *acomp = dev_priv->audio_component;
 503         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 504         enum port port = intel_dig_port->port;
 505
 506         connector = drm_select_eld(encoder);
 507         if (!connector)
 508                 return;
 509
 510         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 511                          connector->base.id,
 512                          connector->name,
 513                          connector->encoder->base.id,
 514                          connector->encoder->name);
 515
 516         /* ELD Conn_Type */
 517         connector->eld[5] &= ~(3 << 2);
 518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 519             intel_pipe_has_type(crtc, INTEL_OUTPUT_DP_MST))
 520                 connector->eld[5] |= (1 << 2);
 521
 522         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 523
 524         if (dev_priv->display.audio_codec_enable)
 525                 dev_priv->display.audio_codec_enable(connector, intel_encoder,
 526                                                      adjusted_mode);
 527
 528         mutex_lock(&dev_priv->av_mutex);
 529         intel_dig_port->audio_connector = connector;
 530         /* referred in audio callbacks */
 531         dev_priv->dig_port_map[port] = intel_encoder;
 532         mutex_unlock(&dev_priv->av_mutex);
 533
 534         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 535                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 536 }
 537
 538 /**
 539  * intel_audio_codec_disable - Disable the audio codec for HD audio
 540  * @intel_encoder: encoder on which to disable audio
 541  *
 542  * The disable sequences must be performed before disabling the transcoder or
 543  * port.
 544  */
 545 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
 546 {
 547         struct drm_encoder *encoder = &intel_encoder->base;
 548         struct drm_device *dev = encoder->dev;
 549         struct drm_i915_private *dev_priv = dev->dev_private;
 550         struct i915_audio_component *acomp = dev_priv->audio_component;
 551         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 552         enum port port = intel_dig_port->port;
 553
 554         if (dev_priv->display.audio_codec_disable)
 555                 dev_priv->display.audio_codec_disable(intel_encoder);
 556
 557         mutex_lock(&dev_priv->av_mutex);
 558         intel_dig_port->audio_connector = NULL;
 559         dev_priv->dig_port_map[port] = NULL;
 560         mutex_unlock(&dev_priv->av_mutex);
 561
 562         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 563                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
 564 }
 565
 566 /**
 567  * intel_init_audio - Set up chip specific audio functions
 568  * @dev: drm device
 569  */
 570 void intel_init_audio(struct drm_device *dev)
 571 {
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573
 574         if (IS_G4X(dev)) {
 575                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 576                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 577         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 578                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 579                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 580         } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
 581                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 582                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 583         } else if (HAS_PCH_SPLIT(dev)) {
 584                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 585                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 586         }
 587 }
 588
 589 static void i915_audio_component_get_power(struct device *dev)
 590 {
 591         intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 592 }
 593
 594 static void i915_audio_component_put_power(struct device *dev)
 595 {
 596         intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 597 }
 598
 599 static void i915_audio_component_codec_wake_override(struct device *dev,
 600                                                      bool enable)
 601 {
 602         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 603         u32 tmp;
 604
 605         if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
 606                 return;
 607
 608         /*
 609          * Enable/disable generating the codec wake signal, overriding the
 610          * internal logic to generate the codec wake to controller.
 611          */
 612         tmp = I915_READ(HSW_AUD_CHICKENBIT);
 613         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
 614         I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 615         usleep_range(1000, 1500);
 616
 617         if (enable) {
 618                 tmp = I915_READ(HSW_AUD_CHICKENBIT);
 619                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
 620                 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
 621                 usleep_range(1000, 1500);
 622         }
 623 }
 624
 625 /* Get CDCLK in kHz  */
 626 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 627 {
 628         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 629         int ret;
 630
 631         if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
 632                 return -ENODEV;
 633
 634         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
 635         ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
 636
 637         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
 638
 639         return ret;
 640 }
 641
 642 static int i915_audio_component_sync_audio_rate(struct device *dev,
 643                                                 int port, int rate)
 644 {
 645         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 646         struct intel_encoder *intel_encoder;
 647         struct intel_crtc *crtc;
 648         struct drm_display_mode *mode;
 649         struct i915_audio_component *acomp = dev_priv->audio_component;
 650         enum pipe pipe = INVALID_PIPE;
 651         u32 tmp;
 652         int n;
 653         int err = 0;
 654
 655         /* HSW, BDW, SKL, KBL need this fix */
 656         if (!IS_SKYLAKE(dev_priv) &&
 657             !IS_KABYLAKE(dev_priv) &&
 658             !IS_BROADWELL(dev_priv) &&
 659             !IS_HASWELL(dev_priv))
 660                 return 0;
 661
 662         mutex_lock(&dev_priv->av_mutex);
 663         /* 1. get the pipe */
 664         intel_encoder = dev_priv->dig_port_map[port];
 665         /* intel_encoder might be NULL for DP MST */
 666         if (!intel_encoder || !intel_encoder->base.crtc ||
 667             intel_encoder->type != INTEL_OUTPUT_HDMI) {
 668                 DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
 669                 err = -ENODEV;
 670                 goto unlock;
 671         }
 672         crtc = to_intel_crtc(intel_encoder->base.crtc);
 673         pipe = crtc->pipe;
 674         if (pipe == INVALID_PIPE) {
 675                 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
 676                 err = -ENODEV;
 677                 goto unlock;
 678         }
 679
 680         DRM_DEBUG_KMS("pipe %c connects port %c\n",
 681                                   pipe_name(pipe), port_name(port));
 682         mode = &crtc->config->base.adjusted_mode;
 683
 684         /* port must be valid now, otherwise the pipe will be invalid */
 685         acomp->aud_sample_rate[port] = rate;
 686
 687         /* 2. check whether to set the N/CTS/M manually or not */
 688         if (!audio_rate_need_prog(crtc, mode)) {
 689                 tmp = I915_READ(HSW_AUD_CFG(pipe));
 690                 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 691                 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 692                 goto unlock;
 693         }
 694
 695         n = audio_config_get_n(mode, rate);
 696         if (n == 0) {
 697                 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
 698                                           port_name(port));
 699                 tmp = I915_READ(HSW_AUD_CFG(pipe));
 700                 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 701                 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 702                 goto unlock;
 703         }
 704
 705         /* 3. set the N/CTS/M */
 706         tmp = I915_READ(HSW_AUD_CFG(pipe));
 707         tmp = audio_config_setup_n_reg(n, tmp);
 708         I915_WRITE(HSW_AUD_CFG(pipe), tmp);
 709
 710  unlock:
 711         mutex_unlock(&dev_priv->av_mutex);
 712         return err;
 713 }
 714
 715 static int i915_audio_component_get_eld(struct device *dev, int port,
 716                                         bool *enabled,
 717                                         unsigned char *buf, int max_bytes)
 718 {
 719         struct drm_i915_private *dev_priv = dev_to_i915(dev);
 720         struct intel_encoder *intel_encoder;
 721         struct intel_digital_port *intel_dig_port;
 722         const u8 *eld;
 723         int ret = -EINVAL;
 724
 725         mutex_lock(&dev_priv->av_mutex);
 726         intel_encoder = dev_priv->dig_port_map[port];
 727         /* intel_encoder might be NULL for DP MST */
 728         if (intel_encoder) {
 729                 ret = 0;
 730                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
 731                 *enabled = intel_dig_port->audio_connector != NULL;
 732                 if (*enabled) {
 733                         eld = intel_dig_port->audio_connector->eld;
 734                         ret = drm_eld_size(eld);
 735                         memcpy(buf, eld, min(max_bytes, ret));
 736                 }
 737         }
 738
 739         mutex_unlock(&dev_priv->av_mutex);
 740         return ret;
 741 }
 742
 743 static const struct i915_audio_component_ops i915_audio_component_ops = {
 744         .owner          = THIS_MODULE,
 745         .get_power      = i915_audio_component_get_power,
 746         .put_power      = i915_audio_component_put_power,
 747         .codec_wake_override = i915_audio_component_codec_wake_override,
 748         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
 749         .sync_audio_rate = i915_audio_component_sync_audio_rate,
 750         .get_eld        = i915_audio_component_get_eld,
 751 };
 752
 753 static int i915_audio_component_bind(struct device *i915_dev,
 754                                      struct device *hda_dev, void *data)
 755 {
 756         struct i915_audio_component *acomp = data;
 757         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 758         int i;
 759
 760         if (WARN_ON(acomp->ops || acomp->dev))
 761                 return -EEXIST;
 762
 763         drm_modeset_lock_all(dev_priv->dev);
 764         acomp->ops = &i915_audio_component_ops;
 765         acomp->dev = i915_dev;
 766         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
 767         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
 768                 acomp->aud_sample_rate[i] = 0;
 769         dev_priv->audio_component = acomp;
 770         drm_modeset_unlock_all(dev_priv->dev);
 771
 772         return 0;
 773 }
 774
 775 static void i915_audio_component_unbind(struct device *i915_dev,
 776                                         struct device *hda_dev, void *data)
 777 {
 778         struct i915_audio_component *acomp = data;
 779         struct drm_i915_private *dev_priv = dev_to_i915(i915_dev);
 780
 781         drm_modeset_lock_all(dev_priv->dev);
 782         acomp->ops = NULL;
 783         acomp->dev = NULL;
 784         dev_priv->audio_component = NULL;
 785         drm_modeset_unlock_all(dev_priv->dev);
 786 }
 787
 788 static const struct component_ops i915_audio_component_bind_ops = {
 789         .bind   = i915_audio_component_bind,
 790         .unbind = i915_audio_component_unbind,
 791 };
 792
 793 /**
 794  * i915_audio_component_init - initialize and register the audio component
 795  * @dev_priv: i915 device instance
 796  *
 797  * This will register with the component framework a child component which
 798  * will bind dynamically to the snd_hda_intel driver's corresponding master
 799  * component when the latter is registered. During binding the child
 800  * initializes an instance of struct i915_audio_component which it receives
 801  * from the master. The master can then start to use the interface defined by
 802  * this struct. Each side can break the binding at any point by deregistering
 803  * its own component after which each side's component unbind callback is
 804  * called.
 805  *
 806  * We ignore any error during registration and continue with reduced
 807  * functionality (i.e. without HDMI audio).
 808  */
 809 void i915_audio_component_init(struct drm_i915_private *dev_priv)
 810 {
 811         int ret;
 812
 813         ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 814         if (ret < 0) {
 815                 DRM_ERROR("failed to add audio component (%d)\n", ret);
 816                 /* continue with reduced functionality */
 817                 return;
 818         }
 819
 820         dev_priv->audio_component_registered = true;
 821 }
 822
 823 /**
 824  * i915_audio_component_cleanup - deregister the audio component
 825  * @dev_priv: i915 device instance
 826  *
 827  * Deregisters the audio component, breaking any existing binding to the
 828  * corresponding snd_hda_intel driver's master component.
 829  */
 830 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
 831 {
 832         if (!dev_priv->audio_component_registered)
 833                 return;
 834
 835         component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops);
 836         dev_priv->audio_component_registered = false;
 837 }