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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
51 };
52
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
63 };
64
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
79 };
80
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
91 };
92
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
103 };
104
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
115 };
116
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
129 };
130
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
142 };
143
144 /* Skylake U */
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake Y */
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
168 };
169
170 /*
171 * Skylake H and S
172 * eDP 1.4 low vswing translation parameters
173 */
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185 };
186
187 /*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
202 };
203
204 /*
205 * Skylake Y
206 * eDP 1.4 low vswing translation parameters
207 */
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219 };
220
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
234 };
235
236 /* Skylake Y */
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
249 };
250
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257 };
258
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
271 };
272
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285 };
286
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302 };
303
304 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
306
307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
310 {
311 struct drm_encoder *encoder = &intel_encoder->base;
312
313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
324 break;
325 case INTEL_OUTPUT_ANALOG:
326 *dig_port = NULL;
327 *port = PORT_E;
328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
332 }
333 }
334
335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336 {
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343 }
344
345 static bool
346 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
347 {
348 return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
349 }
350
351 static const struct ddi_buf_trans *
352 skl_get_buf_trans_dp(struct drm_device *dev, int *n_entries)
353 {
354 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
355 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
356 return skl_y_ddi_translations_dp;
357 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
358 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
359 return skl_u_ddi_translations_dp;
360 } else {
361 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
362 return skl_ddi_translations_dp;
363 }
364 }
365
366 static const struct ddi_buf_trans *
367 skl_get_buf_trans_edp(struct drm_device *dev, int *n_entries)
368 {
369 struct drm_i915_private *dev_priv = dev->dev_private;
370
371 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
372 if (dev_priv->edp_low_vswing) {
373 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
374 return skl_y_ddi_translations_edp;
375 } else {
376 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
377 return skl_y_ddi_translations_dp;
378 }
379 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
380 if (dev_priv->edp_low_vswing) {
381 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
382 return skl_u_ddi_translations_edp;
383 } else {
384 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
385 return skl_u_ddi_translations_dp;
386 }
387 } else {
388 if (dev_priv->edp_low_vswing) {
389 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
390 return skl_ddi_translations_edp;
391 } else {
392 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
393 return skl_ddi_translations_dp;
394 }
395 }
396 }
397
398 static const struct ddi_buf_trans *
399 skl_get_buf_trans_hdmi(struct drm_device *dev, int *n_entries)
400 {
401 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
402 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
403 return skl_y_ddi_translations_hdmi;
404 } else {
405 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
406 return skl_ddi_translations_hdmi;
407 }
408 }
409
410 /*
411 * Starting with Haswell, DDI port buffers must be programmed with correct
412 * values in advance. The buffer values are different for FDI and DP modes,
413 * but the HDMI/DVI fields are shared among those. So we program the DDI
414 * in either FDI or DP modes only, as HDMI connections will work with both
415 * of those
416 */
417 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
418 bool supports_hdmi)
419 {
420 struct drm_i915_private *dev_priv = dev->dev_private;
421 u32 iboost_bit = 0;
422 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
423 size;
424 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
425 const struct ddi_buf_trans *ddi_translations_fdi;
426 const struct ddi_buf_trans *ddi_translations_dp;
427 const struct ddi_buf_trans *ddi_translations_edp;
428 const struct ddi_buf_trans *ddi_translations_hdmi;
429 const struct ddi_buf_trans *ddi_translations;
430
431 if (IS_BROXTON(dev)) {
432 if (!supports_hdmi)
433 return;
434
435 /* Vswing programming for HDMI */
436 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
437 INTEL_OUTPUT_HDMI);
438 return;
439 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
440 ddi_translations_fdi = NULL;
441 ddi_translations_dp =
442 skl_get_buf_trans_dp(dev, &n_dp_entries);
443 ddi_translations_edp =
444 skl_get_buf_trans_edp(dev, &n_edp_entries);
445 ddi_translations_hdmi =
446 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
447 hdmi_default_entry = 8;
448 /* If we're boosting the current, set bit 31 of trans1 */
449 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
450 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
451 iboost_bit = 1<<31;
452 } else if (IS_BROADWELL(dev)) {
453 ddi_translations_fdi = bdw_ddi_translations_fdi;
454 ddi_translations_dp = bdw_ddi_translations_dp;
455 ddi_translations_edp = bdw_ddi_translations_edp;
456 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
457 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
458 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
459 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
460 hdmi_default_entry = 7;
461 } else if (IS_HASWELL(dev)) {
462 ddi_translations_fdi = hsw_ddi_translations_fdi;
463 ddi_translations_dp = hsw_ddi_translations_dp;
464 ddi_translations_edp = hsw_ddi_translations_dp;
465 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
466 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
467 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
468 hdmi_default_entry = 6;
469 } else {
470 WARN(1, "ddi translation table missing\n");
471 ddi_translations_edp = bdw_ddi_translations_dp;
472 ddi_translations_fdi = bdw_ddi_translations_fdi;
473 ddi_translations_dp = bdw_ddi_translations_dp;
474 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
475 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
476 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
477 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
478 hdmi_default_entry = 7;
479 }
480
481 switch (port) {
482 case PORT_A:
483 ddi_translations = ddi_translations_edp;
484 size = n_edp_entries;
485 break;
486 case PORT_B:
487 case PORT_C:
488 ddi_translations = ddi_translations_dp;
489 size = n_dp_entries;
490 break;
491 case PORT_D:
492 if (intel_dp_is_edp(dev, PORT_D)) {
493 ddi_translations = ddi_translations_edp;
494 size = n_edp_entries;
495 } else {
496 ddi_translations = ddi_translations_dp;
497 size = n_dp_entries;
498 }
499 break;
500 case PORT_E:
501 if (ddi_translations_fdi)
502 ddi_translations = ddi_translations_fdi;
503 else
504 ddi_translations = ddi_translations_dp;
505 size = n_dp_entries;
506 break;
507 default:
508 BUG();
509 }
510
511 for (i = 0; i < size; i++) {
512 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
513 ddi_translations[i].trans1 | iboost_bit);
514 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
515 ddi_translations[i].trans2);
516 }
517
518 if (!supports_hdmi)
519 return;
520
521 /* Choose a good default if VBT is badly populated */
522 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
523 hdmi_level >= n_hdmi_entries)
524 hdmi_level = hdmi_default_entry;
525
526 /* Entry 9 is for HDMI: */
527 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
528 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
529 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
530 ddi_translations_hdmi[hdmi_level].trans2);
531 }
532
533 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
534 * mode and port E for FDI.
535 */
536 void intel_prepare_ddi(struct drm_device *dev)
537 {
538 struct intel_encoder *intel_encoder;
539 bool visited[I915_MAX_PORTS] = { 0, };
540
541 if (!HAS_DDI(dev))
542 return;
543
544 for_each_intel_encoder(dev, intel_encoder) {
545 struct intel_digital_port *intel_dig_port;
546 enum port port;
547 bool supports_hdmi;
548
549 if (intel_encoder->type == INTEL_OUTPUT_DSI)
550 continue;
551
552 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
553 if (visited[port])
554 continue;
555
556 supports_hdmi = intel_dig_port &&
557 intel_dig_port_supports_hdmi(intel_dig_port);
558
559 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
560 visited[port] = true;
561 }
562 }
563
564 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
565 enum port port)
566 {
567 i915_reg_t reg = DDI_BUF_CTL(port);
568 int i;
569
570 for (i = 0; i < 16; i++) {
571 udelay(1);
572 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
573 return;
574 }
575 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
576 }
577
578 /* Starting with Haswell, different DDI ports can work in FDI mode for
579 * connection to the PCH-located connectors. For this, it is necessary to train
580 * both the DDI port and PCH receiver for the desired DDI buffer settings.
581 *
582 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
583 * please note that when FDI mode is active on DDI E, it shares 2 lines with
584 * DDI A (which is used for eDP)
585 */
586
587 void hsw_fdi_link_train(struct drm_crtc *crtc)
588 {
589 struct drm_device *dev = crtc->dev;
590 struct drm_i915_private *dev_priv = dev->dev_private;
591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
592 u32 temp, i, rx_ctl_val;
593
594 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
595 * mode set "sequence for CRT port" document:
596 * - TP1 to TP2 time with the default value
597 * - FDI delay to 90h
598 *
599 * WaFDIAutoLinkSetTimingOverrride:hsw
600 */
601 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
602 FDI_RX_PWRDN_LANE0_VAL(2) |
603 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
604
605 /* Enable the PCH Receiver FDI PLL */
606 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
607 FDI_RX_PLL_ENABLE |
608 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
609 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
610 POSTING_READ(FDI_RX_CTL(PIPE_A));
611 udelay(220);
612
613 /* Switch from Rawclk to PCDclk */
614 rx_ctl_val |= FDI_PCDCLK;
615 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
616
617 /* Configure Port Clock Select */
618 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
619 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
620
621 /* Start the training iterating through available voltages and emphasis,
622 * testing each value twice. */
623 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
624 /* Configure DP_TP_CTL with auto-training */
625 I915_WRITE(DP_TP_CTL(PORT_E),
626 DP_TP_CTL_FDI_AUTOTRAIN |
627 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
628 DP_TP_CTL_LINK_TRAIN_PAT1 |
629 DP_TP_CTL_ENABLE);
630
631 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
632 * DDI E does not support port reversal, the functionality is
633 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
634 * port reversal bit */
635 I915_WRITE(DDI_BUF_CTL(PORT_E),
636 DDI_BUF_CTL_ENABLE |
637 ((intel_crtc->config->fdi_lanes - 1) << 1) |
638 DDI_BUF_TRANS_SELECT(i / 2));
639 POSTING_READ(DDI_BUF_CTL(PORT_E));
640
641 udelay(600);
642
643 /* Program PCH FDI Receiver TU */
644 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
645
646 /* Enable PCH FDI Receiver with auto-training */
647 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
648 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
649 POSTING_READ(FDI_RX_CTL(PIPE_A));
650
651 /* Wait for FDI receiver lane calibration */
652 udelay(30);
653
654 /* Unset FDI_RX_MISC pwrdn lanes */
655 temp = I915_READ(FDI_RX_MISC(PIPE_A));
656 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
657 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
658 POSTING_READ(FDI_RX_MISC(PIPE_A));
659
660 /* Wait for FDI auto training time */
661 udelay(5);
662
663 temp = I915_READ(DP_TP_STATUS(PORT_E));
664 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
665 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
666 break;
667 }
668
669 /*
670 * Leave things enabled even if we failed to train FDI.
671 * Results in less fireworks from the state checker.
672 */
673 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
674 DRM_ERROR("FDI link training failed!\n");
675 break;
676 }
677
678 temp = I915_READ(DDI_BUF_CTL(PORT_E));
679 temp &= ~DDI_BUF_CTL_ENABLE;
680 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
681 POSTING_READ(DDI_BUF_CTL(PORT_E));
682
683 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
684 temp = I915_READ(DP_TP_CTL(PORT_E));
685 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
686 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
687 I915_WRITE(DP_TP_CTL(PORT_E), temp);
688 POSTING_READ(DP_TP_CTL(PORT_E));
689
690 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
691
692 rx_ctl_val &= ~FDI_RX_ENABLE;
693 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
694 POSTING_READ(FDI_RX_CTL(PIPE_A));
695
696 /* Reset FDI_RX_MISC pwrdn lanes */
697 temp = I915_READ(FDI_RX_MISC(PIPE_A));
698 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
699 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
700 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
701 POSTING_READ(FDI_RX_MISC(PIPE_A));
702 }
703
704 /* Enable normal pixel sending for FDI */
705 I915_WRITE(DP_TP_CTL(PORT_E),
706 DP_TP_CTL_FDI_AUTOTRAIN |
707 DP_TP_CTL_LINK_TRAIN_NORMAL |
708 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
709 DP_TP_CTL_ENABLE);
710 }
711
712 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
713 {
714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
715 struct intel_digital_port *intel_dig_port =
716 enc_to_dig_port(&encoder->base);
717
718 intel_dp->DP = intel_dig_port->saved_port_bits |
719 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
720 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
721 }
722
723 static struct intel_encoder *
724 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
725 {
726 struct drm_device *dev = crtc->dev;
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728 struct intel_encoder *intel_encoder, *ret = NULL;
729 int num_encoders = 0;
730
731 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
732 ret = intel_encoder;
733 num_encoders++;
734 }
735
736 if (num_encoders != 1)
737 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
738 pipe_name(intel_crtc->pipe));
739
740 BUG_ON(ret == NULL);
741 return ret;
742 }
743
744 struct intel_encoder *
745 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
746 {
747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
748 struct intel_encoder *ret = NULL;
749 struct drm_atomic_state *state;
750 struct drm_connector *connector;
751 struct drm_connector_state *connector_state;
752 int num_encoders = 0;
753 int i;
754
755 state = crtc_state->base.state;
756
757 for_each_connector_in_state(state, connector, connector_state, i) {
758 if (connector_state->crtc != crtc_state->base.crtc)
759 continue;
760
761 ret = to_intel_encoder(connector_state->best_encoder);
762 num_encoders++;
763 }
764
765 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
766 pipe_name(crtc->pipe));
767
768 BUG_ON(ret == NULL);
769 return ret;
770 }
771
772 #define LC_FREQ 2700
773 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
774
775 #define P_MIN 2
776 #define P_MAX 64
777 #define P_INC 2
778
779 /* Constraints for PLL good behavior */
780 #define REF_MIN 48
781 #define REF_MAX 400
782 #define VCO_MIN 2400
783 #define VCO_MAX 4800
784
785 #define abs_diff(a, b) ({ \
786 typeof(a) __a = (a); \
787 typeof(b) __b = (b); \
788 (void) (&__a == &__b); \
789 __a > __b ? (__a - __b) : (__b - __a); })
790
791 struct hsw_wrpll_rnp {
792 unsigned p, n2, r2;
793 };
794
795 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
796 {
797 unsigned budget;
798
799 switch (clock) {
800 case 25175000:
801 case 25200000:
802 case 27000000:
803 case 27027000:
804 case 37762500:
805 case 37800000:
806 case 40500000:
807 case 40541000:
808 case 54000000:
809 case 54054000:
810 case 59341000:
811 case 59400000:
812 case 72000000:
813 case 74176000:
814 case 74250000:
815 case 81000000:
816 case 81081000:
817 case 89012000:
818 case 89100000:
819 case 108000000:
820 case 108108000:
821 case 111264000:
822 case 111375000:
823 case 148352000:
824 case 148500000:
825 case 162000000:
826 case 162162000:
827 case 222525000:
828 case 222750000:
829 case 296703000:
830 case 297000000:
831 budget = 0;
832 break;
833 case 233500000:
834 case 245250000:
835 case 247750000:
836 case 253250000:
837 case 298000000:
838 budget = 1500;
839 break;
840 case 169128000:
841 case 169500000:
842 case 179500000:
843 case 202000000:
844 budget = 2000;
845 break;
846 case 256250000:
847 case 262500000:
848 case 270000000:
849 case 272500000:
850 case 273750000:
851 case 280750000:
852 case 281250000:
853 case 286000000:
854 case 291750000:
855 budget = 4000;
856 break;
857 case 267250000:
858 case 268500000:
859 budget = 5000;
860 break;
861 default:
862 budget = 1000;
863 break;
864 }
865
866 return budget;
867 }
868
869 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
870 unsigned r2, unsigned n2, unsigned p,
871 struct hsw_wrpll_rnp *best)
872 {
873 uint64_t a, b, c, d, diff, diff_best;
874
875 /* No best (r,n,p) yet */
876 if (best->p == 0) {
877 best->p = p;
878 best->n2 = n2;
879 best->r2 = r2;
880 return;
881 }
882
883 /*
884 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
885 * freq2k.
886 *
887 * delta = 1e6 *
888 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
889 * freq2k;
890 *
891 * and we would like delta <= budget.
892 *
893 * If the discrepancy is above the PPM-based budget, always prefer to
894 * improve upon the previous solution. However, if you're within the
895 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
896 */
897 a = freq2k * budget * p * r2;
898 b = freq2k * budget * best->p * best->r2;
899 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
900 diff_best = abs_diff(freq2k * best->p * best->r2,
901 LC_FREQ_2K * best->n2);
902 c = 1000000 * diff;
903 d = 1000000 * diff_best;
904
905 if (a < c && b < d) {
906 /* If both are above the budget, pick the closer */
907 if (best->p * best->r2 * diff < p * r2 * diff_best) {
908 best->p = p;
909 best->n2 = n2;
910 best->r2 = r2;
911 }
912 } else if (a >= c && b < d) {
913 /* If A is below the threshold but B is above it? Update. */
914 best->p = p;
915 best->n2 = n2;
916 best->r2 = r2;
917 } else if (a >= c && b >= d) {
918 /* Both are below the limit, so pick the higher n2/(r2*r2) */
919 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
920 best->p = p;
921 best->n2 = n2;
922 best->r2 = r2;
923 }
924 }
925 /* Otherwise a < c && b >= d, do nothing */
926 }
927
928 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
929 i915_reg_t reg)
930 {
931 int refclk = LC_FREQ;
932 int n, p, r;
933 u32 wrpll;
934
935 wrpll = I915_READ(reg);
936 switch (wrpll & WRPLL_PLL_REF_MASK) {
937 case WRPLL_PLL_SSC:
938 case WRPLL_PLL_NON_SSC:
939 /*
940 * We could calculate spread here, but our checking
941 * code only cares about 5% accuracy, and spread is a max of
942 * 0.5% downspread.
943 */
944 refclk = 135;
945 break;
946 case WRPLL_PLL_LCPLL:
947 refclk = LC_FREQ;
948 break;
949 default:
950 WARN(1, "bad wrpll refclk\n");
951 return 0;
952 }
953
954 r = wrpll & WRPLL_DIVIDER_REF_MASK;
955 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
956 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
957
958 /* Convert to KHz, p & r have a fixed point portion */
959 return (refclk * n * 100) / (p * r);
960 }
961
962 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
963 uint32_t dpll)
964 {
965 i915_reg_t cfgcr1_reg, cfgcr2_reg;
966 uint32_t cfgcr1_val, cfgcr2_val;
967 uint32_t p0, p1, p2, dco_freq;
968
969 cfgcr1_reg = DPLL_CFGCR1(dpll);
970 cfgcr2_reg = DPLL_CFGCR2(dpll);
971
972 cfgcr1_val = I915_READ(cfgcr1_reg);
973 cfgcr2_val = I915_READ(cfgcr2_reg);
974
975 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
976 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
977
978 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
979 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
980 else
981 p1 = 1;
982
983
984 switch (p0) {
985 case DPLL_CFGCR2_PDIV_1:
986 p0 = 1;
987 break;
988 case DPLL_CFGCR2_PDIV_2:
989 p0 = 2;
990 break;
991 case DPLL_CFGCR2_PDIV_3:
992 p0 = 3;
993 break;
994 case DPLL_CFGCR2_PDIV_7:
995 p0 = 7;
996 break;
997 }
998
999 switch (p2) {
1000 case DPLL_CFGCR2_KDIV_5:
1001 p2 = 5;
1002 break;
1003 case DPLL_CFGCR2_KDIV_2:
1004 p2 = 2;
1005 break;
1006 case DPLL_CFGCR2_KDIV_3:
1007 p2 = 3;
1008 break;
1009 case DPLL_CFGCR2_KDIV_1:
1010 p2 = 1;
1011 break;
1012 }
1013
1014 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1015
1016 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1017 1000) / 0x8000;
1018
1019 return dco_freq / (p0 * p1 * p2 * 5);
1020 }
1021
1022 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1023 {
1024 int dotclock;
1025
1026 if (pipe_config->has_pch_encoder)
1027 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1028 &pipe_config->fdi_m_n);
1029 else if (pipe_config->has_dp_encoder)
1030 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1031 &pipe_config->dp_m_n);
1032 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1033 dotclock = pipe_config->port_clock * 2 / 3;
1034 else
1035 dotclock = pipe_config->port_clock;
1036
1037 if (pipe_config->pixel_multiplier)
1038 dotclock /= pipe_config->pixel_multiplier;
1039
1040 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1041 }
1042
1043 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1044 struct intel_crtc_state *pipe_config)
1045 {
1046 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1047 int link_clock = 0;
1048 uint32_t dpll_ctl1, dpll;
1049
1050 dpll = pipe_config->ddi_pll_sel;
1051
1052 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1053
1054 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1055 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1056 } else {
1057 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1058 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1059
1060 switch (link_clock) {
1061 case DPLL_CTRL1_LINK_RATE_810:
1062 link_clock = 81000;
1063 break;
1064 case DPLL_CTRL1_LINK_RATE_1080:
1065 link_clock = 108000;
1066 break;
1067 case DPLL_CTRL1_LINK_RATE_1350:
1068 link_clock = 135000;
1069 break;
1070 case DPLL_CTRL1_LINK_RATE_1620:
1071 link_clock = 162000;
1072 break;
1073 case DPLL_CTRL1_LINK_RATE_2160:
1074 link_clock = 216000;
1075 break;
1076 case DPLL_CTRL1_LINK_RATE_2700:
1077 link_clock = 270000;
1078 break;
1079 default:
1080 WARN(1, "Unsupported link rate\n");
1081 break;
1082 }
1083 link_clock *= 2;
1084 }
1085
1086 pipe_config->port_clock = link_clock;
1087
1088 ddi_dotclock_get(pipe_config);
1089 }
1090
1091 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1092 struct intel_crtc_state *pipe_config)
1093 {
1094 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1095 int link_clock = 0;
1096 u32 val, pll;
1097
1098 val = pipe_config->ddi_pll_sel;
1099 switch (val & PORT_CLK_SEL_MASK) {
1100 case PORT_CLK_SEL_LCPLL_810:
1101 link_clock = 81000;
1102 break;
1103 case PORT_CLK_SEL_LCPLL_1350:
1104 link_clock = 135000;
1105 break;
1106 case PORT_CLK_SEL_LCPLL_2700:
1107 link_clock = 270000;
1108 break;
1109 case PORT_CLK_SEL_WRPLL1:
1110 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1111 break;
1112 case PORT_CLK_SEL_WRPLL2:
1113 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1114 break;
1115 case PORT_CLK_SEL_SPLL:
1116 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1117 if (pll == SPLL_PLL_FREQ_810MHz)
1118 link_clock = 81000;
1119 else if (pll == SPLL_PLL_FREQ_1350MHz)
1120 link_clock = 135000;
1121 else if (pll == SPLL_PLL_FREQ_2700MHz)
1122 link_clock = 270000;
1123 else {
1124 WARN(1, "bad spll freq\n");
1125 return;
1126 }
1127 break;
1128 default:
1129 WARN(1, "bad port clock sel\n");
1130 return;
1131 }
1132
1133 pipe_config->port_clock = link_clock * 2;
1134
1135 ddi_dotclock_get(pipe_config);
1136 }
1137
1138 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1139 enum intel_dpll_id dpll)
1140 {
1141 struct intel_shared_dpll *pll;
1142 struct intel_dpll_hw_state *state;
1143 intel_clock_t clock;
1144
1145 /* For DDI ports we always use a shared PLL. */
1146 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1147 return 0;
1148
1149 pll = &dev_priv->shared_dplls[dpll];
1150 state = &pll->config.hw_state;
1151
1152 clock.m1 = 2;
1153 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1154 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1155 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1156 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1157 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1158 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1159
1160 return chv_calc_dpll_params(100000, &clock);
1161 }
1162
1163 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1164 struct intel_crtc_state *pipe_config)
1165 {
1166 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1167 enum port port = intel_ddi_get_encoder_port(encoder);
1168 uint32_t dpll = port;
1169
1170 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1171
1172 ddi_dotclock_get(pipe_config);
1173 }
1174
1175 void intel_ddi_clock_get(struct intel_encoder *encoder,
1176 struct intel_crtc_state *pipe_config)
1177 {
1178 struct drm_device *dev = encoder->base.dev;
1179
1180 if (INTEL_INFO(dev)->gen <= 8)
1181 hsw_ddi_clock_get(encoder, pipe_config);
1182 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1183 skl_ddi_clock_get(encoder, pipe_config);
1184 else if (IS_BROXTON(dev))
1185 bxt_ddi_clock_get(encoder, pipe_config);
1186 }
1187
1188 static void
1189 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1190 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1191 {
1192 uint64_t freq2k;
1193 unsigned p, n2, r2;
1194 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1195 unsigned budget;
1196
1197 freq2k = clock / 100;
1198
1199 budget = hsw_wrpll_get_budget_for_freq(clock);
1200
1201 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1202 * and directly pass the LC PLL to it. */
1203 if (freq2k == 5400000) {
1204 *n2_out = 2;
1205 *p_out = 1;
1206 *r2_out = 2;
1207 return;
1208 }
1209
1210 /*
1211 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1212 * the WR PLL.
1213 *
1214 * We want R so that REF_MIN <= Ref <= REF_MAX.
1215 * Injecting R2 = 2 * R gives:
1216 * REF_MAX * r2 > LC_FREQ * 2 and
1217 * REF_MIN * r2 < LC_FREQ * 2
1218 *
1219 * Which means the desired boundaries for r2 are:
1220 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1221 *
1222 */
1223 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1224 r2 <= LC_FREQ * 2 / REF_MIN;
1225 r2++) {
1226
1227 /*
1228 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1229 *
1230 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1231 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1232 * VCO_MAX * r2 > n2 * LC_FREQ and
1233 * VCO_MIN * r2 < n2 * LC_FREQ)
1234 *
1235 * Which means the desired boundaries for n2 are:
1236 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1237 */
1238 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1239 n2 <= VCO_MAX * r2 / LC_FREQ;
1240 n2++) {
1241
1242 for (p = P_MIN; p <= P_MAX; p += P_INC)
1243 hsw_wrpll_update_rnp(freq2k, budget,
1244 r2, n2, p, &best);
1245 }
1246 }
1247
1248 *n2_out = best.n2;
1249 *p_out = best.p;
1250 *r2_out = best.r2;
1251 }
1252
1253 static bool
1254 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1255 struct intel_crtc_state *crtc_state,
1256 struct intel_encoder *intel_encoder)
1257 {
1258 int clock = crtc_state->port_clock;
1259
1260 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1261 struct intel_shared_dpll *pll;
1262 uint32_t val;
1263 unsigned p, n2, r2;
1264
1265 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1266
1267 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1268 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1269 WRPLL_DIVIDER_POST(p);
1270
1271 memset(&crtc_state->dpll_hw_state, 0,
1272 sizeof(crtc_state->dpll_hw_state));
1273
1274 crtc_state->dpll_hw_state.wrpll = val;
1275
1276 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1277 if (pll == NULL) {
1278 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1279 pipe_name(intel_crtc->pipe));
1280 return false;
1281 }
1282
1283 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1284 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1285 struct drm_atomic_state *state = crtc_state->base.state;
1286 struct intel_shared_dpll_config *spll =
1287 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1288
1289 if (spll->crtc_mask &&
1290 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1291 return false;
1292
1293 crtc_state->shared_dpll = DPLL_ID_SPLL;
1294 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1295 spll->crtc_mask |= 1 << intel_crtc->pipe;
1296 }
1297
1298 return true;
1299 }
1300
1301 struct skl_wrpll_context {
1302 uint64_t min_deviation; /* current minimal deviation */
1303 uint64_t central_freq; /* chosen central freq */
1304 uint64_t dco_freq; /* chosen dco freq */
1305 unsigned int p; /* chosen divider */
1306 };
1307
1308 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1309 {
1310 memset(ctx, 0, sizeof(*ctx));
1311
1312 ctx->min_deviation = U64_MAX;
1313 }
1314
1315 /* DCO freq must be within +1%/-6% of the DCO central freq */
1316 #define SKL_DCO_MAX_PDEVIATION 100
1317 #define SKL_DCO_MAX_NDEVIATION 600
1318
1319 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1320 uint64_t central_freq,
1321 uint64_t dco_freq,
1322 unsigned int divider)
1323 {
1324 uint64_t deviation;
1325
1326 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1327 central_freq);
1328
1329 /* positive deviation */
1330 if (dco_freq >= central_freq) {
1331 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1332 deviation < ctx->min_deviation) {
1333 ctx->min_deviation = deviation;
1334 ctx->central_freq = central_freq;
1335 ctx->dco_freq = dco_freq;
1336 ctx->p = divider;
1337 }
1338 /* negative deviation */
1339 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1340 deviation < ctx->min_deviation) {
1341 ctx->min_deviation = deviation;
1342 ctx->central_freq = central_freq;
1343 ctx->dco_freq = dco_freq;
1344 ctx->p = divider;
1345 }
1346 }
1347
1348 static void skl_wrpll_get_multipliers(unsigned int p,
1349 unsigned int *p0 /* out */,
1350 unsigned int *p1 /* out */,
1351 unsigned int *p2 /* out */)
1352 {
1353 /* even dividers */
1354 if (p % 2 == 0) {
1355 unsigned int half = p / 2;
1356
1357 if (half == 1 || half == 2 || half == 3 || half == 5) {
1358 *p0 = 2;
1359 *p1 = 1;
1360 *p2 = half;
1361 } else if (half % 2 == 0) {
1362 *p0 = 2;
1363 *p1 = half / 2;
1364 *p2 = 2;
1365 } else if (half % 3 == 0) {
1366 *p0 = 3;
1367 *p1 = half / 3;
1368 *p2 = 2;
1369 } else if (half % 7 == 0) {
1370 *p0 = 7;
1371 *p1 = half / 7;
1372 *p2 = 2;
1373 }
1374 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1375 *p0 = 3;
1376 *p1 = 1;
1377 *p2 = p / 3;
1378 } else if (p == 5 || p == 7) {
1379 *p0 = p;
1380 *p1 = 1;
1381 *p2 = 1;
1382 } else if (p == 15) {
1383 *p0 = 3;
1384 *p1 = 1;
1385 *p2 = 5;
1386 } else if (p == 21) {
1387 *p0 = 7;
1388 *p1 = 1;
1389 *p2 = 3;
1390 } else if (p == 35) {
1391 *p0 = 7;
1392 *p1 = 1;
1393 *p2 = 5;
1394 }
1395 }
1396
1397 struct skl_wrpll_params {
1398 uint32_t dco_fraction;
1399 uint32_t dco_integer;
1400 uint32_t qdiv_ratio;
1401 uint32_t qdiv_mode;
1402 uint32_t kdiv;
1403 uint32_t pdiv;
1404 uint32_t central_freq;
1405 };
1406
1407 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1408 uint64_t afe_clock,
1409 uint64_t central_freq,
1410 uint32_t p0, uint32_t p1, uint32_t p2)
1411 {
1412 uint64_t dco_freq;
1413
1414 switch (central_freq) {
1415 case 9600000000ULL:
1416 params->central_freq = 0;
1417 break;
1418 case 9000000000ULL:
1419 params->central_freq = 1;
1420 break;
1421 case 8400000000ULL:
1422 params->central_freq = 3;
1423 }
1424
1425 switch (p0) {
1426 case 1:
1427 params->pdiv = 0;
1428 break;
1429 case 2:
1430 params->pdiv = 1;
1431 break;
1432 case 3:
1433 params->pdiv = 2;
1434 break;
1435 case 7:
1436 params->pdiv = 4;
1437 break;
1438 default:
1439 WARN(1, "Incorrect PDiv\n");
1440 }
1441
1442 switch (p2) {
1443 case 5:
1444 params->kdiv = 0;
1445 break;
1446 case 2:
1447 params->kdiv = 1;
1448 break;
1449 case 3:
1450 params->kdiv = 2;
1451 break;
1452 case 1:
1453 params->kdiv = 3;
1454 break;
1455 default:
1456 WARN(1, "Incorrect KDiv\n");
1457 }
1458
1459 params->qdiv_ratio = p1;
1460 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1461
1462 dco_freq = p0 * p1 * p2 * afe_clock;
1463
1464 /*
1465 * Intermediate values are in Hz.
1466 * Divide by MHz to match bsepc
1467 */
1468 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1469 params->dco_fraction =
1470 div_u64((div_u64(dco_freq, 24) -
1471 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1472 }
1473
1474 static bool
1475 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1476 struct skl_wrpll_params *wrpll_params)
1477 {
1478 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1479 uint64_t dco_central_freq[3] = {8400000000ULL,
1480 9000000000ULL,
1481 9600000000ULL};
1482 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1483 24, 28, 30, 32, 36, 40, 42, 44,
1484 48, 52, 54, 56, 60, 64, 66, 68,
1485 70, 72, 76, 78, 80, 84, 88, 90,
1486 92, 96, 98 };
1487 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1488 static const struct {
1489 const int *list;
1490 int n_dividers;
1491 } dividers[] = {
1492 { even_dividers, ARRAY_SIZE(even_dividers) },
1493 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1494 };
1495 struct skl_wrpll_context ctx;
1496 unsigned int dco, d, i;
1497 unsigned int p0, p1, p2;
1498
1499 skl_wrpll_context_init(&ctx);
1500
1501 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1502 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1503 for (i = 0; i < dividers[d].n_dividers; i++) {
1504 unsigned int p = dividers[d].list[i];
1505 uint64_t dco_freq = p * afe_clock;
1506
1507 skl_wrpll_try_divider(&ctx,
1508 dco_central_freq[dco],
1509 dco_freq,
1510 p);
1511 /*
1512 * Skip the remaining dividers if we're sure to
1513 * have found the definitive divider, we can't
1514 * improve a 0 deviation.
1515 */
1516 if (ctx.min_deviation == 0)
1517 goto skip_remaining_dividers;
1518 }
1519 }
1520
1521 skip_remaining_dividers:
1522 /*
1523 * If a solution is found with an even divider, prefer
1524 * this one.
1525 */
1526 if (d == 0 && ctx.p)
1527 break;
1528 }
1529
1530 if (!ctx.p) {
1531 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1532 return false;
1533 }
1534
1535 /*
1536 * gcc incorrectly analyses that these can be used without being
1537 * initialized. To be fair, it's hard to guess.
1538 */
1539 p0 = p1 = p2 = 0;
1540 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1541 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1542 p0, p1, p2);
1543
1544 return true;
1545 }
1546
1547 static bool
1548 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1549 struct intel_crtc_state *crtc_state,
1550 struct intel_encoder *intel_encoder)
1551 {
1552 struct intel_shared_dpll *pll;
1553 uint32_t ctrl1, cfgcr1, cfgcr2;
1554 int clock = crtc_state->port_clock;
1555
1556 /*
1557 * See comment in intel_dpll_hw_state to understand why we always use 0
1558 * as the DPLL id in this function.
1559 */
1560
1561 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1562
1563 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1564 struct skl_wrpll_params wrpll_params = { 0, };
1565
1566 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1567
1568 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1569 return false;
1570
1571 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1572 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1573 wrpll_params.dco_integer;
1574
1575 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1576 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1577 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1578 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1579 wrpll_params.central_freq;
1580 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1581 switch (crtc_state->port_clock / 2) {
1582 case 81000:
1583 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1584 break;
1585 case 135000:
1586 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1587 break;
1588 case 270000:
1589 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1590 break;
1591 }
1592
1593 cfgcr1 = cfgcr2 = 0;
1594 } else /* eDP */
1595 return true;
1596
1597 memset(&crtc_state->dpll_hw_state, 0,
1598 sizeof(crtc_state->dpll_hw_state));
1599
1600 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1601 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1602 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1603
1604 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1605 if (pll == NULL) {
1606 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1607 pipe_name(intel_crtc->pipe));
1608 return false;
1609 }
1610
1611 /* shared DPLL id 0 is DPLL 1 */
1612 crtc_state->ddi_pll_sel = pll->id + 1;
1613
1614 return true;
1615 }
1616
1617 /* bxt clock parameters */
1618 struct bxt_clk_div {
1619 int clock;
1620 uint32_t p1;
1621 uint32_t p2;
1622 uint32_t m2_int;
1623 uint32_t m2_frac;
1624 bool m2_frac_en;
1625 uint32_t n;
1626 };
1627
1628 /* pre-calculated values for DP linkrates */
1629 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1630 {162000, 4, 2, 32, 1677722, 1, 1},
1631 {270000, 4, 1, 27, 0, 0, 1},
1632 {540000, 2, 1, 27, 0, 0, 1},
1633 {216000, 3, 2, 32, 1677722, 1, 1},
1634 {243000, 4, 1, 24, 1258291, 1, 1},
1635 {324000, 4, 1, 32, 1677722, 1, 1},
1636 {432000, 3, 1, 32, 1677722, 1, 1}
1637 };
1638
1639 static bool
1640 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1641 struct intel_crtc_state *crtc_state,
1642 struct intel_encoder *intel_encoder)
1643 {
1644 struct intel_shared_dpll *pll;
1645 struct bxt_clk_div clk_div = {0};
1646 int vco = 0;
1647 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1648 uint32_t lanestagger;
1649 int clock = crtc_state->port_clock;
1650
1651 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1652 intel_clock_t best_clock;
1653
1654 /* Calculate HDMI div */
1655 /*
1656 * FIXME: tie the following calculation into
1657 * i9xx_crtc_compute_clock
1658 */
1659 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1660 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1661 clock, pipe_name(intel_crtc->pipe));
1662 return false;
1663 }
1664
1665 clk_div.p1 = best_clock.p1;
1666 clk_div.p2 = best_clock.p2;
1667 WARN_ON(best_clock.m1 != 2);
1668 clk_div.n = best_clock.n;
1669 clk_div.m2_int = best_clock.m2 >> 22;
1670 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1671 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1672
1673 vco = best_clock.vco;
1674 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1675 intel_encoder->type == INTEL_OUTPUT_EDP) {
1676 int i;
1677
1678 clk_div = bxt_dp_clk_val[0];
1679 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1680 if (bxt_dp_clk_val[i].clock == clock) {
1681 clk_div = bxt_dp_clk_val[i];
1682 break;
1683 }
1684 }
1685 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1686 }
1687
1688 if (vco >= 6200000 && vco <= 6700000) {
1689 prop_coef = 4;
1690 int_coef = 9;
1691 gain_ctl = 3;
1692 targ_cnt = 8;
1693 } else if ((vco > 5400000 && vco < 6200000) ||
1694 (vco >= 4800000 && vco < 5400000)) {
1695 prop_coef = 5;
1696 int_coef = 11;
1697 gain_ctl = 3;
1698 targ_cnt = 9;
1699 } else if (vco == 5400000) {
1700 prop_coef = 3;
1701 int_coef = 8;
1702 gain_ctl = 1;
1703 targ_cnt = 9;
1704 } else {
1705 DRM_ERROR("Invalid VCO\n");
1706 return false;
1707 }
1708
1709 memset(&crtc_state->dpll_hw_state, 0,
1710 sizeof(crtc_state->dpll_hw_state));
1711
1712 if (clock > 270000)
1713 lanestagger = 0x18;
1714 else if (clock > 135000)
1715 lanestagger = 0x0d;
1716 else if (clock > 67000)
1717 lanestagger = 0x07;
1718 else if (clock > 33000)
1719 lanestagger = 0x04;
1720 else
1721 lanestagger = 0x02;
1722
1723 crtc_state->dpll_hw_state.ebb0 =
1724 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1725 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1726 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1727 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1728
1729 if (clk_div.m2_frac_en)
1730 crtc_state->dpll_hw_state.pll3 =
1731 PORT_PLL_M2_FRAC_ENABLE;
1732
1733 crtc_state->dpll_hw_state.pll6 =
1734 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1735 crtc_state->dpll_hw_state.pll6 |=
1736 PORT_PLL_GAIN_CTL(gain_ctl);
1737
1738 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1739
1740 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1741
1742 crtc_state->dpll_hw_state.pll10 =
1743 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1744 | PORT_PLL_DCO_AMP_OVR_EN_H;
1745
1746 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1747
1748 crtc_state->dpll_hw_state.pcsdw12 =
1749 LANESTAGGER_STRAP_OVRD | lanestagger;
1750
1751 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1752 if (pll == NULL) {
1753 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1754 pipe_name(intel_crtc->pipe));
1755 return false;
1756 }
1757
1758 /* shared DPLL id 0 is DPLL A */
1759 crtc_state->ddi_pll_sel = pll->id;
1760
1761 return true;
1762 }
1763
1764 /*
1765 * Tries to find a *shared* PLL for the CRTC and store it in
1766 * intel_crtc->ddi_pll_sel.
1767 *
1768 * For private DPLLs, compute_config() should do the selection for us. This
1769 * function should be folded into compute_config() eventually.
1770 */
1771 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1772 struct intel_crtc_state *crtc_state)
1773 {
1774 struct drm_device *dev = intel_crtc->base.dev;
1775 struct intel_encoder *intel_encoder =
1776 intel_ddi_get_crtc_new_encoder(crtc_state);
1777
1778 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1779 return skl_ddi_pll_select(intel_crtc, crtc_state,
1780 intel_encoder);
1781 else if (IS_BROXTON(dev))
1782 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1783 intel_encoder);
1784 else
1785 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1786 intel_encoder);
1787 }
1788
1789 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1790 {
1791 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1794 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1795 int type = intel_encoder->type;
1796 uint32_t temp;
1797
1798 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1799 temp = TRANS_MSA_SYNC_CLK;
1800 switch (intel_crtc->config->pipe_bpp) {
1801 case 18:
1802 temp |= TRANS_MSA_6_BPC;
1803 break;
1804 case 24:
1805 temp |= TRANS_MSA_8_BPC;
1806 break;
1807 case 30:
1808 temp |= TRANS_MSA_10_BPC;
1809 break;
1810 case 36:
1811 temp |= TRANS_MSA_12_BPC;
1812 break;
1813 default:
1814 BUG();
1815 }
1816 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1817 }
1818 }
1819
1820 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1821 {
1822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823 struct drm_device *dev = crtc->dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1826 uint32_t temp;
1827 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1828 if (state == true)
1829 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1830 else
1831 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1832 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1833 }
1834
1835 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1836 {
1837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1838 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1839 struct drm_encoder *encoder = &intel_encoder->base;
1840 struct drm_device *dev = crtc->dev;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 enum pipe pipe = intel_crtc->pipe;
1843 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1844 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1845 int type = intel_encoder->type;
1846 uint32_t temp;
1847
1848 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1849 temp = TRANS_DDI_FUNC_ENABLE;
1850 temp |= TRANS_DDI_SELECT_PORT(port);
1851
1852 switch (intel_crtc->config->pipe_bpp) {
1853 case 18:
1854 temp |= TRANS_DDI_BPC_6;
1855 break;
1856 case 24:
1857 temp |= TRANS_DDI_BPC_8;
1858 break;
1859 case 30:
1860 temp |= TRANS_DDI_BPC_10;
1861 break;
1862 case 36:
1863 temp |= TRANS_DDI_BPC_12;
1864 break;
1865 default:
1866 BUG();
1867 }
1868
1869 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1870 temp |= TRANS_DDI_PVSYNC;
1871 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1872 temp |= TRANS_DDI_PHSYNC;
1873
1874 if (cpu_transcoder == TRANSCODER_EDP) {
1875 switch (pipe) {
1876 case PIPE_A:
1877 /* On Haswell, can only use the always-on power well for
1878 * eDP when not using the panel fitter, and when not
1879 * using motion blur mitigation (which we don't
1880 * support). */
1881 if (IS_HASWELL(dev) &&
1882 (intel_crtc->config->pch_pfit.enabled ||
1883 intel_crtc->config->pch_pfit.force_thru))
1884 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1885 else
1886 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1887 break;
1888 case PIPE_B:
1889 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1890 break;
1891 case PIPE_C:
1892 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1893 break;
1894 default:
1895 BUG();
1896 break;
1897 }
1898 }
1899
1900 if (type == INTEL_OUTPUT_HDMI) {
1901 if (intel_crtc->config->has_hdmi_sink)
1902 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1903 else
1904 temp |= TRANS_DDI_MODE_SELECT_DVI;
1905
1906 } else if (type == INTEL_OUTPUT_ANALOG) {
1907 temp |= TRANS_DDI_MODE_SELECT_FDI;
1908 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1909
1910 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1911 type == INTEL_OUTPUT_EDP) {
1912 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1913
1914 if (intel_dp->is_mst) {
1915 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1916 } else
1917 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1918
1919 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1920 } else if (type == INTEL_OUTPUT_DP_MST) {
1921 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1922
1923 if (intel_dp->is_mst) {
1924 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1925 } else
1926 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1927
1928 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1929 } else {
1930 WARN(1, "Invalid encoder type %d for pipe %c\n",
1931 intel_encoder->type, pipe_name(pipe));
1932 }
1933
1934 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1935 }
1936
1937 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1938 enum transcoder cpu_transcoder)
1939 {
1940 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1941 uint32_t val = I915_READ(reg);
1942
1943 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1944 val |= TRANS_DDI_PORT_NONE;
1945 I915_WRITE(reg, val);
1946 }
1947
1948 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1949 {
1950 struct drm_device *dev = intel_connector->base.dev;
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1952 struct intel_encoder *intel_encoder = intel_connector->encoder;
1953 int type = intel_connector->base.connector_type;
1954 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1955 enum pipe pipe = 0;
1956 enum transcoder cpu_transcoder;
1957 enum intel_display_power_domain power_domain;
1958 uint32_t tmp;
1959
1960 power_domain = intel_display_port_power_domain(intel_encoder);
1961 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1962 return false;
1963
1964 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1965 return false;
1966
1967 if (port == PORT_A)
1968 cpu_transcoder = TRANSCODER_EDP;
1969 else
1970 cpu_transcoder = (enum transcoder) pipe;
1971
1972 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1973
1974 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1975 case TRANS_DDI_MODE_SELECT_HDMI:
1976 case TRANS_DDI_MODE_SELECT_DVI:
1977 return (type == DRM_MODE_CONNECTOR_HDMIA);
1978
1979 case TRANS_DDI_MODE_SELECT_DP_SST:
1980 if (type == DRM_MODE_CONNECTOR_eDP)
1981 return true;
1982 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1983 case TRANS_DDI_MODE_SELECT_DP_MST:
1984 /* if the transcoder is in MST state then
1985 * connector isn't connected */
1986 return false;
1987
1988 case TRANS_DDI_MODE_SELECT_FDI:
1989 return (type == DRM_MODE_CONNECTOR_VGA);
1990
1991 default:
1992 return false;
1993 }
1994 }
1995
1996 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1997 enum pipe *pipe)
1998 {
1999 struct drm_device *dev = encoder->base.dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 enum port port = intel_ddi_get_encoder_port(encoder);
2002 enum intel_display_power_domain power_domain;
2003 u32 tmp;
2004 int i;
2005
2006 power_domain = intel_display_port_power_domain(encoder);
2007 if (!intel_display_power_is_enabled(dev_priv, power_domain))
2008 return false;
2009
2010 tmp = I915_READ(DDI_BUF_CTL(port));
2011
2012 if (!(tmp & DDI_BUF_CTL_ENABLE))
2013 return false;
2014
2015 if (port == PORT_A) {
2016 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2017
2018 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2019 case TRANS_DDI_EDP_INPUT_A_ON:
2020 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2021 *pipe = PIPE_A;
2022 break;
2023 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2024 *pipe = PIPE_B;
2025 break;
2026 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2027 *pipe = PIPE_C;
2028 break;
2029 }
2030
2031 return true;
2032 } else {
2033 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2034 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2035
2036 if ((tmp & TRANS_DDI_PORT_MASK)
2037 == TRANS_DDI_SELECT_PORT(port)) {
2038 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2039 return false;
2040
2041 *pipe = i;
2042 return true;
2043 }
2044 }
2045 }
2046
2047 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2048
2049 return false;
2050 }
2051
2052 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2053 {
2054 struct drm_crtc *crtc = &intel_crtc->base;
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2058 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2060
2061 if (cpu_transcoder != TRANSCODER_EDP)
2062 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2063 TRANS_CLK_SEL_PORT(port));
2064 }
2065
2066 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2067 {
2068 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2069 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2070
2071 if (cpu_transcoder != TRANSCODER_EDP)
2072 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2073 TRANS_CLK_SEL_DISABLED);
2074 }
2075
2076 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2077 enum port port, int type)
2078 {
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 const struct ddi_buf_trans *ddi_translations;
2081 uint8_t iboost;
2082 uint8_t dp_iboost, hdmi_iboost;
2083 int n_entries;
2084 u32 reg;
2085
2086 /* VBT may override standard boost values */
2087 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2088 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2089
2090 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2091 if (dp_iboost) {
2092 iboost = dp_iboost;
2093 } else {
2094 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2095 iboost = ddi_translations[level].i_boost;
2096 }
2097 } else if (type == INTEL_OUTPUT_EDP) {
2098 if (dp_iboost) {
2099 iboost = dp_iboost;
2100 } else {
2101 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2102 iboost = ddi_translations[level].i_boost;
2103 }
2104 } else if (type == INTEL_OUTPUT_HDMI) {
2105 if (hdmi_iboost) {
2106 iboost = hdmi_iboost;
2107 } else {
2108 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2109 iboost = ddi_translations[level].i_boost;
2110 }
2111 } else {
2112 return;
2113 }
2114
2115 /* Make sure that the requested I_boost is valid */
2116 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2117 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2118 return;
2119 }
2120
2121 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2122 reg &= ~BALANCE_LEG_MASK(port);
2123 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2124
2125 if (iboost)
2126 reg |= iboost << BALANCE_LEG_SHIFT(port);
2127 else
2128 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2129
2130 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2131 }
2132
2133 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2134 enum port port, int type)
2135 {
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2137 const struct bxt_ddi_buf_trans *ddi_translations;
2138 u32 n_entries, i;
2139 uint32_t val;
2140
2141 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2142 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2143 ddi_translations = bxt_ddi_translations_edp;
2144 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2145 || type == INTEL_OUTPUT_EDP) {
2146 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2147 ddi_translations = bxt_ddi_translations_dp;
2148 } else if (type == INTEL_OUTPUT_HDMI) {
2149 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2150 ddi_translations = bxt_ddi_translations_hdmi;
2151 } else {
2152 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2153 type);
2154 return;
2155 }
2156
2157 /* Check if default value has to be used */
2158 if (level >= n_entries ||
2159 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2160 for (i = 0; i < n_entries; i++) {
2161 if (ddi_translations[i].default_index) {
2162 level = i;
2163 break;
2164 }
2165 }
2166 }
2167
2168 /*
2169 * While we write to the group register to program all lanes at once we
2170 * can read only lane registers and we pick lanes 0/1 for that.
2171 */
2172 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2173 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2174 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2175
2176 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2177 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2178 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2179 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2180 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2181
2182 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2183 val &= ~SCALE_DCOMP_METHOD;
2184 if (ddi_translations[level].enable)
2185 val |= SCALE_DCOMP_METHOD;
2186
2187 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2188 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2189
2190 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2191
2192 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2193 val &= ~DE_EMPHASIS;
2194 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2195 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2196
2197 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2198 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2199 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2200 }
2201
2202 static uint32_t translate_signal_level(int signal_levels)
2203 {
2204 uint32_t level;
2205
2206 switch (signal_levels) {
2207 default:
2208 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2209 signal_levels);
2210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2211 level = 0;
2212 break;
2213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2214 level = 1;
2215 break;
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2217 level = 2;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2220 level = 3;
2221 break;
2222
2223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2224 level = 4;
2225 break;
2226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2227 level = 5;
2228 break;
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2230 level = 6;
2231 break;
2232
2233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2234 level = 7;
2235 break;
2236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2237 level = 8;
2238 break;
2239
2240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2241 level = 9;
2242 break;
2243 }
2244
2245 return level;
2246 }
2247
2248 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2249 {
2250 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2251 struct drm_device *dev = dport->base.base.dev;
2252 struct intel_encoder *encoder = &dport->base;
2253 uint8_t train_set = intel_dp->train_set[0];
2254 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2255 DP_TRAIN_PRE_EMPHASIS_MASK);
2256 enum port port = dport->port;
2257 uint32_t level;
2258
2259 level = translate_signal_level(signal_levels);
2260
2261 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2262 skl_ddi_set_iboost(dev, level, port, encoder->type);
2263 else if (IS_BROXTON(dev))
2264 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2265
2266 return DDI_BUF_TRANS_SELECT(level);
2267 }
2268
2269 void intel_ddi_clk_select(struct intel_encoder *encoder,
2270 const struct intel_crtc_state *pipe_config)
2271 {
2272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2273 enum port port = intel_ddi_get_encoder_port(encoder);
2274
2275 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2276 uint32_t dpll = pipe_config->ddi_pll_sel;
2277 uint32_t val;
2278
2279 /*
2280 * DPLL0 is used for eDP and is the only "private" DPLL (as
2281 * opposed to shared) on SKL
2282 */
2283 if (encoder->type == INTEL_OUTPUT_EDP) {
2284 WARN_ON(dpll != SKL_DPLL0);
2285
2286 val = I915_READ(DPLL_CTRL1);
2287
2288 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2289 DPLL_CTRL1_SSC(dpll) |
2290 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2291 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
2292
2293 I915_WRITE(DPLL_CTRL1, val);
2294 POSTING_READ(DPLL_CTRL1);
2295 }
2296
2297 /* DDI -> PLL mapping */
2298 val = I915_READ(DPLL_CTRL2);
2299
2300 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2301 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2302 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2303 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2304
2305 I915_WRITE(DPLL_CTRL2, val);
2306
2307 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2308 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2309 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
2310 }
2311 }
2312
2313 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2314 {
2315 struct drm_encoder *encoder = &intel_encoder->base;
2316 struct drm_device *dev = encoder->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2319 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2320 int type = intel_encoder->type;
2321 int hdmi_level;
2322
2323 if (type == INTEL_OUTPUT_EDP) {
2324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2325 intel_edp_panel_on(intel_dp);
2326 }
2327
2328 intel_ddi_clk_select(intel_encoder, crtc->config);
2329
2330 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2332
2333 intel_dp_set_link_params(intel_dp, crtc->config);
2334
2335 intel_ddi_init_dp_buf_reg(intel_encoder);
2336
2337 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2338 intel_dp_start_link_train(intel_dp);
2339 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
2340 intel_dp_stop_link_train(intel_dp);
2341 } else if (type == INTEL_OUTPUT_HDMI) {
2342 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2343
2344 if (IS_BROXTON(dev)) {
2345 hdmi_level = dev_priv->vbt.
2346 ddi_port_info[port].hdmi_level_shift;
2347 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2348 INTEL_OUTPUT_HDMI);
2349 }
2350 intel_hdmi->set_infoframes(encoder,
2351 crtc->config->has_hdmi_sink,
2352 &crtc->config->base.adjusted_mode);
2353 }
2354 }
2355
2356 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2357 {
2358 struct drm_encoder *encoder = &intel_encoder->base;
2359 struct drm_device *dev = encoder->dev;
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2362 int type = intel_encoder->type;
2363 uint32_t val;
2364 bool wait = false;
2365
2366 val = I915_READ(DDI_BUF_CTL(port));
2367 if (val & DDI_BUF_CTL_ENABLE) {
2368 val &= ~DDI_BUF_CTL_ENABLE;
2369 I915_WRITE(DDI_BUF_CTL(port), val);
2370 wait = true;
2371 }
2372
2373 val = I915_READ(DP_TP_CTL(port));
2374 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2375 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2376 I915_WRITE(DP_TP_CTL(port), val);
2377
2378 if (wait)
2379 intel_wait_ddi_buf_idle(dev_priv, port);
2380
2381 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2382 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2383 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2384 intel_edp_panel_vdd_on(intel_dp);
2385 intel_edp_panel_off(intel_dp);
2386 }
2387
2388 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2389 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2390 DPLL_CTRL2_DDI_CLK_OFF(port)));
2391 else if (INTEL_INFO(dev)->gen < 9)
2392 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2393 }
2394
2395 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2396 {
2397 struct drm_encoder *encoder = &intel_encoder->base;
2398 struct drm_crtc *crtc = encoder->crtc;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 struct drm_device *dev = encoder->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2403 int type = intel_encoder->type;
2404
2405 if (type == INTEL_OUTPUT_HDMI) {
2406 struct intel_digital_port *intel_dig_port =
2407 enc_to_dig_port(encoder);
2408
2409 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2410 * are ignored so nothing special needs to be done besides
2411 * enabling the port.
2412 */
2413 I915_WRITE(DDI_BUF_CTL(port),
2414 intel_dig_port->saved_port_bits |
2415 DDI_BUF_CTL_ENABLE);
2416 } else if (type == INTEL_OUTPUT_EDP) {
2417 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2418
2419 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2420 intel_dp_stop_link_train(intel_dp);
2421
2422 intel_edp_backlight_on(intel_dp);
2423 intel_psr_enable(intel_dp);
2424 intel_edp_drrs_enable(intel_dp);
2425 }
2426
2427 if (intel_crtc->config->has_audio) {
2428 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2429 intel_audio_codec_enable(intel_encoder);
2430 }
2431 }
2432
2433 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2434 {
2435 struct drm_encoder *encoder = &intel_encoder->base;
2436 struct drm_crtc *crtc = encoder->crtc;
2437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438 int type = intel_encoder->type;
2439 struct drm_device *dev = encoder->dev;
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441
2442 if (intel_crtc->config->has_audio) {
2443 intel_audio_codec_disable(intel_encoder);
2444 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2445 }
2446
2447 if (type == INTEL_OUTPUT_EDP) {
2448 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2449
2450 intel_edp_drrs_disable(intel_dp);
2451 intel_psr_disable(intel_dp);
2452 intel_edp_backlight_off(intel_dp);
2453 }
2454 }
2455
2456 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2457 struct intel_shared_dpll *pll)
2458 {
2459 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2460 POSTING_READ(WRPLL_CTL(pll->id));
2461 udelay(20);
2462 }
2463
2464 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2465 struct intel_shared_dpll *pll)
2466 {
2467 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2468 POSTING_READ(SPLL_CTL);
2469 udelay(20);
2470 }
2471
2472 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2473 struct intel_shared_dpll *pll)
2474 {
2475 uint32_t val;
2476
2477 val = I915_READ(WRPLL_CTL(pll->id));
2478 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2479 POSTING_READ(WRPLL_CTL(pll->id));
2480 }
2481
2482 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2483 struct intel_shared_dpll *pll)
2484 {
2485 uint32_t val;
2486
2487 val = I915_READ(SPLL_CTL);
2488 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2489 POSTING_READ(SPLL_CTL);
2490 }
2491
2492 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2493 struct intel_shared_dpll *pll,
2494 struct intel_dpll_hw_state *hw_state)
2495 {
2496 uint32_t val;
2497
2498 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2499 return false;
2500
2501 val = I915_READ(WRPLL_CTL(pll->id));
2502 hw_state->wrpll = val;
2503
2504 return val & WRPLL_PLL_ENABLE;
2505 }
2506
2507 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2508 struct intel_shared_dpll *pll,
2509 struct intel_dpll_hw_state *hw_state)
2510 {
2511 uint32_t val;
2512
2513 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2514 return false;
2515
2516 val = I915_READ(SPLL_CTL);
2517 hw_state->spll = val;
2518
2519 return val & SPLL_PLL_ENABLE;
2520 }
2521
2522
2523 static const char * const hsw_ddi_pll_names[] = {
2524 "WRPLL 1",
2525 "WRPLL 2",
2526 "SPLL"
2527 };
2528
2529 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2530 {
2531 int i;
2532
2533 dev_priv->num_shared_dpll = 3;
2534
2535 for (i = 0; i < 2; i++) {
2536 dev_priv->shared_dplls[i].id = i;
2537 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2538 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2539 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2540 dev_priv->shared_dplls[i].get_hw_state =
2541 hsw_ddi_wrpll_get_hw_state;
2542 }
2543
2544 /* SPLL is special, but needs to be initialized anyway.. */
2545 dev_priv->shared_dplls[i].id = i;
2546 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2547 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2548 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2549 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2550
2551 }
2552
2553 static const char * const skl_ddi_pll_names[] = {
2554 "DPLL 1",
2555 "DPLL 2",
2556 "DPLL 3",
2557 };
2558
2559 struct skl_dpll_regs {
2560 i915_reg_t ctl, cfgcr1, cfgcr2;
2561 };
2562
2563 /* this array is indexed by the *shared* pll id */
2564 static const struct skl_dpll_regs skl_dpll_regs[3] = {
2565 {
2566 /* DPLL 1 */
2567 .ctl = LCPLL2_CTL,
2568 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2569 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2570 },
2571 {
2572 /* DPLL 2 */
2573 .ctl = WRPLL_CTL(0),
2574 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2575 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2576 },
2577 {
2578 /* DPLL 3 */
2579 .ctl = WRPLL_CTL(1),
2580 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2581 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2582 },
2583 };
2584
2585 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2586 struct intel_shared_dpll *pll)
2587 {
2588 uint32_t val;
2589 unsigned int dpll;
2590 const struct skl_dpll_regs *regs = skl_dpll_regs;
2591
2592 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2593 dpll = pll->id + 1;
2594
2595 val = I915_READ(DPLL_CTRL1);
2596
2597 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2598 DPLL_CTRL1_LINK_RATE_MASK(dpll));
2599 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2600
2601 I915_WRITE(DPLL_CTRL1, val);
2602 POSTING_READ(DPLL_CTRL1);
2603
2604 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2605 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2606 POSTING_READ(regs[pll->id].cfgcr1);
2607 POSTING_READ(regs[pll->id].cfgcr2);
2608
2609 /* the enable bit is always bit 31 */
2610 I915_WRITE(regs[pll->id].ctl,
2611 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2612
2613 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2614 DRM_ERROR("DPLL %d not locked\n", dpll);
2615 }
2616
2617 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2618 struct intel_shared_dpll *pll)
2619 {
2620 const struct skl_dpll_regs *regs = skl_dpll_regs;
2621
2622 /* the enable bit is always bit 31 */
2623 I915_WRITE(regs[pll->id].ctl,
2624 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2625 POSTING_READ(regs[pll->id].ctl);
2626 }
2627
2628 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2629 struct intel_shared_dpll *pll,
2630 struct intel_dpll_hw_state *hw_state)
2631 {
2632 uint32_t val;
2633 unsigned int dpll;
2634 const struct skl_dpll_regs *regs = skl_dpll_regs;
2635
2636 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2637 return false;
2638
2639 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2640 dpll = pll->id + 1;
2641
2642 val = I915_READ(regs[pll->id].ctl);
2643 if (!(val & LCPLL_PLL_ENABLE))
2644 return false;
2645
2646 val = I915_READ(DPLL_CTRL1);
2647 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2648
2649 /* avoid reading back stale values if HDMI mode is not enabled */
2650 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2651 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2652 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2653 }
2654
2655 return true;
2656 }
2657
2658 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2659 {
2660 int i;
2661
2662 dev_priv->num_shared_dpll = 3;
2663
2664 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2665 dev_priv->shared_dplls[i].id = i;
2666 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2667 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2668 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2669 dev_priv->shared_dplls[i].get_hw_state =
2670 skl_ddi_pll_get_hw_state;
2671 }
2672 }
2673
2674 static void broxton_phy_init(struct drm_i915_private *dev_priv,
2675 enum dpio_phy phy)
2676 {
2677 enum port port;
2678 uint32_t val;
2679
2680 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2681 val |= GT_DISPLAY_POWER_ON(phy);
2682 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2683
2684 /* Considering 10ms timeout until BSpec is updated */
2685 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2686 DRM_ERROR("timeout during PHY%d power on\n", phy);
2687
2688 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2689 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2690 int lane;
2691
2692 for (lane = 0; lane < 4; lane++) {
2693 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2694 /*
2695 * Note that on CHV this flag is called UPAR, but has
2696 * the same function.
2697 */
2698 val &= ~LATENCY_OPTIM;
2699 if (lane != 1)
2700 val |= LATENCY_OPTIM;
2701
2702 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2703 }
2704 }
2705
2706 /* Program PLL Rcomp code offset */
2707 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2708 val &= ~IREF0RC_OFFSET_MASK;
2709 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2710 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2711
2712 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2713 val &= ~IREF1RC_OFFSET_MASK;
2714 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2715 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2716
2717 /* Program power gating */
2718 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2719 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2720 SUS_CLK_CONFIG;
2721 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2722
2723 if (phy == DPIO_PHY0) {
2724 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2725 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2726 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2727 }
2728
2729 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2730 val &= ~OCL2_LDOFUSE_PWR_DIS;
2731 /*
2732 * On PHY1 disable power on the second channel, since no port is
2733 * connected there. On PHY0 both channels have a port, so leave it
2734 * enabled.
2735 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2736 * power down the second channel on PHY0 as well.
2737 */
2738 if (phy == DPIO_PHY1)
2739 val |= OCL2_LDOFUSE_PWR_DIS;
2740 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2741
2742 if (phy == DPIO_PHY0) {
2743 uint32_t grc_code;
2744 /*
2745 * PHY0 isn't connected to an RCOMP resistor so copy over
2746 * the corresponding calibrated value from PHY1, and disable
2747 * the automatic calibration on PHY0.
2748 */
2749 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2750 10))
2751 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2752
2753 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2754 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2755 grc_code = val << GRC_CODE_FAST_SHIFT |
2756 val << GRC_CODE_SLOW_SHIFT |
2757 val;
2758 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2759
2760 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2761 val |= GRC_DIS | GRC_RDY_OVRD;
2762 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2763 }
2764
2765 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2766 val |= COMMON_RESET_DIS;
2767 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2768 }
2769
2770 void broxton_ddi_phy_init(struct drm_device *dev)
2771 {
2772 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2773 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2774 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2775 }
2776
2777 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2778 enum dpio_phy phy)
2779 {
2780 uint32_t val;
2781
2782 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2783 val &= ~COMMON_RESET_DIS;
2784 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2785 }
2786
2787 void broxton_ddi_phy_uninit(struct drm_device *dev)
2788 {
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790
2791 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2792 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2793
2794 /* FIXME: do this in broxton_phy_uninit per phy */
2795 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2796 }
2797
2798 static const char * const bxt_ddi_pll_names[] = {
2799 "PORT PLL A",
2800 "PORT PLL B",
2801 "PORT PLL C",
2802 };
2803
2804 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2805 struct intel_shared_dpll *pll)
2806 {
2807 uint32_t temp;
2808 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2809
2810 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2811 temp &= ~PORT_PLL_REF_SEL;
2812 /* Non-SSC reference */
2813 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2814
2815 /* Disable 10 bit clock */
2816 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2817 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2818 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2819
2820 /* Write P1 & P2 */
2821 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2822 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2823 temp |= pll->config.hw_state.ebb0;
2824 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2825
2826 /* Write M2 integer */
2827 temp = I915_READ(BXT_PORT_PLL(port, 0));
2828 temp &= ~PORT_PLL_M2_MASK;
2829 temp |= pll->config.hw_state.pll0;
2830 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2831
2832 /* Write N */
2833 temp = I915_READ(BXT_PORT_PLL(port, 1));
2834 temp &= ~PORT_PLL_N_MASK;
2835 temp |= pll->config.hw_state.pll1;
2836 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2837
2838 /* Write M2 fraction */
2839 temp = I915_READ(BXT_PORT_PLL(port, 2));
2840 temp &= ~PORT_PLL_M2_FRAC_MASK;
2841 temp |= pll->config.hw_state.pll2;
2842 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2843
2844 /* Write M2 fraction enable */
2845 temp = I915_READ(BXT_PORT_PLL(port, 3));
2846 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2847 temp |= pll->config.hw_state.pll3;
2848 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2849
2850 /* Write coeff */
2851 temp = I915_READ(BXT_PORT_PLL(port, 6));
2852 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2853 temp &= ~PORT_PLL_INT_COEFF_MASK;
2854 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2855 temp |= pll->config.hw_state.pll6;
2856 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2857
2858 /* Write calibration val */
2859 temp = I915_READ(BXT_PORT_PLL(port, 8));
2860 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2861 temp |= pll->config.hw_state.pll8;
2862 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2863
2864 temp = I915_READ(BXT_PORT_PLL(port, 9));
2865 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2866 temp |= pll->config.hw_state.pll9;
2867 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2868
2869 temp = I915_READ(BXT_PORT_PLL(port, 10));
2870 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2871 temp &= ~PORT_PLL_DCO_AMP_MASK;
2872 temp |= pll->config.hw_state.pll10;
2873 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2874
2875 /* Recalibrate with new settings */
2876 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2877 temp |= PORT_PLL_RECALIBRATE;
2878 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2879 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2880 temp |= pll->config.hw_state.ebb4;
2881 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2882
2883 /* Enable PLL */
2884 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2885 temp |= PORT_PLL_ENABLE;
2886 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2887 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2888
2889 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2890 PORT_PLL_LOCK), 200))
2891 DRM_ERROR("PLL %d not locked\n", port);
2892
2893 /*
2894 * While we write to the group register to program all lanes at once we
2895 * can read only lane registers and we pick lanes 0/1 for that.
2896 */
2897 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2898 temp &= ~LANE_STAGGER_MASK;
2899 temp &= ~LANESTAGGER_STRAP_OVRD;
2900 temp |= pll->config.hw_state.pcsdw12;
2901 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2902 }
2903
2904 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2905 struct intel_shared_dpll *pll)
2906 {
2907 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2908 uint32_t temp;
2909
2910 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2911 temp &= ~PORT_PLL_ENABLE;
2912 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2913 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2914 }
2915
2916 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2917 struct intel_shared_dpll *pll,
2918 struct intel_dpll_hw_state *hw_state)
2919 {
2920 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2921 uint32_t val;
2922
2923 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2924 return false;
2925
2926 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2927 if (!(val & PORT_PLL_ENABLE))
2928 return false;
2929
2930 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2931 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2932
2933 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2934 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2935
2936 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2937 hw_state->pll0 &= PORT_PLL_M2_MASK;
2938
2939 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2940 hw_state->pll1 &= PORT_PLL_N_MASK;
2941
2942 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2943 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2944
2945 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2946 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2947
2948 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2949 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2950 PORT_PLL_INT_COEFF_MASK |
2951 PORT_PLL_GAIN_CTL_MASK;
2952
2953 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2954 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2955
2956 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2957 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2958
2959 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2960 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2961 PORT_PLL_DCO_AMP_MASK;
2962
2963 /*
2964 * While we write to the group register to program all lanes at once we
2965 * can read only lane registers. We configure all lanes the same way, so
2966 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2967 */
2968 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2969 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2970 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2971 hw_state->pcsdw12,
2972 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2973 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2974
2975 return true;
2976 }
2977
2978 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2979 {
2980 int i;
2981
2982 dev_priv->num_shared_dpll = 3;
2983
2984 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2985 dev_priv->shared_dplls[i].id = i;
2986 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2987 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2988 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2989 dev_priv->shared_dplls[i].get_hw_state =
2990 bxt_ddi_pll_get_hw_state;
2991 }
2992 }
2993
2994 void intel_ddi_pll_init(struct drm_device *dev)
2995 {
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 uint32_t val = I915_READ(LCPLL_CTL);
2998
2999 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
3000 skl_shared_dplls_init(dev_priv);
3001 else if (IS_BROXTON(dev))
3002 bxt_shared_dplls_init(dev_priv);
3003 else
3004 hsw_shared_dplls_init(dev_priv);
3005
3006 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
3007 int cdclk_freq;
3008
3009 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
3010 dev_priv->skl_boot_cdclk = cdclk_freq;
3011 if (skl_sanitize_cdclk(dev_priv))
3012 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
3013 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3014 DRM_ERROR("LCPLL1 is disabled\n");
3015 } else if (IS_BROXTON(dev)) {
3016 broxton_init_cdclk(dev);
3017 broxton_ddi_phy_init(dev);
3018 } else {
3019 /*
3020 * The LCPLL register should be turned on by the BIOS. For now
3021 * let's just check its state and print errors in case
3022 * something is wrong. Don't even try to turn it on.
3023 */
3024
3025 if (val & LCPLL_CD_SOURCE_FCLK)
3026 DRM_ERROR("CDCLK source is not LCPLL\n");
3027
3028 if (val & LCPLL_PLL_DISABLE)
3029 DRM_ERROR("LCPLL is disabled\n");
3030 }
3031 }
3032
3033 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3034 {
3035 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3036 struct drm_i915_private *dev_priv =
3037 to_i915(intel_dig_port->base.base.dev);
3038 enum port port = intel_dig_port->port;
3039 uint32_t val;
3040 bool wait = false;
3041
3042 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3043 val = I915_READ(DDI_BUF_CTL(port));
3044 if (val & DDI_BUF_CTL_ENABLE) {
3045 val &= ~DDI_BUF_CTL_ENABLE;
3046 I915_WRITE(DDI_BUF_CTL(port), val);
3047 wait = true;
3048 }
3049
3050 val = I915_READ(DP_TP_CTL(port));
3051 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3052 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3053 I915_WRITE(DP_TP_CTL(port), val);
3054 POSTING_READ(DP_TP_CTL(port));
3055
3056 if (wait)
3057 intel_wait_ddi_buf_idle(dev_priv, port);
3058 }
3059
3060 val = DP_TP_CTL_ENABLE |
3061 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3062 if (intel_dp->is_mst)
3063 val |= DP_TP_CTL_MODE_MST;
3064 else {
3065 val |= DP_TP_CTL_MODE_SST;
3066 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3067 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3068 }
3069 I915_WRITE(DP_TP_CTL(port), val);
3070 POSTING_READ(DP_TP_CTL(port));
3071
3072 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3073 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3074 POSTING_READ(DDI_BUF_CTL(port));
3075
3076 udelay(600);
3077 }
3078
3079 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3080 {
3081 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3082 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3083 uint32_t val;
3084
3085 intel_ddi_post_disable(intel_encoder);
3086
3087 val = I915_READ(FDI_RX_CTL(PIPE_A));
3088 val &= ~FDI_RX_ENABLE;
3089 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3090
3091 val = I915_READ(FDI_RX_MISC(PIPE_A));
3092 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3093 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3094 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3095
3096 val = I915_READ(FDI_RX_CTL(PIPE_A));
3097 val &= ~FDI_PCDCLK;
3098 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3099
3100 val = I915_READ(FDI_RX_CTL(PIPE_A));
3101 val &= ~FDI_RX_PLL_ENABLE;
3102 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3103 }
3104
3105 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3106 struct intel_crtc *intel_crtc)
3107 {
3108 u32 temp;
3109
3110 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3111 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3112 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3113 return true;
3114 }
3115 return false;
3116 }
3117
3118 void intel_ddi_get_config(struct intel_encoder *encoder,
3119 struct intel_crtc_state *pipe_config)
3120 {
3121 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3122 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3123 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3124 struct intel_hdmi *intel_hdmi;
3125 u32 temp, flags = 0;
3126
3127 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3128 if (temp & TRANS_DDI_PHSYNC)
3129 flags |= DRM_MODE_FLAG_PHSYNC;
3130 else
3131 flags |= DRM_MODE_FLAG_NHSYNC;
3132 if (temp & TRANS_DDI_PVSYNC)
3133 flags |= DRM_MODE_FLAG_PVSYNC;
3134 else
3135 flags |= DRM_MODE_FLAG_NVSYNC;
3136
3137 pipe_config->base.adjusted_mode.flags |= flags;
3138
3139 switch (temp & TRANS_DDI_BPC_MASK) {
3140 case TRANS_DDI_BPC_6:
3141 pipe_config->pipe_bpp = 18;
3142 break;
3143 case TRANS_DDI_BPC_8:
3144 pipe_config->pipe_bpp = 24;
3145 break;
3146 case TRANS_DDI_BPC_10:
3147 pipe_config->pipe_bpp = 30;
3148 break;
3149 case TRANS_DDI_BPC_12:
3150 pipe_config->pipe_bpp = 36;
3151 break;
3152 default:
3153 break;
3154 }
3155
3156 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3157 case TRANS_DDI_MODE_SELECT_HDMI:
3158 pipe_config->has_hdmi_sink = true;
3159 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3160
3161 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
3162 pipe_config->has_infoframe = true;
3163 break;
3164 case TRANS_DDI_MODE_SELECT_DVI:
3165 case TRANS_DDI_MODE_SELECT_FDI:
3166 break;
3167 case TRANS_DDI_MODE_SELECT_DP_SST:
3168 case TRANS_DDI_MODE_SELECT_DP_MST:
3169 pipe_config->has_dp_encoder = true;
3170 pipe_config->lane_count =
3171 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3172 intel_dp_get_m_n(intel_crtc, pipe_config);
3173 break;
3174 default:
3175 break;
3176 }
3177
3178 pipe_config->has_audio =
3179 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
3180
3181 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3182 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3183 /*
3184 * This is a big fat ugly hack.
3185 *
3186 * Some machines in UEFI boot mode provide us a VBT that has 18
3187 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3188 * unknown we fail to light up. Yet the same BIOS boots up with
3189 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3190 * max, not what it tells us to use.
3191 *
3192 * Note: This will still be broken if the eDP panel is not lit
3193 * up by the BIOS, and thus we can't get the mode at module
3194 * load.
3195 */
3196 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3197 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3198 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3199 }
3200
3201 intel_ddi_clock_get(encoder, pipe_config);
3202 }
3203
3204 static void intel_ddi_destroy(struct drm_encoder *encoder)
3205 {
3206 /* HDMI has nothing special to destroy, so we can go with this. */
3207 intel_dp_encoder_destroy(encoder);
3208 }
3209
3210 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3211 struct intel_crtc_state *pipe_config)
3212 {
3213 int type = encoder->type;
3214 int port = intel_ddi_get_encoder_port(encoder);
3215
3216 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3217
3218 if (port == PORT_A)
3219 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3220
3221 if (type == INTEL_OUTPUT_HDMI)
3222 return intel_hdmi_compute_config(encoder, pipe_config);
3223 else
3224 return intel_dp_compute_config(encoder, pipe_config);
3225 }
3226
3227 static const struct drm_encoder_funcs intel_ddi_funcs = {
3228 .destroy = intel_ddi_destroy,
3229 };
3230
3231 static struct intel_connector *
3232 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3233 {
3234 struct intel_connector *connector;
3235 enum port port = intel_dig_port->port;
3236
3237 connector = intel_connector_alloc();
3238 if (!connector)
3239 return NULL;
3240
3241 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3242 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3243 kfree(connector);
3244 return NULL;
3245 }
3246
3247 return connector;
3248 }
3249
3250 static struct intel_connector *
3251 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3252 {
3253 struct intel_connector *connector;
3254 enum port port = intel_dig_port->port;
3255
3256 connector = intel_connector_alloc();
3257 if (!connector)
3258 return NULL;
3259
3260 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3261 intel_hdmi_init_connector(intel_dig_port, connector);
3262
3263 return connector;
3264 }
3265
3266 void intel_ddi_init(struct drm_device *dev, enum port port)
3267 {
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_digital_port *intel_dig_port;
3270 struct intel_encoder *intel_encoder;
3271 struct drm_encoder *encoder;
3272 bool init_hdmi, init_dp;
3273 int max_lanes;
3274
3275 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3276 switch (port) {
3277 case PORT_A:
3278 max_lanes = 4;
3279 break;
3280 case PORT_E:
3281 max_lanes = 0;
3282 break;
3283 default:
3284 max_lanes = 4;
3285 break;
3286 }
3287 } else {
3288 switch (port) {
3289 case PORT_A:
3290 max_lanes = 2;
3291 break;
3292 case PORT_E:
3293 max_lanes = 2;
3294 break;
3295 default:
3296 max_lanes = 4;
3297 break;
3298 }
3299 }
3300
3301 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3302 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3303 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3304 if (!init_dp && !init_hdmi) {
3305 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3306 port_name(port));
3307 return;
3308 }
3309
3310 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3311 if (!intel_dig_port)
3312 return;
3313
3314 intel_encoder = &intel_dig_port->base;
3315 encoder = &intel_encoder->base;
3316
3317 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3318 DRM_MODE_ENCODER_TMDS);
3319
3320 intel_encoder->compute_config = intel_ddi_compute_config;
3321 intel_encoder->enable = intel_enable_ddi;
3322 intel_encoder->pre_enable = intel_ddi_pre_enable;
3323 intel_encoder->disable = intel_disable_ddi;
3324 intel_encoder->post_disable = intel_ddi_post_disable;
3325 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3326 intel_encoder->get_config = intel_ddi_get_config;
3327
3328 intel_dig_port->port = port;
3329 dev_priv->dig_port_map[port] = intel_encoder;
3330 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3331 (DDI_BUF_PORT_REVERSAL |
3332 DDI_A_4_LANES);
3333 intel_dig_port->max_lanes = max_lanes;
3334
3335 /*
3336 * Bspec says that DDI_A_4_LANES is the only supported configuration
3337 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3338 * wasn't lit up at boot. Force this bit on in our internal
3339 * configuration so that we use the proper lane count for our
3340 * calculations.
3341 */
3342 if (IS_BROXTON(dev) && port == PORT_A) {
3343 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3344 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3345 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3346 }
3347 }
3348
3349 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3350 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3351 intel_encoder->cloneable = 0;
3352
3353 if (init_dp) {
3354 if (!intel_ddi_init_dp_connector(intel_dig_port))
3355 goto err;
3356
3357 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3358 /*
3359 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3360 * interrupts to check the external panel connection.
3361 */
3362 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
3363 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3364 else
3365 dev_priv->hotplug.irq_port[port] = intel_dig_port;
3366 }
3367
3368 /* In theory we don't need the encoder->type check, but leave it just in
3369 * case we have some really bad VBTs... */
3370 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3371 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3372 goto err;
3373 }
3374
3375 return;
3376
3377 err:
3378 drm_encoder_cleanup(encoder);
3379 kfree(intel_dig_port);
3380 }
Linux kernel - Deliverables
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