projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 /* hrawclock is 1/4 the FSB frequency */
146 int intel_hrawclk(struct drm_device *dev)
147 {
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 uint32_t clkcfg;
150
151 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
152 if (IS_VALLEYVIEW(dev))
153 return 200;
154
155 clkcfg = I915_READ(CLKCFG);
156 switch (clkcfg & CLKCFG_FSB_MASK) {
157 case CLKCFG_FSB_400:
158 return 100;
159 case CLKCFG_FSB_533:
160 return 133;
161 case CLKCFG_FSB_667:
162 return 166;
163 case CLKCFG_FSB_800:
164 return 200;
165 case CLKCFG_FSB_1067:
166 return 266;
167 case CLKCFG_FSB_1333:
168 return 333;
169 /* these two are just a guess; one of them might be right */
170 case CLKCFG_FSB_1600:
171 case CLKCFG_FSB_1600_ALT:
172 return 400;
173 default:
174 return 133;
175 }
176 }
177
178 static inline u32 /* units of 100MHz */
179 intel_fdi_link_freq(struct drm_device *dev)
180 {
181 if (IS_GEN5(dev)) {
182 struct drm_i915_private *dev_priv = dev->dev_private;
183 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
184 } else
185 return 27;
186 }
187
188 static const intel_limit_t intel_limits_i8xx_dac = {
189 .dot = { .min = 25000, .max = 350000 },
190 .vco = { .min = 908000, .max = 1512000 },
191 .n = { .min = 2, .max = 16 },
192 .m = { .min = 96, .max = 140 },
193 .m1 = { .min = 18, .max = 26 },
194 .m2 = { .min = 6, .max = 16 },
195 .p = { .min = 4, .max = 128 },
196 .p1 = { .min = 2, .max = 33 },
197 .p2 = { .dot_limit = 165000,
198 .p2_slow = 4, .p2_fast = 2 },
199 };
200
201 static const intel_limit_t intel_limits_i8xx_dvo = {
202 .dot = { .min = 25000, .max = 350000 },
203 .vco = { .min = 908000, .max = 1512000 },
204 .n = { .min = 2, .max = 16 },
205 .m = { .min = 96, .max = 140 },
206 .m1 = { .min = 18, .max = 26 },
207 .m2 = { .min = 6, .max = 16 },
208 .p = { .min = 4, .max = 128 },
209 .p1 = { .min = 2, .max = 33 },
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 4, .p2_fast = 4 },
212 };
213
214 static const intel_limit_t intel_limits_i8xx_lvds = {
215 .dot = { .min = 25000, .max = 350000 },
216 .vco = { .min = 908000, .max = 1512000 },
217 .n = { .min = 2, .max = 16 },
218 .m = { .min = 96, .max = 140 },
219 .m1 = { .min = 18, .max = 26 },
220 .m2 = { .min = 6, .max = 16 },
221 .p = { .min = 4, .max = 128 },
222 .p1 = { .min = 1, .max = 6 },
223 .p2 = { .dot_limit = 165000,
224 .p2_slow = 14, .p2_fast = 7 },
225 };
226
227 static const intel_limit_t intel_limits_i9xx_sdvo = {
228 .dot = { .min = 20000, .max = 400000 },
229 .vco = { .min = 1400000, .max = 2800000 },
230 .n = { .min = 1, .max = 6 },
231 .m = { .min = 70, .max = 120 },
232 .m1 = { .min = 8, .max = 18 },
233 .m2 = { .min = 3, .max = 7 },
234 .p = { .min = 5, .max = 80 },
235 .p1 = { .min = 1, .max = 8 },
236 .p2 = { .dot_limit = 200000,
237 .p2_slow = 10, .p2_fast = 5 },
238 };
239
240 static const intel_limit_t intel_limits_i9xx_lvds = {
241 .dot = { .min = 20000, .max = 400000 },
242 .vco = { .min = 1400000, .max = 2800000 },
243 .n = { .min = 1, .max = 6 },
244 .m = { .min = 70, .max = 120 },
245 .m1 = { .min = 8, .max = 18 },
246 .m2 = { .min = 3, .max = 7 },
247 .p = { .min = 7, .max = 98 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 112000,
250 .p2_slow = 14, .p2_fast = 7 },
251 };
252
253
254 static const intel_limit_t intel_limits_g4x_sdvo = {
255 .dot = { .min = 25000, .max = 270000 },
256 .vco = { .min = 1750000, .max = 3500000},
257 .n = { .min = 1, .max = 4 },
258 .m = { .min = 104, .max = 138 },
259 .m1 = { .min = 17, .max = 23 },
260 .m2 = { .min = 5, .max = 11 },
261 .p = { .min = 10, .max = 30 },
262 .p1 = { .min = 1, .max = 3},
263 .p2 = { .dot_limit = 270000,
264 .p2_slow = 10,
265 .p2_fast = 10
266 },
267 };
268
269 static const intel_limit_t intel_limits_g4x_hdmi = {
270 .dot = { .min = 22000, .max = 400000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 16, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8},
278 .p2 = { .dot_limit = 165000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
283 .dot = { .min = 20000, .max = 115000 },
284 .vco = { .min = 1750000, .max = 3500000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 104, .max = 138 },
287 .m1 = { .min = 17, .max = 23 },
288 .m2 = { .min = 5, .max = 11 },
289 .p = { .min = 28, .max = 112 },
290 .p1 = { .min = 2, .max = 8 },
291 .p2 = { .dot_limit = 0,
292 .p2_slow = 14, .p2_fast = 14
293 },
294 };
295
296 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
297 .dot = { .min = 80000, .max = 224000 },
298 .vco = { .min = 1750000, .max = 3500000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 104, .max = 138 },
301 .m1 = { .min = 17, .max = 23 },
302 .m2 = { .min = 5, .max = 11 },
303 .p = { .min = 14, .max = 42 },
304 .p1 = { .min = 2, .max = 6 },
305 .p2 = { .dot_limit = 0,
306 .p2_slow = 7, .p2_fast = 7
307 },
308 };
309
310 static const intel_limit_t intel_limits_pineview_sdvo = {
311 .dot = { .min = 20000, .max = 400000},
312 .vco = { .min = 1700000, .max = 3500000 },
313 /* Pineview's Ncounter is a ring counter */
314 .n = { .min = 3, .max = 6 },
315 .m = { .min = 2, .max = 256 },
316 /* Pineview only has one combined m divider, which we treat as m2. */
317 .m1 = { .min = 0, .max = 0 },
318 .m2 = { .min = 0, .max = 254 },
319 .p = { .min = 5, .max = 80 },
320 .p1 = { .min = 1, .max = 8 },
321 .p2 = { .dot_limit = 200000,
322 .p2_slow = 10, .p2_fast = 5 },
323 };
324
325 static const intel_limit_t intel_limits_pineview_lvds = {
326 .dot = { .min = 20000, .max = 400000 },
327 .vco = { .min = 1700000, .max = 3500000 },
328 .n = { .min = 3, .max = 6 },
329 .m = { .min = 2, .max = 256 },
330 .m1 = { .min = 0, .max = 0 },
331 .m2 = { .min = 0, .max = 254 },
332 .p = { .min = 7, .max = 112 },
333 .p1 = { .min = 1, .max = 8 },
334 .p2 = { .dot_limit = 112000,
335 .p2_slow = 14, .p2_fast = 14 },
336 };
337
338 /* Ironlake / Sandybridge
339 *
340 * We calculate clock using (register_value + 2) for N/M1/M2, so here
341 * the range value for them is (actual_value - 2).
342 */
343 static const intel_limit_t intel_limits_ironlake_dac = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 5 },
347 .m = { .min = 79, .max = 127 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_single_lvds = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 118 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 14, .p2_fast = 14 },
367 };
368
369 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
370 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = 1760000, .max = 3510000 },
372 .n = { .min = 1, .max = 3 },
373 .m = { .min = 79, .max = 127 },
374 .m1 = { .min = 12, .max = 22 },
375 .m2 = { .min = 5, .max = 9 },
376 .p = { .min = 14, .max = 56 },
377 .p1 = { .min = 2, .max = 8 },
378 .p2 = { .dot_limit = 225000,
379 .p2_slow = 7, .p2_fast = 7 },
380 };
381
382 /* LVDS 100mhz refclk limits. */
383 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 2 },
387 .m = { .min = 79, .max = 126 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 28, .max = 112 },
391 .p1 = { .min = 2, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 14, .p2_fast = 14 },
394 };
395
396 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 126 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 14, .max = 42 },
404 .p1 = { .min = 2, .max = 6 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 7, .p2_fast = 7 },
407 };
408
409 static const intel_limit_t intel_limits_vlv = {
410 /*
411 * These are the data rate limits (measured in fast clocks)
412 * since those are the strictest limits we have. The fast
413 * clock and actual rate limits are more relaxed, so checking
414 * them would make no difference.
415 */
416 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
417 .vco = { .min = 4000000, .max = 6000000 },
418 .n = { .min = 1, .max = 7 },
419 .m1 = { .min = 2, .max = 3 },
420 .m2 = { .min = 11, .max = 156 },
421 .p1 = { .min = 2, .max = 3 },
422 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
423 };
424
425 static const intel_limit_t intel_limits_chv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 540000 * 5},
433 .vco = { .min = 4800000, .max = 6480000 },
434 .n = { .min = 1, .max = 1 },
435 .m1 = { .min = 2, .max = 2 },
436 .m2 = { .min = 24 << 22, .max = 175 << 22 },
437 .p1 = { .min = 2, .max = 4 },
438 .p2 = { .p2_slow = 1, .p2_fast = 14 },
439 };
440
441 static const intel_limit_t intel_limits_bxt = {
442 /* FIXME: find real dot limits */
443 .dot = { .min = 0, .max = INT_MAX },
444 .vco = { .min = 4800000, .max = 6700000 },
445 .n = { .min = 1, .max = 1 },
446 .m1 = { .min = 2, .max = 2 },
447 /* FIXME: find real m2 limits */
448 .m2 = { .min = 2 << 22, .max = 255 << 22 },
449 .p1 = { .min = 2, .max = 4 },
450 .p2 = { .p2_slow = 1, .p2_fast = 20 },
451 };
452
453 static bool
454 needs_modeset(struct drm_crtc_state *state)
455 {
456 return drm_atomic_crtc_needs_modeset(state);
457 }
458
459 /**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
462 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
463 {
464 struct drm_device *dev = crtc->base.dev;
465 struct intel_encoder *encoder;
466
467 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
468 if (encoder->type == type)
469 return true;
470
471 return false;
472 }
473
474 /**
475 * Returns whether any output on the specified pipe will have the specified
476 * type after a staged modeset is complete, i.e., the same as
477 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
478 * encoder->crtc.
479 */
480 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
481 int type)
482 {
483 struct drm_atomic_state *state = crtc_state->base.state;
484 struct drm_connector *connector;
485 struct drm_connector_state *connector_state;
486 struct intel_encoder *encoder;
487 int i, num_connectors = 0;
488
489 for_each_connector_in_state(state, connector, connector_state, i) {
490 if (connector_state->crtc != crtc_state->base.crtc)
491 continue;
492
493 num_connectors++;
494
495 encoder = to_intel_encoder(connector_state->best_encoder);
496 if (encoder->type == type)
497 return true;
498 }
499
500 WARN_ON(num_connectors == 0);
501
502 return false;
503 }
504
505 static const intel_limit_t *
506 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
507 {
508 struct drm_device *dev = crtc_state->base.crtc->dev;
509 const intel_limit_t *limit;
510
511 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
512 if (intel_is_dual_link_lvds(dev)) {
513 if (refclk == 100000)
514 limit = &intel_limits_ironlake_dual_lvds_100m;
515 else
516 limit = &intel_limits_ironlake_dual_lvds;
517 } else {
518 if (refclk == 100000)
519 limit = &intel_limits_ironlake_single_lvds_100m;
520 else
521 limit = &intel_limits_ironlake_single_lvds;
522 }
523 } else
524 limit = &intel_limits_ironlake_dac;
525
526 return limit;
527 }
528
529 static const intel_limit_t *
530 intel_g4x_limit(struct intel_crtc_state *crtc_state)
531 {
532 struct drm_device *dev = crtc_state->base.crtc->dev;
533 const intel_limit_t *limit;
534
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
536 if (intel_is_dual_link_lvds(dev))
537 limit = &intel_limits_g4x_dual_channel_lvds;
538 else
539 limit = &intel_limits_g4x_single_channel_lvds;
540 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
541 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
542 limit = &intel_limits_g4x_hdmi;
543 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
544 limit = &intel_limits_g4x_sdvo;
545 } else /* The option is for other outputs */
546 limit = &intel_limits_i9xx_sdvo;
547
548 return limit;
549 }
550
551 static const intel_limit_t *
552 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
553 {
554 struct drm_device *dev = crtc_state->base.crtc->dev;
555 const intel_limit_t *limit;
556
557 if (IS_BROXTON(dev))
558 limit = &intel_limits_bxt;
559 else if (HAS_PCH_SPLIT(dev))
560 limit = intel_ironlake_limit(crtc_state, refclk);
561 else if (IS_G4X(dev)) {
562 limit = intel_g4x_limit(crtc_state);
563 } else if (IS_PINEVIEW(dev)) {
564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
565 limit = &intel_limits_pineview_lvds;
566 else
567 limit = &intel_limits_pineview_sdvo;
568 } else if (IS_CHERRYVIEW(dev)) {
569 limit = &intel_limits_chv;
570 } else if (IS_VALLEYVIEW(dev)) {
571 limit = &intel_limits_vlv;
572 } else if (!IS_GEN2(dev)) {
573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
574 limit = &intel_limits_i9xx_lvds;
575 else
576 limit = &intel_limits_i9xx_sdvo;
577 } else {
578 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_i8xx_lvds;
580 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
581 limit = &intel_limits_i8xx_dvo;
582 else
583 limit = &intel_limits_i8xx_dac;
584 }
585 return limit;
586 }
587
588 /*
589 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
590 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
591 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
592 * The helpers' return value is the rate of the clock that is fed to the
593 * display engine's pipe which can be the above fast dot clock rate or a
594 * divided-down version of it.
595 */
596 /* m1 is reserved as 0 in Pineview, n is a ring counter */
597 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
598 {
599 clock->m = clock->m2 + 2;
600 clock->p = clock->p1 * clock->p2;
601 if (WARN_ON(clock->n == 0 || clock->p == 0))
602 return 0;
603 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
604 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
605
606 return clock->dot;
607 }
608
609 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
610 {
611 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
612 }
613
614 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
615 {
616 clock->m = i9xx_dpll_compute_m(clock);
617 clock->p = clock->p1 * clock->p2;
618 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
619 return 0;
620 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
621 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
622
623 return clock->dot;
624 }
625
626 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
627 {
628 clock->m = clock->m1 * clock->m2;
629 clock->p = clock->p1 * clock->p2;
630 if (WARN_ON(clock->n == 0 || clock->p == 0))
631 return 0;
632 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634
635 return clock->dot / 5;
636 }
637
638 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
639 {
640 clock->m = clock->m1 * clock->m2;
641 clock->p = clock->p1 * clock->p2;
642 if (WARN_ON(clock->n == 0 || clock->p == 0))
643 return 0;
644 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
645 clock->n << 22);
646 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
647
648 return clock->dot / 5;
649 }
650
651 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
652 /**
653 * Returns whether the given set of divisors are valid for a given refclk with
654 * the given connectors.
655 */
656
657 static bool intel_PLL_is_valid(struct drm_device *dev,
658 const intel_limit_t *limit,
659 const intel_clock_t *clock)
660 {
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
664 INTELPllInvalid("p1 out of range\n");
665 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
666 INTELPllInvalid("m2 out of range\n");
667 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
668 INTELPllInvalid("m1 out of range\n");
669
670 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
671 if (clock->m1 <= clock->m2)
672 INTELPllInvalid("m1 <= m2\n");
673
674 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
675 if (clock->p < limit->p.min || limit->p.max < clock->p)
676 INTELPllInvalid("p out of range\n");
677 if (clock->m < limit->m.min || limit->m.max < clock->m)
678 INTELPllInvalid("m out of range\n");
679 }
680
681 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
682 INTELPllInvalid("vco out of range\n");
683 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
684 * connector, etc., rather than just a single range.
685 */
686 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
687 INTELPllInvalid("dot out of range\n");
688
689 return true;
690 }
691
692 static int
693 i9xx_select_p2_div(const intel_limit_t *limit,
694 const struct intel_crtc_state *crtc_state,
695 int target)
696 {
697 struct drm_device *dev = crtc_state->base.crtc->dev;
698
699 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
700 /*
701 * For LVDS just rely on its current settings for dual-channel.
702 * We haven't figured out how to reliably set up different
703 * single/dual channel state, if we even can.
704 */
705 if (intel_is_dual_link_lvds(dev))
706 return limit->p2.p2_fast;
707 else
708 return limit->p2.p2_slow;
709 } else {
710 if (target < limit->p2.dot_limit)
711 return limit->p2.p2_slow;
712 else
713 return limit->p2.p2_fast;
714 }
715 }
716
717 static bool
718 i9xx_find_best_dpll(const intel_limit_t *limit,
719 struct intel_crtc_state *crtc_state,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc_state->base.crtc->dev;
724 intel_clock_t clock;
725 int err = target;
726
727 memset(best_clock, 0, sizeof(*best_clock));
728
729 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
730
731 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
732 clock.m1++) {
733 for (clock.m2 = limit->m2.min;
734 clock.m2 <= limit->m2.max; clock.m2++) {
735 if (clock.m2 >= clock.m1)
736 break;
737 for (clock.n = limit->n.min;
738 clock.n <= limit->n.max; clock.n++) {
739 for (clock.p1 = limit->p1.min;
740 clock.p1 <= limit->p1.max; clock.p1++) {
741 int this_err;
742
743 i9xx_calc_dpll_params(refclk, &clock);
744 if (!intel_PLL_is_valid(dev, limit,
745 &clock))
746 continue;
747 if (match_clock &&
748 clock.p != match_clock->p)
749 continue;
750
751 this_err = abs(clock.dot - target);
752 if (this_err < err) {
753 *best_clock = clock;
754 err = this_err;
755 }
756 }
757 }
758 }
759 }
760
761 return (err != target);
762 }
763
764 static bool
765 pnv_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 for (clock.n = limit->n.min;
783 clock.n <= limit->n.max; clock.n++) {
784 for (clock.p1 = limit->p1.min;
785 clock.p1 <= limit->p1.max; clock.p1++) {
786 int this_err;
787
788 pnv_calc_dpll_params(refclk, &clock);
789 if (!intel_PLL_is_valid(dev, limit,
790 &clock))
791 continue;
792 if (match_clock &&
793 clock.p != match_clock->p)
794 continue;
795
796 this_err = abs(clock.dot - target);
797 if (this_err < err) {
798 *best_clock = clock;
799 err = this_err;
800 }
801 }
802 }
803 }
804 }
805
806 return (err != target);
807 }
808
809 static bool
810 g4x_find_best_dpll(const intel_limit_t *limit,
811 struct intel_crtc_state *crtc_state,
812 int target, int refclk, intel_clock_t *match_clock,
813 intel_clock_t *best_clock)
814 {
815 struct drm_device *dev = crtc_state->base.crtc->dev;
816 intel_clock_t clock;
817 int max_n;
818 bool found = false;
819 /* approximately equals target * 0.00585 */
820 int err_most = (target >> 8) + (target >> 9);
821
822 memset(best_clock, 0, sizeof(*best_clock));
823
824 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
825
826 max_n = limit->n.max;
827 /* based on hardware requirement, prefer smaller n to precision */
828 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
829 /* based on hardware requirement, prefere larger m1,m2 */
830 for (clock.m1 = limit->m1.max;
831 clock.m1 >= limit->m1.min; clock.m1--) {
832 for (clock.m2 = limit->m2.max;
833 clock.m2 >= limit->m2.min; clock.m2--) {
834 for (clock.p1 = limit->p1.max;
835 clock.p1 >= limit->p1.min; clock.p1--) {
836 int this_err;
837
838 i9xx_calc_dpll_params(refclk, &clock);
839 if (!intel_PLL_is_valid(dev, limit,
840 &clock))
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err_most) {
845 *best_clock = clock;
846 err_most = this_err;
847 max_n = clock.n;
848 found = true;
849 }
850 }
851 }
852 }
853 }
854 return found;
855 }
856
857 /*
858 * Check if the calculated PLL configuration is more optimal compared to the
859 * best configuration and error found so far. Return the calculated error.
860 */
861 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
862 const intel_clock_t *calculated_clock,
863 const intel_clock_t *best_clock,
864 unsigned int best_error_ppm,
865 unsigned int *error_ppm)
866 {
867 /*
868 * For CHV ignore the error and consider only the P value.
869 * Prefer a bigger P value based on HW requirements.
870 */
871 if (IS_CHERRYVIEW(dev)) {
872 *error_ppm = 0;
873
874 return calculated_clock->p > best_clock->p;
875 }
876
877 if (WARN_ON_ONCE(!target_freq))
878 return false;
879
880 *error_ppm = div_u64(1000000ULL *
881 abs(target_freq - calculated_clock->dot),
882 target_freq);
883 /*
884 * Prefer a better P value over a better (smaller) error if the error
885 * is small. Ensure this preference for future configurations too by
886 * setting the error to 0.
887 */
888 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
889 *error_ppm = 0;
890
891 return true;
892 }
893
894 return *error_ppm + 10 < best_error_ppm;
895 }
896
897 static bool
898 vlv_find_best_dpll(const intel_limit_t *limit,
899 struct intel_crtc_state *crtc_state,
900 int target, int refclk, intel_clock_t *match_clock,
901 intel_clock_t *best_clock)
902 {
903 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
904 struct drm_device *dev = crtc->base.dev;
905 intel_clock_t clock;
906 unsigned int bestppm = 1000000;
907 /* min update 19.2 MHz */
908 int max_n = min(limit->n.max, refclk / 19200);
909 bool found = false;
910
911 target *= 5; /* fast clock */
912
913 memset(best_clock, 0, sizeof(*best_clock));
914
915 /* based on hardware requirement, prefer smaller n to precision */
916 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
917 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
918 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
919 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
920 clock.p = clock.p1 * clock.p2;
921 /* based on hardware requirement, prefer bigger m1,m2 values */
922 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
923 unsigned int ppm;
924
925 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
926 refclk * clock.m1);
927
928 vlv_calc_dpll_params(refclk, &clock);
929
930 if (!intel_PLL_is_valid(dev, limit,
931 &clock))
932 continue;
933
934 if (!vlv_PLL_is_optimal(dev, target,
935 &clock,
936 best_clock,
937 bestppm, &ppm))
938 continue;
939
940 *best_clock = clock;
941 bestppm = ppm;
942 found = true;
943 }
944 }
945 }
946 }
947
948 return found;
949 }
950
951 static bool
952 chv_find_best_dpll(const intel_limit_t *limit,
953 struct intel_crtc_state *crtc_state,
954 int target, int refclk, intel_clock_t *match_clock,
955 intel_clock_t *best_clock)
956 {
957 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
958 struct drm_device *dev = crtc->base.dev;
959 unsigned int best_error_ppm;
960 intel_clock_t clock;
961 uint64_t m2;
962 int found = false;
963
964 memset(best_clock, 0, sizeof(*best_clock));
965 best_error_ppm = 1000000;
966
967 /*
968 * Based on hardware doc, the n always set to 1, and m1 always
969 * set to 2. If requires to support 200Mhz refclk, we need to
970 * revisit this because n may not 1 anymore.
971 */
972 clock.n = 1, clock.m1 = 2;
973 target *= 5; /* fast clock */
974
975 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
976 for (clock.p2 = limit->p2.p2_fast;
977 clock.p2 >= limit->p2.p2_slow;
978 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
979 unsigned int error_ppm;
980
981 clock.p = clock.p1 * clock.p2;
982
983 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
984 clock.n) << 22, refclk * clock.m1);
985
986 if (m2 > INT_MAX/clock.m1)
987 continue;
988
989 clock.m2 = m2;
990
991 chv_calc_dpll_params(refclk, &clock);
992
993 if (!intel_PLL_is_valid(dev, limit, &clock))
994 continue;
995
996 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
997 best_error_ppm, &error_ppm))
998 continue;
999
1000 *best_clock = clock;
1001 best_error_ppm = error_ppm;
1002 found = true;
1003 }
1004 }
1005
1006 return found;
1007 }
1008
1009 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1010 intel_clock_t *best_clock)
1011 {
1012 int refclk = i9xx_get_refclk(crtc_state, 0);
1013
1014 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1015 target_clock, refclk, NULL, best_clock);
1016 }
1017
1018 bool intel_crtc_active(struct drm_crtc *crtc)
1019 {
1020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1021
1022 /* Be paranoid as we can arrive here with only partial
1023 * state retrieved from the hardware during setup.
1024 *
1025 * We can ditch the adjusted_mode.crtc_clock check as soon
1026 * as Haswell has gained clock readout/fastboot support.
1027 *
1028 * We can ditch the crtc->primary->fb check as soon as we can
1029 * properly reconstruct framebuffers.
1030 *
1031 * FIXME: The intel_crtc->active here should be switched to
1032 * crtc->state->active once we have proper CRTC states wired up
1033 * for atomic.
1034 */
1035 return intel_crtc->active && crtc->primary->state->fb &&
1036 intel_crtc->config->base.adjusted_mode.crtc_clock;
1037 }
1038
1039 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1040 enum pipe pipe)
1041 {
1042 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1044
1045 return intel_crtc->config->cpu_transcoder;
1046 }
1047
1048 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1049 {
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 u32 reg = PIPEDSL(pipe);
1052 u32 line1, line2;
1053 u32 line_mask;
1054
1055 if (IS_GEN2(dev))
1056 line_mask = DSL_LINEMASK_GEN2;
1057 else
1058 line_mask = DSL_LINEMASK_GEN3;
1059
1060 line1 = I915_READ(reg) & line_mask;
1061 msleep(5);
1062 line2 = I915_READ(reg) & line_mask;
1063
1064 return line1 == line2;
1065 }
1066
1067 /*
1068 * intel_wait_for_pipe_off - wait for pipe to turn off
1069 * @crtc: crtc whose pipe to wait for
1070 *
1071 * After disabling a pipe, we can't wait for vblank in the usual way,
1072 * spinning on the vblank interrupt status bit, since we won't actually
1073 * see an interrupt when the pipe is disabled.
1074 *
1075 * On Gen4 and above:
1076 * wait for the pipe register state bit to turn off
1077 *
1078 * Otherwise:
1079 * wait for the display line value to settle (it usually
1080 * ends up stopping at the start of the next frame).
1081 *
1082 */
1083 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1084 {
1085 struct drm_device *dev = crtc->base.dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1088 enum pipe pipe = crtc->pipe;
1089
1090 if (INTEL_INFO(dev)->gen >= 4) {
1091 int reg = PIPECONF(cpu_transcoder);
1092
1093 /* Wait for the Pipe State to go off */
1094 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1095 100))
1096 WARN(1, "pipe_off wait timed out\n");
1097 } else {
1098 /* Wait for the display line to settle */
1099 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1100 WARN(1, "pipe_off wait timed out\n");
1101 }
1102 }
1103
1104 static const char *state_string(bool enabled)
1105 {
1106 return enabled ? "on" : "off";
1107 }
1108
1109 /* Only for pre-ILK configs */
1110 void assert_pll(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1112 {
1113 int reg;
1114 u32 val;
1115 bool cur_state;
1116
1117 reg = DPLL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & DPLL_VCO_ENABLE);
1120 I915_STATE_WARN(cur_state != state,
1121 "PLL state assertion failure (expected %s, current %s)\n",
1122 state_string(state), state_string(cur_state));
1123 }
1124
1125 /* XXX: the dsi pll is shared between MIPI DSI ports */
1126 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1127 {
1128 u32 val;
1129 bool cur_state;
1130
1131 mutex_lock(&dev_priv->sb_lock);
1132 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1133 mutex_unlock(&dev_priv->sb_lock);
1134
1135 cur_state = val & DSI_PLL_VCO_EN;
1136 I915_STATE_WARN(cur_state != state,
1137 "DSI PLL state assertion failure (expected %s, current %s)\n",
1138 state_string(state), state_string(cur_state));
1139 }
1140 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1142
1143 struct intel_shared_dpll *
1144 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1145 {
1146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1147
1148 if (crtc->config->shared_dpll < 0)
1149 return NULL;
1150
1151 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1152 }
1153
1154 /* For ILK+ */
1155 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1156 struct intel_shared_dpll *pll,
1157 bool state)
1158 {
1159 bool cur_state;
1160 struct intel_dpll_hw_state hw_state;
1161
1162 if (WARN (!pll,
1163 "asserting DPLL %s with no DPLL\n", state_string(state)))
1164 return;
1165
1166 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1167 I915_STATE_WARN(cur_state != state,
1168 "%s assertion failure (expected %s, current %s)\n",
1169 pll->name, state_string(state), state_string(cur_state));
1170 }
1171
1172 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1173 enum pipe pipe, bool state)
1174 {
1175 int reg;
1176 u32 val;
1177 bool cur_state;
1178 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1179 pipe);
1180
1181 if (HAS_DDI(dev_priv->dev)) {
1182 /* DDI does not have a specific FDI_TX register */
1183 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1184 val = I915_READ(reg);
1185 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1186 } else {
1187 reg = FDI_TX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_TX_ENABLE);
1190 }
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI TX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1197
1198 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200 {
1201 int reg;
1202 u32 val;
1203 bool cur_state;
1204
1205 reg = FDI_RX_CTL(pipe);
1206 val = I915_READ(reg);
1207 cur_state = !!(val & FDI_RX_ENABLE);
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI RX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1214
1215 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1216 enum pipe pipe)
1217 {
1218 int reg;
1219 u32 val;
1220
1221 /* ILK FDI PLL is always enabled */
1222 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1223 return;
1224
1225 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1226 if (HAS_DDI(dev_priv->dev))
1227 return;
1228
1229 reg = FDI_TX_CTL(pipe);
1230 val = I915_READ(reg);
1231 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1232 }
1233
1234 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, bool state)
1236 {
1237 int reg;
1238 u32 val;
1239 bool cur_state;
1240
1241 reg = FDI_RX_CTL(pipe);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1244 I915_STATE_WARN(cur_state != state,
1245 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246 state_string(state), state_string(cur_state));
1247 }
1248
1249 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251 {
1252 struct drm_device *dev = dev_priv->dev;
1253 int pp_reg;
1254 u32 val;
1255 enum pipe panel_pipe = PIPE_A;
1256 bool locked = true;
1257
1258 if (WARN_ON(HAS_DDI(dev)))
1259 return;
1260
1261 if (HAS_PCH_SPLIT(dev)) {
1262 u32 port_sel;
1263
1264 pp_reg = PCH_PP_CONTROL;
1265 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1266
1267 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1268 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1269 panel_pipe = PIPE_B;
1270 /* XXX: else fix for eDP */
1271 } else if (IS_VALLEYVIEW(dev)) {
1272 /* presumably write lock depends on pipe, not port select */
1273 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1274 panel_pipe = pipe;
1275 } else {
1276 pp_reg = PP_CONTROL;
1277 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1278 panel_pipe = PIPE_B;
1279 }
1280
1281 val = I915_READ(pp_reg);
1282 if (!(val & PANEL_POWER_ON) ||
1283 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1284 locked = false;
1285
1286 I915_STATE_WARN(panel_pipe == pipe && locked,
1287 "panel assertion failure, pipe %c regs locked\n",
1288 pipe_name(pipe));
1289 }
1290
1291 static void assert_cursor(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, bool state)
1293 {
1294 struct drm_device *dev = dev_priv->dev;
1295 bool cur_state;
1296
1297 if (IS_845G(dev) || IS_I865G(dev))
1298 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1299 else
1300 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1301
1302 I915_STATE_WARN(cur_state != state,
1303 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304 pipe_name(pipe), state_string(state), state_string(cur_state));
1305 }
1306 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1308
1309 void assert_pipe(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, bool state)
1311 {
1312 int reg;
1313 u32 val;
1314 bool cur_state;
1315 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1316 pipe);
1317
1318 /* if we need the pipe quirk it must be always on */
1319 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1320 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1321 state = true;
1322
1323 if (!intel_display_power_is_enabled(dev_priv,
1324 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1325 cur_state = false;
1326 } else {
1327 reg = PIPECONF(cpu_transcoder);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & PIPECONF_ENABLE);
1330 }
1331
1332 I915_STATE_WARN(cur_state != state,
1333 "pipe %c assertion failure (expected %s, current %s)\n",
1334 pipe_name(pipe), state_string(state), state_string(cur_state));
1335 }
1336
1337 static void assert_plane(struct drm_i915_private *dev_priv,
1338 enum plane plane, bool state)
1339 {
1340 int reg;
1341 u32 val;
1342 bool cur_state;
1343
1344 reg = DSPCNTR(plane);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1347 I915_STATE_WARN(cur_state != state,
1348 "plane %c assertion failure (expected %s, current %s)\n",
1349 plane_name(plane), state_string(state), state_string(cur_state));
1350 }
1351
1352 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1354
1355 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357 {
1358 struct drm_device *dev = dev_priv->dev;
1359 int reg, i;
1360 u32 val;
1361 int cur_pipe;
1362
1363 /* Primary planes are fixed to pipes on gen4+ */
1364 if (INTEL_INFO(dev)->gen >= 4) {
1365 reg = DSPCNTR(pipe);
1366 val = I915_READ(reg);
1367 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1368 "plane %c assertion failure, should be disabled but not\n",
1369 plane_name(pipe));
1370 return;
1371 }
1372
1373 /* Need to check both planes against the pipe */
1374 for_each_pipe(dev_priv, i) {
1375 reg = DSPCNTR(i);
1376 val = I915_READ(reg);
1377 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1378 DISPPLANE_SEL_PIPE_SHIFT;
1379 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1380 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381 plane_name(i), pipe_name(pipe));
1382 }
1383 }
1384
1385 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int reg, sprite;
1390 u32 val;
1391
1392 if (INTEL_INFO(dev)->gen >= 9) {
1393 for_each_sprite(dev_priv, pipe, sprite) {
1394 val = I915_READ(PLANE_CTL(pipe, sprite));
1395 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1396 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397 sprite, pipe_name(pipe));
1398 }
1399 } else if (IS_VALLEYVIEW(dev)) {
1400 for_each_sprite(dev_priv, pipe, sprite) {
1401 reg = SPCNTR(pipe, sprite);
1402 val = I915_READ(reg);
1403 I915_STATE_WARN(val & SP_ENABLE,
1404 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1405 sprite_name(pipe, sprite), pipe_name(pipe));
1406 }
1407 } else if (INTEL_INFO(dev)->gen >= 7) {
1408 reg = SPRCTL(pipe);
1409 val = I915_READ(reg);
1410 I915_STATE_WARN(val & SPRITE_ENABLE,
1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412 plane_name(pipe), pipe_name(pipe));
1413 } else if (INTEL_INFO(dev)->gen >= 5) {
1414 reg = DVSCNTR(pipe);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & DVS_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 plane_name(pipe), pipe_name(pipe));
1419 }
1420 }
1421
1422 static void assert_vblank_disabled(struct drm_crtc *crtc)
1423 {
1424 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1425 drm_crtc_vblank_put(crtc);
1426 }
1427
1428 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1429 {
1430 u32 val;
1431 bool enabled;
1432
1433 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1434
1435 val = I915_READ(PCH_DREF_CONTROL);
1436 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1437 DREF_SUPERSPREAD_SOURCE_MASK));
1438 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1439 }
1440
1441 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe)
1443 {
1444 int reg;
1445 u32 val;
1446 bool enabled;
1447
1448 reg = PCH_TRANSCONF(pipe);
1449 val = I915_READ(reg);
1450 enabled = !!(val & TRANS_ENABLE);
1451 I915_STATE_WARN(enabled,
1452 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1453 pipe_name(pipe));
1454 }
1455
1456 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 port_sel, u32 val)
1458 {
1459 if ((val & DP_PORT_EN) == 0)
1460 return false;
1461
1462 if (HAS_PCH_CPT(dev_priv->dev)) {
1463 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1464 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1465 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1466 return false;
1467 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1468 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1469 return false;
1470 } else {
1471 if ((val & DP_PIPE_MASK) != (pipe << 30))
1472 return false;
1473 }
1474 return true;
1475 }
1476
1477 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1478 enum pipe pipe, u32 val)
1479 {
1480 if ((val & SDVO_ENABLE) == 0)
1481 return false;
1482
1483 if (HAS_PCH_CPT(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1485 return false;
1486 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1488 return false;
1489 } else {
1490 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1491 return false;
1492 }
1493 return true;
1494 }
1495
1496 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, u32 val)
1498 {
1499 if ((val & LVDS_PORT_EN) == 0)
1500 return false;
1501
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504 return false;
1505 } else {
1506 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1507 return false;
1508 }
1509 return true;
1510 }
1511
1512 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1513 enum pipe pipe, u32 val)
1514 {
1515 if ((val & ADPA_DAC_ENABLE) == 0)
1516 return false;
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1522 return false;
1523 }
1524 return true;
1525 }
1526
1527 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, int reg, u32 port_sel)
1529 {
1530 u32 val = I915_READ(reg);
1531 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1532 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1533 reg, pipe_name(pipe));
1534
1535 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1536 && (val & DP_PIPEB_SELECT),
1537 "IBX PCH dp port still using transcoder B\n");
1538 }
1539
1540 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg)
1542 {
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1545 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1547
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1549 && (val & SDVO_PIPE_B_SELECT),
1550 "IBX PCH hdmi port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe)
1555 {
1556 int reg;
1557 u32 val;
1558
1559 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1560 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1561 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1562
1563 reg = PCH_ADPA;
1564 val = I915_READ(reg);
1565 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1566 "PCH VGA enabled on transcoder %c, should be disabled\n",
1567 pipe_name(pipe));
1568
1569 reg = PCH_LVDS;
1570 val = I915_READ(reg);
1571 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1572 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1573 pipe_name(pipe));
1574
1575 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1576 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1577 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1578 }
1579
1580 static void vlv_enable_pll(struct intel_crtc *crtc,
1581 const struct intel_crtc_state *pipe_config)
1582 {
1583 struct drm_device *dev = crtc->base.dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 int reg = DPLL(crtc->pipe);
1586 u32 dpll = pipe_config->dpll_hw_state.dpll;
1587
1588 assert_pipe_disabled(dev_priv, crtc->pipe);
1589
1590 /* No really, not for ILK+ */
1591 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1592
1593 /* PLL is protected by panel, make sure we can write it */
1594 if (IS_MOBILE(dev_priv->dev))
1595 assert_panel_unlocked(dev_priv, crtc->pipe);
1596
1597 I915_WRITE(reg, dpll);
1598 POSTING_READ(reg);
1599 udelay(150);
1600
1601 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1602 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1603
1604 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1605 POSTING_READ(DPLL_MD(crtc->pipe));
1606
1607 /* We do this three times for luck */
1608 I915_WRITE(reg, dpll);
1609 POSTING_READ(reg);
1610 udelay(150); /* wait for warmup */
1611 I915_WRITE(reg, dpll);
1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
1617 }
1618
1619 static void chv_enable_pll(struct intel_crtc *crtc,
1620 const struct intel_crtc_state *pipe_config)
1621 {
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int pipe = crtc->pipe;
1625 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1626 u32 tmp;
1627
1628 assert_pipe_disabled(dev_priv, crtc->pipe);
1629
1630 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1631
1632 mutex_lock(&dev_priv->sb_lock);
1633
1634 /* Enable back the 10bit clock to display controller */
1635 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1636 tmp |= DPIO_DCLKP_EN;
1637 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1638
1639 mutex_unlock(&dev_priv->sb_lock);
1640
1641 /*
1642 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1643 */
1644 udelay(1);
1645
1646 /* Enable PLL */
1647 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1648
1649 /* Check PLL is locked */
1650 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1651 DRM_ERROR("PLL %d failed to lock\n", pipe);
1652
1653 /* not sure when this should be written */
1654 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1655 POSTING_READ(DPLL_MD(pipe));
1656 }
1657
1658 static int intel_num_dvo_pipes(struct drm_device *dev)
1659 {
1660 struct intel_crtc *crtc;
1661 int count = 0;
1662
1663 for_each_intel_crtc(dev, crtc)
1664 count += crtc->base.state->active &&
1665 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1666
1667 return count;
1668 }
1669
1670 static void i9xx_enable_pll(struct intel_crtc *crtc)
1671 {
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 int reg = DPLL(crtc->pipe);
1675 u32 dpll = crtc->config->dpll_hw_state.dpll;
1676
1677 assert_pipe_disabled(dev_priv, crtc->pipe);
1678
1679 /* No really, not for ILK+ */
1680 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1681
1682 /* PLL is protected by panel, make sure we can write it */
1683 if (IS_MOBILE(dev) && !IS_I830(dev))
1684 assert_panel_unlocked(dev_priv, crtc->pipe);
1685
1686 /* Enable DVO 2x clock on both PLLs if necessary */
1687 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1688 /*
1689 * It appears to be important that we don't enable this
1690 * for the current pipe before otherwise configuring the
1691 * PLL. No idea how this should be handled if multiple
1692 * DVO outputs are enabled simultaneosly.
1693 */
1694 dpll |= DPLL_DVO_2X_MODE;
1695 I915_WRITE(DPLL(!crtc->pipe),
1696 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1697 }
1698
1699 /* Wait for the clocks to stabilize. */
1700 POSTING_READ(reg);
1701 udelay(150);
1702
1703 if (INTEL_INFO(dev)->gen >= 4) {
1704 I915_WRITE(DPLL_MD(crtc->pipe),
1705 crtc->config->dpll_hw_state.dpll_md);
1706 } else {
1707 /* The pixel multiplier can only be updated once the
1708 * DPLL is enabled and the clocks are stable.
1709 *
1710 * So write it again.
1711 */
1712 I915_WRITE(reg, dpll);
1713 }
1714
1715 /* We do this three times for luck */
1716 I915_WRITE(reg, dpll);
1717 POSTING_READ(reg);
1718 udelay(150); /* wait for warmup */
1719 I915_WRITE(reg, dpll);
1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg, dpll);
1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
1725 }
1726
1727 /**
1728 * i9xx_disable_pll - disable a PLL
1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe PLL to disable
1731 *
1732 * Disable the PLL for @pipe, making sure the pipe is off first.
1733 *
1734 * Note! This is for pre-ILK only.
1735 */
1736 static void i9xx_disable_pll(struct intel_crtc *crtc)
1737 {
1738 struct drm_device *dev = crtc->base.dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 enum pipe pipe = crtc->pipe;
1741
1742 /* Disable DVO 2x clock on both PLLs if necessary */
1743 if (IS_I830(dev) &&
1744 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1745 !intel_num_dvo_pipes(dev)) {
1746 I915_WRITE(DPLL(PIPE_B),
1747 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1748 I915_WRITE(DPLL(PIPE_A),
1749 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1750 }
1751
1752 /* Don't disable pipe or pipe PLLs if needed */
1753 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1754 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1755 return;
1756
1757 /* Make sure the pipe isn't still relying on us */
1758 assert_pipe_disabled(dev_priv, pipe);
1759
1760 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1761 POSTING_READ(DPLL(pipe));
1762 }
1763
1764 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1765 {
1766 u32 val;
1767
1768 /* Make sure the pipe isn't still relying on us */
1769 assert_pipe_disabled(dev_priv, pipe);
1770
1771 /*
1772 * Leave integrated clock source and reference clock enabled for pipe B.
1773 * The latter is needed for VGA hotplug / manual detection.
1774 */
1775 val = DPLL_VGA_MODE_DIS;
1776 if (pipe == PIPE_B)
1777 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1780
1781 }
1782
1783 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1784 {
1785 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1786 u32 val;
1787
1788 /* Make sure the pipe isn't still relying on us */
1789 assert_pipe_disabled(dev_priv, pipe);
1790
1791 /* Set PLL en = 0 */
1792 val = DPLL_SSC_REF_CLK_CHV |
1793 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1794 if (pipe != PIPE_A)
1795 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1796 I915_WRITE(DPLL(pipe), val);
1797 POSTING_READ(DPLL(pipe));
1798
1799 mutex_lock(&dev_priv->sb_lock);
1800
1801 /* Disable 10bit clock to display controller */
1802 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1803 val &= ~DPIO_DCLKP_EN;
1804 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1805
1806 mutex_unlock(&dev_priv->sb_lock);
1807 }
1808
1809 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1810 struct intel_digital_port *dport,
1811 unsigned int expected_mask)
1812 {
1813 u32 port_mask;
1814 int dpll_reg;
1815
1816 switch (dport->port) {
1817 case PORT_B:
1818 port_mask = DPLL_PORTB_READY_MASK;
1819 dpll_reg = DPLL(0);
1820 break;
1821 case PORT_C:
1822 port_mask = DPLL_PORTC_READY_MASK;
1823 dpll_reg = DPLL(0);
1824 expected_mask <<= 4;
1825 break;
1826 case PORT_D:
1827 port_mask = DPLL_PORTD_READY_MASK;
1828 dpll_reg = DPIO_PHY_STATUS;
1829 break;
1830 default:
1831 BUG();
1832 }
1833
1834 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1835 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1837 }
1838
1839 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1840 {
1841 struct drm_device *dev = crtc->base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1844
1845 if (WARN_ON(pll == NULL))
1846 return;
1847
1848 WARN_ON(!pll->config.crtc_mask);
1849 if (pll->active == 0) {
1850 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1851 WARN_ON(pll->on);
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853
1854 pll->mode_set(dev_priv, pll);
1855 }
1856 }
1857
1858 /**
1859 * intel_enable_shared_dpll - enable PCH PLL
1860 * @dev_priv: i915 private structure
1861 * @pipe: pipe PLL to enable
1862 *
1863 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864 * drives the transcoder clock.
1865 */
1866 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1867 {
1868 struct drm_device *dev = crtc->base.dev;
1869 struct drm_i915_private *dev_priv = dev->dev_private;
1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1871
1872 if (WARN_ON(pll == NULL))
1873 return;
1874
1875 if (WARN_ON(pll->config.crtc_mask == 0))
1876 return;
1877
1878 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1879 pll->name, pll->active, pll->on,
1880 crtc->base.base.id);
1881
1882 if (pll->active++) {
1883 WARN_ON(!pll->on);
1884 assert_shared_dpll_enabled(dev_priv, pll);
1885 return;
1886 }
1887 WARN_ON(pll->on);
1888
1889 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1890
1891 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1892 pll->enable(dev_priv, pll);
1893 pll->on = true;
1894 }
1895
1896 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1897 {
1898 struct drm_device *dev = crtc->base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1901
1902 /* PCH only available on ILK+ */
1903 if (INTEL_INFO(dev)->gen < 5)
1904 return;
1905
1906 if (pll == NULL)
1907 return;
1908
1909 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1910 return;
1911
1912 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913 pll->name, pll->active, pll->on,
1914 crtc->base.base.id);
1915
1916 if (WARN_ON(pll->active == 0)) {
1917 assert_shared_dpll_disabled(dev_priv, pll);
1918 return;
1919 }
1920
1921 assert_shared_dpll_enabled(dev_priv, pll);
1922 WARN_ON(!pll->on);
1923 if (--pll->active)
1924 return;
1925
1926 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1927 pll->disable(dev_priv, pll);
1928 pll->on = false;
1929
1930 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1931 }
1932
1933 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934 enum pipe pipe)
1935 {
1936 struct drm_device *dev = dev_priv->dev;
1937 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939 uint32_t reg, val, pipeconf_val;
1940
1941 /* PCH only available on ILK+ */
1942 BUG_ON(!HAS_PCH_SPLIT(dev));
1943
1944 /* Make sure PCH DPLL is enabled */
1945 assert_shared_dpll_enabled(dev_priv,
1946 intel_crtc_to_shared_dpll(intel_crtc));
1947
1948 /* FDI must be feeding us bits for PCH ports */
1949 assert_fdi_tx_enabled(dev_priv, pipe);
1950 assert_fdi_rx_enabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_CPT(dev)) {
1953 /* Workaround: Set the timing override bit before enabling the
1954 * pch transcoder. */
1955 reg = TRANS_CHICKEN2(pipe);
1956 val = I915_READ(reg);
1957 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1958 I915_WRITE(reg, val);
1959 }
1960
1961 reg = PCH_TRANSCONF(pipe);
1962 val = I915_READ(reg);
1963 pipeconf_val = I915_READ(PIPECONF(pipe));
1964
1965 if (HAS_PCH_IBX(dev_priv->dev)) {
1966 /*
1967 * Make the BPC in transcoder be consistent with
1968 * that in pipeconf reg. For HDMI we must use 8bpc
1969 * here for both 8bpc and 12bpc.
1970 */
1971 val &= ~PIPECONF_BPC_MASK;
1972 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1973 val |= PIPECONF_8BPC;
1974 else
1975 val |= pipeconf_val & PIPECONF_BPC_MASK;
1976 }
1977
1978 val &= ~TRANS_INTERLACE_MASK;
1979 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1980 if (HAS_PCH_IBX(dev_priv->dev) &&
1981 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1982 val |= TRANS_LEGACY_INTERLACED_ILK;
1983 else
1984 val |= TRANS_INTERLACED;
1985 else
1986 val |= TRANS_PROGRESSIVE;
1987
1988 I915_WRITE(reg, val | TRANS_ENABLE);
1989 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1990 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1991 }
1992
1993 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1994 enum transcoder cpu_transcoder)
1995 {
1996 u32 val, pipeconf_val;
1997
1998 /* PCH only available on ILK+ */
1999 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2000
2001 /* FDI must be feeding us bits for PCH ports */
2002 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2003 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2004
2005 /* Workaround: set timing override bit. */
2006 val = I915_READ(_TRANSA_CHICKEN2);
2007 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(_TRANSA_CHICKEN2, val);
2009
2010 val = TRANS_ENABLE;
2011 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2012
2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2014 PIPECONF_INTERLACED_ILK)
2015 val |= TRANS_INTERLACED;
2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
2019 I915_WRITE(LPT_TRANSCONF, val);
2020 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2021 DRM_ERROR("Failed to enable PCH transcoder\n");
2022 }
2023
2024 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2025 enum pipe pipe)
2026 {
2027 struct drm_device *dev = dev_priv->dev;
2028 uint32_t reg, val;
2029
2030 /* FDI relies on the transcoder */
2031 assert_fdi_tx_disabled(dev_priv, pipe);
2032 assert_fdi_rx_disabled(dev_priv, pipe);
2033
2034 /* Ports must be off as well */
2035 assert_pch_ports_disabled(dev_priv, pipe);
2036
2037 reg = PCH_TRANSCONF(pipe);
2038 val = I915_READ(reg);
2039 val &= ~TRANS_ENABLE;
2040 I915_WRITE(reg, val);
2041 /* wait for PCH transcoder off, transcoder state */
2042 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2043 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2044
2045 if (!HAS_PCH_IBX(dev)) {
2046 /* Workaround: Clear the timing override chicken bit again. */
2047 reg = TRANS_CHICKEN2(pipe);
2048 val = I915_READ(reg);
2049 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2050 I915_WRITE(reg, val);
2051 }
2052 }
2053
2054 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2055 {
2056 u32 val;
2057
2058 val = I915_READ(LPT_TRANSCONF);
2059 val &= ~TRANS_ENABLE;
2060 I915_WRITE(LPT_TRANSCONF, val);
2061 /* wait for PCH transcoder off, transcoder state */
2062 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2063 DRM_ERROR("Failed to disable PCH transcoder\n");
2064
2065 /* Workaround: clear timing override bit. */
2066 val = I915_READ(_TRANSA_CHICKEN2);
2067 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2068 I915_WRITE(_TRANSA_CHICKEN2, val);
2069 }
2070
2071 /**
2072 * intel_enable_pipe - enable a pipe, asserting requirements
2073 * @crtc: crtc responsible for the pipe
2074 *
2075 * Enable @crtc's pipe, making sure that various hardware specific requirements
2076 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2077 */
2078 static void intel_enable_pipe(struct intel_crtc *crtc)
2079 {
2080 struct drm_device *dev = crtc->base.dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 enum pipe pipe = crtc->pipe;
2083 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2084 pipe);
2085 enum pipe pch_transcoder;
2086 int reg;
2087 u32 val;
2088
2089 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2090
2091 assert_planes_disabled(dev_priv, pipe);
2092 assert_cursor_disabled(dev_priv, pipe);
2093 assert_sprites_disabled(dev_priv, pipe);
2094
2095 if (HAS_PCH_LPT(dev_priv->dev))
2096 pch_transcoder = TRANSCODER_A;
2097 else
2098 pch_transcoder = pipe;
2099
2100 /*
2101 * A pipe without a PLL won't actually be able to drive bits from
2102 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2103 * need the check.
2104 */
2105 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2106 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2107 assert_dsi_pll_enabled(dev_priv);
2108 else
2109 assert_pll_enabled(dev_priv, pipe);
2110 else {
2111 if (crtc->config->has_pch_encoder) {
2112 /* if driving the PCH, we need FDI enabled */
2113 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2114 assert_fdi_tx_pll_enabled(dev_priv,
2115 (enum pipe) cpu_transcoder);
2116 }
2117 /* FIXME: assert CPU port conditions for SNB+ */
2118 }
2119
2120 reg = PIPECONF(cpu_transcoder);
2121 val = I915_READ(reg);
2122 if (val & PIPECONF_ENABLE) {
2123 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2124 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2125 return;
2126 }
2127
2128 I915_WRITE(reg, val | PIPECONF_ENABLE);
2129 POSTING_READ(reg);
2130 }
2131
2132 /**
2133 * intel_disable_pipe - disable a pipe, asserting requirements
2134 * @crtc: crtc whose pipes is to be disabled
2135 *
2136 * Disable the pipe of @crtc, making sure that various hardware
2137 * specific requirements are met, if applicable, e.g. plane
2138 * disabled, panel fitter off, etc.
2139 *
2140 * Will wait until the pipe has shut down before returning.
2141 */
2142 static void intel_disable_pipe(struct intel_crtc *crtc)
2143 {
2144 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2145 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2146 enum pipe pipe = crtc->pipe;
2147 int reg;
2148 u32 val;
2149
2150 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
2157 assert_cursor_disabled(dev_priv, pipe);
2158 assert_sprites_disabled(dev_priv, pipe);
2159
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
2169 if (crtc->config->double_wide)
2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186 return true;
2187 #endif
2188 return false;
2189 }
2190
2191 unsigned int
2192 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2193 uint64_t fb_format_modifier, unsigned int plane)
2194 {
2195 unsigned int tile_height;
2196 uint32_t pixel_bytes;
2197
2198 switch (fb_format_modifier) {
2199 case DRM_FORMAT_MOD_NONE:
2200 tile_height = 1;
2201 break;
2202 case I915_FORMAT_MOD_X_TILED:
2203 tile_height = IS_GEN2(dev) ? 16 : 8;
2204 break;
2205 case I915_FORMAT_MOD_Y_TILED:
2206 tile_height = 32;
2207 break;
2208 case I915_FORMAT_MOD_Yf_TILED:
2209 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2210 switch (pixel_bytes) {
2211 default:
2212 case 1:
2213 tile_height = 64;
2214 break;
2215 case 2:
2216 case 4:
2217 tile_height = 32;
2218 break;
2219 case 8:
2220 tile_height = 16;
2221 break;
2222 case 16:
2223 WARN_ONCE(1,
2224 "128-bit pixels are not supported for display!");
2225 tile_height = 16;
2226 break;
2227 }
2228 break;
2229 default:
2230 MISSING_CASE(fb_format_modifier);
2231 tile_height = 1;
2232 break;
2233 }
2234
2235 return tile_height;
2236 }
2237
2238 unsigned int
2239 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2240 uint32_t pixel_format, uint64_t fb_format_modifier)
2241 {
2242 return ALIGN(height, intel_tile_height(dev, pixel_format,
2243 fb_format_modifier, 0));
2244 }
2245
2246 static int
2247 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2248 const struct drm_plane_state *plane_state)
2249 {
2250 struct intel_rotation_info *info = &view->rotation_info;
2251 unsigned int tile_height, tile_pitch;
2252
2253 *view = i915_ggtt_view_normal;
2254
2255 if (!plane_state)
2256 return 0;
2257
2258 if (!intel_rotation_90_or_270(plane_state->rotation))
2259 return 0;
2260
2261 *view = i915_ggtt_view_rotated;
2262
2263 info->height = fb->height;
2264 info->pixel_format = fb->pixel_format;
2265 info->pitch = fb->pitches[0];
2266 info->uv_offset = fb->offsets[1];
2267 info->fb_modifier = fb->modifier[0];
2268
2269 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2270 fb->modifier[0], 0);
2271 tile_pitch = PAGE_SIZE / tile_height;
2272 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2273 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2274 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2275
2276 if (info->pixel_format == DRM_FORMAT_NV12) {
2277 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2278 fb->modifier[0], 1);
2279 tile_pitch = PAGE_SIZE / tile_height;
2280 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2281 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2282 tile_height);
2283 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2284 PAGE_SIZE;
2285 }
2286
2287 return 0;
2288 }
2289
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2291 {
2292 if (INTEL_INFO(dev_priv)->gen >= 9)
2293 return 256 * 1024;
2294 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295 IS_VALLEYVIEW(dev_priv))
2296 return 128 * 1024;
2297 else if (INTEL_INFO(dev_priv)->gen >= 4)
2298 return 4 * 1024;
2299 else
2300 return 0;
2301 }
2302
2303 int
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305 struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state,
2307 struct intel_engine_cs *pipelined,
2308 struct drm_i915_gem_request **pipelined_request)
2309 {
2310 struct drm_device *dev = fb->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313 struct i915_ggtt_view view;
2314 u32 alignment;
2315 int ret;
2316
2317 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2318
2319 switch (fb->modifier[0]) {
2320 case DRM_FORMAT_MOD_NONE:
2321 alignment = intel_linear_alignment(dev_priv);
2322 break;
2323 case I915_FORMAT_MOD_X_TILED:
2324 if (INTEL_INFO(dev)->gen >= 9)
2325 alignment = 256 * 1024;
2326 else {
2327 /* pin() will align the object as required by fence */
2328 alignment = 0;
2329 }
2330 break;
2331 case I915_FORMAT_MOD_Y_TILED:
2332 case I915_FORMAT_MOD_Yf_TILED:
2333 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2334 "Y tiling bo slipped through, driver bug!\n"))
2335 return -EINVAL;
2336 alignment = 1 * 1024 * 1024;
2337 break;
2338 default:
2339 MISSING_CASE(fb->modifier[0]);
2340 return -EINVAL;
2341 }
2342
2343 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2344 if (ret)
2345 return ret;
2346
2347 /* Note that the w/a also requires 64 PTE of padding following the
2348 * bo. We currently fill all unused PTE with the shadow page and so
2349 * we should always have valid PTE following the scanout preventing
2350 * the VT-d warning.
2351 */
2352 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2353 alignment = 256 * 1024;
2354
2355 /*
2356 * Global gtt pte registers are special registers which actually forward
2357 * writes to a chunk of system memory. Which means that there is no risk
2358 * that the register values disappear as soon as we call
2359 * intel_runtime_pm_put(), so it is correct to wrap only the
2360 * pin/unpin/fence and not more.
2361 */
2362 intel_runtime_pm_get(dev_priv);
2363
2364 dev_priv->mm.interruptible = false;
2365 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2366 pipelined_request, &view);
2367 if (ret)
2368 goto err_interruptible;
2369
2370 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371 * fence, whereas 965+ only requires a fence if using
2372 * framebuffer compression. For simplicity, we always install
2373 * a fence as the cost is not that onerous.
2374 */
2375 ret = i915_gem_object_get_fence(obj);
2376 if (ret == -EDEADLK) {
2377 /*
2378 * -EDEADLK means there are no free fences
2379 * no pending flips.
2380 *
2381 * This is propagated to atomic, but it uses
2382 * -EDEADLK to force a locking recovery, so
2383 * change the returned error to -EBUSY.
2384 */
2385 ret = -EBUSY;
2386 goto err_unpin;
2387 } else if (ret)
2388 goto err_unpin;
2389
2390 i915_gem_object_pin_fence(obj);
2391
2392 dev_priv->mm.interruptible = true;
2393 intel_runtime_pm_put(dev_priv);
2394 return 0;
2395
2396 err_unpin:
2397 i915_gem_object_unpin_from_display_plane(obj, &view);
2398 err_interruptible:
2399 dev_priv->mm.interruptible = true;
2400 intel_runtime_pm_put(dev_priv);
2401 return ret;
2402 }
2403
2404 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2405 const struct drm_plane_state *plane_state)
2406 {
2407 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408 struct i915_ggtt_view view;
2409 int ret;
2410
2411 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2412
2413 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2414 WARN_ONCE(ret, "Couldn't get view from plane state!");
2415
2416 i915_gem_object_unpin_fence(obj);
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2418 }
2419
2420 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2421 * is assumed to be a power-of-two. */
2422 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2423 int *x, int *y,
2424 unsigned int tiling_mode,
2425 unsigned int cpp,
2426 unsigned int pitch)
2427 {
2428 if (tiling_mode != I915_TILING_NONE) {
2429 unsigned int tile_rows, tiles;
2430
2431 tile_rows = *y / 8;
2432 *y %= 8;
2433
2434 tiles = *x / (512/cpp);
2435 *x %= 512/cpp;
2436
2437 return tile_rows * pitch * 8 + tiles * 4096;
2438 } else {
2439 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2440 unsigned int offset;
2441
2442 offset = *y * pitch + *x * cpp;
2443 *y = (offset & alignment) / pitch;
2444 *x = ((offset & alignment) - *y * pitch) / cpp;
2445 return offset & ~alignment;
2446 }
2447 }
2448
2449 static int i9xx_format_to_fourcc(int format)
2450 {
2451 switch (format) {
2452 case DISPPLANE_8BPP:
2453 return DRM_FORMAT_C8;
2454 case DISPPLANE_BGRX555:
2455 return DRM_FORMAT_XRGB1555;
2456 case DISPPLANE_BGRX565:
2457 return DRM_FORMAT_RGB565;
2458 default:
2459 case DISPPLANE_BGRX888:
2460 return DRM_FORMAT_XRGB8888;
2461 case DISPPLANE_RGBX888:
2462 return DRM_FORMAT_XBGR8888;
2463 case DISPPLANE_BGRX101010:
2464 return DRM_FORMAT_XRGB2101010;
2465 case DISPPLANE_RGBX101010:
2466 return DRM_FORMAT_XBGR2101010;
2467 }
2468 }
2469
2470 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2471 {
2472 switch (format) {
2473 case PLANE_CTL_FORMAT_RGB_565:
2474 return DRM_FORMAT_RGB565;
2475 default:
2476 case PLANE_CTL_FORMAT_XRGB_8888:
2477 if (rgb_order) {
2478 if (alpha)
2479 return DRM_FORMAT_ABGR8888;
2480 else
2481 return DRM_FORMAT_XBGR8888;
2482 } else {
2483 if (alpha)
2484 return DRM_FORMAT_ARGB8888;
2485 else
2486 return DRM_FORMAT_XRGB8888;
2487 }
2488 case PLANE_CTL_FORMAT_XRGB_2101010:
2489 if (rgb_order)
2490 return DRM_FORMAT_XBGR2101010;
2491 else
2492 return DRM_FORMAT_XRGB2101010;
2493 }
2494 }
2495
2496 static bool
2497 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2498 struct intel_initial_plane_config *plane_config)
2499 {
2500 struct drm_device *dev = crtc->base.dev;
2501 struct drm_i915_gem_object *obj = NULL;
2502 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2503 struct drm_framebuffer *fb = &plane_config->fb->base;
2504 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2505 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2506 PAGE_SIZE);
2507
2508 size_aligned -= base_aligned;
2509
2510 if (plane_config->size == 0)
2511 return false;
2512
2513 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2514 base_aligned,
2515 base_aligned,
2516 size_aligned);
2517 if (!obj)
2518 return false;
2519
2520 obj->tiling_mode = plane_config->tiling;
2521 if (obj->tiling_mode == I915_TILING_X)
2522 obj->stride = fb->pitches[0];
2523
2524 mode_cmd.pixel_format = fb->pixel_format;
2525 mode_cmd.width = fb->width;
2526 mode_cmd.height = fb->height;
2527 mode_cmd.pitches[0] = fb->pitches[0];
2528 mode_cmd.modifier[0] = fb->modifier[0];
2529 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2530
2531 mutex_lock(&dev->struct_mutex);
2532 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2533 &mode_cmd, obj)) {
2534 DRM_DEBUG_KMS("intel fb init failed\n");
2535 goto out_unref_obj;
2536 }
2537 mutex_unlock(&dev->struct_mutex);
2538
2539 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2540 return true;
2541
2542 out_unref_obj:
2543 drm_gem_object_unreference(&obj->base);
2544 mutex_unlock(&dev->struct_mutex);
2545 return false;
2546 }
2547
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2549 static void
2550 update_state_fb(struct drm_plane *plane)
2551 {
2552 if (plane->fb == plane->state->fb)
2553 return;
2554
2555 if (plane->state->fb)
2556 drm_framebuffer_unreference(plane->state->fb);
2557 plane->state->fb = plane->fb;
2558 if (plane->state->fb)
2559 drm_framebuffer_reference(plane->state->fb);
2560 }
2561
2562 static void
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564 struct intel_initial_plane_config *plane_config)
2565 {
2566 struct drm_device *dev = intel_crtc->base.dev;
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 struct drm_crtc *c;
2569 struct intel_crtc *i;
2570 struct drm_i915_gem_object *obj;
2571 struct drm_plane *primary = intel_crtc->base.primary;
2572 struct drm_plane_state *plane_state = primary->state;
2573 struct drm_framebuffer *fb;
2574
2575 if (!plane_config->fb)
2576 return;
2577
2578 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2579 fb = &plane_config->fb->base;
2580 goto valid_fb;
2581 }
2582
2583 kfree(plane_config->fb);
2584
2585 /*
2586 * Failed to alloc the obj, check to see if we should share
2587 * an fb with another CRTC instead
2588 */
2589 for_each_crtc(dev, c) {
2590 i = to_intel_crtc(c);
2591
2592 if (c == &intel_crtc->base)
2593 continue;
2594
2595 if (!i->active)
2596 continue;
2597
2598 fb = c->primary->fb;
2599 if (!fb)
2600 continue;
2601
2602 obj = intel_fb_obj(fb);
2603 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2604 drm_framebuffer_reference(fb);
2605 goto valid_fb;
2606 }
2607 }
2608
2609 return;
2610
2611 valid_fb:
2612 plane_state->src_x = plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2615
2616 plane_state->crtc_x = plane_state->src_y = 0;
2617 plane_state->crtc_w = fb->width;
2618 plane_state->crtc_h = fb->height;
2619
2620 obj = intel_fb_obj(fb);
2621 if (obj->tiling_mode != I915_TILING_NONE)
2622 dev_priv->preserve_bios_swizzle = true;
2623
2624 drm_framebuffer_reference(fb);
2625 primary->fb = primary->state->fb = fb;
2626 primary->crtc = primary->state->crtc = &intel_crtc->base;
2627 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2628 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2629 }
2630
2631 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2632 struct drm_framebuffer *fb,
2633 int x, int y)
2634 {
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 struct drm_plane *primary = crtc->primary;
2639 bool visible = to_intel_plane_state(primary->state)->visible;
2640 struct drm_i915_gem_object *obj;
2641 int plane = intel_crtc->plane;
2642 unsigned long linear_offset;
2643 u32 dspcntr;
2644 u32 reg = DSPCNTR(plane);
2645 int pixel_size;
2646
2647 if (!visible || !fb) {
2648 I915_WRITE(reg, 0);
2649 if (INTEL_INFO(dev)->gen >= 4)
2650 I915_WRITE(DSPSURF(plane), 0);
2651 else
2652 I915_WRITE(DSPADDR(plane), 0);
2653 POSTING_READ(reg);
2654 return;
2655 }
2656
2657 obj = intel_fb_obj(fb);
2658 if (WARN_ON(obj == NULL))
2659 return;
2660
2661 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2662
2663 dspcntr = DISPPLANE_GAMMA_ENABLE;
2664
2665 dspcntr |= DISPLAY_PLANE_ENABLE;
2666
2667 if (INTEL_INFO(dev)->gen < 4) {
2668 if (intel_crtc->pipe == PIPE_B)
2669 dspcntr |= DISPPLANE_SEL_PIPE_B;
2670
2671 /* pipesrc and dspsize control the size that is scaled from,
2672 * which should always be the user's requested size.
2673 */
2674 I915_WRITE(DSPSIZE(plane),
2675 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2676 (intel_crtc->config->pipe_src_w - 1));
2677 I915_WRITE(DSPPOS(plane), 0);
2678 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2679 I915_WRITE(PRIMSIZE(plane),
2680 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681 (intel_crtc->config->pipe_src_w - 1));
2682 I915_WRITE(PRIMPOS(plane), 0);
2683 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2684 }
2685
2686 switch (fb->pixel_format) {
2687 case DRM_FORMAT_C8:
2688 dspcntr |= DISPPLANE_8BPP;
2689 break;
2690 case DRM_FORMAT_XRGB1555:
2691 dspcntr |= DISPPLANE_BGRX555;
2692 break;
2693 case DRM_FORMAT_RGB565:
2694 dspcntr |= DISPPLANE_BGRX565;
2695 break;
2696 case DRM_FORMAT_XRGB8888:
2697 dspcntr |= DISPPLANE_BGRX888;
2698 break;
2699 case DRM_FORMAT_XBGR8888:
2700 dspcntr |= DISPPLANE_RGBX888;
2701 break;
2702 case DRM_FORMAT_XRGB2101010:
2703 dspcntr |= DISPPLANE_BGRX101010;
2704 break;
2705 case DRM_FORMAT_XBGR2101010:
2706 dspcntr |= DISPPLANE_RGBX101010;
2707 break;
2708 default:
2709 BUG();
2710 }
2711
2712 if (INTEL_INFO(dev)->gen >= 4 &&
2713 obj->tiling_mode != I915_TILING_NONE)
2714 dspcntr |= DISPPLANE_TILED;
2715
2716 if (IS_G4X(dev))
2717 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2718
2719 linear_offset = y * fb->pitches[0] + x * pixel_size;
2720
2721 if (INTEL_INFO(dev)->gen >= 4) {
2722 intel_crtc->dspaddr_offset =
2723 intel_gen4_compute_page_offset(dev_priv,
2724 &x, &y, obj->tiling_mode,
2725 pixel_size,
2726 fb->pitches[0]);
2727 linear_offset -= intel_crtc->dspaddr_offset;
2728 } else {
2729 intel_crtc->dspaddr_offset = linear_offset;
2730 }
2731
2732 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2733 dspcntr |= DISPPLANE_ROTATE_180;
2734
2735 x += (intel_crtc->config->pipe_src_w - 1);
2736 y += (intel_crtc->config->pipe_src_h - 1);
2737
2738 /* Finding the last pixel of the last line of the display
2739 data and adding to linear_offset*/
2740 linear_offset +=
2741 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2742 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2743 }
2744
2745 intel_crtc->adjusted_x = x;
2746 intel_crtc->adjusted_y = y;
2747
2748 I915_WRITE(reg, dspcntr);
2749
2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
2756 } else
2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2758 POSTING_READ(reg);
2759 }
2760
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
2770 struct drm_i915_gem_object *obj;
2771 int plane = intel_crtc->plane;
2772 unsigned long linear_offset;
2773 u32 dspcntr;
2774 u32 reg = DSPCNTR(plane);
2775 int pixel_size;
2776
2777 if (!visible || !fb) {
2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
2792 dspcntr |= DISPLAY_PLANE_ENABLE;
2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2796
2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
2803 break;
2804 case DRM_FORMAT_XRGB8888:
2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
2814 dspcntr |= DISPPLANE_RGBX101010;
2815 break;
2816 default:
2817 BUG();
2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
2822
2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2825
2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
2827 intel_crtc->dspaddr_offset =
2828 intel_gen4_compute_page_offset(dev_priv,
2829 &x, &y, obj->tiling_mode,
2830 pixel_size,
2831 fb->pitches[0]);
2832 linear_offset -= intel_crtc->dspaddr_offset;
2833 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834 dspcntr |= DISPPLANE_ROTATE_180;
2835
2836 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837 x += (intel_crtc->config->pipe_src_w - 1);
2838 y += (intel_crtc->config->pipe_src_h - 1);
2839
2840 /* Finding the last pixel of the last line of the display
2841 data and adding to linear_offset*/
2842 linear_offset +=
2843 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2845 }
2846 }
2847
2848 intel_crtc->adjusted_x = x;
2849 intel_crtc->adjusted_y = y;
2850
2851 I915_WRITE(reg, dspcntr);
2852
2853 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2854 I915_WRITE(DSPSURF(plane),
2855 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2856 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2857 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2858 } else {
2859 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2860 I915_WRITE(DSPLINOFF(plane), linear_offset);
2861 }
2862 POSTING_READ(reg);
2863 }
2864
2865 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2866 uint32_t pixel_format)
2867 {
2868 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2869
2870 /*
2871 * The stride is either expressed as a multiple of 64 bytes
2872 * chunks for linear buffers or in number of tiles for tiled
2873 * buffers.
2874 */
2875 switch (fb_modifier) {
2876 case DRM_FORMAT_MOD_NONE:
2877 return 64;
2878 case I915_FORMAT_MOD_X_TILED:
2879 if (INTEL_INFO(dev)->gen == 2)
2880 return 128;
2881 return 512;
2882 case I915_FORMAT_MOD_Y_TILED:
2883 /* No need to check for old gens and Y tiling since this is
2884 * about the display engine and those will be blocked before
2885 * we get here.
2886 */
2887 return 128;
2888 case I915_FORMAT_MOD_Yf_TILED:
2889 if (bits_per_pixel == 8)
2890 return 64;
2891 else
2892 return 128;
2893 default:
2894 MISSING_CASE(fb_modifier);
2895 return 64;
2896 }
2897 }
2898
2899 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2900 struct drm_i915_gem_object *obj,
2901 unsigned int plane)
2902 {
2903 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904 struct i915_vma *vma;
2905 unsigned char *offset;
2906
2907 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908 view = &i915_ggtt_view_rotated;
2909
2910 vma = i915_gem_obj_to_ggtt_view(obj, view);
2911 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2912 view->type))
2913 return -1;
2914
2915 offset = (unsigned char *)vma->node.start;
2916
2917 if (plane == 1) {
2918 offset += vma->ggtt_view.rotation_info.uv_start_page *
2919 PAGE_SIZE;
2920 }
2921
2922 return (unsigned long)offset;
2923 }
2924
2925 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2926 {
2927 struct drm_device *dev = intel_crtc->base.dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929
2930 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2931 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2932 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2933 }
2934
2935 /*
2936 * This function detaches (aka. unbinds) unused scalers in hardware
2937 */
2938 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2939 {
2940 struct intel_crtc_scaler_state *scaler_state;
2941 int i;
2942
2943 scaler_state = &intel_crtc->config->scaler_state;
2944
2945 /* loop through and disable scalers that aren't in use */
2946 for (i = 0; i < intel_crtc->num_scalers; i++) {
2947 if (!scaler_state->scalers[i].in_use)
2948 skl_detach_scaler(intel_crtc, i);
2949 }
2950 }
2951
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2953 {
2954 switch (pixel_format) {
2955 case DRM_FORMAT_C8:
2956 return PLANE_CTL_FORMAT_INDEXED;
2957 case DRM_FORMAT_RGB565:
2958 return PLANE_CTL_FORMAT_RGB_565;
2959 case DRM_FORMAT_XBGR8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961 case DRM_FORMAT_XRGB8888:
2962 return PLANE_CTL_FORMAT_XRGB_8888;
2963 /*
2964 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965 * to be already pre-multiplied. We need to add a knob (or a different
2966 * DRM_FORMAT) for user-space to configure that.
2967 */
2968 case DRM_FORMAT_ABGR8888:
2969 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971 case DRM_FORMAT_ARGB8888:
2972 return PLANE_CTL_FORMAT_XRGB_8888 |
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 case DRM_FORMAT_XRGB2101010:
2975 return PLANE_CTL_FORMAT_XRGB_2101010;
2976 case DRM_FORMAT_XBGR2101010:
2977 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2978 case DRM_FORMAT_YUYV:
2979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2980 case DRM_FORMAT_YVYU:
2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2982 case DRM_FORMAT_UYVY:
2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2984 case DRM_FORMAT_VYUY:
2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2986 default:
2987 MISSING_CASE(pixel_format);
2988 }
2989
2990 return 0;
2991 }
2992
2993 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2994 {
2995 switch (fb_modifier) {
2996 case DRM_FORMAT_MOD_NONE:
2997 break;
2998 case I915_FORMAT_MOD_X_TILED:
2999 return PLANE_CTL_TILED_X;
3000 case I915_FORMAT_MOD_Y_TILED:
3001 return PLANE_CTL_TILED_Y;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 return PLANE_CTL_TILED_YF;
3004 default:
3005 MISSING_CASE(fb_modifier);
3006 }
3007
3008 return 0;
3009 }
3010
3011 u32 skl_plane_ctl_rotation(unsigned int rotation)
3012 {
3013 switch (rotation) {
3014 case BIT(DRM_ROTATE_0):
3015 break;
3016 /*
3017 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018 * while i915 HW rotation is clockwise, thats why this swapping.
3019 */
3020 case BIT(DRM_ROTATE_90):
3021 return PLANE_CTL_ROTATE_270;
3022 case BIT(DRM_ROTATE_180):
3023 return PLANE_CTL_ROTATE_180;
3024 case BIT(DRM_ROTATE_270):
3025 return PLANE_CTL_ROTATE_90;
3026 default:
3027 MISSING_CASE(rotation);
3028 }
3029
3030 return 0;
3031 }
3032
3033 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3034 struct drm_framebuffer *fb,
3035 int x, int y)
3036 {
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040 struct drm_plane *plane = crtc->primary;
3041 bool visible = to_intel_plane_state(plane->state)->visible;
3042 struct drm_i915_gem_object *obj;
3043 int pipe = intel_crtc->pipe;
3044 u32 plane_ctl, stride_div, stride;
3045 u32 tile_height, plane_offset, plane_size;
3046 unsigned int rotation;
3047 int x_offset, y_offset;
3048 unsigned long surf_addr;
3049 struct intel_crtc_state *crtc_state = intel_crtc->config;
3050 struct intel_plane_state *plane_state;
3051 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3052 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3053 int scaler_id = -1;
3054
3055 plane_state = to_intel_plane_state(plane->state);
3056
3057 if (!visible || !fb) {
3058 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3059 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3060 POSTING_READ(PLANE_CTL(pipe, 0));
3061 return;
3062 }
3063
3064 plane_ctl = PLANE_CTL_ENABLE |
3065 PLANE_CTL_PIPE_GAMMA_ENABLE |
3066 PLANE_CTL_PIPE_CSC_ENABLE;
3067
3068 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3069 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3070 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3071
3072 rotation = plane->state->rotation;
3073 plane_ctl |= skl_plane_ctl_rotation(rotation);
3074
3075 obj = intel_fb_obj(fb);
3076 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3077 fb->pixel_format);
3078 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3079
3080 /*
3081 * FIXME: intel_plane_state->src, dst aren't set when transitional
3082 * update_plane helpers are called from legacy paths.
3083 * Once full atomic crtc is available, below check can be avoided.
3084 */
3085 if (drm_rect_width(&plane_state->src)) {
3086 scaler_id = plane_state->scaler_id;
3087 src_x = plane_state->src.x1 >> 16;
3088 src_y = plane_state->src.y1 >> 16;
3089 src_w = drm_rect_width(&plane_state->src) >> 16;
3090 src_h = drm_rect_height(&plane_state->src) >> 16;
3091 dst_x = plane_state->dst.x1;
3092 dst_y = plane_state->dst.y1;
3093 dst_w = drm_rect_width(&plane_state->dst);
3094 dst_h = drm_rect_height(&plane_state->dst);
3095
3096 WARN_ON(x != src_x || y != src_y);
3097 } else {
3098 src_w = intel_crtc->config->pipe_src_w;
3099 src_h = intel_crtc->config->pipe_src_h;
3100 }
3101
3102 if (intel_rotation_90_or_270(rotation)) {
3103 /* stride = Surface height in tiles */
3104 tile_height = intel_tile_height(dev, fb->pixel_format,
3105 fb->modifier[0], 0);
3106 stride = DIV_ROUND_UP(fb->height, tile_height);
3107 x_offset = stride * tile_height - y - src_h;
3108 y_offset = x;
3109 plane_size = (src_w - 1) << 16 | (src_h - 1);
3110 } else {
3111 stride = fb->pitches[0] / stride_div;
3112 x_offset = x;
3113 y_offset = y;
3114 plane_size = (src_h - 1) << 16 | (src_w - 1);
3115 }
3116 plane_offset = y_offset << 16 | x_offset;
3117
3118 intel_crtc->adjusted_x = x_offset;
3119 intel_crtc->adjusted_y = y_offset;
3120
3121 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3122 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3125
3126 if (scaler_id >= 0) {
3127 uint32_t ps_ctrl = 0;
3128
3129 WARN_ON(!dst_w || !dst_h);
3130 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131 crtc_state->scaler_state.scalers[scaler_id].mode;
3132 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137 } else {
3138 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3139 }
3140
3141 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3142
3143 POSTING_READ(PLANE_SURF(pipe, 0));
3144 }
3145
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3147 static int
3148 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149 int x, int y, enum mode_set_atomic state)
3150 {
3151 struct drm_device *dev = crtc->dev;
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153
3154 if (dev_priv->fbc.disable_fbc)
3155 dev_priv->fbc.disable_fbc(dev_priv);
3156
3157 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3158
3159 return 0;
3160 }
3161
3162 static void intel_complete_page_flips(struct drm_device *dev)
3163 {
3164 struct drm_crtc *crtc;
3165
3166 for_each_crtc(dev, crtc) {
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168 enum plane plane = intel_crtc->plane;
3169
3170 intel_prepare_page_flip(dev, plane);
3171 intel_finish_page_flip_plane(dev, plane);
3172 }
3173 }
3174
3175 static void intel_update_primary_planes(struct drm_device *dev)
3176 {
3177 struct drm_crtc *crtc;
3178
3179 for_each_crtc(dev, crtc) {
3180 struct intel_plane *plane = to_intel_plane(crtc->primary);
3181 struct intel_plane_state *plane_state;
3182
3183 drm_modeset_lock_crtc(crtc, &plane->base);
3184
3185 plane_state = to_intel_plane_state(plane->base.state);
3186
3187 if (plane_state->base.fb)
3188 plane->commit_plane(&plane->base, plane_state);
3189
3190 drm_modeset_unlock_crtc(crtc);
3191 }
3192 }
3193
3194 void intel_prepare_reset(struct drm_device *dev)
3195 {
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
3205 /*
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3208 */
3209 intel_display_suspend(dev);
3210 }
3211
3212 void intel_finish_reset(struct drm_device *dev)
3213 {
3214 struct drm_i915_private *dev_priv = to_i915(dev);
3215
3216 /*
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3220 */
3221 intel_complete_page_flips(dev);
3222
3223 /* no reset support for gen2 */
3224 if (IS_GEN2(dev))
3225 return;
3226
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3229 /*
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3234 *
3235 * FIXME: Atomic will make this obsolete since we won't schedule
3236 * CS-based flips (which might get lost in gpu resets) any more.
3237 */
3238 intel_update_primary_planes(dev);
3239 return;
3240 }
3241
3242 /*
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3245 */
3246 intel_runtime_pm_disable_interrupts(dev_priv);
3247 intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249 intel_modeset_init_hw(dev);
3250
3251 spin_lock_irq(&dev_priv->irq_lock);
3252 if (dev_priv->display.hpd_irq_setup)
3253 dev_priv->display.hpd_irq_setup(dev);
3254 spin_unlock_irq(&dev_priv->irq_lock);
3255
3256 intel_display_resume(dev);
3257
3258 intel_hpd_init(dev_priv);
3259
3260 drm_modeset_unlock_all(dev);
3261 }
3262
3263 static void
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3265 {
3266 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268 bool was_interruptible = dev_priv->mm.interruptible;
3269 int ret;
3270
3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
3278 *
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3281 */
3282 dev_priv->mm.interruptible = false;
3283 ret = i915_gem_object_wait_rendering(obj, true);
3284 dev_priv->mm.interruptible = was_interruptible;
3285
3286 WARN_ON(ret);
3287 }
3288
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290 {
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294 bool pending;
3295
3296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298 return false;
3299
3300 spin_lock_irq(&dev->event_lock);
3301 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302 spin_unlock_irq(&dev->event_lock);
3303
3304 return pending;
3305 }
3306
3307 static void intel_update_pipe_config(struct intel_crtc *crtc,
3308 struct intel_crtc_state *old_crtc_state)
3309 {
3310 struct drm_device *dev = crtc->base.dev;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 struct intel_crtc_state *pipe_config =
3313 to_intel_crtc_state(crtc->base.state);
3314
3315 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3316 crtc->base.mode = crtc->base.state->mode;
3317
3318 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3319 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3320 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3321
3322 if (HAS_DDI(dev))
3323 intel_set_pipe_csc(&crtc->base);
3324
3325 /*
3326 * Update pipe size and adjust fitter if needed: the reason for this is
3327 * that in compute_mode_changes we check the native mode (not the pfit
3328 * mode) to see if we can flip rather than do a full mode set. In the
3329 * fastboot case, we'll flip, but if we don't update the pipesrc and
3330 * pfit state, we'll end up with a big fb scanned out into the wrong
3331 * sized surface.
3332 */
3333
3334 I915_WRITE(PIPESRC(crtc->pipe),
3335 ((pipe_config->pipe_src_w - 1) << 16) |
3336 (pipe_config->pipe_src_h - 1));
3337
3338 /* on skylake this is done by detaching scalers */
3339 if (INTEL_INFO(dev)->gen >= 9) {
3340 skl_detach_scalers(crtc);
3341
3342 if (pipe_config->pch_pfit.enabled)
3343 skylake_pfit_enable(crtc);
3344 } else if (HAS_PCH_SPLIT(dev)) {
3345 if (pipe_config->pch_pfit.enabled)
3346 ironlake_pfit_enable(crtc);
3347 else if (old_crtc_state->pch_pfit.enabled)
3348 ironlake_pfit_disable(crtc, true);
3349 }
3350 }
3351
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353 {
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3358 u32 reg, temp;
3359
3360 /* enable normal train */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 if (IS_IVYBRIDGE(dev)) {
3364 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3366 } else {
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3369 }
3370 I915_WRITE(reg, temp);
3371
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 if (HAS_PCH_CPT(dev)) {
3375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377 } else {
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_NONE;
3380 }
3381 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383 /* wait one idle pattern time */
3384 POSTING_READ(reg);
3385 udelay(1000);
3386
3387 /* IVB wants error correction enabled */
3388 if (IS_IVYBRIDGE(dev))
3389 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390 FDI_FE_ERRC_ENABLE);
3391 }
3392
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395 {
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 int pipe = intel_crtc->pipe;
3400 u32 reg, temp, tries;
3401
3402 /* FDI needs bits from pipe first */
3403 assert_pipe_enabled(dev_priv, pipe);
3404
3405 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406 for train result */
3407 reg = FDI_RX_IMR(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_RX_SYMBOL_LOCK;
3410 temp &= ~FDI_RX_BIT_LOCK;
3411 I915_WRITE(reg, temp);
3412 I915_READ(reg);
3413 udelay(150);
3414
3415 /* enable CPU FDI TX and PCH FDI RX */
3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
3418 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
3422 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424 reg = FDI_RX_CTL(pipe);
3425 temp = I915_READ(reg);
3426 temp &= ~FDI_LINK_TRAIN_NONE;
3427 temp |= FDI_LINK_TRAIN_PATTERN_1;
3428 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430 POSTING_READ(reg);
3431 udelay(150);
3432
3433 /* Ironlake workaround, enable clock pointer after FDI enable*/
3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436 FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438 reg = FDI_RX_IIR(pipe);
3439 for (tries = 0; tries < 5; tries++) {
3440 temp = I915_READ(reg);
3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443 if ((temp & FDI_RX_BIT_LOCK)) {
3444 DRM_DEBUG_KMS("FDI train 1 done.\n");
3445 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446 break;
3447 }
3448 }
3449 if (tries == 5)
3450 DRM_ERROR("FDI train 1 fail!\n");
3451
3452 /* Train 2 */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 I915_WRITE(reg, temp);
3458
3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_2;
3463 I915_WRITE(reg, temp);
3464
3465 POSTING_READ(reg);
3466 udelay(150);
3467
3468 reg = FDI_RX_IIR(pipe);
3469 for (tries = 0; tries < 5; tries++) {
3470 temp = I915_READ(reg);
3471 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473 if (temp & FDI_RX_SYMBOL_LOCK) {
3474 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475 DRM_DEBUG_KMS("FDI train 2 done.\n");
3476 break;
3477 }
3478 }
3479 if (tries == 5)
3480 DRM_ERROR("FDI train 2 fail!\n");
3481
3482 DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 int pipe = intel_crtc->pipe;
3500 u32 reg, temp, i, retry;
3501
3502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503 for train result */
3504 reg = FDI_RX_IMR(pipe);
3505 temp = I915_READ(reg);
3506 temp &= ~FDI_RX_SYMBOL_LOCK;
3507 temp &= ~FDI_RX_BIT_LOCK;
3508 I915_WRITE(reg, temp);
3509
3510 POSTING_READ(reg);
3511 udelay(150);
3512
3513 /* enable CPU FDI TX and PCH FDI RX */
3514 reg = FDI_TX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521 /* SNB-B */
3522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3524
3525 I915_WRITE(FDI_RX_MISC(pipe),
3526 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527
3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 if (HAS_PCH_CPT(dev)) {
3531 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533 } else {
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536 }
3537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3538
3539 POSTING_READ(reg);
3540 udelay(150);
3541
3542 for (i = 0; i < 4; i++) {
3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 temp |= snb_b_fdi_train_param[i];
3547 I915_WRITE(reg, temp);
3548
3549 POSTING_READ(reg);
3550 udelay(500);
3551
3552 for (retry = 0; retry < 5; retry++) {
3553 reg = FDI_RX_IIR(pipe);
3554 temp = I915_READ(reg);
3555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556 if (temp & FDI_RX_BIT_LOCK) {
3557 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558 DRM_DEBUG_KMS("FDI train 1 done.\n");
3559 break;
3560 }
3561 udelay(50);
3562 }
3563 if (retry < 5)
3564 break;
3565 }
3566 if (i == 4)
3567 DRM_ERROR("FDI train 1 fail!\n");
3568
3569 /* Train 2 */
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 if (IS_GEN6(dev)) {
3575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576 /* SNB-B */
3577 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578 }
3579 I915_WRITE(reg, temp);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 if (HAS_PCH_CPT(dev)) {
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586 } else {
3587 temp &= ~FDI_LINK_TRAIN_NONE;
3588 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589 }
3590 I915_WRITE(reg, temp);
3591
3592 POSTING_READ(reg);
3593 udelay(150);
3594
3595 for (i = 0; i < 4; i++) {
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599 temp |= snb_b_fdi_train_param[i];
3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
3603 udelay(500);
3604
3605 for (retry = 0; retry < 5; retry++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609 if (temp & FDI_RX_SYMBOL_LOCK) {
3610 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611 DRM_DEBUG_KMS("FDI train 2 done.\n");
3612 break;
3613 }
3614 udelay(50);
3615 }
3616 if (retry < 5)
3617 break;
3618 }
3619 if (i == 4)
3620 DRM_ERROR("FDI train 2 fail!\n");
3621
3622 DRM_DEBUG_KMS("FDI train done.\n");
3623 }
3624
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627 {
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp, i, j;
3633
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635 for train result */
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3641
3642 POSTING_READ(reg);
3643 udelay(150);
3644
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3647
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
3656
3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
3663
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678 reg = FDI_RX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(1); /* should be 0.5us */
3686
3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696 i);
3697 break;
3698 }
3699 udelay(1); /* should be 0.5us */
3700 }
3701 if (i == 4) {
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703 continue;
3704 }
3705
3706 /* Train 2 */
3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717 I915_WRITE(reg, temp);
3718
3719 POSTING_READ(reg);
3720 udelay(2); /* should be 1.5us */
3721
3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731 i);
3732 goto train_done;
3733 }
3734 udelay(2); /* should be 1.5us */
3735 }
3736 if (i == 4)
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738 }
3739
3740 train_done:
3741 DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746 struct drm_device *dev = intel_crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = intel_crtc->pipe;
3749 u32 reg, temp;
3750
3751
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760 POSTING_READ(reg);
3761 udelay(200);
3762
3763 /* Switch from Rawclk to PCDclk */
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767 POSTING_READ(reg);
3768 udelay(200);
3769
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(100);
3778 }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3786 u32 reg, temp;
3787
3788 /* Switch from PCDclk to Rawclk */
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793 /* Disable CPU FDI TX PLL */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798 POSTING_READ(reg);
3799 udelay(100);
3800
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805 /* Wait for the clocks to turn off. */
3806 POSTING_READ(reg);
3807 udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 int pipe = intel_crtc->pipe;
3816 u32 reg, temp;
3817
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822 POSTING_READ(reg);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(0x7 << 16);
3827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830 POSTING_READ(reg);
3831 udelay(100);
3832
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
3834 if (HAS_PCH_IBX(dev))
3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3836
3837 /* still set train pattern 1 */
3838 reg = FDI_TX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1;
3842 I915_WRITE(reg, temp);
3843
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849 } else {
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852 }
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp &= ~(0x07 << 16);
3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856 I915_WRITE(reg, temp);
3857
3858 POSTING_READ(reg);
3859 udelay(100);
3860 }
3861
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863 {
3864 struct intel_crtc *crtc;
3865
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3872 */
3873 for_each_intel_crtc(dev, crtc) {
3874 if (atomic_read(&crtc->unpin_work_count) == 0)
3875 continue;
3876
3877 if (crtc->unpin_work)
3878 intel_wait_for_vblank(dev, crtc->pipe);
3879
3880 return true;
3881 }
3882
3883 return false;
3884 }
3885
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3887 {
3888 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889 struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3892 smp_rmb();
3893 intel_crtc->unpin_work = NULL;
3894
3895 if (work->event)
3896 drm_send_vblank_event(intel_crtc->base.dev,
3897 intel_crtc->pipe,
3898 work->event);
3899
3900 drm_crtc_vblank_put(&intel_crtc->base);
3901
3902 wake_up_all(&dev_priv->pending_flip_queue);
3903 queue_work(dev_priv->wq, &work->work);
3904
3905 trace_i915_flip_complete(intel_crtc->plane,
3906 work->pending_flip_obj);
3907 }
3908
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3910 {
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916 !intel_crtc_has_pending_flip(crtc),
3917 60*HZ) == 0)) {
3918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3919
3920 spin_lock_irq(&dev->event_lock);
3921 if (intel_crtc->unpin_work) {
3922 WARN_ONCE(1, "Removing stuck page flip\n");
3923 page_flip_completed(intel_crtc);
3924 }
3925 spin_unlock_irq(&dev->event_lock);
3926 }
3927
3928 if (crtc->primary->fb) {
3929 mutex_lock(&dev->struct_mutex);
3930 intel_finish_fb(crtc->primary->fb);
3931 mutex_unlock(&dev->struct_mutex);
3932 }
3933 }
3934
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3937 {
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3942 u32 temp;
3943
3944 mutex_lock(&dev_priv->sb_lock);
3945
3946 /* It is necessary to ungate the pixclk gate prior to programming
3947 * the divisors, and gate it back when it is done.
3948 */
3949 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950
3951 /* Disable SSCCTL */
3952 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3954 SBI_SSCCTL_DISABLE,
3955 SBI_ICLK);
3956
3957 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958 if (clock == 20000) {
3959 auxdiv = 1;
3960 divsel = 0x41;
3961 phaseinc = 0x20;
3962 } else {
3963 /* The iCLK virtual clock root frequency is in MHz,
3964 * but the adjusted_mode->crtc_clock in in KHz. To get the
3965 * divisors, it is necessary to divide one by another, so we
3966 * convert the virtual clock precision to KHz here for higher
3967 * precision.
3968 */
3969 u32 iclk_virtual_root_freq = 172800 * 1000;
3970 u32 iclk_pi_range = 64;
3971 u32 desired_divisor, msb_divisor_value, pi_value;
3972
3973 desired_divisor = (iclk_virtual_root_freq / clock);
3974 msb_divisor_value = desired_divisor / iclk_pi_range;
3975 pi_value = desired_divisor % iclk_pi_range;
3976
3977 auxdiv = 0;
3978 divsel = msb_divisor_value - 2;
3979 phaseinc = pi_value;
3980 }
3981
3982 /* This should not happen with any sane values */
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987
3988 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3989 clock,
3990 auxdiv,
3991 divsel,
3992 phasedir,
3993 phaseinc);
3994
3995 /* Program SSCDIVINTPHASE6 */
3996 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4004
4005 /* Program SSCAUXDIV */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4010
4011 /* Enable modulator and associated divider */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013 temp &= ~SBI_SSCCTL_DISABLE;
4014 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4015
4016 /* Wait for initialization time */
4017 udelay(24);
4018
4019 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4020
4021 mutex_unlock(&dev_priv->sb_lock);
4022 }
4023
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025 enum pipe pch_transcoder)
4026 {
4027 struct drm_device *dev = crtc->base.dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4030
4031 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032 I915_READ(HTOTAL(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034 I915_READ(HBLANK(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036 I915_READ(HSYNC(cpu_transcoder)));
4037
4038 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039 I915_READ(VTOTAL(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041 I915_READ(VBLANK(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043 I915_READ(VSYNC(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4046 }
4047
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4049 {
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 uint32_t temp;
4052
4053 temp = I915_READ(SOUTH_CHICKEN1);
4054 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4055 return;
4056
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059
4060 temp &= ~FDI_BC_BIFURCATION_SELECT;
4061 if (enable)
4062 temp |= FDI_BC_BIFURCATION_SELECT;
4063
4064 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065 I915_WRITE(SOUTH_CHICKEN1, temp);
4066 POSTING_READ(SOUTH_CHICKEN1);
4067 }
4068
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070 {
4071 struct drm_device *dev = intel_crtc->base.dev;
4072
4073 switch (intel_crtc->pipe) {
4074 case PIPE_A:
4075 break;
4076 case PIPE_B:
4077 if (intel_crtc->config->fdi_lanes > 2)
4078 cpt_set_fdi_bc_bifurcation(dev, false);
4079 else
4080 cpt_set_fdi_bc_bifurcation(dev, true);
4081
4082 break;
4083 case PIPE_C:
4084 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086 break;
4087 default:
4088 BUG();
4089 }
4090 }
4091
4092 /*
4093 * Enable PCH resources required for PCH ports:
4094 * - PCH PLLs
4095 * - FDI training & RX/TX
4096 * - update transcoder timings
4097 * - DP transcoding bits
4098 * - transcoder
4099 */
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4101 {
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 int pipe = intel_crtc->pipe;
4106 u32 reg, temp;
4107
4108 assert_pch_transcoder_disabled(dev_priv, pipe);
4109
4110 if (IS_IVYBRIDGE(dev))
4111 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112
4113 /* Write the TU size bits before fdi link training, so that error
4114 * detection works. */
4115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117
4118 /* For PCH output, training FDI link */
4119 dev_priv->display.fdi_link_train(crtc);
4120
4121 /* We need to program the right clock selection before writing the pixel
4122 * mutliplier into the DPLL. */
4123 if (HAS_PCH_CPT(dev)) {
4124 u32 sel;
4125
4126 temp = I915_READ(PCH_DPLL_SEL);
4127 temp |= TRANS_DPLL_ENABLE(pipe);
4128 sel = TRANS_DPLLB_SEL(pipe);
4129 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4130 temp |= sel;
4131 else
4132 temp &= ~sel;
4133 I915_WRITE(PCH_DPLL_SEL, temp);
4134 }
4135
4136 /* XXX: pch pll's can be enabled any time before we enable the PCH
4137 * transcoder, and we actually should do this to not upset any PCH
4138 * transcoder that already use the clock when we share it.
4139 *
4140 * Note that enable_shared_dpll tries to do the right thing, but
4141 * get_shared_dpll unconditionally resets the pll - we need that to have
4142 * the right LVDS enable sequence. */
4143 intel_enable_shared_dpll(intel_crtc);
4144
4145 /* set transcoder timing, panel must allow it */
4146 assert_panel_unlocked(dev_priv, pipe);
4147 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4148
4149 intel_fdi_normal_train(crtc);
4150
4151 /* For PCH DP, enable TRANS_DP_CTL */
4152 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154 reg = TRANS_DP_CTL(pipe);
4155 temp = I915_READ(reg);
4156 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157 TRANS_DP_SYNC_MASK |
4158 TRANS_DP_BPC_MASK);
4159 temp |= TRANS_DP_OUTPUT_ENABLE;
4160 temp |= bpc << 9; /* same format but at 11:9 */
4161
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4166
4167 switch (intel_trans_dp_port_sel(crtc)) {
4168 case PCH_DP_B:
4169 temp |= TRANS_DP_PORT_SEL_B;
4170 break;
4171 case PCH_DP_C:
4172 temp |= TRANS_DP_PORT_SEL_C;
4173 break;
4174 case PCH_DP_D:
4175 temp |= TRANS_DP_PORT_SEL_D;
4176 break;
4177 default:
4178 BUG();
4179 }
4180
4181 I915_WRITE(reg, temp);
4182 }
4183
4184 ironlake_enable_pch_transcoder(dev_priv, pipe);
4185 }
4186
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4188 {
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4193
4194 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4195
4196 lpt_program_iclkip(crtc);
4197
4198 /* Set transcoder timing. */
4199 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4200
4201 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4202 }
4203
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205 struct intel_crtc_state *crtc_state)
4206 {
4207 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208 struct intel_shared_dpll *pll;
4209 struct intel_shared_dpll_config *shared_dpll;
4210 enum intel_dpll_id i;
4211
4212 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4213
4214 if (HAS_PCH_IBX(dev_priv->dev)) {
4215 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216 i = (enum intel_dpll_id) crtc->pipe;
4217 pll = &dev_priv->shared_dplls[i];
4218
4219 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220 crtc->base.base.id, pll->name);
4221
4222 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224 goto found;
4225 }
4226
4227 if (IS_BROXTON(dev_priv->dev)) {
4228 /* PLL is attached to port in bxt */
4229 struct intel_encoder *encoder;
4230 struct intel_digital_port *intel_dig_port;
4231
4232 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233 if (WARN_ON(!encoder))
4234 return NULL;
4235
4236 intel_dig_port = enc_to_dig_port(&encoder->base);
4237 /* 1:1 mapping between ports and PLLs */
4238 i = (enum intel_dpll_id)intel_dig_port->port;
4239 pll = &dev_priv->shared_dplls[i];
4240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241 crtc->base.base.id, pll->name);
4242 WARN_ON(shared_dpll[i].crtc_mask);
4243
4244 goto found;
4245 }
4246
4247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248 pll = &dev_priv->shared_dplls[i];
4249
4250 /* Only want to check enabled timings first */
4251 if (shared_dpll[i].crtc_mask == 0)
4252 continue;
4253
4254 if (memcmp(&crtc_state->dpll_hw_state,
4255 &shared_dpll[i].hw_state,
4256 sizeof(crtc_state->dpll_hw_state)) == 0) {
4257 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258 crtc->base.base.id, pll->name,
4259 shared_dpll[i].crtc_mask,
4260 pll->active);
4261 goto found;
4262 }
4263 }
4264
4265 /* Ok no matching timings, maybe there's a free one? */
4266 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267 pll = &dev_priv->shared_dplls[i];
4268 if (shared_dpll[i].crtc_mask == 0) {
4269 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270 crtc->base.base.id, pll->name);
4271 goto found;
4272 }
4273 }
4274
4275 return NULL;
4276
4277 found:
4278 if (shared_dpll[i].crtc_mask == 0)
4279 shared_dpll[i].hw_state =
4280 crtc_state->dpll_hw_state;
4281
4282 crtc_state->shared_dpll = i;
4283 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284 pipe_name(crtc->pipe));
4285
4286 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4287
4288 return pll;
4289 }
4290
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4292 {
4293 struct drm_i915_private *dev_priv = to_i915(state->dev);
4294 struct intel_shared_dpll_config *shared_dpll;
4295 struct intel_shared_dpll *pll;
4296 enum intel_dpll_id i;
4297
4298 if (!to_intel_atomic_state(state)->dpll_set)
4299 return;
4300
4301 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303 pll = &dev_priv->shared_dplls[i];
4304 pll->config = shared_dpll[i];
4305 }
4306 }
4307
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4309 {
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 int dslreg = PIPEDSL(pipe);
4312 u32 temp;
4313
4314 temp = I915_READ(dslreg);
4315 udelay(500);
4316 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317 if (wait_for(I915_READ(dslreg) != temp, 5))
4318 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4319 }
4320 }
4321
4322 static int
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325 int src_w, int src_h, int dst_w, int dst_h)
4326 {
4327 struct intel_crtc_scaler_state *scaler_state =
4328 &crtc_state->scaler_state;
4329 struct intel_crtc *intel_crtc =
4330 to_intel_crtc(crtc_state->base.crtc);
4331 int need_scaling;
4332
4333 need_scaling = intel_rotation_90_or_270(rotation) ?
4334 (src_h != dst_w || src_w != dst_h):
4335 (src_w != dst_w || src_h != dst_h);
4336
4337 /*
4338 * if plane is being disabled or scaler is no more required or force detach
4339 * - free scaler binded to this plane/crtc
4340 * - in order to do this, update crtc->scaler_usage
4341 *
4342 * Here scaler state in crtc_state is set free so that
4343 * scaler can be assigned to other user. Actual register
4344 * update to free the scaler is done in plane/panel-fit programming.
4345 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4346 */
4347 if (force_detach || !need_scaling) {
4348 if (*scaler_id >= 0) {
4349 scaler_state->scaler_users &= ~(1 << scaler_user);
4350 scaler_state->scalers[*scaler_id].in_use = 0;
4351
4352 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354 intel_crtc->pipe, scaler_user, *scaler_id,
4355 scaler_state->scaler_users);
4356 *scaler_id = -1;
4357 }
4358 return 0;
4359 }
4360
4361 /* range checks */
4362 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4364
4365 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368 "size is out of scaler range\n",
4369 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4370 return -EINVAL;
4371 }
4372
4373 /* mark this plane as a scaler user in crtc_state */
4374 scaler_state->scaler_users |= (1 << scaler_user);
4375 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378 scaler_state->scaler_users);
4379
4380 return 0;
4381 }
4382
4383 /**
4384 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4385 *
4386 * @state: crtc's scaler state
4387 *
4388 * Return
4389 * 0 - scaler_usage updated successfully
4390 * error - requested scaling cannot be supported or other error condition
4391 */
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4393 {
4394 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395 struct drm_display_mode *adjusted_mode =
4396 &state->base.adjusted_mode;
4397
4398 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4399 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4400
4401 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4402 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4403 state->pipe_src_w, state->pipe_src_h,
4404 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4405 }
4406
4407 /**
4408 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4409 *
4410 * @state: crtc's scaler state
4411 * @plane_state: atomic plane state to update
4412 *
4413 * Return
4414 * 0 - scaler_usage updated successfully
4415 * error - requested scaling cannot be supported or other error condition
4416 */
4417 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4418 struct intel_plane_state *plane_state)
4419 {
4420
4421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4422 struct intel_plane *intel_plane =
4423 to_intel_plane(plane_state->base.plane);
4424 struct drm_framebuffer *fb = plane_state->base.fb;
4425 int ret;
4426
4427 bool force_detach = !fb || !plane_state->visible;
4428
4429 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4430 intel_plane->base.base.id, intel_crtc->pipe,
4431 drm_plane_index(&intel_plane->base));
4432
4433 ret = skl_update_scaler(crtc_state, force_detach,
4434 drm_plane_index(&intel_plane->base),
4435 &plane_state->scaler_id,
4436 plane_state->base.rotation,
4437 drm_rect_width(&plane_state->src) >> 16,
4438 drm_rect_height(&plane_state->src) >> 16,
4439 drm_rect_width(&plane_state->dst),
4440 drm_rect_height(&plane_state->dst));
4441
4442 if (ret || plane_state->scaler_id < 0)
4443 return ret;
4444
4445 /* check colorkey */
4446 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4447 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4448 intel_plane->base.base.id);
4449 return -EINVAL;
4450 }
4451
4452 /* Check src format */
4453 switch (fb->pixel_format) {
4454 case DRM_FORMAT_RGB565:
4455 case DRM_FORMAT_XBGR8888:
4456 case DRM_FORMAT_XRGB8888:
4457 case DRM_FORMAT_ABGR8888:
4458 case DRM_FORMAT_ARGB8888:
4459 case DRM_FORMAT_XRGB2101010:
4460 case DRM_FORMAT_XBGR2101010:
4461 case DRM_FORMAT_YUYV:
4462 case DRM_FORMAT_YVYU:
4463 case DRM_FORMAT_UYVY:
4464 case DRM_FORMAT_VYUY:
4465 break;
4466 default:
4467 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4468 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4469 return -EINVAL;
4470 }
4471
4472 return 0;
4473 }
4474
4475 static void skylake_scaler_disable(struct intel_crtc *crtc)
4476 {
4477 int i;
4478
4479 for (i = 0; i < crtc->num_scalers; i++)
4480 skl_detach_scaler(crtc, i);
4481 }
4482
4483 static void skylake_pfit_enable(struct intel_crtc *crtc)
4484 {
4485 struct drm_device *dev = crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 int pipe = crtc->pipe;
4488 struct intel_crtc_scaler_state *scaler_state =
4489 &crtc->config->scaler_state;
4490
4491 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4492
4493 if (crtc->config->pch_pfit.enabled) {
4494 int id;
4495
4496 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4497 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4498 return;
4499 }
4500
4501 id = scaler_state->scaler_id;
4502 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4503 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4504 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4505 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4506
4507 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4508 }
4509 }
4510
4511 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4512 {
4513 struct drm_device *dev = crtc->base.dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 int pipe = crtc->pipe;
4516
4517 if (crtc->config->pch_pfit.enabled) {
4518 /* Force use of hard-coded filter coefficients
4519 * as some pre-programmed values are broken,
4520 * e.g. x201.
4521 */
4522 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4523 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4524 PF_PIPE_SEL_IVB(pipe));
4525 else
4526 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4527 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4528 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4529 }
4530 }
4531
4532 void hsw_enable_ips(struct intel_crtc *crtc)
4533 {
4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537 if (!crtc->config->ips_enabled)
4538 return;
4539
4540 /* We can only enable IPS after we enable a plane and wait for a vblank */
4541 intel_wait_for_vblank(dev, crtc->pipe);
4542
4543 assert_plane_enabled(dev_priv, crtc->plane);
4544 if (IS_BROADWELL(dev)) {
4545 mutex_lock(&dev_priv->rps.hw_lock);
4546 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4547 mutex_unlock(&dev_priv->rps.hw_lock);
4548 /* Quoting Art Runyan: "its not safe to expect any particular
4549 * value in IPS_CTL bit 31 after enabling IPS through the
4550 * mailbox." Moreover, the mailbox may return a bogus state,
4551 * so we need to just enable it and continue on.
4552 */
4553 } else {
4554 I915_WRITE(IPS_CTL, IPS_ENABLE);
4555 /* The bit only becomes 1 in the next vblank, so this wait here
4556 * is essentially intel_wait_for_vblank. If we don't have this
4557 * and don't wait for vblanks until the end of crtc_enable, then
4558 * the HW state readout code will complain that the expected
4559 * IPS_CTL value is not the one we read. */
4560 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4561 DRM_ERROR("Timed out waiting for IPS enable\n");
4562 }
4563 }
4564
4565 void hsw_disable_ips(struct intel_crtc *crtc)
4566 {
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570 if (!crtc->config->ips_enabled)
4571 return;
4572
4573 assert_plane_enabled(dev_priv, crtc->plane);
4574 if (IS_BROADWELL(dev)) {
4575 mutex_lock(&dev_priv->rps.hw_lock);
4576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4579 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4580 DRM_ERROR("Timed out waiting for IPS disable\n");
4581 } else {
4582 I915_WRITE(IPS_CTL, 0);
4583 POSTING_READ(IPS_CTL);
4584 }
4585
4586 /* We need to wait for a vblank before we can disable the plane. */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4588 }
4589
4590 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4591 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4592 {
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 enum pipe pipe = intel_crtc->pipe;
4597 int palreg = PALETTE(pipe);
4598 int i;
4599 bool reenable_ips = false;
4600
4601 /* The clocks have to be on to load the palette. */
4602 if (!crtc->state->active)
4603 return;
4604
4605 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4606 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4607 assert_dsi_pll_enabled(dev_priv);
4608 else
4609 assert_pll_enabled(dev_priv, pipe);
4610 }
4611
4612 /* use legacy palette for Ironlake */
4613 if (!HAS_GMCH_DISPLAY(dev))
4614 palreg = LGC_PALETTE(pipe);
4615
4616 /* Workaround : Do not read or write the pipe palette/gamma data while
4617 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4618 */
4619 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4620 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4621 GAMMA_MODE_MODE_SPLIT)) {
4622 hsw_disable_ips(intel_crtc);
4623 reenable_ips = true;
4624 }
4625
4626 for (i = 0; i < 256; i++) {
4627 I915_WRITE(palreg + 4 * i,
4628 (intel_crtc->lut_r[i] << 16) |
4629 (intel_crtc->lut_g[i] << 8) |
4630 intel_crtc->lut_b[i]);
4631 }
4632
4633 if (reenable_ips)
4634 hsw_enable_ips(intel_crtc);
4635 }
4636
4637 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4638 {
4639 if (intel_crtc->overlay) {
4640 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642
4643 mutex_lock(&dev->struct_mutex);
4644 dev_priv->mm.interruptible = false;
4645 (void) intel_overlay_switch_off(intel_crtc->overlay);
4646 dev_priv->mm.interruptible = true;
4647 mutex_unlock(&dev->struct_mutex);
4648 }
4649
4650 /* Let userspace switch the overlay on again. In most cases userspace
4651 * has to recompute where to put it anyway.
4652 */
4653 }
4654
4655 /**
4656 * intel_post_enable_primary - Perform operations after enabling primary plane
4657 * @crtc: the CRTC whose primary plane was just enabled
4658 *
4659 * Performs potentially sleeping operations that must be done after the primary
4660 * plane is enabled, such as updating FBC and IPS. Note that this may be
4661 * called due to an explicit primary plane update, or due to an implicit
4662 * re-enable that is caused when a sprite plane is updated to no longer
4663 * completely hide the primary plane.
4664 */
4665 static void
4666 intel_post_enable_primary(struct drm_crtc *crtc)
4667 {
4668 struct drm_device *dev = crtc->dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4671 int pipe = intel_crtc->pipe;
4672
4673 /*
4674 * BDW signals flip done immediately if the plane
4675 * is disabled, even if the plane enable is already
4676 * armed to occur at the next vblank :(
4677 */
4678 if (IS_BROADWELL(dev))
4679 intel_wait_for_vblank(dev, pipe);
4680
4681 /*
4682 * FIXME IPS should be fine as long as one plane is
4683 * enabled, but in practice it seems to have problems
4684 * when going from primary only to sprite only and vice
4685 * versa.
4686 */
4687 hsw_enable_ips(intel_crtc);
4688
4689 /*
4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4692 * are enabled.
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
4695 */
4696 if (IS_GEN2(dev))
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
4702 }
4703
4704 /**
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4707 *
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4712 * plane.
4713 */
4714 static void
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4716 {
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
4721
4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4727 */
4728 if (IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731 /*
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4739 */
4740 if (HAS_GMCH_DISPLAY(dev)) {
4741 intel_set_memory_cxsr(dev_priv, false);
4742 dev_priv->wm.vlv.cxsr = false;
4743 intel_wait_for_vblank(dev, pipe);
4744 }
4745
4746 /*
4747 * FIXME IPS should be fine as long as one plane is
4748 * enabled, but in practice it seems to have problems
4749 * when going from primary only to sprite only and vice
4750 * versa.
4751 */
4752 hsw_disable_ips(intel_crtc);
4753 }
4754
4755 static void intel_post_plane_update(struct intel_crtc *crtc)
4756 {
4757 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4758 struct drm_device *dev = crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 struct drm_plane *plane;
4761
4762 if (atomic->wait_vblank)
4763 intel_wait_for_vblank(dev, crtc->pipe);
4764
4765 intel_frontbuffer_flip(dev, atomic->fb_bits);
4766
4767 if (atomic->disable_cxsr)
4768 crtc->wm.cxsr_allowed = true;
4769
4770 if (crtc->atomic.update_wm_post)
4771 intel_update_watermarks(&crtc->base);
4772
4773 if (atomic->update_fbc)
4774 intel_fbc_update(dev_priv);
4775
4776 if (atomic->post_enable_primary)
4777 intel_post_enable_primary(&crtc->base);
4778
4779 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4780 intel_update_sprite_watermarks(plane, &crtc->base,
4781 0, 0, 0, false, false);
4782
4783 memset(atomic, 0, sizeof(*atomic));
4784 }
4785
4786 static void intel_pre_plane_update(struct intel_crtc *crtc)
4787 {
4788 struct drm_device *dev = crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791 struct drm_plane *p;
4792
4793 /* Track fb's for any planes being disabled */
4794 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4795 struct intel_plane *plane = to_intel_plane(p);
4796
4797 mutex_lock(&dev->struct_mutex);
4798 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4799 plane->frontbuffer_bit);
4800 mutex_unlock(&dev->struct_mutex);
4801 }
4802
4803 if (atomic->wait_for_flips)
4804 intel_crtc_wait_for_pending_flips(&crtc->base);
4805
4806 if (atomic->disable_fbc)
4807 intel_fbc_disable_crtc(crtc);
4808
4809 if (crtc->atomic.disable_ips)
4810 hsw_disable_ips(crtc);
4811
4812 if (atomic->pre_disable_primary)
4813 intel_pre_disable_primary(&crtc->base);
4814
4815 if (atomic->disable_cxsr) {
4816 crtc->wm.cxsr_allowed = false;
4817 intel_set_memory_cxsr(dev_priv, false);
4818 }
4819 }
4820
4821 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4822 {
4823 struct drm_device *dev = crtc->dev;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4825 struct drm_plane *p;
4826 int pipe = intel_crtc->pipe;
4827
4828 intel_crtc_dpms_overlay_disable(intel_crtc);
4829
4830 drm_for_each_plane_mask(p, dev, plane_mask)
4831 to_intel_plane(p)->disable_plane(p, crtc);
4832
4833 /*
4834 * FIXME: Once we grow proper nuclear flip support out of this we need
4835 * to compute the mask of flip planes precisely. For the time being
4836 * consider this a flip to a NULL plane.
4837 */
4838 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4839 }
4840
4841 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4842 {
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846 struct intel_encoder *encoder;
4847 int pipe = intel_crtc->pipe;
4848
4849 if (WARN_ON(intel_crtc->active))
4850 return;
4851
4852 if (intel_crtc->config->has_pch_encoder)
4853 intel_prepare_shared_dpll(intel_crtc);
4854
4855 if (intel_crtc->config->has_dp_encoder)
4856 intel_dp_set_m_n(intel_crtc, M1_N1);
4857
4858 intel_set_pipe_timings(intel_crtc);
4859
4860 if (intel_crtc->config->has_pch_encoder) {
4861 intel_cpu_transcoder_set_m_n(intel_crtc,
4862 &intel_crtc->config->fdi_m_n, NULL);
4863 }
4864
4865 ironlake_set_pipeconf(crtc);
4866
4867 intel_crtc->active = true;
4868
4869 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4870 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4871
4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
4875
4876 if (intel_crtc->config->has_pch_encoder) {
4877 /* Note: FDI PLL enabling _must_ be done before we enable the
4878 * cpu pipes, hence this is separate from all the other fdi/pch
4879 * enabling. */
4880 ironlake_fdi_pll_enable(intel_crtc);
4881 } else {
4882 assert_fdi_tx_disabled(dev_priv, pipe);
4883 assert_fdi_rx_disabled(dev_priv, pipe);
4884 }
4885
4886 ironlake_pfit_enable(intel_crtc);
4887
4888 /*
4889 * On ILK+ LUT must be loaded before the pipe is running but with
4890 * clocks enabled
4891 */
4892 intel_crtc_load_lut(crtc);
4893
4894 intel_update_watermarks(crtc);
4895 intel_enable_pipe(intel_crtc);
4896
4897 if (intel_crtc->config->has_pch_encoder)
4898 ironlake_pch_enable(crtc);
4899
4900 assert_vblank_disabled(crtc);
4901 drm_crtc_vblank_on(crtc);
4902
4903 for_each_encoder_on_crtc(dev, crtc, encoder)
4904 encoder->enable(encoder);
4905
4906 if (HAS_PCH_CPT(dev))
4907 cpt_verify_modeset(dev, intel_crtc->pipe);
4908 }
4909
4910 /* IPS only exists on ULT machines and is tied to pipe A. */
4911 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4912 {
4913 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4914 }
4915
4916 static void haswell_crtc_enable(struct drm_crtc *crtc)
4917 {
4918 struct drm_device *dev = crtc->dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 struct intel_encoder *encoder;
4922 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4923 struct intel_crtc_state *pipe_config =
4924 to_intel_crtc_state(crtc->state);
4925
4926 if (WARN_ON(intel_crtc->active))
4927 return;
4928
4929 if (intel_crtc_to_shared_dpll(intel_crtc))
4930 intel_enable_shared_dpll(intel_crtc);
4931
4932 if (intel_crtc->config->has_dp_encoder)
4933 intel_dp_set_m_n(intel_crtc, M1_N1);
4934
4935 intel_set_pipe_timings(intel_crtc);
4936
4937 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4938 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4939 intel_crtc->config->pixel_multiplier - 1);
4940 }
4941
4942 if (intel_crtc->config->has_pch_encoder) {
4943 intel_cpu_transcoder_set_m_n(intel_crtc,
4944 &intel_crtc->config->fdi_m_n, NULL);
4945 }
4946
4947 haswell_set_pipeconf(crtc);
4948
4949 intel_set_pipe_csc(crtc);
4950
4951 intel_crtc->active = true;
4952
4953 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4954 for_each_encoder_on_crtc(dev, crtc, encoder)
4955 if (encoder->pre_enable)
4956 encoder->pre_enable(encoder);
4957
4958 if (intel_crtc->config->has_pch_encoder) {
4959 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4960 true);
4961 dev_priv->display.fdi_link_train(crtc);
4962 }
4963
4964 intel_ddi_enable_pipe_clock(intel_crtc);
4965
4966 if (INTEL_INFO(dev)->gen >= 9)
4967 skylake_pfit_enable(intel_crtc);
4968 else
4969 ironlake_pfit_enable(intel_crtc);
4970
4971 /*
4972 * On ILK+ LUT must be loaded before the pipe is running but with
4973 * clocks enabled
4974 */
4975 intel_crtc_load_lut(crtc);
4976
4977 intel_ddi_set_pipe_settings(crtc);
4978 intel_ddi_enable_transcoder_func(crtc);
4979
4980 intel_update_watermarks(crtc);
4981 intel_enable_pipe(intel_crtc);
4982
4983 if (intel_crtc->config->has_pch_encoder)
4984 lpt_pch_enable(crtc);
4985
4986 if (intel_crtc->config->dp_encoder_is_mst)
4987 intel_ddi_set_vc_payload_alloc(crtc, true);
4988
4989 assert_vblank_disabled(crtc);
4990 drm_crtc_vblank_on(crtc);
4991
4992 for_each_encoder_on_crtc(dev, crtc, encoder) {
4993 encoder->enable(encoder);
4994 intel_opregion_notify_encoder(encoder, true);
4995 }
4996
4997 /* If we change the relative order between pipe/planes enabling, we need
4998 * to change the workaround. */
4999 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5000 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5001 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5002 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5003 }
5004 }
5005
5006 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5007 {
5008 struct drm_device *dev = crtc->base.dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 int pipe = crtc->pipe;
5011
5012 /* To avoid upsetting the power well on haswell only disable the pfit if
5013 * it's in use. The hw state code will make sure we get this right. */
5014 if (force || crtc->config->pch_pfit.enabled) {
5015 I915_WRITE(PF_CTL(pipe), 0);
5016 I915_WRITE(PF_WIN_POS(pipe), 0);
5017 I915_WRITE(PF_WIN_SZ(pipe), 0);
5018 }
5019 }
5020
5021 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5022 {
5023 struct drm_device *dev = crtc->dev;
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 struct intel_encoder *encoder;
5027 int pipe = intel_crtc->pipe;
5028 u32 reg, temp;
5029
5030 for_each_encoder_on_crtc(dev, crtc, encoder)
5031 encoder->disable(encoder);
5032
5033 drm_crtc_vblank_off(crtc);
5034 assert_vblank_disabled(crtc);
5035
5036 if (intel_crtc->config->has_pch_encoder)
5037 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5038
5039 intel_disable_pipe(intel_crtc);
5040
5041 ironlake_pfit_disable(intel_crtc, false);
5042
5043 if (intel_crtc->config->has_pch_encoder)
5044 ironlake_fdi_disable(crtc);
5045
5046 for_each_encoder_on_crtc(dev, crtc, encoder)
5047 if (encoder->post_disable)
5048 encoder->post_disable(encoder);
5049
5050 if (intel_crtc->config->has_pch_encoder) {
5051 ironlake_disable_pch_transcoder(dev_priv, pipe);
5052
5053 if (HAS_PCH_CPT(dev)) {
5054 /* disable TRANS_DP_CTL */
5055 reg = TRANS_DP_CTL(pipe);
5056 temp = I915_READ(reg);
5057 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5058 TRANS_DP_PORT_SEL_MASK);
5059 temp |= TRANS_DP_PORT_SEL_NONE;
5060 I915_WRITE(reg, temp);
5061
5062 /* disable DPLL_SEL */
5063 temp = I915_READ(PCH_DPLL_SEL);
5064 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5065 I915_WRITE(PCH_DPLL_SEL, temp);
5066 }
5067
5068 ironlake_fdi_pll_disable(intel_crtc);
5069 }
5070
5071 intel_crtc->active = false;
5072 intel_update_watermarks(crtc);
5073 }
5074
5075 static void haswell_crtc_disable(struct drm_crtc *crtc)
5076 {
5077 struct drm_device *dev = crtc->dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080 struct intel_encoder *encoder;
5081 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5082
5083 for_each_encoder_on_crtc(dev, crtc, encoder) {
5084 intel_opregion_notify_encoder(encoder, false);
5085 encoder->disable(encoder);
5086 }
5087
5088 drm_crtc_vblank_off(crtc);
5089 assert_vblank_disabled(crtc);
5090
5091 if (intel_crtc->config->has_pch_encoder)
5092 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5093 false);
5094 intel_disable_pipe(intel_crtc);
5095
5096 if (intel_crtc->config->dp_encoder_is_mst)
5097 intel_ddi_set_vc_payload_alloc(crtc, false);
5098
5099 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5100
5101 if (INTEL_INFO(dev)->gen >= 9)
5102 skylake_scaler_disable(intel_crtc);
5103 else
5104 ironlake_pfit_disable(intel_crtc, false);
5105
5106 intel_ddi_disable_pipe_clock(intel_crtc);
5107
5108 if (intel_crtc->config->has_pch_encoder) {
5109 lpt_disable_pch_transcoder(dev_priv);
5110 intel_ddi_fdi_disable(crtc);
5111 }
5112
5113 for_each_encoder_on_crtc(dev, crtc, encoder)
5114 if (encoder->post_disable)
5115 encoder->post_disable(encoder);
5116
5117 intel_crtc->active = false;
5118 intel_update_watermarks(crtc);
5119 }
5120
5121 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5122 {
5123 struct drm_device *dev = crtc->base.dev;
5124 struct drm_i915_private *dev_priv = dev->dev_private;
5125 struct intel_crtc_state *pipe_config = crtc->config;
5126
5127 if (!pipe_config->gmch_pfit.control)
5128 return;
5129
5130 /*
5131 * The panel fitter should only be adjusted whilst the pipe is disabled,
5132 * according to register description and PRM.
5133 */
5134 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5135 assert_pipe_disabled(dev_priv, crtc->pipe);
5136
5137 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5138 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5139
5140 /* Border color in case we don't scale up to the full screen. Black by
5141 * default, change to something else for debugging. */
5142 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5143 }
5144
5145 static enum intel_display_power_domain port_to_power_domain(enum port port)
5146 {
5147 switch (port) {
5148 case PORT_A:
5149 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5150 case PORT_B:
5151 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5152 case PORT_C:
5153 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5154 case PORT_D:
5155 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5156 case PORT_E:
5157 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5158 default:
5159 WARN_ON_ONCE(1);
5160 return POWER_DOMAIN_PORT_OTHER;
5161 }
5162 }
5163
5164 #define for_each_power_domain(domain, mask) \
5165 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5166 if ((1 << (domain)) & (mask))
5167
5168 enum intel_display_power_domain
5169 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5170 {
5171 struct drm_device *dev = intel_encoder->base.dev;
5172 struct intel_digital_port *intel_dig_port;
5173
5174 switch (intel_encoder->type) {
5175 case INTEL_OUTPUT_UNKNOWN:
5176 /* Only DDI platforms should ever use this output type */
5177 WARN_ON_ONCE(!HAS_DDI(dev));
5178 case INTEL_OUTPUT_DISPLAYPORT:
5179 case INTEL_OUTPUT_HDMI:
5180 case INTEL_OUTPUT_EDP:
5181 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5182 return port_to_power_domain(intel_dig_port->port);
5183 case INTEL_OUTPUT_DP_MST:
5184 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185 return port_to_power_domain(intel_dig_port->port);
5186 case INTEL_OUTPUT_ANALOG:
5187 return POWER_DOMAIN_PORT_CRT;
5188 case INTEL_OUTPUT_DSI:
5189 return POWER_DOMAIN_PORT_DSI;
5190 default:
5191 return POWER_DOMAIN_PORT_OTHER;
5192 }
5193 }
5194
5195 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5196 {
5197 struct drm_device *dev = crtc->dev;
5198 struct intel_encoder *intel_encoder;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 enum pipe pipe = intel_crtc->pipe;
5201 unsigned long mask;
5202 enum transcoder transcoder;
5203
5204 if (!crtc->state->active)
5205 return 0;
5206
5207 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5208
5209 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5211 if (intel_crtc->config->pch_pfit.enabled ||
5212 intel_crtc->config->pch_pfit.force_thru)
5213 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214
5215 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5216 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5217
5218 return mask;
5219 }
5220
5221 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5222 {
5223 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5225 enum intel_display_power_domain domain;
5226 unsigned long domains, new_domains, old_domains;
5227
5228 old_domains = intel_crtc->enabled_power_domains;
5229 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5230
5231 domains = new_domains & ~old_domains;
5232
5233 for_each_power_domain(domain, domains)
5234 intel_display_power_get(dev_priv, domain);
5235
5236 return old_domains & ~new_domains;
5237 }
5238
5239 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5240 unsigned long domains)
5241 {
5242 enum intel_display_power_domain domain;
5243
5244 for_each_power_domain(domain, domains)
5245 intel_display_power_put(dev_priv, domain);
5246 }
5247
5248 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5249 {
5250 struct drm_device *dev = state->dev;
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 unsigned long put_domains[I915_MAX_PIPES] = {};
5253 struct drm_crtc_state *crtc_state;
5254 struct drm_crtc *crtc;
5255 int i;
5256
5257 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5258 if (needs_modeset(crtc->state))
5259 put_domains[to_intel_crtc(crtc)->pipe] =
5260 modeset_get_crtc_power_domains(crtc);
5261 }
5262
5263 if (dev_priv->display.modeset_commit_cdclk) {
5264 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5265
5266 if (cdclk != dev_priv->cdclk_freq &&
5267 !WARN_ON(!state->allow_modeset))
5268 dev_priv->display.modeset_commit_cdclk(state);
5269 }
5270
5271 for (i = 0; i < I915_MAX_PIPES; i++)
5272 if (put_domains[i])
5273 modeset_put_power_domains(dev_priv, put_domains[i]);
5274 }
5275
5276 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5277 {
5278 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5279
5280 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5281 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5282 return max_cdclk_freq;
5283 else if (IS_CHERRYVIEW(dev_priv))
5284 return max_cdclk_freq*95/100;
5285 else if (INTEL_INFO(dev_priv)->gen < 4)
5286 return 2*max_cdclk_freq*90/100;
5287 else
5288 return max_cdclk_freq*90/100;
5289 }
5290
5291 static void intel_update_max_cdclk(struct drm_device *dev)
5292 {
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294
5295 if (IS_SKYLAKE(dev)) {
5296 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5297
5298 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5299 dev_priv->max_cdclk_freq = 675000;
5300 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5301 dev_priv->max_cdclk_freq = 540000;
5302 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5303 dev_priv->max_cdclk_freq = 450000;
5304 else
5305 dev_priv->max_cdclk_freq = 337500;
5306 } else if (IS_BROADWELL(dev)) {
5307 /*
5308 * FIXME with extra cooling we can allow
5309 * 540 MHz for ULX and 675 Mhz for ULT.
5310 * How can we know if extra cooling is
5311 * available? PCI ID, VTB, something else?
5312 */
5313 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5314 dev_priv->max_cdclk_freq = 450000;
5315 else if (IS_BDW_ULX(dev))
5316 dev_priv->max_cdclk_freq = 450000;
5317 else if (IS_BDW_ULT(dev))
5318 dev_priv->max_cdclk_freq = 540000;
5319 else
5320 dev_priv->max_cdclk_freq = 675000;
5321 } else if (IS_CHERRYVIEW(dev)) {
5322 dev_priv->max_cdclk_freq = 320000;
5323 } else if (IS_VALLEYVIEW(dev)) {
5324 dev_priv->max_cdclk_freq = 400000;
5325 } else {
5326 /* otherwise assume cdclk is fixed */
5327 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5328 }
5329
5330 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5331
5332 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5333 dev_priv->max_cdclk_freq);
5334
5335 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5336 dev_priv->max_dotclk_freq);
5337 }
5338
5339 static void intel_update_cdclk(struct drm_device *dev)
5340 {
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5345 dev_priv->cdclk_freq);
5346
5347 /*
5348 * Program the gmbus_freq based on the cdclk frequency.
5349 * BSpec erroneously claims we should aim for 4MHz, but
5350 * in fact 1MHz is the correct frequency.
5351 */
5352 if (IS_VALLEYVIEW(dev)) {
5353 /*
5354 * Program the gmbus_freq based on the cdclk frequency.
5355 * BSpec erroneously claims we should aim for 4MHz, but
5356 * in fact 1MHz is the correct frequency.
5357 */
5358 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5359 }
5360
5361 if (dev_priv->max_cdclk_freq == 0)
5362 intel_update_max_cdclk(dev);
5363 }
5364
5365 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5366 {
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 uint32_t divider;
5369 uint32_t ratio;
5370 uint32_t current_freq;
5371 int ret;
5372
5373 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374 switch (frequency) {
5375 case 144000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 288000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381 ratio = BXT_DE_PLL_RATIO(60);
5382 break;
5383 case 384000:
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385 ratio = BXT_DE_PLL_RATIO(60);
5386 break;
5387 case 576000:
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389 ratio = BXT_DE_PLL_RATIO(60);
5390 break;
5391 case 624000:
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(65);
5394 break;
5395 case 19200:
5396 /*
5397 * Bypass frequency with DE PLL disabled. Init ratio, divider
5398 * to suppress GCC warning.
5399 */
5400 ratio = 0;
5401 divider = 0;
5402 break;
5403 default:
5404 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5405
5406 return;
5407 }
5408
5409 mutex_lock(&dev_priv->rps.hw_lock);
5410 /* Inform power controller of upcoming frequency change */
5411 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5412 0x80000000);
5413 mutex_unlock(&dev_priv->rps.hw_lock);
5414
5415 if (ret) {
5416 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5417 ret, frequency);
5418 return;
5419 }
5420
5421 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423 current_freq = current_freq * 500 + 1000;
5424
5425 /*
5426 * DE PLL has to be disabled when
5427 * - setting to 19.2MHz (bypass, PLL isn't used)
5428 * - before setting to 624MHz (PLL needs toggling)
5429 * - before setting to any frequency from 624MHz (PLL needs toggling)
5430 */
5431 if (frequency == 19200 || frequency == 624000 ||
5432 current_freq == 624000) {
5433 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5434 /* Timeout 200us */
5435 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5436 1))
5437 DRM_ERROR("timout waiting for DE PLL unlock\n");
5438 }
5439
5440 if (frequency != 19200) {
5441 uint32_t val;
5442
5443 val = I915_READ(BXT_DE_PLL_CTL);
5444 val &= ~BXT_DE_PLL_RATIO_MASK;
5445 val |= ratio;
5446 I915_WRITE(BXT_DE_PLL_CTL, val);
5447
5448 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5449 /* Timeout 200us */
5450 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451 DRM_ERROR("timeout waiting for DE PLL lock\n");
5452
5453 val = I915_READ(CDCLK_CTL);
5454 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5455 val |= divider;
5456 /*
5457 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458 * enable otherwise.
5459 */
5460 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 if (frequency >= 500000)
5462 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463
5464 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466 val |= (frequency - 1000) / 500;
5467 I915_WRITE(CDCLK_CTL, val);
5468 }
5469
5470 mutex_lock(&dev_priv->rps.hw_lock);
5471 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472 DIV_ROUND_UP(frequency, 25000));
5473 mutex_unlock(&dev_priv->rps.hw_lock);
5474
5475 if (ret) {
5476 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5477 ret, frequency);
5478 return;
5479 }
5480
5481 intel_update_cdclk(dev);
5482 }
5483
5484 void broxton_init_cdclk(struct drm_device *dev)
5485 {
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 uint32_t val;
5488
5489 /*
5490 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491 * or else the reset will hang because there is no PCH to respond.
5492 * Move the handshake programming to initialization sequence.
5493 * Previously was left up to BIOS.
5494 */
5495 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5498
5499 /* Enable PG1 for cdclk */
5500 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5501
5502 /* check if cd clock is enabled */
5503 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504 DRM_DEBUG_KMS("Display already initialized\n");
5505 return;
5506 }
5507
5508 /*
5509 * FIXME:
5510 * - The initial CDCLK needs to be read from VBT.
5511 * Need to make this change after VBT has changes for BXT.
5512 * - check if setting the max (or any) cdclk freq is really necessary
5513 * here, it belongs to modeset time
5514 */
5515 broxton_set_cdclk(dev, 624000);
5516
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5519
5520 udelay(10);
5521
5522 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523 DRM_ERROR("DBuf power enable timeout!\n");
5524 }
5525
5526 void broxton_uninit_cdclk(struct drm_device *dev)
5527 {
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5531 POSTING_READ(DBUF_CTL);
5532
5533 udelay(10);
5534
5535 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536 DRM_ERROR("DBuf power disable timeout!\n");
5537
5538 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539 broxton_set_cdclk(dev, 19200);
5540
5541 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5542 }
5543
5544 static const struct skl_cdclk_entry {
5545 unsigned int freq;
5546 unsigned int vco;
5547 } skl_cdclk_frequencies[] = {
5548 { .freq = 308570, .vco = 8640 },
5549 { .freq = 337500, .vco = 8100 },
5550 { .freq = 432000, .vco = 8640 },
5551 { .freq = 450000, .vco = 8100 },
5552 { .freq = 540000, .vco = 8100 },
5553 { .freq = 617140, .vco = 8640 },
5554 { .freq = 675000, .vco = 8100 },
5555 };
5556
5557 static unsigned int skl_cdclk_decimal(unsigned int freq)
5558 {
5559 return (freq - 1000) / 500;
5560 }
5561
5562 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5563 {
5564 unsigned int i;
5565
5566 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5567 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5568
5569 if (e->freq == freq)
5570 return e->vco;
5571 }
5572
5573 return 8100;
5574 }
5575
5576 static void
5577 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5578 {
5579 unsigned int min_freq;
5580 u32 val;
5581
5582 /* select the minimum CDCLK before enabling DPLL 0 */
5583 val = I915_READ(CDCLK_CTL);
5584 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5585 val |= CDCLK_FREQ_337_308;
5586
5587 if (required_vco == 8640)
5588 min_freq = 308570;
5589 else
5590 min_freq = 337500;
5591
5592 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5593
5594 I915_WRITE(CDCLK_CTL, val);
5595 POSTING_READ(CDCLK_CTL);
5596
5597 /*
5598 * We always enable DPLL0 with the lowest link rate possible, but still
5599 * taking into account the VCO required to operate the eDP panel at the
5600 * desired frequency. The usual DP link rates operate with a VCO of
5601 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5602 * The modeset code is responsible for the selection of the exact link
5603 * rate later on, with the constraint of choosing a frequency that
5604 * works with required_vco.
5605 */
5606 val = I915_READ(DPLL_CTRL1);
5607
5608 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5609 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5610 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5611 if (required_vco == 8640)
5612 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5613 SKL_DPLL0);
5614 else
5615 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5616 SKL_DPLL0);
5617
5618 I915_WRITE(DPLL_CTRL1, val);
5619 POSTING_READ(DPLL_CTRL1);
5620
5621 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5622
5623 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5624 DRM_ERROR("DPLL0 not locked\n");
5625 }
5626
5627 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5628 {
5629 int ret;
5630 u32 val;
5631
5632 /* inform PCU we want to change CDCLK */
5633 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5634 mutex_lock(&dev_priv->rps.hw_lock);
5635 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5636 mutex_unlock(&dev_priv->rps.hw_lock);
5637
5638 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5639 }
5640
5641 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5642 {
5643 unsigned int i;
5644
5645 for (i = 0; i < 15; i++) {
5646 if (skl_cdclk_pcu_ready(dev_priv))
5647 return true;
5648 udelay(10);
5649 }
5650
5651 return false;
5652 }
5653
5654 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5655 {
5656 struct drm_device *dev = dev_priv->dev;
5657 u32 freq_select, pcu_ack;
5658
5659 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5660
5661 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5662 DRM_ERROR("failed to inform PCU about cdclk change\n");
5663 return;
5664 }
5665
5666 /* set CDCLK_CTL */
5667 switch(freq) {
5668 case 450000:
5669 case 432000:
5670 freq_select = CDCLK_FREQ_450_432;
5671 pcu_ack = 1;
5672 break;
5673 case 540000:
5674 freq_select = CDCLK_FREQ_540;
5675 pcu_ack = 2;
5676 break;
5677 case 308570:
5678 case 337500:
5679 default:
5680 freq_select = CDCLK_FREQ_337_308;
5681 pcu_ack = 0;
5682 break;
5683 case 617140:
5684 case 675000:
5685 freq_select = CDCLK_FREQ_675_617;
5686 pcu_ack = 3;
5687 break;
5688 }
5689
5690 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5691 POSTING_READ(CDCLK_CTL);
5692
5693 /* inform PCU of the change */
5694 mutex_lock(&dev_priv->rps.hw_lock);
5695 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5696 mutex_unlock(&dev_priv->rps.hw_lock);
5697
5698 intel_update_cdclk(dev);
5699 }
5700
5701 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5702 {
5703 /* disable DBUF power */
5704 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5705 POSTING_READ(DBUF_CTL);
5706
5707 udelay(10);
5708
5709 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5710 DRM_ERROR("DBuf power disable timeout\n");
5711
5712 /* disable DPLL0 */
5713 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5714 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5715 DRM_ERROR("Couldn't disable DPLL0\n");
5716
5717 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5718 }
5719
5720 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5721 {
5722 u32 val;
5723 unsigned int required_vco;
5724
5725 /* enable PCH reset handshake */
5726 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5727 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5728
5729 /* enable PG1 and Misc I/O */
5730 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5731
5732 /* DPLL0 not enabled (happens on early BIOS versions) */
5733 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5734 /* enable DPLL0 */
5735 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5736 skl_dpll0_enable(dev_priv, required_vco);
5737 }
5738
5739 /* set CDCLK to the frequency the BIOS chose */
5740 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5741
5742 /* enable DBUF power */
5743 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5744 POSTING_READ(DBUF_CTL);
5745
5746 udelay(10);
5747
5748 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5749 DRM_ERROR("DBuf power enable timeout\n");
5750 }
5751
5752 /* returns HPLL frequency in kHz */
5753 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5754 {
5755 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5756
5757 /* Obtain SKU information */
5758 mutex_lock(&dev_priv->sb_lock);
5759 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5760 CCK_FUSE_HPLL_FREQ_MASK;
5761 mutex_unlock(&dev_priv->sb_lock);
5762
5763 return vco_freq[hpll_freq] * 1000;
5764 }
5765
5766 /* Adjust CDclk dividers to allow high res or save power if possible */
5767 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5768 {
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 u32 val, cmd;
5771
5772 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5773 != dev_priv->cdclk_freq);
5774
5775 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5776 cmd = 2;
5777 else if (cdclk == 266667)
5778 cmd = 1;
5779 else
5780 cmd = 0;
5781
5782 mutex_lock(&dev_priv->rps.hw_lock);
5783 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5784 val &= ~DSPFREQGUAR_MASK;
5785 val |= (cmd << DSPFREQGUAR_SHIFT);
5786 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5787 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5788 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5789 50)) {
5790 DRM_ERROR("timed out waiting for CDclk change\n");
5791 }
5792 mutex_unlock(&dev_priv->rps.hw_lock);
5793
5794 mutex_lock(&dev_priv->sb_lock);
5795
5796 if (cdclk == 400000) {
5797 u32 divider;
5798
5799 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5800
5801 /* adjust cdclk divider */
5802 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5803 val &= ~DISPLAY_FREQUENCY_VALUES;
5804 val |= divider;
5805 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5806
5807 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5808 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5809 50))
5810 DRM_ERROR("timed out waiting for CDclk change\n");
5811 }
5812
5813 /* adjust self-refresh exit latency value */
5814 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5815 val &= ~0x7f;
5816
5817 /*
5818 * For high bandwidth configs, we set a higher latency in the bunit
5819 * so that the core display fetch happens in time to avoid underruns.
5820 */
5821 if (cdclk == 400000)
5822 val |= 4500 / 250; /* 4.5 usec */
5823 else
5824 val |= 3000 / 250; /* 3.0 usec */
5825 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5826
5827 mutex_unlock(&dev_priv->sb_lock);
5828
5829 intel_update_cdclk(dev);
5830 }
5831
5832 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5833 {
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 u32 val, cmd;
5836
5837 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5838 != dev_priv->cdclk_freq);
5839
5840 switch (cdclk) {
5841 case 333333:
5842 case 320000:
5843 case 266667:
5844 case 200000:
5845 break;
5846 default:
5847 MISSING_CASE(cdclk);
5848 return;
5849 }
5850
5851 /*
5852 * Specs are full of misinformation, but testing on actual
5853 * hardware has shown that we just need to write the desired
5854 * CCK divider into the Punit register.
5855 */
5856 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5857
5858 mutex_lock(&dev_priv->rps.hw_lock);
5859 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5860 val &= ~DSPFREQGUAR_MASK_CHV;
5861 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5862 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5863 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5864 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5865 50)) {
5866 DRM_ERROR("timed out waiting for CDclk change\n");
5867 }
5868 mutex_unlock(&dev_priv->rps.hw_lock);
5869
5870 intel_update_cdclk(dev);
5871 }
5872
5873 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5874 int max_pixclk)
5875 {
5876 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5877 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5878
5879 /*
5880 * Really only a few cases to deal with, as only 4 CDclks are supported:
5881 * 200MHz
5882 * 267MHz
5883 * 320/333MHz (depends on HPLL freq)
5884 * 400MHz (VLV only)
5885 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5886 * of the lower bin and adjust if needed.
5887 *
5888 * We seem to get an unstable or solid color picture at 200MHz.
5889 * Not sure what's wrong. For now use 200MHz only when all pipes
5890 * are off.
5891 */
5892 if (!IS_CHERRYVIEW(dev_priv) &&
5893 max_pixclk > freq_320*limit/100)
5894 return 400000;
5895 else if (max_pixclk > 266667*limit/100)
5896 return freq_320;
5897 else if (max_pixclk > 0)
5898 return 266667;
5899 else
5900 return 200000;
5901 }
5902
5903 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5904 int max_pixclk)
5905 {
5906 /*
5907 * FIXME:
5908 * - remove the guardband, it's not needed on BXT
5909 * - set 19.2MHz bypass frequency if there are no active pipes
5910 */
5911 if (max_pixclk > 576000*9/10)
5912 return 624000;
5913 else if (max_pixclk > 384000*9/10)
5914 return 576000;
5915 else if (max_pixclk > 288000*9/10)
5916 return 384000;
5917 else if (max_pixclk > 144000*9/10)
5918 return 288000;
5919 else
5920 return 144000;
5921 }
5922
5923 /* Compute the max pixel clock for new configuration. Uses atomic state if
5924 * that's non-NULL, look at current state otherwise. */
5925 static int intel_mode_max_pixclk(struct drm_device *dev,
5926 struct drm_atomic_state *state)
5927 {
5928 struct intel_crtc *intel_crtc;
5929 struct intel_crtc_state *crtc_state;
5930 int max_pixclk = 0;
5931
5932 for_each_intel_crtc(dev, intel_crtc) {
5933 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5934 if (IS_ERR(crtc_state))
5935 return PTR_ERR(crtc_state);
5936
5937 if (!crtc_state->base.enable)
5938 continue;
5939
5940 max_pixclk = max(max_pixclk,
5941 crtc_state->base.adjusted_mode.crtc_clock);
5942 }
5943
5944 return max_pixclk;
5945 }
5946
5947 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5948 {
5949 struct drm_device *dev = state->dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 int max_pixclk = intel_mode_max_pixclk(dev, state);
5952
5953 if (max_pixclk < 0)
5954 return max_pixclk;
5955
5956 to_intel_atomic_state(state)->cdclk =
5957 valleyview_calc_cdclk(dev_priv, max_pixclk);
5958
5959 return 0;
5960 }
5961
5962 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5963 {
5964 struct drm_device *dev = state->dev;
5965 struct drm_i915_private *dev_priv = dev->dev_private;
5966 int max_pixclk = intel_mode_max_pixclk(dev, state);
5967
5968 if (max_pixclk < 0)
5969 return max_pixclk;
5970
5971 to_intel_atomic_state(state)->cdclk =
5972 broxton_calc_cdclk(dev_priv, max_pixclk);
5973
5974 return 0;
5975 }
5976
5977 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5978 {
5979 unsigned int credits, default_credits;
5980
5981 if (IS_CHERRYVIEW(dev_priv))
5982 default_credits = PFI_CREDIT(12);
5983 else
5984 default_credits = PFI_CREDIT(8);
5985
5986 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5987 /* CHV suggested value is 31 or 63 */
5988 if (IS_CHERRYVIEW(dev_priv))
5989 credits = PFI_CREDIT_63;
5990 else
5991 credits = PFI_CREDIT(15);
5992 } else {
5993 credits = default_credits;
5994 }
5995
5996 /*
5997 * WA - write default credits before re-programming
5998 * FIXME: should we also set the resend bit here?
5999 */
6000 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6001 default_credits);
6002
6003 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6004 credits | PFI_CREDIT_RESEND);
6005
6006 /*
6007 * FIXME is this guaranteed to clear
6008 * immediately or should we poll for it?
6009 */
6010 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6011 }
6012
6013 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6014 {
6015 struct drm_device *dev = old_state->dev;
6016 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018
6019 /*
6020 * FIXME: We can end up here with all power domains off, yet
6021 * with a CDCLK frequency other than the minimum. To account
6022 * for this take the PIPE-A power domain, which covers the HW
6023 * blocks needed for the following programming. This can be
6024 * removed once it's guaranteed that we get here either with
6025 * the minimum CDCLK set, or the required power domains
6026 * enabled.
6027 */
6028 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6029
6030 if (IS_CHERRYVIEW(dev))
6031 cherryview_set_cdclk(dev, req_cdclk);
6032 else
6033 valleyview_set_cdclk(dev, req_cdclk);
6034
6035 vlv_program_pfi_credits(dev_priv);
6036
6037 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6038 }
6039
6040 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6041 {
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = to_i915(dev);
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 struct intel_encoder *encoder;
6046 int pipe = intel_crtc->pipe;
6047 bool is_dsi;
6048
6049 if (WARN_ON(intel_crtc->active))
6050 return;
6051
6052 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6053
6054 if (intel_crtc->config->has_dp_encoder)
6055 intel_dp_set_m_n(intel_crtc, M1_N1);
6056
6057 intel_set_pipe_timings(intel_crtc);
6058
6059 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6060 struct drm_i915_private *dev_priv = dev->dev_private;
6061
6062 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6063 I915_WRITE(CHV_CANVAS(pipe), 0);
6064 }
6065
6066 i9xx_set_pipeconf(intel_crtc);
6067
6068 intel_crtc->active = true;
6069
6070 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6071
6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 if (encoder->pre_pll_enable)
6074 encoder->pre_pll_enable(encoder);
6075
6076 if (!is_dsi) {
6077 if (IS_CHERRYVIEW(dev)) {
6078 chv_prepare_pll(intel_crtc, intel_crtc->config);
6079 chv_enable_pll(intel_crtc, intel_crtc->config);
6080 } else {
6081 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6082 vlv_enable_pll(intel_crtc, intel_crtc->config);
6083 }
6084 }
6085
6086 for_each_encoder_on_crtc(dev, crtc, encoder)
6087 if (encoder->pre_enable)
6088 encoder->pre_enable(encoder);
6089
6090 i9xx_pfit_enable(intel_crtc);
6091
6092 intel_crtc_load_lut(crtc);
6093
6094 intel_enable_pipe(intel_crtc);
6095
6096 assert_vblank_disabled(crtc);
6097 drm_crtc_vblank_on(crtc);
6098
6099 for_each_encoder_on_crtc(dev, crtc, encoder)
6100 encoder->enable(encoder);
6101 }
6102
6103 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6104 {
6105 struct drm_device *dev = crtc->base.dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6109 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6110 }
6111
6112 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6113 {
6114 struct drm_device *dev = crtc->dev;
6115 struct drm_i915_private *dev_priv = to_i915(dev);
6116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117 struct intel_encoder *encoder;
6118 int pipe = intel_crtc->pipe;
6119
6120 if (WARN_ON(intel_crtc->active))
6121 return;
6122
6123 i9xx_set_pll_dividers(intel_crtc);
6124
6125 if (intel_crtc->config->has_dp_encoder)
6126 intel_dp_set_m_n(intel_crtc, M1_N1);
6127
6128 intel_set_pipe_timings(intel_crtc);
6129
6130 i9xx_set_pipeconf(intel_crtc);
6131
6132 intel_crtc->active = true;
6133
6134 if (!IS_GEN2(dev))
6135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6136
6137 for_each_encoder_on_crtc(dev, crtc, encoder)
6138 if (encoder->pre_enable)
6139 encoder->pre_enable(encoder);
6140
6141 i9xx_enable_pll(intel_crtc);
6142
6143 i9xx_pfit_enable(intel_crtc);
6144
6145 intel_crtc_load_lut(crtc);
6146
6147 intel_update_watermarks(crtc);
6148 intel_enable_pipe(intel_crtc);
6149
6150 assert_vblank_disabled(crtc);
6151 drm_crtc_vblank_on(crtc);
6152
6153 for_each_encoder_on_crtc(dev, crtc, encoder)
6154 encoder->enable(encoder);
6155 }
6156
6157 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6158 {
6159 struct drm_device *dev = crtc->base.dev;
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161
6162 if (!crtc->config->gmch_pfit.control)
6163 return;
6164
6165 assert_pipe_disabled(dev_priv, crtc->pipe);
6166
6167 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6168 I915_READ(PFIT_CONTROL));
6169 I915_WRITE(PFIT_CONTROL, 0);
6170 }
6171
6172 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6173 {
6174 struct drm_device *dev = crtc->dev;
6175 struct drm_i915_private *dev_priv = dev->dev_private;
6176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6177 struct intel_encoder *encoder;
6178 int pipe = intel_crtc->pipe;
6179
6180 /*
6181 * On gen2 planes are double buffered but the pipe isn't, so we must
6182 * wait for planes to fully turn off before disabling the pipe.
6183 * We also need to wait on all gmch platforms because of the
6184 * self-refresh mode constraint explained above.
6185 */
6186 intel_wait_for_vblank(dev, pipe);
6187
6188 for_each_encoder_on_crtc(dev, crtc, encoder)
6189 encoder->disable(encoder);
6190
6191 drm_crtc_vblank_off(crtc);
6192 assert_vblank_disabled(crtc);
6193
6194 intel_disable_pipe(intel_crtc);
6195
6196 i9xx_pfit_disable(intel_crtc);
6197
6198 for_each_encoder_on_crtc(dev, crtc, encoder)
6199 if (encoder->post_disable)
6200 encoder->post_disable(encoder);
6201
6202 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6203 if (IS_CHERRYVIEW(dev))
6204 chv_disable_pll(dev_priv, pipe);
6205 else if (IS_VALLEYVIEW(dev))
6206 vlv_disable_pll(dev_priv, pipe);
6207 else
6208 i9xx_disable_pll(intel_crtc);
6209 }
6210
6211 for_each_encoder_on_crtc(dev, crtc, encoder)
6212 if (encoder->post_pll_disable)
6213 encoder->post_pll_disable(encoder);
6214
6215 if (!IS_GEN2(dev))
6216 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6217
6218 intel_crtc->active = false;
6219 intel_update_watermarks(crtc);
6220 }
6221
6222 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6223 {
6224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6226 enum intel_display_power_domain domain;
6227 unsigned long domains;
6228
6229 if (!intel_crtc->active)
6230 return;
6231
6232 if (to_intel_plane_state(crtc->primary->state)->visible) {
6233 intel_crtc_wait_for_pending_flips(crtc);
6234 intel_pre_disable_primary(crtc);
6235 }
6236
6237 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6238 dev_priv->display.crtc_disable(crtc);
6239 intel_disable_shared_dpll(intel_crtc);
6240
6241 domains = intel_crtc->enabled_power_domains;
6242 for_each_power_domain(domain, domains)
6243 intel_display_power_put(dev_priv, domain);
6244 intel_crtc->enabled_power_domains = 0;
6245 }
6246
6247 /*
6248 * turn all crtc's off, but do not adjust state
6249 * This has to be paired with a call to intel_modeset_setup_hw_state.
6250 */
6251 int intel_display_suspend(struct drm_device *dev)
6252 {
6253 struct drm_mode_config *config = &dev->mode_config;
6254 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6255 struct drm_atomic_state *state;
6256 struct drm_crtc *crtc;
6257 unsigned crtc_mask = 0;
6258 int ret = 0;
6259
6260 if (WARN_ON(!ctx))
6261 return 0;
6262
6263 lockdep_assert_held(&ctx->ww_ctx);
6264 state = drm_atomic_state_alloc(dev);
6265 if (WARN_ON(!state))
6266 return -ENOMEM;
6267
6268 state->acquire_ctx = ctx;
6269 state->allow_modeset = true;
6270
6271 for_each_crtc(dev, crtc) {
6272 struct drm_crtc_state *crtc_state =
6273 drm_atomic_get_crtc_state(state, crtc);
6274
6275 ret = PTR_ERR_OR_ZERO(crtc_state);
6276 if (ret)
6277 goto free;
6278
6279 if (!crtc_state->active)
6280 continue;
6281
6282 crtc_state->active = false;
6283 crtc_mask |= 1 << drm_crtc_index(crtc);
6284 }
6285
6286 if (crtc_mask) {
6287 ret = drm_atomic_commit(state);
6288
6289 if (!ret) {
6290 for_each_crtc(dev, crtc)
6291 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6292 crtc->state->active = true;
6293
6294 return ret;
6295 }
6296 }
6297
6298 free:
6299 if (ret)
6300 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6301 drm_atomic_state_free(state);
6302 return ret;
6303 }
6304
6305 void intel_encoder_destroy(struct drm_encoder *encoder)
6306 {
6307 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6308
6309 drm_encoder_cleanup(encoder);
6310 kfree(intel_encoder);
6311 }
6312
6313 /* Cross check the actual hw state with our own modeset state tracking (and it's
6314 * internal consistency). */
6315 static void intel_connector_check_state(struct intel_connector *connector)
6316 {
6317 struct drm_crtc *crtc = connector->base.state->crtc;
6318
6319 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6320 connector->base.base.id,
6321 connector->base.name);
6322
6323 if (connector->get_hw_state(connector)) {
6324 struct intel_encoder *encoder = connector->encoder;
6325 struct drm_connector_state *conn_state = connector->base.state;
6326
6327 I915_STATE_WARN(!crtc,
6328 "connector enabled without attached crtc\n");
6329
6330 if (!crtc)
6331 return;
6332
6333 I915_STATE_WARN(!crtc->state->active,
6334 "connector is active, but attached crtc isn't\n");
6335
6336 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6337 return;
6338
6339 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6340 "atomic encoder doesn't match attached encoder\n");
6341
6342 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6343 "attached encoder crtc differs from connector crtc\n");
6344 } else {
6345 I915_STATE_WARN(crtc && crtc->state->active,
6346 "attached crtc is active, but connector isn't\n");
6347 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6348 "best encoder set without crtc!\n");
6349 }
6350 }
6351
6352 int intel_connector_init(struct intel_connector *connector)
6353 {
6354 struct drm_connector_state *connector_state;
6355
6356 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6357 if (!connector_state)
6358 return -ENOMEM;
6359
6360 connector->base.state = connector_state;
6361 return 0;
6362 }
6363
6364 struct intel_connector *intel_connector_alloc(void)
6365 {
6366 struct intel_connector *connector;
6367
6368 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6369 if (!connector)
6370 return NULL;
6371
6372 if (intel_connector_init(connector) < 0) {
6373 kfree(connector);
6374 return NULL;
6375 }
6376
6377 return connector;
6378 }
6379
6380 /* Simple connector->get_hw_state implementation for encoders that support only
6381 * one connector and no cloning and hence the encoder state determines the state
6382 * of the connector. */
6383 bool intel_connector_get_hw_state(struct intel_connector *connector)
6384 {
6385 enum pipe pipe = 0;
6386 struct intel_encoder *encoder = connector->encoder;
6387
6388 return encoder->get_hw_state(encoder, &pipe);
6389 }
6390
6391 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6392 {
6393 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6394 return crtc_state->fdi_lanes;
6395
6396 return 0;
6397 }
6398
6399 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6400 struct intel_crtc_state *pipe_config)
6401 {
6402 struct drm_atomic_state *state = pipe_config->base.state;
6403 struct intel_crtc *other_crtc;
6404 struct intel_crtc_state *other_crtc_state;
6405
6406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6408 if (pipe_config->fdi_lanes > 4) {
6409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6410 pipe_name(pipe), pipe_config->fdi_lanes);
6411 return -EINVAL;
6412 }
6413
6414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6415 if (pipe_config->fdi_lanes > 2) {
6416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6417 pipe_config->fdi_lanes);
6418 return -EINVAL;
6419 } else {
6420 return 0;
6421 }
6422 }
6423
6424 if (INTEL_INFO(dev)->num_pipes == 2)
6425 return 0;
6426
6427 /* Ivybridge 3 pipe is really complicated */
6428 switch (pipe) {
6429 case PIPE_A:
6430 return 0;
6431 case PIPE_B:
6432 if (pipe_config->fdi_lanes <= 2)
6433 return 0;
6434
6435 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6436 other_crtc_state =
6437 intel_atomic_get_crtc_state(state, other_crtc);
6438 if (IS_ERR(other_crtc_state))
6439 return PTR_ERR(other_crtc_state);
6440
6441 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6442 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6443 pipe_name(pipe), pipe_config->fdi_lanes);
6444 return -EINVAL;
6445 }
6446 return 0;
6447 case PIPE_C:
6448 if (pipe_config->fdi_lanes > 2) {
6449 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 return -EINVAL;
6452 }
6453
6454 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6455 other_crtc_state =
6456 intel_atomic_get_crtc_state(state, other_crtc);
6457 if (IS_ERR(other_crtc_state))
6458 return PTR_ERR(other_crtc_state);
6459
6460 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6461 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6462 return -EINVAL;
6463 }
6464 return 0;
6465 default:
6466 BUG();
6467 }
6468 }
6469
6470 #define RETRY 1
6471 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6472 struct intel_crtc_state *pipe_config)
6473 {
6474 struct drm_device *dev = intel_crtc->base.dev;
6475 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6476 int lane, link_bw, fdi_dotclock, ret;
6477 bool needs_recompute = false;
6478
6479 retry:
6480 /* FDI is a binary signal running at ~2.7GHz, encoding
6481 * each output octet as 10 bits. The actual frequency
6482 * is stored as a divider into a 100MHz clock, and the
6483 * mode pixel clock is stored in units of 1KHz.
6484 * Hence the bw of each lane in terms of the mode signal
6485 * is:
6486 */
6487 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6488
6489 fdi_dotclock = adjusted_mode->crtc_clock;
6490
6491 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6492 pipe_config->pipe_bpp);
6493
6494 pipe_config->fdi_lanes = lane;
6495
6496 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6497 link_bw, &pipe_config->fdi_m_n);
6498
6499 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6500 intel_crtc->pipe, pipe_config);
6501 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6502 pipe_config->pipe_bpp -= 2*3;
6503 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6504 pipe_config->pipe_bpp);
6505 needs_recompute = true;
6506 pipe_config->bw_constrained = true;
6507
6508 goto retry;
6509 }
6510
6511 if (needs_recompute)
6512 return RETRY;
6513
6514 return ret;
6515 }
6516
6517 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6518 struct intel_crtc_state *pipe_config)
6519 {
6520 if (pipe_config->pipe_bpp > 24)
6521 return false;
6522
6523 /* HSW can handle pixel rate up to cdclk? */
6524 if (IS_HASWELL(dev_priv->dev))
6525 return true;
6526
6527 /*
6528 * We compare against max which means we must take
6529 * the increased cdclk requirement into account when
6530 * calculating the new cdclk.
6531 *
6532 * Should measure whether using a lower cdclk w/o IPS
6533 */
6534 return ilk_pipe_pixel_rate(pipe_config) <=
6535 dev_priv->max_cdclk_freq * 95 / 100;
6536 }
6537
6538 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6539 struct intel_crtc_state *pipe_config)
6540 {
6541 struct drm_device *dev = crtc->base.dev;
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543
6544 pipe_config->ips_enabled = i915.enable_ips &&
6545 hsw_crtc_supports_ips(crtc) &&
6546 pipe_config_supports_ips(dev_priv, pipe_config);
6547 }
6548
6549 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6550 struct intel_crtc_state *pipe_config)
6551 {
6552 struct drm_device *dev = crtc->base.dev;
6553 struct drm_i915_private *dev_priv = dev->dev_private;
6554 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6555
6556 /* FIXME should check pixel clock limits on all platforms */
6557 if (INTEL_INFO(dev)->gen < 4) {
6558 int clock_limit = dev_priv->max_cdclk_freq;
6559
6560 /*
6561 * Enable pixel doubling when the dot clock
6562 * is > 90% of the (display) core speed.
6563 *
6564 * GDG double wide on either pipe,
6565 * otherwise pipe A only.
6566 */
6567 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6568 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6569 clock_limit *= 2;
6570 pipe_config->double_wide = true;
6571 }
6572
6573 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6574 return -EINVAL;
6575 }
6576
6577 /*
6578 * Pipe horizontal size must be even in:
6579 * - DVO ganged mode
6580 * - LVDS dual channel mode
6581 * - Double wide pipe
6582 */
6583 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6584 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6585 pipe_config->pipe_src_w &= ~1;
6586
6587 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6588 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6589 */
6590 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6591 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6592 return -EINVAL;
6593
6594 if (HAS_IPS(dev))
6595 hsw_compute_ips_config(crtc, pipe_config);
6596
6597 if (pipe_config->has_pch_encoder)
6598 return ironlake_fdi_compute_config(crtc, pipe_config);
6599
6600 return 0;
6601 }
6602
6603 static int skylake_get_display_clock_speed(struct drm_device *dev)
6604 {
6605 struct drm_i915_private *dev_priv = to_i915(dev);
6606 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6607 uint32_t cdctl = I915_READ(CDCLK_CTL);
6608 uint32_t linkrate;
6609
6610 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6611 return 24000; /* 24MHz is the cd freq with NSSC ref */
6612
6613 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6614 return 540000;
6615
6616 linkrate = (I915_READ(DPLL_CTRL1) &
6617 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6618
6619 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6620 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6621 /* vco 8640 */
6622 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6623 case CDCLK_FREQ_450_432:
6624 return 432000;
6625 case CDCLK_FREQ_337_308:
6626 return 308570;
6627 case CDCLK_FREQ_675_617:
6628 return 617140;
6629 default:
6630 WARN(1, "Unknown cd freq selection\n");
6631 }
6632 } else {
6633 /* vco 8100 */
6634 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6635 case CDCLK_FREQ_450_432:
6636 return 450000;
6637 case CDCLK_FREQ_337_308:
6638 return 337500;
6639 case CDCLK_FREQ_675_617:
6640 return 675000;
6641 default:
6642 WARN(1, "Unknown cd freq selection\n");
6643 }
6644 }
6645
6646 /* error case, do as if DPLL0 isn't enabled */
6647 return 24000;
6648 }
6649
6650 static int broxton_get_display_clock_speed(struct drm_device *dev)
6651 {
6652 struct drm_i915_private *dev_priv = to_i915(dev);
6653 uint32_t cdctl = I915_READ(CDCLK_CTL);
6654 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6655 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6656 int cdclk;
6657
6658 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6659 return 19200;
6660
6661 cdclk = 19200 * pll_ratio / 2;
6662
6663 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6664 case BXT_CDCLK_CD2X_DIV_SEL_1:
6665 return cdclk; /* 576MHz or 624MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6667 return cdclk * 2 / 3; /* 384MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_2:
6669 return cdclk / 2; /* 288MHz */
6670 case BXT_CDCLK_CD2X_DIV_SEL_4:
6671 return cdclk / 4; /* 144MHz */
6672 }
6673
6674 /* error case, do as if DE PLL isn't enabled */
6675 return 19200;
6676 }
6677
6678 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6679 {
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 uint32_t lcpll = I915_READ(LCPLL_CTL);
6682 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6683
6684 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6685 return 800000;
6686 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6687 return 450000;
6688 else if (freq == LCPLL_CLK_FREQ_450)
6689 return 450000;
6690 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6691 return 540000;
6692 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6693 return 337500;
6694 else
6695 return 675000;
6696 }
6697
6698 static int haswell_get_display_clock_speed(struct drm_device *dev)
6699 {
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 uint32_t lcpll = I915_READ(LCPLL_CTL);
6702 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705 return 800000;
6706 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707 return 450000;
6708 else if (freq == LCPLL_CLK_FREQ_450)
6709 return 450000;
6710 else if (IS_HSW_ULT(dev))
6711 return 337500;
6712 else
6713 return 540000;
6714 }
6715
6716 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6717 {
6718 struct drm_i915_private *dev_priv = dev->dev_private;
6719 u32 val;
6720 int divider;
6721
6722 if (dev_priv->hpll_freq == 0)
6723 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6724
6725 mutex_lock(&dev_priv->sb_lock);
6726 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6727 mutex_unlock(&dev_priv->sb_lock);
6728
6729 divider = val & DISPLAY_FREQUENCY_VALUES;
6730
6731 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6732 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6733 "cdclk change in progress\n");
6734
6735 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6736 }
6737
6738 static int ilk_get_display_clock_speed(struct drm_device *dev)
6739 {
6740 return 450000;
6741 }
6742
6743 static int i945_get_display_clock_speed(struct drm_device *dev)
6744 {
6745 return 400000;
6746 }
6747
6748 static int i915_get_display_clock_speed(struct drm_device *dev)
6749 {
6750 return 333333;
6751 }
6752
6753 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6754 {
6755 return 200000;
6756 }
6757
6758 static int pnv_get_display_clock_speed(struct drm_device *dev)
6759 {
6760 u16 gcfgc = 0;
6761
6762 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6763
6764 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6765 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6766 return 266667;
6767 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6768 return 333333;
6769 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6770 return 444444;
6771 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6772 return 200000;
6773 default:
6774 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6775 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6776 return 133333;
6777 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6778 return 166667;
6779 }
6780 }
6781
6782 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6783 {
6784 u16 gcfgc = 0;
6785
6786 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6787
6788 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6789 return 133333;
6790 else {
6791 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6792 case GC_DISPLAY_CLOCK_333_MHZ:
6793 return 333333;
6794 default:
6795 case GC_DISPLAY_CLOCK_190_200_MHZ:
6796 return 190000;
6797 }
6798 }
6799 }
6800
6801 static int i865_get_display_clock_speed(struct drm_device *dev)
6802 {
6803 return 266667;
6804 }
6805
6806 static int i85x_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 u16 hpllcc = 0;
6809
6810 /*
6811 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6812 * encoding is different :(
6813 * FIXME is this the right way to detect 852GM/852GMV?
6814 */
6815 if (dev->pdev->revision == 0x1)
6816 return 133333;
6817
6818 pci_bus_read_config_word(dev->pdev->bus,
6819 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6820
6821 /* Assume that the hardware is in the high speed state. This
6822 * should be the default.
6823 */
6824 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6825 case GC_CLOCK_133_200:
6826 case GC_CLOCK_133_200_2:
6827 case GC_CLOCK_100_200:
6828 return 200000;
6829 case GC_CLOCK_166_250:
6830 return 250000;
6831 case GC_CLOCK_100_133:
6832 return 133333;
6833 case GC_CLOCK_133_266:
6834 case GC_CLOCK_133_266_2:
6835 case GC_CLOCK_166_266:
6836 return 266667;
6837 }
6838
6839 /* Shouldn't happen */
6840 return 0;
6841 }
6842
6843 static int i830_get_display_clock_speed(struct drm_device *dev)
6844 {
6845 return 133333;
6846 }
6847
6848 static unsigned int intel_hpll_vco(struct drm_device *dev)
6849 {
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6851 static const unsigned int blb_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 4800000,
6856 [4] = 6400000,
6857 };
6858 static const unsigned int pnv_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 4800000,
6863 [4] = 2666667,
6864 };
6865 static const unsigned int cl_vco[8] = {
6866 [0] = 3200000,
6867 [1] = 4000000,
6868 [2] = 5333333,
6869 [3] = 6400000,
6870 [4] = 3333333,
6871 [5] = 3566667,
6872 [6] = 4266667,
6873 };
6874 static const unsigned int elk_vco[8] = {
6875 [0] = 3200000,
6876 [1] = 4000000,
6877 [2] = 5333333,
6878 [3] = 4800000,
6879 };
6880 static const unsigned int ctg_vco[8] = {
6881 [0] = 3200000,
6882 [1] = 4000000,
6883 [2] = 5333333,
6884 [3] = 6400000,
6885 [4] = 2666667,
6886 [5] = 4266667,
6887 };
6888 const unsigned int *vco_table;
6889 unsigned int vco;
6890 uint8_t tmp = 0;
6891
6892 /* FIXME other chipsets? */
6893 if (IS_GM45(dev))
6894 vco_table = ctg_vco;
6895 else if (IS_G4X(dev))
6896 vco_table = elk_vco;
6897 else if (IS_CRESTLINE(dev))
6898 vco_table = cl_vco;
6899 else if (IS_PINEVIEW(dev))
6900 vco_table = pnv_vco;
6901 else if (IS_G33(dev))
6902 vco_table = blb_vco;
6903 else
6904 return 0;
6905
6906 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6907
6908 vco = vco_table[tmp & 0x7];
6909 if (vco == 0)
6910 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6911 else
6912 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6913
6914 return vco;
6915 }
6916
6917 static int gm45_get_display_clock_speed(struct drm_device *dev)
6918 {
6919 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6920 uint16_t tmp = 0;
6921
6922 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6923
6924 cdclk_sel = (tmp >> 12) & 0x1;
6925
6926 switch (vco) {
6927 case 2666667:
6928 case 4000000:
6929 case 5333333:
6930 return cdclk_sel ? 333333 : 222222;
6931 case 3200000:
6932 return cdclk_sel ? 320000 : 228571;
6933 default:
6934 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6935 return 222222;
6936 }
6937 }
6938
6939 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6940 {
6941 static const uint8_t div_3200[] = { 16, 10, 8 };
6942 static const uint8_t div_4000[] = { 20, 12, 10 };
6943 static const uint8_t div_5333[] = { 24, 16, 14 };
6944 const uint8_t *div_table;
6945 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6946 uint16_t tmp = 0;
6947
6948 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6949
6950 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6951
6952 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6953 goto fail;
6954
6955 switch (vco) {
6956 case 3200000:
6957 div_table = div_3200;
6958 break;
6959 case 4000000:
6960 div_table = div_4000;
6961 break;
6962 case 5333333:
6963 div_table = div_5333;
6964 break;
6965 default:
6966 goto fail;
6967 }
6968
6969 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6970
6971 fail:
6972 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6973 return 200000;
6974 }
6975
6976 static int g33_get_display_clock_speed(struct drm_device *dev)
6977 {
6978 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6979 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6980 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6981 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6982 const uint8_t *div_table;
6983 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6984 uint16_t tmp = 0;
6985
6986 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6987
6988 cdclk_sel = (tmp >> 4) & 0x7;
6989
6990 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6991 goto fail;
6992
6993 switch (vco) {
6994 case 3200000:
6995 div_table = div_3200;
6996 break;
6997 case 4000000:
6998 div_table = div_4000;
6999 break;
7000 case 4800000:
7001 div_table = div_4800;
7002 break;
7003 case 5333333:
7004 div_table = div_5333;
7005 break;
7006 default:
7007 goto fail;
7008 }
7009
7010 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7011
7012 fail:
7013 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7014 return 190476;
7015 }
7016
7017 static void
7018 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7019 {
7020 while (*num > DATA_LINK_M_N_MASK ||
7021 *den > DATA_LINK_M_N_MASK) {
7022 *num >>= 1;
7023 *den >>= 1;
7024 }
7025 }
7026
7027 static void compute_m_n(unsigned int m, unsigned int n,
7028 uint32_t *ret_m, uint32_t *ret_n)
7029 {
7030 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7031 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7032 intel_reduce_m_n_ratio(ret_m, ret_n);
7033 }
7034
7035 void
7036 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7037 int pixel_clock, int link_clock,
7038 struct intel_link_m_n *m_n)
7039 {
7040 m_n->tu = 64;
7041
7042 compute_m_n(bits_per_pixel * pixel_clock,
7043 link_clock * nlanes * 8,
7044 &m_n->gmch_m, &m_n->gmch_n);
7045
7046 compute_m_n(pixel_clock, link_clock,
7047 &m_n->link_m, &m_n->link_n);
7048 }
7049
7050 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7051 {
7052 if (i915.panel_use_ssc >= 0)
7053 return i915.panel_use_ssc != 0;
7054 return dev_priv->vbt.lvds_use_ssc
7055 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7056 }
7057
7058 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7059 int num_connectors)
7060 {
7061 struct drm_device *dev = crtc_state->base.crtc->dev;
7062 struct drm_i915_private *dev_priv = dev->dev_private;
7063 int refclk;
7064
7065 WARN_ON(!crtc_state->base.state);
7066
7067 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7068 refclk = 100000;
7069 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7070 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7071 refclk = dev_priv->vbt.lvds_ssc_freq;
7072 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7073 } else if (!IS_GEN2(dev)) {
7074 refclk = 96000;
7075 } else {
7076 refclk = 48000;
7077 }
7078
7079 return refclk;
7080 }
7081
7082 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7083 {
7084 return (1 << dpll->n) << 16 | dpll->m2;
7085 }
7086
7087 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7088 {
7089 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7090 }
7091
7092 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7093 struct intel_crtc_state *crtc_state,
7094 intel_clock_t *reduced_clock)
7095 {
7096 struct drm_device *dev = crtc->base.dev;
7097 u32 fp, fp2 = 0;
7098
7099 if (IS_PINEVIEW(dev)) {
7100 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7101 if (reduced_clock)
7102 fp2 = pnv_dpll_compute_fp(reduced_clock);
7103 } else {
7104 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7105 if (reduced_clock)
7106 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7107 }
7108
7109 crtc_state->dpll_hw_state.fp0 = fp;
7110
7111 crtc->lowfreq_avail = false;
7112 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7113 reduced_clock) {
7114 crtc_state->dpll_hw_state.fp1 = fp2;
7115 crtc->lowfreq_avail = true;
7116 } else {
7117 crtc_state->dpll_hw_state.fp1 = fp;
7118 }
7119 }
7120
7121 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7122 pipe)
7123 {
7124 u32 reg_val;
7125
7126 /*
7127 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7128 * and set it to a reasonable value instead.
7129 */
7130 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7131 reg_val &= 0xffffff00;
7132 reg_val |= 0x00000030;
7133 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7134
7135 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7136 reg_val &= 0x8cffffff;
7137 reg_val = 0x8c000000;
7138 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7139
7140 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7141 reg_val &= 0xffffff00;
7142 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7143
7144 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7145 reg_val &= 0x00ffffff;
7146 reg_val |= 0xb0000000;
7147 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7148 }
7149
7150 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7151 struct intel_link_m_n *m_n)
7152 {
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 int pipe = crtc->pipe;
7156
7157 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7159 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7160 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7161 }
7162
7163 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7164 struct intel_link_m_n *m_n,
7165 struct intel_link_m_n *m2_n2)
7166 {
7167 struct drm_device *dev = crtc->base.dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 int pipe = crtc->pipe;
7170 enum transcoder transcoder = crtc->config->cpu_transcoder;
7171
7172 if (INTEL_INFO(dev)->gen >= 5) {
7173 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7175 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7176 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7177 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7178 * for gen < 8) and if DRRS is supported (to make sure the
7179 * registers are not unnecessarily accessed).
7180 */
7181 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7182 crtc->config->has_drrs) {
7183 I915_WRITE(PIPE_DATA_M2(transcoder),
7184 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7185 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7186 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7187 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7188 }
7189 } else {
7190 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7192 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7193 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7194 }
7195 }
7196
7197 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7198 {
7199 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7200
7201 if (m_n == M1_N1) {
7202 dp_m_n = &crtc->config->dp_m_n;
7203 dp_m2_n2 = &crtc->config->dp_m2_n2;
7204 } else if (m_n == M2_N2) {
7205
7206 /*
7207 * M2_N2 registers are not supported. Hence m2_n2 divider value
7208 * needs to be programmed into M1_N1.
7209 */
7210 dp_m_n = &crtc->config->dp_m2_n2;
7211 } else {
7212 DRM_ERROR("Unsupported divider value\n");
7213 return;
7214 }
7215
7216 if (crtc->config->has_pch_encoder)
7217 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7218 else
7219 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7220 }
7221
7222 static void vlv_compute_dpll(struct intel_crtc *crtc,
7223 struct intel_crtc_state *pipe_config)
7224 {
7225 u32 dpll, dpll_md;
7226
7227 /*
7228 * Enable DPIO clock input. We should never disable the reference
7229 * clock for pipe B, since VGA hotplug / manual detection depends
7230 * on it.
7231 */
7232 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7233 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7234 /* We should never disable this, set it here for state tracking */
7235 if (crtc->pipe == PIPE_B)
7236 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7237 dpll |= DPLL_VCO_ENABLE;
7238 pipe_config->dpll_hw_state.dpll = dpll;
7239
7240 dpll_md = (pipe_config->pixel_multiplier - 1)
7241 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7242 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7243 }
7244
7245 static void vlv_prepare_pll(struct intel_crtc *crtc,
7246 const struct intel_crtc_state *pipe_config)
7247 {
7248 struct drm_device *dev = crtc->base.dev;
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 int pipe = crtc->pipe;
7251 u32 mdiv;
7252 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7253 u32 coreclk, reg_val;
7254
7255 mutex_lock(&dev_priv->sb_lock);
7256
7257 bestn = pipe_config->dpll.n;
7258 bestm1 = pipe_config->dpll.m1;
7259 bestm2 = pipe_config->dpll.m2;
7260 bestp1 = pipe_config->dpll.p1;
7261 bestp2 = pipe_config->dpll.p2;
7262
7263 /* See eDP HDMI DPIO driver vbios notes doc */
7264
7265 /* PLL B needs special handling */
7266 if (pipe == PIPE_B)
7267 vlv_pllb_recal_opamp(dev_priv, pipe);
7268
7269 /* Set up Tx target for periodic Rcomp update */
7270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7271
7272 /* Disable target IRef on PLL */
7273 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7274 reg_val &= 0x00ffffff;
7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7276
7277 /* Disable fast lock */
7278 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7279
7280 /* Set idtafcrecal before PLL is enabled */
7281 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7282 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7283 mdiv |= ((bestn << DPIO_N_SHIFT));
7284 mdiv |= (1 << DPIO_K_SHIFT);
7285
7286 /*
7287 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7288 * but we don't support that).
7289 * Note: don't use the DAC post divider as it seems unstable.
7290 */
7291 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7293
7294 mdiv |= DPIO_ENABLE_CALIBRATION;
7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7296
7297 /* Set HBR and RBR LPF coefficients */
7298 if (pipe_config->port_clock == 162000 ||
7299 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7300 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7302 0x009f0003);
7303 else
7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7305 0x00d0000f);
7306
7307 if (pipe_config->has_dp_encoder) {
7308 /* Use SSC source */
7309 if (pipe == PIPE_A)
7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7311 0x0df40000);
7312 else
7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7314 0x0df70000);
7315 } else { /* HDMI or VGA */
7316 /* Use bend source */
7317 if (pipe == PIPE_A)
7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319 0x0df70000);
7320 else
7321 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7322 0x0df40000);
7323 }
7324
7325 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7326 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7328 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7329 coreclk |= 0x01000000;
7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7331
7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7333 mutex_unlock(&dev_priv->sb_lock);
7334 }
7335
7336 static void chv_compute_dpll(struct intel_crtc *crtc,
7337 struct intel_crtc_state *pipe_config)
7338 {
7339 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7340 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7341 DPLL_VCO_ENABLE;
7342 if (crtc->pipe != PIPE_A)
7343 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7344
7345 pipe_config->dpll_hw_state.dpll_md =
7346 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7347 }
7348
7349 static void chv_prepare_pll(struct intel_crtc *crtc,
7350 const struct intel_crtc_state *pipe_config)
7351 {
7352 struct drm_device *dev = crtc->base.dev;
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354 int pipe = crtc->pipe;
7355 int dpll_reg = DPLL(crtc->pipe);
7356 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7357 u32 loopfilter, tribuf_calcntr;
7358 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7359 u32 dpio_val;
7360 int vco;
7361
7362 bestn = pipe_config->dpll.n;
7363 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7364 bestm1 = pipe_config->dpll.m1;
7365 bestm2 = pipe_config->dpll.m2 >> 22;
7366 bestp1 = pipe_config->dpll.p1;
7367 bestp2 = pipe_config->dpll.p2;
7368 vco = pipe_config->dpll.vco;
7369 dpio_val = 0;
7370 loopfilter = 0;
7371
7372 /*
7373 * Enable Refclk and SSC
7374 */
7375 I915_WRITE(dpll_reg,
7376 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7377
7378 mutex_lock(&dev_priv->sb_lock);
7379
7380 /* p1 and p2 divider */
7381 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7382 5 << DPIO_CHV_S1_DIV_SHIFT |
7383 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7384 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7385 1 << DPIO_CHV_K_DIV_SHIFT);
7386
7387 /* Feedback post-divider - m2 */
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7389
7390 /* Feedback refclk divider - n and m1 */
7391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7392 DPIO_CHV_M1_DIV_BY_2 |
7393 1 << DPIO_CHV_N_DIV_SHIFT);
7394
7395 /* M2 fraction division */
7396 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7397
7398 /* M2 fraction division enable */
7399 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7400 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7401 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7402 if (bestm2_frac)
7403 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7405
7406 /* Program digital lock detect threshold */
7407 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7408 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7409 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7410 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7411 if (!bestm2_frac)
7412 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7413 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7414
7415 /* Loop filter */
7416 if (vco == 5400000) {
7417 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7418 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7419 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7420 tribuf_calcntr = 0x9;
7421 } else if (vco <= 6200000) {
7422 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7423 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7424 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7425 tribuf_calcntr = 0x9;
7426 } else if (vco <= 6480000) {
7427 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7428 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7429 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430 tribuf_calcntr = 0x8;
7431 } else {
7432 /* Not supported. Apply the same limits as in the max case */
7433 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7434 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7435 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7436 tribuf_calcntr = 0;
7437 }
7438 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7439
7440 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7441 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7442 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7443 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7444
7445 /* AFC Recal */
7446 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7447 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7448 DPIO_AFC_RECAL);
7449
7450 mutex_unlock(&dev_priv->sb_lock);
7451 }
7452
7453 /**
7454 * vlv_force_pll_on - forcibly enable just the PLL
7455 * @dev_priv: i915 private structure
7456 * @pipe: pipe PLL to enable
7457 * @dpll: PLL configuration
7458 *
7459 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7460 * in cases where we need the PLL enabled even when @pipe is not going to
7461 * be enabled.
7462 */
7463 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7464 const struct dpll *dpll)
7465 {
7466 struct intel_crtc *crtc =
7467 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7468 struct intel_crtc_state pipe_config = {
7469 .base.crtc = &crtc->base,
7470 .pixel_multiplier = 1,
7471 .dpll = *dpll,
7472 };
7473
7474 if (IS_CHERRYVIEW(dev)) {
7475 chv_compute_dpll(crtc, &pipe_config);
7476 chv_prepare_pll(crtc, &pipe_config);
7477 chv_enable_pll(crtc, &pipe_config);
7478 } else {
7479 vlv_compute_dpll(crtc, &pipe_config);
7480 vlv_prepare_pll(crtc, &pipe_config);
7481 vlv_enable_pll(crtc, &pipe_config);
7482 }
7483 }
7484
7485 /**
7486 * vlv_force_pll_off - forcibly disable just the PLL
7487 * @dev_priv: i915 private structure
7488 * @pipe: pipe PLL to disable
7489 *
7490 * Disable the PLL for @pipe. To be used in cases where we need
7491 * the PLL enabled even when @pipe is not going to be enabled.
7492 */
7493 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7494 {
7495 if (IS_CHERRYVIEW(dev))
7496 chv_disable_pll(to_i915(dev), pipe);
7497 else
7498 vlv_disable_pll(to_i915(dev), pipe);
7499 }
7500
7501 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7502 struct intel_crtc_state *crtc_state,
7503 intel_clock_t *reduced_clock,
7504 int num_connectors)
7505 {
7506 struct drm_device *dev = crtc->base.dev;
7507 struct drm_i915_private *dev_priv = dev->dev_private;
7508 u32 dpll;
7509 bool is_sdvo;
7510 struct dpll *clock = &crtc_state->dpll;
7511
7512 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7513
7514 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7515 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7516
7517 dpll = DPLL_VGA_MODE_DIS;
7518
7519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7520 dpll |= DPLLB_MODE_LVDS;
7521 else
7522 dpll |= DPLLB_MODE_DAC_SERIAL;
7523
7524 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7525 dpll |= (crtc_state->pixel_multiplier - 1)
7526 << SDVO_MULTIPLIER_SHIFT_HIRES;
7527 }
7528
7529 if (is_sdvo)
7530 dpll |= DPLL_SDVO_HIGH_SPEED;
7531
7532 if (crtc_state->has_dp_encoder)
7533 dpll |= DPLL_SDVO_HIGH_SPEED;
7534
7535 /* compute bitmask from p1 value */
7536 if (IS_PINEVIEW(dev))
7537 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7538 else {
7539 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7540 if (IS_G4X(dev) && reduced_clock)
7541 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7542 }
7543 switch (clock->p2) {
7544 case 5:
7545 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7546 break;
7547 case 7:
7548 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7549 break;
7550 case 10:
7551 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7552 break;
7553 case 14:
7554 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7555 break;
7556 }
7557 if (INTEL_INFO(dev)->gen >= 4)
7558 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7559
7560 if (crtc_state->sdvo_tv_clock)
7561 dpll |= PLL_REF_INPUT_TVCLKINBC;
7562 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7563 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7564 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7565 else
7566 dpll |= PLL_REF_INPUT_DREFCLK;
7567
7568 dpll |= DPLL_VCO_ENABLE;
7569 crtc_state->dpll_hw_state.dpll = dpll;
7570
7571 if (INTEL_INFO(dev)->gen >= 4) {
7572 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7573 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7574 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7575 }
7576 }
7577
7578 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7579 struct intel_crtc_state *crtc_state,
7580 intel_clock_t *reduced_clock,
7581 int num_connectors)
7582 {
7583 struct drm_device *dev = crtc->base.dev;
7584 struct drm_i915_private *dev_priv = dev->dev_private;
7585 u32 dpll;
7586 struct dpll *clock = &crtc_state->dpll;
7587
7588 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7589
7590 dpll = DPLL_VGA_MODE_DIS;
7591
7592 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7594 } else {
7595 if (clock->p1 == 2)
7596 dpll |= PLL_P1_DIVIDE_BY_TWO;
7597 else
7598 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7599 if (clock->p2 == 4)
7600 dpll |= PLL_P2_DIVIDE_BY_4;
7601 }
7602
7603 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7604 dpll |= DPLL_DVO_2X_MODE;
7605
7606 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7607 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7609 else
7610 dpll |= PLL_REF_INPUT_DREFCLK;
7611
7612 dpll |= DPLL_VCO_ENABLE;
7613 crtc_state->dpll_hw_state.dpll = dpll;
7614 }
7615
7616 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7617 {
7618 struct drm_device *dev = intel_crtc->base.dev;
7619 struct drm_i915_private *dev_priv = dev->dev_private;
7620 enum pipe pipe = intel_crtc->pipe;
7621 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7622 struct drm_display_mode *adjusted_mode =
7623 &intel_crtc->config->base.adjusted_mode;
7624 uint32_t crtc_vtotal, crtc_vblank_end;
7625 int vsyncshift = 0;
7626
7627 /* We need to be careful not to changed the adjusted mode, for otherwise
7628 * the hw state checker will get angry at the mismatch. */
7629 crtc_vtotal = adjusted_mode->crtc_vtotal;
7630 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7631
7632 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7633 /* the chip adds 2 halflines automatically */
7634 crtc_vtotal -= 1;
7635 crtc_vblank_end -= 1;
7636
7637 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7638 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7639 else
7640 vsyncshift = adjusted_mode->crtc_hsync_start -
7641 adjusted_mode->crtc_htotal / 2;
7642 if (vsyncshift < 0)
7643 vsyncshift += adjusted_mode->crtc_htotal;
7644 }
7645
7646 if (INTEL_INFO(dev)->gen > 3)
7647 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7648
7649 I915_WRITE(HTOTAL(cpu_transcoder),
7650 (adjusted_mode->crtc_hdisplay - 1) |
7651 ((adjusted_mode->crtc_htotal - 1) << 16));
7652 I915_WRITE(HBLANK(cpu_transcoder),
7653 (adjusted_mode->crtc_hblank_start - 1) |
7654 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7655 I915_WRITE(HSYNC(cpu_transcoder),
7656 (adjusted_mode->crtc_hsync_start - 1) |
7657 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7658
7659 I915_WRITE(VTOTAL(cpu_transcoder),
7660 (adjusted_mode->crtc_vdisplay - 1) |
7661 ((crtc_vtotal - 1) << 16));
7662 I915_WRITE(VBLANK(cpu_transcoder),
7663 (adjusted_mode->crtc_vblank_start - 1) |
7664 ((crtc_vblank_end - 1) << 16));
7665 I915_WRITE(VSYNC(cpu_transcoder),
7666 (adjusted_mode->crtc_vsync_start - 1) |
7667 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7668
7669 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7670 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7671 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7672 * bits. */
7673 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7674 (pipe == PIPE_B || pipe == PIPE_C))
7675 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7676
7677 /* pipesrc controls the size that is scaled from, which should
7678 * always be the user's requested size.
7679 */
7680 I915_WRITE(PIPESRC(pipe),
7681 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7682 (intel_crtc->config->pipe_src_h - 1));
7683 }
7684
7685 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7686 struct intel_crtc_state *pipe_config)
7687 {
7688 struct drm_device *dev = crtc->base.dev;
7689 struct drm_i915_private *dev_priv = dev->dev_private;
7690 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7691 uint32_t tmp;
7692
7693 tmp = I915_READ(HTOTAL(cpu_transcoder));
7694 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7696 tmp = I915_READ(HBLANK(cpu_transcoder));
7697 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7698 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7699 tmp = I915_READ(HSYNC(cpu_transcoder));
7700 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7701 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7702
7703 tmp = I915_READ(VTOTAL(cpu_transcoder));
7704 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7705 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7706 tmp = I915_READ(VBLANK(cpu_transcoder));
7707 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7708 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7709 tmp = I915_READ(VSYNC(cpu_transcoder));
7710 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7711 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7712
7713 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7714 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7715 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7716 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7717 }
7718
7719 tmp = I915_READ(PIPESRC(crtc->pipe));
7720 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7721 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7722
7723 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7724 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7725 }
7726
7727 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7728 struct intel_crtc_state *pipe_config)
7729 {
7730 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7731 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7732 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7733 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7734
7735 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7736 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7737 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7738 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7739
7740 mode->flags = pipe_config->base.adjusted_mode.flags;
7741 mode->type = DRM_MODE_TYPE_DRIVER;
7742
7743 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7744 mode->flags |= pipe_config->base.adjusted_mode.flags;
7745
7746 mode->hsync = drm_mode_hsync(mode);
7747 mode->vrefresh = drm_mode_vrefresh(mode);
7748 drm_mode_set_name(mode);
7749 }
7750
7751 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7752 {
7753 struct drm_device *dev = intel_crtc->base.dev;
7754 struct drm_i915_private *dev_priv = dev->dev_private;
7755 uint32_t pipeconf;
7756
7757 pipeconf = 0;
7758
7759 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7760 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7761 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7762
7763 if (intel_crtc->config->double_wide)
7764 pipeconf |= PIPECONF_DOUBLE_WIDE;
7765
7766 /* only g4x and later have fancy bpc/dither controls */
7767 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7768 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7769 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7770 pipeconf |= PIPECONF_DITHER_EN |
7771 PIPECONF_DITHER_TYPE_SP;
7772
7773 switch (intel_crtc->config->pipe_bpp) {
7774 case 18:
7775 pipeconf |= PIPECONF_6BPC;
7776 break;
7777 case 24:
7778 pipeconf |= PIPECONF_8BPC;
7779 break;
7780 case 30:
7781 pipeconf |= PIPECONF_10BPC;
7782 break;
7783 default:
7784 /* Case prevented by intel_choose_pipe_bpp_dither. */
7785 BUG();
7786 }
7787 }
7788
7789 if (HAS_PIPE_CXSR(dev)) {
7790 if (intel_crtc->lowfreq_avail) {
7791 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7792 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7793 } else {
7794 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7795 }
7796 }
7797
7798 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7799 if (INTEL_INFO(dev)->gen < 4 ||
7800 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7801 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7802 else
7803 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7804 } else
7805 pipeconf |= PIPECONF_PROGRESSIVE;
7806
7807 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7808 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7809
7810 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7811 POSTING_READ(PIPECONF(intel_crtc->pipe));
7812 }
7813
7814 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7815 struct intel_crtc_state *crtc_state)
7816 {
7817 struct drm_device *dev = crtc->base.dev;
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819 int refclk, num_connectors = 0;
7820 intel_clock_t clock;
7821 bool ok;
7822 bool is_dsi = false;
7823 struct intel_encoder *encoder;
7824 const intel_limit_t *limit;
7825 struct drm_atomic_state *state = crtc_state->base.state;
7826 struct drm_connector *connector;
7827 struct drm_connector_state *connector_state;
7828 int i;
7829
7830 memset(&crtc_state->dpll_hw_state, 0,
7831 sizeof(crtc_state->dpll_hw_state));
7832
7833 for_each_connector_in_state(state, connector, connector_state, i) {
7834 if (connector_state->crtc != &crtc->base)
7835 continue;
7836
7837 encoder = to_intel_encoder(connector_state->best_encoder);
7838
7839 switch (encoder->type) {
7840 case INTEL_OUTPUT_DSI:
7841 is_dsi = true;
7842 break;
7843 default:
7844 break;
7845 }
7846
7847 num_connectors++;
7848 }
7849
7850 if (is_dsi)
7851 return 0;
7852
7853 if (!crtc_state->clock_set) {
7854 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7855
7856 /*
7857 * Returns a set of divisors for the desired target clock with
7858 * the given refclk, or FALSE. The returned values represent
7859 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7860 * 2) / p1 / p2.
7861 */
7862 limit = intel_limit(crtc_state, refclk);
7863 ok = dev_priv->display.find_dpll(limit, crtc_state,
7864 crtc_state->port_clock,
7865 refclk, NULL, &clock);
7866 if (!ok) {
7867 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7868 return -EINVAL;
7869 }
7870
7871 /* Compat-code for transition, will disappear. */
7872 crtc_state->dpll.n = clock.n;
7873 crtc_state->dpll.m1 = clock.m1;
7874 crtc_state->dpll.m2 = clock.m2;
7875 crtc_state->dpll.p1 = clock.p1;
7876 crtc_state->dpll.p2 = clock.p2;
7877 }
7878
7879 if (IS_GEN2(dev)) {
7880 i8xx_compute_dpll(crtc, crtc_state, NULL,
7881 num_connectors);
7882 } else if (IS_CHERRYVIEW(dev)) {
7883 chv_compute_dpll(crtc, crtc_state);
7884 } else if (IS_VALLEYVIEW(dev)) {
7885 vlv_compute_dpll(crtc, crtc_state);
7886 } else {
7887 i9xx_compute_dpll(crtc, crtc_state, NULL,
7888 num_connectors);
7889 }
7890
7891 return 0;
7892 }
7893
7894 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7895 struct intel_crtc_state *pipe_config)
7896 {
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 uint32_t tmp;
7900
7901 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7902 return;
7903
7904 tmp = I915_READ(PFIT_CONTROL);
7905 if (!(tmp & PFIT_ENABLE))
7906 return;
7907
7908 /* Check whether the pfit is attached to our pipe. */
7909 if (INTEL_INFO(dev)->gen < 4) {
7910 if (crtc->pipe != PIPE_B)
7911 return;
7912 } else {
7913 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7914 return;
7915 }
7916
7917 pipe_config->gmch_pfit.control = tmp;
7918 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7919 if (INTEL_INFO(dev)->gen < 5)
7920 pipe_config->gmch_pfit.lvds_border_bits =
7921 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7922 }
7923
7924 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7925 struct intel_crtc_state *pipe_config)
7926 {
7927 struct drm_device *dev = crtc->base.dev;
7928 struct drm_i915_private *dev_priv = dev->dev_private;
7929 int pipe = pipe_config->cpu_transcoder;
7930 intel_clock_t clock;
7931 u32 mdiv;
7932 int refclk = 100000;
7933
7934 /* In case of MIPI DPLL will not even be used */
7935 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7936 return;
7937
7938 mutex_lock(&dev_priv->sb_lock);
7939 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7940 mutex_unlock(&dev_priv->sb_lock);
7941
7942 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7943 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7944 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7945 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7946 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7947
7948 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7949 }
7950
7951 static void
7952 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7953 struct intel_initial_plane_config *plane_config)
7954 {
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 u32 val, base, offset;
7958 int pipe = crtc->pipe, plane = crtc->plane;
7959 int fourcc, pixel_format;
7960 unsigned int aligned_height;
7961 struct drm_framebuffer *fb;
7962 struct intel_framebuffer *intel_fb;
7963
7964 val = I915_READ(DSPCNTR(plane));
7965 if (!(val & DISPLAY_PLANE_ENABLE))
7966 return;
7967
7968 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7969 if (!intel_fb) {
7970 DRM_DEBUG_KMS("failed to alloc fb\n");
7971 return;
7972 }
7973
7974 fb = &intel_fb->base;
7975
7976 if (INTEL_INFO(dev)->gen >= 4) {
7977 if (val & DISPPLANE_TILED) {
7978 plane_config->tiling = I915_TILING_X;
7979 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7980 }
7981 }
7982
7983 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7984 fourcc = i9xx_format_to_fourcc(pixel_format);
7985 fb->pixel_format = fourcc;
7986 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7987
7988 if (INTEL_INFO(dev)->gen >= 4) {
7989 if (plane_config->tiling)
7990 offset = I915_READ(DSPTILEOFF(plane));
7991 else
7992 offset = I915_READ(DSPLINOFF(plane));
7993 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7994 } else {
7995 base = I915_READ(DSPADDR(plane));
7996 }
7997 plane_config->base = base;
7998
7999 val = I915_READ(PIPESRC(pipe));
8000 fb->width = ((val >> 16) & 0xfff) + 1;
8001 fb->height = ((val >> 0) & 0xfff) + 1;
8002
8003 val = I915_READ(DSPSTRIDE(pipe));
8004 fb->pitches[0] = val & 0xffffffc0;
8005
8006 aligned_height = intel_fb_align_height(dev, fb->height,
8007 fb->pixel_format,
8008 fb->modifier[0]);
8009
8010 plane_config->size = fb->pitches[0] * aligned_height;
8011
8012 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8013 pipe_name(pipe), plane, fb->width, fb->height,
8014 fb->bits_per_pixel, base, fb->pitches[0],
8015 plane_config->size);
8016
8017 plane_config->fb = intel_fb;
8018 }
8019
8020 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8021 struct intel_crtc_state *pipe_config)
8022 {
8023 struct drm_device *dev = crtc->base.dev;
8024 struct drm_i915_private *dev_priv = dev->dev_private;
8025 int pipe = pipe_config->cpu_transcoder;
8026 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8027 intel_clock_t clock;
8028 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8029 int refclk = 100000;
8030
8031 mutex_lock(&dev_priv->sb_lock);
8032 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8033 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8034 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8035 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8036 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8037 mutex_unlock(&dev_priv->sb_lock);
8038
8039 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8040 clock.m2 = (pll_dw0 & 0xff) << 22;
8041 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8042 clock.m2 |= pll_dw2 & 0x3fffff;
8043 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8044 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8045 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8046
8047 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8048 }
8049
8050 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8051 struct intel_crtc_state *pipe_config)
8052 {
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 uint32_t tmp;
8056
8057 if (!intel_display_power_is_enabled(dev_priv,
8058 POWER_DOMAIN_PIPE(crtc->pipe)))
8059 return false;
8060
8061 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8062 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8063
8064 tmp = I915_READ(PIPECONF(crtc->pipe));
8065 if (!(tmp & PIPECONF_ENABLE))
8066 return false;
8067
8068 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8069 switch (tmp & PIPECONF_BPC_MASK) {
8070 case PIPECONF_6BPC:
8071 pipe_config->pipe_bpp = 18;
8072 break;
8073 case PIPECONF_8BPC:
8074 pipe_config->pipe_bpp = 24;
8075 break;
8076 case PIPECONF_10BPC:
8077 pipe_config->pipe_bpp = 30;
8078 break;
8079 default:
8080 break;
8081 }
8082 }
8083
8084 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8085 pipe_config->limited_color_range = true;
8086
8087 if (INTEL_INFO(dev)->gen < 4)
8088 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8089
8090 intel_get_pipe_timings(crtc, pipe_config);
8091
8092 i9xx_get_pfit_config(crtc, pipe_config);
8093
8094 if (INTEL_INFO(dev)->gen >= 4) {
8095 tmp = I915_READ(DPLL_MD(crtc->pipe));
8096 pipe_config->pixel_multiplier =
8097 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8098 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8099 pipe_config->dpll_hw_state.dpll_md = tmp;
8100 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8101 tmp = I915_READ(DPLL(crtc->pipe));
8102 pipe_config->pixel_multiplier =
8103 ((tmp & SDVO_MULTIPLIER_MASK)
8104 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8105 } else {
8106 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8107 * port and will be fixed up in the encoder->get_config
8108 * function. */
8109 pipe_config->pixel_multiplier = 1;
8110 }
8111 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8112 if (!IS_VALLEYVIEW(dev)) {
8113 /*
8114 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8115 * on 830. Filter it out here so that we don't
8116 * report errors due to that.
8117 */
8118 if (IS_I830(dev))
8119 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8120
8121 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8122 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8123 } else {
8124 /* Mask out read-only status bits. */
8125 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8126 DPLL_PORTC_READY_MASK |
8127 DPLL_PORTB_READY_MASK);
8128 }
8129
8130 if (IS_CHERRYVIEW(dev))
8131 chv_crtc_clock_get(crtc, pipe_config);
8132 else if (IS_VALLEYVIEW(dev))
8133 vlv_crtc_clock_get(crtc, pipe_config);
8134 else
8135 i9xx_crtc_clock_get(crtc, pipe_config);
8136
8137 /*
8138 * Normally the dotclock is filled in by the encoder .get_config()
8139 * but in case the pipe is enabled w/o any ports we need a sane
8140 * default.
8141 */
8142 pipe_config->base.adjusted_mode.crtc_clock =
8143 pipe_config->port_clock / pipe_config->pixel_multiplier;
8144
8145 return true;
8146 }
8147
8148 static void ironlake_init_pch_refclk(struct drm_device *dev)
8149 {
8150 struct drm_i915_private *dev_priv = dev->dev_private;
8151 struct intel_encoder *encoder;
8152 u32 val, final;
8153 bool has_lvds = false;
8154 bool has_cpu_edp = false;
8155 bool has_panel = false;
8156 bool has_ck505 = false;
8157 bool can_ssc = false;
8158
8159 /* We need to take the global config into account */
8160 for_each_intel_encoder(dev, encoder) {
8161 switch (encoder->type) {
8162 case INTEL_OUTPUT_LVDS:
8163 has_panel = true;
8164 has_lvds = true;
8165 break;
8166 case INTEL_OUTPUT_EDP:
8167 has_panel = true;
8168 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8169 has_cpu_edp = true;
8170 break;
8171 default:
8172 break;
8173 }
8174 }
8175
8176 if (HAS_PCH_IBX(dev)) {
8177 has_ck505 = dev_priv->vbt.display_clock_mode;
8178 can_ssc = has_ck505;
8179 } else {
8180 has_ck505 = false;
8181 can_ssc = true;
8182 }
8183
8184 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8185 has_panel, has_lvds, has_ck505);
8186
8187 /* Ironlake: try to setup display ref clock before DPLL
8188 * enabling. This is only under driver's control after
8189 * PCH B stepping, previous chipset stepping should be
8190 * ignoring this setting.
8191 */
8192 val = I915_READ(PCH_DREF_CONTROL);
8193
8194 /* As we must carefully and slowly disable/enable each source in turn,
8195 * compute the final state we want first and check if we need to
8196 * make any changes at all.
8197 */
8198 final = val;
8199 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8200 if (has_ck505)
8201 final |= DREF_NONSPREAD_CK505_ENABLE;
8202 else
8203 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8204
8205 final &= ~DREF_SSC_SOURCE_MASK;
8206 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8207 final &= ~DREF_SSC1_ENABLE;
8208
8209 if (has_panel) {
8210 final |= DREF_SSC_SOURCE_ENABLE;
8211
8212 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8213 final |= DREF_SSC1_ENABLE;
8214
8215 if (has_cpu_edp) {
8216 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8217 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8218 else
8219 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8220 } else
8221 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8222 } else {
8223 final |= DREF_SSC_SOURCE_DISABLE;
8224 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8225 }
8226
8227 if (final == val)
8228 return;
8229
8230 /* Always enable nonspread source */
8231 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8232
8233 if (has_ck505)
8234 val |= DREF_NONSPREAD_CK505_ENABLE;
8235 else
8236 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8237
8238 if (has_panel) {
8239 val &= ~DREF_SSC_SOURCE_MASK;
8240 val |= DREF_SSC_SOURCE_ENABLE;
8241
8242 /* SSC must be turned on before enabling the CPU output */
8243 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8244 DRM_DEBUG_KMS("Using SSC on panel\n");
8245 val |= DREF_SSC1_ENABLE;
8246 } else
8247 val &= ~DREF_SSC1_ENABLE;
8248
8249 /* Get SSC going before enabling the outputs */
8250 I915_WRITE(PCH_DREF_CONTROL, val);
8251 POSTING_READ(PCH_DREF_CONTROL);
8252 udelay(200);
8253
8254 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8255
8256 /* Enable CPU source on CPU attached eDP */
8257 if (has_cpu_edp) {
8258 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8259 DRM_DEBUG_KMS("Using SSC on eDP\n");
8260 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8261 } else
8262 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8263 } else
8264 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8265
8266 I915_WRITE(PCH_DREF_CONTROL, val);
8267 POSTING_READ(PCH_DREF_CONTROL);
8268 udelay(200);
8269 } else {
8270 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8271
8272 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8273
8274 /* Turn off CPU output */
8275 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8276
8277 I915_WRITE(PCH_DREF_CONTROL, val);
8278 POSTING_READ(PCH_DREF_CONTROL);
8279 udelay(200);
8280
8281 /* Turn off the SSC source */
8282 val &= ~DREF_SSC_SOURCE_MASK;
8283 val |= DREF_SSC_SOURCE_DISABLE;
8284
8285 /* Turn off SSC1 */
8286 val &= ~DREF_SSC1_ENABLE;
8287
8288 I915_WRITE(PCH_DREF_CONTROL, val);
8289 POSTING_READ(PCH_DREF_CONTROL);
8290 udelay(200);
8291 }
8292
8293 BUG_ON(val != final);
8294 }
8295
8296 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8297 {
8298 uint32_t tmp;
8299
8300 tmp = I915_READ(SOUTH_CHICKEN2);
8301 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8302 I915_WRITE(SOUTH_CHICKEN2, tmp);
8303
8304 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8305 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8306 DRM_ERROR("FDI mPHY reset assert timeout\n");
8307
8308 tmp = I915_READ(SOUTH_CHICKEN2);
8309 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8310 I915_WRITE(SOUTH_CHICKEN2, tmp);
8311
8312 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8313 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8314 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8315 }
8316
8317 /* WaMPhyProgramming:hsw */
8318 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8319 {
8320 uint32_t tmp;
8321
8322 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8323 tmp &= ~(0xFF << 24);
8324 tmp |= (0x12 << 24);
8325 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8328 tmp |= (1 << 11);
8329 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8332 tmp |= (1 << 11);
8333 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8334
8335 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8336 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8337 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8338
8339 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8340 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8341 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8342
8343 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8344 tmp &= ~(7 << 13);
8345 tmp |= (5 << 13);
8346 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8347
8348 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8349 tmp &= ~(7 << 13);
8350 tmp |= (5 << 13);
8351 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8352
8353 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8354 tmp &= ~0xFF;
8355 tmp |= 0x1C;
8356 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8357
8358 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8359 tmp &= ~0xFF;
8360 tmp |= 0x1C;
8361 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8362
8363 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8364 tmp &= ~(0xFF << 16);
8365 tmp |= (0x1C << 16);
8366 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8367
8368 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8369 tmp &= ~(0xFF << 16);
8370 tmp |= (0x1C << 16);
8371 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8372
8373 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8374 tmp |= (1 << 27);
8375 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8376
8377 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8378 tmp |= (1 << 27);
8379 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8380
8381 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8382 tmp &= ~(0xF << 28);
8383 tmp |= (4 << 28);
8384 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8385
8386 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8387 tmp &= ~(0xF << 28);
8388 tmp |= (4 << 28);
8389 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8390 }
8391
8392 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8393 * Programming" based on the parameters passed:
8394 * - Sequence to enable CLKOUT_DP
8395 * - Sequence to enable CLKOUT_DP without spread
8396 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8397 */
8398 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8399 bool with_fdi)
8400 {
8401 struct drm_i915_private *dev_priv = dev->dev_private;
8402 uint32_t reg, tmp;
8403
8404 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8405 with_spread = true;
8406 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8407 with_fdi = false;
8408
8409 mutex_lock(&dev_priv->sb_lock);
8410
8411 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8412 tmp &= ~SBI_SSCCTL_DISABLE;
8413 tmp |= SBI_SSCCTL_PATHALT;
8414 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8415
8416 udelay(24);
8417
8418 if (with_spread) {
8419 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8420 tmp &= ~SBI_SSCCTL_PATHALT;
8421 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8422
8423 if (with_fdi) {
8424 lpt_reset_fdi_mphy(dev_priv);
8425 lpt_program_fdi_mphy(dev_priv);
8426 }
8427 }
8428
8429 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8430 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8431 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8432 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8433
8434 mutex_unlock(&dev_priv->sb_lock);
8435 }
8436
8437 /* Sequence to disable CLKOUT_DP */
8438 static void lpt_disable_clkout_dp(struct drm_device *dev)
8439 {
8440 struct drm_i915_private *dev_priv = dev->dev_private;
8441 uint32_t reg, tmp;
8442
8443 mutex_lock(&dev_priv->sb_lock);
8444
8445 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8446 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8447 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8448 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8449
8450 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8451 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8452 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8453 tmp |= SBI_SSCCTL_PATHALT;
8454 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8455 udelay(32);
8456 }
8457 tmp |= SBI_SSCCTL_DISABLE;
8458 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8459 }
8460
8461 mutex_unlock(&dev_priv->sb_lock);
8462 }
8463
8464 static void lpt_init_pch_refclk(struct drm_device *dev)
8465 {
8466 struct intel_encoder *encoder;
8467 bool has_vga = false;
8468
8469 for_each_intel_encoder(dev, encoder) {
8470 switch (encoder->type) {
8471 case INTEL_OUTPUT_ANALOG:
8472 has_vga = true;
8473 break;
8474 default:
8475 break;
8476 }
8477 }
8478
8479 if (has_vga)
8480 lpt_enable_clkout_dp(dev, true, true);
8481 else
8482 lpt_disable_clkout_dp(dev);
8483 }
8484
8485 /*
8486 * Initialize reference clocks when the driver loads
8487 */
8488 void intel_init_pch_refclk(struct drm_device *dev)
8489 {
8490 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8491 ironlake_init_pch_refclk(dev);
8492 else if (HAS_PCH_LPT(dev))
8493 lpt_init_pch_refclk(dev);
8494 }
8495
8496 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8497 {
8498 struct drm_device *dev = crtc_state->base.crtc->dev;
8499 struct drm_i915_private *dev_priv = dev->dev_private;
8500 struct drm_atomic_state *state = crtc_state->base.state;
8501 struct drm_connector *connector;
8502 struct drm_connector_state *connector_state;
8503 struct intel_encoder *encoder;
8504 int num_connectors = 0, i;
8505 bool is_lvds = false;
8506
8507 for_each_connector_in_state(state, connector, connector_state, i) {
8508 if (connector_state->crtc != crtc_state->base.crtc)
8509 continue;
8510
8511 encoder = to_intel_encoder(connector_state->best_encoder);
8512
8513 switch (encoder->type) {
8514 case INTEL_OUTPUT_LVDS:
8515 is_lvds = true;
8516 break;
8517 default:
8518 break;
8519 }
8520 num_connectors++;
8521 }
8522
8523 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8524 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8525 dev_priv->vbt.lvds_ssc_freq);
8526 return dev_priv->vbt.lvds_ssc_freq;
8527 }
8528
8529 return 120000;
8530 }
8531
8532 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8533 {
8534 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8536 int pipe = intel_crtc->pipe;
8537 uint32_t val;
8538
8539 val = 0;
8540
8541 switch (intel_crtc->config->pipe_bpp) {
8542 case 18:
8543 val |= PIPECONF_6BPC;
8544 break;
8545 case 24:
8546 val |= PIPECONF_8BPC;
8547 break;
8548 case 30:
8549 val |= PIPECONF_10BPC;
8550 break;
8551 case 36:
8552 val |= PIPECONF_12BPC;
8553 break;
8554 default:
8555 /* Case prevented by intel_choose_pipe_bpp_dither. */
8556 BUG();
8557 }
8558
8559 if (intel_crtc->config->dither)
8560 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8561
8562 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8563 val |= PIPECONF_INTERLACED_ILK;
8564 else
8565 val |= PIPECONF_PROGRESSIVE;
8566
8567 if (intel_crtc->config->limited_color_range)
8568 val |= PIPECONF_COLOR_RANGE_SELECT;
8569
8570 I915_WRITE(PIPECONF(pipe), val);
8571 POSTING_READ(PIPECONF(pipe));
8572 }
8573
8574 /*
8575 * Set up the pipe CSC unit.
8576 *
8577 * Currently only full range RGB to limited range RGB conversion
8578 * is supported, but eventually this should handle various
8579 * RGB<->YCbCr scenarios as well.
8580 */
8581 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8582 {
8583 struct drm_device *dev = crtc->dev;
8584 struct drm_i915_private *dev_priv = dev->dev_private;
8585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8586 int pipe = intel_crtc->pipe;
8587 uint16_t coeff = 0x7800; /* 1.0 */
8588
8589 /*
8590 * TODO: Check what kind of values actually come out of the pipe
8591 * with these coeff/postoff values and adjust to get the best
8592 * accuracy. Perhaps we even need to take the bpc value into
8593 * consideration.
8594 */
8595
8596 if (intel_crtc->config->limited_color_range)
8597 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8598
8599 /*
8600 * GY/GU and RY/RU should be the other way around according
8601 * to BSpec, but reality doesn't agree. Just set them up in
8602 * a way that results in the correct picture.
8603 */
8604 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8605 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8606
8607 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8608 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8609
8610 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8611 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8612
8613 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8614 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8615 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8616
8617 if (INTEL_INFO(dev)->gen > 6) {
8618 uint16_t postoff = 0;
8619
8620 if (intel_crtc->config->limited_color_range)
8621 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8622
8623 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8624 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8625 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8626
8627 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8628 } else {
8629 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8630
8631 if (intel_crtc->config->limited_color_range)
8632 mode |= CSC_BLACK_SCREEN_OFFSET;
8633
8634 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8635 }
8636 }
8637
8638 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8639 {
8640 struct drm_device *dev = crtc->dev;
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8643 enum pipe pipe = intel_crtc->pipe;
8644 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8645 uint32_t val;
8646
8647 val = 0;
8648
8649 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8650 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8651
8652 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8653 val |= PIPECONF_INTERLACED_ILK;
8654 else
8655 val |= PIPECONF_PROGRESSIVE;
8656
8657 I915_WRITE(PIPECONF(cpu_transcoder), val);
8658 POSTING_READ(PIPECONF(cpu_transcoder));
8659
8660 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8661 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8662
8663 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8664 val = 0;
8665
8666 switch (intel_crtc->config->pipe_bpp) {
8667 case 18:
8668 val |= PIPEMISC_DITHER_6_BPC;
8669 break;
8670 case 24:
8671 val |= PIPEMISC_DITHER_8_BPC;
8672 break;
8673 case 30:
8674 val |= PIPEMISC_DITHER_10_BPC;
8675 break;
8676 case 36:
8677 val |= PIPEMISC_DITHER_12_BPC;
8678 break;
8679 default:
8680 /* Case prevented by pipe_config_set_bpp. */
8681 BUG();
8682 }
8683
8684 if (intel_crtc->config->dither)
8685 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8686
8687 I915_WRITE(PIPEMISC(pipe), val);
8688 }
8689 }
8690
8691 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8692 struct intel_crtc_state *crtc_state,
8693 intel_clock_t *clock,
8694 bool *has_reduced_clock,
8695 intel_clock_t *reduced_clock)
8696 {
8697 struct drm_device *dev = crtc->dev;
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 int refclk;
8700 const intel_limit_t *limit;
8701 bool ret;
8702
8703 refclk = ironlake_get_refclk(crtc_state);
8704
8705 /*
8706 * Returns a set of divisors for the desired target clock with the given
8707 * refclk, or FALSE. The returned values represent the clock equation:
8708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8709 */
8710 limit = intel_limit(crtc_state, refclk);
8711 ret = dev_priv->display.find_dpll(limit, crtc_state,
8712 crtc_state->port_clock,
8713 refclk, NULL, clock);
8714 if (!ret)
8715 return false;
8716
8717 return true;
8718 }
8719
8720 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8721 {
8722 /*
8723 * Account for spread spectrum to avoid
8724 * oversubscribing the link. Max center spread
8725 * is 2.5%; use 5% for safety's sake.
8726 */
8727 u32 bps = target_clock * bpp * 21 / 20;
8728 return DIV_ROUND_UP(bps, link_bw * 8);
8729 }
8730
8731 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8732 {
8733 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8734 }
8735
8736 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8737 struct intel_crtc_state *crtc_state,
8738 u32 *fp,
8739 intel_clock_t *reduced_clock, u32 *fp2)
8740 {
8741 struct drm_crtc *crtc = &intel_crtc->base;
8742 struct drm_device *dev = crtc->dev;
8743 struct drm_i915_private *dev_priv = dev->dev_private;
8744 struct drm_atomic_state *state = crtc_state->base.state;
8745 struct drm_connector *connector;
8746 struct drm_connector_state *connector_state;
8747 struct intel_encoder *encoder;
8748 uint32_t dpll;
8749 int factor, num_connectors = 0, i;
8750 bool is_lvds = false, is_sdvo = false;
8751
8752 for_each_connector_in_state(state, connector, connector_state, i) {
8753 if (connector_state->crtc != crtc_state->base.crtc)
8754 continue;
8755
8756 encoder = to_intel_encoder(connector_state->best_encoder);
8757
8758 switch (encoder->type) {
8759 case INTEL_OUTPUT_LVDS:
8760 is_lvds = true;
8761 break;
8762 case INTEL_OUTPUT_SDVO:
8763 case INTEL_OUTPUT_HDMI:
8764 is_sdvo = true;
8765 break;
8766 default:
8767 break;
8768 }
8769
8770 num_connectors++;
8771 }
8772
8773 /* Enable autotuning of the PLL clock (if permissible) */
8774 factor = 21;
8775 if (is_lvds) {
8776 if ((intel_panel_use_ssc(dev_priv) &&
8777 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8778 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8779 factor = 25;
8780 } else if (crtc_state->sdvo_tv_clock)
8781 factor = 20;
8782
8783 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8784 *fp |= FP_CB_TUNE;
8785
8786 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8787 *fp2 |= FP_CB_TUNE;
8788
8789 dpll = 0;
8790
8791 if (is_lvds)
8792 dpll |= DPLLB_MODE_LVDS;
8793 else
8794 dpll |= DPLLB_MODE_DAC_SERIAL;
8795
8796 dpll |= (crtc_state->pixel_multiplier - 1)
8797 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8798
8799 if (is_sdvo)
8800 dpll |= DPLL_SDVO_HIGH_SPEED;
8801 if (crtc_state->has_dp_encoder)
8802 dpll |= DPLL_SDVO_HIGH_SPEED;
8803
8804 /* compute bitmask from p1 value */
8805 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8806 /* also FPA1 */
8807 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8808
8809 switch (crtc_state->dpll.p2) {
8810 case 5:
8811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8812 break;
8813 case 7:
8814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8815 break;
8816 case 10:
8817 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8818 break;
8819 case 14:
8820 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8821 break;
8822 }
8823
8824 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8825 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8826 else
8827 dpll |= PLL_REF_INPUT_DREFCLK;
8828
8829 return dpll | DPLL_VCO_ENABLE;
8830 }
8831
8832 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8833 struct intel_crtc_state *crtc_state)
8834 {
8835 struct drm_device *dev = crtc->base.dev;
8836 intel_clock_t clock, reduced_clock;
8837 u32 dpll = 0, fp = 0, fp2 = 0;
8838 bool ok, has_reduced_clock = false;
8839 bool is_lvds = false;
8840 struct intel_shared_dpll *pll;
8841
8842 memset(&crtc_state->dpll_hw_state, 0,
8843 sizeof(crtc_state->dpll_hw_state));
8844
8845 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8846
8847 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8848 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8849
8850 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8851 &has_reduced_clock, &reduced_clock);
8852 if (!ok && !crtc_state->clock_set) {
8853 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8854 return -EINVAL;
8855 }
8856 /* Compat-code for transition, will disappear. */
8857 if (!crtc_state->clock_set) {
8858 crtc_state->dpll.n = clock.n;
8859 crtc_state->dpll.m1 = clock.m1;
8860 crtc_state->dpll.m2 = clock.m2;
8861 crtc_state->dpll.p1 = clock.p1;
8862 crtc_state->dpll.p2 = clock.p2;
8863 }
8864
8865 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8866 if (crtc_state->has_pch_encoder) {
8867 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8868 if (has_reduced_clock)
8869 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8870
8871 dpll = ironlake_compute_dpll(crtc, crtc_state,
8872 &fp, &reduced_clock,
8873 has_reduced_clock ? &fp2 : NULL);
8874
8875 crtc_state->dpll_hw_state.dpll = dpll;
8876 crtc_state->dpll_hw_state.fp0 = fp;
8877 if (has_reduced_clock)
8878 crtc_state->dpll_hw_state.fp1 = fp2;
8879 else
8880 crtc_state->dpll_hw_state.fp1 = fp;
8881
8882 pll = intel_get_shared_dpll(crtc, crtc_state);
8883 if (pll == NULL) {
8884 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8885 pipe_name(crtc->pipe));
8886 return -EINVAL;
8887 }
8888 }
8889
8890 if (is_lvds && has_reduced_clock)
8891 crtc->lowfreq_avail = true;
8892 else
8893 crtc->lowfreq_avail = false;
8894
8895 return 0;
8896 }
8897
8898 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8899 struct intel_link_m_n *m_n)
8900 {
8901 struct drm_device *dev = crtc->base.dev;
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903 enum pipe pipe = crtc->pipe;
8904
8905 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8906 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8907 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8908 & ~TU_SIZE_MASK;
8909 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8910 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8911 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8912 }
8913
8914 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8915 enum transcoder transcoder,
8916 struct intel_link_m_n *m_n,
8917 struct intel_link_m_n *m2_n2)
8918 {
8919 struct drm_device *dev = crtc->base.dev;
8920 struct drm_i915_private *dev_priv = dev->dev_private;
8921 enum pipe pipe = crtc->pipe;
8922
8923 if (INTEL_INFO(dev)->gen >= 5) {
8924 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8925 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8926 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8927 & ~TU_SIZE_MASK;
8928 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8929 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8930 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8931 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8932 * gen < 8) and if DRRS is supported (to make sure the
8933 * registers are not unnecessarily read).
8934 */
8935 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8936 crtc->config->has_drrs) {
8937 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8938 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8939 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8940 & ~TU_SIZE_MASK;
8941 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8942 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8943 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8944 }
8945 } else {
8946 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8947 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8948 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8949 & ~TU_SIZE_MASK;
8950 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8951 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8952 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8953 }
8954 }
8955
8956 void intel_dp_get_m_n(struct intel_crtc *crtc,
8957 struct intel_crtc_state *pipe_config)
8958 {
8959 if (pipe_config->has_pch_encoder)
8960 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8961 else
8962 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8963 &pipe_config->dp_m_n,
8964 &pipe_config->dp_m2_n2);
8965 }
8966
8967 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8968 struct intel_crtc_state *pipe_config)
8969 {
8970 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8971 &pipe_config->fdi_m_n, NULL);
8972 }
8973
8974 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8975 struct intel_crtc_state *pipe_config)
8976 {
8977 struct drm_device *dev = crtc->base.dev;
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8980 uint32_t ps_ctrl = 0;
8981 int id = -1;
8982 int i;
8983
8984 /* find scaler attached to this pipe */
8985 for (i = 0; i < crtc->num_scalers; i++) {
8986 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8987 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8988 id = i;
8989 pipe_config->pch_pfit.enabled = true;
8990 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8991 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8992 break;
8993 }
8994 }
8995
8996 scaler_state->scaler_id = id;
8997 if (id >= 0) {
8998 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8999 } else {
9000 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9001 }
9002 }
9003
9004 static void
9005 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9006 struct intel_initial_plane_config *plane_config)
9007 {
9008 struct drm_device *dev = crtc->base.dev;
9009 struct drm_i915_private *dev_priv = dev->dev_private;
9010 u32 val, base, offset, stride_mult, tiling;
9011 int pipe = crtc->pipe;
9012 int fourcc, pixel_format;
9013 unsigned int aligned_height;
9014 struct drm_framebuffer *fb;
9015 struct intel_framebuffer *intel_fb;
9016
9017 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9018 if (!intel_fb) {
9019 DRM_DEBUG_KMS("failed to alloc fb\n");
9020 return;
9021 }
9022
9023 fb = &intel_fb->base;
9024
9025 val = I915_READ(PLANE_CTL(pipe, 0));
9026 if (!(val & PLANE_CTL_ENABLE))
9027 goto error;
9028
9029 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9030 fourcc = skl_format_to_fourcc(pixel_format,
9031 val & PLANE_CTL_ORDER_RGBX,
9032 val & PLANE_CTL_ALPHA_MASK);
9033 fb->pixel_format = fourcc;
9034 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9035
9036 tiling = val & PLANE_CTL_TILED_MASK;
9037 switch (tiling) {
9038 case PLANE_CTL_TILED_LINEAR:
9039 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9040 break;
9041 case PLANE_CTL_TILED_X:
9042 plane_config->tiling = I915_TILING_X;
9043 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9044 break;
9045 case PLANE_CTL_TILED_Y:
9046 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9047 break;
9048 case PLANE_CTL_TILED_YF:
9049 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9050 break;
9051 default:
9052 MISSING_CASE(tiling);
9053 goto error;
9054 }
9055
9056 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9057 plane_config->base = base;
9058
9059 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9060
9061 val = I915_READ(PLANE_SIZE(pipe, 0));
9062 fb->height = ((val >> 16) & 0xfff) + 1;
9063 fb->width = ((val >> 0) & 0x1fff) + 1;
9064
9065 val = I915_READ(PLANE_STRIDE(pipe, 0));
9066 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9067 fb->pixel_format);
9068 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9069
9070 aligned_height = intel_fb_align_height(dev, fb->height,
9071 fb->pixel_format,
9072 fb->modifier[0]);
9073
9074 plane_config->size = fb->pitches[0] * aligned_height;
9075
9076 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9077 pipe_name(pipe), fb->width, fb->height,
9078 fb->bits_per_pixel, base, fb->pitches[0],
9079 plane_config->size);
9080
9081 plane_config->fb = intel_fb;
9082 return;
9083
9084 error:
9085 kfree(fb);
9086 }
9087
9088 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9089 struct intel_crtc_state *pipe_config)
9090 {
9091 struct drm_device *dev = crtc->base.dev;
9092 struct drm_i915_private *dev_priv = dev->dev_private;
9093 uint32_t tmp;
9094
9095 tmp = I915_READ(PF_CTL(crtc->pipe));
9096
9097 if (tmp & PF_ENABLE) {
9098 pipe_config->pch_pfit.enabled = true;
9099 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9100 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9101
9102 /* We currently do not free assignements of panel fitters on
9103 * ivb/hsw (since we don't use the higher upscaling modes which
9104 * differentiates them) so just WARN about this case for now. */
9105 if (IS_GEN7(dev)) {
9106 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9107 PF_PIPE_SEL_IVB(crtc->pipe));
9108 }
9109 }
9110 }
9111
9112 static void
9113 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9114 struct intel_initial_plane_config *plane_config)
9115 {
9116 struct drm_device *dev = crtc->base.dev;
9117 struct drm_i915_private *dev_priv = dev->dev_private;
9118 u32 val, base, offset;
9119 int pipe = crtc->pipe;
9120 int fourcc, pixel_format;
9121 unsigned int aligned_height;
9122 struct drm_framebuffer *fb;
9123 struct intel_framebuffer *intel_fb;
9124
9125 val = I915_READ(DSPCNTR(pipe));
9126 if (!(val & DISPLAY_PLANE_ENABLE))
9127 return;
9128
9129 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9130 if (!intel_fb) {
9131 DRM_DEBUG_KMS("failed to alloc fb\n");
9132 return;
9133 }
9134
9135 fb = &intel_fb->base;
9136
9137 if (INTEL_INFO(dev)->gen >= 4) {
9138 if (val & DISPPLANE_TILED) {
9139 plane_config->tiling = I915_TILING_X;
9140 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9141 }
9142 }
9143
9144 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9145 fourcc = i9xx_format_to_fourcc(pixel_format);
9146 fb->pixel_format = fourcc;
9147 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9148
9149 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9150 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9151 offset = I915_READ(DSPOFFSET(pipe));
9152 } else {
9153 if (plane_config->tiling)
9154 offset = I915_READ(DSPTILEOFF(pipe));
9155 else
9156 offset = I915_READ(DSPLINOFF(pipe));
9157 }
9158 plane_config->base = base;
9159
9160 val = I915_READ(PIPESRC(pipe));
9161 fb->width = ((val >> 16) & 0xfff) + 1;
9162 fb->height = ((val >> 0) & 0xfff) + 1;
9163
9164 val = I915_READ(DSPSTRIDE(pipe));
9165 fb->pitches[0] = val & 0xffffffc0;
9166
9167 aligned_height = intel_fb_align_height(dev, fb->height,
9168 fb->pixel_format,
9169 fb->modifier[0]);
9170
9171 plane_config->size = fb->pitches[0] * aligned_height;
9172
9173 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9174 pipe_name(pipe), fb->width, fb->height,
9175 fb->bits_per_pixel, base, fb->pitches[0],
9176 plane_config->size);
9177
9178 plane_config->fb = intel_fb;
9179 }
9180
9181 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9182 struct intel_crtc_state *pipe_config)
9183 {
9184 struct drm_device *dev = crtc->base.dev;
9185 struct drm_i915_private *dev_priv = dev->dev_private;
9186 uint32_t tmp;
9187
9188 if (!intel_display_power_is_enabled(dev_priv,
9189 POWER_DOMAIN_PIPE(crtc->pipe)))
9190 return false;
9191
9192 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9193 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9194
9195 tmp = I915_READ(PIPECONF(crtc->pipe));
9196 if (!(tmp & PIPECONF_ENABLE))
9197 return false;
9198
9199 switch (tmp & PIPECONF_BPC_MASK) {
9200 case PIPECONF_6BPC:
9201 pipe_config->pipe_bpp = 18;
9202 break;
9203 case PIPECONF_8BPC:
9204 pipe_config->pipe_bpp = 24;
9205 break;
9206 case PIPECONF_10BPC:
9207 pipe_config->pipe_bpp = 30;
9208 break;
9209 case PIPECONF_12BPC:
9210 pipe_config->pipe_bpp = 36;
9211 break;
9212 default:
9213 break;
9214 }
9215
9216 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9217 pipe_config->limited_color_range = true;
9218
9219 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9220 struct intel_shared_dpll *pll;
9221
9222 pipe_config->has_pch_encoder = true;
9223
9224 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9225 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9226 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9227
9228 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9229
9230 if (HAS_PCH_IBX(dev_priv->dev)) {
9231 pipe_config->shared_dpll =
9232 (enum intel_dpll_id) crtc->pipe;
9233 } else {
9234 tmp = I915_READ(PCH_DPLL_SEL);
9235 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9236 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9237 else
9238 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9239 }
9240
9241 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9242
9243 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9244 &pipe_config->dpll_hw_state));
9245
9246 tmp = pipe_config->dpll_hw_state.dpll;
9247 pipe_config->pixel_multiplier =
9248 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9249 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9250
9251 ironlake_pch_clock_get(crtc, pipe_config);
9252 } else {
9253 pipe_config->pixel_multiplier = 1;
9254 }
9255
9256 intel_get_pipe_timings(crtc, pipe_config);
9257
9258 ironlake_get_pfit_config(crtc, pipe_config);
9259
9260 return true;
9261 }
9262
9263 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9264 {
9265 struct drm_device *dev = dev_priv->dev;
9266 struct intel_crtc *crtc;
9267
9268 for_each_intel_crtc(dev, crtc)
9269 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9270 pipe_name(crtc->pipe));
9271
9272 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9273 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9274 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9275 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9276 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9277 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9278 "CPU PWM1 enabled\n");
9279 if (IS_HASWELL(dev))
9280 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9281 "CPU PWM2 enabled\n");
9282 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9283 "PCH PWM1 enabled\n");
9284 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9285 "Utility pin enabled\n");
9286 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9287
9288 /*
9289 * In theory we can still leave IRQs enabled, as long as only the HPD
9290 * interrupts remain enabled. We used to check for that, but since it's
9291 * gen-specific and since we only disable LCPLL after we fully disable
9292 * the interrupts, the check below should be enough.
9293 */
9294 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9295 }
9296
9297 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9298 {
9299 struct drm_device *dev = dev_priv->dev;
9300
9301 if (IS_HASWELL(dev))
9302 return I915_READ(D_COMP_HSW);
9303 else
9304 return I915_READ(D_COMP_BDW);
9305 }
9306
9307 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9308 {
9309 struct drm_device *dev = dev_priv->dev;
9310
9311 if (IS_HASWELL(dev)) {
9312 mutex_lock(&dev_priv->rps.hw_lock);
9313 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9314 val))
9315 DRM_ERROR("Failed to write to D_COMP\n");
9316 mutex_unlock(&dev_priv->rps.hw_lock);
9317 } else {
9318 I915_WRITE(D_COMP_BDW, val);
9319 POSTING_READ(D_COMP_BDW);
9320 }
9321 }
9322
9323 /*
9324 * This function implements pieces of two sequences from BSpec:
9325 * - Sequence for display software to disable LCPLL
9326 * - Sequence for display software to allow package C8+
9327 * The steps implemented here are just the steps that actually touch the LCPLL
9328 * register. Callers should take care of disabling all the display engine
9329 * functions, doing the mode unset, fixing interrupts, etc.
9330 */
9331 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9332 bool switch_to_fclk, bool allow_power_down)
9333 {
9334 uint32_t val;
9335
9336 assert_can_disable_lcpll(dev_priv);
9337
9338 val = I915_READ(LCPLL_CTL);
9339
9340 if (switch_to_fclk) {
9341 val |= LCPLL_CD_SOURCE_FCLK;
9342 I915_WRITE(LCPLL_CTL, val);
9343
9344 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9345 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9346 DRM_ERROR("Switching to FCLK failed\n");
9347
9348 val = I915_READ(LCPLL_CTL);
9349 }
9350
9351 val |= LCPLL_PLL_DISABLE;
9352 I915_WRITE(LCPLL_CTL, val);
9353 POSTING_READ(LCPLL_CTL);
9354
9355 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9356 DRM_ERROR("LCPLL still locked\n");
9357
9358 val = hsw_read_dcomp(dev_priv);
9359 val |= D_COMP_COMP_DISABLE;
9360 hsw_write_dcomp(dev_priv, val);
9361 ndelay(100);
9362
9363 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9364 1))
9365 DRM_ERROR("D_COMP RCOMP still in progress\n");
9366
9367 if (allow_power_down) {
9368 val = I915_READ(LCPLL_CTL);
9369 val |= LCPLL_POWER_DOWN_ALLOW;
9370 I915_WRITE(LCPLL_CTL, val);
9371 POSTING_READ(LCPLL_CTL);
9372 }
9373 }
9374
9375 /*
9376 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9377 * source.
9378 */
9379 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9380 {
9381 uint32_t val;
9382
9383 val = I915_READ(LCPLL_CTL);
9384
9385 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9386 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9387 return;
9388
9389 /*
9390 * Make sure we're not on PC8 state before disabling PC8, otherwise
9391 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9392 */
9393 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9394
9395 if (val & LCPLL_POWER_DOWN_ALLOW) {
9396 val &= ~LCPLL_POWER_DOWN_ALLOW;
9397 I915_WRITE(LCPLL_CTL, val);
9398 POSTING_READ(LCPLL_CTL);
9399 }
9400
9401 val = hsw_read_dcomp(dev_priv);
9402 val |= D_COMP_COMP_FORCE;
9403 val &= ~D_COMP_COMP_DISABLE;
9404 hsw_write_dcomp(dev_priv, val);
9405
9406 val = I915_READ(LCPLL_CTL);
9407 val &= ~LCPLL_PLL_DISABLE;
9408 I915_WRITE(LCPLL_CTL, val);
9409
9410 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9411 DRM_ERROR("LCPLL not locked yet\n");
9412
9413 if (val & LCPLL_CD_SOURCE_FCLK) {
9414 val = I915_READ(LCPLL_CTL);
9415 val &= ~LCPLL_CD_SOURCE_FCLK;
9416 I915_WRITE(LCPLL_CTL, val);
9417
9418 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9419 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9420 DRM_ERROR("Switching back to LCPLL failed\n");
9421 }
9422
9423 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9424 intel_update_cdclk(dev_priv->dev);
9425 }
9426
9427 /*
9428 * Package states C8 and deeper are really deep PC states that can only be
9429 * reached when all the devices on the system allow it, so even if the graphics
9430 * device allows PC8+, it doesn't mean the system will actually get to these
9431 * states. Our driver only allows PC8+ when going into runtime PM.
9432 *
9433 * The requirements for PC8+ are that all the outputs are disabled, the power
9434 * well is disabled and most interrupts are disabled, and these are also
9435 * requirements for runtime PM. When these conditions are met, we manually do
9436 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9437 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9438 * hang the machine.
9439 *
9440 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9441 * the state of some registers, so when we come back from PC8+ we need to
9442 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9443 * need to take care of the registers kept by RC6. Notice that this happens even
9444 * if we don't put the device in PCI D3 state (which is what currently happens
9445 * because of the runtime PM support).
9446 *
9447 * For more, read "Display Sequences for Package C8" on the hardware
9448 * documentation.
9449 */
9450 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9451 {
9452 struct drm_device *dev = dev_priv->dev;
9453 uint32_t val;
9454
9455 DRM_DEBUG_KMS("Enabling package C8+\n");
9456
9457 if (HAS_PCH_LPT_LP(dev)) {
9458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9459 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9461 }
9462
9463 lpt_disable_clkout_dp(dev);
9464 hsw_disable_lcpll(dev_priv, true, true);
9465 }
9466
9467 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9468 {
9469 struct drm_device *dev = dev_priv->dev;
9470 uint32_t val;
9471
9472 DRM_DEBUG_KMS("Disabling package C8+\n");
9473
9474 hsw_restore_lcpll(dev_priv);
9475 lpt_init_pch_refclk(dev);
9476
9477 if (HAS_PCH_LPT_LP(dev)) {
9478 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9479 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9480 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9481 }
9482
9483 intel_prepare_ddi(dev);
9484 }
9485
9486 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9487 {
9488 struct drm_device *dev = old_state->dev;
9489 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9490
9491 broxton_set_cdclk(dev, req_cdclk);
9492 }
9493
9494 /* compute the max rate for new configuration */
9495 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9496 {
9497 struct intel_crtc *intel_crtc;
9498 struct intel_crtc_state *crtc_state;
9499 int max_pixel_rate = 0;
9500
9501 for_each_intel_crtc(state->dev, intel_crtc) {
9502 int pixel_rate;
9503
9504 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9505 if (IS_ERR(crtc_state))
9506 return PTR_ERR(crtc_state);
9507
9508 if (!crtc_state->base.enable)
9509 continue;
9510
9511 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9512
9513 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9514 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9515 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9516
9517 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9518 }
9519
9520 return max_pixel_rate;
9521 }
9522
9523 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9524 {
9525 struct drm_i915_private *dev_priv = dev->dev_private;
9526 uint32_t val, data;
9527 int ret;
9528
9529 if (WARN((I915_READ(LCPLL_CTL) &
9530 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9531 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9532 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9533 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9534 "trying to change cdclk frequency with cdclk not enabled\n"))
9535 return;
9536
9537 mutex_lock(&dev_priv->rps.hw_lock);
9538 ret = sandybridge_pcode_write(dev_priv,
9539 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9540 mutex_unlock(&dev_priv->rps.hw_lock);
9541 if (ret) {
9542 DRM_ERROR("failed to inform pcode about cdclk change\n");
9543 return;
9544 }
9545
9546 val = I915_READ(LCPLL_CTL);
9547 val |= LCPLL_CD_SOURCE_FCLK;
9548 I915_WRITE(LCPLL_CTL, val);
9549
9550 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9551 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9552 DRM_ERROR("Switching to FCLK failed\n");
9553
9554 val = I915_READ(LCPLL_CTL);
9555 val &= ~LCPLL_CLK_FREQ_MASK;
9556
9557 switch (cdclk) {
9558 case 450000:
9559 val |= LCPLL_CLK_FREQ_450;
9560 data = 0;
9561 break;
9562 case 540000:
9563 val |= LCPLL_CLK_FREQ_54O_BDW;
9564 data = 1;
9565 break;
9566 case 337500:
9567 val |= LCPLL_CLK_FREQ_337_5_BDW;
9568 data = 2;
9569 break;
9570 case 675000:
9571 val |= LCPLL_CLK_FREQ_675_BDW;
9572 data = 3;
9573 break;
9574 default:
9575 WARN(1, "invalid cdclk frequency\n");
9576 return;
9577 }
9578
9579 I915_WRITE(LCPLL_CTL, val);
9580
9581 val = I915_READ(LCPLL_CTL);
9582 val &= ~LCPLL_CD_SOURCE_FCLK;
9583 I915_WRITE(LCPLL_CTL, val);
9584
9585 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9586 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9587 DRM_ERROR("Switching back to LCPLL failed\n");
9588
9589 mutex_lock(&dev_priv->rps.hw_lock);
9590 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9591 mutex_unlock(&dev_priv->rps.hw_lock);
9592
9593 intel_update_cdclk(dev);
9594
9595 WARN(cdclk != dev_priv->cdclk_freq,
9596 "cdclk requested %d kHz but got %d kHz\n",
9597 cdclk, dev_priv->cdclk_freq);
9598 }
9599
9600 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9601 {
9602 struct drm_i915_private *dev_priv = to_i915(state->dev);
9603 int max_pixclk = ilk_max_pixel_rate(state);
9604 int cdclk;
9605
9606 /*
9607 * FIXME should also account for plane ratio
9608 * once 64bpp pixel formats are supported.
9609 */
9610 if (max_pixclk > 540000)
9611 cdclk = 675000;
9612 else if (max_pixclk > 450000)
9613 cdclk = 540000;
9614 else if (max_pixclk > 337500)
9615 cdclk = 450000;
9616 else
9617 cdclk = 337500;
9618
9619 /*
9620 * FIXME move the cdclk caclulation to
9621 * compute_config() so we can fail gracegully.
9622 */
9623 if (cdclk > dev_priv->max_cdclk_freq) {
9624 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9625 cdclk, dev_priv->max_cdclk_freq);
9626 cdclk = dev_priv->max_cdclk_freq;
9627 }
9628
9629 to_intel_atomic_state(state)->cdclk = cdclk;
9630
9631 return 0;
9632 }
9633
9634 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9635 {
9636 struct drm_device *dev = old_state->dev;
9637 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9638
9639 broadwell_set_cdclk(dev, req_cdclk);
9640 }
9641
9642 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9643 struct intel_crtc_state *crtc_state)
9644 {
9645 if (!intel_ddi_pll_select(crtc, crtc_state))
9646 return -EINVAL;
9647
9648 crtc->lowfreq_avail = false;
9649
9650 return 0;
9651 }
9652
9653 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9654 enum port port,
9655 struct intel_crtc_state *pipe_config)
9656 {
9657 switch (port) {
9658 case PORT_A:
9659 pipe_config->ddi_pll_sel = SKL_DPLL0;
9660 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9661 break;
9662 case PORT_B:
9663 pipe_config->ddi_pll_sel = SKL_DPLL1;
9664 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9665 break;
9666 case PORT_C:
9667 pipe_config->ddi_pll_sel = SKL_DPLL2;
9668 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9669 break;
9670 default:
9671 DRM_ERROR("Incorrect port type\n");
9672 }
9673 }
9674
9675 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9676 enum port port,
9677 struct intel_crtc_state *pipe_config)
9678 {
9679 u32 temp, dpll_ctl1;
9680
9681 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9682 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9683
9684 switch (pipe_config->ddi_pll_sel) {
9685 case SKL_DPLL0:
9686 /*
9687 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9688 * of the shared DPLL framework and thus needs to be read out
9689 * separately
9690 */
9691 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9692 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9693 break;
9694 case SKL_DPLL1:
9695 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9696 break;
9697 case SKL_DPLL2:
9698 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9699 break;
9700 case SKL_DPLL3:
9701 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9702 break;
9703 }
9704 }
9705
9706 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9707 enum port port,
9708 struct intel_crtc_state *pipe_config)
9709 {
9710 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9711
9712 switch (pipe_config->ddi_pll_sel) {
9713 case PORT_CLK_SEL_WRPLL1:
9714 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9715 break;
9716 case PORT_CLK_SEL_WRPLL2:
9717 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9718 break;
9719 }
9720 }
9721
9722 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9723 struct intel_crtc_state *pipe_config)
9724 {
9725 struct drm_device *dev = crtc->base.dev;
9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 struct intel_shared_dpll *pll;
9728 enum port port;
9729 uint32_t tmp;
9730
9731 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9732
9733 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9734
9735 if (IS_SKYLAKE(dev))
9736 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9737 else if (IS_BROXTON(dev))
9738 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9739 else
9740 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9741
9742 if (pipe_config->shared_dpll >= 0) {
9743 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9744
9745 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9746 &pipe_config->dpll_hw_state));
9747 }
9748
9749 /*
9750 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9751 * DDI E. So just check whether this pipe is wired to DDI E and whether
9752 * the PCH transcoder is on.
9753 */
9754 if (INTEL_INFO(dev)->gen < 9 &&
9755 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9756 pipe_config->has_pch_encoder = true;
9757
9758 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9759 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9760 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9761
9762 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9763 }
9764 }
9765
9766 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9767 struct intel_crtc_state *pipe_config)
9768 {
9769 struct drm_device *dev = crtc->base.dev;
9770 struct drm_i915_private *dev_priv = dev->dev_private;
9771 enum intel_display_power_domain pfit_domain;
9772 uint32_t tmp;
9773
9774 if (!intel_display_power_is_enabled(dev_priv,
9775 POWER_DOMAIN_PIPE(crtc->pipe)))
9776 return false;
9777
9778 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9779 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9780
9781 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9782 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9783 enum pipe trans_edp_pipe;
9784 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9785 default:
9786 WARN(1, "unknown pipe linked to edp transcoder\n");
9787 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9788 case TRANS_DDI_EDP_INPUT_A_ON:
9789 trans_edp_pipe = PIPE_A;
9790 break;
9791 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9792 trans_edp_pipe = PIPE_B;
9793 break;
9794 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9795 trans_edp_pipe = PIPE_C;
9796 break;
9797 }
9798
9799 if (trans_edp_pipe == crtc->pipe)
9800 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9801 }
9802
9803 if (!intel_display_power_is_enabled(dev_priv,
9804 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9805 return false;
9806
9807 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9808 if (!(tmp & PIPECONF_ENABLE))
9809 return false;
9810
9811 haswell_get_ddi_port_state(crtc, pipe_config);
9812
9813 intel_get_pipe_timings(crtc, pipe_config);
9814
9815 if (INTEL_INFO(dev)->gen >= 9) {
9816 skl_init_scalers(dev, crtc, pipe_config);
9817 }
9818
9819 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9820
9821 if (INTEL_INFO(dev)->gen >= 9) {
9822 pipe_config->scaler_state.scaler_id = -1;
9823 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9824 }
9825
9826 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9827 if (INTEL_INFO(dev)->gen >= 9)
9828 skylake_get_pfit_config(crtc, pipe_config);
9829 else
9830 ironlake_get_pfit_config(crtc, pipe_config);
9831 }
9832
9833 if (IS_HASWELL(dev))
9834 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9835 (I915_READ(IPS_CTL) & IPS_ENABLE);
9836
9837 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9838 pipe_config->pixel_multiplier =
9839 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9840 } else {
9841 pipe_config->pixel_multiplier = 1;
9842 }
9843
9844 return true;
9845 }
9846
9847 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9848 {
9849 struct drm_device *dev = crtc->dev;
9850 struct drm_i915_private *dev_priv = dev->dev_private;
9851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9852 uint32_t cntl = 0, size = 0;
9853
9854 if (base) {
9855 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9856 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9857 unsigned int stride = roundup_pow_of_two(width) * 4;
9858
9859 switch (stride) {
9860 default:
9861 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9862 width, stride);
9863 stride = 256;
9864 /* fallthrough */
9865 case 256:
9866 case 512:
9867 case 1024:
9868 case 2048:
9869 break;
9870 }
9871
9872 cntl |= CURSOR_ENABLE |
9873 CURSOR_GAMMA_ENABLE |
9874 CURSOR_FORMAT_ARGB |
9875 CURSOR_STRIDE(stride);
9876
9877 size = (height << 12) | width;
9878 }
9879
9880 if (intel_crtc->cursor_cntl != 0 &&
9881 (intel_crtc->cursor_base != base ||
9882 intel_crtc->cursor_size != size ||
9883 intel_crtc->cursor_cntl != cntl)) {
9884 /* On these chipsets we can only modify the base/size/stride
9885 * whilst the cursor is disabled.
9886 */
9887 I915_WRITE(_CURACNTR, 0);
9888 POSTING_READ(_CURACNTR);
9889 intel_crtc->cursor_cntl = 0;
9890 }
9891
9892 if (intel_crtc->cursor_base != base) {
9893 I915_WRITE(_CURABASE, base);
9894 intel_crtc->cursor_base = base;
9895 }
9896
9897 if (intel_crtc->cursor_size != size) {
9898 I915_WRITE(CURSIZE, size);
9899 intel_crtc->cursor_size = size;
9900 }
9901
9902 if (intel_crtc->cursor_cntl != cntl) {
9903 I915_WRITE(_CURACNTR, cntl);
9904 POSTING_READ(_CURACNTR);
9905 intel_crtc->cursor_cntl = cntl;
9906 }
9907 }
9908
9909 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9910 {
9911 struct drm_device *dev = crtc->dev;
9912 struct drm_i915_private *dev_priv = dev->dev_private;
9913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9914 int pipe = intel_crtc->pipe;
9915 uint32_t cntl;
9916
9917 cntl = 0;
9918 if (base) {
9919 cntl = MCURSOR_GAMMA_ENABLE;
9920 switch (intel_crtc->base.cursor->state->crtc_w) {
9921 case 64:
9922 cntl |= CURSOR_MODE_64_ARGB_AX;
9923 break;
9924 case 128:
9925 cntl |= CURSOR_MODE_128_ARGB_AX;
9926 break;
9927 case 256:
9928 cntl |= CURSOR_MODE_256_ARGB_AX;
9929 break;
9930 default:
9931 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9932 return;
9933 }
9934 cntl |= pipe << 28; /* Connect to correct pipe */
9935
9936 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9937 cntl |= CURSOR_PIPE_CSC_ENABLE;
9938 }
9939
9940 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9941 cntl |= CURSOR_ROTATE_180;
9942
9943 if (intel_crtc->cursor_cntl != cntl) {
9944 I915_WRITE(CURCNTR(pipe), cntl);
9945 POSTING_READ(CURCNTR(pipe));
9946 intel_crtc->cursor_cntl = cntl;
9947 }
9948
9949 /* and commit changes on next vblank */
9950 I915_WRITE(CURBASE(pipe), base);
9951 POSTING_READ(CURBASE(pipe));
9952
9953 intel_crtc->cursor_base = base;
9954 }
9955
9956 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9957 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9958 bool on)
9959 {
9960 struct drm_device *dev = crtc->dev;
9961 struct drm_i915_private *dev_priv = dev->dev_private;
9962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9963 int pipe = intel_crtc->pipe;
9964 struct drm_plane_state *cursor_state = crtc->cursor->state;
9965 int x = cursor_state->crtc_x;
9966 int y = cursor_state->crtc_y;
9967 u32 base = 0, pos = 0;
9968
9969 if (on)
9970 base = intel_crtc->cursor_addr;
9971
9972 if (x >= intel_crtc->config->pipe_src_w)
9973 base = 0;
9974
9975 if (y >= intel_crtc->config->pipe_src_h)
9976 base = 0;
9977
9978 if (x < 0) {
9979 if (x + cursor_state->crtc_w <= 0)
9980 base = 0;
9981
9982 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9983 x = -x;
9984 }
9985 pos |= x << CURSOR_X_SHIFT;
9986
9987 if (y < 0) {
9988 if (y + cursor_state->crtc_h <= 0)
9989 base = 0;
9990
9991 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9992 y = -y;
9993 }
9994 pos |= y << CURSOR_Y_SHIFT;
9995
9996 if (base == 0 && intel_crtc->cursor_base == 0)
9997 return;
9998
9999 I915_WRITE(CURPOS(pipe), pos);
10000
10001 /* ILK+ do this automagically */
10002 if (HAS_GMCH_DISPLAY(dev) &&
10003 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10004 base += (cursor_state->crtc_h *
10005 cursor_state->crtc_w - 1) * 4;
10006 }
10007
10008 if (IS_845G(dev) || IS_I865G(dev))
10009 i845_update_cursor(crtc, base);
10010 else
10011 i9xx_update_cursor(crtc, base);
10012 }
10013
10014 static bool cursor_size_ok(struct drm_device *dev,
10015 uint32_t width, uint32_t height)
10016 {
10017 if (width == 0 || height == 0)
10018 return false;
10019
10020 /*
10021 * 845g/865g are special in that they are only limited by
10022 * the width of their cursors, the height is arbitrary up to
10023 * the precision of the register. Everything else requires
10024 * square cursors, limited to a few power-of-two sizes.
10025 */
10026 if (IS_845G(dev) || IS_I865G(dev)) {
10027 if ((width & 63) != 0)
10028 return false;
10029
10030 if (width > (IS_845G(dev) ? 64 : 512))
10031 return false;
10032
10033 if (height > 1023)
10034 return false;
10035 } else {
10036 switch (width | height) {
10037 case 256:
10038 case 128:
10039 if (IS_GEN2(dev))
10040 return false;
10041 case 64:
10042 break;
10043 default:
10044 return false;
10045 }
10046 }
10047
10048 return true;
10049 }
10050
10051 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10052 u16 *blue, uint32_t start, uint32_t size)
10053 {
10054 int end = (start + size > 256) ? 256 : start + size, i;
10055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10056
10057 for (i = start; i < end; i++) {
10058 intel_crtc->lut_r[i] = red[i] >> 8;
10059 intel_crtc->lut_g[i] = green[i] >> 8;
10060 intel_crtc->lut_b[i] = blue[i] >> 8;
10061 }
10062
10063 intel_crtc_load_lut(crtc);
10064 }
10065
10066 /* VESA 640x480x72Hz mode to set on the pipe */
10067 static struct drm_display_mode load_detect_mode = {
10068 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10069 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10070 };
10071
10072 struct drm_framebuffer *
10073 __intel_framebuffer_create(struct drm_device *dev,
10074 struct drm_mode_fb_cmd2 *mode_cmd,
10075 struct drm_i915_gem_object *obj)
10076 {
10077 struct intel_framebuffer *intel_fb;
10078 int ret;
10079
10080 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10081 if (!intel_fb) {
10082 drm_gem_object_unreference(&obj->base);
10083 return ERR_PTR(-ENOMEM);
10084 }
10085
10086 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10087 if (ret)
10088 goto err;
10089
10090 return &intel_fb->base;
10091 err:
10092 drm_gem_object_unreference(&obj->base);
10093 kfree(intel_fb);
10094
10095 return ERR_PTR(ret);
10096 }
10097
10098 static struct drm_framebuffer *
10099 intel_framebuffer_create(struct drm_device *dev,
10100 struct drm_mode_fb_cmd2 *mode_cmd,
10101 struct drm_i915_gem_object *obj)
10102 {
10103 struct drm_framebuffer *fb;
10104 int ret;
10105
10106 ret = i915_mutex_lock_interruptible(dev);
10107 if (ret)
10108 return ERR_PTR(ret);
10109 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10110 mutex_unlock(&dev->struct_mutex);
10111
10112 return fb;
10113 }
10114
10115 static u32
10116 intel_framebuffer_pitch_for_width(int width, int bpp)
10117 {
10118 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10119 return ALIGN(pitch, 64);
10120 }
10121
10122 static u32
10123 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10124 {
10125 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10126 return PAGE_ALIGN(pitch * mode->vdisplay);
10127 }
10128
10129 static struct drm_framebuffer *
10130 intel_framebuffer_create_for_mode(struct drm_device *dev,
10131 struct drm_display_mode *mode,
10132 int depth, int bpp)
10133 {
10134 struct drm_i915_gem_object *obj;
10135 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10136
10137 obj = i915_gem_alloc_object(dev,
10138 intel_framebuffer_size_for_mode(mode, bpp));
10139 if (obj == NULL)
10140 return ERR_PTR(-ENOMEM);
10141
10142 mode_cmd.width = mode->hdisplay;
10143 mode_cmd.height = mode->vdisplay;
10144 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10145 bpp);
10146 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10147
10148 return intel_framebuffer_create(dev, &mode_cmd, obj);
10149 }
10150
10151 static struct drm_framebuffer *
10152 mode_fits_in_fbdev(struct drm_device *dev,
10153 struct drm_display_mode *mode)
10154 {
10155 #ifdef CONFIG_DRM_FBDEV_EMULATION
10156 struct drm_i915_private *dev_priv = dev->dev_private;
10157 struct drm_i915_gem_object *obj;
10158 struct drm_framebuffer *fb;
10159
10160 if (!dev_priv->fbdev)
10161 return NULL;
10162
10163 if (!dev_priv->fbdev->fb)
10164 return NULL;
10165
10166 obj = dev_priv->fbdev->fb->obj;
10167 BUG_ON(!obj);
10168
10169 fb = &dev_priv->fbdev->fb->base;
10170 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10171 fb->bits_per_pixel))
10172 return NULL;
10173
10174 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10175 return NULL;
10176
10177 return fb;
10178 #else
10179 return NULL;
10180 #endif
10181 }
10182
10183 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10184 struct drm_crtc *crtc,
10185 struct drm_display_mode *mode,
10186 struct drm_framebuffer *fb,
10187 int x, int y)
10188 {
10189 struct drm_plane_state *plane_state;
10190 int hdisplay, vdisplay;
10191 int ret;
10192
10193 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10194 if (IS_ERR(plane_state))
10195 return PTR_ERR(plane_state);
10196
10197 if (mode)
10198 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10199 else
10200 hdisplay = vdisplay = 0;
10201
10202 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10203 if (ret)
10204 return ret;
10205 drm_atomic_set_fb_for_plane(plane_state, fb);
10206 plane_state->crtc_x = 0;
10207 plane_state->crtc_y = 0;
10208 plane_state->crtc_w = hdisplay;
10209 plane_state->crtc_h = vdisplay;
10210 plane_state->src_x = x << 16;
10211 plane_state->src_y = y << 16;
10212 plane_state->src_w = hdisplay << 16;
10213 plane_state->src_h = vdisplay << 16;
10214
10215 return 0;
10216 }
10217
10218 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10219 struct drm_display_mode *mode,
10220 struct intel_load_detect_pipe *old,
10221 struct drm_modeset_acquire_ctx *ctx)
10222 {
10223 struct intel_crtc *intel_crtc;
10224 struct intel_encoder *intel_encoder =
10225 intel_attached_encoder(connector);
10226 struct drm_crtc *possible_crtc;
10227 struct drm_encoder *encoder = &intel_encoder->base;
10228 struct drm_crtc *crtc = NULL;
10229 struct drm_device *dev = encoder->dev;
10230 struct drm_framebuffer *fb;
10231 struct drm_mode_config *config = &dev->mode_config;
10232 struct drm_atomic_state *state = NULL;
10233 struct drm_connector_state *connector_state;
10234 struct intel_crtc_state *crtc_state;
10235 int ret, i = -1;
10236
10237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10238 connector->base.id, connector->name,
10239 encoder->base.id, encoder->name);
10240
10241 retry:
10242 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10243 if (ret)
10244 goto fail;
10245
10246 /*
10247 * Algorithm gets a little messy:
10248 *
10249 * - if the connector already has an assigned crtc, use it (but make
10250 * sure it's on first)
10251 *
10252 * - try to find the first unused crtc that can drive this connector,
10253 * and use that if we find one
10254 */
10255
10256 /* See if we already have a CRTC for this connector */
10257 if (encoder->crtc) {
10258 crtc = encoder->crtc;
10259
10260 ret = drm_modeset_lock(&crtc->mutex, ctx);
10261 if (ret)
10262 goto fail;
10263 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10264 if (ret)
10265 goto fail;
10266
10267 old->dpms_mode = connector->dpms;
10268 old->load_detect_temp = false;
10269
10270 /* Make sure the crtc and connector are running */
10271 if (connector->dpms != DRM_MODE_DPMS_ON)
10272 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10273
10274 return true;
10275 }
10276
10277 /* Find an unused one (if possible) */
10278 for_each_crtc(dev, possible_crtc) {
10279 i++;
10280 if (!(encoder->possible_crtcs & (1 << i)))
10281 continue;
10282 if (possible_crtc->state->enable)
10283 continue;
10284
10285 crtc = possible_crtc;
10286 break;
10287 }
10288
10289 /*
10290 * If we didn't find an unused CRTC, don't use any.
10291 */
10292 if (!crtc) {
10293 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10294 goto fail;
10295 }
10296
10297 ret = drm_modeset_lock(&crtc->mutex, ctx);
10298 if (ret)
10299 goto fail;
10300 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10301 if (ret)
10302 goto fail;
10303
10304 intel_crtc = to_intel_crtc(crtc);
10305 old->dpms_mode = connector->dpms;
10306 old->load_detect_temp = true;
10307 old->release_fb = NULL;
10308
10309 state = drm_atomic_state_alloc(dev);
10310 if (!state)
10311 return false;
10312
10313 state->acquire_ctx = ctx;
10314
10315 connector_state = drm_atomic_get_connector_state(state, connector);
10316 if (IS_ERR(connector_state)) {
10317 ret = PTR_ERR(connector_state);
10318 goto fail;
10319 }
10320
10321 connector_state->crtc = crtc;
10322 connector_state->best_encoder = &intel_encoder->base;
10323
10324 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10325 if (IS_ERR(crtc_state)) {
10326 ret = PTR_ERR(crtc_state);
10327 goto fail;
10328 }
10329
10330 crtc_state->base.active = crtc_state->base.enable = true;
10331
10332 if (!mode)
10333 mode = &load_detect_mode;
10334
10335 /* We need a framebuffer large enough to accommodate all accesses
10336 * that the plane may generate whilst we perform load detection.
10337 * We can not rely on the fbcon either being present (we get called
10338 * during its initialisation to detect all boot displays, or it may
10339 * not even exist) or that it is large enough to satisfy the
10340 * requested mode.
10341 */
10342 fb = mode_fits_in_fbdev(dev, mode);
10343 if (fb == NULL) {
10344 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10345 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10346 old->release_fb = fb;
10347 } else
10348 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10349 if (IS_ERR(fb)) {
10350 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10351 goto fail;
10352 }
10353
10354 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10355 if (ret)
10356 goto fail;
10357
10358 drm_mode_copy(&crtc_state->base.mode, mode);
10359
10360 if (drm_atomic_commit(state)) {
10361 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10362 if (old->release_fb)
10363 old->release_fb->funcs->destroy(old->release_fb);
10364 goto fail;
10365 }
10366 crtc->primary->crtc = crtc;
10367
10368 /* let the connector get through one full cycle before testing */
10369 intel_wait_for_vblank(dev, intel_crtc->pipe);
10370 return true;
10371
10372 fail:
10373 drm_atomic_state_free(state);
10374 state = NULL;
10375
10376 if (ret == -EDEADLK) {
10377 drm_modeset_backoff(ctx);
10378 goto retry;
10379 }
10380
10381 return false;
10382 }
10383
10384 void intel_release_load_detect_pipe(struct drm_connector *connector,
10385 struct intel_load_detect_pipe *old,
10386 struct drm_modeset_acquire_ctx *ctx)
10387 {
10388 struct drm_device *dev = connector->dev;
10389 struct intel_encoder *intel_encoder =
10390 intel_attached_encoder(connector);
10391 struct drm_encoder *encoder = &intel_encoder->base;
10392 struct drm_crtc *crtc = encoder->crtc;
10393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10394 struct drm_atomic_state *state;
10395 struct drm_connector_state *connector_state;
10396 struct intel_crtc_state *crtc_state;
10397 int ret;
10398
10399 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10400 connector->base.id, connector->name,
10401 encoder->base.id, encoder->name);
10402
10403 if (old->load_detect_temp) {
10404 state = drm_atomic_state_alloc(dev);
10405 if (!state)
10406 goto fail;
10407
10408 state->acquire_ctx = ctx;
10409
10410 connector_state = drm_atomic_get_connector_state(state, connector);
10411 if (IS_ERR(connector_state))
10412 goto fail;
10413
10414 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10415 if (IS_ERR(crtc_state))
10416 goto fail;
10417
10418 connector_state->best_encoder = NULL;
10419 connector_state->crtc = NULL;
10420
10421 crtc_state->base.enable = crtc_state->base.active = false;
10422
10423 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10424 0, 0);
10425 if (ret)
10426 goto fail;
10427
10428 ret = drm_atomic_commit(state);
10429 if (ret)
10430 goto fail;
10431
10432 if (old->release_fb) {
10433 drm_framebuffer_unregister_private(old->release_fb);
10434 drm_framebuffer_unreference(old->release_fb);
10435 }
10436
10437 return;
10438 }
10439
10440 /* Switch crtc and encoder back off if necessary */
10441 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10442 connector->funcs->dpms(connector, old->dpms_mode);
10443
10444 return;
10445 fail:
10446 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10447 drm_atomic_state_free(state);
10448 }
10449
10450 static int i9xx_pll_refclk(struct drm_device *dev,
10451 const struct intel_crtc_state *pipe_config)
10452 {
10453 struct drm_i915_private *dev_priv = dev->dev_private;
10454 u32 dpll = pipe_config->dpll_hw_state.dpll;
10455
10456 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10457 return dev_priv->vbt.lvds_ssc_freq;
10458 else if (HAS_PCH_SPLIT(dev))
10459 return 120000;
10460 else if (!IS_GEN2(dev))
10461 return 96000;
10462 else
10463 return 48000;
10464 }
10465
10466 /* Returns the clock of the currently programmed mode of the given pipe. */
10467 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10468 struct intel_crtc_state *pipe_config)
10469 {
10470 struct drm_device *dev = crtc->base.dev;
10471 struct drm_i915_private *dev_priv = dev->dev_private;
10472 int pipe = pipe_config->cpu_transcoder;
10473 u32 dpll = pipe_config->dpll_hw_state.dpll;
10474 u32 fp;
10475 intel_clock_t clock;
10476 int port_clock;
10477 int refclk = i9xx_pll_refclk(dev, pipe_config);
10478
10479 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10480 fp = pipe_config->dpll_hw_state.fp0;
10481 else
10482 fp = pipe_config->dpll_hw_state.fp1;
10483
10484 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10485 if (IS_PINEVIEW(dev)) {
10486 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10487 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10488 } else {
10489 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10490 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10491 }
10492
10493 if (!IS_GEN2(dev)) {
10494 if (IS_PINEVIEW(dev))
10495 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10496 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10497 else
10498 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10499 DPLL_FPA01_P1_POST_DIV_SHIFT);
10500
10501 switch (dpll & DPLL_MODE_MASK) {
10502 case DPLLB_MODE_DAC_SERIAL:
10503 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10504 5 : 10;
10505 break;
10506 case DPLLB_MODE_LVDS:
10507 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10508 7 : 14;
10509 break;
10510 default:
10511 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10512 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10513 return;
10514 }
10515
10516 if (IS_PINEVIEW(dev))
10517 port_clock = pnv_calc_dpll_params(refclk, &clock);
10518 else
10519 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10520 } else {
10521 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10522 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10523
10524 if (is_lvds) {
10525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10526 DPLL_FPA01_P1_POST_DIV_SHIFT);
10527
10528 if (lvds & LVDS_CLKB_POWER_UP)
10529 clock.p2 = 7;
10530 else
10531 clock.p2 = 14;
10532 } else {
10533 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10534 clock.p1 = 2;
10535 else {
10536 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10537 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10538 }
10539 if (dpll & PLL_P2_DIVIDE_BY_4)
10540 clock.p2 = 4;
10541 else
10542 clock.p2 = 2;
10543 }
10544
10545 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10546 }
10547
10548 /*
10549 * This value includes pixel_multiplier. We will use
10550 * port_clock to compute adjusted_mode.crtc_clock in the
10551 * encoder's get_config() function.
10552 */
10553 pipe_config->port_clock = port_clock;
10554 }
10555
10556 int intel_dotclock_calculate(int link_freq,
10557 const struct intel_link_m_n *m_n)
10558 {
10559 /*
10560 * The calculation for the data clock is:
10561 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10562 * But we want to avoid losing precison if possible, so:
10563 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10564 *
10565 * and the link clock is simpler:
10566 * link_clock = (m * link_clock) / n
10567 */
10568
10569 if (!m_n->link_n)
10570 return 0;
10571
10572 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10573 }
10574
10575 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10576 struct intel_crtc_state *pipe_config)
10577 {
10578 struct drm_device *dev = crtc->base.dev;
10579
10580 /* read out port_clock from the DPLL */
10581 i9xx_crtc_clock_get(crtc, pipe_config);
10582
10583 /*
10584 * This value does not include pixel_multiplier.
10585 * We will check that port_clock and adjusted_mode.crtc_clock
10586 * agree once we know their relationship in the encoder's
10587 * get_config() function.
10588 */
10589 pipe_config->base.adjusted_mode.crtc_clock =
10590 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10591 &pipe_config->fdi_m_n);
10592 }
10593
10594 /** Returns the currently programmed mode of the given pipe. */
10595 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10596 struct drm_crtc *crtc)
10597 {
10598 struct drm_i915_private *dev_priv = dev->dev_private;
10599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10600 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10601 struct drm_display_mode *mode;
10602 struct intel_crtc_state pipe_config;
10603 int htot = I915_READ(HTOTAL(cpu_transcoder));
10604 int hsync = I915_READ(HSYNC(cpu_transcoder));
10605 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10606 int vsync = I915_READ(VSYNC(cpu_transcoder));
10607 enum pipe pipe = intel_crtc->pipe;
10608
10609 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10610 if (!mode)
10611 return NULL;
10612
10613 /*
10614 * Construct a pipe_config sufficient for getting the clock info
10615 * back out of crtc_clock_get.
10616 *
10617 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10618 * to use a real value here instead.
10619 */
10620 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10621 pipe_config.pixel_multiplier = 1;
10622 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10623 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10624 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10625 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10626
10627 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10628 mode->hdisplay = (htot & 0xffff) + 1;
10629 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10630 mode->hsync_start = (hsync & 0xffff) + 1;
10631 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10632 mode->vdisplay = (vtot & 0xffff) + 1;
10633 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10634 mode->vsync_start = (vsync & 0xffff) + 1;
10635 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10636
10637 drm_mode_set_name(mode);
10638
10639 return mode;
10640 }
10641
10642 void intel_mark_busy(struct drm_device *dev)
10643 {
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645
10646 if (dev_priv->mm.busy)
10647 return;
10648
10649 intel_runtime_pm_get(dev_priv);
10650 i915_update_gfx_val(dev_priv);
10651 if (INTEL_INFO(dev)->gen >= 6)
10652 gen6_rps_busy(dev_priv);
10653 dev_priv->mm.busy = true;
10654 }
10655
10656 void intel_mark_idle(struct drm_device *dev)
10657 {
10658 struct drm_i915_private *dev_priv = dev->dev_private;
10659
10660 if (!dev_priv->mm.busy)
10661 return;
10662
10663 dev_priv->mm.busy = false;
10664
10665 if (INTEL_INFO(dev)->gen >= 6)
10666 gen6_rps_idle(dev->dev_private);
10667
10668 intel_runtime_pm_put(dev_priv);
10669 }
10670
10671 static void intel_crtc_destroy(struct drm_crtc *crtc)
10672 {
10673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10674 struct drm_device *dev = crtc->dev;
10675 struct intel_unpin_work *work;
10676
10677 spin_lock_irq(&dev->event_lock);
10678 work = intel_crtc->unpin_work;
10679 intel_crtc->unpin_work = NULL;
10680 spin_unlock_irq(&dev->event_lock);
10681
10682 if (work) {
10683 cancel_work_sync(&work->work);
10684 kfree(work);
10685 }
10686
10687 drm_crtc_cleanup(crtc);
10688
10689 kfree(intel_crtc);
10690 }
10691
10692 static void intel_unpin_work_fn(struct work_struct *__work)
10693 {
10694 struct intel_unpin_work *work =
10695 container_of(__work, struct intel_unpin_work, work);
10696 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10697 struct drm_device *dev = crtc->base.dev;
10698 struct drm_plane *primary = crtc->base.primary;
10699
10700 mutex_lock(&dev->struct_mutex);
10701 intel_unpin_fb_obj(work->old_fb, primary->state);
10702 drm_gem_object_unreference(&work->pending_flip_obj->base);
10703
10704 if (work->flip_queued_req)
10705 i915_gem_request_assign(&work->flip_queued_req, NULL);
10706 mutex_unlock(&dev->struct_mutex);
10707
10708 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10709 drm_framebuffer_unreference(work->old_fb);
10710
10711 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10712 atomic_dec(&crtc->unpin_work_count);
10713
10714 kfree(work);
10715 }
10716
10717 static void do_intel_finish_page_flip(struct drm_device *dev,
10718 struct drm_crtc *crtc)
10719 {
10720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10721 struct intel_unpin_work *work;
10722 unsigned long flags;
10723
10724 /* Ignore early vblank irqs */
10725 if (intel_crtc == NULL)
10726 return;
10727
10728 /*
10729 * This is called both by irq handlers and the reset code (to complete
10730 * lost pageflips) so needs the full irqsave spinlocks.
10731 */
10732 spin_lock_irqsave(&dev->event_lock, flags);
10733 work = intel_crtc->unpin_work;
10734
10735 /* Ensure we don't miss a work->pending update ... */
10736 smp_rmb();
10737
10738 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10739 spin_unlock_irqrestore(&dev->event_lock, flags);
10740 return;
10741 }
10742
10743 page_flip_completed(intel_crtc);
10744
10745 spin_unlock_irqrestore(&dev->event_lock, flags);
10746 }
10747
10748 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10749 {
10750 struct drm_i915_private *dev_priv = dev->dev_private;
10751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10752
10753 do_intel_finish_page_flip(dev, crtc);
10754 }
10755
10756 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10757 {
10758 struct drm_i915_private *dev_priv = dev->dev_private;
10759 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10760
10761 do_intel_finish_page_flip(dev, crtc);
10762 }
10763
10764 /* Is 'a' after or equal to 'b'? */
10765 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10766 {
10767 return !((a - b) & 0x80000000);
10768 }
10769
10770 static bool page_flip_finished(struct intel_crtc *crtc)
10771 {
10772 struct drm_device *dev = crtc->base.dev;
10773 struct drm_i915_private *dev_priv = dev->dev_private;
10774
10775 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10776 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10777 return true;
10778
10779 /*
10780 * The relevant registers doen't exist on pre-ctg.
10781 * As the flip done interrupt doesn't trigger for mmio
10782 * flips on gmch platforms, a flip count check isn't
10783 * really needed there. But since ctg has the registers,
10784 * include it in the check anyway.
10785 */
10786 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10787 return true;
10788
10789 /*
10790 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10791 * used the same base address. In that case the mmio flip might
10792 * have completed, but the CS hasn't even executed the flip yet.
10793 *
10794 * A flip count check isn't enough as the CS might have updated
10795 * the base address just after start of vblank, but before we
10796 * managed to process the interrupt. This means we'd complete the
10797 * CS flip too soon.
10798 *
10799 * Combining both checks should get us a good enough result. It may
10800 * still happen that the CS flip has been executed, but has not
10801 * yet actually completed. But in case the base address is the same
10802 * anyway, we don't really care.
10803 */
10804 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10805 crtc->unpin_work->gtt_offset &&
10806 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10807 crtc->unpin_work->flip_count);
10808 }
10809
10810 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10811 {
10812 struct drm_i915_private *dev_priv = dev->dev_private;
10813 struct intel_crtc *intel_crtc =
10814 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10815 unsigned long flags;
10816
10817
10818 /*
10819 * This is called both by irq handlers and the reset code (to complete
10820 * lost pageflips) so needs the full irqsave spinlocks.
10821 *
10822 * NB: An MMIO update of the plane base pointer will also
10823 * generate a page-flip completion irq, i.e. every modeset
10824 * is also accompanied by a spurious intel_prepare_page_flip().
10825 */
10826 spin_lock_irqsave(&dev->event_lock, flags);
10827 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10828 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10829 spin_unlock_irqrestore(&dev->event_lock, flags);
10830 }
10831
10832 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10833 {
10834 /* Ensure that the work item is consistent when activating it ... */
10835 smp_wmb();
10836 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10837 /* and that it is marked active as soon as the irq could fire. */
10838 smp_wmb();
10839 }
10840
10841 static int intel_gen2_queue_flip(struct drm_device *dev,
10842 struct drm_crtc *crtc,
10843 struct drm_framebuffer *fb,
10844 struct drm_i915_gem_object *obj,
10845 struct drm_i915_gem_request *req,
10846 uint32_t flags)
10847 {
10848 struct intel_engine_cs *ring = req->ring;
10849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10850 u32 flip_mask;
10851 int ret;
10852
10853 ret = intel_ring_begin(req, 6);
10854 if (ret)
10855 return ret;
10856
10857 /* Can't queue multiple flips, so wait for the previous
10858 * one to finish before executing the next.
10859 */
10860 if (intel_crtc->plane)
10861 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10862 else
10863 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10864 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10865 intel_ring_emit(ring, MI_NOOP);
10866 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10867 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10868 intel_ring_emit(ring, fb->pitches[0]);
10869 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10870 intel_ring_emit(ring, 0); /* aux display base address, unused */
10871
10872 intel_mark_page_flip_active(intel_crtc);
10873 return 0;
10874 }
10875
10876 static int intel_gen3_queue_flip(struct drm_device *dev,
10877 struct drm_crtc *crtc,
10878 struct drm_framebuffer *fb,
10879 struct drm_i915_gem_object *obj,
10880 struct drm_i915_gem_request *req,
10881 uint32_t flags)
10882 {
10883 struct intel_engine_cs *ring = req->ring;
10884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10885 u32 flip_mask;
10886 int ret;
10887
10888 ret = intel_ring_begin(req, 6);
10889 if (ret)
10890 return ret;
10891
10892 if (intel_crtc->plane)
10893 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10894 else
10895 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10896 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10897 intel_ring_emit(ring, MI_NOOP);
10898 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10899 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10900 intel_ring_emit(ring, fb->pitches[0]);
10901 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10902 intel_ring_emit(ring, MI_NOOP);
10903
10904 intel_mark_page_flip_active(intel_crtc);
10905 return 0;
10906 }
10907
10908 static int intel_gen4_queue_flip(struct drm_device *dev,
10909 struct drm_crtc *crtc,
10910 struct drm_framebuffer *fb,
10911 struct drm_i915_gem_object *obj,
10912 struct drm_i915_gem_request *req,
10913 uint32_t flags)
10914 {
10915 struct intel_engine_cs *ring = req->ring;
10916 struct drm_i915_private *dev_priv = dev->dev_private;
10917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10918 uint32_t pf, pipesrc;
10919 int ret;
10920
10921 ret = intel_ring_begin(req, 4);
10922 if (ret)
10923 return ret;
10924
10925 /* i965+ uses the linear or tiled offsets from the
10926 * Display Registers (which do not change across a page-flip)
10927 * so we need only reprogram the base address.
10928 */
10929 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10930 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10931 intel_ring_emit(ring, fb->pitches[0]);
10932 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10933 obj->tiling_mode);
10934
10935 /* XXX Enabling the panel-fitter across page-flip is so far
10936 * untested on non-native modes, so ignore it for now.
10937 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10938 */
10939 pf = 0;
10940 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10941 intel_ring_emit(ring, pf | pipesrc);
10942
10943 intel_mark_page_flip_active(intel_crtc);
10944 return 0;
10945 }
10946
10947 static int intel_gen6_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
10950 struct drm_i915_gem_object *obj,
10951 struct drm_i915_gem_request *req,
10952 uint32_t flags)
10953 {
10954 struct intel_engine_cs *ring = req->ring;
10955 struct drm_i915_private *dev_priv = dev->dev_private;
10956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10957 uint32_t pf, pipesrc;
10958 int ret;
10959
10960 ret = intel_ring_begin(req, 4);
10961 if (ret)
10962 return ret;
10963
10964 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10965 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10966 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10967 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10968
10969 /* Contrary to the suggestions in the documentation,
10970 * "Enable Panel Fitter" does not seem to be required when page
10971 * flipping with a non-native mode, and worse causes a normal
10972 * modeset to fail.
10973 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10974 */
10975 pf = 0;
10976 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10977 intel_ring_emit(ring, pf | pipesrc);
10978
10979 intel_mark_page_flip_active(intel_crtc);
10980 return 0;
10981 }
10982
10983 static int intel_gen7_queue_flip(struct drm_device *dev,
10984 struct drm_crtc *crtc,
10985 struct drm_framebuffer *fb,
10986 struct drm_i915_gem_object *obj,
10987 struct drm_i915_gem_request *req,
10988 uint32_t flags)
10989 {
10990 struct intel_engine_cs *ring = req->ring;
10991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10992 uint32_t plane_bit = 0;
10993 int len, ret;
10994
10995 switch (intel_crtc->plane) {
10996 case PLANE_A:
10997 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10998 break;
10999 case PLANE_B:
11000 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11001 break;
11002 case PLANE_C:
11003 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11004 break;
11005 default:
11006 WARN_ONCE(1, "unknown plane in flip command\n");
11007 return -ENODEV;
11008 }
11009
11010 len = 4;
11011 if (ring->id == RCS) {
11012 len += 6;
11013 /*
11014 * On Gen 8, SRM is now taking an extra dword to accommodate
11015 * 48bits addresses, and we need a NOOP for the batch size to
11016 * stay even.
11017 */
11018 if (IS_GEN8(dev))
11019 len += 2;
11020 }
11021
11022 /*
11023 * BSpec MI_DISPLAY_FLIP for IVB:
11024 * "The full packet must be contained within the same cache line."
11025 *
11026 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11027 * cacheline, if we ever start emitting more commands before
11028 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11029 * then do the cacheline alignment, and finally emit the
11030 * MI_DISPLAY_FLIP.
11031 */
11032 ret = intel_ring_cacheline_align(req);
11033 if (ret)
11034 return ret;
11035
11036 ret = intel_ring_begin(req, len);
11037 if (ret)
11038 return ret;
11039
11040 /* Unmask the flip-done completion message. Note that the bspec says that
11041 * we should do this for both the BCS and RCS, and that we must not unmask
11042 * more than one flip event at any time (or ensure that one flip message
11043 * can be sent by waiting for flip-done prior to queueing new flips).
11044 * Experimentation says that BCS works despite DERRMR masking all
11045 * flip-done completion events and that unmasking all planes at once
11046 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11047 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11048 */
11049 if (ring->id == RCS) {
11050 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11051 intel_ring_emit(ring, DERRMR);
11052 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11053 DERRMR_PIPEB_PRI_FLIP_DONE |
11054 DERRMR_PIPEC_PRI_FLIP_DONE));
11055 if (IS_GEN8(dev))
11056 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11057 MI_SRM_LRM_GLOBAL_GTT);
11058 else
11059 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11060 MI_SRM_LRM_GLOBAL_GTT);
11061 intel_ring_emit(ring, DERRMR);
11062 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11063 if (IS_GEN8(dev)) {
11064 intel_ring_emit(ring, 0);
11065 intel_ring_emit(ring, MI_NOOP);
11066 }
11067 }
11068
11069 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11070 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11071 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11072 intel_ring_emit(ring, (MI_NOOP));
11073
11074 intel_mark_page_flip_active(intel_crtc);
11075 return 0;
11076 }
11077
11078 static bool use_mmio_flip(struct intel_engine_cs *ring,
11079 struct drm_i915_gem_object *obj)
11080 {
11081 /*
11082 * This is not being used for older platforms, because
11083 * non-availability of flip done interrupt forces us to use
11084 * CS flips. Older platforms derive flip done using some clever
11085 * tricks involving the flip_pending status bits and vblank irqs.
11086 * So using MMIO flips there would disrupt this mechanism.
11087 */
11088
11089 if (ring == NULL)
11090 return true;
11091
11092 if (INTEL_INFO(ring->dev)->gen < 5)
11093 return false;
11094
11095 if (i915.use_mmio_flip < 0)
11096 return false;
11097 else if (i915.use_mmio_flip > 0)
11098 return true;
11099 else if (i915.enable_execlists)
11100 return true;
11101 else
11102 return ring != i915_gem_request_get_ring(obj->last_write_req);
11103 }
11104
11105 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11106 {
11107 struct drm_device *dev = intel_crtc->base.dev;
11108 struct drm_i915_private *dev_priv = dev->dev_private;
11109 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11110 const enum pipe pipe = intel_crtc->pipe;
11111 u32 ctl, stride;
11112
11113 ctl = I915_READ(PLANE_CTL(pipe, 0));
11114 ctl &= ~PLANE_CTL_TILED_MASK;
11115 switch (fb->modifier[0]) {
11116 case DRM_FORMAT_MOD_NONE:
11117 break;
11118 case I915_FORMAT_MOD_X_TILED:
11119 ctl |= PLANE_CTL_TILED_X;
11120 break;
11121 case I915_FORMAT_MOD_Y_TILED:
11122 ctl |= PLANE_CTL_TILED_Y;
11123 break;
11124 case I915_FORMAT_MOD_Yf_TILED:
11125 ctl |= PLANE_CTL_TILED_YF;
11126 break;
11127 default:
11128 MISSING_CASE(fb->modifier[0]);
11129 }
11130
11131 /*
11132 * The stride is either expressed as a multiple of 64 bytes chunks for
11133 * linear buffers or in number of tiles for tiled buffers.
11134 */
11135 stride = fb->pitches[0] /
11136 intel_fb_stride_alignment(dev, fb->modifier[0],
11137 fb->pixel_format);
11138
11139 /*
11140 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11141 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11142 */
11143 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11144 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11145
11146 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11147 POSTING_READ(PLANE_SURF(pipe, 0));
11148 }
11149
11150 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11151 {
11152 struct drm_device *dev = intel_crtc->base.dev;
11153 struct drm_i915_private *dev_priv = dev->dev_private;
11154 struct intel_framebuffer *intel_fb =
11155 to_intel_framebuffer(intel_crtc->base.primary->fb);
11156 struct drm_i915_gem_object *obj = intel_fb->obj;
11157 u32 dspcntr;
11158 u32 reg;
11159
11160 reg = DSPCNTR(intel_crtc->plane);
11161 dspcntr = I915_READ(reg);
11162
11163 if (obj->tiling_mode != I915_TILING_NONE)
11164 dspcntr |= DISPPLANE_TILED;
11165 else
11166 dspcntr &= ~DISPPLANE_TILED;
11167
11168 I915_WRITE(reg, dspcntr);
11169
11170 I915_WRITE(DSPSURF(intel_crtc->plane),
11171 intel_crtc->unpin_work->gtt_offset);
11172 POSTING_READ(DSPSURF(intel_crtc->plane));
11173
11174 }
11175
11176 /*
11177 * XXX: This is the temporary way to update the plane registers until we get
11178 * around to using the usual plane update functions for MMIO flips
11179 */
11180 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11181 {
11182 struct drm_device *dev = intel_crtc->base.dev;
11183
11184 intel_mark_page_flip_active(intel_crtc);
11185
11186 intel_pipe_update_start(intel_crtc);
11187
11188 if (INTEL_INFO(dev)->gen >= 9)
11189 skl_do_mmio_flip(intel_crtc);
11190 else
11191 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11192 ilk_do_mmio_flip(intel_crtc);
11193
11194 intel_pipe_update_end(intel_crtc);
11195 }
11196
11197 static void intel_mmio_flip_work_func(struct work_struct *work)
11198 {
11199 struct intel_mmio_flip *mmio_flip =
11200 container_of(work, struct intel_mmio_flip, work);
11201
11202 if (mmio_flip->req)
11203 WARN_ON(__i915_wait_request(mmio_flip->req,
11204 mmio_flip->crtc->reset_counter,
11205 false, NULL,
11206 &mmio_flip->i915->rps.mmioflips));
11207
11208 intel_do_mmio_flip(mmio_flip->crtc);
11209
11210 i915_gem_request_unreference__unlocked(mmio_flip->req);
11211 kfree(mmio_flip);
11212 }
11213
11214 static int intel_queue_mmio_flip(struct drm_device *dev,
11215 struct drm_crtc *crtc,
11216 struct drm_framebuffer *fb,
11217 struct drm_i915_gem_object *obj,
11218 struct intel_engine_cs *ring,
11219 uint32_t flags)
11220 {
11221 struct intel_mmio_flip *mmio_flip;
11222
11223 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11224 if (mmio_flip == NULL)
11225 return -ENOMEM;
11226
11227 mmio_flip->i915 = to_i915(dev);
11228 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11229 mmio_flip->crtc = to_intel_crtc(crtc);
11230
11231 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11232 schedule_work(&mmio_flip->work);
11233
11234 return 0;
11235 }
11236
11237 static int intel_default_queue_flip(struct drm_device *dev,
11238 struct drm_crtc *crtc,
11239 struct drm_framebuffer *fb,
11240 struct drm_i915_gem_object *obj,
11241 struct drm_i915_gem_request *req,
11242 uint32_t flags)
11243 {
11244 return -ENODEV;
11245 }
11246
11247 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11248 struct drm_crtc *crtc)
11249 {
11250 struct drm_i915_private *dev_priv = dev->dev_private;
11251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11252 struct intel_unpin_work *work = intel_crtc->unpin_work;
11253 u32 addr;
11254
11255 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11256 return true;
11257
11258 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11259 return false;
11260
11261 if (!work->enable_stall_check)
11262 return false;
11263
11264 if (work->flip_ready_vblank == 0) {
11265 if (work->flip_queued_req &&
11266 !i915_gem_request_completed(work->flip_queued_req, true))
11267 return false;
11268
11269 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11270 }
11271
11272 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11273 return false;
11274
11275 /* Potential stall - if we see that the flip has happened,
11276 * assume a missed interrupt. */
11277 if (INTEL_INFO(dev)->gen >= 4)
11278 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11279 else
11280 addr = I915_READ(DSPADDR(intel_crtc->plane));
11281
11282 /* There is a potential issue here with a false positive after a flip
11283 * to the same address. We could address this by checking for a
11284 * non-incrementing frame counter.
11285 */
11286 return addr == work->gtt_offset;
11287 }
11288
11289 void intel_check_page_flip(struct drm_device *dev, int pipe)
11290 {
11291 struct drm_i915_private *dev_priv = dev->dev_private;
11292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11294 struct intel_unpin_work *work;
11295
11296 WARN_ON(!in_interrupt());
11297
11298 if (crtc == NULL)
11299 return;
11300
11301 spin_lock(&dev->event_lock);
11302 work = intel_crtc->unpin_work;
11303 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11304 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11305 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11306 page_flip_completed(intel_crtc);
11307 work = NULL;
11308 }
11309 if (work != NULL &&
11310 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11311 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11312 spin_unlock(&dev->event_lock);
11313 }
11314
11315 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11316 struct drm_framebuffer *fb,
11317 struct drm_pending_vblank_event *event,
11318 uint32_t page_flip_flags)
11319 {
11320 struct drm_device *dev = crtc->dev;
11321 struct drm_i915_private *dev_priv = dev->dev_private;
11322 struct drm_framebuffer *old_fb = crtc->primary->fb;
11323 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11325 struct drm_plane *primary = crtc->primary;
11326 enum pipe pipe = intel_crtc->pipe;
11327 struct intel_unpin_work *work;
11328 struct intel_engine_cs *ring;
11329 bool mmio_flip;
11330 struct drm_i915_gem_request *request = NULL;
11331 int ret;
11332
11333 /*
11334 * drm_mode_page_flip_ioctl() should already catch this, but double
11335 * check to be safe. In the future we may enable pageflipping from
11336 * a disabled primary plane.
11337 */
11338 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11339 return -EBUSY;
11340
11341 /* Can't change pixel format via MI display flips. */
11342 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11343 return -EINVAL;
11344
11345 /*
11346 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11347 * Note that pitch changes could also affect these register.
11348 */
11349 if (INTEL_INFO(dev)->gen > 3 &&
11350 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11351 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11352 return -EINVAL;
11353
11354 if (i915_terminally_wedged(&dev_priv->gpu_error))
11355 goto out_hang;
11356
11357 work = kzalloc(sizeof(*work), GFP_KERNEL);
11358 if (work == NULL)
11359 return -ENOMEM;
11360
11361 work->event = event;
11362 work->crtc = crtc;
11363 work->old_fb = old_fb;
11364 INIT_WORK(&work->work, intel_unpin_work_fn);
11365
11366 ret = drm_crtc_vblank_get(crtc);
11367 if (ret)
11368 goto free_work;
11369
11370 /* We borrow the event spin lock for protecting unpin_work */
11371 spin_lock_irq(&dev->event_lock);
11372 if (intel_crtc->unpin_work) {
11373 /* Before declaring the flip queue wedged, check if
11374 * the hardware completed the operation behind our backs.
11375 */
11376 if (__intel_pageflip_stall_check(dev, crtc)) {
11377 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11378 page_flip_completed(intel_crtc);
11379 } else {
11380 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11381 spin_unlock_irq(&dev->event_lock);
11382
11383 drm_crtc_vblank_put(crtc);
11384 kfree(work);
11385 return -EBUSY;
11386 }
11387 }
11388 intel_crtc->unpin_work = work;
11389 spin_unlock_irq(&dev->event_lock);
11390
11391 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11392 flush_workqueue(dev_priv->wq);
11393
11394 /* Reference the objects for the scheduled work. */
11395 drm_framebuffer_reference(work->old_fb);
11396 drm_gem_object_reference(&obj->base);
11397
11398 crtc->primary->fb = fb;
11399 update_state_fb(crtc->primary);
11400
11401 work->pending_flip_obj = obj;
11402
11403 ret = i915_mutex_lock_interruptible(dev);
11404 if (ret)
11405 goto cleanup;
11406
11407 atomic_inc(&intel_crtc->unpin_work_count);
11408 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11409
11410 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11411 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11412
11413 if (IS_VALLEYVIEW(dev)) {
11414 ring = &dev_priv->ring[BCS];
11415 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11416 /* vlv: DISPLAY_FLIP fails to change tiling */
11417 ring = NULL;
11418 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11419 ring = &dev_priv->ring[BCS];
11420 } else if (INTEL_INFO(dev)->gen >= 7) {
11421 ring = i915_gem_request_get_ring(obj->last_write_req);
11422 if (ring == NULL || ring->id != RCS)
11423 ring = &dev_priv->ring[BCS];
11424 } else {
11425 ring = &dev_priv->ring[RCS];
11426 }
11427
11428 mmio_flip = use_mmio_flip(ring, obj);
11429
11430 /* When using CS flips, we want to emit semaphores between rings.
11431 * However, when using mmio flips we will create a task to do the
11432 * synchronisation, so all we want here is to pin the framebuffer
11433 * into the display plane and skip any waits.
11434 */
11435 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11436 crtc->primary->state,
11437 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11438 if (ret)
11439 goto cleanup_pending;
11440
11441 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11442 obj, 0);
11443 work->gtt_offset += intel_crtc->dspaddr_offset;
11444
11445 if (mmio_flip) {
11446 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11447 page_flip_flags);
11448 if (ret)
11449 goto cleanup_unpin;
11450
11451 i915_gem_request_assign(&work->flip_queued_req,
11452 obj->last_write_req);
11453 } else {
11454 if (!request) {
11455 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11456 if (ret)
11457 goto cleanup_unpin;
11458 }
11459
11460 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11461 page_flip_flags);
11462 if (ret)
11463 goto cleanup_unpin;
11464
11465 i915_gem_request_assign(&work->flip_queued_req, request);
11466 }
11467
11468 if (request)
11469 i915_add_request_no_flush(request);
11470
11471 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11472 work->enable_stall_check = true;
11473
11474 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11475 to_intel_plane(primary)->frontbuffer_bit);
11476 mutex_unlock(&dev->struct_mutex);
11477
11478 intel_fbc_disable_crtc(intel_crtc);
11479 intel_frontbuffer_flip_prepare(dev,
11480 to_intel_plane(primary)->frontbuffer_bit);
11481
11482 trace_i915_flip_request(intel_crtc->plane, obj);
11483
11484 return 0;
11485
11486 cleanup_unpin:
11487 intel_unpin_fb_obj(fb, crtc->primary->state);
11488 cleanup_pending:
11489 if (request)
11490 i915_gem_request_cancel(request);
11491 atomic_dec(&intel_crtc->unpin_work_count);
11492 mutex_unlock(&dev->struct_mutex);
11493 cleanup:
11494 crtc->primary->fb = old_fb;
11495 update_state_fb(crtc->primary);
11496
11497 drm_gem_object_unreference_unlocked(&obj->base);
11498 drm_framebuffer_unreference(work->old_fb);
11499
11500 spin_lock_irq(&dev->event_lock);
11501 intel_crtc->unpin_work = NULL;
11502 spin_unlock_irq(&dev->event_lock);
11503
11504 drm_crtc_vblank_put(crtc);
11505 free_work:
11506 kfree(work);
11507
11508 if (ret == -EIO) {
11509 struct drm_atomic_state *state;
11510 struct drm_plane_state *plane_state;
11511
11512 out_hang:
11513 state = drm_atomic_state_alloc(dev);
11514 if (!state)
11515 return -ENOMEM;
11516 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11517
11518 retry:
11519 plane_state = drm_atomic_get_plane_state(state, primary);
11520 ret = PTR_ERR_OR_ZERO(plane_state);
11521 if (!ret) {
11522 drm_atomic_set_fb_for_plane(plane_state, fb);
11523
11524 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11525 if (!ret)
11526 ret = drm_atomic_commit(state);
11527 }
11528
11529 if (ret == -EDEADLK) {
11530 drm_modeset_backoff(state->acquire_ctx);
11531 drm_atomic_state_clear(state);
11532 goto retry;
11533 }
11534
11535 if (ret)
11536 drm_atomic_state_free(state);
11537
11538 if (ret == 0 && event) {
11539 spin_lock_irq(&dev->event_lock);
11540 drm_send_vblank_event(dev, pipe, event);
11541 spin_unlock_irq(&dev->event_lock);
11542 }
11543 }
11544 return ret;
11545 }
11546
11547
11548 /**
11549 * intel_wm_need_update - Check whether watermarks need updating
11550 * @plane: drm plane
11551 * @state: new plane state
11552 *
11553 * Check current plane state versus the new one to determine whether
11554 * watermarks need to be recalculated.
11555 *
11556 * Returns true or false.
11557 */
11558 static bool intel_wm_need_update(struct drm_plane *plane,
11559 struct drm_plane_state *state)
11560 {
11561 /* Update watermarks on tiling changes. */
11562 if (!plane->state->fb || !state->fb ||
11563 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11564 plane->state->rotation != state->rotation)
11565 return true;
11566
11567 if (plane->state->crtc_w != state->crtc_w)
11568 return true;
11569
11570 return false;
11571 }
11572
11573 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11574 struct drm_plane_state *plane_state)
11575 {
11576 struct drm_crtc *crtc = crtc_state->crtc;
11577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11578 struct drm_plane *plane = plane_state->plane;
11579 struct drm_device *dev = crtc->dev;
11580 struct drm_i915_private *dev_priv = dev->dev_private;
11581 struct intel_plane_state *old_plane_state =
11582 to_intel_plane_state(plane->state);
11583 int idx = intel_crtc->base.base.id, ret;
11584 int i = drm_plane_index(plane);
11585 bool mode_changed = needs_modeset(crtc_state);
11586 bool was_crtc_enabled = crtc->state->active;
11587 bool is_crtc_enabled = crtc_state->active;
11588
11589 bool turn_off, turn_on, visible, was_visible;
11590 struct drm_framebuffer *fb = plane_state->fb;
11591
11592 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11593 plane->type != DRM_PLANE_TYPE_CURSOR) {
11594 ret = skl_update_scaler_plane(
11595 to_intel_crtc_state(crtc_state),
11596 to_intel_plane_state(plane_state));
11597 if (ret)
11598 return ret;
11599 }
11600
11601 /*
11602 * Disabling a plane is always okay; we just need to update
11603 * fb tracking in a special way since cleanup_fb() won't
11604 * get called by the plane helpers.
11605 */
11606 if (old_plane_state->base.fb && !fb)
11607 intel_crtc->atomic.disabled_planes |= 1 << i;
11608
11609 was_visible = old_plane_state->visible;
11610 visible = to_intel_plane_state(plane_state)->visible;
11611
11612 if (!was_crtc_enabled && WARN_ON(was_visible))
11613 was_visible = false;
11614
11615 if (!is_crtc_enabled && WARN_ON(visible))
11616 visible = false;
11617
11618 if (!was_visible && !visible)
11619 return 0;
11620
11621 turn_off = was_visible && (!visible || mode_changed);
11622 turn_on = visible && (!was_visible || mode_changed);
11623
11624 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11625 plane->base.id, fb ? fb->base.id : -1);
11626
11627 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11628 plane->base.id, was_visible, visible,
11629 turn_off, turn_on, mode_changed);
11630
11631 if (turn_on) {
11632 intel_crtc->atomic.update_wm_pre = true;
11633 /* must disable cxsr around plane enable/disable */
11634 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11635 intel_crtc->atomic.disable_cxsr = true;
11636 /* to potentially re-enable cxsr */
11637 intel_crtc->atomic.wait_vblank = true;
11638 intel_crtc->atomic.update_wm_post = true;
11639 }
11640 } else if (turn_off) {
11641 intel_crtc->atomic.update_wm_post = true;
11642 /* must disable cxsr around plane enable/disable */
11643 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11644 if (is_crtc_enabled)
11645 intel_crtc->atomic.wait_vblank = true;
11646 intel_crtc->atomic.disable_cxsr = true;
11647 }
11648 } else if (intel_wm_need_update(plane, plane_state)) {
11649 intel_crtc->atomic.update_wm_pre = true;
11650 }
11651
11652 if (visible || was_visible)
11653 intel_crtc->atomic.fb_bits |=
11654 to_intel_plane(plane)->frontbuffer_bit;
11655
11656 switch (plane->type) {
11657 case DRM_PLANE_TYPE_PRIMARY:
11658 intel_crtc->atomic.wait_for_flips = true;
11659 intel_crtc->atomic.pre_disable_primary = turn_off;
11660 intel_crtc->atomic.post_enable_primary = turn_on;
11661
11662 if (turn_off) {
11663 /*
11664 * FIXME: Actually if we will still have any other
11665 * plane enabled on the pipe we could let IPS enabled
11666 * still, but for now lets consider that when we make
11667 * primary invisible by setting DSPCNTR to 0 on
11668 * update_primary_plane function IPS needs to be
11669 * disable.
11670 */
11671 intel_crtc->atomic.disable_ips = true;
11672
11673 intel_crtc->atomic.disable_fbc = true;
11674 }
11675
11676 /*
11677 * FBC does not work on some platforms for rotated
11678 * planes, so disable it when rotation is not 0 and
11679 * update it when rotation is set back to 0.
11680 *
11681 * FIXME: This is redundant with the fbc update done in
11682 * the primary plane enable function except that that
11683 * one is done too late. We eventually need to unify
11684 * this.
11685 */
11686
11687 if (visible &&
11688 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11689 dev_priv->fbc.crtc == intel_crtc &&
11690 plane_state->rotation != BIT(DRM_ROTATE_0))
11691 intel_crtc->atomic.disable_fbc = true;
11692
11693 /*
11694 * BDW signals flip done immediately if the plane
11695 * is disabled, even if the plane enable is already
11696 * armed to occur at the next vblank :(
11697 */
11698 if (turn_on && IS_BROADWELL(dev))
11699 intel_crtc->atomic.wait_vblank = true;
11700
11701 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11702 break;
11703 case DRM_PLANE_TYPE_CURSOR:
11704 break;
11705 case DRM_PLANE_TYPE_OVERLAY:
11706 if (turn_off && !mode_changed) {
11707 intel_crtc->atomic.wait_vblank = true;
11708 intel_crtc->atomic.update_sprite_watermarks |=
11709 1 << i;
11710 }
11711 }
11712 return 0;
11713 }
11714
11715 static bool encoders_cloneable(const struct intel_encoder *a,
11716 const struct intel_encoder *b)
11717 {
11718 /* masks could be asymmetric, so check both ways */
11719 return a == b || (a->cloneable & (1 << b->type) &&
11720 b->cloneable & (1 << a->type));
11721 }
11722
11723 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11724 struct intel_crtc *crtc,
11725 struct intel_encoder *encoder)
11726 {
11727 struct intel_encoder *source_encoder;
11728 struct drm_connector *connector;
11729 struct drm_connector_state *connector_state;
11730 int i;
11731
11732 for_each_connector_in_state(state, connector, connector_state, i) {
11733 if (connector_state->crtc != &crtc->base)
11734 continue;
11735
11736 source_encoder =
11737 to_intel_encoder(connector_state->best_encoder);
11738 if (!encoders_cloneable(encoder, source_encoder))
11739 return false;
11740 }
11741
11742 return true;
11743 }
11744
11745 static bool check_encoder_cloning(struct drm_atomic_state *state,
11746 struct intel_crtc *crtc)
11747 {
11748 struct intel_encoder *encoder;
11749 struct drm_connector *connector;
11750 struct drm_connector_state *connector_state;
11751 int i;
11752
11753 for_each_connector_in_state(state, connector, connector_state, i) {
11754 if (connector_state->crtc != &crtc->base)
11755 continue;
11756
11757 encoder = to_intel_encoder(connector_state->best_encoder);
11758 if (!check_single_encoder_cloning(state, crtc, encoder))
11759 return false;
11760 }
11761
11762 return true;
11763 }
11764
11765 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11766 struct drm_crtc_state *crtc_state)
11767 {
11768 struct drm_device *dev = crtc->dev;
11769 struct drm_i915_private *dev_priv = dev->dev_private;
11770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11771 struct intel_crtc_state *pipe_config =
11772 to_intel_crtc_state(crtc_state);
11773 struct drm_atomic_state *state = crtc_state->state;
11774 int ret;
11775 bool mode_changed = needs_modeset(crtc_state);
11776
11777 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11778 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11779 return -EINVAL;
11780 }
11781
11782 if (mode_changed && !crtc_state->active)
11783 intel_crtc->atomic.update_wm_post = true;
11784
11785 if (mode_changed && crtc_state->enable &&
11786 dev_priv->display.crtc_compute_clock &&
11787 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11788 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11789 pipe_config);
11790 if (ret)
11791 return ret;
11792 }
11793
11794 ret = 0;
11795 if (INTEL_INFO(dev)->gen >= 9) {
11796 if (mode_changed)
11797 ret = skl_update_scaler_crtc(pipe_config);
11798
11799 if (!ret)
11800 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11801 pipe_config);
11802 }
11803
11804 return ret;
11805 }
11806
11807 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11808 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11809 .load_lut = intel_crtc_load_lut,
11810 .atomic_begin = intel_begin_crtc_commit,
11811 .atomic_flush = intel_finish_crtc_commit,
11812 .atomic_check = intel_crtc_atomic_check,
11813 };
11814
11815 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11816 {
11817 struct intel_connector *connector;
11818
11819 for_each_intel_connector(dev, connector) {
11820 if (connector->base.encoder) {
11821 connector->base.state->best_encoder =
11822 connector->base.encoder;
11823 connector->base.state->crtc =
11824 connector->base.encoder->crtc;
11825 } else {
11826 connector->base.state->best_encoder = NULL;
11827 connector->base.state->crtc = NULL;
11828 }
11829 }
11830 }
11831
11832 static void
11833 connected_sink_compute_bpp(struct intel_connector *connector,
11834 struct intel_crtc_state *pipe_config)
11835 {
11836 int bpp = pipe_config->pipe_bpp;
11837
11838 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11839 connector->base.base.id,
11840 connector->base.name);
11841
11842 /* Don't use an invalid EDID bpc value */
11843 if (connector->base.display_info.bpc &&
11844 connector->base.display_info.bpc * 3 < bpp) {
11845 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11846 bpp, connector->base.display_info.bpc*3);
11847 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11848 }
11849
11850 /* Clamp bpp to 8 on screens without EDID 1.4 */
11851 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11852 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11853 bpp);
11854 pipe_config->pipe_bpp = 24;
11855 }
11856 }
11857
11858 static int
11859 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11860 struct intel_crtc_state *pipe_config)
11861 {
11862 struct drm_device *dev = crtc->base.dev;
11863 struct drm_atomic_state *state;
11864 struct drm_connector *connector;
11865 struct drm_connector_state *connector_state;
11866 int bpp, i;
11867
11868 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11869 bpp = 10*3;
11870 else if (INTEL_INFO(dev)->gen >= 5)
11871 bpp = 12*3;
11872 else
11873 bpp = 8*3;
11874
11875
11876 pipe_config->pipe_bpp = bpp;
11877
11878 state = pipe_config->base.state;
11879
11880 /* Clamp display bpp to EDID value */
11881 for_each_connector_in_state(state, connector, connector_state, i) {
11882 if (connector_state->crtc != &crtc->base)
11883 continue;
11884
11885 connected_sink_compute_bpp(to_intel_connector(connector),
11886 pipe_config);
11887 }
11888
11889 return bpp;
11890 }
11891
11892 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11893 {
11894 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11895 "type: 0x%x flags: 0x%x\n",
11896 mode->crtc_clock,
11897 mode->crtc_hdisplay, mode->crtc_hsync_start,
11898 mode->crtc_hsync_end, mode->crtc_htotal,
11899 mode->crtc_vdisplay, mode->crtc_vsync_start,
11900 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11901 }
11902
11903 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11904 struct intel_crtc_state *pipe_config,
11905 const char *context)
11906 {
11907 struct drm_device *dev = crtc->base.dev;
11908 struct drm_plane *plane;
11909 struct intel_plane *intel_plane;
11910 struct intel_plane_state *state;
11911 struct drm_framebuffer *fb;
11912
11913 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11914 context, pipe_config, pipe_name(crtc->pipe));
11915
11916 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11917 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11918 pipe_config->pipe_bpp, pipe_config->dither);
11919 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11920 pipe_config->has_pch_encoder,
11921 pipe_config->fdi_lanes,
11922 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11923 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11924 pipe_config->fdi_m_n.tu);
11925 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11926 pipe_config->has_dp_encoder,
11927 pipe_config->lane_count,
11928 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11929 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11930 pipe_config->dp_m_n.tu);
11931
11932 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11933 pipe_config->has_dp_encoder,
11934 pipe_config->lane_count,
11935 pipe_config->dp_m2_n2.gmch_m,
11936 pipe_config->dp_m2_n2.gmch_n,
11937 pipe_config->dp_m2_n2.link_m,
11938 pipe_config->dp_m2_n2.link_n,
11939 pipe_config->dp_m2_n2.tu);
11940
11941 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11942 pipe_config->has_audio,
11943 pipe_config->has_infoframe);
11944
11945 DRM_DEBUG_KMS("requested mode:\n");
11946 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11947 DRM_DEBUG_KMS("adjusted mode:\n");
11948 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11949 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11950 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11951 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11952 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11953 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11954 crtc->num_scalers,
11955 pipe_config->scaler_state.scaler_users,
11956 pipe_config->scaler_state.scaler_id);
11957 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11958 pipe_config->gmch_pfit.control,
11959 pipe_config->gmch_pfit.pgm_ratios,
11960 pipe_config->gmch_pfit.lvds_border_bits);
11961 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11962 pipe_config->pch_pfit.pos,
11963 pipe_config->pch_pfit.size,
11964 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11965 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11966 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11967
11968 if (IS_BROXTON(dev)) {
11969 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11970 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11971 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11972 pipe_config->ddi_pll_sel,
11973 pipe_config->dpll_hw_state.ebb0,
11974 pipe_config->dpll_hw_state.ebb4,
11975 pipe_config->dpll_hw_state.pll0,
11976 pipe_config->dpll_hw_state.pll1,
11977 pipe_config->dpll_hw_state.pll2,
11978 pipe_config->dpll_hw_state.pll3,
11979 pipe_config->dpll_hw_state.pll6,
11980 pipe_config->dpll_hw_state.pll8,
11981 pipe_config->dpll_hw_state.pll9,
11982 pipe_config->dpll_hw_state.pll10,
11983 pipe_config->dpll_hw_state.pcsdw12);
11984 } else if (IS_SKYLAKE(dev)) {
11985 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11986 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11987 pipe_config->ddi_pll_sel,
11988 pipe_config->dpll_hw_state.ctrl1,
11989 pipe_config->dpll_hw_state.cfgcr1,
11990 pipe_config->dpll_hw_state.cfgcr2);
11991 } else if (HAS_DDI(dev)) {
11992 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11993 pipe_config->ddi_pll_sel,
11994 pipe_config->dpll_hw_state.wrpll);
11995 } else {
11996 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11997 "fp0: 0x%x, fp1: 0x%x\n",
11998 pipe_config->dpll_hw_state.dpll,
11999 pipe_config->dpll_hw_state.dpll_md,
12000 pipe_config->dpll_hw_state.fp0,
12001 pipe_config->dpll_hw_state.fp1);
12002 }
12003
12004 DRM_DEBUG_KMS("planes on this crtc\n");
12005 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12006 intel_plane = to_intel_plane(plane);
12007 if (intel_plane->pipe != crtc->pipe)
12008 continue;
12009
12010 state = to_intel_plane_state(plane->state);
12011 fb = state->base.fb;
12012 if (!fb) {
12013 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12014 "disabled, scaler_id = %d\n",
12015 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12016 plane->base.id, intel_plane->pipe,
12017 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12018 drm_plane_index(plane), state->scaler_id);
12019 continue;
12020 }
12021
12022 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12023 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12024 plane->base.id, intel_plane->pipe,
12025 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12026 drm_plane_index(plane));
12027 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12028 fb->base.id, fb->width, fb->height, fb->pixel_format);
12029 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12030 state->scaler_id,
12031 state->src.x1 >> 16, state->src.y1 >> 16,
12032 drm_rect_width(&state->src) >> 16,
12033 drm_rect_height(&state->src) >> 16,
12034 state->dst.x1, state->dst.y1,
12035 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12036 }
12037 }
12038
12039 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12040 {
12041 struct drm_device *dev = state->dev;
12042 struct intel_encoder *encoder;
12043 struct drm_connector *connector;
12044 struct drm_connector_state *connector_state;
12045 unsigned int used_ports = 0;
12046 int i;
12047
12048 /*
12049 * Walk the connector list instead of the encoder
12050 * list to detect the problem on ddi platforms
12051 * where there's just one encoder per digital port.
12052 */
12053 for_each_connector_in_state(state, connector, connector_state, i) {
12054 if (!connector_state->best_encoder)
12055 continue;
12056
12057 encoder = to_intel_encoder(connector_state->best_encoder);
12058
12059 WARN_ON(!connector_state->crtc);
12060
12061 switch (encoder->type) {
12062 unsigned int port_mask;
12063 case INTEL_OUTPUT_UNKNOWN:
12064 if (WARN_ON(!HAS_DDI(dev)))
12065 break;
12066 case INTEL_OUTPUT_DISPLAYPORT:
12067 case INTEL_OUTPUT_HDMI:
12068 case INTEL_OUTPUT_EDP:
12069 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12070
12071 /* the same port mustn't appear more than once */
12072 if (used_ports & port_mask)
12073 return false;
12074
12075 used_ports |= port_mask;
12076 default:
12077 break;
12078 }
12079 }
12080
12081 return true;
12082 }
12083
12084 static void
12085 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12086 {
12087 struct drm_crtc_state tmp_state;
12088 struct intel_crtc_scaler_state scaler_state;
12089 struct intel_dpll_hw_state dpll_hw_state;
12090 enum intel_dpll_id shared_dpll;
12091 uint32_t ddi_pll_sel;
12092 bool force_thru;
12093
12094 /* FIXME: before the switch to atomic started, a new pipe_config was
12095 * kzalloc'd. Code that depends on any field being zero should be
12096 * fixed, so that the crtc_state can be safely duplicated. For now,
12097 * only fields that are know to not cause problems are preserved. */
12098
12099 tmp_state = crtc_state->base;
12100 scaler_state = crtc_state->scaler_state;
12101 shared_dpll = crtc_state->shared_dpll;
12102 dpll_hw_state = crtc_state->dpll_hw_state;
12103 ddi_pll_sel = crtc_state->ddi_pll_sel;
12104 force_thru = crtc_state->pch_pfit.force_thru;
12105
12106 memset(crtc_state, 0, sizeof *crtc_state);
12107
12108 crtc_state->base = tmp_state;
12109 crtc_state->scaler_state = scaler_state;
12110 crtc_state->shared_dpll = shared_dpll;
12111 crtc_state->dpll_hw_state = dpll_hw_state;
12112 crtc_state->ddi_pll_sel = ddi_pll_sel;
12113 crtc_state->pch_pfit.force_thru = force_thru;
12114 }
12115
12116 static int
12117 intel_modeset_pipe_config(struct drm_crtc *crtc,
12118 struct intel_crtc_state *pipe_config)
12119 {
12120 struct drm_atomic_state *state = pipe_config->base.state;
12121 struct intel_encoder *encoder;
12122 struct drm_connector *connector;
12123 struct drm_connector_state *connector_state;
12124 int base_bpp, ret = -EINVAL;
12125 int i;
12126 bool retry = true;
12127
12128 clear_intel_crtc_state(pipe_config);
12129
12130 pipe_config->cpu_transcoder =
12131 (enum transcoder) to_intel_crtc(crtc)->pipe;
12132
12133 /*
12134 * Sanitize sync polarity flags based on requested ones. If neither
12135 * positive or negative polarity is requested, treat this as meaning
12136 * negative polarity.
12137 */
12138 if (!(pipe_config->base.adjusted_mode.flags &
12139 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12140 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12141
12142 if (!(pipe_config->base.adjusted_mode.flags &
12143 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12144 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12145
12146 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12147 pipe_config);
12148 if (base_bpp < 0)
12149 goto fail;
12150
12151 /*
12152 * Determine the real pipe dimensions. Note that stereo modes can
12153 * increase the actual pipe size due to the frame doubling and
12154 * insertion of additional space for blanks between the frame. This
12155 * is stored in the crtc timings. We use the requested mode to do this
12156 * computation to clearly distinguish it from the adjusted mode, which
12157 * can be changed by the connectors in the below retry loop.
12158 */
12159 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12160 &pipe_config->pipe_src_w,
12161 &pipe_config->pipe_src_h);
12162
12163 encoder_retry:
12164 /* Ensure the port clock defaults are reset when retrying. */
12165 pipe_config->port_clock = 0;
12166 pipe_config->pixel_multiplier = 1;
12167
12168 /* Fill in default crtc timings, allow encoders to overwrite them. */
12169 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12170 CRTC_STEREO_DOUBLE);
12171
12172 /* Pass our mode to the connectors and the CRTC to give them a chance to
12173 * adjust it according to limitations or connector properties, and also
12174 * a chance to reject the mode entirely.
12175 */
12176 for_each_connector_in_state(state, connector, connector_state, i) {
12177 if (connector_state->crtc != crtc)
12178 continue;
12179
12180 encoder = to_intel_encoder(connector_state->best_encoder);
12181
12182 if (!(encoder->compute_config(encoder, pipe_config))) {
12183 DRM_DEBUG_KMS("Encoder config failure\n");
12184 goto fail;
12185 }
12186 }
12187
12188 /* Set default port clock if not overwritten by the encoder. Needs to be
12189 * done afterwards in case the encoder adjusts the mode. */
12190 if (!pipe_config->port_clock)
12191 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12192 * pipe_config->pixel_multiplier;
12193
12194 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12195 if (ret < 0) {
12196 DRM_DEBUG_KMS("CRTC fixup failed\n");
12197 goto fail;
12198 }
12199
12200 if (ret == RETRY) {
12201 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12202 ret = -EINVAL;
12203 goto fail;
12204 }
12205
12206 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12207 retry = false;
12208 goto encoder_retry;
12209 }
12210
12211 /* Dithering seems to not pass-through bits correctly when it should, so
12212 * only enable it on 6bpc panels. */
12213 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12214 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12215 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12216
12217 fail:
12218 return ret;
12219 }
12220
12221 static void
12222 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12223 {
12224 struct drm_crtc *crtc;
12225 struct drm_crtc_state *crtc_state;
12226 int i;
12227
12228 /* Double check state. */
12229 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12230 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12231
12232 /* Update hwmode for vblank functions */
12233 if (crtc->state->active)
12234 crtc->hwmode = crtc->state->adjusted_mode;
12235 else
12236 crtc->hwmode.crtc_clock = 0;
12237 }
12238 }
12239
12240 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12241 {
12242 int diff;
12243
12244 if (clock1 == clock2)
12245 return true;
12246
12247 if (!clock1 || !clock2)
12248 return false;
12249
12250 diff = abs(clock1 - clock2);
12251
12252 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12253 return true;
12254
12255 return false;
12256 }
12257
12258 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12259 list_for_each_entry((intel_crtc), \
12260 &(dev)->mode_config.crtc_list, \
12261 base.head) \
12262 if (mask & (1 <<(intel_crtc)->pipe))
12263
12264 static bool
12265 intel_compare_m_n(unsigned int m, unsigned int n,
12266 unsigned int m2, unsigned int n2,
12267 bool exact)
12268 {
12269 if (m == m2 && n == n2)
12270 return true;
12271
12272 if (exact || !m || !n || !m2 || !n2)
12273 return false;
12274
12275 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12276
12277 if (m > m2) {
12278 while (m > m2) {
12279 m2 <<= 1;
12280 n2 <<= 1;
12281 }
12282 } else if (m < m2) {
12283 while (m < m2) {
12284 m <<= 1;
12285 n <<= 1;
12286 }
12287 }
12288
12289 return m == m2 && n == n2;
12290 }
12291
12292 static bool
12293 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12294 struct intel_link_m_n *m2_n2,
12295 bool adjust)
12296 {
12297 if (m_n->tu == m2_n2->tu &&
12298 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12299 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12300 intel_compare_m_n(m_n->link_m, m_n->link_n,
12301 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12302 if (adjust)
12303 *m2_n2 = *m_n;
12304
12305 return true;
12306 }
12307
12308 return false;
12309 }
12310
12311 static bool
12312 intel_pipe_config_compare(struct drm_device *dev,
12313 struct intel_crtc_state *current_config,
12314 struct intel_crtc_state *pipe_config,
12315 bool adjust)
12316 {
12317 bool ret = true;
12318
12319 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12320 do { \
12321 if (!adjust) \
12322 DRM_ERROR(fmt, ##__VA_ARGS__); \
12323 else \
12324 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12325 } while (0)
12326
12327 #define PIPE_CONF_CHECK_X(name) \
12328 if (current_config->name != pipe_config->name) { \
12329 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12330 "(expected 0x%08x, found 0x%08x)\n", \
12331 current_config->name, \
12332 pipe_config->name); \
12333 ret = false; \
12334 }
12335
12336 #define PIPE_CONF_CHECK_I(name) \
12337 if (current_config->name != pipe_config->name) { \
12338 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12339 "(expected %i, found %i)\n", \
12340 current_config->name, \
12341 pipe_config->name); \
12342 ret = false; \
12343 }
12344
12345 #define PIPE_CONF_CHECK_M_N(name) \
12346 if (!intel_compare_link_m_n(&current_config->name, \
12347 &pipe_config->name,\
12348 adjust)) { \
12349 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12350 "(expected tu %i gmch %i/%i link %i/%i, " \
12351 "found tu %i, gmch %i/%i link %i/%i)\n", \
12352 current_config->name.tu, \
12353 current_config->name.gmch_m, \
12354 current_config->name.gmch_n, \
12355 current_config->name.link_m, \
12356 current_config->name.link_n, \
12357 pipe_config->name.tu, \
12358 pipe_config->name.gmch_m, \
12359 pipe_config->name.gmch_n, \
12360 pipe_config->name.link_m, \
12361 pipe_config->name.link_n); \
12362 ret = false; \
12363 }
12364
12365 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12366 if (!intel_compare_link_m_n(&current_config->name, \
12367 &pipe_config->name, adjust) && \
12368 !intel_compare_link_m_n(&current_config->alt_name, \
12369 &pipe_config->name, adjust)) { \
12370 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12371 "(expected tu %i gmch %i/%i link %i/%i, " \
12372 "or tu %i gmch %i/%i link %i/%i, " \
12373 "found tu %i, gmch %i/%i link %i/%i)\n", \
12374 current_config->name.tu, \
12375 current_config->name.gmch_m, \
12376 current_config->name.gmch_n, \
12377 current_config->name.link_m, \
12378 current_config->name.link_n, \
12379 current_config->alt_name.tu, \
12380 current_config->alt_name.gmch_m, \
12381 current_config->alt_name.gmch_n, \
12382 current_config->alt_name.link_m, \
12383 current_config->alt_name.link_n, \
12384 pipe_config->name.tu, \
12385 pipe_config->name.gmch_m, \
12386 pipe_config->name.gmch_n, \
12387 pipe_config->name.link_m, \
12388 pipe_config->name.link_n); \
12389 ret = false; \
12390 }
12391
12392 /* This is required for BDW+ where there is only one set of registers for
12393 * switching between high and low RR.
12394 * This macro can be used whenever a comparison has to be made between one
12395 * hw state and multiple sw state variables.
12396 */
12397 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12398 if ((current_config->name != pipe_config->name) && \
12399 (current_config->alt_name != pipe_config->name)) { \
12400 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12401 "(expected %i or %i, found %i)\n", \
12402 current_config->name, \
12403 current_config->alt_name, \
12404 pipe_config->name); \
12405 ret = false; \
12406 }
12407
12408 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12409 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12410 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12411 "(expected %i, found %i)\n", \
12412 current_config->name & (mask), \
12413 pipe_config->name & (mask)); \
12414 ret = false; \
12415 }
12416
12417 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12418 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12419 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12420 "(expected %i, found %i)\n", \
12421 current_config->name, \
12422 pipe_config->name); \
12423 ret = false; \
12424 }
12425
12426 #define PIPE_CONF_QUIRK(quirk) \
12427 ((current_config->quirks | pipe_config->quirks) & (quirk))
12428
12429 PIPE_CONF_CHECK_I(cpu_transcoder);
12430
12431 PIPE_CONF_CHECK_I(has_pch_encoder);
12432 PIPE_CONF_CHECK_I(fdi_lanes);
12433 PIPE_CONF_CHECK_M_N(fdi_m_n);
12434
12435 PIPE_CONF_CHECK_I(has_dp_encoder);
12436 PIPE_CONF_CHECK_I(lane_count);
12437
12438 if (INTEL_INFO(dev)->gen < 8) {
12439 PIPE_CONF_CHECK_M_N(dp_m_n);
12440
12441 PIPE_CONF_CHECK_I(has_drrs);
12442 if (current_config->has_drrs)
12443 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12444 } else
12445 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12446
12447 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12448 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12449 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12450 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12451 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12452 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12453
12454 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12455 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12456 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12457 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12458 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12459 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12460
12461 PIPE_CONF_CHECK_I(pixel_multiplier);
12462 PIPE_CONF_CHECK_I(has_hdmi_sink);
12463 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12464 IS_VALLEYVIEW(dev))
12465 PIPE_CONF_CHECK_I(limited_color_range);
12466 PIPE_CONF_CHECK_I(has_infoframe);
12467
12468 PIPE_CONF_CHECK_I(has_audio);
12469
12470 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12471 DRM_MODE_FLAG_INTERLACE);
12472
12473 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12474 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12475 DRM_MODE_FLAG_PHSYNC);
12476 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12477 DRM_MODE_FLAG_NHSYNC);
12478 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12479 DRM_MODE_FLAG_PVSYNC);
12480 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12481 DRM_MODE_FLAG_NVSYNC);
12482 }
12483
12484 PIPE_CONF_CHECK_X(gmch_pfit.control);
12485 /* pfit ratios are autocomputed by the hw on gen4+ */
12486 if (INTEL_INFO(dev)->gen < 4)
12487 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12488 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12489
12490 if (!adjust) {
12491 PIPE_CONF_CHECK_I(pipe_src_w);
12492 PIPE_CONF_CHECK_I(pipe_src_h);
12493
12494 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12495 if (current_config->pch_pfit.enabled) {
12496 PIPE_CONF_CHECK_X(pch_pfit.pos);
12497 PIPE_CONF_CHECK_X(pch_pfit.size);
12498 }
12499
12500 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12501 }
12502
12503 /* BDW+ don't expose a synchronous way to read the state */
12504 if (IS_HASWELL(dev))
12505 PIPE_CONF_CHECK_I(ips_enabled);
12506
12507 PIPE_CONF_CHECK_I(double_wide);
12508
12509 PIPE_CONF_CHECK_X(ddi_pll_sel);
12510
12511 PIPE_CONF_CHECK_I(shared_dpll);
12512 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12513 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12514 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12515 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12516 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12517 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12518 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12519 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12520
12521 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12522 PIPE_CONF_CHECK_I(pipe_bpp);
12523
12524 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12525 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12526
12527 #undef PIPE_CONF_CHECK_X
12528 #undef PIPE_CONF_CHECK_I
12529 #undef PIPE_CONF_CHECK_I_ALT
12530 #undef PIPE_CONF_CHECK_FLAGS
12531 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12532 #undef PIPE_CONF_QUIRK
12533 #undef INTEL_ERR_OR_DBG_KMS
12534
12535 return ret;
12536 }
12537
12538 static void check_wm_state(struct drm_device *dev)
12539 {
12540 struct drm_i915_private *dev_priv = dev->dev_private;
12541 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12542 struct intel_crtc *intel_crtc;
12543 int plane;
12544
12545 if (INTEL_INFO(dev)->gen < 9)
12546 return;
12547
12548 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12549 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12550
12551 for_each_intel_crtc(dev, intel_crtc) {
12552 struct skl_ddb_entry *hw_entry, *sw_entry;
12553 const enum pipe pipe = intel_crtc->pipe;
12554
12555 if (!intel_crtc->active)
12556 continue;
12557
12558 /* planes */
12559 for_each_plane(dev_priv, pipe, plane) {
12560 hw_entry = &hw_ddb.plane[pipe][plane];
12561 sw_entry = &sw_ddb->plane[pipe][plane];
12562
12563 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12564 continue;
12565
12566 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12567 "(expected (%u,%u), found (%u,%u))\n",
12568 pipe_name(pipe), plane + 1,
12569 sw_entry->start, sw_entry->end,
12570 hw_entry->start, hw_entry->end);
12571 }
12572
12573 /* cursor */
12574 hw_entry = &hw_ddb.cursor[pipe];
12575 sw_entry = &sw_ddb->cursor[pipe];
12576
12577 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12578 continue;
12579
12580 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12581 "(expected (%u,%u), found (%u,%u))\n",
12582 pipe_name(pipe),
12583 sw_entry->start, sw_entry->end,
12584 hw_entry->start, hw_entry->end);
12585 }
12586 }
12587
12588 static void
12589 check_connector_state(struct drm_device *dev,
12590 struct drm_atomic_state *old_state)
12591 {
12592 struct drm_connector_state *old_conn_state;
12593 struct drm_connector *connector;
12594 int i;
12595
12596 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12597 struct drm_encoder *encoder = connector->encoder;
12598 struct drm_connector_state *state = connector->state;
12599
12600 /* This also checks the encoder/connector hw state with the
12601 * ->get_hw_state callbacks. */
12602 intel_connector_check_state(to_intel_connector(connector));
12603
12604 I915_STATE_WARN(state->best_encoder != encoder,
12605 "connector's atomic encoder doesn't match legacy encoder\n");
12606 }
12607 }
12608
12609 static void
12610 check_encoder_state(struct drm_device *dev)
12611 {
12612 struct intel_encoder *encoder;
12613 struct intel_connector *connector;
12614
12615 for_each_intel_encoder(dev, encoder) {
12616 bool enabled = false;
12617 enum pipe pipe;
12618
12619 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12620 encoder->base.base.id,
12621 encoder->base.name);
12622
12623 for_each_intel_connector(dev, connector) {
12624 if (connector->base.state->best_encoder != &encoder->base)
12625 continue;
12626 enabled = true;
12627
12628 I915_STATE_WARN(connector->base.state->crtc !=
12629 encoder->base.crtc,
12630 "connector's crtc doesn't match encoder crtc\n");
12631 }
12632
12633 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12634 "encoder's enabled state mismatch "
12635 "(expected %i, found %i)\n",
12636 !!encoder->base.crtc, enabled);
12637
12638 if (!encoder->base.crtc) {
12639 bool active;
12640
12641 active = encoder->get_hw_state(encoder, &pipe);
12642 I915_STATE_WARN(active,
12643 "encoder detached but still enabled on pipe %c.\n",
12644 pipe_name(pipe));
12645 }
12646 }
12647 }
12648
12649 static void
12650 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12651 {
12652 struct drm_i915_private *dev_priv = dev->dev_private;
12653 struct intel_encoder *encoder;
12654 struct drm_crtc_state *old_crtc_state;
12655 struct drm_crtc *crtc;
12656 int i;
12657
12658 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12660 struct intel_crtc_state *pipe_config, *sw_config;
12661 bool active;
12662
12663 if (!needs_modeset(crtc->state) &&
12664 !to_intel_crtc_state(crtc->state)->update_pipe)
12665 continue;
12666
12667 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12668 pipe_config = to_intel_crtc_state(old_crtc_state);
12669 memset(pipe_config, 0, sizeof(*pipe_config));
12670 pipe_config->base.crtc = crtc;
12671 pipe_config->base.state = old_state;
12672
12673 DRM_DEBUG_KMS("[CRTC:%d]\n",
12674 crtc->base.id);
12675
12676 active = dev_priv->display.get_pipe_config(intel_crtc,
12677 pipe_config);
12678
12679 /* hw state is inconsistent with the pipe quirk */
12680 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12681 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12682 active = crtc->state->active;
12683
12684 I915_STATE_WARN(crtc->state->active != active,
12685 "crtc active state doesn't match with hw state "
12686 "(expected %i, found %i)\n", crtc->state->active, active);
12687
12688 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12689 "transitional active state does not match atomic hw state "
12690 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12691
12692 for_each_encoder_on_crtc(dev, crtc, encoder) {
12693 enum pipe pipe;
12694
12695 active = encoder->get_hw_state(encoder, &pipe);
12696 I915_STATE_WARN(active != crtc->state->active,
12697 "[ENCODER:%i] active %i with crtc active %i\n",
12698 encoder->base.base.id, active, crtc->state->active);
12699
12700 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12701 "Encoder connected to wrong pipe %c\n",
12702 pipe_name(pipe));
12703
12704 if (active)
12705 encoder->get_config(encoder, pipe_config);
12706 }
12707
12708 if (!crtc->state->active)
12709 continue;
12710
12711 sw_config = to_intel_crtc_state(crtc->state);
12712 if (!intel_pipe_config_compare(dev, sw_config,
12713 pipe_config, false)) {
12714 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12715 intel_dump_pipe_config(intel_crtc, pipe_config,
12716 "[hw state]");
12717 intel_dump_pipe_config(intel_crtc, sw_config,
12718 "[sw state]");
12719 }
12720 }
12721 }
12722
12723 static void
12724 check_shared_dpll_state(struct drm_device *dev)
12725 {
12726 struct drm_i915_private *dev_priv = dev->dev_private;
12727 struct intel_crtc *crtc;
12728 struct intel_dpll_hw_state dpll_hw_state;
12729 int i;
12730
12731 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12732 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12733 int enabled_crtcs = 0, active_crtcs = 0;
12734 bool active;
12735
12736 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12737
12738 DRM_DEBUG_KMS("%s\n", pll->name);
12739
12740 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12741
12742 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12743 "more active pll users than references: %i vs %i\n",
12744 pll->active, hweight32(pll->config.crtc_mask));
12745 I915_STATE_WARN(pll->active && !pll->on,
12746 "pll in active use but not on in sw tracking\n");
12747 I915_STATE_WARN(pll->on && !pll->active,
12748 "pll in on but not on in use in sw tracking\n");
12749 I915_STATE_WARN(pll->on != active,
12750 "pll on state mismatch (expected %i, found %i)\n",
12751 pll->on, active);
12752
12753 for_each_intel_crtc(dev, crtc) {
12754 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12755 enabled_crtcs++;
12756 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12757 active_crtcs++;
12758 }
12759 I915_STATE_WARN(pll->active != active_crtcs,
12760 "pll active crtcs mismatch (expected %i, found %i)\n",
12761 pll->active, active_crtcs);
12762 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12763 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12764 hweight32(pll->config.crtc_mask), enabled_crtcs);
12765
12766 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12767 sizeof(dpll_hw_state)),
12768 "pll hw state mismatch\n");
12769 }
12770 }
12771
12772 static void
12773 intel_modeset_check_state(struct drm_device *dev,
12774 struct drm_atomic_state *old_state)
12775 {
12776 check_wm_state(dev);
12777 check_connector_state(dev, old_state);
12778 check_encoder_state(dev);
12779 check_crtc_state(dev, old_state);
12780 check_shared_dpll_state(dev);
12781 }
12782
12783 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12784 int dotclock)
12785 {
12786 /*
12787 * FDI already provided one idea for the dotclock.
12788 * Yell if the encoder disagrees.
12789 */
12790 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12791 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12792 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12793 }
12794
12795 static void update_scanline_offset(struct intel_crtc *crtc)
12796 {
12797 struct drm_device *dev = crtc->base.dev;
12798
12799 /*
12800 * The scanline counter increments at the leading edge of hsync.
12801 *
12802 * On most platforms it starts counting from vtotal-1 on the
12803 * first active line. That means the scanline counter value is
12804 * always one less than what we would expect. Ie. just after
12805 * start of vblank, which also occurs at start of hsync (on the
12806 * last active line), the scanline counter will read vblank_start-1.
12807 *
12808 * On gen2 the scanline counter starts counting from 1 instead
12809 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12810 * to keep the value positive), instead of adding one.
12811 *
12812 * On HSW+ the behaviour of the scanline counter depends on the output
12813 * type. For DP ports it behaves like most other platforms, but on HDMI
12814 * there's an extra 1 line difference. So we need to add two instead of
12815 * one to the value.
12816 */
12817 if (IS_GEN2(dev)) {
12818 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12819 int vtotal;
12820
12821 vtotal = mode->crtc_vtotal;
12822 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12823 vtotal /= 2;
12824
12825 crtc->scanline_offset = vtotal - 1;
12826 } else if (HAS_DDI(dev) &&
12827 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12828 crtc->scanline_offset = 2;
12829 } else
12830 crtc->scanline_offset = 1;
12831 }
12832
12833 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12834 {
12835 struct drm_device *dev = state->dev;
12836 struct drm_i915_private *dev_priv = to_i915(dev);
12837 struct intel_shared_dpll_config *shared_dpll = NULL;
12838 struct intel_crtc *intel_crtc;
12839 struct intel_crtc_state *intel_crtc_state;
12840 struct drm_crtc *crtc;
12841 struct drm_crtc_state *crtc_state;
12842 int i;
12843
12844 if (!dev_priv->display.crtc_compute_clock)
12845 return;
12846
12847 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12848 int dpll;
12849
12850 intel_crtc = to_intel_crtc(crtc);
12851 intel_crtc_state = to_intel_crtc_state(crtc_state);
12852 dpll = intel_crtc_state->shared_dpll;
12853
12854 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12855 continue;
12856
12857 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12858
12859 if (!shared_dpll)
12860 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12861
12862 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12863 }
12864 }
12865
12866 /*
12867 * This implements the workaround described in the "notes" section of the mode
12868 * set sequence documentation. When going from no pipes or single pipe to
12869 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12870 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12871 */
12872 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12873 {
12874 struct drm_crtc_state *crtc_state;
12875 struct intel_crtc *intel_crtc;
12876 struct drm_crtc *crtc;
12877 struct intel_crtc_state *first_crtc_state = NULL;
12878 struct intel_crtc_state *other_crtc_state = NULL;
12879 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12880 int i;
12881
12882 /* look at all crtc's that are going to be enabled in during modeset */
12883 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12884 intel_crtc = to_intel_crtc(crtc);
12885
12886 if (!crtc_state->active || !needs_modeset(crtc_state))
12887 continue;
12888
12889 if (first_crtc_state) {
12890 other_crtc_state = to_intel_crtc_state(crtc_state);
12891 break;
12892 } else {
12893 first_crtc_state = to_intel_crtc_state(crtc_state);
12894 first_pipe = intel_crtc->pipe;
12895 }
12896 }
12897
12898 /* No workaround needed? */
12899 if (!first_crtc_state)
12900 return 0;
12901
12902 /* w/a possibly needed, check how many crtc's are already enabled. */
12903 for_each_intel_crtc(state->dev, intel_crtc) {
12904 struct intel_crtc_state *pipe_config;
12905
12906 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12907 if (IS_ERR(pipe_config))
12908 return PTR_ERR(pipe_config);
12909
12910 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12911
12912 if (!pipe_config->base.active ||
12913 needs_modeset(&pipe_config->base))
12914 continue;
12915
12916 /* 2 or more enabled crtcs means no need for w/a */
12917 if (enabled_pipe != INVALID_PIPE)
12918 return 0;
12919
12920 enabled_pipe = intel_crtc->pipe;
12921 }
12922
12923 if (enabled_pipe != INVALID_PIPE)
12924 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12925 else if (other_crtc_state)
12926 other_crtc_state->hsw_workaround_pipe = first_pipe;
12927
12928 return 0;
12929 }
12930
12931 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12932 {
12933 struct drm_crtc *crtc;
12934 struct drm_crtc_state *crtc_state;
12935 int ret = 0;
12936
12937 /* add all active pipes to the state */
12938 for_each_crtc(state->dev, crtc) {
12939 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12940 if (IS_ERR(crtc_state))
12941 return PTR_ERR(crtc_state);
12942
12943 if (!crtc_state->active || needs_modeset(crtc_state))
12944 continue;
12945
12946 crtc_state->mode_changed = true;
12947
12948 ret = drm_atomic_add_affected_connectors(state, crtc);
12949 if (ret)
12950 break;
12951
12952 ret = drm_atomic_add_affected_planes(state, crtc);
12953 if (ret)
12954 break;
12955 }
12956
12957 return ret;
12958 }
12959
12960 static int intel_modeset_checks(struct drm_atomic_state *state)
12961 {
12962 struct drm_device *dev = state->dev;
12963 struct drm_i915_private *dev_priv = dev->dev_private;
12964 int ret;
12965
12966 if (!check_digital_port_conflicts(state)) {
12967 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12968 return -EINVAL;
12969 }
12970
12971 /*
12972 * See if the config requires any additional preparation, e.g.
12973 * to adjust global state with pipes off. We need to do this
12974 * here so we can get the modeset_pipe updated config for the new
12975 * mode set on this crtc. For other crtcs we need to use the
12976 * adjusted_mode bits in the crtc directly.
12977 */
12978 if (dev_priv->display.modeset_calc_cdclk) {
12979 unsigned int cdclk;
12980
12981 ret = dev_priv->display.modeset_calc_cdclk(state);
12982
12983 cdclk = to_intel_atomic_state(state)->cdclk;
12984 if (!ret && cdclk != dev_priv->cdclk_freq)
12985 ret = intel_modeset_all_pipes(state);
12986
12987 if (ret < 0)
12988 return ret;
12989 } else
12990 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12991
12992 intel_modeset_clear_plls(state);
12993
12994 if (IS_HASWELL(dev))
12995 return haswell_mode_set_planes_workaround(state);
12996
12997 return 0;
12998 }
12999
13000 /**
13001 * intel_atomic_check - validate state object
13002 * @dev: drm device
13003 * @state: state to validate
13004 */
13005 static int intel_atomic_check(struct drm_device *dev,
13006 struct drm_atomic_state *state)
13007 {
13008 struct drm_crtc *crtc;
13009 struct drm_crtc_state *crtc_state;
13010 int ret, i;
13011 bool any_ms = false;
13012
13013 ret = drm_atomic_helper_check_modeset(dev, state);
13014 if (ret)
13015 return ret;
13016
13017 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13018 struct intel_crtc_state *pipe_config =
13019 to_intel_crtc_state(crtc_state);
13020
13021 /* Catch I915_MODE_FLAG_INHERITED */
13022 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13023 crtc_state->mode_changed = true;
13024
13025 if (!crtc_state->enable) {
13026 if (needs_modeset(crtc_state))
13027 any_ms = true;
13028 continue;
13029 }
13030
13031 if (!needs_modeset(crtc_state))
13032 continue;
13033
13034 /* FIXME: For only active_changed we shouldn't need to do any
13035 * state recomputation at all. */
13036
13037 ret = drm_atomic_add_affected_connectors(state, crtc);
13038 if (ret)
13039 return ret;
13040
13041 ret = intel_modeset_pipe_config(crtc, pipe_config);
13042 if (ret)
13043 return ret;
13044
13045 if (intel_pipe_config_compare(state->dev,
13046 to_intel_crtc_state(crtc->state),
13047 pipe_config, true)) {
13048 crtc_state->mode_changed = false;
13049 to_intel_crtc_state(crtc_state)->update_pipe = true;
13050 }
13051
13052 if (needs_modeset(crtc_state)) {
13053 any_ms = true;
13054
13055 ret = drm_atomic_add_affected_planes(state, crtc);
13056 if (ret)
13057 return ret;
13058 }
13059
13060 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13061 needs_modeset(crtc_state) ?
13062 "[modeset]" : "[fastset]");
13063 }
13064
13065 if (any_ms) {
13066 ret = intel_modeset_checks(state);
13067
13068 if (ret)
13069 return ret;
13070 } else
13071 to_intel_atomic_state(state)->cdclk =
13072 to_i915(state->dev)->cdclk_freq;
13073
13074 return drm_atomic_helper_check_planes(state->dev, state);
13075 }
13076
13077 /**
13078 * intel_atomic_commit - commit validated state object
13079 * @dev: DRM device
13080 * @state: the top-level driver state object
13081 * @async: asynchronous commit
13082 *
13083 * This function commits a top-level state object that has been validated
13084 * with drm_atomic_helper_check().
13085 *
13086 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13087 * we can only handle plane-related operations and do not yet support
13088 * asynchronous commit.
13089 *
13090 * RETURNS
13091 * Zero for success or -errno.
13092 */
13093 static int intel_atomic_commit(struct drm_device *dev,
13094 struct drm_atomic_state *state,
13095 bool async)
13096 {
13097 struct drm_i915_private *dev_priv = dev->dev_private;
13098 struct drm_crtc *crtc;
13099 struct drm_crtc_state *crtc_state;
13100 int ret = 0;
13101 int i;
13102 bool any_ms = false;
13103
13104 if (async) {
13105 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13106 return -EINVAL;
13107 }
13108
13109 ret = drm_atomic_helper_prepare_planes(dev, state);
13110 if (ret)
13111 return ret;
13112
13113 drm_atomic_helper_swap_state(dev, state);
13114
13115 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13117
13118 if (!needs_modeset(crtc->state))
13119 continue;
13120
13121 any_ms = true;
13122 intel_pre_plane_update(intel_crtc);
13123
13124 if (crtc_state->active) {
13125 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13126 dev_priv->display.crtc_disable(crtc);
13127 intel_crtc->active = false;
13128 intel_disable_shared_dpll(intel_crtc);
13129 }
13130 }
13131
13132 /* Only after disabling all output pipelines that will be changed can we
13133 * update the the output configuration. */
13134 intel_modeset_update_crtc_state(state);
13135
13136 if (any_ms) {
13137 intel_shared_dpll_commit(state);
13138
13139 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13140 modeset_update_crtc_power_domains(state);
13141 }
13142
13143 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13144 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13146 bool modeset = needs_modeset(crtc->state);
13147 bool update_pipe = !modeset &&
13148 to_intel_crtc_state(crtc->state)->update_pipe;
13149 unsigned long put_domains = 0;
13150
13151 if (modeset && crtc->state->active) {
13152 update_scanline_offset(to_intel_crtc(crtc));
13153 dev_priv->display.crtc_enable(crtc);
13154 }
13155
13156 if (update_pipe) {
13157 put_domains = modeset_get_crtc_power_domains(crtc);
13158
13159 /* make sure intel_modeset_check_state runs */
13160 any_ms = true;
13161 }
13162
13163 if (!modeset)
13164 intel_pre_plane_update(intel_crtc);
13165
13166 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13167
13168 if (put_domains)
13169 modeset_put_power_domains(dev_priv, put_domains);
13170
13171 intel_post_plane_update(intel_crtc);
13172 }
13173
13174 /* FIXME: add subpixel order */
13175
13176 drm_atomic_helper_wait_for_vblanks(dev, state);
13177 drm_atomic_helper_cleanup_planes(dev, state);
13178
13179 if (any_ms)
13180 intel_modeset_check_state(dev, state);
13181
13182 drm_atomic_state_free(state);
13183
13184 return 0;
13185 }
13186
13187 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13188 {
13189 struct drm_device *dev = crtc->dev;
13190 struct drm_atomic_state *state;
13191 struct drm_crtc_state *crtc_state;
13192 int ret;
13193
13194 state = drm_atomic_state_alloc(dev);
13195 if (!state) {
13196 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13197 crtc->base.id);
13198 return;
13199 }
13200
13201 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13202
13203 retry:
13204 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13205 ret = PTR_ERR_OR_ZERO(crtc_state);
13206 if (!ret) {
13207 if (!crtc_state->active)
13208 goto out;
13209
13210 crtc_state->mode_changed = true;
13211 ret = drm_atomic_commit(state);
13212 }
13213
13214 if (ret == -EDEADLK) {
13215 drm_atomic_state_clear(state);
13216 drm_modeset_backoff(state->acquire_ctx);
13217 goto retry;
13218 }
13219
13220 if (ret)
13221 out:
13222 drm_atomic_state_free(state);
13223 }
13224
13225 #undef for_each_intel_crtc_masked
13226
13227 static const struct drm_crtc_funcs intel_crtc_funcs = {
13228 .gamma_set = intel_crtc_gamma_set,
13229 .set_config = drm_atomic_helper_set_config,
13230 .destroy = intel_crtc_destroy,
13231 .page_flip = intel_crtc_page_flip,
13232 .atomic_duplicate_state = intel_crtc_duplicate_state,
13233 .atomic_destroy_state = intel_crtc_destroy_state,
13234 };
13235
13236 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13237 struct intel_shared_dpll *pll,
13238 struct intel_dpll_hw_state *hw_state)
13239 {
13240 uint32_t val;
13241
13242 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13243 return false;
13244
13245 val = I915_READ(PCH_DPLL(pll->id));
13246 hw_state->dpll = val;
13247 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13248 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13249
13250 return val & DPLL_VCO_ENABLE;
13251 }
13252
13253 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13254 struct intel_shared_dpll *pll)
13255 {
13256 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13257 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13258 }
13259
13260 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13261 struct intel_shared_dpll *pll)
13262 {
13263 /* PCH refclock must be enabled first */
13264 ibx_assert_pch_refclk_enabled(dev_priv);
13265
13266 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13267
13268 /* Wait for the clocks to stabilize. */
13269 POSTING_READ(PCH_DPLL(pll->id));
13270 udelay(150);
13271
13272 /* The pixel multiplier can only be updated once the
13273 * DPLL is enabled and the clocks are stable.
13274 *
13275 * So write it again.
13276 */
13277 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13278 POSTING_READ(PCH_DPLL(pll->id));
13279 udelay(200);
13280 }
13281
13282 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13283 struct intel_shared_dpll *pll)
13284 {
13285 struct drm_device *dev = dev_priv->dev;
13286 struct intel_crtc *crtc;
13287
13288 /* Make sure no transcoder isn't still depending on us. */
13289 for_each_intel_crtc(dev, crtc) {
13290 if (intel_crtc_to_shared_dpll(crtc) == pll)
13291 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13292 }
13293
13294 I915_WRITE(PCH_DPLL(pll->id), 0);
13295 POSTING_READ(PCH_DPLL(pll->id));
13296 udelay(200);
13297 }
13298
13299 static char *ibx_pch_dpll_names[] = {
13300 "PCH DPLL A",
13301 "PCH DPLL B",
13302 };
13303
13304 static void ibx_pch_dpll_init(struct drm_device *dev)
13305 {
13306 struct drm_i915_private *dev_priv = dev->dev_private;
13307 int i;
13308
13309 dev_priv->num_shared_dpll = 2;
13310
13311 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13312 dev_priv->shared_dplls[i].id = i;
13313 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13314 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13315 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13316 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13317 dev_priv->shared_dplls[i].get_hw_state =
13318 ibx_pch_dpll_get_hw_state;
13319 }
13320 }
13321
13322 static void intel_shared_dpll_init(struct drm_device *dev)
13323 {
13324 struct drm_i915_private *dev_priv = dev->dev_private;
13325
13326 intel_update_cdclk(dev);
13327
13328 if (HAS_DDI(dev))
13329 intel_ddi_pll_init(dev);
13330 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13331 ibx_pch_dpll_init(dev);
13332 else
13333 dev_priv->num_shared_dpll = 0;
13334
13335 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13336 }
13337
13338 /**
13339 * intel_prepare_plane_fb - Prepare fb for usage on plane
13340 * @plane: drm plane to prepare for
13341 * @fb: framebuffer to prepare for presentation
13342 *
13343 * Prepares a framebuffer for usage on a display plane. Generally this
13344 * involves pinning the underlying object and updating the frontbuffer tracking
13345 * bits. Some older platforms need special physical address handling for
13346 * cursor planes.
13347 *
13348 * Returns 0 on success, negative error code on failure.
13349 */
13350 int
13351 intel_prepare_plane_fb(struct drm_plane *plane,
13352 const struct drm_plane_state *new_state)
13353 {
13354 struct drm_device *dev = plane->dev;
13355 struct drm_framebuffer *fb = new_state->fb;
13356 struct intel_plane *intel_plane = to_intel_plane(plane);
13357 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13358 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13359 int ret = 0;
13360
13361 if (!obj)
13362 return 0;
13363
13364 mutex_lock(&dev->struct_mutex);
13365
13366 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13367 INTEL_INFO(dev)->cursor_needs_physical) {
13368 int align = IS_I830(dev) ? 16 * 1024 : 256;
13369 ret = i915_gem_object_attach_phys(obj, align);
13370 if (ret)
13371 DRM_DEBUG_KMS("failed to attach phys object\n");
13372 } else {
13373 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13374 }
13375
13376 if (ret == 0)
13377 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13378
13379 mutex_unlock(&dev->struct_mutex);
13380
13381 return ret;
13382 }
13383
13384 /**
13385 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13386 * @plane: drm plane to clean up for
13387 * @fb: old framebuffer that was on plane
13388 *
13389 * Cleans up a framebuffer that has just been removed from a plane.
13390 */
13391 void
13392 intel_cleanup_plane_fb(struct drm_plane *plane,
13393 const struct drm_plane_state *old_state)
13394 {
13395 struct drm_device *dev = plane->dev;
13396 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13397
13398 if (!obj)
13399 return;
13400
13401 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13402 !INTEL_INFO(dev)->cursor_needs_physical) {
13403 mutex_lock(&dev->struct_mutex);
13404 intel_unpin_fb_obj(old_state->fb, old_state);
13405 mutex_unlock(&dev->struct_mutex);
13406 }
13407 }
13408
13409 int
13410 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13411 {
13412 int max_scale;
13413 struct drm_device *dev;
13414 struct drm_i915_private *dev_priv;
13415 int crtc_clock, cdclk;
13416
13417 if (!intel_crtc || !crtc_state)
13418 return DRM_PLANE_HELPER_NO_SCALING;
13419
13420 dev = intel_crtc->base.dev;
13421 dev_priv = dev->dev_private;
13422 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13423 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13424
13425 if (!crtc_clock || !cdclk)
13426 return DRM_PLANE_HELPER_NO_SCALING;
13427
13428 /*
13429 * skl max scale is lower of:
13430 * close to 3 but not 3, -1 is for that purpose
13431 * or
13432 * cdclk/crtc_clock
13433 */
13434 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13435
13436 return max_scale;
13437 }
13438
13439 static int
13440 intel_check_primary_plane(struct drm_plane *plane,
13441 struct intel_crtc_state *crtc_state,
13442 struct intel_plane_state *state)
13443 {
13444 struct drm_crtc *crtc = state->base.crtc;
13445 struct drm_framebuffer *fb = state->base.fb;
13446 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13447 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13448 bool can_position = false;
13449
13450 /* use scaler when colorkey is not required */
13451 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13452 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13453 min_scale = 1;
13454 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13455 can_position = true;
13456 }
13457
13458 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13459 &state->dst, &state->clip,
13460 min_scale, max_scale,
13461 can_position, true,
13462 &state->visible);
13463 }
13464
13465 static void
13466 intel_commit_primary_plane(struct drm_plane *plane,
13467 struct intel_plane_state *state)
13468 {
13469 struct drm_crtc *crtc = state->base.crtc;
13470 struct drm_framebuffer *fb = state->base.fb;
13471 struct drm_device *dev = plane->dev;
13472 struct drm_i915_private *dev_priv = dev->dev_private;
13473 struct intel_crtc *intel_crtc;
13474 struct drm_rect *src = &state->src;
13475
13476 crtc = crtc ? crtc : plane->crtc;
13477 intel_crtc = to_intel_crtc(crtc);
13478
13479 plane->fb = fb;
13480 crtc->x = src->x1 >> 16;
13481 crtc->y = src->y1 >> 16;
13482
13483 if (!crtc->state->active)
13484 return;
13485
13486 dev_priv->display.update_primary_plane(crtc, fb,
13487 state->src.x1 >> 16,
13488 state->src.y1 >> 16);
13489 }
13490
13491 static void
13492 intel_disable_primary_plane(struct drm_plane *plane,
13493 struct drm_crtc *crtc)
13494 {
13495 struct drm_device *dev = plane->dev;
13496 struct drm_i915_private *dev_priv = dev->dev_private;
13497
13498 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13499 }
13500
13501 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13502 struct drm_crtc_state *old_crtc_state)
13503 {
13504 struct drm_device *dev = crtc->dev;
13505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13506 struct intel_crtc_state *old_intel_state =
13507 to_intel_crtc_state(old_crtc_state);
13508 bool modeset = needs_modeset(crtc->state);
13509
13510 if (intel_crtc->atomic.update_wm_pre)
13511 intel_update_watermarks(crtc);
13512
13513 /* Perform vblank evasion around commit operation */
13514 if (crtc->state->active)
13515 intel_pipe_update_start(intel_crtc);
13516
13517 if (modeset)
13518 return;
13519
13520 if (to_intel_crtc_state(crtc->state)->update_pipe)
13521 intel_update_pipe_config(intel_crtc, old_intel_state);
13522 else if (INTEL_INFO(dev)->gen >= 9)
13523 skl_detach_scalers(intel_crtc);
13524 }
13525
13526 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13527 struct drm_crtc_state *old_crtc_state)
13528 {
13529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13530
13531 if (crtc->state->active)
13532 intel_pipe_update_end(intel_crtc);
13533 }
13534
13535 /**
13536 * intel_plane_destroy - destroy a plane
13537 * @plane: plane to destroy
13538 *
13539 * Common destruction function for all types of planes (primary, cursor,
13540 * sprite).
13541 */
13542 void intel_plane_destroy(struct drm_plane *plane)
13543 {
13544 struct intel_plane *intel_plane = to_intel_plane(plane);
13545 drm_plane_cleanup(plane);
13546 kfree(intel_plane);
13547 }
13548
13549 const struct drm_plane_funcs intel_plane_funcs = {
13550 .update_plane = drm_atomic_helper_update_plane,
13551 .disable_plane = drm_atomic_helper_disable_plane,
13552 .destroy = intel_plane_destroy,
13553 .set_property = drm_atomic_helper_plane_set_property,
13554 .atomic_get_property = intel_plane_atomic_get_property,
13555 .atomic_set_property = intel_plane_atomic_set_property,
13556 .atomic_duplicate_state = intel_plane_duplicate_state,
13557 .atomic_destroy_state = intel_plane_destroy_state,
13558
13559 };
13560
13561 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13562 int pipe)
13563 {
13564 struct intel_plane *primary;
13565 struct intel_plane_state *state;
13566 const uint32_t *intel_primary_formats;
13567 unsigned int num_formats;
13568
13569 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13570 if (primary == NULL)
13571 return NULL;
13572
13573 state = intel_create_plane_state(&primary->base);
13574 if (!state) {
13575 kfree(primary);
13576 return NULL;
13577 }
13578 primary->base.state = &state->base;
13579
13580 primary->can_scale = false;
13581 primary->max_downscale = 1;
13582 if (INTEL_INFO(dev)->gen >= 9) {
13583 primary->can_scale = true;
13584 state->scaler_id = -1;
13585 }
13586 primary->pipe = pipe;
13587 primary->plane = pipe;
13588 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13589 primary->check_plane = intel_check_primary_plane;
13590 primary->commit_plane = intel_commit_primary_plane;
13591 primary->disable_plane = intel_disable_primary_plane;
13592 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13593 primary->plane = !pipe;
13594
13595 if (INTEL_INFO(dev)->gen >= 9) {
13596 intel_primary_formats = skl_primary_formats;
13597 num_formats = ARRAY_SIZE(skl_primary_formats);
13598 } else if (INTEL_INFO(dev)->gen >= 4) {
13599 intel_primary_formats = i965_primary_formats;
13600 num_formats = ARRAY_SIZE(i965_primary_formats);
13601 } else {
13602 intel_primary_formats = i8xx_primary_formats;
13603 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13604 }
13605
13606 drm_universal_plane_init(dev, &primary->base, 0,
13607 &intel_plane_funcs,
13608 intel_primary_formats, num_formats,
13609 DRM_PLANE_TYPE_PRIMARY);
13610
13611 if (INTEL_INFO(dev)->gen >= 4)
13612 intel_create_rotation_property(dev, primary);
13613
13614 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13615
13616 return &primary->base;
13617 }
13618
13619 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13620 {
13621 if (!dev->mode_config.rotation_property) {
13622 unsigned long flags = BIT(DRM_ROTATE_0) |
13623 BIT(DRM_ROTATE_180);
13624
13625 if (INTEL_INFO(dev)->gen >= 9)
13626 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13627
13628 dev->mode_config.rotation_property =
13629 drm_mode_create_rotation_property(dev, flags);
13630 }
13631 if (dev->mode_config.rotation_property)
13632 drm_object_attach_property(&plane->base.base,
13633 dev->mode_config.rotation_property,
13634 plane->base.state->rotation);
13635 }
13636
13637 static int
13638 intel_check_cursor_plane(struct drm_plane *plane,
13639 struct intel_crtc_state *crtc_state,
13640 struct intel_plane_state *state)
13641 {
13642 struct drm_crtc *crtc = crtc_state->base.crtc;
13643 struct drm_framebuffer *fb = state->base.fb;
13644 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13645 unsigned stride;
13646 int ret;
13647
13648 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13649 &state->dst, &state->clip,
13650 DRM_PLANE_HELPER_NO_SCALING,
13651 DRM_PLANE_HELPER_NO_SCALING,
13652 true, true, &state->visible);
13653 if (ret)
13654 return ret;
13655
13656 /* if we want to turn off the cursor ignore width and height */
13657 if (!obj)
13658 return 0;
13659
13660 /* Check for which cursor types we support */
13661 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13662 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13663 state->base.crtc_w, state->base.crtc_h);
13664 return -EINVAL;
13665 }
13666
13667 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13668 if (obj->base.size < stride * state->base.crtc_h) {
13669 DRM_DEBUG_KMS("buffer is too small\n");
13670 return -ENOMEM;
13671 }
13672
13673 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13674 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13675 return -EINVAL;
13676 }
13677
13678 return 0;
13679 }
13680
13681 static void
13682 intel_disable_cursor_plane(struct drm_plane *plane,
13683 struct drm_crtc *crtc)
13684 {
13685 intel_crtc_update_cursor(crtc, false);
13686 }
13687
13688 static void
13689 intel_commit_cursor_plane(struct drm_plane *plane,
13690 struct intel_plane_state *state)
13691 {
13692 struct drm_crtc *crtc = state->base.crtc;
13693 struct drm_device *dev = plane->dev;
13694 struct intel_crtc *intel_crtc;
13695 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13696 uint32_t addr;
13697
13698 crtc = crtc ? crtc : plane->crtc;
13699 intel_crtc = to_intel_crtc(crtc);
13700
13701 if (intel_crtc->cursor_bo == obj)
13702 goto update;
13703
13704 if (!obj)
13705 addr = 0;
13706 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13707 addr = i915_gem_obj_ggtt_offset(obj);
13708 else
13709 addr = obj->phys_handle->busaddr;
13710
13711 intel_crtc->cursor_addr = addr;
13712 intel_crtc->cursor_bo = obj;
13713
13714 update:
13715 if (crtc->state->active)
13716 intel_crtc_update_cursor(crtc, state->visible);
13717 }
13718
13719 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13720 int pipe)
13721 {
13722 struct intel_plane *cursor;
13723 struct intel_plane_state *state;
13724
13725 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13726 if (cursor == NULL)
13727 return NULL;
13728
13729 state = intel_create_plane_state(&cursor->base);
13730 if (!state) {
13731 kfree(cursor);
13732 return NULL;
13733 }
13734 cursor->base.state = &state->base;
13735
13736 cursor->can_scale = false;
13737 cursor->max_downscale = 1;
13738 cursor->pipe = pipe;
13739 cursor->plane = pipe;
13740 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13741 cursor->check_plane = intel_check_cursor_plane;
13742 cursor->commit_plane = intel_commit_cursor_plane;
13743 cursor->disable_plane = intel_disable_cursor_plane;
13744
13745 drm_universal_plane_init(dev, &cursor->base, 0,
13746 &intel_plane_funcs,
13747 intel_cursor_formats,
13748 ARRAY_SIZE(intel_cursor_formats),
13749 DRM_PLANE_TYPE_CURSOR);
13750
13751 if (INTEL_INFO(dev)->gen >= 4) {
13752 if (!dev->mode_config.rotation_property)
13753 dev->mode_config.rotation_property =
13754 drm_mode_create_rotation_property(dev,
13755 BIT(DRM_ROTATE_0) |
13756 BIT(DRM_ROTATE_180));
13757 if (dev->mode_config.rotation_property)
13758 drm_object_attach_property(&cursor->base.base,
13759 dev->mode_config.rotation_property,
13760 state->base.rotation);
13761 }
13762
13763 if (INTEL_INFO(dev)->gen >=9)
13764 state->scaler_id = -1;
13765
13766 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13767
13768 return &cursor->base;
13769 }
13770
13771 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13772 struct intel_crtc_state *crtc_state)
13773 {
13774 int i;
13775 struct intel_scaler *intel_scaler;
13776 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13777
13778 for (i = 0; i < intel_crtc->num_scalers; i++) {
13779 intel_scaler = &scaler_state->scalers[i];
13780 intel_scaler->in_use = 0;
13781 intel_scaler->mode = PS_SCALER_MODE_DYN;
13782 }
13783
13784 scaler_state->scaler_id = -1;
13785 }
13786
13787 static void intel_crtc_init(struct drm_device *dev, int pipe)
13788 {
13789 struct drm_i915_private *dev_priv = dev->dev_private;
13790 struct intel_crtc *intel_crtc;
13791 struct intel_crtc_state *crtc_state = NULL;
13792 struct drm_plane *primary = NULL;
13793 struct drm_plane *cursor = NULL;
13794 int i, ret;
13795
13796 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13797 if (intel_crtc == NULL)
13798 return;
13799
13800 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13801 if (!crtc_state)
13802 goto fail;
13803 intel_crtc->config = crtc_state;
13804 intel_crtc->base.state = &crtc_state->base;
13805 crtc_state->base.crtc = &intel_crtc->base;
13806
13807 /* initialize shared scalers */
13808 if (INTEL_INFO(dev)->gen >= 9) {
13809 if (pipe == PIPE_C)
13810 intel_crtc->num_scalers = 1;
13811 else
13812 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13813
13814 skl_init_scalers(dev, intel_crtc, crtc_state);
13815 }
13816
13817 primary = intel_primary_plane_create(dev, pipe);
13818 if (!primary)
13819 goto fail;
13820
13821 cursor = intel_cursor_plane_create(dev, pipe);
13822 if (!cursor)
13823 goto fail;
13824
13825 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13826 cursor, &intel_crtc_funcs);
13827 if (ret)
13828 goto fail;
13829
13830 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13831 for (i = 0; i < 256; i++) {
13832 intel_crtc->lut_r[i] = i;
13833 intel_crtc->lut_g[i] = i;
13834 intel_crtc->lut_b[i] = i;
13835 }
13836
13837 /*
13838 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13839 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13840 */
13841 intel_crtc->pipe = pipe;
13842 intel_crtc->plane = pipe;
13843 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13844 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13845 intel_crtc->plane = !pipe;
13846 }
13847
13848 intel_crtc->cursor_base = ~0;
13849 intel_crtc->cursor_cntl = ~0;
13850 intel_crtc->cursor_size = ~0;
13851
13852 intel_crtc->wm.cxsr_allowed = true;
13853
13854 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13855 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13856 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13857 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13858
13859 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13860
13861 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13862 return;
13863
13864 fail:
13865 if (primary)
13866 drm_plane_cleanup(primary);
13867 if (cursor)
13868 drm_plane_cleanup(cursor);
13869 kfree(crtc_state);
13870 kfree(intel_crtc);
13871 }
13872
13873 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13874 {
13875 struct drm_encoder *encoder = connector->base.encoder;
13876 struct drm_device *dev = connector->base.dev;
13877
13878 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13879
13880 if (!encoder || WARN_ON(!encoder->crtc))
13881 return INVALID_PIPE;
13882
13883 return to_intel_crtc(encoder->crtc)->pipe;
13884 }
13885
13886 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13887 struct drm_file *file)
13888 {
13889 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13890 struct drm_crtc *drmmode_crtc;
13891 struct intel_crtc *crtc;
13892
13893 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13894
13895 if (!drmmode_crtc) {
13896 DRM_ERROR("no such CRTC id\n");
13897 return -ENOENT;
13898 }
13899
13900 crtc = to_intel_crtc(drmmode_crtc);
13901 pipe_from_crtc_id->pipe = crtc->pipe;
13902
13903 return 0;
13904 }
13905
13906 static int intel_encoder_clones(struct intel_encoder *encoder)
13907 {
13908 struct drm_device *dev = encoder->base.dev;
13909 struct intel_encoder *source_encoder;
13910 int index_mask = 0;
13911 int entry = 0;
13912
13913 for_each_intel_encoder(dev, source_encoder) {
13914 if (encoders_cloneable(encoder, source_encoder))
13915 index_mask |= (1 << entry);
13916
13917 entry++;
13918 }
13919
13920 return index_mask;
13921 }
13922
13923 static bool has_edp_a(struct drm_device *dev)
13924 {
13925 struct drm_i915_private *dev_priv = dev->dev_private;
13926
13927 if (!IS_MOBILE(dev))
13928 return false;
13929
13930 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13931 return false;
13932
13933 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13934 return false;
13935
13936 return true;
13937 }
13938
13939 static bool intel_crt_present(struct drm_device *dev)
13940 {
13941 struct drm_i915_private *dev_priv = dev->dev_private;
13942
13943 if (INTEL_INFO(dev)->gen >= 9)
13944 return false;
13945
13946 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13947 return false;
13948
13949 if (IS_CHERRYVIEW(dev))
13950 return false;
13951
13952 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13953 return false;
13954
13955 return true;
13956 }
13957
13958 static void intel_setup_outputs(struct drm_device *dev)
13959 {
13960 struct drm_i915_private *dev_priv = dev->dev_private;
13961 struct intel_encoder *encoder;
13962 bool dpd_is_edp = false;
13963
13964 intel_lvds_init(dev);
13965
13966 if (intel_crt_present(dev))
13967 intel_crt_init(dev);
13968
13969 if (IS_BROXTON(dev)) {
13970 /*
13971 * FIXME: Broxton doesn't support port detection via the
13972 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13973 * detect the ports.
13974 */
13975 intel_ddi_init(dev, PORT_A);
13976 intel_ddi_init(dev, PORT_B);
13977 intel_ddi_init(dev, PORT_C);
13978 } else if (HAS_DDI(dev)) {
13979 int found;
13980
13981 /*
13982 * Haswell uses DDI functions to detect digital outputs.
13983 * On SKL pre-D0 the strap isn't connected, so we assume
13984 * it's there.
13985 */
13986 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13987 /* WaIgnoreDDIAStrap: skl */
13988 if (found || IS_SKYLAKE(dev))
13989 intel_ddi_init(dev, PORT_A);
13990
13991 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13992 * register */
13993 found = I915_READ(SFUSE_STRAP);
13994
13995 if (found & SFUSE_STRAP_DDIB_DETECTED)
13996 intel_ddi_init(dev, PORT_B);
13997 if (found & SFUSE_STRAP_DDIC_DETECTED)
13998 intel_ddi_init(dev, PORT_C);
13999 if (found & SFUSE_STRAP_DDID_DETECTED)
14000 intel_ddi_init(dev, PORT_D);
14001 /*
14002 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14003 */
14004 if (IS_SKYLAKE(dev) &&
14005 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14006 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14007 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14008 intel_ddi_init(dev, PORT_E);
14009
14010 } else if (HAS_PCH_SPLIT(dev)) {
14011 int found;
14012 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14013
14014 if (has_edp_a(dev))
14015 intel_dp_init(dev, DP_A, PORT_A);
14016
14017 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14018 /* PCH SDVOB multiplex with HDMIB */
14019 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14020 if (!found)
14021 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14022 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14023 intel_dp_init(dev, PCH_DP_B, PORT_B);
14024 }
14025
14026 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14027 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14028
14029 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14030 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14031
14032 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14033 intel_dp_init(dev, PCH_DP_C, PORT_C);
14034
14035 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14036 intel_dp_init(dev, PCH_DP_D, PORT_D);
14037 } else if (IS_VALLEYVIEW(dev)) {
14038 /*
14039 * The DP_DETECTED bit is the latched state of the DDC
14040 * SDA pin at boot. However since eDP doesn't require DDC
14041 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14042 * eDP ports may have been muxed to an alternate function.
14043 * Thus we can't rely on the DP_DETECTED bit alone to detect
14044 * eDP ports. Consult the VBT as well as DP_DETECTED to
14045 * detect eDP ports.
14046 */
14047 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14048 !intel_dp_is_edp(dev, PORT_B))
14049 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14050 PORT_B);
14051 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14052 intel_dp_is_edp(dev, PORT_B))
14053 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14054
14055 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14056 !intel_dp_is_edp(dev, PORT_C))
14057 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14058 PORT_C);
14059 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14060 intel_dp_is_edp(dev, PORT_C))
14061 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14062
14063 if (IS_CHERRYVIEW(dev)) {
14064 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14065 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14066 PORT_D);
14067 /* eDP not supported on port D, so don't check VBT */
14068 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14069 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14070 }
14071
14072 intel_dsi_init(dev);
14073 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14074 bool found = false;
14075
14076 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14077 DRM_DEBUG_KMS("probing SDVOB\n");
14078 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14079 if (!found && IS_G4X(dev)) {
14080 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14081 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14082 }
14083
14084 if (!found && IS_G4X(dev))
14085 intel_dp_init(dev, DP_B, PORT_B);
14086 }
14087
14088 /* Before G4X SDVOC doesn't have its own detect register */
14089
14090 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14091 DRM_DEBUG_KMS("probing SDVOC\n");
14092 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14093 }
14094
14095 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14096
14097 if (IS_G4X(dev)) {
14098 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14099 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14100 }
14101 if (IS_G4X(dev))
14102 intel_dp_init(dev, DP_C, PORT_C);
14103 }
14104
14105 if (IS_G4X(dev) &&
14106 (I915_READ(DP_D) & DP_DETECTED))
14107 intel_dp_init(dev, DP_D, PORT_D);
14108 } else if (IS_GEN2(dev))
14109 intel_dvo_init(dev);
14110
14111 if (SUPPORTS_TV(dev))
14112 intel_tv_init(dev);
14113
14114 intel_psr_init(dev);
14115
14116 for_each_intel_encoder(dev, encoder) {
14117 encoder->base.possible_crtcs = encoder->crtc_mask;
14118 encoder->base.possible_clones =
14119 intel_encoder_clones(encoder);
14120 }
14121
14122 intel_init_pch_refclk(dev);
14123
14124 drm_helper_move_panel_connectors_to_head(dev);
14125 }
14126
14127 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14128 {
14129 struct drm_device *dev = fb->dev;
14130 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14131
14132 drm_framebuffer_cleanup(fb);
14133 mutex_lock(&dev->struct_mutex);
14134 WARN_ON(!intel_fb->obj->framebuffer_references--);
14135 drm_gem_object_unreference(&intel_fb->obj->base);
14136 mutex_unlock(&dev->struct_mutex);
14137 kfree(intel_fb);
14138 }
14139
14140 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14141 struct drm_file *file,
14142 unsigned int *handle)
14143 {
14144 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14145 struct drm_i915_gem_object *obj = intel_fb->obj;
14146
14147 return drm_gem_handle_create(file, &obj->base, handle);
14148 }
14149
14150 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14151 struct drm_file *file,
14152 unsigned flags, unsigned color,
14153 struct drm_clip_rect *clips,
14154 unsigned num_clips)
14155 {
14156 struct drm_device *dev = fb->dev;
14157 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14158 struct drm_i915_gem_object *obj = intel_fb->obj;
14159
14160 mutex_lock(&dev->struct_mutex);
14161 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14162 mutex_unlock(&dev->struct_mutex);
14163
14164 return 0;
14165 }
14166
14167 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14168 .destroy = intel_user_framebuffer_destroy,
14169 .create_handle = intel_user_framebuffer_create_handle,
14170 .dirty = intel_user_framebuffer_dirty,
14171 };
14172
14173 static
14174 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14175 uint32_t pixel_format)
14176 {
14177 u32 gen = INTEL_INFO(dev)->gen;
14178
14179 if (gen >= 9) {
14180 /* "The stride in bytes must not exceed the of the size of 8K
14181 * pixels and 32K bytes."
14182 */
14183 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14184 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14185 return 32*1024;
14186 } else if (gen >= 4) {
14187 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14188 return 16*1024;
14189 else
14190 return 32*1024;
14191 } else if (gen >= 3) {
14192 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14193 return 8*1024;
14194 else
14195 return 16*1024;
14196 } else {
14197 /* XXX DSPC is limited to 4k tiled */
14198 return 8*1024;
14199 }
14200 }
14201
14202 static int intel_framebuffer_init(struct drm_device *dev,
14203 struct intel_framebuffer *intel_fb,
14204 struct drm_mode_fb_cmd2 *mode_cmd,
14205 struct drm_i915_gem_object *obj)
14206 {
14207 unsigned int aligned_height;
14208 int ret;
14209 u32 pitch_limit, stride_alignment;
14210
14211 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14212
14213 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14214 /* Enforce that fb modifier and tiling mode match, but only for
14215 * X-tiled. This is needed for FBC. */
14216 if (!!(obj->tiling_mode == I915_TILING_X) !=
14217 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14218 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14219 return -EINVAL;
14220 }
14221 } else {
14222 if (obj->tiling_mode == I915_TILING_X)
14223 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14224 else if (obj->tiling_mode == I915_TILING_Y) {
14225 DRM_DEBUG("No Y tiling for legacy addfb\n");
14226 return -EINVAL;
14227 }
14228 }
14229
14230 /* Passed in modifier sanity checking. */
14231 switch (mode_cmd->modifier[0]) {
14232 case I915_FORMAT_MOD_Y_TILED:
14233 case I915_FORMAT_MOD_Yf_TILED:
14234 if (INTEL_INFO(dev)->gen < 9) {
14235 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14236 mode_cmd->modifier[0]);
14237 return -EINVAL;
14238 }
14239 case DRM_FORMAT_MOD_NONE:
14240 case I915_FORMAT_MOD_X_TILED:
14241 break;
14242 default:
14243 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14244 mode_cmd->modifier[0]);
14245 return -EINVAL;
14246 }
14247
14248 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14249 mode_cmd->pixel_format);
14250 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14251 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14252 mode_cmd->pitches[0], stride_alignment);
14253 return -EINVAL;
14254 }
14255
14256 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14257 mode_cmd->pixel_format);
14258 if (mode_cmd->pitches[0] > pitch_limit) {
14259 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14260 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14261 "tiled" : "linear",
14262 mode_cmd->pitches[0], pitch_limit);
14263 return -EINVAL;
14264 }
14265
14266 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14267 mode_cmd->pitches[0] != obj->stride) {
14268 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14269 mode_cmd->pitches[0], obj->stride);
14270 return -EINVAL;
14271 }
14272
14273 /* Reject formats not supported by any plane early. */
14274 switch (mode_cmd->pixel_format) {
14275 case DRM_FORMAT_C8:
14276 case DRM_FORMAT_RGB565:
14277 case DRM_FORMAT_XRGB8888:
14278 case DRM_FORMAT_ARGB8888:
14279 break;
14280 case DRM_FORMAT_XRGB1555:
14281 if (INTEL_INFO(dev)->gen > 3) {
14282 DRM_DEBUG("unsupported pixel format: %s\n",
14283 drm_get_format_name(mode_cmd->pixel_format));
14284 return -EINVAL;
14285 }
14286 break;
14287 case DRM_FORMAT_ABGR8888:
14288 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14289 DRM_DEBUG("unsupported pixel format: %s\n",
14290 drm_get_format_name(mode_cmd->pixel_format));
14291 return -EINVAL;
14292 }
14293 break;
14294 case DRM_FORMAT_XBGR8888:
14295 case DRM_FORMAT_XRGB2101010:
14296 case DRM_FORMAT_XBGR2101010:
14297 if (INTEL_INFO(dev)->gen < 4) {
14298 DRM_DEBUG("unsupported pixel format: %s\n",
14299 drm_get_format_name(mode_cmd->pixel_format));
14300 return -EINVAL;
14301 }
14302 break;
14303 case DRM_FORMAT_ABGR2101010:
14304 if (!IS_VALLEYVIEW(dev)) {
14305 DRM_DEBUG("unsupported pixel format: %s\n",
14306 drm_get_format_name(mode_cmd->pixel_format));
14307 return -EINVAL;
14308 }
14309 break;
14310 case DRM_FORMAT_YUYV:
14311 case DRM_FORMAT_UYVY:
14312 case DRM_FORMAT_YVYU:
14313 case DRM_FORMAT_VYUY:
14314 if (INTEL_INFO(dev)->gen < 5) {
14315 DRM_DEBUG("unsupported pixel format: %s\n",
14316 drm_get_format_name(mode_cmd->pixel_format));
14317 return -EINVAL;
14318 }
14319 break;
14320 default:
14321 DRM_DEBUG("unsupported pixel format: %s\n",
14322 drm_get_format_name(mode_cmd->pixel_format));
14323 return -EINVAL;
14324 }
14325
14326 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14327 if (mode_cmd->offsets[0] != 0)
14328 return -EINVAL;
14329
14330 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14331 mode_cmd->pixel_format,
14332 mode_cmd->modifier[0]);
14333 /* FIXME drm helper for size checks (especially planar formats)? */
14334 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14335 return -EINVAL;
14336
14337 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14338 intel_fb->obj = obj;
14339 intel_fb->obj->framebuffer_references++;
14340
14341 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14342 if (ret) {
14343 DRM_ERROR("framebuffer init failed %d\n", ret);
14344 return ret;
14345 }
14346
14347 return 0;
14348 }
14349
14350 static struct drm_framebuffer *
14351 intel_user_framebuffer_create(struct drm_device *dev,
14352 struct drm_file *filp,
14353 struct drm_mode_fb_cmd2 *mode_cmd)
14354 {
14355 struct drm_i915_gem_object *obj;
14356
14357 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14358 mode_cmd->handles[0]));
14359 if (&obj->base == NULL)
14360 return ERR_PTR(-ENOENT);
14361
14362 return intel_framebuffer_create(dev, mode_cmd, obj);
14363 }
14364
14365 #ifndef CONFIG_DRM_FBDEV_EMULATION
14366 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14367 {
14368 }
14369 #endif
14370
14371 static const struct drm_mode_config_funcs intel_mode_funcs = {
14372 .fb_create = intel_user_framebuffer_create,
14373 .output_poll_changed = intel_fbdev_output_poll_changed,
14374 .atomic_check = intel_atomic_check,
14375 .atomic_commit = intel_atomic_commit,
14376 .atomic_state_alloc = intel_atomic_state_alloc,
14377 .atomic_state_clear = intel_atomic_state_clear,
14378 };
14379
14380 /* Set up chip specific display functions */
14381 static void intel_init_display(struct drm_device *dev)
14382 {
14383 struct drm_i915_private *dev_priv = dev->dev_private;
14384
14385 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14386 dev_priv->display.find_dpll = g4x_find_best_dpll;
14387 else if (IS_CHERRYVIEW(dev))
14388 dev_priv->display.find_dpll = chv_find_best_dpll;
14389 else if (IS_VALLEYVIEW(dev))
14390 dev_priv->display.find_dpll = vlv_find_best_dpll;
14391 else if (IS_PINEVIEW(dev))
14392 dev_priv->display.find_dpll = pnv_find_best_dpll;
14393 else
14394 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14395
14396 if (INTEL_INFO(dev)->gen >= 9) {
14397 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14398 dev_priv->display.get_initial_plane_config =
14399 skylake_get_initial_plane_config;
14400 dev_priv->display.crtc_compute_clock =
14401 haswell_crtc_compute_clock;
14402 dev_priv->display.crtc_enable = haswell_crtc_enable;
14403 dev_priv->display.crtc_disable = haswell_crtc_disable;
14404 dev_priv->display.update_primary_plane =
14405 skylake_update_primary_plane;
14406 } else if (HAS_DDI(dev)) {
14407 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14408 dev_priv->display.get_initial_plane_config =
14409 ironlake_get_initial_plane_config;
14410 dev_priv->display.crtc_compute_clock =
14411 haswell_crtc_compute_clock;
14412 dev_priv->display.crtc_enable = haswell_crtc_enable;
14413 dev_priv->display.crtc_disable = haswell_crtc_disable;
14414 dev_priv->display.update_primary_plane =
14415 ironlake_update_primary_plane;
14416 } else if (HAS_PCH_SPLIT(dev)) {
14417 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14418 dev_priv->display.get_initial_plane_config =
14419 ironlake_get_initial_plane_config;
14420 dev_priv->display.crtc_compute_clock =
14421 ironlake_crtc_compute_clock;
14422 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14423 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14424 dev_priv->display.update_primary_plane =
14425 ironlake_update_primary_plane;
14426 } else if (IS_VALLEYVIEW(dev)) {
14427 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14428 dev_priv->display.get_initial_plane_config =
14429 i9xx_get_initial_plane_config;
14430 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14431 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14432 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14433 dev_priv->display.update_primary_plane =
14434 i9xx_update_primary_plane;
14435 } else {
14436 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14437 dev_priv->display.get_initial_plane_config =
14438 i9xx_get_initial_plane_config;
14439 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14440 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14441 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14442 dev_priv->display.update_primary_plane =
14443 i9xx_update_primary_plane;
14444 }
14445
14446 /* Returns the core display clock speed */
14447 if (IS_SKYLAKE(dev))
14448 dev_priv->display.get_display_clock_speed =
14449 skylake_get_display_clock_speed;
14450 else if (IS_BROXTON(dev))
14451 dev_priv->display.get_display_clock_speed =
14452 broxton_get_display_clock_speed;
14453 else if (IS_BROADWELL(dev))
14454 dev_priv->display.get_display_clock_speed =
14455 broadwell_get_display_clock_speed;
14456 else if (IS_HASWELL(dev))
14457 dev_priv->display.get_display_clock_speed =
14458 haswell_get_display_clock_speed;
14459 else if (IS_VALLEYVIEW(dev))
14460 dev_priv->display.get_display_clock_speed =
14461 valleyview_get_display_clock_speed;
14462 else if (IS_GEN5(dev))
14463 dev_priv->display.get_display_clock_speed =
14464 ilk_get_display_clock_speed;
14465 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14466 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14467 dev_priv->display.get_display_clock_speed =
14468 i945_get_display_clock_speed;
14469 else if (IS_GM45(dev))
14470 dev_priv->display.get_display_clock_speed =
14471 gm45_get_display_clock_speed;
14472 else if (IS_CRESTLINE(dev))
14473 dev_priv->display.get_display_clock_speed =
14474 i965gm_get_display_clock_speed;
14475 else if (IS_PINEVIEW(dev))
14476 dev_priv->display.get_display_clock_speed =
14477 pnv_get_display_clock_speed;
14478 else if (IS_G33(dev) || IS_G4X(dev))
14479 dev_priv->display.get_display_clock_speed =
14480 g33_get_display_clock_speed;
14481 else if (IS_I915G(dev))
14482 dev_priv->display.get_display_clock_speed =
14483 i915_get_display_clock_speed;
14484 else if (IS_I945GM(dev) || IS_845G(dev))
14485 dev_priv->display.get_display_clock_speed =
14486 i9xx_misc_get_display_clock_speed;
14487 else if (IS_PINEVIEW(dev))
14488 dev_priv->display.get_display_clock_speed =
14489 pnv_get_display_clock_speed;
14490 else if (IS_I915GM(dev))
14491 dev_priv->display.get_display_clock_speed =
14492 i915gm_get_display_clock_speed;
14493 else if (IS_I865G(dev))
14494 dev_priv->display.get_display_clock_speed =
14495 i865_get_display_clock_speed;
14496 else if (IS_I85X(dev))
14497 dev_priv->display.get_display_clock_speed =
14498 i85x_get_display_clock_speed;
14499 else { /* 830 */
14500 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14501 dev_priv->display.get_display_clock_speed =
14502 i830_get_display_clock_speed;
14503 }
14504
14505 if (IS_GEN5(dev)) {
14506 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14507 } else if (IS_GEN6(dev)) {
14508 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14509 } else if (IS_IVYBRIDGE(dev)) {
14510 /* FIXME: detect B0+ stepping and use auto training */
14511 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14512 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14513 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14514 if (IS_BROADWELL(dev)) {
14515 dev_priv->display.modeset_commit_cdclk =
14516 broadwell_modeset_commit_cdclk;
14517 dev_priv->display.modeset_calc_cdclk =
14518 broadwell_modeset_calc_cdclk;
14519 }
14520 } else if (IS_VALLEYVIEW(dev)) {
14521 dev_priv->display.modeset_commit_cdclk =
14522 valleyview_modeset_commit_cdclk;
14523 dev_priv->display.modeset_calc_cdclk =
14524 valleyview_modeset_calc_cdclk;
14525 } else if (IS_BROXTON(dev)) {
14526 dev_priv->display.modeset_commit_cdclk =
14527 broxton_modeset_commit_cdclk;
14528 dev_priv->display.modeset_calc_cdclk =
14529 broxton_modeset_calc_cdclk;
14530 }
14531
14532 switch (INTEL_INFO(dev)->gen) {
14533 case 2:
14534 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14535 break;
14536
14537 case 3:
14538 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14539 break;
14540
14541 case 4:
14542 case 5:
14543 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14544 break;
14545
14546 case 6:
14547 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14548 break;
14549 case 7:
14550 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14551 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14552 break;
14553 case 9:
14554 /* Drop through - unsupported since execlist only. */
14555 default:
14556 /* Default just returns -ENODEV to indicate unsupported */
14557 dev_priv->display.queue_flip = intel_default_queue_flip;
14558 }
14559
14560 intel_panel_init_backlight_funcs(dev);
14561
14562 mutex_init(&dev_priv->pps_mutex);
14563 }
14564
14565 /*
14566 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14567 * resume, or other times. This quirk makes sure that's the case for
14568 * affected systems.
14569 */
14570 static void quirk_pipea_force(struct drm_device *dev)
14571 {
14572 struct drm_i915_private *dev_priv = dev->dev_private;
14573
14574 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14575 DRM_INFO("applying pipe a force quirk\n");
14576 }
14577
14578 static void quirk_pipeb_force(struct drm_device *dev)
14579 {
14580 struct drm_i915_private *dev_priv = dev->dev_private;
14581
14582 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14583 DRM_INFO("applying pipe b force quirk\n");
14584 }
14585
14586 /*
14587 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14588 */
14589 static void quirk_ssc_force_disable(struct drm_device *dev)
14590 {
14591 struct drm_i915_private *dev_priv = dev->dev_private;
14592 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14593 DRM_INFO("applying lvds SSC disable quirk\n");
14594 }
14595
14596 /*
14597 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14598 * brightness value
14599 */
14600 static void quirk_invert_brightness(struct drm_device *dev)
14601 {
14602 struct drm_i915_private *dev_priv = dev->dev_private;
14603 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14604 DRM_INFO("applying inverted panel brightness quirk\n");
14605 }
14606
14607 /* Some VBT's incorrectly indicate no backlight is present */
14608 static void quirk_backlight_present(struct drm_device *dev)
14609 {
14610 struct drm_i915_private *dev_priv = dev->dev_private;
14611 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14612 DRM_INFO("applying backlight present quirk\n");
14613 }
14614
14615 struct intel_quirk {
14616 int device;
14617 int subsystem_vendor;
14618 int subsystem_device;
14619 void (*hook)(struct drm_device *dev);
14620 };
14621
14622 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14623 struct intel_dmi_quirk {
14624 void (*hook)(struct drm_device *dev);
14625 const struct dmi_system_id (*dmi_id_list)[];
14626 };
14627
14628 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14629 {
14630 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14631 return 1;
14632 }
14633
14634 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14635 {
14636 .dmi_id_list = &(const struct dmi_system_id[]) {
14637 {
14638 .callback = intel_dmi_reverse_brightness,
14639 .ident = "NCR Corporation",
14640 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14641 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14642 },
14643 },
14644 { } /* terminating entry */
14645 },
14646 .hook = quirk_invert_brightness,
14647 },
14648 };
14649
14650 static struct intel_quirk intel_quirks[] = {
14651 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14652 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14653
14654 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14655 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14656
14657 /* 830 needs to leave pipe A & dpll A up */
14658 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14659
14660 /* 830 needs to leave pipe B & dpll B up */
14661 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14662
14663 /* Lenovo U160 cannot use SSC on LVDS */
14664 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14665
14666 /* Sony Vaio Y cannot use SSC on LVDS */
14667 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14668
14669 /* Acer Aspire 5734Z must invert backlight brightness */
14670 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14671
14672 /* Acer/eMachines G725 */
14673 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14674
14675 /* Acer/eMachines e725 */
14676 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14677
14678 /* Acer/Packard Bell NCL20 */
14679 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14680
14681 /* Acer Aspire 4736Z */
14682 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14683
14684 /* Acer Aspire 5336 */
14685 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14686
14687 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14688 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14689
14690 /* Acer C720 Chromebook (Core i3 4005U) */
14691 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14692
14693 /* Apple Macbook 2,1 (Core 2 T7400) */
14694 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14695
14696 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14697 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14698
14699 /* HP Chromebook 14 (Celeron 2955U) */
14700 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14701
14702 /* Dell Chromebook 11 */
14703 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14704 };
14705
14706 static void intel_init_quirks(struct drm_device *dev)
14707 {
14708 struct pci_dev *d = dev->pdev;
14709 int i;
14710
14711 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14712 struct intel_quirk *q = &intel_quirks[i];
14713
14714 if (d->device == q->device &&
14715 (d->subsystem_vendor == q->subsystem_vendor ||
14716 q->subsystem_vendor == PCI_ANY_ID) &&
14717 (d->subsystem_device == q->subsystem_device ||
14718 q->subsystem_device == PCI_ANY_ID))
14719 q->hook(dev);
14720 }
14721 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14722 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14723 intel_dmi_quirks[i].hook(dev);
14724 }
14725 }
14726
14727 /* Disable the VGA plane that we never use */
14728 static void i915_disable_vga(struct drm_device *dev)
14729 {
14730 struct drm_i915_private *dev_priv = dev->dev_private;
14731 u8 sr1;
14732 u32 vga_reg = i915_vgacntrl_reg(dev);
14733
14734 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14735 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14736 outb(SR01, VGA_SR_INDEX);
14737 sr1 = inb(VGA_SR_DATA);
14738 outb(sr1 | 1<<5, VGA_SR_DATA);
14739 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14740 udelay(300);
14741
14742 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14743 POSTING_READ(vga_reg);
14744 }
14745
14746 void intel_modeset_init_hw(struct drm_device *dev)
14747 {
14748 intel_update_cdclk(dev);
14749 intel_prepare_ddi(dev);
14750 intel_init_clock_gating(dev);
14751 intel_enable_gt_powersave(dev);
14752 }
14753
14754 void intel_modeset_init(struct drm_device *dev)
14755 {
14756 struct drm_i915_private *dev_priv = dev->dev_private;
14757 int sprite, ret;
14758 enum pipe pipe;
14759 struct intel_crtc *crtc;
14760
14761 drm_mode_config_init(dev);
14762
14763 dev->mode_config.min_width = 0;
14764 dev->mode_config.min_height = 0;
14765
14766 dev->mode_config.preferred_depth = 24;
14767 dev->mode_config.prefer_shadow = 1;
14768
14769 dev->mode_config.allow_fb_modifiers = true;
14770
14771 dev->mode_config.funcs = &intel_mode_funcs;
14772
14773 intel_init_quirks(dev);
14774
14775 intel_init_pm(dev);
14776
14777 if (INTEL_INFO(dev)->num_pipes == 0)
14778 return;
14779
14780 /*
14781 * There may be no VBT; and if the BIOS enabled SSC we can
14782 * just keep using it to avoid unnecessary flicker. Whereas if the
14783 * BIOS isn't using it, don't assume it will work even if the VBT
14784 * indicates as much.
14785 */
14786 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14787 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14788 DREF_SSC1_ENABLE);
14789
14790 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14791 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14792 bios_lvds_use_ssc ? "en" : "dis",
14793 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14794 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14795 }
14796 }
14797
14798 intel_init_display(dev);
14799 intel_init_audio(dev);
14800
14801 if (IS_GEN2(dev)) {
14802 dev->mode_config.max_width = 2048;
14803 dev->mode_config.max_height = 2048;
14804 } else if (IS_GEN3(dev)) {
14805 dev->mode_config.max_width = 4096;
14806 dev->mode_config.max_height = 4096;
14807 } else {
14808 dev->mode_config.max_width = 8192;
14809 dev->mode_config.max_height = 8192;
14810 }
14811
14812 if (IS_845G(dev) || IS_I865G(dev)) {
14813 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14814 dev->mode_config.cursor_height = 1023;
14815 } else if (IS_GEN2(dev)) {
14816 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14817 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14818 } else {
14819 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14820 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14821 }
14822
14823 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14824
14825 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14826 INTEL_INFO(dev)->num_pipes,
14827 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14828
14829 for_each_pipe(dev_priv, pipe) {
14830 intel_crtc_init(dev, pipe);
14831 for_each_sprite(dev_priv, pipe, sprite) {
14832 ret = intel_plane_init(dev, pipe, sprite);
14833 if (ret)
14834 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14835 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14836 }
14837 }
14838
14839 intel_shared_dpll_init(dev);
14840
14841 /* Just disable it once at startup */
14842 i915_disable_vga(dev);
14843 intel_setup_outputs(dev);
14844
14845 /* Just in case the BIOS is doing something questionable. */
14846 intel_fbc_disable(dev_priv);
14847
14848 drm_modeset_lock_all(dev);
14849 intel_modeset_setup_hw_state(dev);
14850 drm_modeset_unlock_all(dev);
14851
14852 for_each_intel_crtc(dev, crtc) {
14853 struct intel_initial_plane_config plane_config = {};
14854
14855 if (!crtc->active)
14856 continue;
14857
14858 /*
14859 * Note that reserving the BIOS fb up front prevents us
14860 * from stuffing other stolen allocations like the ring
14861 * on top. This prevents some ugliness at boot time, and
14862 * can even allow for smooth boot transitions if the BIOS
14863 * fb is large enough for the active pipe configuration.
14864 */
14865 dev_priv->display.get_initial_plane_config(crtc,
14866 &plane_config);
14867
14868 /*
14869 * If the fb is shared between multiple heads, we'll
14870 * just get the first one.
14871 */
14872 intel_find_initial_plane_obj(crtc, &plane_config);
14873 }
14874 }
14875
14876 static void intel_enable_pipe_a(struct drm_device *dev)
14877 {
14878 struct intel_connector *connector;
14879 struct drm_connector *crt = NULL;
14880 struct intel_load_detect_pipe load_detect_temp;
14881 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14882
14883 /* We can't just switch on the pipe A, we need to set things up with a
14884 * proper mode and output configuration. As a gross hack, enable pipe A
14885 * by enabling the load detect pipe once. */
14886 for_each_intel_connector(dev, connector) {
14887 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14888 crt = &connector->base;
14889 break;
14890 }
14891 }
14892
14893 if (!crt)
14894 return;
14895
14896 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14897 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14898 }
14899
14900 static bool
14901 intel_check_plane_mapping(struct intel_crtc *crtc)
14902 {
14903 struct drm_device *dev = crtc->base.dev;
14904 struct drm_i915_private *dev_priv = dev->dev_private;
14905 u32 reg, val;
14906
14907 if (INTEL_INFO(dev)->num_pipes == 1)
14908 return true;
14909
14910 reg = DSPCNTR(!crtc->plane);
14911 val = I915_READ(reg);
14912
14913 if ((val & DISPLAY_PLANE_ENABLE) &&
14914 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14915 return false;
14916
14917 return true;
14918 }
14919
14920 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14921 {
14922 struct drm_device *dev = crtc->base.dev;
14923 struct intel_encoder *encoder;
14924
14925 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14926 return true;
14927
14928 return false;
14929 }
14930
14931 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14932 {
14933 struct drm_device *dev = crtc->base.dev;
14934 struct drm_i915_private *dev_priv = dev->dev_private;
14935 u32 reg;
14936
14937 /* Clear any frame start delays used for debugging left by the BIOS */
14938 reg = PIPECONF(crtc->config->cpu_transcoder);
14939 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14940
14941 /* restore vblank interrupts to correct state */
14942 drm_crtc_vblank_reset(&crtc->base);
14943 if (crtc->active) {
14944 struct intel_plane *plane;
14945
14946 drm_crtc_vblank_on(&crtc->base);
14947
14948 /* Disable everything but the primary plane */
14949 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14950 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14951 continue;
14952
14953 plane->disable_plane(&plane->base, &crtc->base);
14954 }
14955 }
14956
14957 /* We need to sanitize the plane -> pipe mapping first because this will
14958 * disable the crtc (and hence change the state) if it is wrong. Note
14959 * that gen4+ has a fixed plane -> pipe mapping. */
14960 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14961 bool plane;
14962
14963 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14964 crtc->base.base.id);
14965
14966 /* Pipe has the wrong plane attached and the plane is active.
14967 * Temporarily change the plane mapping and disable everything
14968 * ... */
14969 plane = crtc->plane;
14970 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14971 crtc->plane = !plane;
14972 intel_crtc_disable_noatomic(&crtc->base);
14973 crtc->plane = plane;
14974 }
14975
14976 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14977 crtc->pipe == PIPE_A && !crtc->active) {
14978 /* BIOS forgot to enable pipe A, this mostly happens after
14979 * resume. Force-enable the pipe to fix this, the update_dpms
14980 * call below we restore the pipe to the right state, but leave
14981 * the required bits on. */
14982 intel_enable_pipe_a(dev);
14983 }
14984
14985 /* Adjust the state of the output pipe according to whether we
14986 * have active connectors/encoders. */
14987 if (!intel_crtc_has_encoders(crtc))
14988 intel_crtc_disable_noatomic(&crtc->base);
14989
14990 if (crtc->active != crtc->base.state->active) {
14991 struct intel_encoder *encoder;
14992
14993 /* This can happen either due to bugs in the get_hw_state
14994 * functions or because of calls to intel_crtc_disable_noatomic,
14995 * or because the pipe is force-enabled due to the
14996 * pipe A quirk. */
14997 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14998 crtc->base.base.id,
14999 crtc->base.state->enable ? "enabled" : "disabled",
15000 crtc->active ? "enabled" : "disabled");
15001
15002 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15003 crtc->base.state->active = crtc->active;
15004 crtc->base.enabled = crtc->active;
15005
15006 /* Because we only establish the connector -> encoder ->
15007 * crtc links if something is active, this means the
15008 * crtc is now deactivated. Break the links. connector
15009 * -> encoder links are only establish when things are
15010 * actually up, hence no need to break them. */
15011 WARN_ON(crtc->active);
15012
15013 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15014 encoder->base.crtc = NULL;
15015 }
15016
15017 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15018 /*
15019 * We start out with underrun reporting disabled to avoid races.
15020 * For correct bookkeeping mark this on active crtcs.
15021 *
15022 * Also on gmch platforms we dont have any hardware bits to
15023 * disable the underrun reporting. Which means we need to start
15024 * out with underrun reporting disabled also on inactive pipes,
15025 * since otherwise we'll complain about the garbage we read when
15026 * e.g. coming up after runtime pm.
15027 *
15028 * No protection against concurrent access is required - at
15029 * worst a fifo underrun happens which also sets this to false.
15030 */
15031 crtc->cpu_fifo_underrun_disabled = true;
15032 crtc->pch_fifo_underrun_disabled = true;
15033 }
15034 }
15035
15036 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15037 {
15038 struct intel_connector *connector;
15039 struct drm_device *dev = encoder->base.dev;
15040 bool active = false;
15041
15042 /* We need to check both for a crtc link (meaning that the
15043 * encoder is active and trying to read from a pipe) and the
15044 * pipe itself being active. */
15045 bool has_active_crtc = encoder->base.crtc &&
15046 to_intel_crtc(encoder->base.crtc)->active;
15047
15048 for_each_intel_connector(dev, connector) {
15049 if (connector->base.encoder != &encoder->base)
15050 continue;
15051
15052 active = true;
15053 break;
15054 }
15055
15056 if (active && !has_active_crtc) {
15057 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15058 encoder->base.base.id,
15059 encoder->base.name);
15060
15061 /* Connector is active, but has no active pipe. This is
15062 * fallout from our resume register restoring. Disable
15063 * the encoder manually again. */
15064 if (encoder->base.crtc) {
15065 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15066 encoder->base.base.id,
15067 encoder->base.name);
15068 encoder->disable(encoder);
15069 if (encoder->post_disable)
15070 encoder->post_disable(encoder);
15071 }
15072 encoder->base.crtc = NULL;
15073
15074 /* Inconsistent output/port/pipe state happens presumably due to
15075 * a bug in one of the get_hw_state functions. Or someplace else
15076 * in our code, like the register restore mess on resume. Clamp
15077 * things to off as a safer default. */
15078 for_each_intel_connector(dev, connector) {
15079 if (connector->encoder != encoder)
15080 continue;
15081 connector->base.dpms = DRM_MODE_DPMS_OFF;
15082 connector->base.encoder = NULL;
15083 }
15084 }
15085 /* Enabled encoders without active connectors will be fixed in
15086 * the crtc fixup. */
15087 }
15088
15089 void i915_redisable_vga_power_on(struct drm_device *dev)
15090 {
15091 struct drm_i915_private *dev_priv = dev->dev_private;
15092 u32 vga_reg = i915_vgacntrl_reg(dev);
15093
15094 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15095 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15096 i915_disable_vga(dev);
15097 }
15098 }
15099
15100 void i915_redisable_vga(struct drm_device *dev)
15101 {
15102 struct drm_i915_private *dev_priv = dev->dev_private;
15103
15104 /* This function can be called both from intel_modeset_setup_hw_state or
15105 * at a very early point in our resume sequence, where the power well
15106 * structures are not yet restored. Since this function is at a very
15107 * paranoid "someone might have enabled VGA while we were not looking"
15108 * level, just check if the power well is enabled instead of trying to
15109 * follow the "don't touch the power well if we don't need it" policy
15110 * the rest of the driver uses. */
15111 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15112 return;
15113
15114 i915_redisable_vga_power_on(dev);
15115 }
15116
15117 static bool primary_get_hw_state(struct intel_plane *plane)
15118 {
15119 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15120
15121 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15122 }
15123
15124 /* FIXME read out full plane state for all planes */
15125 static void readout_plane_state(struct intel_crtc *crtc)
15126 {
15127 struct intel_plane_state *plane_state =
15128 to_intel_plane_state(crtc->base.primary->state);
15129
15130 plane_state->visible =
15131 primary_get_hw_state(to_intel_plane(crtc->base.primary));
15132 }
15133
15134 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15135 {
15136 struct drm_i915_private *dev_priv = dev->dev_private;
15137 enum pipe pipe;
15138 struct intel_crtc *crtc;
15139 struct intel_encoder *encoder;
15140 struct intel_connector *connector;
15141 int i;
15142
15143 for_each_intel_crtc(dev, crtc) {
15144 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15145 memset(crtc->config, 0, sizeof(*crtc->config));
15146 crtc->config->base.crtc = &crtc->base;
15147
15148 crtc->active = dev_priv->display.get_pipe_config(crtc,
15149 crtc->config);
15150
15151 crtc->base.state->active = crtc->active;
15152 crtc->base.enabled = crtc->active;
15153
15154 readout_plane_state(crtc);
15155
15156 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15157 crtc->base.base.id,
15158 crtc->active ? "enabled" : "disabled");
15159 }
15160
15161 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15162 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15163
15164 pll->on = pll->get_hw_state(dev_priv, pll,
15165 &pll->config.hw_state);
15166 pll->active = 0;
15167 pll->config.crtc_mask = 0;
15168 for_each_intel_crtc(dev, crtc) {
15169 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15170 pll->active++;
15171 pll->config.crtc_mask |= 1 << crtc->pipe;
15172 }
15173 }
15174
15175 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15176 pll->name, pll->config.crtc_mask, pll->on);
15177
15178 if (pll->config.crtc_mask)
15179 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15180 }
15181
15182 for_each_intel_encoder(dev, encoder) {
15183 pipe = 0;
15184
15185 if (encoder->get_hw_state(encoder, &pipe)) {
15186 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15187 encoder->base.crtc = &crtc->base;
15188 encoder->get_config(encoder, crtc->config);
15189 } else {
15190 encoder->base.crtc = NULL;
15191 }
15192
15193 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15194 encoder->base.base.id,
15195 encoder->base.name,
15196 encoder->base.crtc ? "enabled" : "disabled",
15197 pipe_name(pipe));
15198 }
15199
15200 for_each_intel_connector(dev, connector) {
15201 if (connector->get_hw_state(connector)) {
15202 connector->base.dpms = DRM_MODE_DPMS_ON;
15203 connector->base.encoder = &connector->encoder->base;
15204 } else {
15205 connector->base.dpms = DRM_MODE_DPMS_OFF;
15206 connector->base.encoder = NULL;
15207 }
15208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15209 connector->base.base.id,
15210 connector->base.name,
15211 connector->base.encoder ? "enabled" : "disabled");
15212 }
15213
15214 for_each_intel_crtc(dev, crtc) {
15215 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15216
15217 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15218 if (crtc->base.state->active) {
15219 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15220 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15221 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15222
15223 /*
15224 * The initial mode needs to be set in order to keep
15225 * the atomic core happy. It wants a valid mode if the
15226 * crtc's enabled, so we do the above call.
15227 *
15228 * At this point some state updated by the connectors
15229 * in their ->detect() callback has not run yet, so
15230 * no recalculation can be done yet.
15231 *
15232 * Even if we could do a recalculation and modeset
15233 * right now it would cause a double modeset if
15234 * fbdev or userspace chooses a different initial mode.
15235 *
15236 * If that happens, someone indicated they wanted a
15237 * mode change, which means it's safe to do a full
15238 * recalculation.
15239 */
15240 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15241
15242 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15243 update_scanline_offset(crtc);
15244 }
15245 }
15246 }
15247
15248 /* Scan out the current hw modeset state,
15249 * and sanitizes it to the current state
15250 */
15251 static void
15252 intel_modeset_setup_hw_state(struct drm_device *dev)
15253 {
15254 struct drm_i915_private *dev_priv = dev->dev_private;
15255 enum pipe pipe;
15256 struct intel_crtc *crtc;
15257 struct intel_encoder *encoder;
15258 int i;
15259
15260 intel_modeset_readout_hw_state(dev);
15261
15262 /* HW state is read out, now we need to sanitize this mess. */
15263 for_each_intel_encoder(dev, encoder) {
15264 intel_sanitize_encoder(encoder);
15265 }
15266
15267 for_each_pipe(dev_priv, pipe) {
15268 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15269 intel_sanitize_crtc(crtc);
15270 intel_dump_pipe_config(crtc, crtc->config,
15271 "[setup_hw_state]");
15272 }
15273
15274 intel_modeset_update_connector_atomic_state(dev);
15275
15276 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15277 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15278
15279 if (!pll->on || pll->active)
15280 continue;
15281
15282 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15283
15284 pll->disable(dev_priv, pll);
15285 pll->on = false;
15286 }
15287
15288 if (IS_VALLEYVIEW(dev))
15289 vlv_wm_get_hw_state(dev);
15290 else if (IS_GEN9(dev))
15291 skl_wm_get_hw_state(dev);
15292 else if (HAS_PCH_SPLIT(dev))
15293 ilk_wm_get_hw_state(dev);
15294
15295 for_each_intel_crtc(dev, crtc) {
15296 unsigned long put_domains;
15297
15298 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15299 if (WARN_ON(put_domains))
15300 modeset_put_power_domains(dev_priv, put_domains);
15301 }
15302 intel_display_set_init_power(dev_priv, false);
15303 }
15304
15305 void intel_display_resume(struct drm_device *dev)
15306 {
15307 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15308 struct intel_connector *conn;
15309 struct intel_plane *plane;
15310 struct drm_crtc *crtc;
15311 int ret;
15312
15313 if (!state)
15314 return;
15315
15316 state->acquire_ctx = dev->mode_config.acquire_ctx;
15317
15318 /* preserve complete old state, including dpll */
15319 intel_atomic_get_shared_dpll_state(state);
15320
15321 for_each_crtc(dev, crtc) {
15322 struct drm_crtc_state *crtc_state =
15323 drm_atomic_get_crtc_state(state, crtc);
15324
15325 ret = PTR_ERR_OR_ZERO(crtc_state);
15326 if (ret)
15327 goto err;
15328
15329 /* force a restore */
15330 crtc_state->mode_changed = true;
15331 }
15332
15333 for_each_intel_plane(dev, plane) {
15334 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15335 if (ret)
15336 goto err;
15337 }
15338
15339 for_each_intel_connector(dev, conn) {
15340 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15341 if (ret)
15342 goto err;
15343 }
15344
15345 intel_modeset_setup_hw_state(dev);
15346
15347 i915_redisable_vga(dev);
15348 ret = drm_atomic_commit(state);
15349 if (!ret)
15350 return;
15351
15352 err:
15353 DRM_ERROR("Restoring old state failed with %i\n", ret);
15354 drm_atomic_state_free(state);
15355 }
15356
15357 void intel_modeset_gem_init(struct drm_device *dev)
15358 {
15359 struct drm_crtc *c;
15360 struct drm_i915_gem_object *obj;
15361 int ret;
15362
15363 mutex_lock(&dev->struct_mutex);
15364 intel_init_gt_powersave(dev);
15365 mutex_unlock(&dev->struct_mutex);
15366
15367 intel_modeset_init_hw(dev);
15368
15369 intel_setup_overlay(dev);
15370
15371 /*
15372 * Make sure any fbs we allocated at startup are properly
15373 * pinned & fenced. When we do the allocation it's too early
15374 * for this.
15375 */
15376 for_each_crtc(dev, c) {
15377 obj = intel_fb_obj(c->primary->fb);
15378 if (obj == NULL)
15379 continue;
15380
15381 mutex_lock(&dev->struct_mutex);
15382 ret = intel_pin_and_fence_fb_obj(c->primary,
15383 c->primary->fb,
15384 c->primary->state,
15385 NULL, NULL);
15386 mutex_unlock(&dev->struct_mutex);
15387 if (ret) {
15388 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15389 to_intel_crtc(c)->pipe);
15390 drm_framebuffer_unreference(c->primary->fb);
15391 c->primary->fb = NULL;
15392 c->primary->crtc = c->primary->state->crtc = NULL;
15393 update_state_fb(c->primary);
15394 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15395 }
15396 }
15397
15398 intel_backlight_register(dev);
15399 }
15400
15401 void intel_connector_unregister(struct intel_connector *intel_connector)
15402 {
15403 struct drm_connector *connector = &intel_connector->base;
15404
15405 intel_panel_destroy_backlight(connector);
15406 drm_connector_unregister(connector);
15407 }
15408
15409 void intel_modeset_cleanup(struct drm_device *dev)
15410 {
15411 struct drm_i915_private *dev_priv = dev->dev_private;
15412 struct drm_connector *connector;
15413
15414 intel_disable_gt_powersave(dev);
15415
15416 intel_backlight_unregister(dev);
15417
15418 /*
15419 * Interrupts and polling as the first thing to avoid creating havoc.
15420 * Too much stuff here (turning of connectors, ...) would
15421 * experience fancy races otherwise.
15422 */
15423 intel_irq_uninstall(dev_priv);
15424
15425 /*
15426 * Due to the hpd irq storm handling the hotplug work can re-arm the
15427 * poll handlers. Hence disable polling after hpd handling is shut down.
15428 */
15429 drm_kms_helper_poll_fini(dev);
15430
15431 intel_unregister_dsm_handler();
15432
15433 intel_fbc_disable(dev_priv);
15434
15435 /* flush any delayed tasks or pending work */
15436 flush_scheduled_work();
15437
15438 /* destroy the backlight and sysfs files before encoders/connectors */
15439 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15440 struct intel_connector *intel_connector;
15441
15442 intel_connector = to_intel_connector(connector);
15443 intel_connector->unregister(intel_connector);
15444 }
15445
15446 drm_mode_config_cleanup(dev);
15447
15448 intel_cleanup_overlay(dev);
15449
15450 mutex_lock(&dev->struct_mutex);
15451 intel_cleanup_gt_powersave(dev);
15452 mutex_unlock(&dev->struct_mutex);
15453 }
15454
15455 /*
15456 * Return which encoder is currently attached for connector.
15457 */
15458 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15459 {
15460 return &intel_attached_encoder(connector)->base;
15461 }
15462
15463 void intel_connector_attach_encoder(struct intel_connector *connector,
15464 struct intel_encoder *encoder)
15465 {
15466 connector->encoder = encoder;
15467 drm_mode_connector_attach_encoder(&connector->base,
15468 &encoder->base);
15469 }
15470
15471 /*
15472 * set vga decode state - true == enable VGA decode
15473 */
15474 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15475 {
15476 struct drm_i915_private *dev_priv = dev->dev_private;
15477 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15478 u16 gmch_ctrl;
15479
15480 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15481 DRM_ERROR("failed to read control word\n");
15482 return -EIO;
15483 }
15484
15485 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15486 return 0;
15487
15488 if (state)
15489 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15490 else
15491 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15492
15493 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15494 DRM_ERROR("failed to write control word\n");
15495 return -EIO;
15496 }
15497
15498 return 0;
15499 }
15500
15501 struct intel_display_error_state {
15502
15503 u32 power_well_driver;
15504
15505 int num_transcoders;
15506
15507 struct intel_cursor_error_state {
15508 u32 control;
15509 u32 position;
15510 u32 base;
15511 u32 size;
15512 } cursor[I915_MAX_PIPES];
15513
15514 struct intel_pipe_error_state {
15515 bool power_domain_on;
15516 u32 source;
15517 u32 stat;
15518 } pipe[I915_MAX_PIPES];
15519
15520 struct intel_plane_error_state {
15521 u32 control;
15522 u32 stride;
15523 u32 size;
15524 u32 pos;
15525 u32 addr;
15526 u32 surface;
15527 u32 tile_offset;
15528 } plane[I915_MAX_PIPES];
15529
15530 struct intel_transcoder_error_state {
15531 bool power_domain_on;
15532 enum transcoder cpu_transcoder;
15533
15534 u32 conf;
15535
15536 u32 htotal;
15537 u32 hblank;
15538 u32 hsync;
15539 u32 vtotal;
15540 u32 vblank;
15541 u32 vsync;
15542 } transcoder[4];
15543 };
15544
15545 struct intel_display_error_state *
15546 intel_display_capture_error_state(struct drm_device *dev)
15547 {
15548 struct drm_i915_private *dev_priv = dev->dev_private;
15549 struct intel_display_error_state *error;
15550 int transcoders[] = {
15551 TRANSCODER_A,
15552 TRANSCODER_B,
15553 TRANSCODER_C,
15554 TRANSCODER_EDP,
15555 };
15556 int i;
15557
15558 if (INTEL_INFO(dev)->num_pipes == 0)
15559 return NULL;
15560
15561 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15562 if (error == NULL)
15563 return NULL;
15564
15565 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15566 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15567
15568 for_each_pipe(dev_priv, i) {
15569 error->pipe[i].power_domain_on =
15570 __intel_display_power_is_enabled(dev_priv,
15571 POWER_DOMAIN_PIPE(i));
15572 if (!error->pipe[i].power_domain_on)
15573 continue;
15574
15575 error->cursor[i].control = I915_READ(CURCNTR(i));
15576 error->cursor[i].position = I915_READ(CURPOS(i));
15577 error->cursor[i].base = I915_READ(CURBASE(i));
15578
15579 error->plane[i].control = I915_READ(DSPCNTR(i));
15580 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15581 if (INTEL_INFO(dev)->gen <= 3) {
15582 error->plane[i].size = I915_READ(DSPSIZE(i));
15583 error->plane[i].pos = I915_READ(DSPPOS(i));
15584 }
15585 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15586 error->plane[i].addr = I915_READ(DSPADDR(i));
15587 if (INTEL_INFO(dev)->gen >= 4) {
15588 error->plane[i].surface = I915_READ(DSPSURF(i));
15589 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15590 }
15591
15592 error->pipe[i].source = I915_READ(PIPESRC(i));
15593
15594 if (HAS_GMCH_DISPLAY(dev))
15595 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15596 }
15597
15598 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15599 if (HAS_DDI(dev_priv->dev))
15600 error->num_transcoders++; /* Account for eDP. */
15601
15602 for (i = 0; i < error->num_transcoders; i++) {
15603 enum transcoder cpu_transcoder = transcoders[i];
15604
15605 error->transcoder[i].power_domain_on =
15606 __intel_display_power_is_enabled(dev_priv,
15607 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15608 if (!error->transcoder[i].power_domain_on)
15609 continue;
15610
15611 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15612
15613 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15614 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15615 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15616 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15617 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15618 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15619 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15620 }
15621
15622 return error;
15623 }
15624
15625 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15626
15627 void
15628 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15629 struct drm_device *dev,
15630 struct intel_display_error_state *error)
15631 {
15632 struct drm_i915_private *dev_priv = dev->dev_private;
15633 int i;
15634
15635 if (!error)
15636 return;
15637
15638 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15639 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15640 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15641 error->power_well_driver);
15642 for_each_pipe(dev_priv, i) {
15643 err_printf(m, "Pipe [%d]:\n", i);
15644 err_printf(m, " Power: %s\n",
15645 error->pipe[i].power_domain_on ? "on" : "off");
15646 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15647 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15648
15649 err_printf(m, "Plane [%d]:\n", i);
15650 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15651 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15652 if (INTEL_INFO(dev)->gen <= 3) {
15653 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15654 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15655 }
15656 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15657 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15658 if (INTEL_INFO(dev)->gen >= 4) {
15659 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15660 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15661 }
15662
15663 err_printf(m, "Cursor [%d]:\n", i);
15664 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15665 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15666 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15667 }
15668
15669 for (i = 0; i < error->num_transcoders; i++) {
15670 err_printf(m, "CPU transcoder: %c\n",
15671 transcoder_name(error->transcoder[i].cpu_transcoder));
15672 err_printf(m, " Power: %s\n",
15673 error->transcoder[i].power_domain_on ? "on" : "off");
15674 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15675 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15676 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15677 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15678 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15679 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15680 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15681 }
15682 }
15683
15684 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15685 {
15686 struct intel_crtc *crtc;
15687
15688 for_each_intel_crtc(dev, crtc) {
15689 struct intel_unpin_work *work;
15690
15691 spin_lock_irq(&dev->event_lock);
15692
15693 work = crtc->unpin_work;
15694
15695 if (work && work->event &&
15696 work->event->base.file_priv == file) {
15697 kfree(work->event);
15698 work->event = NULL;
15699 }
15700
15701 spin_unlock_irq(&dev->event_lock);
15702 }
15703 }
Linux kernel - Deliverables
This page took 0.372261 seconds and 5 git commands to generate.