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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
128
129 struct intel_limit {
130 struct {
131 int min, max;
132 } dot, vco, n, m, m1, m2, p, p1;
133
134 struct {
135 int dot_limit;
136 int p2_slow, p2_fast;
137 } p2;
138 };
139
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
142 {
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
144
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
150
151 return vco_freq[hpll_freq] * 1000;
152 }
153
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
156 {
157 u32 val;
158 int divider;
159
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
163
164 divider = val & CCK_FREQUENCY_VALUES;
165
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
169
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
171 }
172
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
175 {
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
178
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
181 }
182
183 static int
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
185 {
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
187 }
188
189 static int
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
191 {
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
195 }
196
197 static int
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
199 {
200 uint32_t clkcfg;
201
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
205 case CLKCFG_FSB_400:
206 return 100000;
207 case CLKCFG_FSB_533:
208 return 133333;
209 case CLKCFG_FSB_667:
210 return 166667;
211 case CLKCFG_FSB_800:
212 return 200000;
213 case CLKCFG_FSB_1067:
214 return 266667;
215 case CLKCFG_FSB_1333:
216 return 333333;
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
220 return 400000;
221 default:
222 return 133333;
223 }
224 }
225
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
227 {
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
234 else
235 return; /* no rawclk on other platforms, or no need to know it */
236
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
238 }
239
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
241 {
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
243 return;
244
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
247
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
249 }
250
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
254 {
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
259 else
260 return 270000;
261 }
262
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
274 };
275
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
287 };
288
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
300 };
301
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
326 };
327
328
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 10,
340 .p2_fast = 10
341 },
342 };
343
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
355 };
356
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
368 },
369 };
370
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
382 },
383 };
384
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
398 };
399
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
411 };
412
413 /* Ironlake / Sandybridge
414 *
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
417 */
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
429 };
430
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
469 };
470
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
482 };
483
484 static const struct intel_limit intel_limits_vlv = {
485 /*
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
490 */
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
498 };
499
500 static const struct intel_limit intel_limits_chv = {
501 /*
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
506 */
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
514 };
515
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
526 };
527
528 static bool
529 needs_modeset(struct drm_crtc_state *state)
530 {
531 return drm_atomic_crtc_needs_modeset(state);
532 }
533
534 /*
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
541 */
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
544 {
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
548 return 0;
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
551
552 return clock->dot;
553 }
554
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
556 {
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
558 }
559
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
561 {
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
565 return 0;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568
569 return clock->dot;
570 }
571
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
573 {
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
577 return 0;
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580
581 return clock->dot / 5;
582 }
583
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
585 {
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593
594 return clock->dot / 5;
595 }
596
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 /**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
606 {
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
635
636 return true;
637 }
638
639 static int
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
642 int target)
643 {
644 struct drm_device *dev = crtc_state->base.crtc->dev;
645
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
647 /*
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
651 */
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
654 else
655 return limit->p2.p2_slow;
656 } else {
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
659 else
660 return limit->p2.p2_fast;
661 }
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
693 break;
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 /*
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 *
726 * Target and reference clocks are specified in kHz.
727 *
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
730 */
731 static bool
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
736 {
737 struct drm_device *dev = crtc_state->base.crtc->dev;
738 struct dpll clock;
739 int err = target;
740
741 memset(best_clock, 0, sizeof(*best_clock));
742
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
746 clock.m1++) {
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
753 int this_err;
754
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
757 &clock))
758 continue;
759 if (match_clock &&
760 clock.p != match_clock->p)
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
765 *best_clock = clock;
766 err = this_err;
767 }
768 }
769 }
770 }
771 }
772
773 return (err != target);
774 }
775
776 /*
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 *
781 * Target and reference clocks are specified in kHz.
782 *
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
785 */
786 static bool
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
791 {
792 struct drm_device *dev = crtc_state->base.crtc->dev;
793 struct dpll clock;
794 int max_n;
795 bool found = false;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
798
799 memset(best_clock, 0, sizeof(*best_clock));
800
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
802
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
813 int this_err;
814
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
817 &clock))
818 continue;
819
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
822 *best_clock = clock;
823 err_most = this_err;
824 max_n = clock.n;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831 return found;
832 }
833
834 /*
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
837 */
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
843 {
844 /*
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
847 */
848 if (IS_CHERRYVIEW(dev)) {
849 *error_ppm = 0;
850
851 return calculated_clock->p > best_clock->p;
852 }
853
854 if (WARN_ON_ONCE(!target_freq))
855 return false;
856
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
859 target_freq);
860 /*
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
864 */
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 *error_ppm = 0;
867
868 return true;
869 }
870
871 return *error_ppm + 10 < best_error_ppm;
872 }
873
874 /*
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
878 */
879 static bool
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
884 {
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
887 struct dpll clock;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
891 bool found = false;
892
893 target *= 5; /* fast clock */
894
895 memset(best_clock, 0, sizeof(*best_clock));
896
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
905 unsigned int ppm;
906
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
908 refclk * clock.m1);
909
910 vlv_calc_dpll_params(refclk, &clock);
911
912 if (!intel_PLL_is_valid(dev, limit,
913 &clock))
914 continue;
915
916 if (!vlv_PLL_is_optimal(dev, target,
917 &clock,
918 best_clock,
919 bestppm, &ppm))
920 continue;
921
922 *best_clock = clock;
923 bestppm = ppm;
924 found = true;
925 }
926 }
927 }
928 }
929
930 return found;
931 }
932
933 /*
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
937 */
938 static bool
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
943 {
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
947 struct dpll clock;
948 uint64_t m2;
949 int found = false;
950
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
953
954 /*
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
958 */
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
961
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
967
968 clock.p = clock.p1 * clock.p2;
969
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
972
973 if (m2 > INT_MAX/clock.m1)
974 continue;
975
976 clock.m2 = m2;
977
978 chv_calc_dpll_params(refclk, &clock);
979
980 if (!intel_PLL_is_valid(dev, limit, &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
985 continue;
986
987 *best_clock = clock;
988 best_error_ppm = error_ppm;
989 found = true;
990 }
991 }
992
993 return found;
994 }
995
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
998 {
999 int refclk = 100000;
1000 const struct intel_limit *limit = &intel_limits_bxt;
1001
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1012 *
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1015 *
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1018 *
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1021 * for atomic.
1022 */
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029 {
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033 return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1040 u32 line1, line2;
1041 u32 line_mask;
1042
1043 if (IS_GEN2(dev))
1044 line_mask = DSL_LINEMASK_GEN2;
1045 else
1046 line_mask = DSL_LINEMASK_GEN3;
1047
1048 line1 = I915_READ(reg) & line_mask;
1049 msleep(5);
1050 line2 = I915_READ(reg) & line_mask;
1051
1052 return line1 == line2;
1053 }
1054
1055 /*
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1058 *
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1062 *
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1065 *
1066 * Otherwise:
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1069 *
1070 */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1077
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1084 100))
1085 WARN(1, "pipe_off wait timed out\n");
1086 } else {
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1090 }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 u32 val;
1098 bool cur_state;
1099
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110 u32 val;
1111 bool cur_state;
1112
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1116
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 } else {
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 u32 val;
1149 bool cur_state;
1150
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1171 return;
1172
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 u32 val;
1181 bool cur_state;
1182
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 enum pipe pipe)
1192 {
1193 struct drm_device *dev = &dev_priv->drm;
1194 i915_reg_t pp_reg;
1195 u32 val;
1196 enum pipe panel_pipe = PIPE_A;
1197 bool locked = true;
1198
1199 if (WARN_ON(HAS_DDI(dev)))
1200 return;
1201
1202 if (HAS_PCH_SPLIT(dev)) {
1203 u32 port_sel;
1204
1205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = PP_CONTROL(pipe);
1215 panel_pipe = pipe;
1216 } else {
1217 pp_reg = PP_CONTROL(0);
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1220 }
1221
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225 locked = false;
1226
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 struct drm_device *dev = &dev_priv->drm;
1236 bool cur_state;
1237
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240 else
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1252 {
1253 bool cur_state;
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255 pipe);
1256 enum intel_display_power_domain power_domain;
1257
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261 state = true;
1262
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268 intel_display_power_put(dev_priv, power_domain);
1269 } else {
1270 cur_state = false;
1271 }
1272
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1280 {
1281 u32 val;
1282 bool cur_state;
1283
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = &dev_priv->drm;
1298 int i;
1299
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1305 plane_name(pipe));
1306 return;
1307 }
1308
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1317 }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe)
1322 {
1323 struct drm_device *dev = &dev_priv->drm;
1324 int sprite;
1325
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1332 }
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1339 }
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1350 }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369 pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375 if ((val & DP_PORT_EN) == 0)
1376 return false;
1377
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
1385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & SDVO_ENABLE) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400 return false;
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
1404 } else {
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413 {
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429 {
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1444 u32 port_sel)
1445 {
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1458 {
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe)
1471 {
1472 u32 val;
1473
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1495 {
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1501 udelay(150);
1502
1503 if (intel_wait_for_register(dev_priv,
1504 DPLL(pipe),
1505 DPLL_LOCK_VLV,
1506 DPLL_LOCK_VLV,
1507 1))
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1513 {
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1516
1517 assert_pipe_disabled(dev_priv, pipe);
1518
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1521
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1524
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1532 {
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536 u32 tmp;
1537
1538 mutex_lock(&dev_priv->sb_lock);
1539
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545 mutex_unlock(&dev_priv->sb_lock);
1546
1547 /*
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 */
1550 udelay(1);
1551
1552 /* Enable PLL */
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558 1))
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1564 {
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1567
1568 assert_pipe_disabled(dev_priv, pipe);
1569
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1572
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1575
1576 if (pipe != PIPE_A) {
1577 /*
1578 * WaPixelRepeatModeFixForC0:chv
1579 *
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1582 */
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588 /*
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1591 */
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593 } else {
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1596 }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601 struct intel_crtc *crtc;
1602 int count = 0;
1603
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607 }
1608
1609 return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627 /*
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1632 */
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636 }
1637
1638 /*
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1642 */
1643 I915_WRITE(reg, 0);
1644
1645 I915_WRITE(reg, dpll);
1646
1647 /* Wait for the clocks to stabilize. */
1648 POSTING_READ(reg);
1649 udelay(150);
1650
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1654 } else {
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1657 *
1658 * So write it again.
1659 */
1660 I915_WRITE(reg, dpll);
1661 }
1662
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1665 POSTING_READ(reg);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1668 POSTING_READ(reg);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1679 *
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 *
1682 * Note! This is for pre-ILK only.
1683 */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1689
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1691 if (IS_I830(dev) &&
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698 }
1699
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703 return;
1704
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1707
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731 u32 val;
1732
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1735
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1743
1744 mutex_lock(&dev_priv->sb_lock);
1745
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751 mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1757 {
1758 u32 port_mask;
1759 i915_reg_t dpll_reg;
1760
1761 switch (dport->port) {
1762 case PORT_B:
1763 port_mask = DPLL_PORTB_READY_MASK;
1764 dpll_reg = DPLL(0);
1765 break;
1766 case PORT_C:
1767 port_mask = DPLL_PORTC_READY_MASK;
1768 dpll_reg = DPLL(0);
1769 expected_mask <<= 4;
1770 break;
1771 case PORT_D:
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1774 break;
1775 default:
1776 BUG();
1777 }
1778
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1781 1000))
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787 enum pipe pipe)
1788 {
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792 i915_reg_t reg;
1793 uint32_t val, pipeconf_val;
1794
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1809 }
1810
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815 if (HAS_PCH_IBX(dev_priv)) {
1816 /*
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1820 */
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1824 else
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1826 }
1827
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1833 else
1834 val |= TRANS_INTERLACED;
1835 else
1836 val |= TRANS_PROGRESSIVE;
1837
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841 100))
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1847 {
1848 u32 val, pipeconf_val;
1849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859 val = TRANS_ENABLE;
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1865 else
1866 val |= TRANS_PROGRESSIVE;
1867
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF,
1871 TRANS_STATE_ENABLE,
1872 TRANS_STATE_ENABLE,
1873 100))
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = &dev_priv->drm;
1881 i915_reg_t reg;
1882 uint32_t val;
1883
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1890
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1898 50))
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1907 }
1908 }
1909
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912 u32 val;
1913
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920 50))
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1932 *
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1943 i915_reg_t reg;
1944 u32 val;
1945
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1951
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = TRANSCODER_A;
1954 else
1955 pch_transcoder = pipe;
1956
1957 /*
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 * need the check.
1961 */
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1965 else
1966 assert_pll_enabled(dev_priv, pipe);
1967 } else {
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1973 }
1974 /* FIXME: assert CPU port conditions for SNB+ */
1975 }
1976
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982 return;
1983 }
1984
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1986 POSTING_READ(reg);
1987
1988 /*
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1994 */
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2003 *
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2007 *
2008 * Will wait until the pipe has shut down before returning.
2009 */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2015 i915_reg_t reg;
2016 u32 val;
2017
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020 /*
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2023 */
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2031 return;
2032
2033 /*
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2036 */
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2044
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2057 {
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2060 return cpp;
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2063 return 128;
2064 else
2065 return 512;
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068 return 128;
2069 else
2070 return 512;
2071 case I915_FORMAT_MOD_Yf_TILED:
2072 switch (cpp) {
2073 case 1:
2074 return 64;
2075 case 2:
2076 case 4:
2077 return 128;
2078 case 8:
2079 case 16:
2080 return 256;
2081 default:
2082 MISSING_CASE(cpp);
2083 return cpp;
2084 }
2085 break;
2086 default:
2087 MISSING_CASE(fb_modifier);
2088 return cpp;
2089 }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2094 {
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096 return 1;
2097 else
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2107 unsigned int cpp)
2108 {
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123 return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128 unsigned int size = 0;
2129 int i;
2130
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134 return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2141 {
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145 } else {
2146 *view = i915_ggtt_view_normal;
2147 }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2153 return 256 * 1024;
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156 return 128 * 1024;
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2158 return 4 * 1024;
2159 else
2160 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2165 {
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2171 return 256 * 1024;
2172 return 0;
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2176 default:
2177 MISSING_CASE(fb_modifier);
2178 return 0;
2179 }
2180 }
2181
2182 struct i915_vma *
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2184 {
2185 struct drm_device *dev = fb->dev;
2186 struct drm_i915_private *dev_priv = to_i915(dev);
2187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188 struct i915_ggtt_view view;
2189 struct i915_vma *vma;
2190 u32 alignment;
2191
2192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2193
2194 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2195
2196 intel_fill_fb_ggtt_view(&view, fb, rotation);
2197
2198 /* Note that the w/a also requires 64 PTE of padding following the
2199 * bo. We currently fill all unused PTE with the shadow page and so
2200 * we should always have valid PTE following the scanout preventing
2201 * the VT-d warning.
2202 */
2203 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204 alignment = 256 * 1024;
2205
2206 /*
2207 * Global gtt pte registers are special registers which actually forward
2208 * writes to a chunk of system memory. Which means that there is no risk
2209 * that the register values disappear as soon as we call
2210 * intel_runtime_pm_put(), so it is correct to wrap only the
2211 * pin/unpin/fence and not more.
2212 */
2213 intel_runtime_pm_get(dev_priv);
2214
2215 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2216 if (IS_ERR(vma))
2217 goto err;
2218
2219 if (i915_vma_is_map_and_fenceable(vma)) {
2220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221 * fence, whereas 965+ only requires a fence if using
2222 * framebuffer compression. For simplicity, we always, when
2223 * possible, install a fence as the cost is not that onerous.
2224 *
2225 * If we fail to fence the tiled scanout, then either the
2226 * modeset will reject the change (which is highly unlikely as
2227 * the affected systems, all but one, do not have unmappable
2228 * space) or we will not be able to enable full powersaving
2229 * techniques (also likely not to apply due to various limits
2230 * FBC and the like impose on the size of the buffer, which
2231 * presumably we violated anyway with this unmappable buffer).
2232 * Anyway, it is presumably better to stumble onwards with
2233 * something and try to run the system in a "less than optimal"
2234 * mode that matches the user configuration.
2235 */
2236 if (i915_vma_get_fence(vma) == 0)
2237 i915_vma_pin_fence(vma);
2238 }
2239
2240 err:
2241 intel_runtime_pm_put(dev_priv);
2242 return vma;
2243 }
2244
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2246 {
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 struct i915_ggtt_view view;
2249 struct i915_vma *vma;
2250
2251 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2252
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254 vma = i915_gem_object_to_ggtt(obj, &view);
2255
2256 i915_vma_unpin_fence(vma);
2257 i915_gem_object_unpin_from_display_plane(vma);
2258 }
2259
2260 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation)
2262 {
2263 if (intel_rotation_90_or_270(rotation))
2264 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2265 else
2266 return fb->pitches[plane];
2267 }
2268
2269 /*
2270 * Convert the x/y offsets into a linear offset.
2271 * Only valid with 0/180 degree rotation, which is fine since linear
2272 * offset is only used with linear buffers on pre-hsw and tiled buffers
2273 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274 */
2275 u32 intel_fb_xy_to_linear(int x, int y,
2276 const struct intel_plane_state *state,
2277 int plane)
2278 {
2279 const struct drm_framebuffer *fb = state->base.fb;
2280 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2281 unsigned int pitch = fb->pitches[plane];
2282
2283 return y * pitch + x * cpp;
2284 }
2285
2286 /*
2287 * Add the x/y offsets derived from fb->offsets[] to the user
2288 * specified plane src x/y offsets. The resulting x/y offsets
2289 * specify the start of scanout from the beginning of the gtt mapping.
2290 */
2291 void intel_add_fb_offsets(int *x, int *y,
2292 const struct intel_plane_state *state,
2293 int plane)
2294
2295 {
2296 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2297 unsigned int rotation = state->base.rotation;
2298
2299 if (intel_rotation_90_or_270(rotation)) {
2300 *x += intel_fb->rotated[plane].x;
2301 *y += intel_fb->rotated[plane].y;
2302 } else {
2303 *x += intel_fb->normal[plane].x;
2304 *y += intel_fb->normal[plane].y;
2305 }
2306 }
2307
2308 /*
2309 * Input tile dimensions and pitch must already be
2310 * rotated to match x and y, and in pixel units.
2311 */
2312 static u32 _intel_adjust_tile_offset(int *x, int *y,
2313 unsigned int tile_width,
2314 unsigned int tile_height,
2315 unsigned int tile_size,
2316 unsigned int pitch_tiles,
2317 u32 old_offset,
2318 u32 new_offset)
2319 {
2320 unsigned int pitch_pixels = pitch_tiles * tile_width;
2321 unsigned int tiles;
2322
2323 WARN_ON(old_offset & (tile_size - 1));
2324 WARN_ON(new_offset & (tile_size - 1));
2325 WARN_ON(new_offset > old_offset);
2326
2327 tiles = (old_offset - new_offset) / tile_size;
2328
2329 *y += tiles / pitch_tiles * tile_height;
2330 *x += tiles % pitch_tiles * tile_width;
2331
2332 /* minimize x in case it got needlessly big */
2333 *y += *x / pitch_pixels * tile_height;
2334 *x %= pitch_pixels;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Adjust the tile offset by moving the difference into
2341 * the x/y offsets.
2342 */
2343 static u32 intel_adjust_tile_offset(int *x, int *y,
2344 const struct intel_plane_state *state, int plane,
2345 u32 old_offset, u32 new_offset)
2346 {
2347 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2348 const struct drm_framebuffer *fb = state->base.fb;
2349 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2350 unsigned int rotation = state->base.rotation;
2351 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2352
2353 WARN_ON(new_offset > old_offset);
2354
2355 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2361 fb->modifier[plane], cpp);
2362
2363 if (intel_rotation_90_or_270(rotation)) {
2364 pitch_tiles = pitch / tile_height;
2365 swap(tile_width, tile_height);
2366 } else {
2367 pitch_tiles = pitch / (tile_width * cpp);
2368 }
2369
2370 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2371 tile_size, pitch_tiles,
2372 old_offset, new_offset);
2373 } else {
2374 old_offset += *y * pitch + *x * cpp;
2375
2376 *y = (old_offset - new_offset) / pitch;
2377 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2378 }
2379
2380 return new_offset;
2381 }
2382
2383 /*
2384 * Computes the linear offset to the base tile and adjusts
2385 * x, y. bytes per pixel is assumed to be a power-of-two.
2386 *
2387 * In the 90/270 rotated case, x and y are assumed
2388 * to be already rotated to match the rotated GTT view, and
2389 * pitch is the tile_height aligned framebuffer height.
2390 *
2391 * This function is used when computing the derived information
2392 * under intel_framebuffer, so using any of that information
2393 * here is not allowed. Anything under drm_framebuffer can be
2394 * used. This is why the user has to pass in the pitch since it
2395 * is specified in the rotated orientation.
2396 */
2397 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2398 int *x, int *y,
2399 const struct drm_framebuffer *fb, int plane,
2400 unsigned int pitch,
2401 unsigned int rotation,
2402 u32 alignment)
2403 {
2404 uint64_t fb_modifier = fb->modifier[plane];
2405 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2406 u32 offset, offset_aligned;
2407
2408 if (alignment)
2409 alignment--;
2410
2411 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2412 unsigned int tile_size, tile_width, tile_height;
2413 unsigned int tile_rows, tiles, pitch_tiles;
2414
2415 tile_size = intel_tile_size(dev_priv);
2416 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2417 fb_modifier, cpp);
2418
2419 if (intel_rotation_90_or_270(rotation)) {
2420 pitch_tiles = pitch / tile_height;
2421 swap(tile_width, tile_height);
2422 } else {
2423 pitch_tiles = pitch / (tile_width * cpp);
2424 }
2425
2426 tile_rows = *y / tile_height;
2427 *y %= tile_height;
2428
2429 tiles = *x / tile_width;
2430 *x %= tile_width;
2431
2432 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2433 offset_aligned = offset & ~alignment;
2434
2435 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2436 tile_size, pitch_tiles,
2437 offset, offset_aligned);
2438 } else {
2439 offset = *y * pitch + *x * cpp;
2440 offset_aligned = offset & ~alignment;
2441
2442 *y = (offset & alignment) / pitch;
2443 *x = ((offset & alignment) - *y * pitch) / cpp;
2444 }
2445
2446 return offset_aligned;
2447 }
2448
2449 u32 intel_compute_tile_offset(int *x, int *y,
2450 const struct intel_plane_state *state,
2451 int plane)
2452 {
2453 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2454 const struct drm_framebuffer *fb = state->base.fb;
2455 unsigned int rotation = state->base.rotation;
2456 int pitch = intel_fb_pitch(fb, plane, rotation);
2457 u32 alignment;
2458
2459 /* AUX_DIST needs only 4K alignment */
2460 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2461 alignment = 4096;
2462 else
2463 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2464
2465 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2466 rotation, alignment);
2467 }
2468
2469 /* Convert the fb->offset[] linear offset into x/y offsets */
2470 static void intel_fb_offset_to_xy(int *x, int *y,
2471 const struct drm_framebuffer *fb, int plane)
2472 {
2473 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2474 unsigned int pitch = fb->pitches[plane];
2475 u32 linear_offset = fb->offsets[plane];
2476
2477 *y = linear_offset / pitch;
2478 *x = linear_offset % pitch / cpp;
2479 }
2480
2481 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2482 {
2483 switch (fb_modifier) {
2484 case I915_FORMAT_MOD_X_TILED:
2485 return I915_TILING_X;
2486 case I915_FORMAT_MOD_Y_TILED:
2487 return I915_TILING_Y;
2488 default:
2489 return I915_TILING_NONE;
2490 }
2491 }
2492
2493 static int
2494 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2495 struct drm_framebuffer *fb)
2496 {
2497 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2498 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2499 u32 gtt_offset_rotated = 0;
2500 unsigned int max_size = 0;
2501 uint32_t format = fb->pixel_format;
2502 int i, num_planes = drm_format_num_planes(format);
2503 unsigned int tile_size = intel_tile_size(dev_priv);
2504
2505 for (i = 0; i < num_planes; i++) {
2506 unsigned int width, height;
2507 unsigned int cpp, size;
2508 u32 offset;
2509 int x, y;
2510
2511 cpp = drm_format_plane_cpp(format, i);
2512 width = drm_format_plane_width(fb->width, format, i);
2513 height = drm_format_plane_height(fb->height, format, i);
2514
2515 intel_fb_offset_to_xy(&x, &y, fb, i);
2516
2517 /*
2518 * The fence (if used) is aligned to the start of the object
2519 * so having the framebuffer wrap around across the edge of the
2520 * fenced region doesn't really work. We have no API to configure
2521 * the fence start offset within the object (nor could we probably
2522 * on gen2/3). So it's just easier if we just require that the
2523 * fb layout agrees with the fence layout. We already check that the
2524 * fb stride matches the fence stride elsewhere.
2525 */
2526 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2527 (x + width) * cpp > fb->pitches[i]) {
2528 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2529 i, fb->offsets[i]);
2530 return -EINVAL;
2531 }
2532
2533 /*
2534 * First pixel of the framebuffer from
2535 * the start of the normal gtt mapping.
2536 */
2537 intel_fb->normal[i].x = x;
2538 intel_fb->normal[i].y = y;
2539
2540 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2541 fb, 0, fb->pitches[i],
2542 DRM_ROTATE_0, tile_size);
2543 offset /= tile_size;
2544
2545 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2546 unsigned int tile_width, tile_height;
2547 unsigned int pitch_tiles;
2548 struct drm_rect r;
2549
2550 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2551 fb->modifier[i], cpp);
2552
2553 rot_info->plane[i].offset = offset;
2554 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2555 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2556 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2557
2558 intel_fb->rotated[i].pitch =
2559 rot_info->plane[i].height * tile_height;
2560
2561 /* how many tiles does this plane need */
2562 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2563 /*
2564 * If the plane isn't horizontally tile aligned,
2565 * we need one more tile.
2566 */
2567 if (x != 0)
2568 size++;
2569
2570 /* rotate the x/y offsets to match the GTT view */
2571 r.x1 = x;
2572 r.y1 = y;
2573 r.x2 = x + width;
2574 r.y2 = y + height;
2575 drm_rect_rotate(&r,
2576 rot_info->plane[i].width * tile_width,
2577 rot_info->plane[i].height * tile_height,
2578 DRM_ROTATE_270);
2579 x = r.x1;
2580 y = r.y1;
2581
2582 /* rotate the tile dimensions to match the GTT view */
2583 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2584 swap(tile_width, tile_height);
2585
2586 /*
2587 * We only keep the x/y offsets, so push all of the
2588 * gtt offset into the x/y offsets.
2589 */
2590 _intel_adjust_tile_offset(&x, &y, tile_size,
2591 tile_width, tile_height, pitch_tiles,
2592 gtt_offset_rotated * tile_size, 0);
2593
2594 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2595
2596 /*
2597 * First pixel of the framebuffer from
2598 * the start of the rotated gtt mapping.
2599 */
2600 intel_fb->rotated[i].x = x;
2601 intel_fb->rotated[i].y = y;
2602 } else {
2603 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2604 x * cpp, tile_size);
2605 }
2606
2607 /* how many tiles in total needed in the bo */
2608 max_size = max(max_size, offset + size);
2609 }
2610
2611 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2612 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2613 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2614 return -EINVAL;
2615 }
2616
2617 return 0;
2618 }
2619
2620 static int i9xx_format_to_fourcc(int format)
2621 {
2622 switch (format) {
2623 case DISPPLANE_8BPP:
2624 return DRM_FORMAT_C8;
2625 case DISPPLANE_BGRX555:
2626 return DRM_FORMAT_XRGB1555;
2627 case DISPPLANE_BGRX565:
2628 return DRM_FORMAT_RGB565;
2629 default:
2630 case DISPPLANE_BGRX888:
2631 return DRM_FORMAT_XRGB8888;
2632 case DISPPLANE_RGBX888:
2633 return DRM_FORMAT_XBGR8888;
2634 case DISPPLANE_BGRX101010:
2635 return DRM_FORMAT_XRGB2101010;
2636 case DISPPLANE_RGBX101010:
2637 return DRM_FORMAT_XBGR2101010;
2638 }
2639 }
2640
2641 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2642 {
2643 switch (format) {
2644 case PLANE_CTL_FORMAT_RGB_565:
2645 return DRM_FORMAT_RGB565;
2646 default:
2647 case PLANE_CTL_FORMAT_XRGB_8888:
2648 if (rgb_order) {
2649 if (alpha)
2650 return DRM_FORMAT_ABGR8888;
2651 else
2652 return DRM_FORMAT_XBGR8888;
2653 } else {
2654 if (alpha)
2655 return DRM_FORMAT_ARGB8888;
2656 else
2657 return DRM_FORMAT_XRGB8888;
2658 }
2659 case PLANE_CTL_FORMAT_XRGB_2101010:
2660 if (rgb_order)
2661 return DRM_FORMAT_XBGR2101010;
2662 else
2663 return DRM_FORMAT_XRGB2101010;
2664 }
2665 }
2666
2667 static bool
2668 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2669 struct intel_initial_plane_config *plane_config)
2670 {
2671 struct drm_device *dev = crtc->base.dev;
2672 struct drm_i915_private *dev_priv = to_i915(dev);
2673 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2674 struct drm_i915_gem_object *obj = NULL;
2675 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2676 struct drm_framebuffer *fb = &plane_config->fb->base;
2677 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2678 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2679 PAGE_SIZE);
2680
2681 size_aligned -= base_aligned;
2682
2683 if (plane_config->size == 0)
2684 return false;
2685
2686 /* If the FB is too big, just don't use it since fbdev is not very
2687 * important and we should probably use that space with FBC or other
2688 * features. */
2689 if (size_aligned * 2 > ggtt->stolen_usable_size)
2690 return false;
2691
2692 mutex_lock(&dev->struct_mutex);
2693
2694 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2695 base_aligned,
2696 base_aligned,
2697 size_aligned);
2698 if (!obj) {
2699 mutex_unlock(&dev->struct_mutex);
2700 return false;
2701 }
2702
2703 if (plane_config->tiling == I915_TILING_X)
2704 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2705
2706 mode_cmd.pixel_format = fb->pixel_format;
2707 mode_cmd.width = fb->width;
2708 mode_cmd.height = fb->height;
2709 mode_cmd.pitches[0] = fb->pitches[0];
2710 mode_cmd.modifier[0] = fb->modifier[0];
2711 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2712
2713 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2714 &mode_cmd, obj)) {
2715 DRM_DEBUG_KMS("intel fb init failed\n");
2716 goto out_unref_obj;
2717 }
2718
2719 mutex_unlock(&dev->struct_mutex);
2720
2721 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2722 return true;
2723
2724 out_unref_obj:
2725 i915_gem_object_put(obj);
2726 mutex_unlock(&dev->struct_mutex);
2727 return false;
2728 }
2729
2730 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 static void
2732 update_state_fb(struct drm_plane *plane)
2733 {
2734 if (plane->fb == plane->state->fb)
2735 return;
2736
2737 if (plane->state->fb)
2738 drm_framebuffer_unreference(plane->state->fb);
2739 plane->state->fb = plane->fb;
2740 if (plane->state->fb)
2741 drm_framebuffer_reference(plane->state->fb);
2742 }
2743
2744 static void
2745 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2746 struct intel_initial_plane_config *plane_config)
2747 {
2748 struct drm_device *dev = intel_crtc->base.dev;
2749 struct drm_i915_private *dev_priv = to_i915(dev);
2750 struct drm_crtc *c;
2751 struct intel_crtc *i;
2752 struct drm_i915_gem_object *obj;
2753 struct drm_plane *primary = intel_crtc->base.primary;
2754 struct drm_plane_state *plane_state = primary->state;
2755 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2756 struct intel_plane *intel_plane = to_intel_plane(primary);
2757 struct intel_plane_state *intel_state =
2758 to_intel_plane_state(plane_state);
2759 struct drm_framebuffer *fb;
2760
2761 if (!plane_config->fb)
2762 return;
2763
2764 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2765 fb = &plane_config->fb->base;
2766 goto valid_fb;
2767 }
2768
2769 kfree(plane_config->fb);
2770
2771 /*
2772 * Failed to alloc the obj, check to see if we should share
2773 * an fb with another CRTC instead
2774 */
2775 for_each_crtc(dev, c) {
2776 i = to_intel_crtc(c);
2777
2778 if (c == &intel_crtc->base)
2779 continue;
2780
2781 if (!i->active)
2782 continue;
2783
2784 fb = c->primary->fb;
2785 if (!fb)
2786 continue;
2787
2788 obj = intel_fb_obj(fb);
2789 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2790 drm_framebuffer_reference(fb);
2791 goto valid_fb;
2792 }
2793 }
2794
2795 /*
2796 * We've failed to reconstruct the BIOS FB. Current display state
2797 * indicates that the primary plane is visible, but has a NULL FB,
2798 * which will lead to problems later if we don't fix it up. The
2799 * simplest solution is to just disable the primary plane now and
2800 * pretend the BIOS never had it enabled.
2801 */
2802 to_intel_plane_state(plane_state)->base.visible = false;
2803 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2804 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2805 intel_plane->disable_plane(primary, &intel_crtc->base);
2806
2807 return;
2808
2809 valid_fb:
2810 plane_state->src_x = 0;
2811 plane_state->src_y = 0;
2812 plane_state->src_w = fb->width << 16;
2813 plane_state->src_h = fb->height << 16;
2814
2815 plane_state->crtc_x = 0;
2816 plane_state->crtc_y = 0;
2817 plane_state->crtc_w = fb->width;
2818 plane_state->crtc_h = fb->height;
2819
2820 intel_state->base.src.x1 = plane_state->src_x;
2821 intel_state->base.src.y1 = plane_state->src_y;
2822 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2823 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2824 intel_state->base.dst.x1 = plane_state->crtc_x;
2825 intel_state->base.dst.y1 = plane_state->crtc_y;
2826 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2827 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2828
2829 obj = intel_fb_obj(fb);
2830 if (i915_gem_object_is_tiled(obj))
2831 dev_priv->preserve_bios_swizzle = true;
2832
2833 drm_framebuffer_reference(fb);
2834 primary->fb = primary->state->fb = fb;
2835 primary->crtc = primary->state->crtc = &intel_crtc->base;
2836 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2837 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2838 &obj->frontbuffer_bits);
2839 }
2840
2841 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2842 unsigned int rotation)
2843 {
2844 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2845
2846 switch (fb->modifier[plane]) {
2847 case DRM_FORMAT_MOD_NONE:
2848 case I915_FORMAT_MOD_X_TILED:
2849 switch (cpp) {
2850 case 8:
2851 return 4096;
2852 case 4:
2853 case 2:
2854 case 1:
2855 return 8192;
2856 default:
2857 MISSING_CASE(cpp);
2858 break;
2859 }
2860 break;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 case I915_FORMAT_MOD_Yf_TILED:
2863 switch (cpp) {
2864 case 8:
2865 return 2048;
2866 case 4:
2867 return 4096;
2868 case 2:
2869 case 1:
2870 return 8192;
2871 default:
2872 MISSING_CASE(cpp);
2873 break;
2874 }
2875 break;
2876 default:
2877 MISSING_CASE(fb->modifier[plane]);
2878 }
2879
2880 return 2048;
2881 }
2882
2883 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2884 {
2885 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2886 const struct drm_framebuffer *fb = plane_state->base.fb;
2887 unsigned int rotation = plane_state->base.rotation;
2888 int x = plane_state->base.src.x1 >> 16;
2889 int y = plane_state->base.src.y1 >> 16;
2890 int w = drm_rect_width(&plane_state->base.src) >> 16;
2891 int h = drm_rect_height(&plane_state->base.src) >> 16;
2892 int max_width = skl_max_plane_width(fb, 0, rotation);
2893 int max_height = 4096;
2894 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2895
2896 if (w > max_width || h > max_height) {
2897 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2898 w, h, max_width, max_height);
2899 return -EINVAL;
2900 }
2901
2902 intel_add_fb_offsets(&x, &y, plane_state, 0);
2903 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2904
2905 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2906
2907 /*
2908 * AUX surface offset is specified as the distance from the
2909 * main surface offset, and it must be non-negative. Make
2910 * sure that is what we will get.
2911 */
2912 if (offset > aux_offset)
2913 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2914 offset, aux_offset & ~(alignment - 1));
2915
2916 /*
2917 * When using an X-tiled surface, the plane blows up
2918 * if the x offset + width exceed the stride.
2919 *
2920 * TODO: linear and Y-tiled seem fine, Yf untested,
2921 */
2922 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2923 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2924
2925 while ((x + w) * cpp > fb->pitches[0]) {
2926 if (offset == 0) {
2927 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2928 return -EINVAL;
2929 }
2930
2931 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2932 offset, offset - alignment);
2933 }
2934 }
2935
2936 plane_state->main.offset = offset;
2937 plane_state->main.x = x;
2938 plane_state->main.y = y;
2939
2940 return 0;
2941 }
2942
2943 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2944 {
2945 const struct drm_framebuffer *fb = plane_state->base.fb;
2946 unsigned int rotation = plane_state->base.rotation;
2947 int max_width = skl_max_plane_width(fb, 1, rotation);
2948 int max_height = 4096;
2949 int x = plane_state->base.src.x1 >> 17;
2950 int y = plane_state->base.src.y1 >> 17;
2951 int w = drm_rect_width(&plane_state->base.src) >> 17;
2952 int h = drm_rect_height(&plane_state->base.src) >> 17;
2953 u32 offset;
2954
2955 intel_add_fb_offsets(&x, &y, plane_state, 1);
2956 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2957
2958 /* FIXME not quite sure how/if these apply to the chroma plane */
2959 if (w > max_width || h > max_height) {
2960 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2961 w, h, max_width, max_height);
2962 return -EINVAL;
2963 }
2964
2965 plane_state->aux.offset = offset;
2966 plane_state->aux.x = x;
2967 plane_state->aux.y = y;
2968
2969 return 0;
2970 }
2971
2972 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2973 {
2974 const struct drm_framebuffer *fb = plane_state->base.fb;
2975 unsigned int rotation = plane_state->base.rotation;
2976 int ret;
2977
2978 /* Rotate src coordinates to match rotated GTT view */
2979 if (intel_rotation_90_or_270(rotation))
2980 drm_rect_rotate(&plane_state->base.src,
2981 fb->width, fb->height, DRM_ROTATE_270);
2982
2983 /*
2984 * Handle the AUX surface first since
2985 * the main surface setup depends on it.
2986 */
2987 if (fb->pixel_format == DRM_FORMAT_NV12) {
2988 ret = skl_check_nv12_aux_surface(plane_state);
2989 if (ret)
2990 return ret;
2991 } else {
2992 plane_state->aux.offset = ~0xfff;
2993 plane_state->aux.x = 0;
2994 plane_state->aux.y = 0;
2995 }
2996
2997 ret = skl_check_main_surface(plane_state);
2998 if (ret)
2999 return ret;
3000
3001 return 0;
3002 }
3003
3004 static void i9xx_update_primary_plane(struct drm_plane *primary,
3005 const struct intel_crtc_state *crtc_state,
3006 const struct intel_plane_state *plane_state)
3007 {
3008 struct drm_device *dev = primary->dev;
3009 struct drm_i915_private *dev_priv = to_i915(dev);
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3011 struct drm_framebuffer *fb = plane_state->base.fb;
3012 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3013 int plane = intel_crtc->plane;
3014 u32 linear_offset;
3015 u32 dspcntr;
3016 i915_reg_t reg = DSPCNTR(plane);
3017 unsigned int rotation = plane_state->base.rotation;
3018 int x = plane_state->base.src.x1 >> 16;
3019 int y = plane_state->base.src.y1 >> 16;
3020
3021 dspcntr = DISPPLANE_GAMMA_ENABLE;
3022
3023 dspcntr |= DISPLAY_PLANE_ENABLE;
3024
3025 if (INTEL_INFO(dev)->gen < 4) {
3026 if (intel_crtc->pipe == PIPE_B)
3027 dspcntr |= DISPPLANE_SEL_PIPE_B;
3028
3029 /* pipesrc and dspsize control the size that is scaled from,
3030 * which should always be the user's requested size.
3031 */
3032 I915_WRITE(DSPSIZE(plane),
3033 ((crtc_state->pipe_src_h - 1) << 16) |
3034 (crtc_state->pipe_src_w - 1));
3035 I915_WRITE(DSPPOS(plane), 0);
3036 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3037 I915_WRITE(PRIMSIZE(plane),
3038 ((crtc_state->pipe_src_h - 1) << 16) |
3039 (crtc_state->pipe_src_w - 1));
3040 I915_WRITE(PRIMPOS(plane), 0);
3041 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3042 }
3043
3044 switch (fb->pixel_format) {
3045 case DRM_FORMAT_C8:
3046 dspcntr |= DISPPLANE_8BPP;
3047 break;
3048 case DRM_FORMAT_XRGB1555:
3049 dspcntr |= DISPPLANE_BGRX555;
3050 break;
3051 case DRM_FORMAT_RGB565:
3052 dspcntr |= DISPPLANE_BGRX565;
3053 break;
3054 case DRM_FORMAT_XRGB8888:
3055 dspcntr |= DISPPLANE_BGRX888;
3056 break;
3057 case DRM_FORMAT_XBGR8888:
3058 dspcntr |= DISPPLANE_RGBX888;
3059 break;
3060 case DRM_FORMAT_XRGB2101010:
3061 dspcntr |= DISPPLANE_BGRX101010;
3062 break;
3063 case DRM_FORMAT_XBGR2101010:
3064 dspcntr |= DISPPLANE_RGBX101010;
3065 break;
3066 default:
3067 BUG();
3068 }
3069
3070 if (INTEL_GEN(dev_priv) >= 4 &&
3071 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3072 dspcntr |= DISPPLANE_TILED;
3073
3074 if (IS_G4X(dev))
3075 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3076
3077 intel_add_fb_offsets(&x, &y, plane_state, 0);
3078
3079 if (INTEL_INFO(dev)->gen >= 4)
3080 intel_crtc->dspaddr_offset =
3081 intel_compute_tile_offset(&x, &y, plane_state, 0);
3082
3083 if (rotation == DRM_ROTATE_180) {
3084 dspcntr |= DISPPLANE_ROTATE_180;
3085
3086 x += (crtc_state->pipe_src_w - 1);
3087 y += (crtc_state->pipe_src_h - 1);
3088 }
3089
3090 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3091
3092 if (INTEL_INFO(dev)->gen < 4)
3093 intel_crtc->dspaddr_offset = linear_offset;
3094
3095 intel_crtc->adjusted_x = x;
3096 intel_crtc->adjusted_y = y;
3097
3098 I915_WRITE(reg, dspcntr);
3099
3100 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3101 if (INTEL_INFO(dev)->gen >= 4) {
3102 I915_WRITE(DSPSURF(plane),
3103 intel_fb_gtt_offset(fb, rotation) +
3104 intel_crtc->dspaddr_offset);
3105 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3106 I915_WRITE(DSPLINOFF(plane), linear_offset);
3107 } else
3108 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3109 POSTING_READ(reg);
3110 }
3111
3112 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3113 struct drm_crtc *crtc)
3114 {
3115 struct drm_device *dev = crtc->dev;
3116 struct drm_i915_private *dev_priv = to_i915(dev);
3117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118 int plane = intel_crtc->plane;
3119
3120 I915_WRITE(DSPCNTR(plane), 0);
3121 if (INTEL_INFO(dev_priv)->gen >= 4)
3122 I915_WRITE(DSPSURF(plane), 0);
3123 else
3124 I915_WRITE(DSPADDR(plane), 0);
3125 POSTING_READ(DSPCNTR(plane));
3126 }
3127
3128 static void ironlake_update_primary_plane(struct drm_plane *primary,
3129 const struct intel_crtc_state *crtc_state,
3130 const struct intel_plane_state *plane_state)
3131 {
3132 struct drm_device *dev = primary->dev;
3133 struct drm_i915_private *dev_priv = to_i915(dev);
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3135 struct drm_framebuffer *fb = plane_state->base.fb;
3136 int plane = intel_crtc->plane;
3137 u32 linear_offset;
3138 u32 dspcntr;
3139 i915_reg_t reg = DSPCNTR(plane);
3140 unsigned int rotation = plane_state->base.rotation;
3141 int x = plane_state->base.src.x1 >> 16;
3142 int y = plane_state->base.src.y1 >> 16;
3143
3144 dspcntr = DISPPLANE_GAMMA_ENABLE;
3145 dspcntr |= DISPLAY_PLANE_ENABLE;
3146
3147 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3148 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3149
3150 switch (fb->pixel_format) {
3151 case DRM_FORMAT_C8:
3152 dspcntr |= DISPPLANE_8BPP;
3153 break;
3154 case DRM_FORMAT_RGB565:
3155 dspcntr |= DISPPLANE_BGRX565;
3156 break;
3157 case DRM_FORMAT_XRGB8888:
3158 dspcntr |= DISPPLANE_BGRX888;
3159 break;
3160 case DRM_FORMAT_XBGR8888:
3161 dspcntr |= DISPPLANE_RGBX888;
3162 break;
3163 case DRM_FORMAT_XRGB2101010:
3164 dspcntr |= DISPPLANE_BGRX101010;
3165 break;
3166 case DRM_FORMAT_XBGR2101010:
3167 dspcntr |= DISPPLANE_RGBX101010;
3168 break;
3169 default:
3170 BUG();
3171 }
3172
3173 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3174 dspcntr |= DISPPLANE_TILED;
3175
3176 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3177 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3178
3179 intel_add_fb_offsets(&x, &y, plane_state, 0);
3180
3181 intel_crtc->dspaddr_offset =
3182 intel_compute_tile_offset(&x, &y, plane_state, 0);
3183
3184 if (rotation == DRM_ROTATE_180) {
3185 dspcntr |= DISPPLANE_ROTATE_180;
3186
3187 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3188 x += (crtc_state->pipe_src_w - 1);
3189 y += (crtc_state->pipe_src_h - 1);
3190 }
3191 }
3192
3193 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3194
3195 intel_crtc->adjusted_x = x;
3196 intel_crtc->adjusted_y = y;
3197
3198 I915_WRITE(reg, dspcntr);
3199
3200 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3201 I915_WRITE(DSPSURF(plane),
3202 intel_fb_gtt_offset(fb, rotation) +
3203 intel_crtc->dspaddr_offset);
3204 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3205 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3206 } else {
3207 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3208 I915_WRITE(DSPLINOFF(plane), linear_offset);
3209 }
3210 POSTING_READ(reg);
3211 }
3212
3213 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3214 uint64_t fb_modifier, uint32_t pixel_format)
3215 {
3216 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3217 return 64;
3218 } else {
3219 int cpp = drm_format_plane_cpp(pixel_format, 0);
3220
3221 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3222 }
3223 }
3224
3225 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3226 unsigned int rotation)
3227 {
3228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3229 struct i915_ggtt_view view;
3230 struct i915_vma *vma;
3231
3232 intel_fill_fb_ggtt_view(&view, fb, rotation);
3233
3234 vma = i915_gem_object_to_ggtt(obj, &view);
3235 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3236 view.type))
3237 return -1;
3238
3239 return i915_ggtt_offset(vma);
3240 }
3241
3242 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3243 {
3244 struct drm_device *dev = intel_crtc->base.dev;
3245 struct drm_i915_private *dev_priv = to_i915(dev);
3246
3247 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3248 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3249 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3250 }
3251
3252 /*
3253 * This function detaches (aka. unbinds) unused scalers in hardware
3254 */
3255 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3256 {
3257 struct intel_crtc_scaler_state *scaler_state;
3258 int i;
3259
3260 scaler_state = &intel_crtc->config->scaler_state;
3261
3262 /* loop through and disable scalers that aren't in use */
3263 for (i = 0; i < intel_crtc->num_scalers; i++) {
3264 if (!scaler_state->scalers[i].in_use)
3265 skl_detach_scaler(intel_crtc, i);
3266 }
3267 }
3268
3269 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3270 unsigned int rotation)
3271 {
3272 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3273 u32 stride = intel_fb_pitch(fb, plane, rotation);
3274
3275 /*
3276 * The stride is either expressed as a multiple of 64 bytes chunks for
3277 * linear buffers or in number of tiles for tiled buffers.
3278 */
3279 if (intel_rotation_90_or_270(rotation)) {
3280 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3281
3282 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3283 } else {
3284 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3285 fb->pixel_format);
3286 }
3287
3288 return stride;
3289 }
3290
3291 u32 skl_plane_ctl_format(uint32_t pixel_format)
3292 {
3293 switch (pixel_format) {
3294 case DRM_FORMAT_C8:
3295 return PLANE_CTL_FORMAT_INDEXED;
3296 case DRM_FORMAT_RGB565:
3297 return PLANE_CTL_FORMAT_RGB_565;
3298 case DRM_FORMAT_XBGR8888:
3299 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3300 case DRM_FORMAT_XRGB8888:
3301 return PLANE_CTL_FORMAT_XRGB_8888;
3302 /*
3303 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3304 * to be already pre-multiplied. We need to add a knob (or a different
3305 * DRM_FORMAT) for user-space to configure that.
3306 */
3307 case DRM_FORMAT_ABGR8888:
3308 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3309 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3310 case DRM_FORMAT_ARGB8888:
3311 return PLANE_CTL_FORMAT_XRGB_8888 |
3312 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3313 case DRM_FORMAT_XRGB2101010:
3314 return PLANE_CTL_FORMAT_XRGB_2101010;
3315 case DRM_FORMAT_XBGR2101010:
3316 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3317 case DRM_FORMAT_YUYV:
3318 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3319 case DRM_FORMAT_YVYU:
3320 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3321 case DRM_FORMAT_UYVY:
3322 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3323 case DRM_FORMAT_VYUY:
3324 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3325 default:
3326 MISSING_CASE(pixel_format);
3327 }
3328
3329 return 0;
3330 }
3331
3332 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3333 {
3334 switch (fb_modifier) {
3335 case DRM_FORMAT_MOD_NONE:
3336 break;
3337 case I915_FORMAT_MOD_X_TILED:
3338 return PLANE_CTL_TILED_X;
3339 case I915_FORMAT_MOD_Y_TILED:
3340 return PLANE_CTL_TILED_Y;
3341 case I915_FORMAT_MOD_Yf_TILED:
3342 return PLANE_CTL_TILED_YF;
3343 default:
3344 MISSING_CASE(fb_modifier);
3345 }
3346
3347 return 0;
3348 }
3349
3350 u32 skl_plane_ctl_rotation(unsigned int rotation)
3351 {
3352 switch (rotation) {
3353 case DRM_ROTATE_0:
3354 break;
3355 /*
3356 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3357 * while i915 HW rotation is clockwise, thats why this swapping.
3358 */
3359 case DRM_ROTATE_90:
3360 return PLANE_CTL_ROTATE_270;
3361 case DRM_ROTATE_180:
3362 return PLANE_CTL_ROTATE_180;
3363 case DRM_ROTATE_270:
3364 return PLANE_CTL_ROTATE_90;
3365 default:
3366 MISSING_CASE(rotation);
3367 }
3368
3369 return 0;
3370 }
3371
3372 static void skylake_update_primary_plane(struct drm_plane *plane,
3373 const struct intel_crtc_state *crtc_state,
3374 const struct intel_plane_state *plane_state)
3375 {
3376 struct drm_device *dev = plane->dev;
3377 struct drm_i915_private *dev_priv = to_i915(dev);
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3379 struct drm_framebuffer *fb = plane_state->base.fb;
3380 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3381 int pipe = intel_crtc->pipe;
3382 u32 plane_ctl;
3383 unsigned int rotation = plane_state->base.rotation;
3384 u32 stride = skl_plane_stride(fb, 0, rotation);
3385 u32 surf_addr = plane_state->main.offset;
3386 int scaler_id = plane_state->scaler_id;
3387 int src_x = plane_state->main.x;
3388 int src_y = plane_state->main.y;
3389 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3390 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3391 int dst_x = plane_state->base.dst.x1;
3392 int dst_y = plane_state->base.dst.y1;
3393 int dst_w = drm_rect_width(&plane_state->base.dst);
3394 int dst_h = drm_rect_height(&plane_state->base.dst);
3395
3396 plane_ctl = PLANE_CTL_ENABLE |
3397 PLANE_CTL_PIPE_GAMMA_ENABLE |
3398 PLANE_CTL_PIPE_CSC_ENABLE;
3399
3400 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3401 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3402 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3403 plane_ctl |= skl_plane_ctl_rotation(rotation);
3404
3405 /* Sizes are 0 based */
3406 src_w--;
3407 src_h--;
3408 dst_w--;
3409 dst_h--;
3410
3411 intel_crtc->adjusted_x = src_x;
3412 intel_crtc->adjusted_y = src_y;
3413
3414 if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3415 skl_write_plane_wm(intel_crtc, wm, 0);
3416
3417 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3418 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3419 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3420 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3421
3422 if (scaler_id >= 0) {
3423 uint32_t ps_ctrl = 0;
3424
3425 WARN_ON(!dst_w || !dst_h);
3426 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3427 crtc_state->scaler_state.scalers[scaler_id].mode;
3428 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3429 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3430 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3431 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3432 I915_WRITE(PLANE_POS(pipe, 0), 0);
3433 } else {
3434 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3435 }
3436
3437 I915_WRITE(PLANE_SURF(pipe, 0),
3438 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3439
3440 POSTING_READ(PLANE_SURF(pipe, 0));
3441 }
3442
3443 static void skylake_disable_primary_plane(struct drm_plane *primary,
3444 struct drm_crtc *crtc)
3445 {
3446 struct drm_device *dev = crtc->dev;
3447 struct drm_i915_private *dev_priv = to_i915(dev);
3448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449 int pipe = intel_crtc->pipe;
3450
3451 /*
3452 * We only populate skl_results on watermark updates, and if the
3453 * plane's visiblity isn't actually changing neither is its watermarks.
3454 */
3455 if (!crtc->primary->state->visible)
3456 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3457
3458 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3459 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3460 POSTING_READ(PLANE_SURF(pipe, 0));
3461 }
3462
3463 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3464 static int
3465 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3466 int x, int y, enum mode_set_atomic state)
3467 {
3468 /* Support for kgdboc is disabled, this needs a major rework. */
3469 DRM_ERROR("legacy panic handler not supported any more.\n");
3470
3471 return -ENODEV;
3472 }
3473
3474 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3475 {
3476 struct intel_crtc *crtc;
3477
3478 for_each_intel_crtc(&dev_priv->drm, crtc)
3479 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3480 }
3481
3482 static void intel_update_primary_planes(struct drm_device *dev)
3483 {
3484 struct drm_crtc *crtc;
3485
3486 for_each_crtc(dev, crtc) {
3487 struct intel_plane *plane = to_intel_plane(crtc->primary);
3488 struct intel_plane_state *plane_state =
3489 to_intel_plane_state(plane->base.state);
3490
3491 if (plane_state->base.visible)
3492 plane->update_plane(&plane->base,
3493 to_intel_crtc_state(crtc->state),
3494 plane_state);
3495 }
3496 }
3497
3498 static int
3499 __intel_display_resume(struct drm_device *dev,
3500 struct drm_atomic_state *state)
3501 {
3502 struct drm_crtc_state *crtc_state;
3503 struct drm_crtc *crtc;
3504 int i, ret;
3505
3506 intel_modeset_setup_hw_state(dev);
3507 i915_redisable_vga(dev);
3508
3509 if (!state)
3510 return 0;
3511
3512 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3513 /*
3514 * Force recalculation even if we restore
3515 * current state. With fast modeset this may not result
3516 * in a modeset when the state is compatible.
3517 */
3518 crtc_state->mode_changed = true;
3519 }
3520
3521 /* ignore any reset values/BIOS leftovers in the WM registers */
3522 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3523
3524 ret = drm_atomic_commit(state);
3525
3526 WARN_ON(ret == -EDEADLK);
3527 return ret;
3528 }
3529
3530 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3531 {
3532 return intel_has_gpu_reset(dev_priv) &&
3533 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3534 }
3535
3536 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3537 {
3538 struct drm_device *dev = &dev_priv->drm;
3539 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540 struct drm_atomic_state *state;
3541 int ret;
3542
3543 /*
3544 * Need mode_config.mutex so that we don't
3545 * trample ongoing ->detect() and whatnot.
3546 */
3547 mutex_lock(&dev->mode_config.mutex);
3548 drm_modeset_acquire_init(ctx, 0);
3549 while (1) {
3550 ret = drm_modeset_lock_all_ctx(dev, ctx);
3551 if (ret != -EDEADLK)
3552 break;
3553
3554 drm_modeset_backoff(ctx);
3555 }
3556
3557 /* reset doesn't touch the display, but flips might get nuked anyway, */
3558 if (!i915.force_reset_modeset_test &&
3559 !gpu_reset_clobbers_display(dev_priv))
3560 return;
3561
3562 /*
3563 * Disabling the crtcs gracefully seems nicer. Also the
3564 * g33 docs say we should at least disable all the planes.
3565 */
3566 state = drm_atomic_helper_duplicate_state(dev, ctx);
3567 if (IS_ERR(state)) {
3568 ret = PTR_ERR(state);
3569 state = NULL;
3570 DRM_ERROR("Duplicating state failed with %i\n", ret);
3571 goto err;
3572 }
3573
3574 ret = drm_atomic_helper_disable_all(dev, ctx);
3575 if (ret) {
3576 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3577 goto err;
3578 }
3579
3580 dev_priv->modeset_restore_state = state;
3581 state->acquire_ctx = ctx;
3582 return;
3583
3584 err:
3585 drm_atomic_state_free(state);
3586 }
3587
3588 void intel_finish_reset(struct drm_i915_private *dev_priv)
3589 {
3590 struct drm_device *dev = &dev_priv->drm;
3591 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3593 int ret;
3594
3595 /*
3596 * Flips in the rings will be nuked by the reset,
3597 * so complete all pending flips so that user space
3598 * will get its events and not get stuck.
3599 */
3600 intel_complete_page_flips(dev_priv);
3601
3602 dev_priv->modeset_restore_state = NULL;
3603
3604 dev_priv->modeset_restore_state = NULL;
3605
3606 /* reset doesn't touch the display */
3607 if (!gpu_reset_clobbers_display(dev_priv)) {
3608 if (!state) {
3609 /*
3610 * Flips in the rings have been nuked by the reset,
3611 * so update the base address of all primary
3612 * planes to the the last fb to make sure we're
3613 * showing the correct fb after a reset.
3614 *
3615 * FIXME: Atomic will make this obsolete since we won't schedule
3616 * CS-based flips (which might get lost in gpu resets) any more.
3617 */
3618 intel_update_primary_planes(dev);
3619 } else {
3620 ret = __intel_display_resume(dev, state);
3621 if (ret)
3622 DRM_ERROR("Restoring old state failed with %i\n", ret);
3623 }
3624 } else {
3625 /*
3626 * The display has been reset as well,
3627 * so need a full re-initialization.
3628 */
3629 intel_runtime_pm_disable_interrupts(dev_priv);
3630 intel_runtime_pm_enable_interrupts(dev_priv);
3631
3632 intel_modeset_init_hw(dev);
3633
3634 spin_lock_irq(&dev_priv->irq_lock);
3635 if (dev_priv->display.hpd_irq_setup)
3636 dev_priv->display.hpd_irq_setup(dev_priv);
3637 spin_unlock_irq(&dev_priv->irq_lock);
3638
3639 ret = __intel_display_resume(dev, state);
3640 if (ret)
3641 DRM_ERROR("Restoring old state failed with %i\n", ret);
3642
3643 intel_hpd_init(dev_priv);
3644 }
3645
3646 drm_modeset_drop_locks(ctx);
3647 drm_modeset_acquire_fini(ctx);
3648 mutex_unlock(&dev->mode_config.mutex);
3649 }
3650
3651 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3652 {
3653 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3654
3655 if (i915_reset_in_progress(error))
3656 return true;
3657
3658 if (crtc->reset_count != i915_reset_count(error))
3659 return true;
3660
3661 return false;
3662 }
3663
3664 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3665 {
3666 struct drm_device *dev = crtc->dev;
3667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3668 bool pending;
3669
3670 if (abort_flip_on_reset(intel_crtc))
3671 return false;
3672
3673 spin_lock_irq(&dev->event_lock);
3674 pending = to_intel_crtc(crtc)->flip_work != NULL;
3675 spin_unlock_irq(&dev->event_lock);
3676
3677 return pending;
3678 }
3679
3680 static void intel_update_pipe_config(struct intel_crtc *crtc,
3681 struct intel_crtc_state *old_crtc_state)
3682 {
3683 struct drm_device *dev = crtc->base.dev;
3684 struct drm_i915_private *dev_priv = to_i915(dev);
3685 struct intel_crtc_state *pipe_config =
3686 to_intel_crtc_state(crtc->base.state);
3687
3688 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3689 crtc->base.mode = crtc->base.state->mode;
3690
3691 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3692 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3693 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3694
3695 /*
3696 * Update pipe size and adjust fitter if needed: the reason for this is
3697 * that in compute_mode_changes we check the native mode (not the pfit
3698 * mode) to see if we can flip rather than do a full mode set. In the
3699 * fastboot case, we'll flip, but if we don't update the pipesrc and
3700 * pfit state, we'll end up with a big fb scanned out into the wrong
3701 * sized surface.
3702 */
3703
3704 I915_WRITE(PIPESRC(crtc->pipe),
3705 ((pipe_config->pipe_src_w - 1) << 16) |
3706 (pipe_config->pipe_src_h - 1));
3707
3708 /* on skylake this is done by detaching scalers */
3709 if (INTEL_INFO(dev)->gen >= 9) {
3710 skl_detach_scalers(crtc);
3711
3712 if (pipe_config->pch_pfit.enabled)
3713 skylake_pfit_enable(crtc);
3714 } else if (HAS_PCH_SPLIT(dev)) {
3715 if (pipe_config->pch_pfit.enabled)
3716 ironlake_pfit_enable(crtc);
3717 else if (old_crtc_state->pch_pfit.enabled)
3718 ironlake_pfit_disable(crtc, true);
3719 }
3720 }
3721
3722 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3723 {
3724 struct drm_device *dev = crtc->dev;
3725 struct drm_i915_private *dev_priv = to_i915(dev);
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727 int pipe = intel_crtc->pipe;
3728 i915_reg_t reg;
3729 u32 temp;
3730
3731 /* enable normal train */
3732 reg = FDI_TX_CTL(pipe);
3733 temp = I915_READ(reg);
3734 if (IS_IVYBRIDGE(dev)) {
3735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3736 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3737 } else {
3738 temp &= ~FDI_LINK_TRAIN_NONE;
3739 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3740 }
3741 I915_WRITE(reg, temp);
3742
3743 reg = FDI_RX_CTL(pipe);
3744 temp = I915_READ(reg);
3745 if (HAS_PCH_CPT(dev)) {
3746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3747 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3748 } else {
3749 temp &= ~FDI_LINK_TRAIN_NONE;
3750 temp |= FDI_LINK_TRAIN_NONE;
3751 }
3752 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3753
3754 /* wait one idle pattern time */
3755 POSTING_READ(reg);
3756 udelay(1000);
3757
3758 /* IVB wants error correction enabled */
3759 if (IS_IVYBRIDGE(dev))
3760 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3761 FDI_FE_ERRC_ENABLE);
3762 }
3763
3764 /* The FDI link training functions for ILK/Ibexpeak. */
3765 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3766 {
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = to_i915(dev);
3769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770 int pipe = intel_crtc->pipe;
3771 i915_reg_t reg;
3772 u32 temp, tries;
3773
3774 /* FDI needs bits from pipe first */
3775 assert_pipe_enabled(dev_priv, pipe);
3776
3777 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3778 for train result */
3779 reg = FDI_RX_IMR(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_RX_SYMBOL_LOCK;
3782 temp &= ~FDI_RX_BIT_LOCK;
3783 I915_WRITE(reg, temp);
3784 I915_READ(reg);
3785 udelay(150);
3786
3787 /* enable CPU FDI TX and PCH FDI RX */
3788 reg = FDI_TX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3791 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3792 temp &= ~FDI_LINK_TRAIN_NONE;
3793 temp |= FDI_LINK_TRAIN_PATTERN_1;
3794 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3795
3796 reg = FDI_RX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~FDI_LINK_TRAIN_NONE;
3799 temp |= FDI_LINK_TRAIN_PATTERN_1;
3800 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3801
3802 POSTING_READ(reg);
3803 udelay(150);
3804
3805 /* Ironlake workaround, enable clock pointer after FDI enable*/
3806 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3807 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3808 FDI_RX_PHASE_SYNC_POINTER_EN);
3809
3810 reg = FDI_RX_IIR(pipe);
3811 for (tries = 0; tries < 5; tries++) {
3812 temp = I915_READ(reg);
3813 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3814
3815 if ((temp & FDI_RX_BIT_LOCK)) {
3816 DRM_DEBUG_KMS("FDI train 1 done.\n");
3817 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3818 break;
3819 }
3820 }
3821 if (tries == 5)
3822 DRM_ERROR("FDI train 1 fail!\n");
3823
3824 /* Train 2 */
3825 reg = FDI_TX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 temp &= ~FDI_LINK_TRAIN_NONE;
3828 temp |= FDI_LINK_TRAIN_PATTERN_2;
3829 I915_WRITE(reg, temp);
3830
3831 reg = FDI_RX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 temp &= ~FDI_LINK_TRAIN_NONE;
3834 temp |= FDI_LINK_TRAIN_PATTERN_2;
3835 I915_WRITE(reg, temp);
3836
3837 POSTING_READ(reg);
3838 udelay(150);
3839
3840 reg = FDI_RX_IIR(pipe);
3841 for (tries = 0; tries < 5; tries++) {
3842 temp = I915_READ(reg);
3843 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3844
3845 if (temp & FDI_RX_SYMBOL_LOCK) {
3846 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3847 DRM_DEBUG_KMS("FDI train 2 done.\n");
3848 break;
3849 }
3850 }
3851 if (tries == 5)
3852 DRM_ERROR("FDI train 2 fail!\n");
3853
3854 DRM_DEBUG_KMS("FDI train done\n");
3855
3856 }
3857
3858 static const int snb_b_fdi_train_param[] = {
3859 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3860 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3861 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3862 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3863 };
3864
3865 /* The FDI link training functions for SNB/Cougarpoint. */
3866 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3867 {
3868 struct drm_device *dev = crtc->dev;
3869 struct drm_i915_private *dev_priv = to_i915(dev);
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871 int pipe = intel_crtc->pipe;
3872 i915_reg_t reg;
3873 u32 temp, i, retry;
3874
3875 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3876 for train result */
3877 reg = FDI_RX_IMR(pipe);
3878 temp = I915_READ(reg);
3879 temp &= ~FDI_RX_SYMBOL_LOCK;
3880 temp &= ~FDI_RX_BIT_LOCK;
3881 I915_WRITE(reg, temp);
3882
3883 POSTING_READ(reg);
3884 udelay(150);
3885
3886 /* enable CPU FDI TX and PCH FDI RX */
3887 reg = FDI_TX_CTL(pipe);
3888 temp = I915_READ(reg);
3889 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3890 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3891 temp &= ~FDI_LINK_TRAIN_NONE;
3892 temp |= FDI_LINK_TRAIN_PATTERN_1;
3893 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3894 /* SNB-B */
3895 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3896 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3897
3898 I915_WRITE(FDI_RX_MISC(pipe),
3899 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3900
3901 reg = FDI_RX_CTL(pipe);
3902 temp = I915_READ(reg);
3903 if (HAS_PCH_CPT(dev)) {
3904 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3905 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3906 } else {
3907 temp &= ~FDI_LINK_TRAIN_NONE;
3908 temp |= FDI_LINK_TRAIN_PATTERN_1;
3909 }
3910 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3911
3912 POSTING_READ(reg);
3913 udelay(150);
3914
3915 for (i = 0; i < 4; i++) {
3916 reg = FDI_TX_CTL(pipe);
3917 temp = I915_READ(reg);
3918 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3919 temp |= snb_b_fdi_train_param[i];
3920 I915_WRITE(reg, temp);
3921
3922 POSTING_READ(reg);
3923 udelay(500);
3924
3925 for (retry = 0; retry < 5; retry++) {
3926 reg = FDI_RX_IIR(pipe);
3927 temp = I915_READ(reg);
3928 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3929 if (temp & FDI_RX_BIT_LOCK) {
3930 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3931 DRM_DEBUG_KMS("FDI train 1 done.\n");
3932 break;
3933 }
3934 udelay(50);
3935 }
3936 if (retry < 5)
3937 break;
3938 }
3939 if (i == 4)
3940 DRM_ERROR("FDI train 1 fail!\n");
3941
3942 /* Train 2 */
3943 reg = FDI_TX_CTL(pipe);
3944 temp = I915_READ(reg);
3945 temp &= ~FDI_LINK_TRAIN_NONE;
3946 temp |= FDI_LINK_TRAIN_PATTERN_2;
3947 if (IS_GEN6(dev)) {
3948 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3949 /* SNB-B */
3950 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3951 }
3952 I915_WRITE(reg, temp);
3953
3954 reg = FDI_RX_CTL(pipe);
3955 temp = I915_READ(reg);
3956 if (HAS_PCH_CPT(dev)) {
3957 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3958 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3959 } else {
3960 temp &= ~FDI_LINK_TRAIN_NONE;
3961 temp |= FDI_LINK_TRAIN_PATTERN_2;
3962 }
3963 I915_WRITE(reg, temp);
3964
3965 POSTING_READ(reg);
3966 udelay(150);
3967
3968 for (i = 0; i < 4; i++) {
3969 reg = FDI_TX_CTL(pipe);
3970 temp = I915_READ(reg);
3971 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3972 temp |= snb_b_fdi_train_param[i];
3973 I915_WRITE(reg, temp);
3974
3975 POSTING_READ(reg);
3976 udelay(500);
3977
3978 for (retry = 0; retry < 5; retry++) {
3979 reg = FDI_RX_IIR(pipe);
3980 temp = I915_READ(reg);
3981 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3982 if (temp & FDI_RX_SYMBOL_LOCK) {
3983 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3984 DRM_DEBUG_KMS("FDI train 2 done.\n");
3985 break;
3986 }
3987 udelay(50);
3988 }
3989 if (retry < 5)
3990 break;
3991 }
3992 if (i == 4)
3993 DRM_ERROR("FDI train 2 fail!\n");
3994
3995 DRM_DEBUG_KMS("FDI train done.\n");
3996 }
3997
3998 /* Manual link training for Ivy Bridge A0 parts */
3999 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4000 {
4001 struct drm_device *dev = crtc->dev;
4002 struct drm_i915_private *dev_priv = to_i915(dev);
4003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4004 int pipe = intel_crtc->pipe;
4005 i915_reg_t reg;
4006 u32 temp, i, j;
4007
4008 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4009 for train result */
4010 reg = FDI_RX_IMR(pipe);
4011 temp = I915_READ(reg);
4012 temp &= ~FDI_RX_SYMBOL_LOCK;
4013 temp &= ~FDI_RX_BIT_LOCK;
4014 I915_WRITE(reg, temp);
4015
4016 POSTING_READ(reg);
4017 udelay(150);
4018
4019 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4020 I915_READ(FDI_RX_IIR(pipe)));
4021
4022 /* Try each vswing and preemphasis setting twice before moving on */
4023 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4024 /* disable first in case we need to retry */
4025 reg = FDI_TX_CTL(pipe);
4026 temp = I915_READ(reg);
4027 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4028 temp &= ~FDI_TX_ENABLE;
4029 I915_WRITE(reg, temp);
4030
4031 reg = FDI_RX_CTL(pipe);
4032 temp = I915_READ(reg);
4033 temp &= ~FDI_LINK_TRAIN_AUTO;
4034 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4035 temp &= ~FDI_RX_ENABLE;
4036 I915_WRITE(reg, temp);
4037
4038 /* enable CPU FDI TX and PCH FDI RX */
4039 reg = FDI_TX_CTL(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4042 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4043 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4044 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4045 temp |= snb_b_fdi_train_param[j/2];
4046 temp |= FDI_COMPOSITE_SYNC;
4047 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4048
4049 I915_WRITE(FDI_RX_MISC(pipe),
4050 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4051
4052 reg = FDI_RX_CTL(pipe);
4053 temp = I915_READ(reg);
4054 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4055 temp |= FDI_COMPOSITE_SYNC;
4056 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4057
4058 POSTING_READ(reg);
4059 udelay(1); /* should be 0.5us */
4060
4061 for (i = 0; i < 4; i++) {
4062 reg = FDI_RX_IIR(pipe);
4063 temp = I915_READ(reg);
4064 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4065
4066 if (temp & FDI_RX_BIT_LOCK ||
4067 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4068 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4069 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4070 i);
4071 break;
4072 }
4073 udelay(1); /* should be 0.5us */
4074 }
4075 if (i == 4) {
4076 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4077 continue;
4078 }
4079
4080 /* Train 2 */
4081 reg = FDI_TX_CTL(pipe);
4082 temp = I915_READ(reg);
4083 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4084 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4085 I915_WRITE(reg, temp);
4086
4087 reg = FDI_RX_CTL(pipe);
4088 temp = I915_READ(reg);
4089 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4090 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4091 I915_WRITE(reg, temp);
4092
4093 POSTING_READ(reg);
4094 udelay(2); /* should be 1.5us */
4095
4096 for (i = 0; i < 4; i++) {
4097 reg = FDI_RX_IIR(pipe);
4098 temp = I915_READ(reg);
4099 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4100
4101 if (temp & FDI_RX_SYMBOL_LOCK ||
4102 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4103 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4104 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4105 i);
4106 goto train_done;
4107 }
4108 udelay(2); /* should be 1.5us */
4109 }
4110 if (i == 4)
4111 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4112 }
4113
4114 train_done:
4115 DRM_DEBUG_KMS("FDI train done.\n");
4116 }
4117
4118 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4119 {
4120 struct drm_device *dev = intel_crtc->base.dev;
4121 struct drm_i915_private *dev_priv = to_i915(dev);
4122 int pipe = intel_crtc->pipe;
4123 i915_reg_t reg;
4124 u32 temp;
4125
4126 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4127 reg = FDI_RX_CTL(pipe);
4128 temp = I915_READ(reg);
4129 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4130 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4131 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4132 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4133
4134 POSTING_READ(reg);
4135 udelay(200);
4136
4137 /* Switch from Rawclk to PCDclk */
4138 temp = I915_READ(reg);
4139 I915_WRITE(reg, temp | FDI_PCDCLK);
4140
4141 POSTING_READ(reg);
4142 udelay(200);
4143
4144 /* Enable CPU FDI TX PLL, always on for Ironlake */
4145 reg = FDI_TX_CTL(pipe);
4146 temp = I915_READ(reg);
4147 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4148 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4149
4150 POSTING_READ(reg);
4151 udelay(100);
4152 }
4153 }
4154
4155 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4156 {
4157 struct drm_device *dev = intel_crtc->base.dev;
4158 struct drm_i915_private *dev_priv = to_i915(dev);
4159 int pipe = intel_crtc->pipe;
4160 i915_reg_t reg;
4161 u32 temp;
4162
4163 /* Switch from PCDclk to Rawclk */
4164 reg = FDI_RX_CTL(pipe);
4165 temp = I915_READ(reg);
4166 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4167
4168 /* Disable CPU FDI TX PLL */
4169 reg = FDI_TX_CTL(pipe);
4170 temp = I915_READ(reg);
4171 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4172
4173 POSTING_READ(reg);
4174 udelay(100);
4175
4176 reg = FDI_RX_CTL(pipe);
4177 temp = I915_READ(reg);
4178 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4179
4180 /* Wait for the clocks to turn off. */
4181 POSTING_READ(reg);
4182 udelay(100);
4183 }
4184
4185 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4186 {
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = to_i915(dev);
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190 int pipe = intel_crtc->pipe;
4191 i915_reg_t reg;
4192 u32 temp;
4193
4194 /* disable CPU FDI tx and PCH FDI rx */
4195 reg = FDI_TX_CTL(pipe);
4196 temp = I915_READ(reg);
4197 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4198 POSTING_READ(reg);
4199
4200 reg = FDI_RX_CTL(pipe);
4201 temp = I915_READ(reg);
4202 temp &= ~(0x7 << 16);
4203 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4204 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4205
4206 POSTING_READ(reg);
4207 udelay(100);
4208
4209 /* Ironlake workaround, disable clock pointer after downing FDI */
4210 if (HAS_PCH_IBX(dev))
4211 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4212
4213 /* still set train pattern 1 */
4214 reg = FDI_TX_CTL(pipe);
4215 temp = I915_READ(reg);
4216 temp &= ~FDI_LINK_TRAIN_NONE;
4217 temp |= FDI_LINK_TRAIN_PATTERN_1;
4218 I915_WRITE(reg, temp);
4219
4220 reg = FDI_RX_CTL(pipe);
4221 temp = I915_READ(reg);
4222 if (HAS_PCH_CPT(dev)) {
4223 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4224 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4225 } else {
4226 temp &= ~FDI_LINK_TRAIN_NONE;
4227 temp |= FDI_LINK_TRAIN_PATTERN_1;
4228 }
4229 /* BPC in FDI rx is consistent with that in PIPECONF */
4230 temp &= ~(0x07 << 16);
4231 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4232 I915_WRITE(reg, temp);
4233
4234 POSTING_READ(reg);
4235 udelay(100);
4236 }
4237
4238 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4239 {
4240 struct intel_crtc *crtc;
4241
4242 /* Note that we don't need to be called with mode_config.lock here
4243 * as our list of CRTC objects is static for the lifetime of the
4244 * device and so cannot disappear as we iterate. Similarly, we can
4245 * happily treat the predicates as racy, atomic checks as userspace
4246 * cannot claim and pin a new fb without at least acquring the
4247 * struct_mutex and so serialising with us.
4248 */
4249 for_each_intel_crtc(dev, crtc) {
4250 if (atomic_read(&crtc->unpin_work_count) == 0)
4251 continue;
4252
4253 if (crtc->flip_work)
4254 intel_wait_for_vblank(dev, crtc->pipe);
4255
4256 return true;
4257 }
4258
4259 return false;
4260 }
4261
4262 static void page_flip_completed(struct intel_crtc *intel_crtc)
4263 {
4264 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4265 struct intel_flip_work *work = intel_crtc->flip_work;
4266
4267 intel_crtc->flip_work = NULL;
4268
4269 if (work->event)
4270 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4271
4272 drm_crtc_vblank_put(&intel_crtc->base);
4273
4274 wake_up_all(&dev_priv->pending_flip_queue);
4275 queue_work(dev_priv->wq, &work->unpin_work);
4276
4277 trace_i915_flip_complete(intel_crtc->plane,
4278 work->pending_flip_obj);
4279 }
4280
4281 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4282 {
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = to_i915(dev);
4285 long ret;
4286
4287 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4288
4289 ret = wait_event_interruptible_timeout(
4290 dev_priv->pending_flip_queue,
4291 !intel_crtc_has_pending_flip(crtc),
4292 60*HZ);
4293
4294 if (ret < 0)
4295 return ret;
4296
4297 if (ret == 0) {
4298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299 struct intel_flip_work *work;
4300
4301 spin_lock_irq(&dev->event_lock);
4302 work = intel_crtc->flip_work;
4303 if (work && !is_mmio_work(work)) {
4304 WARN_ONCE(1, "Removing stuck page flip\n");
4305 page_flip_completed(intel_crtc);
4306 }
4307 spin_unlock_irq(&dev->event_lock);
4308 }
4309
4310 return 0;
4311 }
4312
4313 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4314 {
4315 u32 temp;
4316
4317 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4318
4319 mutex_lock(&dev_priv->sb_lock);
4320
4321 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4322 temp |= SBI_SSCCTL_DISABLE;
4323 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4324
4325 mutex_unlock(&dev_priv->sb_lock);
4326 }
4327
4328 /* Program iCLKIP clock to the desired frequency */
4329 static void lpt_program_iclkip(struct drm_crtc *crtc)
4330 {
4331 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4332 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4333 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4334 u32 temp;
4335
4336 lpt_disable_iclkip(dev_priv);
4337
4338 /* The iCLK virtual clock root frequency is in MHz,
4339 * but the adjusted_mode->crtc_clock in in KHz. To get the
4340 * divisors, it is necessary to divide one by another, so we
4341 * convert the virtual clock precision to KHz here for higher
4342 * precision.
4343 */
4344 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4345 u32 iclk_virtual_root_freq = 172800 * 1000;
4346 u32 iclk_pi_range = 64;
4347 u32 desired_divisor;
4348
4349 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4350 clock << auxdiv);
4351 divsel = (desired_divisor / iclk_pi_range) - 2;
4352 phaseinc = desired_divisor % iclk_pi_range;
4353
4354 /*
4355 * Near 20MHz is a corner case which is
4356 * out of range for the 7-bit divisor
4357 */
4358 if (divsel <= 0x7f)
4359 break;
4360 }
4361
4362 /* This should not happen with any sane values */
4363 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4364 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4365 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4366 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4367
4368 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4369 clock,
4370 auxdiv,
4371 divsel,
4372 phasedir,
4373 phaseinc);
4374
4375 mutex_lock(&dev_priv->sb_lock);
4376
4377 /* Program SSCDIVINTPHASE6 */
4378 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4379 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4380 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4381 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4382 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4383 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4384 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4385 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4386
4387 /* Program SSCAUXDIV */
4388 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4389 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4390 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4391 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4392
4393 /* Enable modulator and associated divider */
4394 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4395 temp &= ~SBI_SSCCTL_DISABLE;
4396 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4397
4398 mutex_unlock(&dev_priv->sb_lock);
4399
4400 /* Wait for initialization time */
4401 udelay(24);
4402
4403 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4404 }
4405
4406 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4407 {
4408 u32 divsel, phaseinc, auxdiv;
4409 u32 iclk_virtual_root_freq = 172800 * 1000;
4410 u32 iclk_pi_range = 64;
4411 u32 desired_divisor;
4412 u32 temp;
4413
4414 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4415 return 0;
4416
4417 mutex_lock(&dev_priv->sb_lock);
4418
4419 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4420 if (temp & SBI_SSCCTL_DISABLE) {
4421 mutex_unlock(&dev_priv->sb_lock);
4422 return 0;
4423 }
4424
4425 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4426 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4427 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4428 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4429 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4430
4431 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4432 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4433 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4434
4435 mutex_unlock(&dev_priv->sb_lock);
4436
4437 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4438
4439 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4440 desired_divisor << auxdiv);
4441 }
4442
4443 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4444 enum pipe pch_transcoder)
4445 {
4446 struct drm_device *dev = crtc->base.dev;
4447 struct drm_i915_private *dev_priv = to_i915(dev);
4448 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4449
4450 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4451 I915_READ(HTOTAL(cpu_transcoder)));
4452 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4453 I915_READ(HBLANK(cpu_transcoder)));
4454 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4455 I915_READ(HSYNC(cpu_transcoder)));
4456
4457 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4458 I915_READ(VTOTAL(cpu_transcoder)));
4459 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4460 I915_READ(VBLANK(cpu_transcoder)));
4461 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4462 I915_READ(VSYNC(cpu_transcoder)));
4463 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4464 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4465 }
4466
4467 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4468 {
4469 struct drm_i915_private *dev_priv = to_i915(dev);
4470 uint32_t temp;
4471
4472 temp = I915_READ(SOUTH_CHICKEN1);
4473 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4474 return;
4475
4476 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4478
4479 temp &= ~FDI_BC_BIFURCATION_SELECT;
4480 if (enable)
4481 temp |= FDI_BC_BIFURCATION_SELECT;
4482
4483 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4484 I915_WRITE(SOUTH_CHICKEN1, temp);
4485 POSTING_READ(SOUTH_CHICKEN1);
4486 }
4487
4488 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4489 {
4490 struct drm_device *dev = intel_crtc->base.dev;
4491
4492 switch (intel_crtc->pipe) {
4493 case PIPE_A:
4494 break;
4495 case PIPE_B:
4496 if (intel_crtc->config->fdi_lanes > 2)
4497 cpt_set_fdi_bc_bifurcation(dev, false);
4498 else
4499 cpt_set_fdi_bc_bifurcation(dev, true);
4500
4501 break;
4502 case PIPE_C:
4503 cpt_set_fdi_bc_bifurcation(dev, true);
4504
4505 break;
4506 default:
4507 BUG();
4508 }
4509 }
4510
4511 /* Return which DP Port should be selected for Transcoder DP control */
4512 static enum port
4513 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4514 {
4515 struct drm_device *dev = crtc->dev;
4516 struct intel_encoder *encoder;
4517
4518 for_each_encoder_on_crtc(dev, crtc, encoder) {
4519 if (encoder->type == INTEL_OUTPUT_DP ||
4520 encoder->type == INTEL_OUTPUT_EDP)
4521 return enc_to_dig_port(&encoder->base)->port;
4522 }
4523
4524 return -1;
4525 }
4526
4527 /*
4528 * Enable PCH resources required for PCH ports:
4529 * - PCH PLLs
4530 * - FDI training & RX/TX
4531 * - update transcoder timings
4532 * - DP transcoding bits
4533 * - transcoder
4534 */
4535 static void ironlake_pch_enable(struct drm_crtc *crtc)
4536 {
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = to_i915(dev);
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 int pipe = intel_crtc->pipe;
4541 u32 temp;
4542
4543 assert_pch_transcoder_disabled(dev_priv, pipe);
4544
4545 if (IS_IVYBRIDGE(dev))
4546 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4547
4548 /* Write the TU size bits before fdi link training, so that error
4549 * detection works. */
4550 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4551 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4552
4553 /* For PCH output, training FDI link */
4554 dev_priv->display.fdi_link_train(crtc);
4555
4556 /* We need to program the right clock selection before writing the pixel
4557 * mutliplier into the DPLL. */
4558 if (HAS_PCH_CPT(dev)) {
4559 u32 sel;
4560
4561 temp = I915_READ(PCH_DPLL_SEL);
4562 temp |= TRANS_DPLL_ENABLE(pipe);
4563 sel = TRANS_DPLLB_SEL(pipe);
4564 if (intel_crtc->config->shared_dpll ==
4565 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4566 temp |= sel;
4567 else
4568 temp &= ~sel;
4569 I915_WRITE(PCH_DPLL_SEL, temp);
4570 }
4571
4572 /* XXX: pch pll's can be enabled any time before we enable the PCH
4573 * transcoder, and we actually should do this to not upset any PCH
4574 * transcoder that already use the clock when we share it.
4575 *
4576 * Note that enable_shared_dpll tries to do the right thing, but
4577 * get_shared_dpll unconditionally resets the pll - we need that to have
4578 * the right LVDS enable sequence. */
4579 intel_enable_shared_dpll(intel_crtc);
4580
4581 /* set transcoder timing, panel must allow it */
4582 assert_panel_unlocked(dev_priv, pipe);
4583 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4584
4585 intel_fdi_normal_train(crtc);
4586
4587 /* For PCH DP, enable TRANS_DP_CTL */
4588 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4589 const struct drm_display_mode *adjusted_mode =
4590 &intel_crtc->config->base.adjusted_mode;
4591 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4592 i915_reg_t reg = TRANS_DP_CTL(pipe);
4593 temp = I915_READ(reg);
4594 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4595 TRANS_DP_SYNC_MASK |
4596 TRANS_DP_BPC_MASK);
4597 temp |= TRANS_DP_OUTPUT_ENABLE;
4598 temp |= bpc << 9; /* same format but at 11:9 */
4599
4600 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4601 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4602 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4603 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4604
4605 switch (intel_trans_dp_port_sel(crtc)) {
4606 case PORT_B:
4607 temp |= TRANS_DP_PORT_SEL_B;
4608 break;
4609 case PORT_C:
4610 temp |= TRANS_DP_PORT_SEL_C;
4611 break;
4612 case PORT_D:
4613 temp |= TRANS_DP_PORT_SEL_D;
4614 break;
4615 default:
4616 BUG();
4617 }
4618
4619 I915_WRITE(reg, temp);
4620 }
4621
4622 ironlake_enable_pch_transcoder(dev_priv, pipe);
4623 }
4624
4625 static void lpt_pch_enable(struct drm_crtc *crtc)
4626 {
4627 struct drm_device *dev = crtc->dev;
4628 struct drm_i915_private *dev_priv = to_i915(dev);
4629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4631
4632 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4633
4634 lpt_program_iclkip(crtc);
4635
4636 /* Set transcoder timing. */
4637 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4638
4639 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4640 }
4641
4642 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4643 {
4644 struct drm_i915_private *dev_priv = to_i915(dev);
4645 i915_reg_t dslreg = PIPEDSL(pipe);
4646 u32 temp;
4647
4648 temp = I915_READ(dslreg);
4649 udelay(500);
4650 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4651 if (wait_for(I915_READ(dslreg) != temp, 5))
4652 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4653 }
4654 }
4655
4656 static int
4657 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4658 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4659 int src_w, int src_h, int dst_w, int dst_h)
4660 {
4661 struct intel_crtc_scaler_state *scaler_state =
4662 &crtc_state->scaler_state;
4663 struct intel_crtc *intel_crtc =
4664 to_intel_crtc(crtc_state->base.crtc);
4665 int need_scaling;
4666
4667 need_scaling = intel_rotation_90_or_270(rotation) ?
4668 (src_h != dst_w || src_w != dst_h):
4669 (src_w != dst_w || src_h != dst_h);
4670
4671 /*
4672 * if plane is being disabled or scaler is no more required or force detach
4673 * - free scaler binded to this plane/crtc
4674 * - in order to do this, update crtc->scaler_usage
4675 *
4676 * Here scaler state in crtc_state is set free so that
4677 * scaler can be assigned to other user. Actual register
4678 * update to free the scaler is done in plane/panel-fit programming.
4679 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4680 */
4681 if (force_detach || !need_scaling) {
4682 if (*scaler_id >= 0) {
4683 scaler_state->scaler_users &= ~(1 << scaler_user);
4684 scaler_state->scalers[*scaler_id].in_use = 0;
4685
4686 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4687 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4688 intel_crtc->pipe, scaler_user, *scaler_id,
4689 scaler_state->scaler_users);
4690 *scaler_id = -1;
4691 }
4692 return 0;
4693 }
4694
4695 /* range checks */
4696 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4697 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4698
4699 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4700 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4701 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4702 "size is out of scaler range\n",
4703 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4704 return -EINVAL;
4705 }
4706
4707 /* mark this plane as a scaler user in crtc_state */
4708 scaler_state->scaler_users |= (1 << scaler_user);
4709 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4710 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4711 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4712 scaler_state->scaler_users);
4713
4714 return 0;
4715 }
4716
4717 /**
4718 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4719 *
4720 * @state: crtc's scaler state
4721 *
4722 * Return
4723 * 0 - scaler_usage updated successfully
4724 * error - requested scaling cannot be supported or other error condition
4725 */
4726 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4727 {
4728 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4729 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4730
4731 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4732 intel_crtc->base.base.id, intel_crtc->base.name,
4733 intel_crtc->pipe, SKL_CRTC_INDEX);
4734
4735 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4736 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4737 state->pipe_src_w, state->pipe_src_h,
4738 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4739 }
4740
4741 /**
4742 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4743 *
4744 * @state: crtc's scaler state
4745 * @plane_state: atomic plane state to update
4746 *
4747 * Return
4748 * 0 - scaler_usage updated successfully
4749 * error - requested scaling cannot be supported or other error condition
4750 */
4751 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4752 struct intel_plane_state *plane_state)
4753 {
4754
4755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4756 struct intel_plane *intel_plane =
4757 to_intel_plane(plane_state->base.plane);
4758 struct drm_framebuffer *fb = plane_state->base.fb;
4759 int ret;
4760
4761 bool force_detach = !fb || !plane_state->base.visible;
4762
4763 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4764 intel_plane->base.base.id, intel_plane->base.name,
4765 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4766
4767 ret = skl_update_scaler(crtc_state, force_detach,
4768 drm_plane_index(&intel_plane->base),
4769 &plane_state->scaler_id,
4770 plane_state->base.rotation,
4771 drm_rect_width(&plane_state->base.src) >> 16,
4772 drm_rect_height(&plane_state->base.src) >> 16,
4773 drm_rect_width(&plane_state->base.dst),
4774 drm_rect_height(&plane_state->base.dst));
4775
4776 if (ret || plane_state->scaler_id < 0)
4777 return ret;
4778
4779 /* check colorkey */
4780 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4781 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4782 intel_plane->base.base.id,
4783 intel_plane->base.name);
4784 return -EINVAL;
4785 }
4786
4787 /* Check src format */
4788 switch (fb->pixel_format) {
4789 case DRM_FORMAT_RGB565:
4790 case DRM_FORMAT_XBGR8888:
4791 case DRM_FORMAT_XRGB8888:
4792 case DRM_FORMAT_ABGR8888:
4793 case DRM_FORMAT_ARGB8888:
4794 case DRM_FORMAT_XRGB2101010:
4795 case DRM_FORMAT_XBGR2101010:
4796 case DRM_FORMAT_YUYV:
4797 case DRM_FORMAT_YVYU:
4798 case DRM_FORMAT_UYVY:
4799 case DRM_FORMAT_VYUY:
4800 break;
4801 default:
4802 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4803 intel_plane->base.base.id, intel_plane->base.name,
4804 fb->base.id, fb->pixel_format);
4805 return -EINVAL;
4806 }
4807
4808 return 0;
4809 }
4810
4811 static void skylake_scaler_disable(struct intel_crtc *crtc)
4812 {
4813 int i;
4814
4815 for (i = 0; i < crtc->num_scalers; i++)
4816 skl_detach_scaler(crtc, i);
4817 }
4818
4819 static void skylake_pfit_enable(struct intel_crtc *crtc)
4820 {
4821 struct drm_device *dev = crtc->base.dev;
4822 struct drm_i915_private *dev_priv = to_i915(dev);
4823 int pipe = crtc->pipe;
4824 struct intel_crtc_scaler_state *scaler_state =
4825 &crtc->config->scaler_state;
4826
4827 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4828
4829 if (crtc->config->pch_pfit.enabled) {
4830 int id;
4831
4832 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4833 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4834 return;
4835 }
4836
4837 id = scaler_state->scaler_id;
4838 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4839 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4840 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4841 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4842
4843 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4844 }
4845 }
4846
4847 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4848 {
4849 struct drm_device *dev = crtc->base.dev;
4850 struct drm_i915_private *dev_priv = to_i915(dev);
4851 int pipe = crtc->pipe;
4852
4853 if (crtc->config->pch_pfit.enabled) {
4854 /* Force use of hard-coded filter coefficients
4855 * as some pre-programmed values are broken,
4856 * e.g. x201.
4857 */
4858 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4859 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4860 PF_PIPE_SEL_IVB(pipe));
4861 else
4862 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4863 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4864 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4865 }
4866 }
4867
4868 void hsw_enable_ips(struct intel_crtc *crtc)
4869 {
4870 struct drm_device *dev = crtc->base.dev;
4871 struct drm_i915_private *dev_priv = to_i915(dev);
4872
4873 if (!crtc->config->ips_enabled)
4874 return;
4875
4876 /*
4877 * We can only enable IPS after we enable a plane and wait for a vblank
4878 * This function is called from post_plane_update, which is run after
4879 * a vblank wait.
4880 */
4881
4882 assert_plane_enabled(dev_priv, crtc->plane);
4883 if (IS_BROADWELL(dev)) {
4884 mutex_lock(&dev_priv->rps.hw_lock);
4885 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4886 mutex_unlock(&dev_priv->rps.hw_lock);
4887 /* Quoting Art Runyan: "its not safe to expect any particular
4888 * value in IPS_CTL bit 31 after enabling IPS through the
4889 * mailbox." Moreover, the mailbox may return a bogus state,
4890 * so we need to just enable it and continue on.
4891 */
4892 } else {
4893 I915_WRITE(IPS_CTL, IPS_ENABLE);
4894 /* The bit only becomes 1 in the next vblank, so this wait here
4895 * is essentially intel_wait_for_vblank. If we don't have this
4896 * and don't wait for vblanks until the end of crtc_enable, then
4897 * the HW state readout code will complain that the expected
4898 * IPS_CTL value is not the one we read. */
4899 if (intel_wait_for_register(dev_priv,
4900 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4901 50))
4902 DRM_ERROR("Timed out waiting for IPS enable\n");
4903 }
4904 }
4905
4906 void hsw_disable_ips(struct intel_crtc *crtc)
4907 {
4908 struct drm_device *dev = crtc->base.dev;
4909 struct drm_i915_private *dev_priv = to_i915(dev);
4910
4911 if (!crtc->config->ips_enabled)
4912 return;
4913
4914 assert_plane_enabled(dev_priv, crtc->plane);
4915 if (IS_BROADWELL(dev)) {
4916 mutex_lock(&dev_priv->rps.hw_lock);
4917 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4918 mutex_unlock(&dev_priv->rps.hw_lock);
4919 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4920 if (intel_wait_for_register(dev_priv,
4921 IPS_CTL, IPS_ENABLE, 0,
4922 42))
4923 DRM_ERROR("Timed out waiting for IPS disable\n");
4924 } else {
4925 I915_WRITE(IPS_CTL, 0);
4926 POSTING_READ(IPS_CTL);
4927 }
4928
4929 /* We need to wait for a vblank before we can disable the plane. */
4930 intel_wait_for_vblank(dev, crtc->pipe);
4931 }
4932
4933 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4934 {
4935 if (intel_crtc->overlay) {
4936 struct drm_device *dev = intel_crtc->base.dev;
4937 struct drm_i915_private *dev_priv = to_i915(dev);
4938
4939 mutex_lock(&dev->struct_mutex);
4940 dev_priv->mm.interruptible = false;
4941 (void) intel_overlay_switch_off(intel_crtc->overlay);
4942 dev_priv->mm.interruptible = true;
4943 mutex_unlock(&dev->struct_mutex);
4944 }
4945
4946 /* Let userspace switch the overlay on again. In most cases userspace
4947 * has to recompute where to put it anyway.
4948 */
4949 }
4950
4951 /**
4952 * intel_post_enable_primary - Perform operations after enabling primary plane
4953 * @crtc: the CRTC whose primary plane was just enabled
4954 *
4955 * Performs potentially sleeping operations that must be done after the primary
4956 * plane is enabled, such as updating FBC and IPS. Note that this may be
4957 * called due to an explicit primary plane update, or due to an implicit
4958 * re-enable that is caused when a sprite plane is updated to no longer
4959 * completely hide the primary plane.
4960 */
4961 static void
4962 intel_post_enable_primary(struct drm_crtc *crtc)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = to_i915(dev);
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 int pipe = intel_crtc->pipe;
4968
4969 /*
4970 * FIXME IPS should be fine as long as one plane is
4971 * enabled, but in practice it seems to have problems
4972 * when going from primary only to sprite only and vice
4973 * versa.
4974 */
4975 hsw_enable_ips(intel_crtc);
4976
4977 /*
4978 * Gen2 reports pipe underruns whenever all planes are disabled.
4979 * So don't enable underrun reporting before at least some planes
4980 * are enabled.
4981 * FIXME: Need to fix the logic to work when we turn off all planes
4982 * but leave the pipe running.
4983 */
4984 if (IS_GEN2(dev))
4985 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4986
4987 /* Underruns don't always raise interrupts, so check manually. */
4988 intel_check_cpu_fifo_underruns(dev_priv);
4989 intel_check_pch_fifo_underruns(dev_priv);
4990 }
4991
4992 /* FIXME move all this to pre_plane_update() with proper state tracking */
4993 static void
4994 intel_pre_disable_primary(struct drm_crtc *crtc)
4995 {
4996 struct drm_device *dev = crtc->dev;
4997 struct drm_i915_private *dev_priv = to_i915(dev);
4998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4999 int pipe = intel_crtc->pipe;
5000
5001 /*
5002 * Gen2 reports pipe underruns whenever all planes are disabled.
5003 * So diasble underrun reporting before all the planes get disabled.
5004 * FIXME: Need to fix the logic to work when we turn off all planes
5005 * but leave the pipe running.
5006 */
5007 if (IS_GEN2(dev))
5008 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5009
5010 /*
5011 * FIXME IPS should be fine as long as one plane is
5012 * enabled, but in practice it seems to have problems
5013 * when going from primary only to sprite only and vice
5014 * versa.
5015 */
5016 hsw_disable_ips(intel_crtc);
5017 }
5018
5019 /* FIXME get rid of this and use pre_plane_update */
5020 static void
5021 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5022 {
5023 struct drm_device *dev = crtc->dev;
5024 struct drm_i915_private *dev_priv = to_i915(dev);
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 int pipe = intel_crtc->pipe;
5027
5028 intel_pre_disable_primary(crtc);
5029
5030 /*
5031 * Vblank time updates from the shadow to live plane control register
5032 * are blocked if the memory self-refresh mode is active at that
5033 * moment. So to make sure the plane gets truly disabled, disable
5034 * first the self-refresh mode. The self-refresh enable bit in turn
5035 * will be checked/applied by the HW only at the next frame start
5036 * event which is after the vblank start event, so we need to have a
5037 * wait-for-vblank between disabling the plane and the pipe.
5038 */
5039 if (HAS_GMCH_DISPLAY(dev)) {
5040 intel_set_memory_cxsr(dev_priv, false);
5041 dev_priv->wm.vlv.cxsr = false;
5042 intel_wait_for_vblank(dev, pipe);
5043 }
5044 }
5045
5046 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5047 {
5048 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5049 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5050 struct intel_crtc_state *pipe_config =
5051 to_intel_crtc_state(crtc->base.state);
5052 struct drm_plane *primary = crtc->base.primary;
5053 struct drm_plane_state *old_pri_state =
5054 drm_atomic_get_existing_plane_state(old_state, primary);
5055
5056 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5057
5058 crtc->wm.cxsr_allowed = true;
5059
5060 if (pipe_config->update_wm_post && pipe_config->base.active)
5061 intel_update_watermarks(&crtc->base);
5062
5063 if (old_pri_state) {
5064 struct intel_plane_state *primary_state =
5065 to_intel_plane_state(primary->state);
5066 struct intel_plane_state *old_primary_state =
5067 to_intel_plane_state(old_pri_state);
5068
5069 intel_fbc_post_update(crtc);
5070
5071 if (primary_state->base.visible &&
5072 (needs_modeset(&pipe_config->base) ||
5073 !old_primary_state->base.visible))
5074 intel_post_enable_primary(&crtc->base);
5075 }
5076 }
5077
5078 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5079 {
5080 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5081 struct drm_device *dev = crtc->base.dev;
5082 struct drm_i915_private *dev_priv = to_i915(dev);
5083 struct intel_crtc_state *pipe_config =
5084 to_intel_crtc_state(crtc->base.state);
5085 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5086 struct drm_plane *primary = crtc->base.primary;
5087 struct drm_plane_state *old_pri_state =
5088 drm_atomic_get_existing_plane_state(old_state, primary);
5089 bool modeset = needs_modeset(&pipe_config->base);
5090
5091 if (old_pri_state) {
5092 struct intel_plane_state *primary_state =
5093 to_intel_plane_state(primary->state);
5094 struct intel_plane_state *old_primary_state =
5095 to_intel_plane_state(old_pri_state);
5096
5097 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5098
5099 if (old_primary_state->base.visible &&
5100 (modeset || !primary_state->base.visible))
5101 intel_pre_disable_primary(&crtc->base);
5102 }
5103
5104 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5105 crtc->wm.cxsr_allowed = false;
5106
5107 /*
5108 * Vblank time updates from the shadow to live plane control register
5109 * are blocked if the memory self-refresh mode is active at that
5110 * moment. So to make sure the plane gets truly disabled, disable
5111 * first the self-refresh mode. The self-refresh enable bit in turn
5112 * will be checked/applied by the HW only at the next frame start
5113 * event which is after the vblank start event, so we need to have a
5114 * wait-for-vblank between disabling the plane and the pipe.
5115 */
5116 if (old_crtc_state->base.active) {
5117 intel_set_memory_cxsr(dev_priv, false);
5118 dev_priv->wm.vlv.cxsr = false;
5119 intel_wait_for_vblank(dev, crtc->pipe);
5120 }
5121 }
5122
5123 /*
5124 * IVB workaround: must disable low power watermarks for at least
5125 * one frame before enabling scaling. LP watermarks can be re-enabled
5126 * when scaling is disabled.
5127 *
5128 * WaCxSRDisabledForSpriteScaling:ivb
5129 */
5130 if (pipe_config->disable_lp_wm) {
5131 ilk_disable_lp_wm(dev);
5132 intel_wait_for_vblank(dev, crtc->pipe);
5133 }
5134
5135 /*
5136 * If we're doing a modeset, we're done. No need to do any pre-vblank
5137 * watermark programming here.
5138 */
5139 if (needs_modeset(&pipe_config->base))
5140 return;
5141
5142 /*
5143 * For platforms that support atomic watermarks, program the
5144 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5145 * will be the intermediate values that are safe for both pre- and
5146 * post- vblank; when vblank happens, the 'active' values will be set
5147 * to the final 'target' values and we'll do this again to get the
5148 * optimal watermarks. For gen9+ platforms, the values we program here
5149 * will be the final target values which will get automatically latched
5150 * at vblank time; no further programming will be necessary.
5151 *
5152 * If a platform hasn't been transitioned to atomic watermarks yet,
5153 * we'll continue to update watermarks the old way, if flags tell
5154 * us to.
5155 */
5156 if (dev_priv->display.initial_watermarks != NULL)
5157 dev_priv->display.initial_watermarks(pipe_config);
5158 else if (pipe_config->update_wm_pre)
5159 intel_update_watermarks(&crtc->base);
5160 }
5161
5162 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5163 {
5164 struct drm_device *dev = crtc->dev;
5165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5166 struct drm_plane *p;
5167 int pipe = intel_crtc->pipe;
5168
5169 intel_crtc_dpms_overlay_disable(intel_crtc);
5170
5171 drm_for_each_plane_mask(p, dev, plane_mask)
5172 to_intel_plane(p)->disable_plane(p, crtc);
5173
5174 /*
5175 * FIXME: Once we grow proper nuclear flip support out of this we need
5176 * to compute the mask of flip planes precisely. For the time being
5177 * consider this a flip to a NULL plane.
5178 */
5179 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5180 }
5181
5182 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5183 struct intel_crtc_state *crtc_state,
5184 struct drm_atomic_state *old_state)
5185 {
5186 struct drm_connector_state *old_conn_state;
5187 struct drm_connector *conn;
5188 int i;
5189
5190 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5191 struct drm_connector_state *conn_state = conn->state;
5192 struct intel_encoder *encoder =
5193 to_intel_encoder(conn_state->best_encoder);
5194
5195 if (conn_state->crtc != crtc)
5196 continue;
5197
5198 if (encoder->pre_pll_enable)
5199 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5200 }
5201 }
5202
5203 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5204 struct intel_crtc_state *crtc_state,
5205 struct drm_atomic_state *old_state)
5206 {
5207 struct drm_connector_state *old_conn_state;
5208 struct drm_connector *conn;
5209 int i;
5210
5211 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5212 struct drm_connector_state *conn_state = conn->state;
5213 struct intel_encoder *encoder =
5214 to_intel_encoder(conn_state->best_encoder);
5215
5216 if (conn_state->crtc != crtc)
5217 continue;
5218
5219 if (encoder->pre_enable)
5220 encoder->pre_enable(encoder, crtc_state, conn_state);
5221 }
5222 }
5223
5224 static void intel_encoders_enable(struct drm_crtc *crtc,
5225 struct intel_crtc_state *crtc_state,
5226 struct drm_atomic_state *old_state)
5227 {
5228 struct drm_connector_state *old_conn_state;
5229 struct drm_connector *conn;
5230 int i;
5231
5232 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5233 struct drm_connector_state *conn_state = conn->state;
5234 struct intel_encoder *encoder =
5235 to_intel_encoder(conn_state->best_encoder);
5236
5237 if (conn_state->crtc != crtc)
5238 continue;
5239
5240 encoder->enable(encoder, crtc_state, conn_state);
5241 intel_opregion_notify_encoder(encoder, true);
5242 }
5243 }
5244
5245 static void intel_encoders_disable(struct drm_crtc *crtc,
5246 struct intel_crtc_state *old_crtc_state,
5247 struct drm_atomic_state *old_state)
5248 {
5249 struct drm_connector_state *old_conn_state;
5250 struct drm_connector *conn;
5251 int i;
5252
5253 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5254 struct intel_encoder *encoder =
5255 to_intel_encoder(old_conn_state->best_encoder);
5256
5257 if (old_conn_state->crtc != crtc)
5258 continue;
5259
5260 intel_opregion_notify_encoder(encoder, false);
5261 encoder->disable(encoder, old_crtc_state, old_conn_state);
5262 }
5263 }
5264
5265 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5266 struct intel_crtc_state *old_crtc_state,
5267 struct drm_atomic_state *old_state)
5268 {
5269 struct drm_connector_state *old_conn_state;
5270 struct drm_connector *conn;
5271 int i;
5272
5273 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5274 struct intel_encoder *encoder =
5275 to_intel_encoder(old_conn_state->best_encoder);
5276
5277 if (old_conn_state->crtc != crtc)
5278 continue;
5279
5280 if (encoder->post_disable)
5281 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5282 }
5283 }
5284
5285 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5286 struct intel_crtc_state *old_crtc_state,
5287 struct drm_atomic_state *old_state)
5288 {
5289 struct drm_connector_state *old_conn_state;
5290 struct drm_connector *conn;
5291 int i;
5292
5293 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5294 struct intel_encoder *encoder =
5295 to_intel_encoder(old_conn_state->best_encoder);
5296
5297 if (old_conn_state->crtc != crtc)
5298 continue;
5299
5300 if (encoder->post_pll_disable)
5301 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5302 }
5303 }
5304
5305 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5306 struct drm_atomic_state *old_state)
5307 {
5308 struct drm_crtc *crtc = pipe_config->base.crtc;
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = to_i915(dev);
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 int pipe = intel_crtc->pipe;
5313
5314 if (WARN_ON(intel_crtc->active))
5315 return;
5316
5317 /*
5318 * Sometimes spurious CPU pipe underruns happen during FDI
5319 * training, at least with VGA+HDMI cloning. Suppress them.
5320 *
5321 * On ILK we get an occasional spurious CPU pipe underruns
5322 * between eDP port A enable and vdd enable. Also PCH port
5323 * enable seems to result in the occasional CPU pipe underrun.
5324 *
5325 * Spurious PCH underruns also occur during PCH enabling.
5326 */
5327 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5328 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5329 if (intel_crtc->config->has_pch_encoder)
5330 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5331
5332 if (intel_crtc->config->has_pch_encoder)
5333 intel_prepare_shared_dpll(intel_crtc);
5334
5335 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5336 intel_dp_set_m_n(intel_crtc, M1_N1);
5337
5338 intel_set_pipe_timings(intel_crtc);
5339 intel_set_pipe_src_size(intel_crtc);
5340
5341 if (intel_crtc->config->has_pch_encoder) {
5342 intel_cpu_transcoder_set_m_n(intel_crtc,
5343 &intel_crtc->config->fdi_m_n, NULL);
5344 }
5345
5346 ironlake_set_pipeconf(crtc);
5347
5348 intel_crtc->active = true;
5349
5350 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5351
5352 if (intel_crtc->config->has_pch_encoder) {
5353 /* Note: FDI PLL enabling _must_ be done before we enable the
5354 * cpu pipes, hence this is separate from all the other fdi/pch
5355 * enabling. */
5356 ironlake_fdi_pll_enable(intel_crtc);
5357 } else {
5358 assert_fdi_tx_disabled(dev_priv, pipe);
5359 assert_fdi_rx_disabled(dev_priv, pipe);
5360 }
5361
5362 ironlake_pfit_enable(intel_crtc);
5363
5364 /*
5365 * On ILK+ LUT must be loaded before the pipe is running but with
5366 * clocks enabled
5367 */
5368 intel_color_load_luts(&pipe_config->base);
5369
5370 if (dev_priv->display.initial_watermarks != NULL)
5371 dev_priv->display.initial_watermarks(intel_crtc->config);
5372 intel_enable_pipe(intel_crtc);
5373
5374 if (intel_crtc->config->has_pch_encoder)
5375 ironlake_pch_enable(crtc);
5376
5377 assert_vblank_disabled(crtc);
5378 drm_crtc_vblank_on(crtc);
5379
5380 intel_encoders_enable(crtc, pipe_config, old_state);
5381
5382 if (HAS_PCH_CPT(dev))
5383 cpt_verify_modeset(dev, intel_crtc->pipe);
5384
5385 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5386 if (intel_crtc->config->has_pch_encoder)
5387 intel_wait_for_vblank(dev, pipe);
5388 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5389 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5390 }
5391
5392 /* IPS only exists on ULT machines and is tied to pipe A. */
5393 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5394 {
5395 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5396 }
5397
5398 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5399 struct drm_atomic_state *old_state)
5400 {
5401 struct drm_crtc *crtc = pipe_config->base.crtc;
5402 struct drm_device *dev = crtc->dev;
5403 struct drm_i915_private *dev_priv = to_i915(dev);
5404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5405 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5406 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5407
5408 if (WARN_ON(intel_crtc->active))
5409 return;
5410
5411 if (intel_crtc->config->has_pch_encoder)
5412 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5413 false);
5414
5415 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5416
5417 if (intel_crtc->config->shared_dpll)
5418 intel_enable_shared_dpll(intel_crtc);
5419
5420 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5421 intel_dp_set_m_n(intel_crtc, M1_N1);
5422
5423 if (!transcoder_is_dsi(cpu_transcoder))
5424 intel_set_pipe_timings(intel_crtc);
5425
5426 intel_set_pipe_src_size(intel_crtc);
5427
5428 if (cpu_transcoder != TRANSCODER_EDP &&
5429 !transcoder_is_dsi(cpu_transcoder)) {
5430 I915_WRITE(PIPE_MULT(cpu_transcoder),
5431 intel_crtc->config->pixel_multiplier - 1);
5432 }
5433
5434 if (intel_crtc->config->has_pch_encoder) {
5435 intel_cpu_transcoder_set_m_n(intel_crtc,
5436 &intel_crtc->config->fdi_m_n, NULL);
5437 }
5438
5439 if (!transcoder_is_dsi(cpu_transcoder))
5440 haswell_set_pipeconf(crtc);
5441
5442 haswell_set_pipemisc(crtc);
5443
5444 intel_color_set_csc(&pipe_config->base);
5445
5446 intel_crtc->active = true;
5447
5448 if (intel_crtc->config->has_pch_encoder)
5449 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5450 else
5451 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5452
5453 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5454
5455 if (intel_crtc->config->has_pch_encoder)
5456 dev_priv->display.fdi_link_train(crtc);
5457
5458 if (!transcoder_is_dsi(cpu_transcoder))
5459 intel_ddi_enable_pipe_clock(intel_crtc);
5460
5461 if (INTEL_INFO(dev)->gen >= 9)
5462 skylake_pfit_enable(intel_crtc);
5463 else
5464 ironlake_pfit_enable(intel_crtc);
5465
5466 /*
5467 * On ILK+ LUT must be loaded before the pipe is running but with
5468 * clocks enabled
5469 */
5470 intel_color_load_luts(&pipe_config->base);
5471
5472 intel_ddi_set_pipe_settings(crtc);
5473 if (!transcoder_is_dsi(cpu_transcoder))
5474 intel_ddi_enable_transcoder_func(crtc);
5475
5476 if (dev_priv->display.initial_watermarks != NULL)
5477 dev_priv->display.initial_watermarks(pipe_config);
5478 else
5479 intel_update_watermarks(crtc);
5480
5481 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5482 if (!transcoder_is_dsi(cpu_transcoder))
5483 intel_enable_pipe(intel_crtc);
5484
5485 if (intel_crtc->config->has_pch_encoder)
5486 lpt_pch_enable(crtc);
5487
5488 if (intel_crtc->config->dp_encoder_is_mst)
5489 intel_ddi_set_vc_payload_alloc(crtc, true);
5490
5491 assert_vblank_disabled(crtc);
5492 drm_crtc_vblank_on(crtc);
5493
5494 intel_encoders_enable(crtc, pipe_config, old_state);
5495
5496 if (intel_crtc->config->has_pch_encoder) {
5497 intel_wait_for_vblank(dev, pipe);
5498 intel_wait_for_vblank(dev, pipe);
5499 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5500 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5501 true);
5502 }
5503
5504 /* If we change the relative order between pipe/planes enabling, we need
5505 * to change the workaround. */
5506 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5507 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5508 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5509 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5510 }
5511 }
5512
5513 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5514 {
5515 struct drm_device *dev = crtc->base.dev;
5516 struct drm_i915_private *dev_priv = to_i915(dev);
5517 int pipe = crtc->pipe;
5518
5519 /* To avoid upsetting the power well on haswell only disable the pfit if
5520 * it's in use. The hw state code will make sure we get this right. */
5521 if (force || crtc->config->pch_pfit.enabled) {
5522 I915_WRITE(PF_CTL(pipe), 0);
5523 I915_WRITE(PF_WIN_POS(pipe), 0);
5524 I915_WRITE(PF_WIN_SZ(pipe), 0);
5525 }
5526 }
5527
5528 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5529 struct drm_atomic_state *old_state)
5530 {
5531 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5532 struct drm_device *dev = crtc->dev;
5533 struct drm_i915_private *dev_priv = to_i915(dev);
5534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5535 int pipe = intel_crtc->pipe;
5536
5537 /*
5538 * Sometimes spurious CPU pipe underruns happen when the
5539 * pipe is already disabled, but FDI RX/TX is still enabled.
5540 * Happens at least with VGA+HDMI cloning. Suppress them.
5541 */
5542 if (intel_crtc->config->has_pch_encoder) {
5543 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5544 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5545 }
5546
5547 intel_encoders_disable(crtc, old_crtc_state, old_state);
5548
5549 drm_crtc_vblank_off(crtc);
5550 assert_vblank_disabled(crtc);
5551
5552 intel_disable_pipe(intel_crtc);
5553
5554 ironlake_pfit_disable(intel_crtc, false);
5555
5556 if (intel_crtc->config->has_pch_encoder)
5557 ironlake_fdi_disable(crtc);
5558
5559 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5560
5561 if (intel_crtc->config->has_pch_encoder) {
5562 ironlake_disable_pch_transcoder(dev_priv, pipe);
5563
5564 if (HAS_PCH_CPT(dev)) {
5565 i915_reg_t reg;
5566 u32 temp;
5567
5568 /* disable TRANS_DP_CTL */
5569 reg = TRANS_DP_CTL(pipe);
5570 temp = I915_READ(reg);
5571 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5572 TRANS_DP_PORT_SEL_MASK);
5573 temp |= TRANS_DP_PORT_SEL_NONE;
5574 I915_WRITE(reg, temp);
5575
5576 /* disable DPLL_SEL */
5577 temp = I915_READ(PCH_DPLL_SEL);
5578 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5579 I915_WRITE(PCH_DPLL_SEL, temp);
5580 }
5581
5582 ironlake_fdi_pll_disable(intel_crtc);
5583 }
5584
5585 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5586 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5587 }
5588
5589 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5590 struct drm_atomic_state *old_state)
5591 {
5592 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5593 struct drm_device *dev = crtc->dev;
5594 struct drm_i915_private *dev_priv = to_i915(dev);
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5597
5598 if (intel_crtc->config->has_pch_encoder)
5599 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5600 false);
5601
5602 intel_encoders_disable(crtc, old_crtc_state, old_state);
5603
5604 drm_crtc_vblank_off(crtc);
5605 assert_vblank_disabled(crtc);
5606
5607 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5608 if (!transcoder_is_dsi(cpu_transcoder))
5609 intel_disable_pipe(intel_crtc);
5610
5611 if (intel_crtc->config->dp_encoder_is_mst)
5612 intel_ddi_set_vc_payload_alloc(crtc, false);
5613
5614 if (!transcoder_is_dsi(cpu_transcoder))
5615 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5616
5617 if (INTEL_INFO(dev)->gen >= 9)
5618 skylake_scaler_disable(intel_crtc);
5619 else
5620 ironlake_pfit_disable(intel_crtc, false);
5621
5622 if (!transcoder_is_dsi(cpu_transcoder))
5623 intel_ddi_disable_pipe_clock(intel_crtc);
5624
5625 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5626
5627 if (old_crtc_state->has_pch_encoder)
5628 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5629 true);
5630 }
5631
5632 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5633 {
5634 struct drm_device *dev = crtc->base.dev;
5635 struct drm_i915_private *dev_priv = to_i915(dev);
5636 struct intel_crtc_state *pipe_config = crtc->config;
5637
5638 if (!pipe_config->gmch_pfit.control)
5639 return;
5640
5641 /*
5642 * The panel fitter should only be adjusted whilst the pipe is disabled,
5643 * according to register description and PRM.
5644 */
5645 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5646 assert_pipe_disabled(dev_priv, crtc->pipe);
5647
5648 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5649 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5650
5651 /* Border color in case we don't scale up to the full screen. Black by
5652 * default, change to something else for debugging. */
5653 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5654 }
5655
5656 static enum intel_display_power_domain port_to_power_domain(enum port port)
5657 {
5658 switch (port) {
5659 case PORT_A:
5660 return POWER_DOMAIN_PORT_DDI_A_LANES;
5661 case PORT_B:
5662 return POWER_DOMAIN_PORT_DDI_B_LANES;
5663 case PORT_C:
5664 return POWER_DOMAIN_PORT_DDI_C_LANES;
5665 case PORT_D:
5666 return POWER_DOMAIN_PORT_DDI_D_LANES;
5667 case PORT_E:
5668 return POWER_DOMAIN_PORT_DDI_E_LANES;
5669 default:
5670 MISSING_CASE(port);
5671 return POWER_DOMAIN_PORT_OTHER;
5672 }
5673 }
5674
5675 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5676 {
5677 switch (port) {
5678 case PORT_A:
5679 return POWER_DOMAIN_AUX_A;
5680 case PORT_B:
5681 return POWER_DOMAIN_AUX_B;
5682 case PORT_C:
5683 return POWER_DOMAIN_AUX_C;
5684 case PORT_D:
5685 return POWER_DOMAIN_AUX_D;
5686 case PORT_E:
5687 /* FIXME: Check VBT for actual wiring of PORT E */
5688 return POWER_DOMAIN_AUX_D;
5689 default:
5690 MISSING_CASE(port);
5691 return POWER_DOMAIN_AUX_A;
5692 }
5693 }
5694
5695 enum intel_display_power_domain
5696 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5697 {
5698 struct drm_device *dev = intel_encoder->base.dev;
5699 struct intel_digital_port *intel_dig_port;
5700
5701 switch (intel_encoder->type) {
5702 case INTEL_OUTPUT_UNKNOWN:
5703 /* Only DDI platforms should ever use this output type */
5704 WARN_ON_ONCE(!HAS_DDI(dev));
5705 case INTEL_OUTPUT_DP:
5706 case INTEL_OUTPUT_HDMI:
5707 case INTEL_OUTPUT_EDP:
5708 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5709 return port_to_power_domain(intel_dig_port->port);
5710 case INTEL_OUTPUT_DP_MST:
5711 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5712 return port_to_power_domain(intel_dig_port->port);
5713 case INTEL_OUTPUT_ANALOG:
5714 return POWER_DOMAIN_PORT_CRT;
5715 case INTEL_OUTPUT_DSI:
5716 return POWER_DOMAIN_PORT_DSI;
5717 default:
5718 return POWER_DOMAIN_PORT_OTHER;
5719 }
5720 }
5721
5722 enum intel_display_power_domain
5723 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5724 {
5725 struct drm_device *dev = intel_encoder->base.dev;
5726 struct intel_digital_port *intel_dig_port;
5727
5728 switch (intel_encoder->type) {
5729 case INTEL_OUTPUT_UNKNOWN:
5730 case INTEL_OUTPUT_HDMI:
5731 /*
5732 * Only DDI platforms should ever use these output types.
5733 * We can get here after the HDMI detect code has already set
5734 * the type of the shared encoder. Since we can't be sure
5735 * what's the status of the given connectors, play safe and
5736 * run the DP detection too.
5737 */
5738 WARN_ON_ONCE(!HAS_DDI(dev));
5739 case INTEL_OUTPUT_DP:
5740 case INTEL_OUTPUT_EDP:
5741 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5742 return port_to_aux_power_domain(intel_dig_port->port);
5743 case INTEL_OUTPUT_DP_MST:
5744 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5745 return port_to_aux_power_domain(intel_dig_port->port);
5746 default:
5747 MISSING_CASE(intel_encoder->type);
5748 return POWER_DOMAIN_AUX_A;
5749 }
5750 }
5751
5752 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5753 struct intel_crtc_state *crtc_state)
5754 {
5755 struct drm_device *dev = crtc->dev;
5756 struct drm_encoder *encoder;
5757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758 enum pipe pipe = intel_crtc->pipe;
5759 unsigned long mask;
5760 enum transcoder transcoder = crtc_state->cpu_transcoder;
5761
5762 if (!crtc_state->base.active)
5763 return 0;
5764
5765 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5766 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5767 if (crtc_state->pch_pfit.enabled ||
5768 crtc_state->pch_pfit.force_thru)
5769 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5770
5771 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5772 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5773
5774 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5775 }
5776
5777 if (crtc_state->shared_dpll)
5778 mask |= BIT(POWER_DOMAIN_PLLS);
5779
5780 return mask;
5781 }
5782
5783 static unsigned long
5784 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5785 struct intel_crtc_state *crtc_state)
5786 {
5787 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5789 enum intel_display_power_domain domain;
5790 unsigned long domains, new_domains, old_domains;
5791
5792 old_domains = intel_crtc->enabled_power_domains;
5793 intel_crtc->enabled_power_domains = new_domains =
5794 get_crtc_power_domains(crtc, crtc_state);
5795
5796 domains = new_domains & ~old_domains;
5797
5798 for_each_power_domain(domain, domains)
5799 intel_display_power_get(dev_priv, domain);
5800
5801 return old_domains & ~new_domains;
5802 }
5803
5804 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5805 unsigned long domains)
5806 {
5807 enum intel_display_power_domain domain;
5808
5809 for_each_power_domain(domain, domains)
5810 intel_display_power_put(dev_priv, domain);
5811 }
5812
5813 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5814 {
5815 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5816
5817 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5818 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5819 return max_cdclk_freq;
5820 else if (IS_CHERRYVIEW(dev_priv))
5821 return max_cdclk_freq*95/100;
5822 else if (INTEL_INFO(dev_priv)->gen < 4)
5823 return 2*max_cdclk_freq*90/100;
5824 else
5825 return max_cdclk_freq*90/100;
5826 }
5827
5828 static int skl_calc_cdclk(int max_pixclk, int vco);
5829
5830 static void intel_update_max_cdclk(struct drm_device *dev)
5831 {
5832 struct drm_i915_private *dev_priv = to_i915(dev);
5833
5834 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5835 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5836 int max_cdclk, vco;
5837
5838 vco = dev_priv->skl_preferred_vco_freq;
5839 WARN_ON(vco != 8100000 && vco != 8640000);
5840
5841 /*
5842 * Use the lower (vco 8640) cdclk values as a
5843 * first guess. skl_calc_cdclk() will correct it
5844 * if the preferred vco is 8100 instead.
5845 */
5846 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5847 max_cdclk = 617143;
5848 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5849 max_cdclk = 540000;
5850 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5851 max_cdclk = 432000;
5852 else
5853 max_cdclk = 308571;
5854
5855 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5856 } else if (IS_BROXTON(dev)) {
5857 dev_priv->max_cdclk_freq = 624000;
5858 } else if (IS_BROADWELL(dev)) {
5859 /*
5860 * FIXME with extra cooling we can allow
5861 * 540 MHz for ULX and 675 Mhz for ULT.
5862 * How can we know if extra cooling is
5863 * available? PCI ID, VTB, something else?
5864 */
5865 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5866 dev_priv->max_cdclk_freq = 450000;
5867 else if (IS_BDW_ULX(dev))
5868 dev_priv->max_cdclk_freq = 450000;
5869 else if (IS_BDW_ULT(dev))
5870 dev_priv->max_cdclk_freq = 540000;
5871 else
5872 dev_priv->max_cdclk_freq = 675000;
5873 } else if (IS_CHERRYVIEW(dev)) {
5874 dev_priv->max_cdclk_freq = 320000;
5875 } else if (IS_VALLEYVIEW(dev)) {
5876 dev_priv->max_cdclk_freq = 400000;
5877 } else {
5878 /* otherwise assume cdclk is fixed */
5879 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5880 }
5881
5882 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5883
5884 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5885 dev_priv->max_cdclk_freq);
5886
5887 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5888 dev_priv->max_dotclk_freq);
5889 }
5890
5891 static void intel_update_cdclk(struct drm_device *dev)
5892 {
5893 struct drm_i915_private *dev_priv = to_i915(dev);
5894
5895 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5896
5897 if (INTEL_GEN(dev_priv) >= 9)
5898 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5899 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5900 dev_priv->cdclk_pll.ref);
5901 else
5902 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5903 dev_priv->cdclk_freq);
5904
5905 /*
5906 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5907 * Programmng [sic] note: bit[9:2] should be programmed to the number
5908 * of cdclk that generates 4MHz reference clock freq which is used to
5909 * generate GMBus clock. This will vary with the cdclk freq.
5910 */
5911 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5912 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5913 }
5914
5915 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5916 static int skl_cdclk_decimal(int cdclk)
5917 {
5918 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5919 }
5920
5921 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5922 {
5923 int ratio;
5924
5925 if (cdclk == dev_priv->cdclk_pll.ref)
5926 return 0;
5927
5928 switch (cdclk) {
5929 default:
5930 MISSING_CASE(cdclk);
5931 case 144000:
5932 case 288000:
5933 case 384000:
5934 case 576000:
5935 ratio = 60;
5936 break;
5937 case 624000:
5938 ratio = 65;
5939 break;
5940 }
5941
5942 return dev_priv->cdclk_pll.ref * ratio;
5943 }
5944
5945 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5946 {
5947 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5948
5949 /* Timeout 200us */
5950 if (intel_wait_for_register(dev_priv,
5951 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5952 1))
5953 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5954
5955 dev_priv->cdclk_pll.vco = 0;
5956 }
5957
5958 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5959 {
5960 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5961 u32 val;
5962
5963 val = I915_READ(BXT_DE_PLL_CTL);
5964 val &= ~BXT_DE_PLL_RATIO_MASK;
5965 val |= BXT_DE_PLL_RATIO(ratio);
5966 I915_WRITE(BXT_DE_PLL_CTL, val);
5967
5968 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5969
5970 /* Timeout 200us */
5971 if (intel_wait_for_register(dev_priv,
5972 BXT_DE_PLL_ENABLE,
5973 BXT_DE_PLL_LOCK,
5974 BXT_DE_PLL_LOCK,
5975 1))
5976 DRM_ERROR("timeout waiting for DE PLL lock\n");
5977
5978 dev_priv->cdclk_pll.vco = vco;
5979 }
5980
5981 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5982 {
5983 u32 val, divider;
5984 int vco, ret;
5985
5986 vco = bxt_de_pll_vco(dev_priv, cdclk);
5987
5988 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5989
5990 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5991 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5992 case 8:
5993 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5994 break;
5995 case 4:
5996 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5997 break;
5998 case 3:
5999 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6000 break;
6001 case 2:
6002 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6003 break;
6004 default:
6005 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6006 WARN_ON(vco != 0);
6007
6008 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6009 break;
6010 }
6011
6012 /* Inform power controller of upcoming frequency change */
6013 mutex_lock(&dev_priv->rps.hw_lock);
6014 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6015 0x80000000);
6016 mutex_unlock(&dev_priv->rps.hw_lock);
6017
6018 if (ret) {
6019 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6020 ret, cdclk);
6021 return;
6022 }
6023
6024 if (dev_priv->cdclk_pll.vco != 0 &&
6025 dev_priv->cdclk_pll.vco != vco)
6026 bxt_de_pll_disable(dev_priv);
6027
6028 if (dev_priv->cdclk_pll.vco != vco)
6029 bxt_de_pll_enable(dev_priv, vco);
6030
6031 val = divider | skl_cdclk_decimal(cdclk);
6032 /*
6033 * FIXME if only the cd2x divider needs changing, it could be done
6034 * without shutting off the pipe (if only one pipe is active).
6035 */
6036 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6037 /*
6038 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6039 * enable otherwise.
6040 */
6041 if (cdclk >= 500000)
6042 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6043 I915_WRITE(CDCLK_CTL, val);
6044
6045 mutex_lock(&dev_priv->rps.hw_lock);
6046 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6047 DIV_ROUND_UP(cdclk, 25000));
6048 mutex_unlock(&dev_priv->rps.hw_lock);
6049
6050 if (ret) {
6051 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6052 ret, cdclk);
6053 return;
6054 }
6055
6056 intel_update_cdclk(&dev_priv->drm);
6057 }
6058
6059 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6060 {
6061 u32 cdctl, expected;
6062
6063 intel_update_cdclk(&dev_priv->drm);
6064
6065 if (dev_priv->cdclk_pll.vco == 0 ||
6066 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6067 goto sanitize;
6068
6069 /* DPLL okay; verify the cdclock
6070 *
6071 * Some BIOS versions leave an incorrect decimal frequency value and
6072 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6073 * so sanitize this register.
6074 */
6075 cdctl = I915_READ(CDCLK_CTL);
6076 /*
6077 * Let's ignore the pipe field, since BIOS could have configured the
6078 * dividers both synching to an active pipe, or asynchronously
6079 * (PIPE_NONE).
6080 */
6081 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6082
6083 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6084 skl_cdclk_decimal(dev_priv->cdclk_freq);
6085 /*
6086 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6087 * enable otherwise.
6088 */
6089 if (dev_priv->cdclk_freq >= 500000)
6090 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6091
6092 if (cdctl == expected)
6093 /* All well; nothing to sanitize */
6094 return;
6095
6096 sanitize:
6097 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6098
6099 /* force cdclk programming */
6100 dev_priv->cdclk_freq = 0;
6101
6102 /* force full PLL disable + enable */
6103 dev_priv->cdclk_pll.vco = -1;
6104 }
6105
6106 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6107 {
6108 bxt_sanitize_cdclk(dev_priv);
6109
6110 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6111 return;
6112
6113 /*
6114 * FIXME:
6115 * - The initial CDCLK needs to be read from VBT.
6116 * Need to make this change after VBT has changes for BXT.
6117 */
6118 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6119 }
6120
6121 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6122 {
6123 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6124 }
6125
6126 static int skl_calc_cdclk(int max_pixclk, int vco)
6127 {
6128 if (vco == 8640000) {
6129 if (max_pixclk > 540000)
6130 return 617143;
6131 else if (max_pixclk > 432000)
6132 return 540000;
6133 else if (max_pixclk > 308571)
6134 return 432000;
6135 else
6136 return 308571;
6137 } else {
6138 if (max_pixclk > 540000)
6139 return 675000;
6140 else if (max_pixclk > 450000)
6141 return 540000;
6142 else if (max_pixclk > 337500)
6143 return 450000;
6144 else
6145 return 337500;
6146 }
6147 }
6148
6149 static void
6150 skl_dpll0_update(struct drm_i915_private *dev_priv)
6151 {
6152 u32 val;
6153
6154 dev_priv->cdclk_pll.ref = 24000;
6155 dev_priv->cdclk_pll.vco = 0;
6156
6157 val = I915_READ(LCPLL1_CTL);
6158 if ((val & LCPLL_PLL_ENABLE) == 0)
6159 return;
6160
6161 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6162 return;
6163
6164 val = I915_READ(DPLL_CTRL1);
6165
6166 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6167 DPLL_CTRL1_SSC(SKL_DPLL0) |
6168 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6169 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6170 return;
6171
6172 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6173 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6174 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6177 dev_priv->cdclk_pll.vco = 8100000;
6178 break;
6179 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6180 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6181 dev_priv->cdclk_pll.vco = 8640000;
6182 break;
6183 default:
6184 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6185 break;
6186 }
6187 }
6188
6189 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6190 {
6191 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6192
6193 dev_priv->skl_preferred_vco_freq = vco;
6194
6195 if (changed)
6196 intel_update_max_cdclk(&dev_priv->drm);
6197 }
6198
6199 static void
6200 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6201 {
6202 int min_cdclk = skl_calc_cdclk(0, vco);
6203 u32 val;
6204
6205 WARN_ON(vco != 8100000 && vco != 8640000);
6206
6207 /* select the minimum CDCLK before enabling DPLL 0 */
6208 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6209 I915_WRITE(CDCLK_CTL, val);
6210 POSTING_READ(CDCLK_CTL);
6211
6212 /*
6213 * We always enable DPLL0 with the lowest link rate possible, but still
6214 * taking into account the VCO required to operate the eDP panel at the
6215 * desired frequency. The usual DP link rates operate with a VCO of
6216 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6217 * The modeset code is responsible for the selection of the exact link
6218 * rate later on, with the constraint of choosing a frequency that
6219 * works with vco.
6220 */
6221 val = I915_READ(DPLL_CTRL1);
6222
6223 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6224 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6225 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6226 if (vco == 8640000)
6227 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6228 SKL_DPLL0);
6229 else
6230 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6231 SKL_DPLL0);
6232
6233 I915_WRITE(DPLL_CTRL1, val);
6234 POSTING_READ(DPLL_CTRL1);
6235
6236 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6237
6238 if (intel_wait_for_register(dev_priv,
6239 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6240 5))
6241 DRM_ERROR("DPLL0 not locked\n");
6242
6243 dev_priv->cdclk_pll.vco = vco;
6244
6245 /* We'll want to keep using the current vco from now on. */
6246 skl_set_preferred_cdclk_vco(dev_priv, vco);
6247 }
6248
6249 static void
6250 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6251 {
6252 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6253 if (intel_wait_for_register(dev_priv,
6254 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6255 1))
6256 DRM_ERROR("Couldn't disable DPLL0\n");
6257
6258 dev_priv->cdclk_pll.vco = 0;
6259 }
6260
6261 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6262 {
6263 int ret;
6264 u32 val;
6265
6266 /* inform PCU we want to change CDCLK */
6267 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6268 mutex_lock(&dev_priv->rps.hw_lock);
6269 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6270 mutex_unlock(&dev_priv->rps.hw_lock);
6271
6272 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6273 }
6274
6275 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6276 {
6277 return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6278 }
6279
6280 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6281 {
6282 struct drm_device *dev = &dev_priv->drm;
6283 u32 freq_select, pcu_ack;
6284
6285 WARN_ON((cdclk == 24000) != (vco == 0));
6286
6287 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6288
6289 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6290 DRM_ERROR("failed to inform PCU about cdclk change\n");
6291 return;
6292 }
6293
6294 /* set CDCLK_CTL */
6295 switch (cdclk) {
6296 case 450000:
6297 case 432000:
6298 freq_select = CDCLK_FREQ_450_432;
6299 pcu_ack = 1;
6300 break;
6301 case 540000:
6302 freq_select = CDCLK_FREQ_540;
6303 pcu_ack = 2;
6304 break;
6305 case 308571:
6306 case 337500:
6307 default:
6308 freq_select = CDCLK_FREQ_337_308;
6309 pcu_ack = 0;
6310 break;
6311 case 617143:
6312 case 675000:
6313 freq_select = CDCLK_FREQ_675_617;
6314 pcu_ack = 3;
6315 break;
6316 }
6317
6318 if (dev_priv->cdclk_pll.vco != 0 &&
6319 dev_priv->cdclk_pll.vco != vco)
6320 skl_dpll0_disable(dev_priv);
6321
6322 if (dev_priv->cdclk_pll.vco != vco)
6323 skl_dpll0_enable(dev_priv, vco);
6324
6325 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6326 POSTING_READ(CDCLK_CTL);
6327
6328 /* inform PCU of the change */
6329 mutex_lock(&dev_priv->rps.hw_lock);
6330 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6331 mutex_unlock(&dev_priv->rps.hw_lock);
6332
6333 intel_update_cdclk(dev);
6334 }
6335
6336 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6337
6338 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6339 {
6340 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6341 }
6342
6343 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6344 {
6345 int cdclk, vco;
6346
6347 skl_sanitize_cdclk(dev_priv);
6348
6349 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6350 /*
6351 * Use the current vco as our initial
6352 * guess as to what the preferred vco is.
6353 */
6354 if (dev_priv->skl_preferred_vco_freq == 0)
6355 skl_set_preferred_cdclk_vco(dev_priv,
6356 dev_priv->cdclk_pll.vco);
6357 return;
6358 }
6359
6360 vco = dev_priv->skl_preferred_vco_freq;
6361 if (vco == 0)
6362 vco = 8100000;
6363 cdclk = skl_calc_cdclk(0, vco);
6364
6365 skl_set_cdclk(dev_priv, cdclk, vco);
6366 }
6367
6368 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6369 {
6370 uint32_t cdctl, expected;
6371
6372 /*
6373 * check if the pre-os intialized the display
6374 * There is SWF18 scratchpad register defined which is set by the
6375 * pre-os which can be used by the OS drivers to check the status
6376 */
6377 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6378 goto sanitize;
6379
6380 intel_update_cdclk(&dev_priv->drm);
6381 /* Is PLL enabled and locked ? */
6382 if (dev_priv->cdclk_pll.vco == 0 ||
6383 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6384 goto sanitize;
6385
6386 /* DPLL okay; verify the cdclock
6387 *
6388 * Noticed in some instances that the freq selection is correct but
6389 * decimal part is programmed wrong from BIOS where pre-os does not
6390 * enable display. Verify the same as well.
6391 */
6392 cdctl = I915_READ(CDCLK_CTL);
6393 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6394 skl_cdclk_decimal(dev_priv->cdclk_freq);
6395 if (cdctl == expected)
6396 /* All well; nothing to sanitize */
6397 return;
6398
6399 sanitize:
6400 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6401
6402 /* force cdclk programming */
6403 dev_priv->cdclk_freq = 0;
6404 /* force full PLL disable + enable */
6405 dev_priv->cdclk_pll.vco = -1;
6406 }
6407
6408 /* Adjust CDclk dividers to allow high res or save power if possible */
6409 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6410 {
6411 struct drm_i915_private *dev_priv = to_i915(dev);
6412 u32 val, cmd;
6413
6414 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6415 != dev_priv->cdclk_freq);
6416
6417 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6418 cmd = 2;
6419 else if (cdclk == 266667)
6420 cmd = 1;
6421 else
6422 cmd = 0;
6423
6424 mutex_lock(&dev_priv->rps.hw_lock);
6425 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6426 val &= ~DSPFREQGUAR_MASK;
6427 val |= (cmd << DSPFREQGUAR_SHIFT);
6428 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6429 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6430 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6431 50)) {
6432 DRM_ERROR("timed out waiting for CDclk change\n");
6433 }
6434 mutex_unlock(&dev_priv->rps.hw_lock);
6435
6436 mutex_lock(&dev_priv->sb_lock);
6437
6438 if (cdclk == 400000) {
6439 u32 divider;
6440
6441 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6442
6443 /* adjust cdclk divider */
6444 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6445 val &= ~CCK_FREQUENCY_VALUES;
6446 val |= divider;
6447 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6448
6449 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6450 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6451 50))
6452 DRM_ERROR("timed out waiting for CDclk change\n");
6453 }
6454
6455 /* adjust self-refresh exit latency value */
6456 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6457 val &= ~0x7f;
6458
6459 /*
6460 * For high bandwidth configs, we set a higher latency in the bunit
6461 * so that the core display fetch happens in time to avoid underruns.
6462 */
6463 if (cdclk == 400000)
6464 val |= 4500 / 250; /* 4.5 usec */
6465 else
6466 val |= 3000 / 250; /* 3.0 usec */
6467 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6468
6469 mutex_unlock(&dev_priv->sb_lock);
6470
6471 intel_update_cdclk(dev);
6472 }
6473
6474 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6475 {
6476 struct drm_i915_private *dev_priv = to_i915(dev);
6477 u32 val, cmd;
6478
6479 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6480 != dev_priv->cdclk_freq);
6481
6482 switch (cdclk) {
6483 case 333333:
6484 case 320000:
6485 case 266667:
6486 case 200000:
6487 break;
6488 default:
6489 MISSING_CASE(cdclk);
6490 return;
6491 }
6492
6493 /*
6494 * Specs are full of misinformation, but testing on actual
6495 * hardware has shown that we just need to write the desired
6496 * CCK divider into the Punit register.
6497 */
6498 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6499
6500 mutex_lock(&dev_priv->rps.hw_lock);
6501 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6502 val &= ~DSPFREQGUAR_MASK_CHV;
6503 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6504 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6505 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6506 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6507 50)) {
6508 DRM_ERROR("timed out waiting for CDclk change\n");
6509 }
6510 mutex_unlock(&dev_priv->rps.hw_lock);
6511
6512 intel_update_cdclk(dev);
6513 }
6514
6515 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6516 int max_pixclk)
6517 {
6518 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6519 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6520
6521 /*
6522 * Really only a few cases to deal with, as only 4 CDclks are supported:
6523 * 200MHz
6524 * 267MHz
6525 * 320/333MHz (depends on HPLL freq)
6526 * 400MHz (VLV only)
6527 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6528 * of the lower bin and adjust if needed.
6529 *
6530 * We seem to get an unstable or solid color picture at 200MHz.
6531 * Not sure what's wrong. For now use 200MHz only when all pipes
6532 * are off.
6533 */
6534 if (!IS_CHERRYVIEW(dev_priv) &&
6535 max_pixclk > freq_320*limit/100)
6536 return 400000;
6537 else if (max_pixclk > 266667*limit/100)
6538 return freq_320;
6539 else if (max_pixclk > 0)
6540 return 266667;
6541 else
6542 return 200000;
6543 }
6544
6545 static int bxt_calc_cdclk(int max_pixclk)
6546 {
6547 if (max_pixclk > 576000)
6548 return 624000;
6549 else if (max_pixclk > 384000)
6550 return 576000;
6551 else if (max_pixclk > 288000)
6552 return 384000;
6553 else if (max_pixclk > 144000)
6554 return 288000;
6555 else
6556 return 144000;
6557 }
6558
6559 /* Compute the max pixel clock for new configuration. */
6560 static int intel_mode_max_pixclk(struct drm_device *dev,
6561 struct drm_atomic_state *state)
6562 {
6563 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6564 struct drm_i915_private *dev_priv = to_i915(dev);
6565 struct drm_crtc *crtc;
6566 struct drm_crtc_state *crtc_state;
6567 unsigned max_pixclk = 0, i;
6568 enum pipe pipe;
6569
6570 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6571 sizeof(intel_state->min_pixclk));
6572
6573 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6574 int pixclk = 0;
6575
6576 if (crtc_state->enable)
6577 pixclk = crtc_state->adjusted_mode.crtc_clock;
6578
6579 intel_state->min_pixclk[i] = pixclk;
6580 }
6581
6582 for_each_pipe(dev_priv, pipe)
6583 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6584
6585 return max_pixclk;
6586 }
6587
6588 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6589 {
6590 struct drm_device *dev = state->dev;
6591 struct drm_i915_private *dev_priv = to_i915(dev);
6592 int max_pixclk = intel_mode_max_pixclk(dev, state);
6593 struct intel_atomic_state *intel_state =
6594 to_intel_atomic_state(state);
6595
6596 intel_state->cdclk = intel_state->dev_cdclk =
6597 valleyview_calc_cdclk(dev_priv, max_pixclk);
6598
6599 if (!intel_state->active_crtcs)
6600 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6601
6602 return 0;
6603 }
6604
6605 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6606 {
6607 int max_pixclk = ilk_max_pixel_rate(state);
6608 struct intel_atomic_state *intel_state =
6609 to_intel_atomic_state(state);
6610
6611 intel_state->cdclk = intel_state->dev_cdclk =
6612 bxt_calc_cdclk(max_pixclk);
6613
6614 if (!intel_state->active_crtcs)
6615 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6616
6617 return 0;
6618 }
6619
6620 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6621 {
6622 unsigned int credits, default_credits;
6623
6624 if (IS_CHERRYVIEW(dev_priv))
6625 default_credits = PFI_CREDIT(12);
6626 else
6627 default_credits = PFI_CREDIT(8);
6628
6629 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6630 /* CHV suggested value is 31 or 63 */
6631 if (IS_CHERRYVIEW(dev_priv))
6632 credits = PFI_CREDIT_63;
6633 else
6634 credits = PFI_CREDIT(15);
6635 } else {
6636 credits = default_credits;
6637 }
6638
6639 /*
6640 * WA - write default credits before re-programming
6641 * FIXME: should we also set the resend bit here?
6642 */
6643 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6644 default_credits);
6645
6646 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6647 credits | PFI_CREDIT_RESEND);
6648
6649 /*
6650 * FIXME is this guaranteed to clear
6651 * immediately or should we poll for it?
6652 */
6653 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6654 }
6655
6656 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6657 {
6658 struct drm_device *dev = old_state->dev;
6659 struct drm_i915_private *dev_priv = to_i915(dev);
6660 struct intel_atomic_state *old_intel_state =
6661 to_intel_atomic_state(old_state);
6662 unsigned req_cdclk = old_intel_state->dev_cdclk;
6663
6664 /*
6665 * FIXME: We can end up here with all power domains off, yet
6666 * with a CDCLK frequency other than the minimum. To account
6667 * for this take the PIPE-A power domain, which covers the HW
6668 * blocks needed for the following programming. This can be
6669 * removed once it's guaranteed that we get here either with
6670 * the minimum CDCLK set, or the required power domains
6671 * enabled.
6672 */
6673 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6674
6675 if (IS_CHERRYVIEW(dev))
6676 cherryview_set_cdclk(dev, req_cdclk);
6677 else
6678 valleyview_set_cdclk(dev, req_cdclk);
6679
6680 vlv_program_pfi_credits(dev_priv);
6681
6682 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6683 }
6684
6685 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6686 struct drm_atomic_state *old_state)
6687 {
6688 struct drm_crtc *crtc = pipe_config->base.crtc;
6689 struct drm_device *dev = crtc->dev;
6690 struct drm_i915_private *dev_priv = to_i915(dev);
6691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6692 int pipe = intel_crtc->pipe;
6693
6694 if (WARN_ON(intel_crtc->active))
6695 return;
6696
6697 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6698 intel_dp_set_m_n(intel_crtc, M1_N1);
6699
6700 intel_set_pipe_timings(intel_crtc);
6701 intel_set_pipe_src_size(intel_crtc);
6702
6703 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6704 struct drm_i915_private *dev_priv = to_i915(dev);
6705
6706 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6707 I915_WRITE(CHV_CANVAS(pipe), 0);
6708 }
6709
6710 i9xx_set_pipeconf(intel_crtc);
6711
6712 intel_crtc->active = true;
6713
6714 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6715
6716 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6717
6718 if (IS_CHERRYVIEW(dev)) {
6719 chv_prepare_pll(intel_crtc, intel_crtc->config);
6720 chv_enable_pll(intel_crtc, intel_crtc->config);
6721 } else {
6722 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6723 vlv_enable_pll(intel_crtc, intel_crtc->config);
6724 }
6725
6726 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6727
6728 i9xx_pfit_enable(intel_crtc);
6729
6730 intel_color_load_luts(&pipe_config->base);
6731
6732 intel_update_watermarks(crtc);
6733 intel_enable_pipe(intel_crtc);
6734
6735 assert_vblank_disabled(crtc);
6736 drm_crtc_vblank_on(crtc);
6737
6738 intel_encoders_enable(crtc, pipe_config, old_state);
6739 }
6740
6741 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6742 {
6743 struct drm_device *dev = crtc->base.dev;
6744 struct drm_i915_private *dev_priv = to_i915(dev);
6745
6746 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6747 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6748 }
6749
6750 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6751 struct drm_atomic_state *old_state)
6752 {
6753 struct drm_crtc *crtc = pipe_config->base.crtc;
6754 struct drm_device *dev = crtc->dev;
6755 struct drm_i915_private *dev_priv = to_i915(dev);
6756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6757 enum pipe pipe = intel_crtc->pipe;
6758
6759 if (WARN_ON(intel_crtc->active))
6760 return;
6761
6762 i9xx_set_pll_dividers(intel_crtc);
6763
6764 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6765 intel_dp_set_m_n(intel_crtc, M1_N1);
6766
6767 intel_set_pipe_timings(intel_crtc);
6768 intel_set_pipe_src_size(intel_crtc);
6769
6770 i9xx_set_pipeconf(intel_crtc);
6771
6772 intel_crtc->active = true;
6773
6774 if (!IS_GEN2(dev))
6775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6776
6777 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6778
6779 i9xx_enable_pll(intel_crtc);
6780
6781 i9xx_pfit_enable(intel_crtc);
6782
6783 intel_color_load_luts(&pipe_config->base);
6784
6785 intel_update_watermarks(crtc);
6786 intel_enable_pipe(intel_crtc);
6787
6788 assert_vblank_disabled(crtc);
6789 drm_crtc_vblank_on(crtc);
6790
6791 intel_encoders_enable(crtc, pipe_config, old_state);
6792 }
6793
6794 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6795 {
6796 struct drm_device *dev = crtc->base.dev;
6797 struct drm_i915_private *dev_priv = to_i915(dev);
6798
6799 if (!crtc->config->gmch_pfit.control)
6800 return;
6801
6802 assert_pipe_disabled(dev_priv, crtc->pipe);
6803
6804 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6805 I915_READ(PFIT_CONTROL));
6806 I915_WRITE(PFIT_CONTROL, 0);
6807 }
6808
6809 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6810 struct drm_atomic_state *old_state)
6811 {
6812 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6813 struct drm_device *dev = crtc->dev;
6814 struct drm_i915_private *dev_priv = to_i915(dev);
6815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6816 int pipe = intel_crtc->pipe;
6817
6818 /*
6819 * On gen2 planes are double buffered but the pipe isn't, so we must
6820 * wait for planes to fully turn off before disabling the pipe.
6821 */
6822 if (IS_GEN2(dev))
6823 intel_wait_for_vblank(dev, pipe);
6824
6825 intel_encoders_disable(crtc, old_crtc_state, old_state);
6826
6827 drm_crtc_vblank_off(crtc);
6828 assert_vblank_disabled(crtc);
6829
6830 intel_disable_pipe(intel_crtc);
6831
6832 i9xx_pfit_disable(intel_crtc);
6833
6834 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6835
6836 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6837 if (IS_CHERRYVIEW(dev))
6838 chv_disable_pll(dev_priv, pipe);
6839 else if (IS_VALLEYVIEW(dev))
6840 vlv_disable_pll(dev_priv, pipe);
6841 else
6842 i9xx_disable_pll(intel_crtc);
6843 }
6844
6845 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6846
6847 if (!IS_GEN2(dev))
6848 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6849 }
6850
6851 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6852 {
6853 struct intel_encoder *encoder;
6854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6855 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6856 enum intel_display_power_domain domain;
6857 unsigned long domains;
6858 struct drm_atomic_state *state;
6859 struct intel_crtc_state *crtc_state;
6860 int ret;
6861
6862 if (!intel_crtc->active)
6863 return;
6864
6865 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6866 WARN_ON(intel_crtc->flip_work);
6867
6868 intel_pre_disable_primary_noatomic(crtc);
6869
6870 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6871 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6872 }
6873
6874 state = drm_atomic_state_alloc(crtc->dev);
6875 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6876
6877 /* Everything's already locked, -EDEADLK can't happen. */
6878 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6879 ret = drm_atomic_add_affected_connectors(state, crtc);
6880
6881 WARN_ON(IS_ERR(crtc_state) || ret);
6882
6883 dev_priv->display.crtc_disable(crtc_state, state);
6884
6885 drm_atomic_state_free(state);
6886
6887 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6888 crtc->base.id, crtc->name);
6889
6890 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6891 crtc->state->active = false;
6892 intel_crtc->active = false;
6893 crtc->enabled = false;
6894 crtc->state->connector_mask = 0;
6895 crtc->state->encoder_mask = 0;
6896
6897 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6898 encoder->base.crtc = NULL;
6899
6900 intel_fbc_disable(intel_crtc);
6901 intel_update_watermarks(crtc);
6902 intel_disable_shared_dpll(intel_crtc);
6903
6904 domains = intel_crtc->enabled_power_domains;
6905 for_each_power_domain(domain, domains)
6906 intel_display_power_put(dev_priv, domain);
6907 intel_crtc->enabled_power_domains = 0;
6908
6909 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6910 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6911 }
6912
6913 /*
6914 * turn all crtc's off, but do not adjust state
6915 * This has to be paired with a call to intel_modeset_setup_hw_state.
6916 */
6917 int intel_display_suspend(struct drm_device *dev)
6918 {
6919 struct drm_i915_private *dev_priv = to_i915(dev);
6920 struct drm_atomic_state *state;
6921 int ret;
6922
6923 state = drm_atomic_helper_suspend(dev);
6924 ret = PTR_ERR_OR_ZERO(state);
6925 if (ret)
6926 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6927 else
6928 dev_priv->modeset_restore_state = state;
6929 return ret;
6930 }
6931
6932 void intel_encoder_destroy(struct drm_encoder *encoder)
6933 {
6934 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6935
6936 drm_encoder_cleanup(encoder);
6937 kfree(intel_encoder);
6938 }
6939
6940 /* Cross check the actual hw state with our own modeset state tracking (and it's
6941 * internal consistency). */
6942 static void intel_connector_verify_state(struct intel_connector *connector)
6943 {
6944 struct drm_crtc *crtc = connector->base.state->crtc;
6945
6946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6947 connector->base.base.id,
6948 connector->base.name);
6949
6950 if (connector->get_hw_state(connector)) {
6951 struct intel_encoder *encoder = connector->encoder;
6952 struct drm_connector_state *conn_state = connector->base.state;
6953
6954 I915_STATE_WARN(!crtc,
6955 "connector enabled without attached crtc\n");
6956
6957 if (!crtc)
6958 return;
6959
6960 I915_STATE_WARN(!crtc->state->active,
6961 "connector is active, but attached crtc isn't\n");
6962
6963 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6964 return;
6965
6966 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6967 "atomic encoder doesn't match attached encoder\n");
6968
6969 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6970 "attached encoder crtc differs from connector crtc\n");
6971 } else {
6972 I915_STATE_WARN(crtc && crtc->state->active,
6973 "attached crtc is active, but connector isn't\n");
6974 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6975 "best encoder set without crtc!\n");
6976 }
6977 }
6978
6979 int intel_connector_init(struct intel_connector *connector)
6980 {
6981 drm_atomic_helper_connector_reset(&connector->base);
6982
6983 if (!connector->base.state)
6984 return -ENOMEM;
6985
6986 return 0;
6987 }
6988
6989 struct intel_connector *intel_connector_alloc(void)
6990 {
6991 struct intel_connector *connector;
6992
6993 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6994 if (!connector)
6995 return NULL;
6996
6997 if (intel_connector_init(connector) < 0) {
6998 kfree(connector);
6999 return NULL;
7000 }
7001
7002 return connector;
7003 }
7004
7005 /* Simple connector->get_hw_state implementation for encoders that support only
7006 * one connector and no cloning and hence the encoder state determines the state
7007 * of the connector. */
7008 bool intel_connector_get_hw_state(struct intel_connector *connector)
7009 {
7010 enum pipe pipe = 0;
7011 struct intel_encoder *encoder = connector->encoder;
7012
7013 return encoder->get_hw_state(encoder, &pipe);
7014 }
7015
7016 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7017 {
7018 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7019 return crtc_state->fdi_lanes;
7020
7021 return 0;
7022 }
7023
7024 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7025 struct intel_crtc_state *pipe_config)
7026 {
7027 struct drm_atomic_state *state = pipe_config->base.state;
7028 struct intel_crtc *other_crtc;
7029 struct intel_crtc_state *other_crtc_state;
7030
7031 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7032 pipe_name(pipe), pipe_config->fdi_lanes);
7033 if (pipe_config->fdi_lanes > 4) {
7034 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7035 pipe_name(pipe), pipe_config->fdi_lanes);
7036 return -EINVAL;
7037 }
7038
7039 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7040 if (pipe_config->fdi_lanes > 2) {
7041 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7042 pipe_config->fdi_lanes);
7043 return -EINVAL;
7044 } else {
7045 return 0;
7046 }
7047 }
7048
7049 if (INTEL_INFO(dev)->num_pipes == 2)
7050 return 0;
7051
7052 /* Ivybridge 3 pipe is really complicated */
7053 switch (pipe) {
7054 case PIPE_A:
7055 return 0;
7056 case PIPE_B:
7057 if (pipe_config->fdi_lanes <= 2)
7058 return 0;
7059
7060 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7061 other_crtc_state =
7062 intel_atomic_get_crtc_state(state, other_crtc);
7063 if (IS_ERR(other_crtc_state))
7064 return PTR_ERR(other_crtc_state);
7065
7066 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7067 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7068 pipe_name(pipe), pipe_config->fdi_lanes);
7069 return -EINVAL;
7070 }
7071 return 0;
7072 case PIPE_C:
7073 if (pipe_config->fdi_lanes > 2) {
7074 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7075 pipe_name(pipe), pipe_config->fdi_lanes);
7076 return -EINVAL;
7077 }
7078
7079 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7080 other_crtc_state =
7081 intel_atomic_get_crtc_state(state, other_crtc);
7082 if (IS_ERR(other_crtc_state))
7083 return PTR_ERR(other_crtc_state);
7084
7085 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7086 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7087 return -EINVAL;
7088 }
7089 return 0;
7090 default:
7091 BUG();
7092 }
7093 }
7094
7095 #define RETRY 1
7096 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7097 struct intel_crtc_state *pipe_config)
7098 {
7099 struct drm_device *dev = intel_crtc->base.dev;
7100 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7101 int lane, link_bw, fdi_dotclock, ret;
7102 bool needs_recompute = false;
7103
7104 retry:
7105 /* FDI is a binary signal running at ~2.7GHz, encoding
7106 * each output octet as 10 bits. The actual frequency
7107 * is stored as a divider into a 100MHz clock, and the
7108 * mode pixel clock is stored in units of 1KHz.
7109 * Hence the bw of each lane in terms of the mode signal
7110 * is:
7111 */
7112 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7113
7114 fdi_dotclock = adjusted_mode->crtc_clock;
7115
7116 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7117 pipe_config->pipe_bpp);
7118
7119 pipe_config->fdi_lanes = lane;
7120
7121 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7122 link_bw, &pipe_config->fdi_m_n);
7123
7124 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7125 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7126 pipe_config->pipe_bpp -= 2*3;
7127 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7128 pipe_config->pipe_bpp);
7129 needs_recompute = true;
7130 pipe_config->bw_constrained = true;
7131
7132 goto retry;
7133 }
7134
7135 if (needs_recompute)
7136 return RETRY;
7137
7138 return ret;
7139 }
7140
7141 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7142 struct intel_crtc_state *pipe_config)
7143 {
7144 if (pipe_config->pipe_bpp > 24)
7145 return false;
7146
7147 /* HSW can handle pixel rate up to cdclk? */
7148 if (IS_HASWELL(dev_priv))
7149 return true;
7150
7151 /*
7152 * We compare against max which means we must take
7153 * the increased cdclk requirement into account when
7154 * calculating the new cdclk.
7155 *
7156 * Should measure whether using a lower cdclk w/o IPS
7157 */
7158 return ilk_pipe_pixel_rate(pipe_config) <=
7159 dev_priv->max_cdclk_freq * 95 / 100;
7160 }
7161
7162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7163 struct intel_crtc_state *pipe_config)
7164 {
7165 struct drm_device *dev = crtc->base.dev;
7166 struct drm_i915_private *dev_priv = to_i915(dev);
7167
7168 pipe_config->ips_enabled = i915.enable_ips &&
7169 hsw_crtc_supports_ips(crtc) &&
7170 pipe_config_supports_ips(dev_priv, pipe_config);
7171 }
7172
7173 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7174 {
7175 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7176
7177 /* GDG double wide on either pipe, otherwise pipe A only */
7178 return INTEL_INFO(dev_priv)->gen < 4 &&
7179 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7180 }
7181
7182 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7183 struct intel_crtc_state *pipe_config)
7184 {
7185 struct drm_device *dev = crtc->base.dev;
7186 struct drm_i915_private *dev_priv = to_i915(dev);
7187 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7188 int clock_limit = dev_priv->max_dotclk_freq;
7189
7190 if (INTEL_INFO(dev)->gen < 4) {
7191 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7192
7193 /*
7194 * Enable double wide mode when the dot clock
7195 * is > 90% of the (display) core speed.
7196 */
7197 if (intel_crtc_supports_double_wide(crtc) &&
7198 adjusted_mode->crtc_clock > clock_limit) {
7199 clock_limit = dev_priv->max_dotclk_freq;
7200 pipe_config->double_wide = true;
7201 }
7202 }
7203
7204 if (adjusted_mode->crtc_clock > clock_limit) {
7205 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7206 adjusted_mode->crtc_clock, clock_limit,
7207 yesno(pipe_config->double_wide));
7208 return -EINVAL;
7209 }
7210
7211 /*
7212 * Pipe horizontal size must be even in:
7213 * - DVO ganged mode
7214 * - LVDS dual channel mode
7215 * - Double wide pipe
7216 */
7217 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7218 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7219 pipe_config->pipe_src_w &= ~1;
7220
7221 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7222 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7223 */
7224 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7225 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7226 return -EINVAL;
7227
7228 if (HAS_IPS(dev))
7229 hsw_compute_ips_config(crtc, pipe_config);
7230
7231 if (pipe_config->has_pch_encoder)
7232 return ironlake_fdi_compute_config(crtc, pipe_config);
7233
7234 return 0;
7235 }
7236
7237 static int skylake_get_display_clock_speed(struct drm_device *dev)
7238 {
7239 struct drm_i915_private *dev_priv = to_i915(dev);
7240 uint32_t cdctl;
7241
7242 skl_dpll0_update(dev_priv);
7243
7244 if (dev_priv->cdclk_pll.vco == 0)
7245 return dev_priv->cdclk_pll.ref;
7246
7247 cdctl = I915_READ(CDCLK_CTL);
7248
7249 if (dev_priv->cdclk_pll.vco == 8640000) {
7250 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7251 case CDCLK_FREQ_450_432:
7252 return 432000;
7253 case CDCLK_FREQ_337_308:
7254 return 308571;
7255 case CDCLK_FREQ_540:
7256 return 540000;
7257 case CDCLK_FREQ_675_617:
7258 return 617143;
7259 default:
7260 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7261 }
7262 } else {
7263 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7264 case CDCLK_FREQ_450_432:
7265 return 450000;
7266 case CDCLK_FREQ_337_308:
7267 return 337500;
7268 case CDCLK_FREQ_540:
7269 return 540000;
7270 case CDCLK_FREQ_675_617:
7271 return 675000;
7272 default:
7273 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7274 }
7275 }
7276
7277 return dev_priv->cdclk_pll.ref;
7278 }
7279
7280 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7281 {
7282 u32 val;
7283
7284 dev_priv->cdclk_pll.ref = 19200;
7285 dev_priv->cdclk_pll.vco = 0;
7286
7287 val = I915_READ(BXT_DE_PLL_ENABLE);
7288 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7289 return;
7290
7291 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7292 return;
7293
7294 val = I915_READ(BXT_DE_PLL_CTL);
7295 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7296 dev_priv->cdclk_pll.ref;
7297 }
7298
7299 static int broxton_get_display_clock_speed(struct drm_device *dev)
7300 {
7301 struct drm_i915_private *dev_priv = to_i915(dev);
7302 u32 divider;
7303 int div, vco;
7304
7305 bxt_de_pll_update(dev_priv);
7306
7307 vco = dev_priv->cdclk_pll.vco;
7308 if (vco == 0)
7309 return dev_priv->cdclk_pll.ref;
7310
7311 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7312
7313 switch (divider) {
7314 case BXT_CDCLK_CD2X_DIV_SEL_1:
7315 div = 2;
7316 break;
7317 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7318 div = 3;
7319 break;
7320 case BXT_CDCLK_CD2X_DIV_SEL_2:
7321 div = 4;
7322 break;
7323 case BXT_CDCLK_CD2X_DIV_SEL_4:
7324 div = 8;
7325 break;
7326 default:
7327 MISSING_CASE(divider);
7328 return dev_priv->cdclk_pll.ref;
7329 }
7330
7331 return DIV_ROUND_CLOSEST(vco, div);
7332 }
7333
7334 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7335 {
7336 struct drm_i915_private *dev_priv = to_i915(dev);
7337 uint32_t lcpll = I915_READ(LCPLL_CTL);
7338 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7339
7340 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7341 return 800000;
7342 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7343 return 450000;
7344 else if (freq == LCPLL_CLK_FREQ_450)
7345 return 450000;
7346 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7347 return 540000;
7348 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7349 return 337500;
7350 else
7351 return 675000;
7352 }
7353
7354 static int haswell_get_display_clock_speed(struct drm_device *dev)
7355 {
7356 struct drm_i915_private *dev_priv = to_i915(dev);
7357 uint32_t lcpll = I915_READ(LCPLL_CTL);
7358 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7359
7360 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7361 return 800000;
7362 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7363 return 450000;
7364 else if (freq == LCPLL_CLK_FREQ_450)
7365 return 450000;
7366 else if (IS_HSW_ULT(dev))
7367 return 337500;
7368 else
7369 return 540000;
7370 }
7371
7372 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7373 {
7374 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7375 CCK_DISPLAY_CLOCK_CONTROL);
7376 }
7377
7378 static int ilk_get_display_clock_speed(struct drm_device *dev)
7379 {
7380 return 450000;
7381 }
7382
7383 static int i945_get_display_clock_speed(struct drm_device *dev)
7384 {
7385 return 400000;
7386 }
7387
7388 static int i915_get_display_clock_speed(struct drm_device *dev)
7389 {
7390 return 333333;
7391 }
7392
7393 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7394 {
7395 return 200000;
7396 }
7397
7398 static int pnv_get_display_clock_speed(struct drm_device *dev)
7399 {
7400 struct pci_dev *pdev = dev->pdev;
7401 u16 gcfgc = 0;
7402
7403 pci_read_config_word(pdev, GCFGC, &gcfgc);
7404
7405 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7406 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7407 return 266667;
7408 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7409 return 333333;
7410 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7411 return 444444;
7412 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7413 return 200000;
7414 default:
7415 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7416 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7417 return 133333;
7418 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7419 return 166667;
7420 }
7421 }
7422
7423 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7424 {
7425 struct pci_dev *pdev = dev->pdev;
7426 u16 gcfgc = 0;
7427
7428 pci_read_config_word(pdev, GCFGC, &gcfgc);
7429
7430 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7431 return 133333;
7432 else {
7433 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7434 case GC_DISPLAY_CLOCK_333_MHZ:
7435 return 333333;
7436 default:
7437 case GC_DISPLAY_CLOCK_190_200_MHZ:
7438 return 190000;
7439 }
7440 }
7441 }
7442
7443 static int i865_get_display_clock_speed(struct drm_device *dev)
7444 {
7445 return 266667;
7446 }
7447
7448 static int i85x_get_display_clock_speed(struct drm_device *dev)
7449 {
7450 struct pci_dev *pdev = dev->pdev;
7451 u16 hpllcc = 0;
7452
7453 /*
7454 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7455 * encoding is different :(
7456 * FIXME is this the right way to detect 852GM/852GMV?
7457 */
7458 if (pdev->revision == 0x1)
7459 return 133333;
7460
7461 pci_bus_read_config_word(pdev->bus,
7462 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7463
7464 /* Assume that the hardware is in the high speed state. This
7465 * should be the default.
7466 */
7467 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7468 case GC_CLOCK_133_200:
7469 case GC_CLOCK_133_200_2:
7470 case GC_CLOCK_100_200:
7471 return 200000;
7472 case GC_CLOCK_166_250:
7473 return 250000;
7474 case GC_CLOCK_100_133:
7475 return 133333;
7476 case GC_CLOCK_133_266:
7477 case GC_CLOCK_133_266_2:
7478 case GC_CLOCK_166_266:
7479 return 266667;
7480 }
7481
7482 /* Shouldn't happen */
7483 return 0;
7484 }
7485
7486 static int i830_get_display_clock_speed(struct drm_device *dev)
7487 {
7488 return 133333;
7489 }
7490
7491 static unsigned int intel_hpll_vco(struct drm_device *dev)
7492 {
7493 struct drm_i915_private *dev_priv = to_i915(dev);
7494 static const unsigned int blb_vco[8] = {
7495 [0] = 3200000,
7496 [1] = 4000000,
7497 [2] = 5333333,
7498 [3] = 4800000,
7499 [4] = 6400000,
7500 };
7501 static const unsigned int pnv_vco[8] = {
7502 [0] = 3200000,
7503 [1] = 4000000,
7504 [2] = 5333333,
7505 [3] = 4800000,
7506 [4] = 2666667,
7507 };
7508 static const unsigned int cl_vco[8] = {
7509 [0] = 3200000,
7510 [1] = 4000000,
7511 [2] = 5333333,
7512 [3] = 6400000,
7513 [4] = 3333333,
7514 [5] = 3566667,
7515 [6] = 4266667,
7516 };
7517 static const unsigned int elk_vco[8] = {
7518 [0] = 3200000,
7519 [1] = 4000000,
7520 [2] = 5333333,
7521 [3] = 4800000,
7522 };
7523 static const unsigned int ctg_vco[8] = {
7524 [0] = 3200000,
7525 [1] = 4000000,
7526 [2] = 5333333,
7527 [3] = 6400000,
7528 [4] = 2666667,
7529 [5] = 4266667,
7530 };
7531 const unsigned int *vco_table;
7532 unsigned int vco;
7533 uint8_t tmp = 0;
7534
7535 /* FIXME other chipsets? */
7536 if (IS_GM45(dev))
7537 vco_table = ctg_vco;
7538 else if (IS_G4X(dev))
7539 vco_table = elk_vco;
7540 else if (IS_CRESTLINE(dev))
7541 vco_table = cl_vco;
7542 else if (IS_PINEVIEW(dev))
7543 vco_table = pnv_vco;
7544 else if (IS_G33(dev))
7545 vco_table = blb_vco;
7546 else
7547 return 0;
7548
7549 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7550
7551 vco = vco_table[tmp & 0x7];
7552 if (vco == 0)
7553 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7554 else
7555 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7556
7557 return vco;
7558 }
7559
7560 static int gm45_get_display_clock_speed(struct drm_device *dev)
7561 {
7562 struct pci_dev *pdev = dev->pdev;
7563 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7564 uint16_t tmp = 0;
7565
7566 pci_read_config_word(pdev, GCFGC, &tmp);
7567
7568 cdclk_sel = (tmp >> 12) & 0x1;
7569
7570 switch (vco) {
7571 case 2666667:
7572 case 4000000:
7573 case 5333333:
7574 return cdclk_sel ? 333333 : 222222;
7575 case 3200000:
7576 return cdclk_sel ? 320000 : 228571;
7577 default:
7578 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7579 return 222222;
7580 }
7581 }
7582
7583 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7584 {
7585 struct pci_dev *pdev = dev->pdev;
7586 static const uint8_t div_3200[] = { 16, 10, 8 };
7587 static const uint8_t div_4000[] = { 20, 12, 10 };
7588 static const uint8_t div_5333[] = { 24, 16, 14 };
7589 const uint8_t *div_table;
7590 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7591 uint16_t tmp = 0;
7592
7593 pci_read_config_word(pdev, GCFGC, &tmp);
7594
7595 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7596
7597 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7598 goto fail;
7599
7600 switch (vco) {
7601 case 3200000:
7602 div_table = div_3200;
7603 break;
7604 case 4000000:
7605 div_table = div_4000;
7606 break;
7607 case 5333333:
7608 div_table = div_5333;
7609 break;
7610 default:
7611 goto fail;
7612 }
7613
7614 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7615
7616 fail:
7617 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7618 return 200000;
7619 }
7620
7621 static int g33_get_display_clock_speed(struct drm_device *dev)
7622 {
7623 struct pci_dev *pdev = dev->pdev;
7624 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7625 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7626 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7627 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7628 const uint8_t *div_table;
7629 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7630 uint16_t tmp = 0;
7631
7632 pci_read_config_word(pdev, GCFGC, &tmp);
7633
7634 cdclk_sel = (tmp >> 4) & 0x7;
7635
7636 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7637 goto fail;
7638
7639 switch (vco) {
7640 case 3200000:
7641 div_table = div_3200;
7642 break;
7643 case 4000000:
7644 div_table = div_4000;
7645 break;
7646 case 4800000:
7647 div_table = div_4800;
7648 break;
7649 case 5333333:
7650 div_table = div_5333;
7651 break;
7652 default:
7653 goto fail;
7654 }
7655
7656 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7657
7658 fail:
7659 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7660 return 190476;
7661 }
7662
7663 static void
7664 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7665 {
7666 while (*num > DATA_LINK_M_N_MASK ||
7667 *den > DATA_LINK_M_N_MASK) {
7668 *num >>= 1;
7669 *den >>= 1;
7670 }
7671 }
7672
7673 static void compute_m_n(unsigned int m, unsigned int n,
7674 uint32_t *ret_m, uint32_t *ret_n)
7675 {
7676 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7677 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7678 intel_reduce_m_n_ratio(ret_m, ret_n);
7679 }
7680
7681 void
7682 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7683 int pixel_clock, int link_clock,
7684 struct intel_link_m_n *m_n)
7685 {
7686 m_n->tu = 64;
7687
7688 compute_m_n(bits_per_pixel * pixel_clock,
7689 link_clock * nlanes * 8,
7690 &m_n->gmch_m, &m_n->gmch_n);
7691
7692 compute_m_n(pixel_clock, link_clock,
7693 &m_n->link_m, &m_n->link_n);
7694 }
7695
7696 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7697 {
7698 if (i915.panel_use_ssc >= 0)
7699 return i915.panel_use_ssc != 0;
7700 return dev_priv->vbt.lvds_use_ssc
7701 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7702 }
7703
7704 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7705 {
7706 return (1 << dpll->n) << 16 | dpll->m2;
7707 }
7708
7709 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7710 {
7711 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7712 }
7713
7714 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7715 struct intel_crtc_state *crtc_state,
7716 struct dpll *reduced_clock)
7717 {
7718 struct drm_device *dev = crtc->base.dev;
7719 u32 fp, fp2 = 0;
7720
7721 if (IS_PINEVIEW(dev)) {
7722 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7723 if (reduced_clock)
7724 fp2 = pnv_dpll_compute_fp(reduced_clock);
7725 } else {
7726 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7727 if (reduced_clock)
7728 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7729 }
7730
7731 crtc_state->dpll_hw_state.fp0 = fp;
7732
7733 crtc->lowfreq_avail = false;
7734 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7735 reduced_clock) {
7736 crtc_state->dpll_hw_state.fp1 = fp2;
7737 crtc->lowfreq_avail = true;
7738 } else {
7739 crtc_state->dpll_hw_state.fp1 = fp;
7740 }
7741 }
7742
7743 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7744 pipe)
7745 {
7746 u32 reg_val;
7747
7748 /*
7749 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7750 * and set it to a reasonable value instead.
7751 */
7752 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7753 reg_val &= 0xffffff00;
7754 reg_val |= 0x00000030;
7755 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7756
7757 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7758 reg_val &= 0x8cffffff;
7759 reg_val = 0x8c000000;
7760 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7761
7762 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7763 reg_val &= 0xffffff00;
7764 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7765
7766 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7767 reg_val &= 0x00ffffff;
7768 reg_val |= 0xb0000000;
7769 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7770 }
7771
7772 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7773 struct intel_link_m_n *m_n)
7774 {
7775 struct drm_device *dev = crtc->base.dev;
7776 struct drm_i915_private *dev_priv = to_i915(dev);
7777 int pipe = crtc->pipe;
7778
7779 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7780 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7781 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7782 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7783 }
7784
7785 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7786 struct intel_link_m_n *m_n,
7787 struct intel_link_m_n *m2_n2)
7788 {
7789 struct drm_device *dev = crtc->base.dev;
7790 struct drm_i915_private *dev_priv = to_i915(dev);
7791 int pipe = crtc->pipe;
7792 enum transcoder transcoder = crtc->config->cpu_transcoder;
7793
7794 if (INTEL_INFO(dev)->gen >= 5) {
7795 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7796 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7797 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7798 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7799 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7800 * for gen < 8) and if DRRS is supported (to make sure the
7801 * registers are not unnecessarily accessed).
7802 */
7803 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7804 crtc->config->has_drrs) {
7805 I915_WRITE(PIPE_DATA_M2(transcoder),
7806 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7807 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7808 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7809 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7810 }
7811 } else {
7812 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7813 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7814 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7815 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7816 }
7817 }
7818
7819 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7820 {
7821 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7822
7823 if (m_n == M1_N1) {
7824 dp_m_n = &crtc->config->dp_m_n;
7825 dp_m2_n2 = &crtc->config->dp_m2_n2;
7826 } else if (m_n == M2_N2) {
7827
7828 /*
7829 * M2_N2 registers are not supported. Hence m2_n2 divider value
7830 * needs to be programmed into M1_N1.
7831 */
7832 dp_m_n = &crtc->config->dp_m2_n2;
7833 } else {
7834 DRM_ERROR("Unsupported divider value\n");
7835 return;
7836 }
7837
7838 if (crtc->config->has_pch_encoder)
7839 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7840 else
7841 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7842 }
7843
7844 static void vlv_compute_dpll(struct intel_crtc *crtc,
7845 struct intel_crtc_state *pipe_config)
7846 {
7847 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7848 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7849 if (crtc->pipe != PIPE_A)
7850 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7851
7852 /* DPLL not used with DSI, but still need the rest set up */
7853 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7854 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7855 DPLL_EXT_BUFFER_ENABLE_VLV;
7856
7857 pipe_config->dpll_hw_state.dpll_md =
7858 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7859 }
7860
7861 static void chv_compute_dpll(struct intel_crtc *crtc,
7862 struct intel_crtc_state *pipe_config)
7863 {
7864 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7865 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7866 if (crtc->pipe != PIPE_A)
7867 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7868
7869 /* DPLL not used with DSI, but still need the rest set up */
7870 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7871 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7872
7873 pipe_config->dpll_hw_state.dpll_md =
7874 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7875 }
7876
7877 static void vlv_prepare_pll(struct intel_crtc *crtc,
7878 const struct intel_crtc_state *pipe_config)
7879 {
7880 struct drm_device *dev = crtc->base.dev;
7881 struct drm_i915_private *dev_priv = to_i915(dev);
7882 enum pipe pipe = crtc->pipe;
7883 u32 mdiv;
7884 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7885 u32 coreclk, reg_val;
7886
7887 /* Enable Refclk */
7888 I915_WRITE(DPLL(pipe),
7889 pipe_config->dpll_hw_state.dpll &
7890 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7891
7892 /* No need to actually set up the DPLL with DSI */
7893 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7894 return;
7895
7896 mutex_lock(&dev_priv->sb_lock);
7897
7898 bestn = pipe_config->dpll.n;
7899 bestm1 = pipe_config->dpll.m1;
7900 bestm2 = pipe_config->dpll.m2;
7901 bestp1 = pipe_config->dpll.p1;
7902 bestp2 = pipe_config->dpll.p2;
7903
7904 /* See eDP HDMI DPIO driver vbios notes doc */
7905
7906 /* PLL B needs special handling */
7907 if (pipe == PIPE_B)
7908 vlv_pllb_recal_opamp(dev_priv, pipe);
7909
7910 /* Set up Tx target for periodic Rcomp update */
7911 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7912
7913 /* Disable target IRef on PLL */
7914 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7915 reg_val &= 0x00ffffff;
7916 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7917
7918 /* Disable fast lock */
7919 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7920
7921 /* Set idtafcrecal before PLL is enabled */
7922 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7923 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7924 mdiv |= ((bestn << DPIO_N_SHIFT));
7925 mdiv |= (1 << DPIO_K_SHIFT);
7926
7927 /*
7928 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7929 * but we don't support that).
7930 * Note: don't use the DAC post divider as it seems unstable.
7931 */
7932 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7934
7935 mdiv |= DPIO_ENABLE_CALIBRATION;
7936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7937
7938 /* Set HBR and RBR LPF coefficients */
7939 if (pipe_config->port_clock == 162000 ||
7940 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7941 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7943 0x009f0003);
7944 else
7945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7946 0x00d0000f);
7947
7948 if (intel_crtc_has_dp_encoder(pipe_config)) {
7949 /* Use SSC source */
7950 if (pipe == PIPE_A)
7951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7952 0x0df40000);
7953 else
7954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7955 0x0df70000);
7956 } else { /* HDMI or VGA */
7957 /* Use bend source */
7958 if (pipe == PIPE_A)
7959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7960 0x0df70000);
7961 else
7962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963 0x0df40000);
7964 }
7965
7966 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7967 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7968 if (intel_crtc_has_dp_encoder(crtc->config))
7969 coreclk |= 0x01000000;
7970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7971
7972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7973 mutex_unlock(&dev_priv->sb_lock);
7974 }
7975
7976 static void chv_prepare_pll(struct intel_crtc *crtc,
7977 const struct intel_crtc_state *pipe_config)
7978 {
7979 struct drm_device *dev = crtc->base.dev;
7980 struct drm_i915_private *dev_priv = to_i915(dev);
7981 enum pipe pipe = crtc->pipe;
7982 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7983 u32 loopfilter, tribuf_calcntr;
7984 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7985 u32 dpio_val;
7986 int vco;
7987
7988 /* Enable Refclk and SSC */
7989 I915_WRITE(DPLL(pipe),
7990 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7991
7992 /* No need to actually set up the DPLL with DSI */
7993 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7994 return;
7995
7996 bestn = pipe_config->dpll.n;
7997 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7998 bestm1 = pipe_config->dpll.m1;
7999 bestm2 = pipe_config->dpll.m2 >> 22;
8000 bestp1 = pipe_config->dpll.p1;
8001 bestp2 = pipe_config->dpll.p2;
8002 vco = pipe_config->dpll.vco;
8003 dpio_val = 0;
8004 loopfilter = 0;
8005
8006 mutex_lock(&dev_priv->sb_lock);
8007
8008 /* p1 and p2 divider */
8009 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8010 5 << DPIO_CHV_S1_DIV_SHIFT |
8011 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8012 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8013 1 << DPIO_CHV_K_DIV_SHIFT);
8014
8015 /* Feedback post-divider - m2 */
8016 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8017
8018 /* Feedback refclk divider - n and m1 */
8019 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8020 DPIO_CHV_M1_DIV_BY_2 |
8021 1 << DPIO_CHV_N_DIV_SHIFT);
8022
8023 /* M2 fraction division */
8024 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8025
8026 /* M2 fraction division enable */
8027 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8028 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8029 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8030 if (bestm2_frac)
8031 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8032 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8033
8034 /* Program digital lock detect threshold */
8035 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8036 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8037 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8038 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8039 if (!bestm2_frac)
8040 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8041 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8042
8043 /* Loop filter */
8044 if (vco == 5400000) {
8045 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8046 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8047 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8048 tribuf_calcntr = 0x9;
8049 } else if (vco <= 6200000) {
8050 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8051 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8052 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8053 tribuf_calcntr = 0x9;
8054 } else if (vco <= 6480000) {
8055 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8056 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8057 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8058 tribuf_calcntr = 0x8;
8059 } else {
8060 /* Not supported. Apply the same limits as in the max case */
8061 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8062 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8063 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8064 tribuf_calcntr = 0;
8065 }
8066 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8067
8068 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8069 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8070 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8072
8073 /* AFC Recal */
8074 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8075 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8076 DPIO_AFC_RECAL);
8077
8078 mutex_unlock(&dev_priv->sb_lock);
8079 }
8080
8081 /**
8082 * vlv_force_pll_on - forcibly enable just the PLL
8083 * @dev_priv: i915 private structure
8084 * @pipe: pipe PLL to enable
8085 * @dpll: PLL configuration
8086 *
8087 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8088 * in cases where we need the PLL enabled even when @pipe is not going to
8089 * be enabled.
8090 */
8091 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8092 const struct dpll *dpll)
8093 {
8094 struct intel_crtc *crtc =
8095 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8096 struct intel_crtc_state *pipe_config;
8097
8098 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8099 if (!pipe_config)
8100 return -ENOMEM;
8101
8102 pipe_config->base.crtc = &crtc->base;
8103 pipe_config->pixel_multiplier = 1;
8104 pipe_config->dpll = *dpll;
8105
8106 if (IS_CHERRYVIEW(dev)) {
8107 chv_compute_dpll(crtc, pipe_config);
8108 chv_prepare_pll(crtc, pipe_config);
8109 chv_enable_pll(crtc, pipe_config);
8110 } else {
8111 vlv_compute_dpll(crtc, pipe_config);
8112 vlv_prepare_pll(crtc, pipe_config);
8113 vlv_enable_pll(crtc, pipe_config);
8114 }
8115
8116 kfree(pipe_config);
8117
8118 return 0;
8119 }
8120
8121 /**
8122 * vlv_force_pll_off - forcibly disable just the PLL
8123 * @dev_priv: i915 private structure
8124 * @pipe: pipe PLL to disable
8125 *
8126 * Disable the PLL for @pipe. To be used in cases where we need
8127 * the PLL enabled even when @pipe is not going to be enabled.
8128 */
8129 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8130 {
8131 if (IS_CHERRYVIEW(dev))
8132 chv_disable_pll(to_i915(dev), pipe);
8133 else
8134 vlv_disable_pll(to_i915(dev), pipe);
8135 }
8136
8137 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8138 struct intel_crtc_state *crtc_state,
8139 struct dpll *reduced_clock)
8140 {
8141 struct drm_device *dev = crtc->base.dev;
8142 struct drm_i915_private *dev_priv = to_i915(dev);
8143 u32 dpll;
8144 struct dpll *clock = &crtc_state->dpll;
8145
8146 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8147
8148 dpll = DPLL_VGA_MODE_DIS;
8149
8150 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8151 dpll |= DPLLB_MODE_LVDS;
8152 else
8153 dpll |= DPLLB_MODE_DAC_SERIAL;
8154
8155 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8156 dpll |= (crtc_state->pixel_multiplier - 1)
8157 << SDVO_MULTIPLIER_SHIFT_HIRES;
8158 }
8159
8160 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8161 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8162 dpll |= DPLL_SDVO_HIGH_SPEED;
8163
8164 if (intel_crtc_has_dp_encoder(crtc_state))
8165 dpll |= DPLL_SDVO_HIGH_SPEED;
8166
8167 /* compute bitmask from p1 value */
8168 if (IS_PINEVIEW(dev))
8169 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8170 else {
8171 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8172 if (IS_G4X(dev) && reduced_clock)
8173 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8174 }
8175 switch (clock->p2) {
8176 case 5:
8177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8178 break;
8179 case 7:
8180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8181 break;
8182 case 10:
8183 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8184 break;
8185 case 14:
8186 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8187 break;
8188 }
8189 if (INTEL_INFO(dev)->gen >= 4)
8190 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8191
8192 if (crtc_state->sdvo_tv_clock)
8193 dpll |= PLL_REF_INPUT_TVCLKINBC;
8194 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8195 intel_panel_use_ssc(dev_priv))
8196 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8197 else
8198 dpll |= PLL_REF_INPUT_DREFCLK;
8199
8200 dpll |= DPLL_VCO_ENABLE;
8201 crtc_state->dpll_hw_state.dpll = dpll;
8202
8203 if (INTEL_INFO(dev)->gen >= 4) {
8204 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8205 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8206 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8207 }
8208 }
8209
8210 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8211 struct intel_crtc_state *crtc_state,
8212 struct dpll *reduced_clock)
8213 {
8214 struct drm_device *dev = crtc->base.dev;
8215 struct drm_i915_private *dev_priv = to_i915(dev);
8216 u32 dpll;
8217 struct dpll *clock = &crtc_state->dpll;
8218
8219 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8220
8221 dpll = DPLL_VGA_MODE_DIS;
8222
8223 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8224 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8225 } else {
8226 if (clock->p1 == 2)
8227 dpll |= PLL_P1_DIVIDE_BY_TWO;
8228 else
8229 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8230 if (clock->p2 == 4)
8231 dpll |= PLL_P2_DIVIDE_BY_4;
8232 }
8233
8234 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8235 dpll |= DPLL_DVO_2X_MODE;
8236
8237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8238 intel_panel_use_ssc(dev_priv))
8239 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8240 else
8241 dpll |= PLL_REF_INPUT_DREFCLK;
8242
8243 dpll |= DPLL_VCO_ENABLE;
8244 crtc_state->dpll_hw_state.dpll = dpll;
8245 }
8246
8247 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8248 {
8249 struct drm_device *dev = intel_crtc->base.dev;
8250 struct drm_i915_private *dev_priv = to_i915(dev);
8251 enum pipe pipe = intel_crtc->pipe;
8252 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8253 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8254 uint32_t crtc_vtotal, crtc_vblank_end;
8255 int vsyncshift = 0;
8256
8257 /* We need to be careful not to changed the adjusted mode, for otherwise
8258 * the hw state checker will get angry at the mismatch. */
8259 crtc_vtotal = adjusted_mode->crtc_vtotal;
8260 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8261
8262 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8263 /* the chip adds 2 halflines automatically */
8264 crtc_vtotal -= 1;
8265 crtc_vblank_end -= 1;
8266
8267 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8268 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8269 else
8270 vsyncshift = adjusted_mode->crtc_hsync_start -
8271 adjusted_mode->crtc_htotal / 2;
8272 if (vsyncshift < 0)
8273 vsyncshift += adjusted_mode->crtc_htotal;
8274 }
8275
8276 if (INTEL_INFO(dev)->gen > 3)
8277 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8278
8279 I915_WRITE(HTOTAL(cpu_transcoder),
8280 (adjusted_mode->crtc_hdisplay - 1) |
8281 ((adjusted_mode->crtc_htotal - 1) << 16));
8282 I915_WRITE(HBLANK(cpu_transcoder),
8283 (adjusted_mode->crtc_hblank_start - 1) |
8284 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8285 I915_WRITE(HSYNC(cpu_transcoder),
8286 (adjusted_mode->crtc_hsync_start - 1) |
8287 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8288
8289 I915_WRITE(VTOTAL(cpu_transcoder),
8290 (adjusted_mode->crtc_vdisplay - 1) |
8291 ((crtc_vtotal - 1) << 16));
8292 I915_WRITE(VBLANK(cpu_transcoder),
8293 (adjusted_mode->crtc_vblank_start - 1) |
8294 ((crtc_vblank_end - 1) << 16));
8295 I915_WRITE(VSYNC(cpu_transcoder),
8296 (adjusted_mode->crtc_vsync_start - 1) |
8297 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8298
8299 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8300 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8301 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8302 * bits. */
8303 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8304 (pipe == PIPE_B || pipe == PIPE_C))
8305 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8306
8307 }
8308
8309 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8310 {
8311 struct drm_device *dev = intel_crtc->base.dev;
8312 struct drm_i915_private *dev_priv = to_i915(dev);
8313 enum pipe pipe = intel_crtc->pipe;
8314
8315 /* pipesrc controls the size that is scaled from, which should
8316 * always be the user's requested size.
8317 */
8318 I915_WRITE(PIPESRC(pipe),
8319 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8320 (intel_crtc->config->pipe_src_h - 1));
8321 }
8322
8323 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8324 struct intel_crtc_state *pipe_config)
8325 {
8326 struct drm_device *dev = crtc->base.dev;
8327 struct drm_i915_private *dev_priv = to_i915(dev);
8328 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8329 uint32_t tmp;
8330
8331 tmp = I915_READ(HTOTAL(cpu_transcoder));
8332 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8333 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8334 tmp = I915_READ(HBLANK(cpu_transcoder));
8335 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8336 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8337 tmp = I915_READ(HSYNC(cpu_transcoder));
8338 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8339 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8340
8341 tmp = I915_READ(VTOTAL(cpu_transcoder));
8342 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8343 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8344 tmp = I915_READ(VBLANK(cpu_transcoder));
8345 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8346 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8347 tmp = I915_READ(VSYNC(cpu_transcoder));
8348 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8349 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8350
8351 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8352 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8353 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8354 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8355 }
8356 }
8357
8358 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8359 struct intel_crtc_state *pipe_config)
8360 {
8361 struct drm_device *dev = crtc->base.dev;
8362 struct drm_i915_private *dev_priv = to_i915(dev);
8363 u32 tmp;
8364
8365 tmp = I915_READ(PIPESRC(crtc->pipe));
8366 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8367 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8368
8369 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8370 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8371 }
8372
8373 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8374 struct intel_crtc_state *pipe_config)
8375 {
8376 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8377 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8378 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8379 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8380
8381 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8382 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8383 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8384 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8385
8386 mode->flags = pipe_config->base.adjusted_mode.flags;
8387 mode->type = DRM_MODE_TYPE_DRIVER;
8388
8389 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8390 mode->flags |= pipe_config->base.adjusted_mode.flags;
8391
8392 mode->hsync = drm_mode_hsync(mode);
8393 mode->vrefresh = drm_mode_vrefresh(mode);
8394 drm_mode_set_name(mode);
8395 }
8396
8397 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8398 {
8399 struct drm_device *dev = intel_crtc->base.dev;
8400 struct drm_i915_private *dev_priv = to_i915(dev);
8401 uint32_t pipeconf;
8402
8403 pipeconf = 0;
8404
8405 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8406 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8407 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8408
8409 if (intel_crtc->config->double_wide)
8410 pipeconf |= PIPECONF_DOUBLE_WIDE;
8411
8412 /* only g4x and later have fancy bpc/dither controls */
8413 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8414 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8415 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8416 pipeconf |= PIPECONF_DITHER_EN |
8417 PIPECONF_DITHER_TYPE_SP;
8418
8419 switch (intel_crtc->config->pipe_bpp) {
8420 case 18:
8421 pipeconf |= PIPECONF_6BPC;
8422 break;
8423 case 24:
8424 pipeconf |= PIPECONF_8BPC;
8425 break;
8426 case 30:
8427 pipeconf |= PIPECONF_10BPC;
8428 break;
8429 default:
8430 /* Case prevented by intel_choose_pipe_bpp_dither. */
8431 BUG();
8432 }
8433 }
8434
8435 if (HAS_PIPE_CXSR(dev)) {
8436 if (intel_crtc->lowfreq_avail) {
8437 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8438 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8439 } else {
8440 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8441 }
8442 }
8443
8444 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8445 if (INTEL_INFO(dev)->gen < 4 ||
8446 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8447 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8448 else
8449 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8450 } else
8451 pipeconf |= PIPECONF_PROGRESSIVE;
8452
8453 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8454 intel_crtc->config->limited_color_range)
8455 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8456
8457 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8458 POSTING_READ(PIPECONF(intel_crtc->pipe));
8459 }
8460
8461 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8462 struct intel_crtc_state *crtc_state)
8463 {
8464 struct drm_device *dev = crtc->base.dev;
8465 struct drm_i915_private *dev_priv = to_i915(dev);
8466 const struct intel_limit *limit;
8467 int refclk = 48000;
8468
8469 memset(&crtc_state->dpll_hw_state, 0,
8470 sizeof(crtc_state->dpll_hw_state));
8471
8472 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8473 if (intel_panel_use_ssc(dev_priv)) {
8474 refclk = dev_priv->vbt.lvds_ssc_freq;
8475 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8476 }
8477
8478 limit = &intel_limits_i8xx_lvds;
8479 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8480 limit = &intel_limits_i8xx_dvo;
8481 } else {
8482 limit = &intel_limits_i8xx_dac;
8483 }
8484
8485 if (!crtc_state->clock_set &&
8486 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8487 refclk, NULL, &crtc_state->dpll)) {
8488 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8489 return -EINVAL;
8490 }
8491
8492 i8xx_compute_dpll(crtc, crtc_state, NULL);
8493
8494 return 0;
8495 }
8496
8497 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8498 struct intel_crtc_state *crtc_state)
8499 {
8500 struct drm_device *dev = crtc->base.dev;
8501 struct drm_i915_private *dev_priv = to_i915(dev);
8502 const struct intel_limit *limit;
8503 int refclk = 96000;
8504
8505 memset(&crtc_state->dpll_hw_state, 0,
8506 sizeof(crtc_state->dpll_hw_state));
8507
8508 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8509 if (intel_panel_use_ssc(dev_priv)) {
8510 refclk = dev_priv->vbt.lvds_ssc_freq;
8511 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8512 }
8513
8514 if (intel_is_dual_link_lvds(dev))
8515 limit = &intel_limits_g4x_dual_channel_lvds;
8516 else
8517 limit = &intel_limits_g4x_single_channel_lvds;
8518 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8519 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8520 limit = &intel_limits_g4x_hdmi;
8521 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8522 limit = &intel_limits_g4x_sdvo;
8523 } else {
8524 /* The option is for other outputs */
8525 limit = &intel_limits_i9xx_sdvo;
8526 }
8527
8528 if (!crtc_state->clock_set &&
8529 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8530 refclk, NULL, &crtc_state->dpll)) {
8531 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8532 return -EINVAL;
8533 }
8534
8535 i9xx_compute_dpll(crtc, crtc_state, NULL);
8536
8537 return 0;
8538 }
8539
8540 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8541 struct intel_crtc_state *crtc_state)
8542 {
8543 struct drm_device *dev = crtc->base.dev;
8544 struct drm_i915_private *dev_priv = to_i915(dev);
8545 const struct intel_limit *limit;
8546 int refclk = 96000;
8547
8548 memset(&crtc_state->dpll_hw_state, 0,
8549 sizeof(crtc_state->dpll_hw_state));
8550
8551 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8552 if (intel_panel_use_ssc(dev_priv)) {
8553 refclk = dev_priv->vbt.lvds_ssc_freq;
8554 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8555 }
8556
8557 limit = &intel_limits_pineview_lvds;
8558 } else {
8559 limit = &intel_limits_pineview_sdvo;
8560 }
8561
8562 if (!crtc_state->clock_set &&
8563 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8564 refclk, NULL, &crtc_state->dpll)) {
8565 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8566 return -EINVAL;
8567 }
8568
8569 i9xx_compute_dpll(crtc, crtc_state, NULL);
8570
8571 return 0;
8572 }
8573
8574 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8575 struct intel_crtc_state *crtc_state)
8576 {
8577 struct drm_device *dev = crtc->base.dev;
8578 struct drm_i915_private *dev_priv = to_i915(dev);
8579 const struct intel_limit *limit;
8580 int refclk = 96000;
8581
8582 memset(&crtc_state->dpll_hw_state, 0,
8583 sizeof(crtc_state->dpll_hw_state));
8584
8585 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8586 if (intel_panel_use_ssc(dev_priv)) {
8587 refclk = dev_priv->vbt.lvds_ssc_freq;
8588 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8589 }
8590
8591 limit = &intel_limits_i9xx_lvds;
8592 } else {
8593 limit = &intel_limits_i9xx_sdvo;
8594 }
8595
8596 if (!crtc_state->clock_set &&
8597 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8598 refclk, NULL, &crtc_state->dpll)) {
8599 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8600 return -EINVAL;
8601 }
8602
8603 i9xx_compute_dpll(crtc, crtc_state, NULL);
8604
8605 return 0;
8606 }
8607
8608 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8609 struct intel_crtc_state *crtc_state)
8610 {
8611 int refclk = 100000;
8612 const struct intel_limit *limit = &intel_limits_chv;
8613
8614 memset(&crtc_state->dpll_hw_state, 0,
8615 sizeof(crtc_state->dpll_hw_state));
8616
8617 if (!crtc_state->clock_set &&
8618 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8619 refclk, NULL, &crtc_state->dpll)) {
8620 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8621 return -EINVAL;
8622 }
8623
8624 chv_compute_dpll(crtc, crtc_state);
8625
8626 return 0;
8627 }
8628
8629 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8630 struct intel_crtc_state *crtc_state)
8631 {
8632 int refclk = 100000;
8633 const struct intel_limit *limit = &intel_limits_vlv;
8634
8635 memset(&crtc_state->dpll_hw_state, 0,
8636 sizeof(crtc_state->dpll_hw_state));
8637
8638 if (!crtc_state->clock_set &&
8639 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8640 refclk, NULL, &crtc_state->dpll)) {
8641 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8642 return -EINVAL;
8643 }
8644
8645 vlv_compute_dpll(crtc, crtc_state);
8646
8647 return 0;
8648 }
8649
8650 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8651 struct intel_crtc_state *pipe_config)
8652 {
8653 struct drm_device *dev = crtc->base.dev;
8654 struct drm_i915_private *dev_priv = to_i915(dev);
8655 uint32_t tmp;
8656
8657 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8658 return;
8659
8660 tmp = I915_READ(PFIT_CONTROL);
8661 if (!(tmp & PFIT_ENABLE))
8662 return;
8663
8664 /* Check whether the pfit is attached to our pipe. */
8665 if (INTEL_INFO(dev)->gen < 4) {
8666 if (crtc->pipe != PIPE_B)
8667 return;
8668 } else {
8669 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8670 return;
8671 }
8672
8673 pipe_config->gmch_pfit.control = tmp;
8674 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8675 }
8676
8677 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8678 struct intel_crtc_state *pipe_config)
8679 {
8680 struct drm_device *dev = crtc->base.dev;
8681 struct drm_i915_private *dev_priv = to_i915(dev);
8682 int pipe = pipe_config->cpu_transcoder;
8683 struct dpll clock;
8684 u32 mdiv;
8685 int refclk = 100000;
8686
8687 /* In case of DSI, DPLL will not be used */
8688 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8689 return;
8690
8691 mutex_lock(&dev_priv->sb_lock);
8692 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8693 mutex_unlock(&dev_priv->sb_lock);
8694
8695 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8696 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8697 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8698 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8699 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8700
8701 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8702 }
8703
8704 static void
8705 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8706 struct intel_initial_plane_config *plane_config)
8707 {
8708 struct drm_device *dev = crtc->base.dev;
8709 struct drm_i915_private *dev_priv = to_i915(dev);
8710 u32 val, base, offset;
8711 int pipe = crtc->pipe, plane = crtc->plane;
8712 int fourcc, pixel_format;
8713 unsigned int aligned_height;
8714 struct drm_framebuffer *fb;
8715 struct intel_framebuffer *intel_fb;
8716
8717 val = I915_READ(DSPCNTR(plane));
8718 if (!(val & DISPLAY_PLANE_ENABLE))
8719 return;
8720
8721 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8722 if (!intel_fb) {
8723 DRM_DEBUG_KMS("failed to alloc fb\n");
8724 return;
8725 }
8726
8727 fb = &intel_fb->base;
8728
8729 if (INTEL_INFO(dev)->gen >= 4) {
8730 if (val & DISPPLANE_TILED) {
8731 plane_config->tiling = I915_TILING_X;
8732 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8733 }
8734 }
8735
8736 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8737 fourcc = i9xx_format_to_fourcc(pixel_format);
8738 fb->pixel_format = fourcc;
8739 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8740
8741 if (INTEL_INFO(dev)->gen >= 4) {
8742 if (plane_config->tiling)
8743 offset = I915_READ(DSPTILEOFF(plane));
8744 else
8745 offset = I915_READ(DSPLINOFF(plane));
8746 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8747 } else {
8748 base = I915_READ(DSPADDR(plane));
8749 }
8750 plane_config->base = base;
8751
8752 val = I915_READ(PIPESRC(pipe));
8753 fb->width = ((val >> 16) & 0xfff) + 1;
8754 fb->height = ((val >> 0) & 0xfff) + 1;
8755
8756 val = I915_READ(DSPSTRIDE(pipe));
8757 fb->pitches[0] = val & 0xffffffc0;
8758
8759 aligned_height = intel_fb_align_height(dev, fb->height,
8760 fb->pixel_format,
8761 fb->modifier[0]);
8762
8763 plane_config->size = fb->pitches[0] * aligned_height;
8764
8765 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8766 pipe_name(pipe), plane, fb->width, fb->height,
8767 fb->bits_per_pixel, base, fb->pitches[0],
8768 plane_config->size);
8769
8770 plane_config->fb = intel_fb;
8771 }
8772
8773 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8774 struct intel_crtc_state *pipe_config)
8775 {
8776 struct drm_device *dev = crtc->base.dev;
8777 struct drm_i915_private *dev_priv = to_i915(dev);
8778 int pipe = pipe_config->cpu_transcoder;
8779 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8780 struct dpll clock;
8781 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8782 int refclk = 100000;
8783
8784 /* In case of DSI, DPLL will not be used */
8785 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8786 return;
8787
8788 mutex_lock(&dev_priv->sb_lock);
8789 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8790 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8791 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8792 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8793 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8794 mutex_unlock(&dev_priv->sb_lock);
8795
8796 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8797 clock.m2 = (pll_dw0 & 0xff) << 22;
8798 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8799 clock.m2 |= pll_dw2 & 0x3fffff;
8800 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8801 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8802 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8803
8804 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8805 }
8806
8807 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8808 struct intel_crtc_state *pipe_config)
8809 {
8810 struct drm_device *dev = crtc->base.dev;
8811 struct drm_i915_private *dev_priv = to_i915(dev);
8812 enum intel_display_power_domain power_domain;
8813 uint32_t tmp;
8814 bool ret;
8815
8816 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8817 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8818 return false;
8819
8820 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8821 pipe_config->shared_dpll = NULL;
8822
8823 ret = false;
8824
8825 tmp = I915_READ(PIPECONF(crtc->pipe));
8826 if (!(tmp & PIPECONF_ENABLE))
8827 goto out;
8828
8829 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8830 switch (tmp & PIPECONF_BPC_MASK) {
8831 case PIPECONF_6BPC:
8832 pipe_config->pipe_bpp = 18;
8833 break;
8834 case PIPECONF_8BPC:
8835 pipe_config->pipe_bpp = 24;
8836 break;
8837 case PIPECONF_10BPC:
8838 pipe_config->pipe_bpp = 30;
8839 break;
8840 default:
8841 break;
8842 }
8843 }
8844
8845 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8846 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8847 pipe_config->limited_color_range = true;
8848
8849 if (INTEL_INFO(dev)->gen < 4)
8850 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8851
8852 intel_get_pipe_timings(crtc, pipe_config);
8853 intel_get_pipe_src_size(crtc, pipe_config);
8854
8855 i9xx_get_pfit_config(crtc, pipe_config);
8856
8857 if (INTEL_INFO(dev)->gen >= 4) {
8858 /* No way to read it out on pipes B and C */
8859 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8860 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8861 else
8862 tmp = I915_READ(DPLL_MD(crtc->pipe));
8863 pipe_config->pixel_multiplier =
8864 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8865 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8866 pipe_config->dpll_hw_state.dpll_md = tmp;
8867 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8868 tmp = I915_READ(DPLL(crtc->pipe));
8869 pipe_config->pixel_multiplier =
8870 ((tmp & SDVO_MULTIPLIER_MASK)
8871 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8872 } else {
8873 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8874 * port and will be fixed up in the encoder->get_config
8875 * function. */
8876 pipe_config->pixel_multiplier = 1;
8877 }
8878 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8879 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8880 /*
8881 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8882 * on 830. Filter it out here so that we don't
8883 * report errors due to that.
8884 */
8885 if (IS_I830(dev))
8886 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8887
8888 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8889 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8890 } else {
8891 /* Mask out read-only status bits. */
8892 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8893 DPLL_PORTC_READY_MASK |
8894 DPLL_PORTB_READY_MASK);
8895 }
8896
8897 if (IS_CHERRYVIEW(dev))
8898 chv_crtc_clock_get(crtc, pipe_config);
8899 else if (IS_VALLEYVIEW(dev))
8900 vlv_crtc_clock_get(crtc, pipe_config);
8901 else
8902 i9xx_crtc_clock_get(crtc, pipe_config);
8903
8904 /*
8905 * Normally the dotclock is filled in by the encoder .get_config()
8906 * but in case the pipe is enabled w/o any ports we need a sane
8907 * default.
8908 */
8909 pipe_config->base.adjusted_mode.crtc_clock =
8910 pipe_config->port_clock / pipe_config->pixel_multiplier;
8911
8912 ret = true;
8913
8914 out:
8915 intel_display_power_put(dev_priv, power_domain);
8916
8917 return ret;
8918 }
8919
8920 static void ironlake_init_pch_refclk(struct drm_device *dev)
8921 {
8922 struct drm_i915_private *dev_priv = to_i915(dev);
8923 struct intel_encoder *encoder;
8924 int i;
8925 u32 val, final;
8926 bool has_lvds = false;
8927 bool has_cpu_edp = false;
8928 bool has_panel = false;
8929 bool has_ck505 = false;
8930 bool can_ssc = false;
8931 bool using_ssc_source = false;
8932
8933 /* We need to take the global config into account */
8934 for_each_intel_encoder(dev, encoder) {
8935 switch (encoder->type) {
8936 case INTEL_OUTPUT_LVDS:
8937 has_panel = true;
8938 has_lvds = true;
8939 break;
8940 case INTEL_OUTPUT_EDP:
8941 has_panel = true;
8942 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8943 has_cpu_edp = true;
8944 break;
8945 default:
8946 break;
8947 }
8948 }
8949
8950 if (HAS_PCH_IBX(dev)) {
8951 has_ck505 = dev_priv->vbt.display_clock_mode;
8952 can_ssc = has_ck505;
8953 } else {
8954 has_ck505 = false;
8955 can_ssc = true;
8956 }
8957
8958 /* Check if any DPLLs are using the SSC source */
8959 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8960 u32 temp = I915_READ(PCH_DPLL(i));
8961
8962 if (!(temp & DPLL_VCO_ENABLE))
8963 continue;
8964
8965 if ((temp & PLL_REF_INPUT_MASK) ==
8966 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8967 using_ssc_source = true;
8968 break;
8969 }
8970 }
8971
8972 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8973 has_panel, has_lvds, has_ck505, using_ssc_source);
8974
8975 /* Ironlake: try to setup display ref clock before DPLL
8976 * enabling. This is only under driver's control after
8977 * PCH B stepping, previous chipset stepping should be
8978 * ignoring this setting.
8979 */
8980 val = I915_READ(PCH_DREF_CONTROL);
8981
8982 /* As we must carefully and slowly disable/enable each source in turn,
8983 * compute the final state we want first and check if we need to
8984 * make any changes at all.
8985 */
8986 final = val;
8987 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8988 if (has_ck505)
8989 final |= DREF_NONSPREAD_CK505_ENABLE;
8990 else
8991 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8992
8993 final &= ~DREF_SSC_SOURCE_MASK;
8994 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8995 final &= ~DREF_SSC1_ENABLE;
8996
8997 if (has_panel) {
8998 final |= DREF_SSC_SOURCE_ENABLE;
8999
9000 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9001 final |= DREF_SSC1_ENABLE;
9002
9003 if (has_cpu_edp) {
9004 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9005 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9006 else
9007 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9008 } else
9009 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9010 } else if (using_ssc_source) {
9011 final |= DREF_SSC_SOURCE_ENABLE;
9012 final |= DREF_SSC1_ENABLE;
9013 }
9014
9015 if (final == val)
9016 return;
9017
9018 /* Always enable nonspread source */
9019 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9020
9021 if (has_ck505)
9022 val |= DREF_NONSPREAD_CK505_ENABLE;
9023 else
9024 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9025
9026 if (has_panel) {
9027 val &= ~DREF_SSC_SOURCE_MASK;
9028 val |= DREF_SSC_SOURCE_ENABLE;
9029
9030 /* SSC must be turned on before enabling the CPU output */
9031 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9032 DRM_DEBUG_KMS("Using SSC on panel\n");
9033 val |= DREF_SSC1_ENABLE;
9034 } else
9035 val &= ~DREF_SSC1_ENABLE;
9036
9037 /* Get SSC going before enabling the outputs */
9038 I915_WRITE(PCH_DREF_CONTROL, val);
9039 POSTING_READ(PCH_DREF_CONTROL);
9040 udelay(200);
9041
9042 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9043
9044 /* Enable CPU source on CPU attached eDP */
9045 if (has_cpu_edp) {
9046 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9047 DRM_DEBUG_KMS("Using SSC on eDP\n");
9048 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9049 } else
9050 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9051 } else
9052 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9053
9054 I915_WRITE(PCH_DREF_CONTROL, val);
9055 POSTING_READ(PCH_DREF_CONTROL);
9056 udelay(200);
9057 } else {
9058 DRM_DEBUG_KMS("Disabling CPU source output\n");
9059
9060 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9061
9062 /* Turn off CPU output */
9063 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9064
9065 I915_WRITE(PCH_DREF_CONTROL, val);
9066 POSTING_READ(PCH_DREF_CONTROL);
9067 udelay(200);
9068
9069 if (!using_ssc_source) {
9070 DRM_DEBUG_KMS("Disabling SSC source\n");
9071
9072 /* Turn off the SSC source */
9073 val &= ~DREF_SSC_SOURCE_MASK;
9074 val |= DREF_SSC_SOURCE_DISABLE;
9075
9076 /* Turn off SSC1 */
9077 val &= ~DREF_SSC1_ENABLE;
9078
9079 I915_WRITE(PCH_DREF_CONTROL, val);
9080 POSTING_READ(PCH_DREF_CONTROL);
9081 udelay(200);
9082 }
9083 }
9084
9085 BUG_ON(val != final);
9086 }
9087
9088 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9089 {
9090 uint32_t tmp;
9091
9092 tmp = I915_READ(SOUTH_CHICKEN2);
9093 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9094 I915_WRITE(SOUTH_CHICKEN2, tmp);
9095
9096 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9097 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9098 DRM_ERROR("FDI mPHY reset assert timeout\n");
9099
9100 tmp = I915_READ(SOUTH_CHICKEN2);
9101 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9102 I915_WRITE(SOUTH_CHICKEN2, tmp);
9103
9104 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9105 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9106 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9107 }
9108
9109 /* WaMPhyProgramming:hsw */
9110 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9111 {
9112 uint32_t tmp;
9113
9114 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9115 tmp &= ~(0xFF << 24);
9116 tmp |= (0x12 << 24);
9117 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9118
9119 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9120 tmp |= (1 << 11);
9121 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9122
9123 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9124 tmp |= (1 << 11);
9125 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9126
9127 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9128 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9129 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9130
9131 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9132 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9133 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9134
9135 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9136 tmp &= ~(7 << 13);
9137 tmp |= (5 << 13);
9138 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9139
9140 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9141 tmp &= ~(7 << 13);
9142 tmp |= (5 << 13);
9143 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9144
9145 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9146 tmp &= ~0xFF;
9147 tmp |= 0x1C;
9148 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9149
9150 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9151 tmp &= ~0xFF;
9152 tmp |= 0x1C;
9153 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9154
9155 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9156 tmp &= ~(0xFF << 16);
9157 tmp |= (0x1C << 16);
9158 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9159
9160 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9161 tmp &= ~(0xFF << 16);
9162 tmp |= (0x1C << 16);
9163 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9164
9165 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9166 tmp |= (1 << 27);
9167 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9168
9169 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9170 tmp |= (1 << 27);
9171 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9172
9173 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9174 tmp &= ~(0xF << 28);
9175 tmp |= (4 << 28);
9176 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9177
9178 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9179 tmp &= ~(0xF << 28);
9180 tmp |= (4 << 28);
9181 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9182 }
9183
9184 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9185 * Programming" based on the parameters passed:
9186 * - Sequence to enable CLKOUT_DP
9187 * - Sequence to enable CLKOUT_DP without spread
9188 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9189 */
9190 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9191 bool with_fdi)
9192 {
9193 struct drm_i915_private *dev_priv = to_i915(dev);
9194 uint32_t reg, tmp;
9195
9196 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9197 with_spread = true;
9198 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9199 with_fdi = false;
9200
9201 mutex_lock(&dev_priv->sb_lock);
9202
9203 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9204 tmp &= ~SBI_SSCCTL_DISABLE;
9205 tmp |= SBI_SSCCTL_PATHALT;
9206 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9207
9208 udelay(24);
9209
9210 if (with_spread) {
9211 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9212 tmp &= ~SBI_SSCCTL_PATHALT;
9213 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9214
9215 if (with_fdi) {
9216 lpt_reset_fdi_mphy(dev_priv);
9217 lpt_program_fdi_mphy(dev_priv);
9218 }
9219 }
9220
9221 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9222 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9223 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9224 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9225
9226 mutex_unlock(&dev_priv->sb_lock);
9227 }
9228
9229 /* Sequence to disable CLKOUT_DP */
9230 static void lpt_disable_clkout_dp(struct drm_device *dev)
9231 {
9232 struct drm_i915_private *dev_priv = to_i915(dev);
9233 uint32_t reg, tmp;
9234
9235 mutex_lock(&dev_priv->sb_lock);
9236
9237 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9238 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9239 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9240 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9241
9242 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9243 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9244 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9245 tmp |= SBI_SSCCTL_PATHALT;
9246 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9247 udelay(32);
9248 }
9249 tmp |= SBI_SSCCTL_DISABLE;
9250 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9251 }
9252
9253 mutex_unlock(&dev_priv->sb_lock);
9254 }
9255
9256 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9257
9258 static const uint16_t sscdivintphase[] = {
9259 [BEND_IDX( 50)] = 0x3B23,
9260 [BEND_IDX( 45)] = 0x3B23,
9261 [BEND_IDX( 40)] = 0x3C23,
9262 [BEND_IDX( 35)] = 0x3C23,
9263 [BEND_IDX( 30)] = 0x3D23,
9264 [BEND_IDX( 25)] = 0x3D23,
9265 [BEND_IDX( 20)] = 0x3E23,
9266 [BEND_IDX( 15)] = 0x3E23,
9267 [BEND_IDX( 10)] = 0x3F23,
9268 [BEND_IDX( 5)] = 0x3F23,
9269 [BEND_IDX( 0)] = 0x0025,
9270 [BEND_IDX( -5)] = 0x0025,
9271 [BEND_IDX(-10)] = 0x0125,
9272 [BEND_IDX(-15)] = 0x0125,
9273 [BEND_IDX(-20)] = 0x0225,
9274 [BEND_IDX(-25)] = 0x0225,
9275 [BEND_IDX(-30)] = 0x0325,
9276 [BEND_IDX(-35)] = 0x0325,
9277 [BEND_IDX(-40)] = 0x0425,
9278 [BEND_IDX(-45)] = 0x0425,
9279 [BEND_IDX(-50)] = 0x0525,
9280 };
9281
9282 /*
9283 * Bend CLKOUT_DP
9284 * steps -50 to 50 inclusive, in steps of 5
9285 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9286 * change in clock period = -(steps / 10) * 5.787 ps
9287 */
9288 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9289 {
9290 uint32_t tmp;
9291 int idx = BEND_IDX(steps);
9292
9293 if (WARN_ON(steps % 5 != 0))
9294 return;
9295
9296 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9297 return;
9298
9299 mutex_lock(&dev_priv->sb_lock);
9300
9301 if (steps % 10 != 0)
9302 tmp = 0xAAAAAAAB;
9303 else
9304 tmp = 0x00000000;
9305 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9306
9307 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9308 tmp &= 0xffff0000;
9309 tmp |= sscdivintphase[idx];
9310 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9311
9312 mutex_unlock(&dev_priv->sb_lock);
9313 }
9314
9315 #undef BEND_IDX
9316
9317 static void lpt_init_pch_refclk(struct drm_device *dev)
9318 {
9319 struct intel_encoder *encoder;
9320 bool has_vga = false;
9321
9322 for_each_intel_encoder(dev, encoder) {
9323 switch (encoder->type) {
9324 case INTEL_OUTPUT_ANALOG:
9325 has_vga = true;
9326 break;
9327 default:
9328 break;
9329 }
9330 }
9331
9332 if (has_vga) {
9333 lpt_bend_clkout_dp(to_i915(dev), 0);
9334 lpt_enable_clkout_dp(dev, true, true);
9335 } else {
9336 lpt_disable_clkout_dp(dev);
9337 }
9338 }
9339
9340 /*
9341 * Initialize reference clocks when the driver loads
9342 */
9343 void intel_init_pch_refclk(struct drm_device *dev)
9344 {
9345 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9346 ironlake_init_pch_refclk(dev);
9347 else if (HAS_PCH_LPT(dev))
9348 lpt_init_pch_refclk(dev);
9349 }
9350
9351 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9352 {
9353 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9355 int pipe = intel_crtc->pipe;
9356 uint32_t val;
9357
9358 val = 0;
9359
9360 switch (intel_crtc->config->pipe_bpp) {
9361 case 18:
9362 val |= PIPECONF_6BPC;
9363 break;
9364 case 24:
9365 val |= PIPECONF_8BPC;
9366 break;
9367 case 30:
9368 val |= PIPECONF_10BPC;
9369 break;
9370 case 36:
9371 val |= PIPECONF_12BPC;
9372 break;
9373 default:
9374 /* Case prevented by intel_choose_pipe_bpp_dither. */
9375 BUG();
9376 }
9377
9378 if (intel_crtc->config->dither)
9379 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9380
9381 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9382 val |= PIPECONF_INTERLACED_ILK;
9383 else
9384 val |= PIPECONF_PROGRESSIVE;
9385
9386 if (intel_crtc->config->limited_color_range)
9387 val |= PIPECONF_COLOR_RANGE_SELECT;
9388
9389 I915_WRITE(PIPECONF(pipe), val);
9390 POSTING_READ(PIPECONF(pipe));
9391 }
9392
9393 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9394 {
9395 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9397 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9398 u32 val = 0;
9399
9400 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9401 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9402
9403 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9404 val |= PIPECONF_INTERLACED_ILK;
9405 else
9406 val |= PIPECONF_PROGRESSIVE;
9407
9408 I915_WRITE(PIPECONF(cpu_transcoder), val);
9409 POSTING_READ(PIPECONF(cpu_transcoder));
9410 }
9411
9412 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9413 {
9414 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9416
9417 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9418 u32 val = 0;
9419
9420 switch (intel_crtc->config->pipe_bpp) {
9421 case 18:
9422 val |= PIPEMISC_DITHER_6_BPC;
9423 break;
9424 case 24:
9425 val |= PIPEMISC_DITHER_8_BPC;
9426 break;
9427 case 30:
9428 val |= PIPEMISC_DITHER_10_BPC;
9429 break;
9430 case 36:
9431 val |= PIPEMISC_DITHER_12_BPC;
9432 break;
9433 default:
9434 /* Case prevented by pipe_config_set_bpp. */
9435 BUG();
9436 }
9437
9438 if (intel_crtc->config->dither)
9439 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9440
9441 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9442 }
9443 }
9444
9445 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9446 {
9447 /*
9448 * Account for spread spectrum to avoid
9449 * oversubscribing the link. Max center spread
9450 * is 2.5%; use 5% for safety's sake.
9451 */
9452 u32 bps = target_clock * bpp * 21 / 20;
9453 return DIV_ROUND_UP(bps, link_bw * 8);
9454 }
9455
9456 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9457 {
9458 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9459 }
9460
9461 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9462 struct intel_crtc_state *crtc_state,
9463 struct dpll *reduced_clock)
9464 {
9465 struct drm_crtc *crtc = &intel_crtc->base;
9466 struct drm_device *dev = crtc->dev;
9467 struct drm_i915_private *dev_priv = to_i915(dev);
9468 u32 dpll, fp, fp2;
9469 int factor;
9470
9471 /* Enable autotuning of the PLL clock (if permissible) */
9472 factor = 21;
9473 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9474 if ((intel_panel_use_ssc(dev_priv) &&
9475 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9476 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9477 factor = 25;
9478 } else if (crtc_state->sdvo_tv_clock)
9479 factor = 20;
9480
9481 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9482
9483 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9484 fp |= FP_CB_TUNE;
9485
9486 if (reduced_clock) {
9487 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9488
9489 if (reduced_clock->m < factor * reduced_clock->n)
9490 fp2 |= FP_CB_TUNE;
9491 } else {
9492 fp2 = fp;
9493 }
9494
9495 dpll = 0;
9496
9497 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9498 dpll |= DPLLB_MODE_LVDS;
9499 else
9500 dpll |= DPLLB_MODE_DAC_SERIAL;
9501
9502 dpll |= (crtc_state->pixel_multiplier - 1)
9503 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9504
9505 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9506 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9507 dpll |= DPLL_SDVO_HIGH_SPEED;
9508
9509 if (intel_crtc_has_dp_encoder(crtc_state))
9510 dpll |= DPLL_SDVO_HIGH_SPEED;
9511
9512 /* compute bitmask from p1 value */
9513 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9514 /* also FPA1 */
9515 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9516
9517 switch (crtc_state->dpll.p2) {
9518 case 5:
9519 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9520 break;
9521 case 7:
9522 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9523 break;
9524 case 10:
9525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9526 break;
9527 case 14:
9528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9529 break;
9530 }
9531
9532 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9533 intel_panel_use_ssc(dev_priv))
9534 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9535 else
9536 dpll |= PLL_REF_INPUT_DREFCLK;
9537
9538 dpll |= DPLL_VCO_ENABLE;
9539
9540 crtc_state->dpll_hw_state.dpll = dpll;
9541 crtc_state->dpll_hw_state.fp0 = fp;
9542 crtc_state->dpll_hw_state.fp1 = fp2;
9543 }
9544
9545 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9546 struct intel_crtc_state *crtc_state)
9547 {
9548 struct drm_device *dev = crtc->base.dev;
9549 struct drm_i915_private *dev_priv = to_i915(dev);
9550 struct dpll reduced_clock;
9551 bool has_reduced_clock = false;
9552 struct intel_shared_dpll *pll;
9553 const struct intel_limit *limit;
9554 int refclk = 120000;
9555
9556 memset(&crtc_state->dpll_hw_state, 0,
9557 sizeof(crtc_state->dpll_hw_state));
9558
9559 crtc->lowfreq_avail = false;
9560
9561 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9562 if (!crtc_state->has_pch_encoder)
9563 return 0;
9564
9565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9566 if (intel_panel_use_ssc(dev_priv)) {
9567 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9568 dev_priv->vbt.lvds_ssc_freq);
9569 refclk = dev_priv->vbt.lvds_ssc_freq;
9570 }
9571
9572 if (intel_is_dual_link_lvds(dev)) {
9573 if (refclk == 100000)
9574 limit = &intel_limits_ironlake_dual_lvds_100m;
9575 else
9576 limit = &intel_limits_ironlake_dual_lvds;
9577 } else {
9578 if (refclk == 100000)
9579 limit = &intel_limits_ironlake_single_lvds_100m;
9580 else
9581 limit = &intel_limits_ironlake_single_lvds;
9582 }
9583 } else {
9584 limit = &intel_limits_ironlake_dac;
9585 }
9586
9587 if (!crtc_state->clock_set &&
9588 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9589 refclk, NULL, &crtc_state->dpll)) {
9590 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9591 return -EINVAL;
9592 }
9593
9594 ironlake_compute_dpll(crtc, crtc_state,
9595 has_reduced_clock ? &reduced_clock : NULL);
9596
9597 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9598 if (pll == NULL) {
9599 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9600 pipe_name(crtc->pipe));
9601 return -EINVAL;
9602 }
9603
9604 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9605 has_reduced_clock)
9606 crtc->lowfreq_avail = true;
9607
9608 return 0;
9609 }
9610
9611 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9612 struct intel_link_m_n *m_n)
9613 {
9614 struct drm_device *dev = crtc->base.dev;
9615 struct drm_i915_private *dev_priv = to_i915(dev);
9616 enum pipe pipe = crtc->pipe;
9617
9618 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9619 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9620 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9621 & ~TU_SIZE_MASK;
9622 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9623 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9624 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9625 }
9626
9627 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9628 enum transcoder transcoder,
9629 struct intel_link_m_n *m_n,
9630 struct intel_link_m_n *m2_n2)
9631 {
9632 struct drm_device *dev = crtc->base.dev;
9633 struct drm_i915_private *dev_priv = to_i915(dev);
9634 enum pipe pipe = crtc->pipe;
9635
9636 if (INTEL_INFO(dev)->gen >= 5) {
9637 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9638 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9639 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9640 & ~TU_SIZE_MASK;
9641 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9642 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9643 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9644 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9645 * gen < 8) and if DRRS is supported (to make sure the
9646 * registers are not unnecessarily read).
9647 */
9648 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9649 crtc->config->has_drrs) {
9650 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9651 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9652 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9653 & ~TU_SIZE_MASK;
9654 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9655 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9656 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9657 }
9658 } else {
9659 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9660 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9661 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9662 & ~TU_SIZE_MASK;
9663 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9664 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9665 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9666 }
9667 }
9668
9669 void intel_dp_get_m_n(struct intel_crtc *crtc,
9670 struct intel_crtc_state *pipe_config)
9671 {
9672 if (pipe_config->has_pch_encoder)
9673 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9674 else
9675 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9676 &pipe_config->dp_m_n,
9677 &pipe_config->dp_m2_n2);
9678 }
9679
9680 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9681 struct intel_crtc_state *pipe_config)
9682 {
9683 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9684 &pipe_config->fdi_m_n, NULL);
9685 }
9686
9687 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9688 struct intel_crtc_state *pipe_config)
9689 {
9690 struct drm_device *dev = crtc->base.dev;
9691 struct drm_i915_private *dev_priv = to_i915(dev);
9692 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9693 uint32_t ps_ctrl = 0;
9694 int id = -1;
9695 int i;
9696
9697 /* find scaler attached to this pipe */
9698 for (i = 0; i < crtc->num_scalers; i++) {
9699 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9700 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9701 id = i;
9702 pipe_config->pch_pfit.enabled = true;
9703 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9704 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9705 break;
9706 }
9707 }
9708
9709 scaler_state->scaler_id = id;
9710 if (id >= 0) {
9711 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9712 } else {
9713 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9714 }
9715 }
9716
9717 static void
9718 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9719 struct intel_initial_plane_config *plane_config)
9720 {
9721 struct drm_device *dev = crtc->base.dev;
9722 struct drm_i915_private *dev_priv = to_i915(dev);
9723 u32 val, base, offset, stride_mult, tiling;
9724 int pipe = crtc->pipe;
9725 int fourcc, pixel_format;
9726 unsigned int aligned_height;
9727 struct drm_framebuffer *fb;
9728 struct intel_framebuffer *intel_fb;
9729
9730 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9731 if (!intel_fb) {
9732 DRM_DEBUG_KMS("failed to alloc fb\n");
9733 return;
9734 }
9735
9736 fb = &intel_fb->base;
9737
9738 val = I915_READ(PLANE_CTL(pipe, 0));
9739 if (!(val & PLANE_CTL_ENABLE))
9740 goto error;
9741
9742 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9743 fourcc = skl_format_to_fourcc(pixel_format,
9744 val & PLANE_CTL_ORDER_RGBX,
9745 val & PLANE_CTL_ALPHA_MASK);
9746 fb->pixel_format = fourcc;
9747 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9748
9749 tiling = val & PLANE_CTL_TILED_MASK;
9750 switch (tiling) {
9751 case PLANE_CTL_TILED_LINEAR:
9752 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9753 break;
9754 case PLANE_CTL_TILED_X:
9755 plane_config->tiling = I915_TILING_X;
9756 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9757 break;
9758 case PLANE_CTL_TILED_Y:
9759 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9760 break;
9761 case PLANE_CTL_TILED_YF:
9762 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9763 break;
9764 default:
9765 MISSING_CASE(tiling);
9766 goto error;
9767 }
9768
9769 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9770 plane_config->base = base;
9771
9772 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9773
9774 val = I915_READ(PLANE_SIZE(pipe, 0));
9775 fb->height = ((val >> 16) & 0xfff) + 1;
9776 fb->width = ((val >> 0) & 0x1fff) + 1;
9777
9778 val = I915_READ(PLANE_STRIDE(pipe, 0));
9779 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9780 fb->pixel_format);
9781 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9782
9783 aligned_height = intel_fb_align_height(dev, fb->height,
9784 fb->pixel_format,
9785 fb->modifier[0]);
9786
9787 plane_config->size = fb->pitches[0] * aligned_height;
9788
9789 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9790 pipe_name(pipe), fb->width, fb->height,
9791 fb->bits_per_pixel, base, fb->pitches[0],
9792 plane_config->size);
9793
9794 plane_config->fb = intel_fb;
9795 return;
9796
9797 error:
9798 kfree(intel_fb);
9799 }
9800
9801 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9802 struct intel_crtc_state *pipe_config)
9803 {
9804 struct drm_device *dev = crtc->base.dev;
9805 struct drm_i915_private *dev_priv = to_i915(dev);
9806 uint32_t tmp;
9807
9808 tmp = I915_READ(PF_CTL(crtc->pipe));
9809
9810 if (tmp & PF_ENABLE) {
9811 pipe_config->pch_pfit.enabled = true;
9812 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9813 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9814
9815 /* We currently do not free assignements of panel fitters on
9816 * ivb/hsw (since we don't use the higher upscaling modes which
9817 * differentiates them) so just WARN about this case for now. */
9818 if (IS_GEN7(dev)) {
9819 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9820 PF_PIPE_SEL_IVB(crtc->pipe));
9821 }
9822 }
9823 }
9824
9825 static void
9826 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9827 struct intel_initial_plane_config *plane_config)
9828 {
9829 struct drm_device *dev = crtc->base.dev;
9830 struct drm_i915_private *dev_priv = to_i915(dev);
9831 u32 val, base, offset;
9832 int pipe = crtc->pipe;
9833 int fourcc, pixel_format;
9834 unsigned int aligned_height;
9835 struct drm_framebuffer *fb;
9836 struct intel_framebuffer *intel_fb;
9837
9838 val = I915_READ(DSPCNTR(pipe));
9839 if (!(val & DISPLAY_PLANE_ENABLE))
9840 return;
9841
9842 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9843 if (!intel_fb) {
9844 DRM_DEBUG_KMS("failed to alloc fb\n");
9845 return;
9846 }
9847
9848 fb = &intel_fb->base;
9849
9850 if (INTEL_INFO(dev)->gen >= 4) {
9851 if (val & DISPPLANE_TILED) {
9852 plane_config->tiling = I915_TILING_X;
9853 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9854 }
9855 }
9856
9857 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9858 fourcc = i9xx_format_to_fourcc(pixel_format);
9859 fb->pixel_format = fourcc;
9860 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9861
9862 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9863 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9864 offset = I915_READ(DSPOFFSET(pipe));
9865 } else {
9866 if (plane_config->tiling)
9867 offset = I915_READ(DSPTILEOFF(pipe));
9868 else
9869 offset = I915_READ(DSPLINOFF(pipe));
9870 }
9871 plane_config->base = base;
9872
9873 val = I915_READ(PIPESRC(pipe));
9874 fb->width = ((val >> 16) & 0xfff) + 1;
9875 fb->height = ((val >> 0) & 0xfff) + 1;
9876
9877 val = I915_READ(DSPSTRIDE(pipe));
9878 fb->pitches[0] = val & 0xffffffc0;
9879
9880 aligned_height = intel_fb_align_height(dev, fb->height,
9881 fb->pixel_format,
9882 fb->modifier[0]);
9883
9884 plane_config->size = fb->pitches[0] * aligned_height;
9885
9886 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9887 pipe_name(pipe), fb->width, fb->height,
9888 fb->bits_per_pixel, base, fb->pitches[0],
9889 plane_config->size);
9890
9891 plane_config->fb = intel_fb;
9892 }
9893
9894 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9895 struct intel_crtc_state *pipe_config)
9896 {
9897 struct drm_device *dev = crtc->base.dev;
9898 struct drm_i915_private *dev_priv = to_i915(dev);
9899 enum intel_display_power_domain power_domain;
9900 uint32_t tmp;
9901 bool ret;
9902
9903 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9905 return false;
9906
9907 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9908 pipe_config->shared_dpll = NULL;
9909
9910 ret = false;
9911 tmp = I915_READ(PIPECONF(crtc->pipe));
9912 if (!(tmp & PIPECONF_ENABLE))
9913 goto out;
9914
9915 switch (tmp & PIPECONF_BPC_MASK) {
9916 case PIPECONF_6BPC:
9917 pipe_config->pipe_bpp = 18;
9918 break;
9919 case PIPECONF_8BPC:
9920 pipe_config->pipe_bpp = 24;
9921 break;
9922 case PIPECONF_10BPC:
9923 pipe_config->pipe_bpp = 30;
9924 break;
9925 case PIPECONF_12BPC:
9926 pipe_config->pipe_bpp = 36;
9927 break;
9928 default:
9929 break;
9930 }
9931
9932 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9933 pipe_config->limited_color_range = true;
9934
9935 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9936 struct intel_shared_dpll *pll;
9937 enum intel_dpll_id pll_id;
9938
9939 pipe_config->has_pch_encoder = true;
9940
9941 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9942 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9943 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9944
9945 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9946
9947 if (HAS_PCH_IBX(dev_priv)) {
9948 /*
9949 * The pipe->pch transcoder and pch transcoder->pll
9950 * mapping is fixed.
9951 */
9952 pll_id = (enum intel_dpll_id) crtc->pipe;
9953 } else {
9954 tmp = I915_READ(PCH_DPLL_SEL);
9955 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9956 pll_id = DPLL_ID_PCH_PLL_B;
9957 else
9958 pll_id= DPLL_ID_PCH_PLL_A;
9959 }
9960
9961 pipe_config->shared_dpll =
9962 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9963 pll = pipe_config->shared_dpll;
9964
9965 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9966 &pipe_config->dpll_hw_state));
9967
9968 tmp = pipe_config->dpll_hw_state.dpll;
9969 pipe_config->pixel_multiplier =
9970 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9971 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9972
9973 ironlake_pch_clock_get(crtc, pipe_config);
9974 } else {
9975 pipe_config->pixel_multiplier = 1;
9976 }
9977
9978 intel_get_pipe_timings(crtc, pipe_config);
9979 intel_get_pipe_src_size(crtc, pipe_config);
9980
9981 ironlake_get_pfit_config(crtc, pipe_config);
9982
9983 ret = true;
9984
9985 out:
9986 intel_display_power_put(dev_priv, power_domain);
9987
9988 return ret;
9989 }
9990
9991 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9992 {
9993 struct drm_device *dev = &dev_priv->drm;
9994 struct intel_crtc *crtc;
9995
9996 for_each_intel_crtc(dev, crtc)
9997 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9998 pipe_name(crtc->pipe));
9999
10000 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10001 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10002 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10003 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10004 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10005 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10006 "CPU PWM1 enabled\n");
10007 if (IS_HASWELL(dev))
10008 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10009 "CPU PWM2 enabled\n");
10010 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10011 "PCH PWM1 enabled\n");
10012 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10013 "Utility pin enabled\n");
10014 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10015
10016 /*
10017 * In theory we can still leave IRQs enabled, as long as only the HPD
10018 * interrupts remain enabled. We used to check for that, but since it's
10019 * gen-specific and since we only disable LCPLL after we fully disable
10020 * the interrupts, the check below should be enough.
10021 */
10022 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10023 }
10024
10025 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10026 {
10027 struct drm_device *dev = &dev_priv->drm;
10028
10029 if (IS_HASWELL(dev))
10030 return I915_READ(D_COMP_HSW);
10031 else
10032 return I915_READ(D_COMP_BDW);
10033 }
10034
10035 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10036 {
10037 struct drm_device *dev = &dev_priv->drm;
10038
10039 if (IS_HASWELL(dev)) {
10040 mutex_lock(&dev_priv->rps.hw_lock);
10041 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10042 val))
10043 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10044 mutex_unlock(&dev_priv->rps.hw_lock);
10045 } else {
10046 I915_WRITE(D_COMP_BDW, val);
10047 POSTING_READ(D_COMP_BDW);
10048 }
10049 }
10050
10051 /*
10052 * This function implements pieces of two sequences from BSpec:
10053 * - Sequence for display software to disable LCPLL
10054 * - Sequence for display software to allow package C8+
10055 * The steps implemented here are just the steps that actually touch the LCPLL
10056 * register. Callers should take care of disabling all the display engine
10057 * functions, doing the mode unset, fixing interrupts, etc.
10058 */
10059 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10060 bool switch_to_fclk, bool allow_power_down)
10061 {
10062 uint32_t val;
10063
10064 assert_can_disable_lcpll(dev_priv);
10065
10066 val = I915_READ(LCPLL_CTL);
10067
10068 if (switch_to_fclk) {
10069 val |= LCPLL_CD_SOURCE_FCLK;
10070 I915_WRITE(LCPLL_CTL, val);
10071
10072 if (wait_for_us(I915_READ(LCPLL_CTL) &
10073 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10074 DRM_ERROR("Switching to FCLK failed\n");
10075
10076 val = I915_READ(LCPLL_CTL);
10077 }
10078
10079 val |= LCPLL_PLL_DISABLE;
10080 I915_WRITE(LCPLL_CTL, val);
10081 POSTING_READ(LCPLL_CTL);
10082
10083 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10084 DRM_ERROR("LCPLL still locked\n");
10085
10086 val = hsw_read_dcomp(dev_priv);
10087 val |= D_COMP_COMP_DISABLE;
10088 hsw_write_dcomp(dev_priv, val);
10089 ndelay(100);
10090
10091 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10092 1))
10093 DRM_ERROR("D_COMP RCOMP still in progress\n");
10094
10095 if (allow_power_down) {
10096 val = I915_READ(LCPLL_CTL);
10097 val |= LCPLL_POWER_DOWN_ALLOW;
10098 I915_WRITE(LCPLL_CTL, val);
10099 POSTING_READ(LCPLL_CTL);
10100 }
10101 }
10102
10103 /*
10104 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10105 * source.
10106 */
10107 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10108 {
10109 uint32_t val;
10110
10111 val = I915_READ(LCPLL_CTL);
10112
10113 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10114 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10115 return;
10116
10117 /*
10118 * Make sure we're not on PC8 state before disabling PC8, otherwise
10119 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10120 */
10121 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10122
10123 if (val & LCPLL_POWER_DOWN_ALLOW) {
10124 val &= ~LCPLL_POWER_DOWN_ALLOW;
10125 I915_WRITE(LCPLL_CTL, val);
10126 POSTING_READ(LCPLL_CTL);
10127 }
10128
10129 val = hsw_read_dcomp(dev_priv);
10130 val |= D_COMP_COMP_FORCE;
10131 val &= ~D_COMP_COMP_DISABLE;
10132 hsw_write_dcomp(dev_priv, val);
10133
10134 val = I915_READ(LCPLL_CTL);
10135 val &= ~LCPLL_PLL_DISABLE;
10136 I915_WRITE(LCPLL_CTL, val);
10137
10138 if (intel_wait_for_register(dev_priv,
10139 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10140 5))
10141 DRM_ERROR("LCPLL not locked yet\n");
10142
10143 if (val & LCPLL_CD_SOURCE_FCLK) {
10144 val = I915_READ(LCPLL_CTL);
10145 val &= ~LCPLL_CD_SOURCE_FCLK;
10146 I915_WRITE(LCPLL_CTL, val);
10147
10148 if (wait_for_us((I915_READ(LCPLL_CTL) &
10149 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10150 DRM_ERROR("Switching back to LCPLL failed\n");
10151 }
10152
10153 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10154 intel_update_cdclk(&dev_priv->drm);
10155 }
10156
10157 /*
10158 * Package states C8 and deeper are really deep PC states that can only be
10159 * reached when all the devices on the system allow it, so even if the graphics
10160 * device allows PC8+, it doesn't mean the system will actually get to these
10161 * states. Our driver only allows PC8+ when going into runtime PM.
10162 *
10163 * The requirements for PC8+ are that all the outputs are disabled, the power
10164 * well is disabled and most interrupts are disabled, and these are also
10165 * requirements for runtime PM. When these conditions are met, we manually do
10166 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10167 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10168 * hang the machine.
10169 *
10170 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10171 * the state of some registers, so when we come back from PC8+ we need to
10172 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10173 * need to take care of the registers kept by RC6. Notice that this happens even
10174 * if we don't put the device in PCI D3 state (which is what currently happens
10175 * because of the runtime PM support).
10176 *
10177 * For more, read "Display Sequences for Package C8" on the hardware
10178 * documentation.
10179 */
10180 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10181 {
10182 struct drm_device *dev = &dev_priv->drm;
10183 uint32_t val;
10184
10185 DRM_DEBUG_KMS("Enabling package C8+\n");
10186
10187 if (HAS_PCH_LPT_LP(dev)) {
10188 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10189 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10190 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10191 }
10192
10193 lpt_disable_clkout_dp(dev);
10194 hsw_disable_lcpll(dev_priv, true, true);
10195 }
10196
10197 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10198 {
10199 struct drm_device *dev = &dev_priv->drm;
10200 uint32_t val;
10201
10202 DRM_DEBUG_KMS("Disabling package C8+\n");
10203
10204 hsw_restore_lcpll(dev_priv);
10205 lpt_init_pch_refclk(dev);
10206
10207 if (HAS_PCH_LPT_LP(dev)) {
10208 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10209 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10210 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10211 }
10212 }
10213
10214 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10215 {
10216 struct drm_device *dev = old_state->dev;
10217 struct intel_atomic_state *old_intel_state =
10218 to_intel_atomic_state(old_state);
10219 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10220
10221 bxt_set_cdclk(to_i915(dev), req_cdclk);
10222 }
10223
10224 /* compute the max rate for new configuration */
10225 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10226 {
10227 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10228 struct drm_i915_private *dev_priv = to_i915(state->dev);
10229 struct drm_crtc *crtc;
10230 struct drm_crtc_state *cstate;
10231 struct intel_crtc_state *crtc_state;
10232 unsigned max_pixel_rate = 0, i;
10233 enum pipe pipe;
10234
10235 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10236 sizeof(intel_state->min_pixclk));
10237
10238 for_each_crtc_in_state(state, crtc, cstate, i) {
10239 int pixel_rate;
10240
10241 crtc_state = to_intel_crtc_state(cstate);
10242 if (!crtc_state->base.enable) {
10243 intel_state->min_pixclk[i] = 0;
10244 continue;
10245 }
10246
10247 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10248
10249 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10250 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10251 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10252
10253 intel_state->min_pixclk[i] = pixel_rate;
10254 }
10255
10256 for_each_pipe(dev_priv, pipe)
10257 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10258
10259 return max_pixel_rate;
10260 }
10261
10262 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10263 {
10264 struct drm_i915_private *dev_priv = to_i915(dev);
10265 uint32_t val, data;
10266 int ret;
10267
10268 if (WARN((I915_READ(LCPLL_CTL) &
10269 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10270 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10271 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10272 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10273 "trying to change cdclk frequency with cdclk not enabled\n"))
10274 return;
10275
10276 mutex_lock(&dev_priv->rps.hw_lock);
10277 ret = sandybridge_pcode_write(dev_priv,
10278 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10279 mutex_unlock(&dev_priv->rps.hw_lock);
10280 if (ret) {
10281 DRM_ERROR("failed to inform pcode about cdclk change\n");
10282 return;
10283 }
10284
10285 val = I915_READ(LCPLL_CTL);
10286 val |= LCPLL_CD_SOURCE_FCLK;
10287 I915_WRITE(LCPLL_CTL, val);
10288
10289 if (wait_for_us(I915_READ(LCPLL_CTL) &
10290 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10291 DRM_ERROR("Switching to FCLK failed\n");
10292
10293 val = I915_READ(LCPLL_CTL);
10294 val &= ~LCPLL_CLK_FREQ_MASK;
10295
10296 switch (cdclk) {
10297 case 450000:
10298 val |= LCPLL_CLK_FREQ_450;
10299 data = 0;
10300 break;
10301 case 540000:
10302 val |= LCPLL_CLK_FREQ_54O_BDW;
10303 data = 1;
10304 break;
10305 case 337500:
10306 val |= LCPLL_CLK_FREQ_337_5_BDW;
10307 data = 2;
10308 break;
10309 case 675000:
10310 val |= LCPLL_CLK_FREQ_675_BDW;
10311 data = 3;
10312 break;
10313 default:
10314 WARN(1, "invalid cdclk frequency\n");
10315 return;
10316 }
10317
10318 I915_WRITE(LCPLL_CTL, val);
10319
10320 val = I915_READ(LCPLL_CTL);
10321 val &= ~LCPLL_CD_SOURCE_FCLK;
10322 I915_WRITE(LCPLL_CTL, val);
10323
10324 if (wait_for_us((I915_READ(LCPLL_CTL) &
10325 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10326 DRM_ERROR("Switching back to LCPLL failed\n");
10327
10328 mutex_lock(&dev_priv->rps.hw_lock);
10329 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10330 mutex_unlock(&dev_priv->rps.hw_lock);
10331
10332 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10333
10334 intel_update_cdclk(dev);
10335
10336 WARN(cdclk != dev_priv->cdclk_freq,
10337 "cdclk requested %d kHz but got %d kHz\n",
10338 cdclk, dev_priv->cdclk_freq);
10339 }
10340
10341 static int broadwell_calc_cdclk(int max_pixclk)
10342 {
10343 if (max_pixclk > 540000)
10344 return 675000;
10345 else if (max_pixclk > 450000)
10346 return 540000;
10347 else if (max_pixclk > 337500)
10348 return 450000;
10349 else
10350 return 337500;
10351 }
10352
10353 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10354 {
10355 struct drm_i915_private *dev_priv = to_i915(state->dev);
10356 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10357 int max_pixclk = ilk_max_pixel_rate(state);
10358 int cdclk;
10359
10360 /*
10361 * FIXME should also account for plane ratio
10362 * once 64bpp pixel formats are supported.
10363 */
10364 cdclk = broadwell_calc_cdclk(max_pixclk);
10365
10366 if (cdclk > dev_priv->max_cdclk_freq) {
10367 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10368 cdclk, dev_priv->max_cdclk_freq);
10369 return -EINVAL;
10370 }
10371
10372 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10373 if (!intel_state->active_crtcs)
10374 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10375
10376 return 0;
10377 }
10378
10379 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10380 {
10381 struct drm_device *dev = old_state->dev;
10382 struct intel_atomic_state *old_intel_state =
10383 to_intel_atomic_state(old_state);
10384 unsigned req_cdclk = old_intel_state->dev_cdclk;
10385
10386 broadwell_set_cdclk(dev, req_cdclk);
10387 }
10388
10389 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10390 {
10391 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10392 struct drm_i915_private *dev_priv = to_i915(state->dev);
10393 const int max_pixclk = ilk_max_pixel_rate(state);
10394 int vco = intel_state->cdclk_pll_vco;
10395 int cdclk;
10396
10397 /*
10398 * FIXME should also account for plane ratio
10399 * once 64bpp pixel formats are supported.
10400 */
10401 cdclk = skl_calc_cdclk(max_pixclk, vco);
10402
10403 /*
10404 * FIXME move the cdclk caclulation to
10405 * compute_config() so we can fail gracegully.
10406 */
10407 if (cdclk > dev_priv->max_cdclk_freq) {
10408 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10409 cdclk, dev_priv->max_cdclk_freq);
10410 cdclk = dev_priv->max_cdclk_freq;
10411 }
10412
10413 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10414 if (!intel_state->active_crtcs)
10415 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10416
10417 return 0;
10418 }
10419
10420 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10421 {
10422 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10423 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10424 unsigned int req_cdclk = intel_state->dev_cdclk;
10425 unsigned int req_vco = intel_state->cdclk_pll_vco;
10426
10427 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10428 }
10429
10430 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10431 struct intel_crtc_state *crtc_state)
10432 {
10433 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10434 if (!intel_ddi_pll_select(crtc, crtc_state))
10435 return -EINVAL;
10436 }
10437
10438 crtc->lowfreq_avail = false;
10439
10440 return 0;
10441 }
10442
10443 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10444 enum port port,
10445 struct intel_crtc_state *pipe_config)
10446 {
10447 enum intel_dpll_id id;
10448
10449 switch (port) {
10450 case PORT_A:
10451 id = DPLL_ID_SKL_DPLL0;
10452 break;
10453 case PORT_B:
10454 id = DPLL_ID_SKL_DPLL1;
10455 break;
10456 case PORT_C:
10457 id = DPLL_ID_SKL_DPLL2;
10458 break;
10459 default:
10460 DRM_ERROR("Incorrect port type\n");
10461 return;
10462 }
10463
10464 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10465 }
10466
10467 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10468 enum port port,
10469 struct intel_crtc_state *pipe_config)
10470 {
10471 enum intel_dpll_id id;
10472 u32 temp;
10473
10474 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10475 id = temp >> (port * 3 + 1);
10476
10477 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10478 return;
10479
10480 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10481 }
10482
10483 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10484 enum port port,
10485 struct intel_crtc_state *pipe_config)
10486 {
10487 enum intel_dpll_id id;
10488 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10489
10490 switch (ddi_pll_sel) {
10491 case PORT_CLK_SEL_WRPLL1:
10492 id = DPLL_ID_WRPLL1;
10493 break;
10494 case PORT_CLK_SEL_WRPLL2:
10495 id = DPLL_ID_WRPLL2;
10496 break;
10497 case PORT_CLK_SEL_SPLL:
10498 id = DPLL_ID_SPLL;
10499 break;
10500 case PORT_CLK_SEL_LCPLL_810:
10501 id = DPLL_ID_LCPLL_810;
10502 break;
10503 case PORT_CLK_SEL_LCPLL_1350:
10504 id = DPLL_ID_LCPLL_1350;
10505 break;
10506 case PORT_CLK_SEL_LCPLL_2700:
10507 id = DPLL_ID_LCPLL_2700;
10508 break;
10509 default:
10510 MISSING_CASE(ddi_pll_sel);
10511 /* fall through */
10512 case PORT_CLK_SEL_NONE:
10513 return;
10514 }
10515
10516 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10517 }
10518
10519 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10520 struct intel_crtc_state *pipe_config,
10521 unsigned long *power_domain_mask)
10522 {
10523 struct drm_device *dev = crtc->base.dev;
10524 struct drm_i915_private *dev_priv = to_i915(dev);
10525 enum intel_display_power_domain power_domain;
10526 u32 tmp;
10527
10528 /*
10529 * The pipe->transcoder mapping is fixed with the exception of the eDP
10530 * transcoder handled below.
10531 */
10532 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10533
10534 /*
10535 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10536 * consistency and less surprising code; it's in always on power).
10537 */
10538 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10539 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10540 enum pipe trans_edp_pipe;
10541 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10542 default:
10543 WARN(1, "unknown pipe linked to edp transcoder\n");
10544 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10545 case TRANS_DDI_EDP_INPUT_A_ON:
10546 trans_edp_pipe = PIPE_A;
10547 break;
10548 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10549 trans_edp_pipe = PIPE_B;
10550 break;
10551 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10552 trans_edp_pipe = PIPE_C;
10553 break;
10554 }
10555
10556 if (trans_edp_pipe == crtc->pipe)
10557 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10558 }
10559
10560 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10561 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10562 return false;
10563 *power_domain_mask |= BIT(power_domain);
10564
10565 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10566
10567 return tmp & PIPECONF_ENABLE;
10568 }
10569
10570 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10571 struct intel_crtc_state *pipe_config,
10572 unsigned long *power_domain_mask)
10573 {
10574 struct drm_device *dev = crtc->base.dev;
10575 struct drm_i915_private *dev_priv = to_i915(dev);
10576 enum intel_display_power_domain power_domain;
10577 enum port port;
10578 enum transcoder cpu_transcoder;
10579 u32 tmp;
10580
10581 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10582 if (port == PORT_A)
10583 cpu_transcoder = TRANSCODER_DSI_A;
10584 else
10585 cpu_transcoder = TRANSCODER_DSI_C;
10586
10587 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10588 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10589 continue;
10590 *power_domain_mask |= BIT(power_domain);
10591
10592 /*
10593 * The PLL needs to be enabled with a valid divider
10594 * configuration, otherwise accessing DSI registers will hang
10595 * the machine. See BSpec North Display Engine
10596 * registers/MIPI[BXT]. We can break out here early, since we
10597 * need the same DSI PLL to be enabled for both DSI ports.
10598 */
10599 if (!intel_dsi_pll_is_enabled(dev_priv))
10600 break;
10601
10602 /* XXX: this works for video mode only */
10603 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10604 if (!(tmp & DPI_ENABLE))
10605 continue;
10606
10607 tmp = I915_READ(MIPI_CTRL(port));
10608 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10609 continue;
10610
10611 pipe_config->cpu_transcoder = cpu_transcoder;
10612 break;
10613 }
10614
10615 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10616 }
10617
10618 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10619 struct intel_crtc_state *pipe_config)
10620 {
10621 struct drm_device *dev = crtc->base.dev;
10622 struct drm_i915_private *dev_priv = to_i915(dev);
10623 struct intel_shared_dpll *pll;
10624 enum port port;
10625 uint32_t tmp;
10626
10627 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10628
10629 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10630
10631 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10632 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10633 else if (IS_BROXTON(dev))
10634 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10635 else
10636 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10637
10638 pll = pipe_config->shared_dpll;
10639 if (pll) {
10640 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10641 &pipe_config->dpll_hw_state));
10642 }
10643
10644 /*
10645 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10646 * DDI E. So just check whether this pipe is wired to DDI E and whether
10647 * the PCH transcoder is on.
10648 */
10649 if (INTEL_INFO(dev)->gen < 9 &&
10650 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10651 pipe_config->has_pch_encoder = true;
10652
10653 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10654 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10655 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10656
10657 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10658 }
10659 }
10660
10661 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10662 struct intel_crtc_state *pipe_config)
10663 {
10664 struct drm_device *dev = crtc->base.dev;
10665 struct drm_i915_private *dev_priv = to_i915(dev);
10666 enum intel_display_power_domain power_domain;
10667 unsigned long power_domain_mask;
10668 bool active;
10669
10670 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10671 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10672 return false;
10673 power_domain_mask = BIT(power_domain);
10674
10675 pipe_config->shared_dpll = NULL;
10676
10677 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10678
10679 if (IS_BROXTON(dev_priv) &&
10680 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10681 WARN_ON(active);
10682 active = true;
10683 }
10684
10685 if (!active)
10686 goto out;
10687
10688 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10689 haswell_get_ddi_port_state(crtc, pipe_config);
10690 intel_get_pipe_timings(crtc, pipe_config);
10691 }
10692
10693 intel_get_pipe_src_size(crtc, pipe_config);
10694
10695 pipe_config->gamma_mode =
10696 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10697
10698 if (INTEL_INFO(dev)->gen >= 9) {
10699 skl_init_scalers(dev, crtc, pipe_config);
10700 }
10701
10702 if (INTEL_INFO(dev)->gen >= 9) {
10703 pipe_config->scaler_state.scaler_id = -1;
10704 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10705 }
10706
10707 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10708 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10709 power_domain_mask |= BIT(power_domain);
10710 if (INTEL_INFO(dev)->gen >= 9)
10711 skylake_get_pfit_config(crtc, pipe_config);
10712 else
10713 ironlake_get_pfit_config(crtc, pipe_config);
10714 }
10715
10716 if (IS_HASWELL(dev))
10717 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10718 (I915_READ(IPS_CTL) & IPS_ENABLE);
10719
10720 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10721 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10722 pipe_config->pixel_multiplier =
10723 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10724 } else {
10725 pipe_config->pixel_multiplier = 1;
10726 }
10727
10728 out:
10729 for_each_power_domain(power_domain, power_domain_mask)
10730 intel_display_power_put(dev_priv, power_domain);
10731
10732 return active;
10733 }
10734
10735 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10736 const struct intel_plane_state *plane_state)
10737 {
10738 struct drm_device *dev = crtc->dev;
10739 struct drm_i915_private *dev_priv = to_i915(dev);
10740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741 uint32_t cntl = 0, size = 0;
10742
10743 if (plane_state && plane_state->base.visible) {
10744 unsigned int width = plane_state->base.crtc_w;
10745 unsigned int height = plane_state->base.crtc_h;
10746 unsigned int stride = roundup_pow_of_two(width) * 4;
10747
10748 switch (stride) {
10749 default:
10750 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10751 width, stride);
10752 stride = 256;
10753 /* fallthrough */
10754 case 256:
10755 case 512:
10756 case 1024:
10757 case 2048:
10758 break;
10759 }
10760
10761 cntl |= CURSOR_ENABLE |
10762 CURSOR_GAMMA_ENABLE |
10763 CURSOR_FORMAT_ARGB |
10764 CURSOR_STRIDE(stride);
10765
10766 size = (height << 12) | width;
10767 }
10768
10769 if (intel_crtc->cursor_cntl != 0 &&
10770 (intel_crtc->cursor_base != base ||
10771 intel_crtc->cursor_size != size ||
10772 intel_crtc->cursor_cntl != cntl)) {
10773 /* On these chipsets we can only modify the base/size/stride
10774 * whilst the cursor is disabled.
10775 */
10776 I915_WRITE(CURCNTR(PIPE_A), 0);
10777 POSTING_READ(CURCNTR(PIPE_A));
10778 intel_crtc->cursor_cntl = 0;
10779 }
10780
10781 if (intel_crtc->cursor_base != base) {
10782 I915_WRITE(CURBASE(PIPE_A), base);
10783 intel_crtc->cursor_base = base;
10784 }
10785
10786 if (intel_crtc->cursor_size != size) {
10787 I915_WRITE(CURSIZE, size);
10788 intel_crtc->cursor_size = size;
10789 }
10790
10791 if (intel_crtc->cursor_cntl != cntl) {
10792 I915_WRITE(CURCNTR(PIPE_A), cntl);
10793 POSTING_READ(CURCNTR(PIPE_A));
10794 intel_crtc->cursor_cntl = cntl;
10795 }
10796 }
10797
10798 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10799 const struct intel_plane_state *plane_state)
10800 {
10801 struct drm_device *dev = crtc->dev;
10802 struct drm_i915_private *dev_priv = to_i915(dev);
10803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10804 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10805 int pipe = intel_crtc->pipe;
10806 uint32_t cntl = 0;
10807
10808 if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10809 skl_write_cursor_wm(intel_crtc, wm);
10810
10811 if (plane_state && plane_state->base.visible) {
10812 cntl = MCURSOR_GAMMA_ENABLE;
10813 switch (plane_state->base.crtc_w) {
10814 case 64:
10815 cntl |= CURSOR_MODE_64_ARGB_AX;
10816 break;
10817 case 128:
10818 cntl |= CURSOR_MODE_128_ARGB_AX;
10819 break;
10820 case 256:
10821 cntl |= CURSOR_MODE_256_ARGB_AX;
10822 break;
10823 default:
10824 MISSING_CASE(plane_state->base.crtc_w);
10825 return;
10826 }
10827 cntl |= pipe << 28; /* Connect to correct pipe */
10828
10829 if (HAS_DDI(dev))
10830 cntl |= CURSOR_PIPE_CSC_ENABLE;
10831
10832 if (plane_state->base.rotation == DRM_ROTATE_180)
10833 cntl |= CURSOR_ROTATE_180;
10834 }
10835
10836 if (intel_crtc->cursor_cntl != cntl) {
10837 I915_WRITE(CURCNTR(pipe), cntl);
10838 POSTING_READ(CURCNTR(pipe));
10839 intel_crtc->cursor_cntl = cntl;
10840 }
10841
10842 /* and commit changes on next vblank */
10843 I915_WRITE(CURBASE(pipe), base);
10844 POSTING_READ(CURBASE(pipe));
10845
10846 intel_crtc->cursor_base = base;
10847 }
10848
10849 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10850 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10851 const struct intel_plane_state *plane_state)
10852 {
10853 struct drm_device *dev = crtc->dev;
10854 struct drm_i915_private *dev_priv = to_i915(dev);
10855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10856 int pipe = intel_crtc->pipe;
10857 u32 base = intel_crtc->cursor_addr;
10858 u32 pos = 0;
10859
10860 if (plane_state) {
10861 int x = plane_state->base.crtc_x;
10862 int y = plane_state->base.crtc_y;
10863
10864 if (x < 0) {
10865 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10866 x = -x;
10867 }
10868 pos |= x << CURSOR_X_SHIFT;
10869
10870 if (y < 0) {
10871 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10872 y = -y;
10873 }
10874 pos |= y << CURSOR_Y_SHIFT;
10875
10876 /* ILK+ do this automagically */
10877 if (HAS_GMCH_DISPLAY(dev) &&
10878 plane_state->base.rotation == DRM_ROTATE_180) {
10879 base += (plane_state->base.crtc_h *
10880 plane_state->base.crtc_w - 1) * 4;
10881 }
10882 }
10883
10884 I915_WRITE(CURPOS(pipe), pos);
10885
10886 if (IS_845G(dev) || IS_I865G(dev))
10887 i845_update_cursor(crtc, base, plane_state);
10888 else
10889 i9xx_update_cursor(crtc, base, plane_state);
10890 }
10891
10892 static bool cursor_size_ok(struct drm_device *dev,
10893 uint32_t width, uint32_t height)
10894 {
10895 if (width == 0 || height == 0)
10896 return false;
10897
10898 /*
10899 * 845g/865g are special in that they are only limited by
10900 * the width of their cursors, the height is arbitrary up to
10901 * the precision of the register. Everything else requires
10902 * square cursors, limited to a few power-of-two sizes.
10903 */
10904 if (IS_845G(dev) || IS_I865G(dev)) {
10905 if ((width & 63) != 0)
10906 return false;
10907
10908 if (width > (IS_845G(dev) ? 64 : 512))
10909 return false;
10910
10911 if (height > 1023)
10912 return false;
10913 } else {
10914 switch (width | height) {
10915 case 256:
10916 case 128:
10917 if (IS_GEN2(dev))
10918 return false;
10919 case 64:
10920 break;
10921 default:
10922 return false;
10923 }
10924 }
10925
10926 return true;
10927 }
10928
10929 /* VESA 640x480x72Hz mode to set on the pipe */
10930 static struct drm_display_mode load_detect_mode = {
10931 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10932 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10933 };
10934
10935 struct drm_framebuffer *
10936 __intel_framebuffer_create(struct drm_device *dev,
10937 struct drm_mode_fb_cmd2 *mode_cmd,
10938 struct drm_i915_gem_object *obj)
10939 {
10940 struct intel_framebuffer *intel_fb;
10941 int ret;
10942
10943 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10944 if (!intel_fb)
10945 return ERR_PTR(-ENOMEM);
10946
10947 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10948 if (ret)
10949 goto err;
10950
10951 return &intel_fb->base;
10952
10953 err:
10954 kfree(intel_fb);
10955 return ERR_PTR(ret);
10956 }
10957
10958 static struct drm_framebuffer *
10959 intel_framebuffer_create(struct drm_device *dev,
10960 struct drm_mode_fb_cmd2 *mode_cmd,
10961 struct drm_i915_gem_object *obj)
10962 {
10963 struct drm_framebuffer *fb;
10964 int ret;
10965
10966 ret = i915_mutex_lock_interruptible(dev);
10967 if (ret)
10968 return ERR_PTR(ret);
10969 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10970 mutex_unlock(&dev->struct_mutex);
10971
10972 return fb;
10973 }
10974
10975 static u32
10976 intel_framebuffer_pitch_for_width(int width, int bpp)
10977 {
10978 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10979 return ALIGN(pitch, 64);
10980 }
10981
10982 static u32
10983 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10984 {
10985 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10986 return PAGE_ALIGN(pitch * mode->vdisplay);
10987 }
10988
10989 static struct drm_framebuffer *
10990 intel_framebuffer_create_for_mode(struct drm_device *dev,
10991 struct drm_display_mode *mode,
10992 int depth, int bpp)
10993 {
10994 struct drm_framebuffer *fb;
10995 struct drm_i915_gem_object *obj;
10996 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10997
10998 obj = i915_gem_object_create(dev,
10999 intel_framebuffer_size_for_mode(mode, bpp));
11000 if (IS_ERR(obj))
11001 return ERR_CAST(obj);
11002
11003 mode_cmd.width = mode->hdisplay;
11004 mode_cmd.height = mode->vdisplay;
11005 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11006 bpp);
11007 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11008
11009 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11010 if (IS_ERR(fb))
11011 i915_gem_object_put_unlocked(obj);
11012
11013 return fb;
11014 }
11015
11016 static struct drm_framebuffer *
11017 mode_fits_in_fbdev(struct drm_device *dev,
11018 struct drm_display_mode *mode)
11019 {
11020 #ifdef CONFIG_DRM_FBDEV_EMULATION
11021 struct drm_i915_private *dev_priv = to_i915(dev);
11022 struct drm_i915_gem_object *obj;
11023 struct drm_framebuffer *fb;
11024
11025 if (!dev_priv->fbdev)
11026 return NULL;
11027
11028 if (!dev_priv->fbdev->fb)
11029 return NULL;
11030
11031 obj = dev_priv->fbdev->fb->obj;
11032 BUG_ON(!obj);
11033
11034 fb = &dev_priv->fbdev->fb->base;
11035 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11036 fb->bits_per_pixel))
11037 return NULL;
11038
11039 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11040 return NULL;
11041
11042 drm_framebuffer_reference(fb);
11043 return fb;
11044 #else
11045 return NULL;
11046 #endif
11047 }
11048
11049 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11050 struct drm_crtc *crtc,
11051 struct drm_display_mode *mode,
11052 struct drm_framebuffer *fb,
11053 int x, int y)
11054 {
11055 struct drm_plane_state *plane_state;
11056 int hdisplay, vdisplay;
11057 int ret;
11058
11059 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11060 if (IS_ERR(plane_state))
11061 return PTR_ERR(plane_state);
11062
11063 if (mode)
11064 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11065 else
11066 hdisplay = vdisplay = 0;
11067
11068 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11069 if (ret)
11070 return ret;
11071 drm_atomic_set_fb_for_plane(plane_state, fb);
11072 plane_state->crtc_x = 0;
11073 plane_state->crtc_y = 0;
11074 plane_state->crtc_w = hdisplay;
11075 plane_state->crtc_h = vdisplay;
11076 plane_state->src_x = x << 16;
11077 plane_state->src_y = y << 16;
11078 plane_state->src_w = hdisplay << 16;
11079 plane_state->src_h = vdisplay << 16;
11080
11081 return 0;
11082 }
11083
11084 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11085 struct drm_display_mode *mode,
11086 struct intel_load_detect_pipe *old,
11087 struct drm_modeset_acquire_ctx *ctx)
11088 {
11089 struct intel_crtc *intel_crtc;
11090 struct intel_encoder *intel_encoder =
11091 intel_attached_encoder(connector);
11092 struct drm_crtc *possible_crtc;
11093 struct drm_encoder *encoder = &intel_encoder->base;
11094 struct drm_crtc *crtc = NULL;
11095 struct drm_device *dev = encoder->dev;
11096 struct drm_framebuffer *fb;
11097 struct drm_mode_config *config = &dev->mode_config;
11098 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11099 struct drm_connector_state *connector_state;
11100 struct intel_crtc_state *crtc_state;
11101 int ret, i = -1;
11102
11103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11104 connector->base.id, connector->name,
11105 encoder->base.id, encoder->name);
11106
11107 old->restore_state = NULL;
11108
11109 retry:
11110 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11111 if (ret)
11112 goto fail;
11113
11114 /*
11115 * Algorithm gets a little messy:
11116 *
11117 * - if the connector already has an assigned crtc, use it (but make
11118 * sure it's on first)
11119 *
11120 * - try to find the first unused crtc that can drive this connector,
11121 * and use that if we find one
11122 */
11123
11124 /* See if we already have a CRTC for this connector */
11125 if (connector->state->crtc) {
11126 crtc = connector->state->crtc;
11127
11128 ret = drm_modeset_lock(&crtc->mutex, ctx);
11129 if (ret)
11130 goto fail;
11131
11132 /* Make sure the crtc and connector are running */
11133 goto found;
11134 }
11135
11136 /* Find an unused one (if possible) */
11137 for_each_crtc(dev, possible_crtc) {
11138 i++;
11139 if (!(encoder->possible_crtcs & (1 << i)))
11140 continue;
11141
11142 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11143 if (ret)
11144 goto fail;
11145
11146 if (possible_crtc->state->enable) {
11147 drm_modeset_unlock(&possible_crtc->mutex);
11148 continue;
11149 }
11150
11151 crtc = possible_crtc;
11152 break;
11153 }
11154
11155 /*
11156 * If we didn't find an unused CRTC, don't use any.
11157 */
11158 if (!crtc) {
11159 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11160 goto fail;
11161 }
11162
11163 found:
11164 intel_crtc = to_intel_crtc(crtc);
11165
11166 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11167 if (ret)
11168 goto fail;
11169
11170 state = drm_atomic_state_alloc(dev);
11171 restore_state = drm_atomic_state_alloc(dev);
11172 if (!state || !restore_state) {
11173 ret = -ENOMEM;
11174 goto fail;
11175 }
11176
11177 state->acquire_ctx = ctx;
11178 restore_state->acquire_ctx = ctx;
11179
11180 connector_state = drm_atomic_get_connector_state(state, connector);
11181 if (IS_ERR(connector_state)) {
11182 ret = PTR_ERR(connector_state);
11183 goto fail;
11184 }
11185
11186 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11187 if (ret)
11188 goto fail;
11189
11190 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11191 if (IS_ERR(crtc_state)) {
11192 ret = PTR_ERR(crtc_state);
11193 goto fail;
11194 }
11195
11196 crtc_state->base.active = crtc_state->base.enable = true;
11197
11198 if (!mode)
11199 mode = &load_detect_mode;
11200
11201 /* We need a framebuffer large enough to accommodate all accesses
11202 * that the plane may generate whilst we perform load detection.
11203 * We can not rely on the fbcon either being present (we get called
11204 * during its initialisation to detect all boot displays, or it may
11205 * not even exist) or that it is large enough to satisfy the
11206 * requested mode.
11207 */
11208 fb = mode_fits_in_fbdev(dev, mode);
11209 if (fb == NULL) {
11210 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11211 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11212 } else
11213 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11214 if (IS_ERR(fb)) {
11215 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11216 goto fail;
11217 }
11218
11219 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11220 if (ret)
11221 goto fail;
11222
11223 drm_framebuffer_unreference(fb);
11224
11225 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11226 if (ret)
11227 goto fail;
11228
11229 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11230 if (!ret)
11231 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11232 if (!ret)
11233 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11234 if (ret) {
11235 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11236 goto fail;
11237 }
11238
11239 ret = drm_atomic_commit(state);
11240 if (ret) {
11241 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11242 goto fail;
11243 }
11244
11245 old->restore_state = restore_state;
11246
11247 /* let the connector get through one full cycle before testing */
11248 intel_wait_for_vblank(dev, intel_crtc->pipe);
11249 return true;
11250
11251 fail:
11252 drm_atomic_state_free(state);
11253 drm_atomic_state_free(restore_state);
11254 restore_state = state = NULL;
11255
11256 if (ret == -EDEADLK) {
11257 drm_modeset_backoff(ctx);
11258 goto retry;
11259 }
11260
11261 return false;
11262 }
11263
11264 void intel_release_load_detect_pipe(struct drm_connector *connector,
11265 struct intel_load_detect_pipe *old,
11266 struct drm_modeset_acquire_ctx *ctx)
11267 {
11268 struct intel_encoder *intel_encoder =
11269 intel_attached_encoder(connector);
11270 struct drm_encoder *encoder = &intel_encoder->base;
11271 struct drm_atomic_state *state = old->restore_state;
11272 int ret;
11273
11274 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11275 connector->base.id, connector->name,
11276 encoder->base.id, encoder->name);
11277
11278 if (!state)
11279 return;
11280
11281 ret = drm_atomic_commit(state);
11282 if (ret) {
11283 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11284 drm_atomic_state_free(state);
11285 }
11286 }
11287
11288 static int i9xx_pll_refclk(struct drm_device *dev,
11289 const struct intel_crtc_state *pipe_config)
11290 {
11291 struct drm_i915_private *dev_priv = to_i915(dev);
11292 u32 dpll = pipe_config->dpll_hw_state.dpll;
11293
11294 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11295 return dev_priv->vbt.lvds_ssc_freq;
11296 else if (HAS_PCH_SPLIT(dev))
11297 return 120000;
11298 else if (!IS_GEN2(dev))
11299 return 96000;
11300 else
11301 return 48000;
11302 }
11303
11304 /* Returns the clock of the currently programmed mode of the given pipe. */
11305 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11306 struct intel_crtc_state *pipe_config)
11307 {
11308 struct drm_device *dev = crtc->base.dev;
11309 struct drm_i915_private *dev_priv = to_i915(dev);
11310 int pipe = pipe_config->cpu_transcoder;
11311 u32 dpll = pipe_config->dpll_hw_state.dpll;
11312 u32 fp;
11313 struct dpll clock;
11314 int port_clock;
11315 int refclk = i9xx_pll_refclk(dev, pipe_config);
11316
11317 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11318 fp = pipe_config->dpll_hw_state.fp0;
11319 else
11320 fp = pipe_config->dpll_hw_state.fp1;
11321
11322 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11323 if (IS_PINEVIEW(dev)) {
11324 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11325 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11326 } else {
11327 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11328 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11329 }
11330
11331 if (!IS_GEN2(dev)) {
11332 if (IS_PINEVIEW(dev))
11333 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11334 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11335 else
11336 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11337 DPLL_FPA01_P1_POST_DIV_SHIFT);
11338
11339 switch (dpll & DPLL_MODE_MASK) {
11340 case DPLLB_MODE_DAC_SERIAL:
11341 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11342 5 : 10;
11343 break;
11344 case DPLLB_MODE_LVDS:
11345 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11346 7 : 14;
11347 break;
11348 default:
11349 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11350 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11351 return;
11352 }
11353
11354 if (IS_PINEVIEW(dev))
11355 port_clock = pnv_calc_dpll_params(refclk, &clock);
11356 else
11357 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11358 } else {
11359 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11360 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11361
11362 if (is_lvds) {
11363 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11364 DPLL_FPA01_P1_POST_DIV_SHIFT);
11365
11366 if (lvds & LVDS_CLKB_POWER_UP)
11367 clock.p2 = 7;
11368 else
11369 clock.p2 = 14;
11370 } else {
11371 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11372 clock.p1 = 2;
11373 else {
11374 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11375 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11376 }
11377 if (dpll & PLL_P2_DIVIDE_BY_4)
11378 clock.p2 = 4;
11379 else
11380 clock.p2 = 2;
11381 }
11382
11383 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11384 }
11385
11386 /*
11387 * This value includes pixel_multiplier. We will use
11388 * port_clock to compute adjusted_mode.crtc_clock in the
11389 * encoder's get_config() function.
11390 */
11391 pipe_config->port_clock = port_clock;
11392 }
11393
11394 int intel_dotclock_calculate(int link_freq,
11395 const struct intel_link_m_n *m_n)
11396 {
11397 /*
11398 * The calculation for the data clock is:
11399 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11400 * But we want to avoid losing precison if possible, so:
11401 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11402 *
11403 * and the link clock is simpler:
11404 * link_clock = (m * link_clock) / n
11405 */
11406
11407 if (!m_n->link_n)
11408 return 0;
11409
11410 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11411 }
11412
11413 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11414 struct intel_crtc_state *pipe_config)
11415 {
11416 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11417
11418 /* read out port_clock from the DPLL */
11419 i9xx_crtc_clock_get(crtc, pipe_config);
11420
11421 /*
11422 * In case there is an active pipe without active ports,
11423 * we may need some idea for the dotclock anyway.
11424 * Calculate one based on the FDI configuration.
11425 */
11426 pipe_config->base.adjusted_mode.crtc_clock =
11427 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11428 &pipe_config->fdi_m_n);
11429 }
11430
11431 /** Returns the currently programmed mode of the given pipe. */
11432 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11433 struct drm_crtc *crtc)
11434 {
11435 struct drm_i915_private *dev_priv = to_i915(dev);
11436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11437 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11438 struct drm_display_mode *mode;
11439 struct intel_crtc_state *pipe_config;
11440 int htot = I915_READ(HTOTAL(cpu_transcoder));
11441 int hsync = I915_READ(HSYNC(cpu_transcoder));
11442 int vtot = I915_READ(VTOTAL(cpu_transcoder));
11443 int vsync = I915_READ(VSYNC(cpu_transcoder));
11444 enum pipe pipe = intel_crtc->pipe;
11445
11446 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11447 if (!mode)
11448 return NULL;
11449
11450 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11451 if (!pipe_config) {
11452 kfree(mode);
11453 return NULL;
11454 }
11455
11456 /*
11457 * Construct a pipe_config sufficient for getting the clock info
11458 * back out of crtc_clock_get.
11459 *
11460 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11461 * to use a real value here instead.
11462 */
11463 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11464 pipe_config->pixel_multiplier = 1;
11465 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11466 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11467 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11468 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11469
11470 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11471 mode->hdisplay = (htot & 0xffff) + 1;
11472 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11473 mode->hsync_start = (hsync & 0xffff) + 1;
11474 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11475 mode->vdisplay = (vtot & 0xffff) + 1;
11476 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11477 mode->vsync_start = (vsync & 0xffff) + 1;
11478 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11479
11480 drm_mode_set_name(mode);
11481
11482 kfree(pipe_config);
11483
11484 return mode;
11485 }
11486
11487 static void intel_crtc_destroy(struct drm_crtc *crtc)
11488 {
11489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11490 struct drm_device *dev = crtc->dev;
11491 struct intel_flip_work *work;
11492
11493 spin_lock_irq(&dev->event_lock);
11494 work = intel_crtc->flip_work;
11495 intel_crtc->flip_work = NULL;
11496 spin_unlock_irq(&dev->event_lock);
11497
11498 if (work) {
11499 cancel_work_sync(&work->mmio_work);
11500 cancel_work_sync(&work->unpin_work);
11501 kfree(work);
11502 }
11503
11504 drm_crtc_cleanup(crtc);
11505
11506 kfree(intel_crtc);
11507 }
11508
11509 static void intel_unpin_work_fn(struct work_struct *__work)
11510 {
11511 struct intel_flip_work *work =
11512 container_of(__work, struct intel_flip_work, unpin_work);
11513 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11514 struct drm_device *dev = crtc->base.dev;
11515 struct drm_plane *primary = crtc->base.primary;
11516
11517 if (is_mmio_work(work))
11518 flush_work(&work->mmio_work);
11519
11520 mutex_lock(&dev->struct_mutex);
11521 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11522 i915_gem_object_put(work->pending_flip_obj);
11523 mutex_unlock(&dev->struct_mutex);
11524
11525 i915_gem_request_put(work->flip_queued_req);
11526
11527 intel_frontbuffer_flip_complete(to_i915(dev),
11528 to_intel_plane(primary)->frontbuffer_bit);
11529 intel_fbc_post_update(crtc);
11530 drm_framebuffer_unreference(work->old_fb);
11531
11532 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11533 atomic_dec(&crtc->unpin_work_count);
11534
11535 kfree(work);
11536 }
11537
11538 /* Is 'a' after or equal to 'b'? */
11539 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11540 {
11541 return !((a - b) & 0x80000000);
11542 }
11543
11544 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11545 struct intel_flip_work *work)
11546 {
11547 struct drm_device *dev = crtc->base.dev;
11548 struct drm_i915_private *dev_priv = to_i915(dev);
11549
11550 if (abort_flip_on_reset(crtc))
11551 return true;
11552
11553 /*
11554 * The relevant registers doen't exist on pre-ctg.
11555 * As the flip done interrupt doesn't trigger for mmio
11556 * flips on gmch platforms, a flip count check isn't
11557 * really needed there. But since ctg has the registers,
11558 * include it in the check anyway.
11559 */
11560 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11561 return true;
11562
11563 /*
11564 * BDW signals flip done immediately if the plane
11565 * is disabled, even if the plane enable is already
11566 * armed to occur at the next vblank :(
11567 */
11568
11569 /*
11570 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11571 * used the same base address. In that case the mmio flip might
11572 * have completed, but the CS hasn't even executed the flip yet.
11573 *
11574 * A flip count check isn't enough as the CS might have updated
11575 * the base address just after start of vblank, but before we
11576 * managed to process the interrupt. This means we'd complete the
11577 * CS flip too soon.
11578 *
11579 * Combining both checks should get us a good enough result. It may
11580 * still happen that the CS flip has been executed, but has not
11581 * yet actually completed. But in case the base address is the same
11582 * anyway, we don't really care.
11583 */
11584 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11585 crtc->flip_work->gtt_offset &&
11586 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11587 crtc->flip_work->flip_count);
11588 }
11589
11590 static bool
11591 __pageflip_finished_mmio(struct intel_crtc *crtc,
11592 struct intel_flip_work *work)
11593 {
11594 /*
11595 * MMIO work completes when vblank is different from
11596 * flip_queued_vblank.
11597 *
11598 * Reset counter value doesn't matter, this is handled by
11599 * i915_wait_request finishing early, so no need to handle
11600 * reset here.
11601 */
11602 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11603 }
11604
11605
11606 static bool pageflip_finished(struct intel_crtc *crtc,
11607 struct intel_flip_work *work)
11608 {
11609 if (!atomic_read(&work->pending))
11610 return false;
11611
11612 smp_rmb();
11613
11614 if (is_mmio_work(work))
11615 return __pageflip_finished_mmio(crtc, work);
11616 else
11617 return __pageflip_finished_cs(crtc, work);
11618 }
11619
11620 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11621 {
11622 struct drm_device *dev = &dev_priv->drm;
11623 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11625 struct intel_flip_work *work;
11626 unsigned long flags;
11627
11628 /* Ignore early vblank irqs */
11629 if (!crtc)
11630 return;
11631
11632 /*
11633 * This is called both by irq handlers and the reset code (to complete
11634 * lost pageflips) so needs the full irqsave spinlocks.
11635 */
11636 spin_lock_irqsave(&dev->event_lock, flags);
11637 work = intel_crtc->flip_work;
11638
11639 if (work != NULL &&
11640 !is_mmio_work(work) &&
11641 pageflip_finished(intel_crtc, work))
11642 page_flip_completed(intel_crtc);
11643
11644 spin_unlock_irqrestore(&dev->event_lock, flags);
11645 }
11646
11647 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11648 {
11649 struct drm_device *dev = &dev_priv->drm;
11650 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11652 struct intel_flip_work *work;
11653 unsigned long flags;
11654
11655 /* Ignore early vblank irqs */
11656 if (!crtc)
11657 return;
11658
11659 /*
11660 * This is called both by irq handlers and the reset code (to complete
11661 * lost pageflips) so needs the full irqsave spinlocks.
11662 */
11663 spin_lock_irqsave(&dev->event_lock, flags);
11664 work = intel_crtc->flip_work;
11665
11666 if (work != NULL &&
11667 is_mmio_work(work) &&
11668 pageflip_finished(intel_crtc, work))
11669 page_flip_completed(intel_crtc);
11670
11671 spin_unlock_irqrestore(&dev->event_lock, flags);
11672 }
11673
11674 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11675 struct intel_flip_work *work)
11676 {
11677 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11678
11679 /* Ensure that the work item is consistent when activating it ... */
11680 smp_mb__before_atomic();
11681 atomic_set(&work->pending, 1);
11682 }
11683
11684 static int intel_gen2_queue_flip(struct drm_device *dev,
11685 struct drm_crtc *crtc,
11686 struct drm_framebuffer *fb,
11687 struct drm_i915_gem_object *obj,
11688 struct drm_i915_gem_request *req,
11689 uint32_t flags)
11690 {
11691 struct intel_ring *ring = req->ring;
11692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11693 u32 flip_mask;
11694 int ret;
11695
11696 ret = intel_ring_begin(req, 6);
11697 if (ret)
11698 return ret;
11699
11700 /* Can't queue multiple flips, so wait for the previous
11701 * one to finish before executing the next.
11702 */
11703 if (intel_crtc->plane)
11704 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11705 else
11706 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11707 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11708 intel_ring_emit(ring, MI_NOOP);
11709 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11710 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11711 intel_ring_emit(ring, fb->pitches[0]);
11712 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11713 intel_ring_emit(ring, 0); /* aux display base address, unused */
11714
11715 return 0;
11716 }
11717
11718 static int intel_gen3_queue_flip(struct drm_device *dev,
11719 struct drm_crtc *crtc,
11720 struct drm_framebuffer *fb,
11721 struct drm_i915_gem_object *obj,
11722 struct drm_i915_gem_request *req,
11723 uint32_t flags)
11724 {
11725 struct intel_ring *ring = req->ring;
11726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11727 u32 flip_mask;
11728 int ret;
11729
11730 ret = intel_ring_begin(req, 6);
11731 if (ret)
11732 return ret;
11733
11734 if (intel_crtc->plane)
11735 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11736 else
11737 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11738 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11739 intel_ring_emit(ring, MI_NOOP);
11740 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11741 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11742 intel_ring_emit(ring, fb->pitches[0]);
11743 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11744 intel_ring_emit(ring, MI_NOOP);
11745
11746 return 0;
11747 }
11748
11749 static int intel_gen4_queue_flip(struct drm_device *dev,
11750 struct drm_crtc *crtc,
11751 struct drm_framebuffer *fb,
11752 struct drm_i915_gem_object *obj,
11753 struct drm_i915_gem_request *req,
11754 uint32_t flags)
11755 {
11756 struct intel_ring *ring = req->ring;
11757 struct drm_i915_private *dev_priv = to_i915(dev);
11758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11759 uint32_t pf, pipesrc;
11760 int ret;
11761
11762 ret = intel_ring_begin(req, 4);
11763 if (ret)
11764 return ret;
11765
11766 /* i965+ uses the linear or tiled offsets from the
11767 * Display Registers (which do not change across a page-flip)
11768 * so we need only reprogram the base address.
11769 */
11770 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11771 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11772 intel_ring_emit(ring, fb->pitches[0]);
11773 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11774 intel_fb_modifier_to_tiling(fb->modifier[0]));
11775
11776 /* XXX Enabling the panel-fitter across page-flip is so far
11777 * untested on non-native modes, so ignore it for now.
11778 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11779 */
11780 pf = 0;
11781 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11782 intel_ring_emit(ring, pf | pipesrc);
11783
11784 return 0;
11785 }
11786
11787 static int intel_gen6_queue_flip(struct drm_device *dev,
11788 struct drm_crtc *crtc,
11789 struct drm_framebuffer *fb,
11790 struct drm_i915_gem_object *obj,
11791 struct drm_i915_gem_request *req,
11792 uint32_t flags)
11793 {
11794 struct intel_ring *ring = req->ring;
11795 struct drm_i915_private *dev_priv = to_i915(dev);
11796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11797 uint32_t pf, pipesrc;
11798 int ret;
11799
11800 ret = intel_ring_begin(req, 4);
11801 if (ret)
11802 return ret;
11803
11804 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11805 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11806 intel_ring_emit(ring, fb->pitches[0] |
11807 intel_fb_modifier_to_tiling(fb->modifier[0]));
11808 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11809
11810 /* Contrary to the suggestions in the documentation,
11811 * "Enable Panel Fitter" does not seem to be required when page
11812 * flipping with a non-native mode, and worse causes a normal
11813 * modeset to fail.
11814 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11815 */
11816 pf = 0;
11817 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11818 intel_ring_emit(ring, pf | pipesrc);
11819
11820 return 0;
11821 }
11822
11823 static int intel_gen7_queue_flip(struct drm_device *dev,
11824 struct drm_crtc *crtc,
11825 struct drm_framebuffer *fb,
11826 struct drm_i915_gem_object *obj,
11827 struct drm_i915_gem_request *req,
11828 uint32_t flags)
11829 {
11830 struct intel_ring *ring = req->ring;
11831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11832 uint32_t plane_bit = 0;
11833 int len, ret;
11834
11835 switch (intel_crtc->plane) {
11836 case PLANE_A:
11837 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11838 break;
11839 case PLANE_B:
11840 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11841 break;
11842 case PLANE_C:
11843 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11844 break;
11845 default:
11846 WARN_ONCE(1, "unknown plane in flip command\n");
11847 return -ENODEV;
11848 }
11849
11850 len = 4;
11851 if (req->engine->id == RCS) {
11852 len += 6;
11853 /*
11854 * On Gen 8, SRM is now taking an extra dword to accommodate
11855 * 48bits addresses, and we need a NOOP for the batch size to
11856 * stay even.
11857 */
11858 if (IS_GEN8(dev))
11859 len += 2;
11860 }
11861
11862 /*
11863 * BSpec MI_DISPLAY_FLIP for IVB:
11864 * "The full packet must be contained within the same cache line."
11865 *
11866 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11867 * cacheline, if we ever start emitting more commands before
11868 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11869 * then do the cacheline alignment, and finally emit the
11870 * MI_DISPLAY_FLIP.
11871 */
11872 ret = intel_ring_cacheline_align(req);
11873 if (ret)
11874 return ret;
11875
11876 ret = intel_ring_begin(req, len);
11877 if (ret)
11878 return ret;
11879
11880 /* Unmask the flip-done completion message. Note that the bspec says that
11881 * we should do this for both the BCS and RCS, and that we must not unmask
11882 * more than one flip event at any time (or ensure that one flip message
11883 * can be sent by waiting for flip-done prior to queueing new flips).
11884 * Experimentation says that BCS works despite DERRMR masking all
11885 * flip-done completion events and that unmasking all planes at once
11886 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11887 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11888 */
11889 if (req->engine->id == RCS) {
11890 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11891 intel_ring_emit_reg(ring, DERRMR);
11892 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11893 DERRMR_PIPEB_PRI_FLIP_DONE |
11894 DERRMR_PIPEC_PRI_FLIP_DONE));
11895 if (IS_GEN8(dev))
11896 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11897 MI_SRM_LRM_GLOBAL_GTT);
11898 else
11899 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11900 MI_SRM_LRM_GLOBAL_GTT);
11901 intel_ring_emit_reg(ring, DERRMR);
11902 intel_ring_emit(ring,
11903 i915_ggtt_offset(req->engine->scratch) + 256);
11904 if (IS_GEN8(dev)) {
11905 intel_ring_emit(ring, 0);
11906 intel_ring_emit(ring, MI_NOOP);
11907 }
11908 }
11909
11910 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11911 intel_ring_emit(ring, fb->pitches[0] |
11912 intel_fb_modifier_to_tiling(fb->modifier[0]));
11913 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11914 intel_ring_emit(ring, (MI_NOOP));
11915
11916 return 0;
11917 }
11918
11919 static bool use_mmio_flip(struct intel_engine_cs *engine,
11920 struct drm_i915_gem_object *obj)
11921 {
11922 struct reservation_object *resv;
11923
11924 /*
11925 * This is not being used for older platforms, because
11926 * non-availability of flip done interrupt forces us to use
11927 * CS flips. Older platforms derive flip done using some clever
11928 * tricks involving the flip_pending status bits and vblank irqs.
11929 * So using MMIO flips there would disrupt this mechanism.
11930 */
11931
11932 if (engine == NULL)
11933 return true;
11934
11935 if (INTEL_GEN(engine->i915) < 5)
11936 return false;
11937
11938 if (i915.use_mmio_flip < 0)
11939 return false;
11940 else if (i915.use_mmio_flip > 0)
11941 return true;
11942 else if (i915.enable_execlists)
11943 return true;
11944
11945 resv = i915_gem_object_get_dmabuf_resv(obj);
11946 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11947 return true;
11948
11949 return engine != i915_gem_active_get_engine(&obj->last_write,
11950 &obj->base.dev->struct_mutex);
11951 }
11952
11953 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11954 unsigned int rotation,
11955 struct intel_flip_work *work)
11956 {
11957 struct drm_device *dev = intel_crtc->base.dev;
11958 struct drm_i915_private *dev_priv = to_i915(dev);
11959 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11960 const enum pipe pipe = intel_crtc->pipe;
11961 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11962
11963 ctl = I915_READ(PLANE_CTL(pipe, 0));
11964 ctl &= ~PLANE_CTL_TILED_MASK;
11965 switch (fb->modifier[0]) {
11966 case DRM_FORMAT_MOD_NONE:
11967 break;
11968 case I915_FORMAT_MOD_X_TILED:
11969 ctl |= PLANE_CTL_TILED_X;
11970 break;
11971 case I915_FORMAT_MOD_Y_TILED:
11972 ctl |= PLANE_CTL_TILED_Y;
11973 break;
11974 case I915_FORMAT_MOD_Yf_TILED:
11975 ctl |= PLANE_CTL_TILED_YF;
11976 break;
11977 default:
11978 MISSING_CASE(fb->modifier[0]);
11979 }
11980
11981 /*
11982 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11983 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11984 */
11985 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11986 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11987
11988 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11989 POSTING_READ(PLANE_SURF(pipe, 0));
11990 }
11991
11992 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11993 struct intel_flip_work *work)
11994 {
11995 struct drm_device *dev = intel_crtc->base.dev;
11996 struct drm_i915_private *dev_priv = to_i915(dev);
11997 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11998 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11999 u32 dspcntr;
12000
12001 dspcntr = I915_READ(reg);
12002
12003 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12004 dspcntr |= DISPPLANE_TILED;
12005 else
12006 dspcntr &= ~DISPPLANE_TILED;
12007
12008 I915_WRITE(reg, dspcntr);
12009
12010 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12011 POSTING_READ(DSPSURF(intel_crtc->plane));
12012 }
12013
12014 static void intel_mmio_flip_work_func(struct work_struct *w)
12015 {
12016 struct intel_flip_work *work =
12017 container_of(w, struct intel_flip_work, mmio_work);
12018 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12020 struct intel_framebuffer *intel_fb =
12021 to_intel_framebuffer(crtc->base.primary->fb);
12022 struct drm_i915_gem_object *obj = intel_fb->obj;
12023 struct reservation_object *resv;
12024
12025 if (work->flip_queued_req)
12026 WARN_ON(i915_wait_request(work->flip_queued_req,
12027 0, NULL, NO_WAITBOOST));
12028
12029 /* For framebuffer backed by dmabuf, wait for fence */
12030 resv = i915_gem_object_get_dmabuf_resv(obj);
12031 if (resv)
12032 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12033 MAX_SCHEDULE_TIMEOUT) < 0);
12034
12035 intel_pipe_update_start(crtc);
12036
12037 if (INTEL_GEN(dev_priv) >= 9)
12038 skl_do_mmio_flip(crtc, work->rotation, work);
12039 else
12040 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12041 ilk_do_mmio_flip(crtc, work);
12042
12043 intel_pipe_update_end(crtc, work);
12044 }
12045
12046 static int intel_default_queue_flip(struct drm_device *dev,
12047 struct drm_crtc *crtc,
12048 struct drm_framebuffer *fb,
12049 struct drm_i915_gem_object *obj,
12050 struct drm_i915_gem_request *req,
12051 uint32_t flags)
12052 {
12053 return -ENODEV;
12054 }
12055
12056 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12057 struct intel_crtc *intel_crtc,
12058 struct intel_flip_work *work)
12059 {
12060 u32 addr, vblank;
12061
12062 if (!atomic_read(&work->pending))
12063 return false;
12064
12065 smp_rmb();
12066
12067 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12068 if (work->flip_ready_vblank == 0) {
12069 if (work->flip_queued_req &&
12070 !i915_gem_request_completed(work->flip_queued_req))
12071 return false;
12072
12073 work->flip_ready_vblank = vblank;
12074 }
12075
12076 if (vblank - work->flip_ready_vblank < 3)
12077 return false;
12078
12079 /* Potential stall - if we see that the flip has happened,
12080 * assume a missed interrupt. */
12081 if (INTEL_GEN(dev_priv) >= 4)
12082 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12083 else
12084 addr = I915_READ(DSPADDR(intel_crtc->plane));
12085
12086 /* There is a potential issue here with a false positive after a flip
12087 * to the same address. We could address this by checking for a
12088 * non-incrementing frame counter.
12089 */
12090 return addr == work->gtt_offset;
12091 }
12092
12093 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12094 {
12095 struct drm_device *dev = &dev_priv->drm;
12096 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12098 struct intel_flip_work *work;
12099
12100 WARN_ON(!in_interrupt());
12101
12102 if (crtc == NULL)
12103 return;
12104
12105 spin_lock(&dev->event_lock);
12106 work = intel_crtc->flip_work;
12107
12108 if (work != NULL && !is_mmio_work(work) &&
12109 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12110 WARN_ONCE(1,
12111 "Kicking stuck page flip: queued at %d, now %d\n",
12112 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12113 page_flip_completed(intel_crtc);
12114 work = NULL;
12115 }
12116
12117 if (work != NULL && !is_mmio_work(work) &&
12118 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12119 intel_queue_rps_boost_for_request(work->flip_queued_req);
12120 spin_unlock(&dev->event_lock);
12121 }
12122
12123 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12124 struct drm_framebuffer *fb,
12125 struct drm_pending_vblank_event *event,
12126 uint32_t page_flip_flags)
12127 {
12128 struct drm_device *dev = crtc->dev;
12129 struct drm_i915_private *dev_priv = to_i915(dev);
12130 struct drm_framebuffer *old_fb = crtc->primary->fb;
12131 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12133 struct drm_plane *primary = crtc->primary;
12134 enum pipe pipe = intel_crtc->pipe;
12135 struct intel_flip_work *work;
12136 struct intel_engine_cs *engine;
12137 bool mmio_flip;
12138 struct drm_i915_gem_request *request;
12139 struct i915_vma *vma;
12140 int ret;
12141
12142 /*
12143 * drm_mode_page_flip_ioctl() should already catch this, but double
12144 * check to be safe. In the future we may enable pageflipping from
12145 * a disabled primary plane.
12146 */
12147 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12148 return -EBUSY;
12149
12150 /* Can't change pixel format via MI display flips. */
12151 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12152 return -EINVAL;
12153
12154 /*
12155 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12156 * Note that pitch changes could also affect these register.
12157 */
12158 if (INTEL_INFO(dev)->gen > 3 &&
12159 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12160 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12161 return -EINVAL;
12162
12163 if (i915_terminally_wedged(&dev_priv->gpu_error))
12164 goto out_hang;
12165
12166 work = kzalloc(sizeof(*work), GFP_KERNEL);
12167 if (work == NULL)
12168 return -ENOMEM;
12169
12170 work->event = event;
12171 work->crtc = crtc;
12172 work->old_fb = old_fb;
12173 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12174
12175 ret = drm_crtc_vblank_get(crtc);
12176 if (ret)
12177 goto free_work;
12178
12179 /* We borrow the event spin lock for protecting flip_work */
12180 spin_lock_irq(&dev->event_lock);
12181 if (intel_crtc->flip_work) {
12182 /* Before declaring the flip queue wedged, check if
12183 * the hardware completed the operation behind our backs.
12184 */
12185 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12186 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12187 page_flip_completed(intel_crtc);
12188 } else {
12189 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12190 spin_unlock_irq(&dev->event_lock);
12191
12192 drm_crtc_vblank_put(crtc);
12193 kfree(work);
12194 return -EBUSY;
12195 }
12196 }
12197 intel_crtc->flip_work = work;
12198 spin_unlock_irq(&dev->event_lock);
12199
12200 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12201 flush_workqueue(dev_priv->wq);
12202
12203 /* Reference the objects for the scheduled work. */
12204 drm_framebuffer_reference(work->old_fb);
12205
12206 crtc->primary->fb = fb;
12207 update_state_fb(crtc->primary);
12208
12209 work->pending_flip_obj = i915_gem_object_get(obj);
12210
12211 ret = i915_mutex_lock_interruptible(dev);
12212 if (ret)
12213 goto cleanup;
12214
12215 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12216 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12217 ret = -EIO;
12218 goto cleanup;
12219 }
12220
12221 atomic_inc(&intel_crtc->unpin_work_count);
12222
12223 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12224 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12225
12226 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12227 engine = &dev_priv->engine[BCS];
12228 if (fb->modifier[0] != old_fb->modifier[0])
12229 /* vlv: DISPLAY_FLIP fails to change tiling */
12230 engine = NULL;
12231 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12232 engine = &dev_priv->engine[BCS];
12233 } else if (INTEL_INFO(dev)->gen >= 7) {
12234 engine = i915_gem_active_get_engine(&obj->last_write,
12235 &obj->base.dev->struct_mutex);
12236 if (engine == NULL || engine->id != RCS)
12237 engine = &dev_priv->engine[BCS];
12238 } else {
12239 engine = &dev_priv->engine[RCS];
12240 }
12241
12242 mmio_flip = use_mmio_flip(engine, obj);
12243
12244 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12245 if (IS_ERR(vma)) {
12246 ret = PTR_ERR(vma);
12247 goto cleanup_pending;
12248 }
12249
12250 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12251 work->gtt_offset += intel_crtc->dspaddr_offset;
12252 work->rotation = crtc->primary->state->rotation;
12253
12254 /*
12255 * There's the potential that the next frame will not be compatible with
12256 * FBC, so we want to call pre_update() before the actual page flip.
12257 * The problem is that pre_update() caches some information about the fb
12258 * object, so we want to do this only after the object is pinned. Let's
12259 * be on the safe side and do this immediately before scheduling the
12260 * flip.
12261 */
12262 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12263 to_intel_plane_state(primary->state));
12264
12265 if (mmio_flip) {
12266 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12267
12268 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12269 &obj->base.dev->struct_mutex);
12270 schedule_work(&work->mmio_work);
12271 } else {
12272 request = i915_gem_request_alloc(engine, engine->last_context);
12273 if (IS_ERR(request)) {
12274 ret = PTR_ERR(request);
12275 goto cleanup_unpin;
12276 }
12277
12278 ret = i915_gem_request_await_object(request, obj, false);
12279 if (ret)
12280 goto cleanup_request;
12281
12282 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12283 page_flip_flags);
12284 if (ret)
12285 goto cleanup_request;
12286
12287 intel_mark_page_flip_active(intel_crtc, work);
12288
12289 work->flip_queued_req = i915_gem_request_get(request);
12290 i915_add_request_no_flush(request);
12291 }
12292
12293 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12294 to_intel_plane(primary)->frontbuffer_bit);
12295 mutex_unlock(&dev->struct_mutex);
12296
12297 intel_frontbuffer_flip_prepare(to_i915(dev),
12298 to_intel_plane(primary)->frontbuffer_bit);
12299
12300 trace_i915_flip_request(intel_crtc->plane, obj);
12301
12302 return 0;
12303
12304 cleanup_request:
12305 i915_add_request_no_flush(request);
12306 cleanup_unpin:
12307 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12308 cleanup_pending:
12309 atomic_dec(&intel_crtc->unpin_work_count);
12310 mutex_unlock(&dev->struct_mutex);
12311 cleanup:
12312 crtc->primary->fb = old_fb;
12313 update_state_fb(crtc->primary);
12314
12315 i915_gem_object_put_unlocked(obj);
12316 drm_framebuffer_unreference(work->old_fb);
12317
12318 spin_lock_irq(&dev->event_lock);
12319 intel_crtc->flip_work = NULL;
12320 spin_unlock_irq(&dev->event_lock);
12321
12322 drm_crtc_vblank_put(crtc);
12323 free_work:
12324 kfree(work);
12325
12326 if (ret == -EIO) {
12327 struct drm_atomic_state *state;
12328 struct drm_plane_state *plane_state;
12329
12330 out_hang:
12331 state = drm_atomic_state_alloc(dev);
12332 if (!state)
12333 return -ENOMEM;
12334 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12335
12336 retry:
12337 plane_state = drm_atomic_get_plane_state(state, primary);
12338 ret = PTR_ERR_OR_ZERO(plane_state);
12339 if (!ret) {
12340 drm_atomic_set_fb_for_plane(plane_state, fb);
12341
12342 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12343 if (!ret)
12344 ret = drm_atomic_commit(state);
12345 }
12346
12347 if (ret == -EDEADLK) {
12348 drm_modeset_backoff(state->acquire_ctx);
12349 drm_atomic_state_clear(state);
12350 goto retry;
12351 }
12352
12353 if (ret)
12354 drm_atomic_state_free(state);
12355
12356 if (ret == 0 && event) {
12357 spin_lock_irq(&dev->event_lock);
12358 drm_crtc_send_vblank_event(crtc, event);
12359 spin_unlock_irq(&dev->event_lock);
12360 }
12361 }
12362 return ret;
12363 }
12364
12365
12366 /**
12367 * intel_wm_need_update - Check whether watermarks need updating
12368 * @plane: drm plane
12369 * @state: new plane state
12370 *
12371 * Check current plane state versus the new one to determine whether
12372 * watermarks need to be recalculated.
12373 *
12374 * Returns true or false.
12375 */
12376 static bool intel_wm_need_update(struct drm_plane *plane,
12377 struct drm_plane_state *state)
12378 {
12379 struct intel_plane_state *new = to_intel_plane_state(state);
12380 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12381
12382 /* Update watermarks on tiling or size changes. */
12383 if (new->base.visible != cur->base.visible)
12384 return true;
12385
12386 if (!cur->base.fb || !new->base.fb)
12387 return false;
12388
12389 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12390 cur->base.rotation != new->base.rotation ||
12391 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12392 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12393 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12394 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12395 return true;
12396
12397 return false;
12398 }
12399
12400 static bool needs_scaling(struct intel_plane_state *state)
12401 {
12402 int src_w = drm_rect_width(&state->base.src) >> 16;
12403 int src_h = drm_rect_height(&state->base.src) >> 16;
12404 int dst_w = drm_rect_width(&state->base.dst);
12405 int dst_h = drm_rect_height(&state->base.dst);
12406
12407 return (src_w != dst_w || src_h != dst_h);
12408 }
12409
12410 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12411 struct drm_plane_state *plane_state)
12412 {
12413 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12414 struct drm_crtc *crtc = crtc_state->crtc;
12415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12416 struct drm_plane *plane = plane_state->plane;
12417 struct drm_device *dev = crtc->dev;
12418 struct drm_i915_private *dev_priv = to_i915(dev);
12419 struct intel_plane_state *old_plane_state =
12420 to_intel_plane_state(plane->state);
12421 bool mode_changed = needs_modeset(crtc_state);
12422 bool was_crtc_enabled = crtc->state->active;
12423 bool is_crtc_enabled = crtc_state->active;
12424 bool turn_off, turn_on, visible, was_visible;
12425 struct drm_framebuffer *fb = plane_state->fb;
12426 int ret;
12427
12428 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12429 ret = skl_update_scaler_plane(
12430 to_intel_crtc_state(crtc_state),
12431 to_intel_plane_state(plane_state));
12432 if (ret)
12433 return ret;
12434 }
12435
12436 was_visible = old_plane_state->base.visible;
12437 visible = to_intel_plane_state(plane_state)->base.visible;
12438
12439 if (!was_crtc_enabled && WARN_ON(was_visible))
12440 was_visible = false;
12441
12442 /*
12443 * Visibility is calculated as if the crtc was on, but
12444 * after scaler setup everything depends on it being off
12445 * when the crtc isn't active.
12446 *
12447 * FIXME this is wrong for watermarks. Watermarks should also
12448 * be computed as if the pipe would be active. Perhaps move
12449 * per-plane wm computation to the .check_plane() hook, and
12450 * only combine the results from all planes in the current place?
12451 */
12452 if (!is_crtc_enabled)
12453 to_intel_plane_state(plane_state)->base.visible = visible = false;
12454
12455 if (!was_visible && !visible)
12456 return 0;
12457
12458 if (fb != old_plane_state->base.fb)
12459 pipe_config->fb_changed = true;
12460
12461 turn_off = was_visible && (!visible || mode_changed);
12462 turn_on = visible && (!was_visible || mode_changed);
12463
12464 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12465 intel_crtc->base.base.id,
12466 intel_crtc->base.name,
12467 plane->base.id, plane->name,
12468 fb ? fb->base.id : -1);
12469
12470 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12471 plane->base.id, plane->name,
12472 was_visible, visible,
12473 turn_off, turn_on, mode_changed);
12474
12475 if (turn_on) {
12476 pipe_config->update_wm_pre = true;
12477
12478 /* must disable cxsr around plane enable/disable */
12479 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12480 pipe_config->disable_cxsr = true;
12481 } else if (turn_off) {
12482 pipe_config->update_wm_post = true;
12483
12484 /* must disable cxsr around plane enable/disable */
12485 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12486 pipe_config->disable_cxsr = true;
12487 } else if (intel_wm_need_update(plane, plane_state)) {
12488 /* FIXME bollocks */
12489 pipe_config->update_wm_pre = true;
12490 pipe_config->update_wm_post = true;
12491 }
12492
12493 /* Pre-gen9 platforms need two-step watermark updates */
12494 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12495 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12496 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12497
12498 if (visible || was_visible)
12499 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12500
12501 /*
12502 * WaCxSRDisabledForSpriteScaling:ivb
12503 *
12504 * cstate->update_wm was already set above, so this flag will
12505 * take effect when we commit and program watermarks.
12506 */
12507 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12508 needs_scaling(to_intel_plane_state(plane_state)) &&
12509 !needs_scaling(old_plane_state))
12510 pipe_config->disable_lp_wm = true;
12511
12512 return 0;
12513 }
12514
12515 static bool encoders_cloneable(const struct intel_encoder *a,
12516 const struct intel_encoder *b)
12517 {
12518 /* masks could be asymmetric, so check both ways */
12519 return a == b || (a->cloneable & (1 << b->type) &&
12520 b->cloneable & (1 << a->type));
12521 }
12522
12523 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12524 struct intel_crtc *crtc,
12525 struct intel_encoder *encoder)
12526 {
12527 struct intel_encoder *source_encoder;
12528 struct drm_connector *connector;
12529 struct drm_connector_state *connector_state;
12530 int i;
12531
12532 for_each_connector_in_state(state, connector, connector_state, i) {
12533 if (connector_state->crtc != &crtc->base)
12534 continue;
12535
12536 source_encoder =
12537 to_intel_encoder(connector_state->best_encoder);
12538 if (!encoders_cloneable(encoder, source_encoder))
12539 return false;
12540 }
12541
12542 return true;
12543 }
12544
12545 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12546 struct drm_crtc_state *crtc_state)
12547 {
12548 struct drm_device *dev = crtc->dev;
12549 struct drm_i915_private *dev_priv = to_i915(dev);
12550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12551 struct intel_crtc_state *pipe_config =
12552 to_intel_crtc_state(crtc_state);
12553 struct drm_atomic_state *state = crtc_state->state;
12554 int ret;
12555 bool mode_changed = needs_modeset(crtc_state);
12556
12557 if (mode_changed && !crtc_state->active)
12558 pipe_config->update_wm_post = true;
12559
12560 if (mode_changed && crtc_state->enable &&
12561 dev_priv->display.crtc_compute_clock &&
12562 !WARN_ON(pipe_config->shared_dpll)) {
12563 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12564 pipe_config);
12565 if (ret)
12566 return ret;
12567 }
12568
12569 if (crtc_state->color_mgmt_changed) {
12570 ret = intel_color_check(crtc, crtc_state);
12571 if (ret)
12572 return ret;
12573
12574 /*
12575 * Changing color management on Intel hardware is
12576 * handled as part of planes update.
12577 */
12578 crtc_state->planes_changed = true;
12579 }
12580
12581 ret = 0;
12582 if (dev_priv->display.compute_pipe_wm) {
12583 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12584 if (ret) {
12585 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12586 return ret;
12587 }
12588 }
12589
12590 if (dev_priv->display.compute_intermediate_wm &&
12591 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12592 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12593 return 0;
12594
12595 /*
12596 * Calculate 'intermediate' watermarks that satisfy both the
12597 * old state and the new state. We can program these
12598 * immediately.
12599 */
12600 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12601 intel_crtc,
12602 pipe_config);
12603 if (ret) {
12604 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12605 return ret;
12606 }
12607 } else if (dev_priv->display.compute_intermediate_wm) {
12608 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12609 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12610 }
12611
12612 if (INTEL_INFO(dev)->gen >= 9) {
12613 if (mode_changed)
12614 ret = skl_update_scaler_crtc(pipe_config);
12615
12616 if (!ret)
12617 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12618 pipe_config);
12619 }
12620
12621 return ret;
12622 }
12623
12624 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12625 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12626 .atomic_begin = intel_begin_crtc_commit,
12627 .atomic_flush = intel_finish_crtc_commit,
12628 .atomic_check = intel_crtc_atomic_check,
12629 };
12630
12631 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12632 {
12633 struct intel_connector *connector;
12634
12635 for_each_intel_connector(dev, connector) {
12636 if (connector->base.state->crtc)
12637 drm_connector_unreference(&connector->base);
12638
12639 if (connector->base.encoder) {
12640 connector->base.state->best_encoder =
12641 connector->base.encoder;
12642 connector->base.state->crtc =
12643 connector->base.encoder->crtc;
12644
12645 drm_connector_reference(&connector->base);
12646 } else {
12647 connector->base.state->best_encoder = NULL;
12648 connector->base.state->crtc = NULL;
12649 }
12650 }
12651 }
12652
12653 static void
12654 connected_sink_compute_bpp(struct intel_connector *connector,
12655 struct intel_crtc_state *pipe_config)
12656 {
12657 int bpp = pipe_config->pipe_bpp;
12658
12659 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12660 connector->base.base.id,
12661 connector->base.name);
12662
12663 /* Don't use an invalid EDID bpc value */
12664 if (connector->base.display_info.bpc &&
12665 connector->base.display_info.bpc * 3 < bpp) {
12666 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12667 bpp, connector->base.display_info.bpc*3);
12668 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12669 }
12670
12671 /* Clamp bpp to 8 on screens without EDID 1.4 */
12672 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12673 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12674 bpp);
12675 pipe_config->pipe_bpp = 24;
12676 }
12677 }
12678
12679 static int
12680 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12681 struct intel_crtc_state *pipe_config)
12682 {
12683 struct drm_device *dev = crtc->base.dev;
12684 struct drm_atomic_state *state;
12685 struct drm_connector *connector;
12686 struct drm_connector_state *connector_state;
12687 int bpp, i;
12688
12689 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12690 bpp = 10*3;
12691 else if (INTEL_INFO(dev)->gen >= 5)
12692 bpp = 12*3;
12693 else
12694 bpp = 8*3;
12695
12696
12697 pipe_config->pipe_bpp = bpp;
12698
12699 state = pipe_config->base.state;
12700
12701 /* Clamp display bpp to EDID value */
12702 for_each_connector_in_state(state, connector, connector_state, i) {
12703 if (connector_state->crtc != &crtc->base)
12704 continue;
12705
12706 connected_sink_compute_bpp(to_intel_connector(connector),
12707 pipe_config);
12708 }
12709
12710 return bpp;
12711 }
12712
12713 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12714 {
12715 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12716 "type: 0x%x flags: 0x%x\n",
12717 mode->crtc_clock,
12718 mode->crtc_hdisplay, mode->crtc_hsync_start,
12719 mode->crtc_hsync_end, mode->crtc_htotal,
12720 mode->crtc_vdisplay, mode->crtc_vsync_start,
12721 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12722 }
12723
12724 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12725 struct intel_crtc_state *pipe_config,
12726 const char *context)
12727 {
12728 struct drm_device *dev = crtc->base.dev;
12729 struct drm_plane *plane;
12730 struct intel_plane *intel_plane;
12731 struct intel_plane_state *state;
12732 struct drm_framebuffer *fb;
12733
12734 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12735 crtc->base.base.id, crtc->base.name,
12736 context, pipe_config, pipe_name(crtc->pipe));
12737
12738 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12739 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12740 pipe_config->pipe_bpp, pipe_config->dither);
12741 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12742 pipe_config->has_pch_encoder,
12743 pipe_config->fdi_lanes,
12744 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12745 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12746 pipe_config->fdi_m_n.tu);
12747 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12748 intel_crtc_has_dp_encoder(pipe_config),
12749 pipe_config->lane_count,
12750 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12751 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12752 pipe_config->dp_m_n.tu);
12753
12754 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12755 intel_crtc_has_dp_encoder(pipe_config),
12756 pipe_config->lane_count,
12757 pipe_config->dp_m2_n2.gmch_m,
12758 pipe_config->dp_m2_n2.gmch_n,
12759 pipe_config->dp_m2_n2.link_m,
12760 pipe_config->dp_m2_n2.link_n,
12761 pipe_config->dp_m2_n2.tu);
12762
12763 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12764 pipe_config->has_audio,
12765 pipe_config->has_infoframe);
12766
12767 DRM_DEBUG_KMS("requested mode:\n");
12768 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12769 DRM_DEBUG_KMS("adjusted mode:\n");
12770 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12771 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12772 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12773 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12774 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12775 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12776 crtc->num_scalers,
12777 pipe_config->scaler_state.scaler_users,
12778 pipe_config->scaler_state.scaler_id);
12779 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12780 pipe_config->gmch_pfit.control,
12781 pipe_config->gmch_pfit.pgm_ratios,
12782 pipe_config->gmch_pfit.lvds_border_bits);
12783 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12784 pipe_config->pch_pfit.pos,
12785 pipe_config->pch_pfit.size,
12786 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12787 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12788 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12789
12790 if (IS_BROXTON(dev)) {
12791 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12792 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12793 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12794 pipe_config->dpll_hw_state.ebb0,
12795 pipe_config->dpll_hw_state.ebb4,
12796 pipe_config->dpll_hw_state.pll0,
12797 pipe_config->dpll_hw_state.pll1,
12798 pipe_config->dpll_hw_state.pll2,
12799 pipe_config->dpll_hw_state.pll3,
12800 pipe_config->dpll_hw_state.pll6,
12801 pipe_config->dpll_hw_state.pll8,
12802 pipe_config->dpll_hw_state.pll9,
12803 pipe_config->dpll_hw_state.pll10,
12804 pipe_config->dpll_hw_state.pcsdw12);
12805 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12806 DRM_DEBUG_KMS("dpll_hw_state: "
12807 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12808 pipe_config->dpll_hw_state.ctrl1,
12809 pipe_config->dpll_hw_state.cfgcr1,
12810 pipe_config->dpll_hw_state.cfgcr2);
12811 } else if (HAS_DDI(dev)) {
12812 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12813 pipe_config->dpll_hw_state.wrpll,
12814 pipe_config->dpll_hw_state.spll);
12815 } else {
12816 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12817 "fp0: 0x%x, fp1: 0x%x\n",
12818 pipe_config->dpll_hw_state.dpll,
12819 pipe_config->dpll_hw_state.dpll_md,
12820 pipe_config->dpll_hw_state.fp0,
12821 pipe_config->dpll_hw_state.fp1);
12822 }
12823
12824 DRM_DEBUG_KMS("planes on this crtc\n");
12825 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12826 char *format_name;
12827 intel_plane = to_intel_plane(plane);
12828 if (intel_plane->pipe != crtc->pipe)
12829 continue;
12830
12831 state = to_intel_plane_state(plane->state);
12832 fb = state->base.fb;
12833 if (!fb) {
12834 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12835 plane->base.id, plane->name, state->scaler_id);
12836 continue;
12837 }
12838
12839 format_name = drm_get_format_name(fb->pixel_format);
12840
12841 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12842 plane->base.id, plane->name);
12843 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12844 fb->base.id, fb->width, fb->height, format_name);
12845 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12846 state->scaler_id,
12847 state->base.src.x1 >> 16,
12848 state->base.src.y1 >> 16,
12849 drm_rect_width(&state->base.src) >> 16,
12850 drm_rect_height(&state->base.src) >> 16,
12851 state->base.dst.x1, state->base.dst.y1,
12852 drm_rect_width(&state->base.dst),
12853 drm_rect_height(&state->base.dst));
12854
12855 kfree(format_name);
12856 }
12857 }
12858
12859 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12860 {
12861 struct drm_device *dev = state->dev;
12862 struct drm_connector *connector;
12863 unsigned int used_ports = 0;
12864 unsigned int used_mst_ports = 0;
12865
12866 /*
12867 * Walk the connector list instead of the encoder
12868 * list to detect the problem on ddi platforms
12869 * where there's just one encoder per digital port.
12870 */
12871 drm_for_each_connector(connector, dev) {
12872 struct drm_connector_state *connector_state;
12873 struct intel_encoder *encoder;
12874
12875 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12876 if (!connector_state)
12877 connector_state = connector->state;
12878
12879 if (!connector_state->best_encoder)
12880 continue;
12881
12882 encoder = to_intel_encoder(connector_state->best_encoder);
12883
12884 WARN_ON(!connector_state->crtc);
12885
12886 switch (encoder->type) {
12887 unsigned int port_mask;
12888 case INTEL_OUTPUT_UNKNOWN:
12889 if (WARN_ON(!HAS_DDI(dev)))
12890 break;
12891 case INTEL_OUTPUT_DP:
12892 case INTEL_OUTPUT_HDMI:
12893 case INTEL_OUTPUT_EDP:
12894 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12895
12896 /* the same port mustn't appear more than once */
12897 if (used_ports & port_mask)
12898 return false;
12899
12900 used_ports |= port_mask;
12901 break;
12902 case INTEL_OUTPUT_DP_MST:
12903 used_mst_ports |=
12904 1 << enc_to_mst(&encoder->base)->primary->port;
12905 break;
12906 default:
12907 break;
12908 }
12909 }
12910
12911 /* can't mix MST and SST/HDMI on the same port */
12912 if (used_ports & used_mst_ports)
12913 return false;
12914
12915 return true;
12916 }
12917
12918 static void
12919 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12920 {
12921 struct drm_crtc_state tmp_state;
12922 struct intel_crtc_scaler_state scaler_state;
12923 struct intel_dpll_hw_state dpll_hw_state;
12924 struct intel_shared_dpll *shared_dpll;
12925 bool force_thru;
12926
12927 /* FIXME: before the switch to atomic started, a new pipe_config was
12928 * kzalloc'd. Code that depends on any field being zero should be
12929 * fixed, so that the crtc_state can be safely duplicated. For now,
12930 * only fields that are know to not cause problems are preserved. */
12931
12932 tmp_state = crtc_state->base;
12933 scaler_state = crtc_state->scaler_state;
12934 shared_dpll = crtc_state->shared_dpll;
12935 dpll_hw_state = crtc_state->dpll_hw_state;
12936 force_thru = crtc_state->pch_pfit.force_thru;
12937
12938 memset(crtc_state, 0, sizeof *crtc_state);
12939
12940 crtc_state->base = tmp_state;
12941 crtc_state->scaler_state = scaler_state;
12942 crtc_state->shared_dpll = shared_dpll;
12943 crtc_state->dpll_hw_state = dpll_hw_state;
12944 crtc_state->pch_pfit.force_thru = force_thru;
12945 }
12946
12947 static int
12948 intel_modeset_pipe_config(struct drm_crtc *crtc,
12949 struct intel_crtc_state *pipe_config)
12950 {
12951 struct drm_atomic_state *state = pipe_config->base.state;
12952 struct intel_encoder *encoder;
12953 struct drm_connector *connector;
12954 struct drm_connector_state *connector_state;
12955 int base_bpp, ret = -EINVAL;
12956 int i;
12957 bool retry = true;
12958
12959 clear_intel_crtc_state(pipe_config);
12960
12961 pipe_config->cpu_transcoder =
12962 (enum transcoder) to_intel_crtc(crtc)->pipe;
12963
12964 /*
12965 * Sanitize sync polarity flags based on requested ones. If neither
12966 * positive or negative polarity is requested, treat this as meaning
12967 * negative polarity.
12968 */
12969 if (!(pipe_config->base.adjusted_mode.flags &
12970 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12971 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12972
12973 if (!(pipe_config->base.adjusted_mode.flags &
12974 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12975 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12976
12977 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12978 pipe_config);
12979 if (base_bpp < 0)
12980 goto fail;
12981
12982 /*
12983 * Determine the real pipe dimensions. Note that stereo modes can
12984 * increase the actual pipe size due to the frame doubling and
12985 * insertion of additional space for blanks between the frame. This
12986 * is stored in the crtc timings. We use the requested mode to do this
12987 * computation to clearly distinguish it from the adjusted mode, which
12988 * can be changed by the connectors in the below retry loop.
12989 */
12990 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12991 &pipe_config->pipe_src_w,
12992 &pipe_config->pipe_src_h);
12993
12994 for_each_connector_in_state(state, connector, connector_state, i) {
12995 if (connector_state->crtc != crtc)
12996 continue;
12997
12998 encoder = to_intel_encoder(connector_state->best_encoder);
12999
13000 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13001 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13002 goto fail;
13003 }
13004
13005 /*
13006 * Determine output_types before calling the .compute_config()
13007 * hooks so that the hooks can use this information safely.
13008 */
13009 pipe_config->output_types |= 1 << encoder->type;
13010 }
13011
13012 encoder_retry:
13013 /* Ensure the port clock defaults are reset when retrying. */
13014 pipe_config->port_clock = 0;
13015 pipe_config->pixel_multiplier = 1;
13016
13017 /* Fill in default crtc timings, allow encoders to overwrite them. */
13018 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13019 CRTC_STEREO_DOUBLE);
13020
13021 /* Pass our mode to the connectors and the CRTC to give them a chance to
13022 * adjust it according to limitations or connector properties, and also
13023 * a chance to reject the mode entirely.
13024 */
13025 for_each_connector_in_state(state, connector, connector_state, i) {
13026 if (connector_state->crtc != crtc)
13027 continue;
13028
13029 encoder = to_intel_encoder(connector_state->best_encoder);
13030
13031 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13032 DRM_DEBUG_KMS("Encoder config failure\n");
13033 goto fail;
13034 }
13035 }
13036
13037 /* Set default port clock if not overwritten by the encoder. Needs to be
13038 * done afterwards in case the encoder adjusts the mode. */
13039 if (!pipe_config->port_clock)
13040 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13041 * pipe_config->pixel_multiplier;
13042
13043 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13044 if (ret < 0) {
13045 DRM_DEBUG_KMS("CRTC fixup failed\n");
13046 goto fail;
13047 }
13048
13049 if (ret == RETRY) {
13050 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13051 ret = -EINVAL;
13052 goto fail;
13053 }
13054
13055 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13056 retry = false;
13057 goto encoder_retry;
13058 }
13059
13060 /* Dithering seems to not pass-through bits correctly when it should, so
13061 * only enable it on 6bpc panels. */
13062 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13063 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13064 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13065
13066 fail:
13067 return ret;
13068 }
13069
13070 static void
13071 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13072 {
13073 struct drm_crtc *crtc;
13074 struct drm_crtc_state *crtc_state;
13075 int i;
13076
13077 /* Double check state. */
13078 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13079 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13080
13081 /* Update hwmode for vblank functions */
13082 if (crtc->state->active)
13083 crtc->hwmode = crtc->state->adjusted_mode;
13084 else
13085 crtc->hwmode.crtc_clock = 0;
13086
13087 /*
13088 * Update legacy state to satisfy fbc code. This can
13089 * be removed when fbc uses the atomic state.
13090 */
13091 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13092 struct drm_plane_state *plane_state = crtc->primary->state;
13093
13094 crtc->primary->fb = plane_state->fb;
13095 crtc->x = plane_state->src_x >> 16;
13096 crtc->y = plane_state->src_y >> 16;
13097 }
13098 }
13099 }
13100
13101 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13102 {
13103 int diff;
13104
13105 if (clock1 == clock2)
13106 return true;
13107
13108 if (!clock1 || !clock2)
13109 return false;
13110
13111 diff = abs(clock1 - clock2);
13112
13113 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13114 return true;
13115
13116 return false;
13117 }
13118
13119 static bool
13120 intel_compare_m_n(unsigned int m, unsigned int n,
13121 unsigned int m2, unsigned int n2,
13122 bool exact)
13123 {
13124 if (m == m2 && n == n2)
13125 return true;
13126
13127 if (exact || !m || !n || !m2 || !n2)
13128 return false;
13129
13130 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13131
13132 if (n > n2) {
13133 while (n > n2) {
13134 m2 <<= 1;
13135 n2 <<= 1;
13136 }
13137 } else if (n < n2) {
13138 while (n < n2) {
13139 m <<= 1;
13140 n <<= 1;
13141 }
13142 }
13143
13144 if (n != n2)
13145 return false;
13146
13147 return intel_fuzzy_clock_check(m, m2);
13148 }
13149
13150 static bool
13151 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13152 struct intel_link_m_n *m2_n2,
13153 bool adjust)
13154 {
13155 if (m_n->tu == m2_n2->tu &&
13156 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13157 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13158 intel_compare_m_n(m_n->link_m, m_n->link_n,
13159 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13160 if (adjust)
13161 *m2_n2 = *m_n;
13162
13163 return true;
13164 }
13165
13166 return false;
13167 }
13168
13169 static bool
13170 intel_pipe_config_compare(struct drm_device *dev,
13171 struct intel_crtc_state *current_config,
13172 struct intel_crtc_state *pipe_config,
13173 bool adjust)
13174 {
13175 bool ret = true;
13176
13177 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13178 do { \
13179 if (!adjust) \
13180 DRM_ERROR(fmt, ##__VA_ARGS__); \
13181 else \
13182 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13183 } while (0)
13184
13185 #define PIPE_CONF_CHECK_X(name) \
13186 if (current_config->name != pipe_config->name) { \
13187 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13188 "(expected 0x%08x, found 0x%08x)\n", \
13189 current_config->name, \
13190 pipe_config->name); \
13191 ret = false; \
13192 }
13193
13194 #define PIPE_CONF_CHECK_I(name) \
13195 if (current_config->name != pipe_config->name) { \
13196 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13197 "(expected %i, found %i)\n", \
13198 current_config->name, \
13199 pipe_config->name); \
13200 ret = false; \
13201 }
13202
13203 #define PIPE_CONF_CHECK_P(name) \
13204 if (current_config->name != pipe_config->name) { \
13205 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13206 "(expected %p, found %p)\n", \
13207 current_config->name, \
13208 pipe_config->name); \
13209 ret = false; \
13210 }
13211
13212 #define PIPE_CONF_CHECK_M_N(name) \
13213 if (!intel_compare_link_m_n(&current_config->name, \
13214 &pipe_config->name,\
13215 adjust)) { \
13216 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13217 "(expected tu %i gmch %i/%i link %i/%i, " \
13218 "found tu %i, gmch %i/%i link %i/%i)\n", \
13219 current_config->name.tu, \
13220 current_config->name.gmch_m, \
13221 current_config->name.gmch_n, \
13222 current_config->name.link_m, \
13223 current_config->name.link_n, \
13224 pipe_config->name.tu, \
13225 pipe_config->name.gmch_m, \
13226 pipe_config->name.gmch_n, \
13227 pipe_config->name.link_m, \
13228 pipe_config->name.link_n); \
13229 ret = false; \
13230 }
13231
13232 /* This is required for BDW+ where there is only one set of registers for
13233 * switching between high and low RR.
13234 * This macro can be used whenever a comparison has to be made between one
13235 * hw state and multiple sw state variables.
13236 */
13237 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13238 if (!intel_compare_link_m_n(&current_config->name, \
13239 &pipe_config->name, adjust) && \
13240 !intel_compare_link_m_n(&current_config->alt_name, \
13241 &pipe_config->name, adjust)) { \
13242 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13243 "(expected tu %i gmch %i/%i link %i/%i, " \
13244 "or tu %i gmch %i/%i link %i/%i, " \
13245 "found tu %i, gmch %i/%i link %i/%i)\n", \
13246 current_config->name.tu, \
13247 current_config->name.gmch_m, \
13248 current_config->name.gmch_n, \
13249 current_config->name.link_m, \
13250 current_config->name.link_n, \
13251 current_config->alt_name.tu, \
13252 current_config->alt_name.gmch_m, \
13253 current_config->alt_name.gmch_n, \
13254 current_config->alt_name.link_m, \
13255 current_config->alt_name.link_n, \
13256 pipe_config->name.tu, \
13257 pipe_config->name.gmch_m, \
13258 pipe_config->name.gmch_n, \
13259 pipe_config->name.link_m, \
13260 pipe_config->name.link_n); \
13261 ret = false; \
13262 }
13263
13264 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13265 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13266 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13267 "(expected %i, found %i)\n", \
13268 current_config->name & (mask), \
13269 pipe_config->name & (mask)); \
13270 ret = false; \
13271 }
13272
13273 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13274 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13275 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13276 "(expected %i, found %i)\n", \
13277 current_config->name, \
13278 pipe_config->name); \
13279 ret = false; \
13280 }
13281
13282 #define PIPE_CONF_QUIRK(quirk) \
13283 ((current_config->quirks | pipe_config->quirks) & (quirk))
13284
13285 PIPE_CONF_CHECK_I(cpu_transcoder);
13286
13287 PIPE_CONF_CHECK_I(has_pch_encoder);
13288 PIPE_CONF_CHECK_I(fdi_lanes);
13289 PIPE_CONF_CHECK_M_N(fdi_m_n);
13290
13291 PIPE_CONF_CHECK_I(lane_count);
13292 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13293
13294 if (INTEL_INFO(dev)->gen < 8) {
13295 PIPE_CONF_CHECK_M_N(dp_m_n);
13296
13297 if (current_config->has_drrs)
13298 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13299 } else
13300 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13301
13302 PIPE_CONF_CHECK_X(output_types);
13303
13304 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13305 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13306 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13310
13311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13312 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13313 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13314 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13315 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13316 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13317
13318 PIPE_CONF_CHECK_I(pixel_multiplier);
13319 PIPE_CONF_CHECK_I(has_hdmi_sink);
13320 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13321 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13322 PIPE_CONF_CHECK_I(limited_color_range);
13323 PIPE_CONF_CHECK_I(has_infoframe);
13324
13325 PIPE_CONF_CHECK_I(has_audio);
13326
13327 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13328 DRM_MODE_FLAG_INTERLACE);
13329
13330 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13331 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13332 DRM_MODE_FLAG_PHSYNC);
13333 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13334 DRM_MODE_FLAG_NHSYNC);
13335 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13336 DRM_MODE_FLAG_PVSYNC);
13337 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13338 DRM_MODE_FLAG_NVSYNC);
13339 }
13340
13341 PIPE_CONF_CHECK_X(gmch_pfit.control);
13342 /* pfit ratios are autocomputed by the hw on gen4+ */
13343 if (INTEL_INFO(dev)->gen < 4)
13344 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13345 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13346
13347 if (!adjust) {
13348 PIPE_CONF_CHECK_I(pipe_src_w);
13349 PIPE_CONF_CHECK_I(pipe_src_h);
13350
13351 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13352 if (current_config->pch_pfit.enabled) {
13353 PIPE_CONF_CHECK_X(pch_pfit.pos);
13354 PIPE_CONF_CHECK_X(pch_pfit.size);
13355 }
13356
13357 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13358 }
13359
13360 /* BDW+ don't expose a synchronous way to read the state */
13361 if (IS_HASWELL(dev))
13362 PIPE_CONF_CHECK_I(ips_enabled);
13363
13364 PIPE_CONF_CHECK_I(double_wide);
13365
13366 PIPE_CONF_CHECK_P(shared_dpll);
13367 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13368 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13369 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13370 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13371 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13372 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13373 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13374 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13375 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13376
13377 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13378 PIPE_CONF_CHECK_X(dsi_pll.div);
13379
13380 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13381 PIPE_CONF_CHECK_I(pipe_bpp);
13382
13383 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13384 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13385
13386 #undef PIPE_CONF_CHECK_X
13387 #undef PIPE_CONF_CHECK_I
13388 #undef PIPE_CONF_CHECK_P
13389 #undef PIPE_CONF_CHECK_FLAGS
13390 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13391 #undef PIPE_CONF_QUIRK
13392 #undef INTEL_ERR_OR_DBG_KMS
13393
13394 return ret;
13395 }
13396
13397 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13398 const struct intel_crtc_state *pipe_config)
13399 {
13400 if (pipe_config->has_pch_encoder) {
13401 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13402 &pipe_config->fdi_m_n);
13403 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13404
13405 /*
13406 * FDI already provided one idea for the dotclock.
13407 * Yell if the encoder disagrees.
13408 */
13409 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13410 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13411 fdi_dotclock, dotclock);
13412 }
13413 }
13414
13415 static void verify_wm_state(struct drm_crtc *crtc,
13416 struct drm_crtc_state *new_state)
13417 {
13418 struct drm_device *dev = crtc->dev;
13419 struct drm_i915_private *dev_priv = to_i915(dev);
13420 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13421 struct skl_ddb_entry *hw_entry, *sw_entry;
13422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13423 const enum pipe pipe = intel_crtc->pipe;
13424 int plane;
13425
13426 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13427 return;
13428
13429 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13430 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13431
13432 /* planes */
13433 for_each_plane(dev_priv, pipe, plane) {
13434 hw_entry = &hw_ddb.plane[pipe][plane];
13435 sw_entry = &sw_ddb->plane[pipe][plane];
13436
13437 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13438 continue;
13439
13440 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13441 "(expected (%u,%u), found (%u,%u))\n",
13442 pipe_name(pipe), plane + 1,
13443 sw_entry->start, sw_entry->end,
13444 hw_entry->start, hw_entry->end);
13445 }
13446
13447 /*
13448 * cursor
13449 * If the cursor plane isn't active, we may not have updated it's ddb
13450 * allocation. In that case since the ddb allocation will be updated
13451 * once the plane becomes visible, we can skip this check
13452 */
13453 if (intel_crtc->cursor_addr) {
13454 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13455 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13456
13457 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13458 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13459 "(expected (%u,%u), found (%u,%u))\n",
13460 pipe_name(pipe),
13461 sw_entry->start, sw_entry->end,
13462 hw_entry->start, hw_entry->end);
13463 }
13464 }
13465 }
13466
13467 static void
13468 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13469 {
13470 struct drm_connector *connector;
13471
13472 drm_for_each_connector(connector, dev) {
13473 struct drm_encoder *encoder = connector->encoder;
13474 struct drm_connector_state *state = connector->state;
13475
13476 if (state->crtc != crtc)
13477 continue;
13478
13479 intel_connector_verify_state(to_intel_connector(connector));
13480
13481 I915_STATE_WARN(state->best_encoder != encoder,
13482 "connector's atomic encoder doesn't match legacy encoder\n");
13483 }
13484 }
13485
13486 static void
13487 verify_encoder_state(struct drm_device *dev)
13488 {
13489 struct intel_encoder *encoder;
13490 struct intel_connector *connector;
13491
13492 for_each_intel_encoder(dev, encoder) {
13493 bool enabled = false;
13494 enum pipe pipe;
13495
13496 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13497 encoder->base.base.id,
13498 encoder->base.name);
13499
13500 for_each_intel_connector(dev, connector) {
13501 if (connector->base.state->best_encoder != &encoder->base)
13502 continue;
13503 enabled = true;
13504
13505 I915_STATE_WARN(connector->base.state->crtc !=
13506 encoder->base.crtc,
13507 "connector's crtc doesn't match encoder crtc\n");
13508 }
13509
13510 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13511 "encoder's enabled state mismatch "
13512 "(expected %i, found %i)\n",
13513 !!encoder->base.crtc, enabled);
13514
13515 if (!encoder->base.crtc) {
13516 bool active;
13517
13518 active = encoder->get_hw_state(encoder, &pipe);
13519 I915_STATE_WARN(active,
13520 "encoder detached but still enabled on pipe %c.\n",
13521 pipe_name(pipe));
13522 }
13523 }
13524 }
13525
13526 static void
13527 verify_crtc_state(struct drm_crtc *crtc,
13528 struct drm_crtc_state *old_crtc_state,
13529 struct drm_crtc_state *new_crtc_state)
13530 {
13531 struct drm_device *dev = crtc->dev;
13532 struct drm_i915_private *dev_priv = to_i915(dev);
13533 struct intel_encoder *encoder;
13534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13535 struct intel_crtc_state *pipe_config, *sw_config;
13536 struct drm_atomic_state *old_state;
13537 bool active;
13538
13539 old_state = old_crtc_state->state;
13540 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13541 pipe_config = to_intel_crtc_state(old_crtc_state);
13542 memset(pipe_config, 0, sizeof(*pipe_config));
13543 pipe_config->base.crtc = crtc;
13544 pipe_config->base.state = old_state;
13545
13546 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13547
13548 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13549
13550 /* hw state is inconsistent with the pipe quirk */
13551 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13552 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13553 active = new_crtc_state->active;
13554
13555 I915_STATE_WARN(new_crtc_state->active != active,
13556 "crtc active state doesn't match with hw state "
13557 "(expected %i, found %i)\n", new_crtc_state->active, active);
13558
13559 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13560 "transitional active state does not match atomic hw state "
13561 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13562
13563 for_each_encoder_on_crtc(dev, crtc, encoder) {
13564 enum pipe pipe;
13565
13566 active = encoder->get_hw_state(encoder, &pipe);
13567 I915_STATE_WARN(active != new_crtc_state->active,
13568 "[ENCODER:%i] active %i with crtc active %i\n",
13569 encoder->base.base.id, active, new_crtc_state->active);
13570
13571 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13572 "Encoder connected to wrong pipe %c\n",
13573 pipe_name(pipe));
13574
13575 if (active) {
13576 pipe_config->output_types |= 1 << encoder->type;
13577 encoder->get_config(encoder, pipe_config);
13578 }
13579 }
13580
13581 if (!new_crtc_state->active)
13582 return;
13583
13584 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13585
13586 sw_config = to_intel_crtc_state(crtc->state);
13587 if (!intel_pipe_config_compare(dev, sw_config,
13588 pipe_config, false)) {
13589 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13590 intel_dump_pipe_config(intel_crtc, pipe_config,
13591 "[hw state]");
13592 intel_dump_pipe_config(intel_crtc, sw_config,
13593 "[sw state]");
13594 }
13595 }
13596
13597 static void
13598 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13599 struct intel_shared_dpll *pll,
13600 struct drm_crtc *crtc,
13601 struct drm_crtc_state *new_state)
13602 {
13603 struct intel_dpll_hw_state dpll_hw_state;
13604 unsigned crtc_mask;
13605 bool active;
13606
13607 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13608
13609 DRM_DEBUG_KMS("%s\n", pll->name);
13610
13611 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13612
13613 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13614 I915_STATE_WARN(!pll->on && pll->active_mask,
13615 "pll in active use but not on in sw tracking\n");
13616 I915_STATE_WARN(pll->on && !pll->active_mask,
13617 "pll is on but not used by any active crtc\n");
13618 I915_STATE_WARN(pll->on != active,
13619 "pll on state mismatch (expected %i, found %i)\n",
13620 pll->on, active);
13621 }
13622
13623 if (!crtc) {
13624 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13625 "more active pll users than references: %x vs %x\n",
13626 pll->active_mask, pll->config.crtc_mask);
13627
13628 return;
13629 }
13630
13631 crtc_mask = 1 << drm_crtc_index(crtc);
13632
13633 if (new_state->active)
13634 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13635 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13636 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13637 else
13638 I915_STATE_WARN(pll->active_mask & crtc_mask,
13639 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13640 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13641
13642 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13643 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13644 crtc_mask, pll->config.crtc_mask);
13645
13646 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13647 &dpll_hw_state,
13648 sizeof(dpll_hw_state)),
13649 "pll hw state mismatch\n");
13650 }
13651
13652 static void
13653 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13654 struct drm_crtc_state *old_crtc_state,
13655 struct drm_crtc_state *new_crtc_state)
13656 {
13657 struct drm_i915_private *dev_priv = to_i915(dev);
13658 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13659 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13660
13661 if (new_state->shared_dpll)
13662 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13663
13664 if (old_state->shared_dpll &&
13665 old_state->shared_dpll != new_state->shared_dpll) {
13666 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13667 struct intel_shared_dpll *pll = old_state->shared_dpll;
13668
13669 I915_STATE_WARN(pll->active_mask & crtc_mask,
13670 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13671 pipe_name(drm_crtc_index(crtc)));
13672 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13673 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13674 pipe_name(drm_crtc_index(crtc)));
13675 }
13676 }
13677
13678 static void
13679 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13680 struct drm_crtc_state *old_state,
13681 struct drm_crtc_state *new_state)
13682 {
13683 if (!needs_modeset(new_state) &&
13684 !to_intel_crtc_state(new_state)->update_pipe)
13685 return;
13686
13687 verify_wm_state(crtc, new_state);
13688 verify_connector_state(crtc->dev, crtc);
13689 verify_crtc_state(crtc, old_state, new_state);
13690 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13691 }
13692
13693 static void
13694 verify_disabled_dpll_state(struct drm_device *dev)
13695 {
13696 struct drm_i915_private *dev_priv = to_i915(dev);
13697 int i;
13698
13699 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13700 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13701 }
13702
13703 static void
13704 intel_modeset_verify_disabled(struct drm_device *dev)
13705 {
13706 verify_encoder_state(dev);
13707 verify_connector_state(dev, NULL);
13708 verify_disabled_dpll_state(dev);
13709 }
13710
13711 static void update_scanline_offset(struct intel_crtc *crtc)
13712 {
13713 struct drm_device *dev = crtc->base.dev;
13714
13715 /*
13716 * The scanline counter increments at the leading edge of hsync.
13717 *
13718 * On most platforms it starts counting from vtotal-1 on the
13719 * first active line. That means the scanline counter value is
13720 * always one less than what we would expect. Ie. just after
13721 * start of vblank, which also occurs at start of hsync (on the
13722 * last active line), the scanline counter will read vblank_start-1.
13723 *
13724 * On gen2 the scanline counter starts counting from 1 instead
13725 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13726 * to keep the value positive), instead of adding one.
13727 *
13728 * On HSW+ the behaviour of the scanline counter depends on the output
13729 * type. For DP ports it behaves like most other platforms, but on HDMI
13730 * there's an extra 1 line difference. So we need to add two instead of
13731 * one to the value.
13732 */
13733 if (IS_GEN2(dev)) {
13734 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13735 int vtotal;
13736
13737 vtotal = adjusted_mode->crtc_vtotal;
13738 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13739 vtotal /= 2;
13740
13741 crtc->scanline_offset = vtotal - 1;
13742 } else if (HAS_DDI(dev) &&
13743 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13744 crtc->scanline_offset = 2;
13745 } else
13746 crtc->scanline_offset = 1;
13747 }
13748
13749 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13750 {
13751 struct drm_device *dev = state->dev;
13752 struct drm_i915_private *dev_priv = to_i915(dev);
13753 struct intel_shared_dpll_config *shared_dpll = NULL;
13754 struct drm_crtc *crtc;
13755 struct drm_crtc_state *crtc_state;
13756 int i;
13757
13758 if (!dev_priv->display.crtc_compute_clock)
13759 return;
13760
13761 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13763 struct intel_shared_dpll *old_dpll =
13764 to_intel_crtc_state(crtc->state)->shared_dpll;
13765
13766 if (!needs_modeset(crtc_state))
13767 continue;
13768
13769 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13770
13771 if (!old_dpll)
13772 continue;
13773
13774 if (!shared_dpll)
13775 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13776
13777 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13778 }
13779 }
13780
13781 /*
13782 * This implements the workaround described in the "notes" section of the mode
13783 * set sequence documentation. When going from no pipes or single pipe to
13784 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13785 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13786 */
13787 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13788 {
13789 struct drm_crtc_state *crtc_state;
13790 struct intel_crtc *intel_crtc;
13791 struct drm_crtc *crtc;
13792 struct intel_crtc_state *first_crtc_state = NULL;
13793 struct intel_crtc_state *other_crtc_state = NULL;
13794 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13795 int i;
13796
13797 /* look at all crtc's that are going to be enabled in during modeset */
13798 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13799 intel_crtc = to_intel_crtc(crtc);
13800
13801 if (!crtc_state->active || !needs_modeset(crtc_state))
13802 continue;
13803
13804 if (first_crtc_state) {
13805 other_crtc_state = to_intel_crtc_state(crtc_state);
13806 break;
13807 } else {
13808 first_crtc_state = to_intel_crtc_state(crtc_state);
13809 first_pipe = intel_crtc->pipe;
13810 }
13811 }
13812
13813 /* No workaround needed? */
13814 if (!first_crtc_state)
13815 return 0;
13816
13817 /* w/a possibly needed, check how many crtc's are already enabled. */
13818 for_each_intel_crtc(state->dev, intel_crtc) {
13819 struct intel_crtc_state *pipe_config;
13820
13821 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13822 if (IS_ERR(pipe_config))
13823 return PTR_ERR(pipe_config);
13824
13825 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13826
13827 if (!pipe_config->base.active ||
13828 needs_modeset(&pipe_config->base))
13829 continue;
13830
13831 /* 2 or more enabled crtcs means no need for w/a */
13832 if (enabled_pipe != INVALID_PIPE)
13833 return 0;
13834
13835 enabled_pipe = intel_crtc->pipe;
13836 }
13837
13838 if (enabled_pipe != INVALID_PIPE)
13839 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13840 else if (other_crtc_state)
13841 other_crtc_state->hsw_workaround_pipe = first_pipe;
13842
13843 return 0;
13844 }
13845
13846 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13847 {
13848 struct drm_crtc *crtc;
13849 struct drm_crtc_state *crtc_state;
13850 int ret = 0;
13851
13852 /* add all active pipes to the state */
13853 for_each_crtc(state->dev, crtc) {
13854 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13855 if (IS_ERR(crtc_state))
13856 return PTR_ERR(crtc_state);
13857
13858 if (!crtc_state->active || needs_modeset(crtc_state))
13859 continue;
13860
13861 crtc_state->mode_changed = true;
13862
13863 ret = drm_atomic_add_affected_connectors(state, crtc);
13864 if (ret)
13865 break;
13866
13867 ret = drm_atomic_add_affected_planes(state, crtc);
13868 if (ret)
13869 break;
13870 }
13871
13872 return ret;
13873 }
13874
13875 static int intel_modeset_checks(struct drm_atomic_state *state)
13876 {
13877 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13878 struct drm_i915_private *dev_priv = to_i915(state->dev);
13879 struct drm_crtc *crtc;
13880 struct drm_crtc_state *crtc_state;
13881 int ret = 0, i;
13882
13883 if (!check_digital_port_conflicts(state)) {
13884 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13885 return -EINVAL;
13886 }
13887
13888 intel_state->modeset = true;
13889 intel_state->active_crtcs = dev_priv->active_crtcs;
13890
13891 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13892 if (crtc_state->active)
13893 intel_state->active_crtcs |= 1 << i;
13894 else
13895 intel_state->active_crtcs &= ~(1 << i);
13896
13897 if (crtc_state->active != crtc->state->active)
13898 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13899 }
13900
13901 /*
13902 * See if the config requires any additional preparation, e.g.
13903 * to adjust global state with pipes off. We need to do this
13904 * here so we can get the modeset_pipe updated config for the new
13905 * mode set on this crtc. For other crtcs we need to use the
13906 * adjusted_mode bits in the crtc directly.
13907 */
13908 if (dev_priv->display.modeset_calc_cdclk) {
13909 if (!intel_state->cdclk_pll_vco)
13910 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13911 if (!intel_state->cdclk_pll_vco)
13912 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13913
13914 ret = dev_priv->display.modeset_calc_cdclk(state);
13915 if (ret < 0)
13916 return ret;
13917
13918 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13919 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13920 ret = intel_modeset_all_pipes(state);
13921
13922 if (ret < 0)
13923 return ret;
13924
13925 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13926 intel_state->cdclk, intel_state->dev_cdclk);
13927 } else
13928 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13929
13930 intel_modeset_clear_plls(state);
13931
13932 if (IS_HASWELL(dev_priv))
13933 return haswell_mode_set_planes_workaround(state);
13934
13935 return 0;
13936 }
13937
13938 /*
13939 * Handle calculation of various watermark data at the end of the atomic check
13940 * phase. The code here should be run after the per-crtc and per-plane 'check'
13941 * handlers to ensure that all derived state has been updated.
13942 */
13943 static int calc_watermark_data(struct drm_atomic_state *state)
13944 {
13945 struct drm_device *dev = state->dev;
13946 struct drm_i915_private *dev_priv = to_i915(dev);
13947
13948 /* Is there platform-specific watermark information to calculate? */
13949 if (dev_priv->display.compute_global_watermarks)
13950 return dev_priv->display.compute_global_watermarks(state);
13951
13952 return 0;
13953 }
13954
13955 /**
13956 * intel_atomic_check - validate state object
13957 * @dev: drm device
13958 * @state: state to validate
13959 */
13960 static int intel_atomic_check(struct drm_device *dev,
13961 struct drm_atomic_state *state)
13962 {
13963 struct drm_i915_private *dev_priv = to_i915(dev);
13964 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13965 struct drm_crtc *crtc;
13966 struct drm_crtc_state *crtc_state;
13967 int ret, i;
13968 bool any_ms = false;
13969
13970 ret = drm_atomic_helper_check_modeset(dev, state);
13971 if (ret)
13972 return ret;
13973
13974 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13975 struct intel_crtc_state *pipe_config =
13976 to_intel_crtc_state(crtc_state);
13977
13978 /* Catch I915_MODE_FLAG_INHERITED */
13979 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13980 crtc_state->mode_changed = true;
13981
13982 if (!needs_modeset(crtc_state))
13983 continue;
13984
13985 if (!crtc_state->enable) {
13986 any_ms = true;
13987 continue;
13988 }
13989
13990 /* FIXME: For only active_changed we shouldn't need to do any
13991 * state recomputation at all. */
13992
13993 ret = drm_atomic_add_affected_connectors(state, crtc);
13994 if (ret)
13995 return ret;
13996
13997 ret = intel_modeset_pipe_config(crtc, pipe_config);
13998 if (ret) {
13999 intel_dump_pipe_config(to_intel_crtc(crtc),
14000 pipe_config, "[failed]");
14001 return ret;
14002 }
14003
14004 if (i915.fastboot &&
14005 intel_pipe_config_compare(dev,
14006 to_intel_crtc_state(crtc->state),
14007 pipe_config, true)) {
14008 crtc_state->mode_changed = false;
14009 to_intel_crtc_state(crtc_state)->update_pipe = true;
14010 }
14011
14012 if (needs_modeset(crtc_state))
14013 any_ms = true;
14014
14015 ret = drm_atomic_add_affected_planes(state, crtc);
14016 if (ret)
14017 return ret;
14018
14019 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14020 needs_modeset(crtc_state) ?
14021 "[modeset]" : "[fastset]");
14022 }
14023
14024 if (any_ms) {
14025 ret = intel_modeset_checks(state);
14026
14027 if (ret)
14028 return ret;
14029 } else
14030 intel_state->cdclk = dev_priv->cdclk_freq;
14031
14032 ret = drm_atomic_helper_check_planes(dev, state);
14033 if (ret)
14034 return ret;
14035
14036 intel_fbc_choose_crtc(dev_priv, state);
14037 return calc_watermark_data(state);
14038 }
14039
14040 static int intel_atomic_prepare_commit(struct drm_device *dev,
14041 struct drm_atomic_state *state,
14042 bool nonblock)
14043 {
14044 struct drm_i915_private *dev_priv = to_i915(dev);
14045 struct drm_plane_state *plane_state;
14046 struct drm_crtc_state *crtc_state;
14047 struct drm_plane *plane;
14048 struct drm_crtc *crtc;
14049 int i, ret;
14050
14051 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14052 if (state->legacy_cursor_update)
14053 continue;
14054
14055 ret = intel_crtc_wait_for_pending_flips(crtc);
14056 if (ret)
14057 return ret;
14058
14059 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14060 flush_workqueue(dev_priv->wq);
14061 }
14062
14063 ret = mutex_lock_interruptible(&dev->struct_mutex);
14064 if (ret)
14065 return ret;
14066
14067 ret = drm_atomic_helper_prepare_planes(dev, state);
14068 mutex_unlock(&dev->struct_mutex);
14069
14070 if (!ret && !nonblock) {
14071 for_each_plane_in_state(state, plane, plane_state, i) {
14072 struct intel_plane_state *intel_plane_state =
14073 to_intel_plane_state(plane_state);
14074
14075 if (!intel_plane_state->wait_req)
14076 continue;
14077
14078 ret = i915_wait_request(intel_plane_state->wait_req,
14079 I915_WAIT_INTERRUPTIBLE,
14080 NULL, NULL);
14081 if (ret) {
14082 /* Any hang should be swallowed by the wait */
14083 WARN_ON(ret == -EIO);
14084 mutex_lock(&dev->struct_mutex);
14085 drm_atomic_helper_cleanup_planes(dev, state);
14086 mutex_unlock(&dev->struct_mutex);
14087 break;
14088 }
14089 }
14090 }
14091
14092 return ret;
14093 }
14094
14095 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14096 {
14097 struct drm_device *dev = crtc->base.dev;
14098
14099 if (!dev->max_vblank_count)
14100 return drm_accurate_vblank_count(&crtc->base);
14101
14102 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14103 }
14104
14105 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14106 struct drm_i915_private *dev_priv,
14107 unsigned crtc_mask)
14108 {
14109 unsigned last_vblank_count[I915_MAX_PIPES];
14110 enum pipe pipe;
14111 int ret;
14112
14113 if (!crtc_mask)
14114 return;
14115
14116 for_each_pipe(dev_priv, pipe) {
14117 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14118
14119 if (!((1 << pipe) & crtc_mask))
14120 continue;
14121
14122 ret = drm_crtc_vblank_get(crtc);
14123 if (WARN_ON(ret != 0)) {
14124 crtc_mask &= ~(1 << pipe);
14125 continue;
14126 }
14127
14128 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14129 }
14130
14131 for_each_pipe(dev_priv, pipe) {
14132 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14133 long lret;
14134
14135 if (!((1 << pipe) & crtc_mask))
14136 continue;
14137
14138 lret = wait_event_timeout(dev->vblank[pipe].queue,
14139 last_vblank_count[pipe] !=
14140 drm_crtc_vblank_count(crtc),
14141 msecs_to_jiffies(50));
14142
14143 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14144
14145 drm_crtc_vblank_put(crtc);
14146 }
14147 }
14148
14149 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14150 {
14151 /* fb updated, need to unpin old fb */
14152 if (crtc_state->fb_changed)
14153 return true;
14154
14155 /* wm changes, need vblank before final wm's */
14156 if (crtc_state->update_wm_post)
14157 return true;
14158
14159 /*
14160 * cxsr is re-enabled after vblank.
14161 * This is already handled by crtc_state->update_wm_post,
14162 * but added for clarity.
14163 */
14164 if (crtc_state->disable_cxsr)
14165 return true;
14166
14167 return false;
14168 }
14169
14170 static void intel_update_crtc(struct drm_crtc *crtc,
14171 struct drm_atomic_state *state,
14172 struct drm_crtc_state *old_crtc_state,
14173 unsigned int *crtc_vblank_mask)
14174 {
14175 struct drm_device *dev = crtc->dev;
14176 struct drm_i915_private *dev_priv = to_i915(dev);
14177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14178 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14179 bool modeset = needs_modeset(crtc->state);
14180
14181 if (modeset) {
14182 update_scanline_offset(intel_crtc);
14183 dev_priv->display.crtc_enable(pipe_config, state);
14184 } else {
14185 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14186 }
14187
14188 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14189 intel_fbc_enable(
14190 intel_crtc, pipe_config,
14191 to_intel_plane_state(crtc->primary->state));
14192 }
14193
14194 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14195
14196 if (needs_vblank_wait(pipe_config))
14197 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14198 }
14199
14200 static void intel_update_crtcs(struct drm_atomic_state *state,
14201 unsigned int *crtc_vblank_mask)
14202 {
14203 struct drm_crtc *crtc;
14204 struct drm_crtc_state *old_crtc_state;
14205 int i;
14206
14207 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14208 if (!crtc->state->active)
14209 continue;
14210
14211 intel_update_crtc(crtc, state, old_crtc_state,
14212 crtc_vblank_mask);
14213 }
14214 }
14215
14216 static void skl_update_crtcs(struct drm_atomic_state *state,
14217 unsigned int *crtc_vblank_mask)
14218 {
14219 struct drm_device *dev = state->dev;
14220 struct drm_i915_private *dev_priv = to_i915(dev);
14221 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14222 struct drm_crtc *crtc;
14223 struct drm_crtc_state *old_crtc_state;
14224 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14225 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14226 unsigned int updated = 0;
14227 bool progress;
14228 enum pipe pipe;
14229
14230 /*
14231 * Whenever the number of active pipes changes, we need to make sure we
14232 * update the pipes in the right order so that their ddb allocations
14233 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14234 * cause pipe underruns and other bad stuff.
14235 */
14236 do {
14237 int i;
14238 progress = false;
14239
14240 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14241 bool vbl_wait = false;
14242 unsigned int cmask = drm_crtc_mask(crtc);
14243 pipe = to_intel_crtc(crtc)->pipe;
14244
14245 if (updated & cmask || !crtc->state->active)
14246 continue;
14247 if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14248 pipe))
14249 continue;
14250
14251 updated |= cmask;
14252
14253 /*
14254 * If this is an already active pipe, it's DDB changed,
14255 * and this isn't the last pipe that needs updating
14256 * then we need to wait for a vblank to pass for the
14257 * new ddb allocation to take effect.
14258 */
14259 if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14260 !crtc->state->active_changed &&
14261 intel_state->wm_results.dirty_pipes != updated)
14262 vbl_wait = true;
14263
14264 intel_update_crtc(crtc, state, old_crtc_state,
14265 crtc_vblank_mask);
14266
14267 if (vbl_wait)
14268 intel_wait_for_vblank(dev, pipe);
14269
14270 progress = true;
14271 }
14272 } while (progress);
14273 }
14274
14275 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14276 {
14277 struct drm_device *dev = state->dev;
14278 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14279 struct drm_i915_private *dev_priv = to_i915(dev);
14280 struct drm_crtc_state *old_crtc_state;
14281 struct drm_crtc *crtc;
14282 struct intel_crtc_state *intel_cstate;
14283 struct drm_plane *plane;
14284 struct drm_plane_state *plane_state;
14285 bool hw_check = intel_state->modeset;
14286 unsigned long put_domains[I915_MAX_PIPES] = {};
14287 unsigned crtc_vblank_mask = 0;
14288 int i, ret;
14289
14290 for_each_plane_in_state(state, plane, plane_state, i) {
14291 struct intel_plane_state *intel_plane_state =
14292 to_intel_plane_state(plane_state);
14293
14294 if (!intel_plane_state->wait_req)
14295 continue;
14296
14297 ret = i915_wait_request(intel_plane_state->wait_req,
14298 0, NULL, NULL);
14299 /* EIO should be eaten, and we can't get interrupted in the
14300 * worker, and blocking commits have waited already. */
14301 WARN_ON(ret);
14302 }
14303
14304 drm_atomic_helper_wait_for_dependencies(state);
14305
14306 if (intel_state->modeset) {
14307 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14308 sizeof(intel_state->min_pixclk));
14309 dev_priv->active_crtcs = intel_state->active_crtcs;
14310 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14311
14312 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14313 }
14314
14315 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14317
14318 if (needs_modeset(crtc->state) ||
14319 to_intel_crtc_state(crtc->state)->update_pipe) {
14320 hw_check = true;
14321
14322 put_domains[to_intel_crtc(crtc)->pipe] =
14323 modeset_get_crtc_power_domains(crtc,
14324 to_intel_crtc_state(crtc->state));
14325 }
14326
14327 if (!needs_modeset(crtc->state))
14328 continue;
14329
14330 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14331
14332 if (old_crtc_state->active) {
14333 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14334 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14335 intel_crtc->active = false;
14336 intel_fbc_disable(intel_crtc);
14337 intel_disable_shared_dpll(intel_crtc);
14338
14339 /*
14340 * Underruns don't always raise
14341 * interrupts, so check manually.
14342 */
14343 intel_check_cpu_fifo_underruns(dev_priv);
14344 intel_check_pch_fifo_underruns(dev_priv);
14345
14346 if (!crtc->state->active)
14347 intel_update_watermarks(crtc);
14348 }
14349 }
14350
14351 /* Only after disabling all output pipelines that will be changed can we
14352 * update the the output configuration. */
14353 intel_modeset_update_crtc_state(state);
14354
14355 if (intel_state->modeset) {
14356 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14357
14358 if (dev_priv->display.modeset_commit_cdclk &&
14359 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14360 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14361 dev_priv->display.modeset_commit_cdclk(state);
14362
14363 /*
14364 * SKL workaround: bspec recommends we disable the SAGV when we
14365 * have more then one pipe enabled
14366 */
14367 if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
14368 skl_disable_sagv(dev_priv);
14369
14370 intel_modeset_verify_disabled(dev);
14371 }
14372
14373 /* Complete the events for pipes that have now been disabled */
14374 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14375 bool modeset = needs_modeset(crtc->state);
14376
14377 /* Complete events for now disable pipes here. */
14378 if (modeset && !crtc->state->active && crtc->state->event) {
14379 spin_lock_irq(&dev->event_lock);
14380 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14381 spin_unlock_irq(&dev->event_lock);
14382
14383 crtc->state->event = NULL;
14384 }
14385 }
14386
14387 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14388 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14389
14390 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14391 * already, but still need the state for the delayed optimization. To
14392 * fix this:
14393 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14394 * - schedule that vblank worker _before_ calling hw_done
14395 * - at the start of commit_tail, cancel it _synchrously
14396 * - switch over to the vblank wait helper in the core after that since
14397 * we don't need out special handling any more.
14398 */
14399 if (!state->legacy_cursor_update)
14400 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14401
14402 /*
14403 * Now that the vblank has passed, we can go ahead and program the
14404 * optimal watermarks on platforms that need two-step watermark
14405 * programming.
14406 *
14407 * TODO: Move this (and other cleanup) to an async worker eventually.
14408 */
14409 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14410 intel_cstate = to_intel_crtc_state(crtc->state);
14411
14412 if (dev_priv->display.optimize_watermarks)
14413 dev_priv->display.optimize_watermarks(intel_cstate);
14414 }
14415
14416 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14417 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14418
14419 if (put_domains[i])
14420 modeset_put_power_domains(dev_priv, put_domains[i]);
14421
14422 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14423 }
14424
14425 if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
14426 skl_can_enable_sagv(state))
14427 skl_enable_sagv(dev_priv);
14428
14429 drm_atomic_helper_commit_hw_done(state);
14430
14431 if (intel_state->modeset)
14432 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14433
14434 mutex_lock(&dev->struct_mutex);
14435 drm_atomic_helper_cleanup_planes(dev, state);
14436 mutex_unlock(&dev->struct_mutex);
14437
14438 drm_atomic_helper_commit_cleanup_done(state);
14439
14440 drm_atomic_state_free(state);
14441
14442 /* As one of the primary mmio accessors, KMS has a high likelihood
14443 * of triggering bugs in unclaimed access. After we finish
14444 * modesetting, see if an error has been flagged, and if so
14445 * enable debugging for the next modeset - and hope we catch
14446 * the culprit.
14447 *
14448 * XXX note that we assume display power is on at this point.
14449 * This might hold true now but we need to add pm helper to check
14450 * unclaimed only when the hardware is on, as atomic commits
14451 * can happen also when the device is completely off.
14452 */
14453 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14454 }
14455
14456 static void intel_atomic_commit_work(struct work_struct *work)
14457 {
14458 struct drm_atomic_state *state = container_of(work,
14459 struct drm_atomic_state,
14460 commit_work);
14461 intel_atomic_commit_tail(state);
14462 }
14463
14464 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14465 {
14466 struct drm_plane_state *old_plane_state;
14467 struct drm_plane *plane;
14468 int i;
14469
14470 for_each_plane_in_state(state, plane, old_plane_state, i)
14471 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14472 intel_fb_obj(plane->state->fb),
14473 to_intel_plane(plane)->frontbuffer_bit);
14474 }
14475
14476 /**
14477 * intel_atomic_commit - commit validated state object
14478 * @dev: DRM device
14479 * @state: the top-level driver state object
14480 * @nonblock: nonblocking commit
14481 *
14482 * This function commits a top-level state object that has been validated
14483 * with drm_atomic_helper_check().
14484 *
14485 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14486 * nonblocking commits are only safe for pure plane updates. Everything else
14487 * should work though.
14488 *
14489 * RETURNS
14490 * Zero for success or -errno.
14491 */
14492 static int intel_atomic_commit(struct drm_device *dev,
14493 struct drm_atomic_state *state,
14494 bool nonblock)
14495 {
14496 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14497 struct drm_i915_private *dev_priv = to_i915(dev);
14498 int ret = 0;
14499
14500 if (intel_state->modeset && nonblock) {
14501 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14502 return -EINVAL;
14503 }
14504
14505 ret = drm_atomic_helper_setup_commit(state, nonblock);
14506 if (ret)
14507 return ret;
14508
14509 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14510
14511 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14512 if (ret) {
14513 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14514 return ret;
14515 }
14516
14517 drm_atomic_helper_swap_state(state, true);
14518 dev_priv->wm.distrust_bios_wm = false;
14519 dev_priv->wm.skl_results = intel_state->wm_results;
14520 intel_shared_dpll_commit(state);
14521 intel_atomic_track_fbs(state);
14522
14523 if (nonblock)
14524 queue_work(system_unbound_wq, &state->commit_work);
14525 else
14526 intel_atomic_commit_tail(state);
14527
14528 return 0;
14529 }
14530
14531 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14532 {
14533 struct drm_device *dev = crtc->dev;
14534 struct drm_atomic_state *state;
14535 struct drm_crtc_state *crtc_state;
14536 int ret;
14537
14538 state = drm_atomic_state_alloc(dev);
14539 if (!state) {
14540 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14541 crtc->base.id, crtc->name);
14542 return;
14543 }
14544
14545 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14546
14547 retry:
14548 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14549 ret = PTR_ERR_OR_ZERO(crtc_state);
14550 if (!ret) {
14551 if (!crtc_state->active)
14552 goto out;
14553
14554 crtc_state->mode_changed = true;
14555 ret = drm_atomic_commit(state);
14556 }
14557
14558 if (ret == -EDEADLK) {
14559 drm_atomic_state_clear(state);
14560 drm_modeset_backoff(state->acquire_ctx);
14561 goto retry;
14562 }
14563
14564 if (ret)
14565 out:
14566 drm_atomic_state_free(state);
14567 }
14568
14569 /*
14570 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14571 * drm_atomic_helper_legacy_gamma_set() directly.
14572 */
14573 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14574 u16 *red, u16 *green, u16 *blue,
14575 uint32_t size)
14576 {
14577 struct drm_device *dev = crtc->dev;
14578 struct drm_mode_config *config = &dev->mode_config;
14579 struct drm_crtc_state *state;
14580 int ret;
14581
14582 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14583 if (ret)
14584 return ret;
14585
14586 /*
14587 * Make sure we update the legacy properties so this works when
14588 * atomic is not enabled.
14589 */
14590
14591 state = crtc->state;
14592
14593 drm_object_property_set_value(&crtc->base,
14594 config->degamma_lut_property,
14595 (state->degamma_lut) ?
14596 state->degamma_lut->base.id : 0);
14597
14598 drm_object_property_set_value(&crtc->base,
14599 config->ctm_property,
14600 (state->ctm) ?
14601 state->ctm->base.id : 0);
14602
14603 drm_object_property_set_value(&crtc->base,
14604 config->gamma_lut_property,
14605 (state->gamma_lut) ?
14606 state->gamma_lut->base.id : 0);
14607
14608 return 0;
14609 }
14610
14611 static const struct drm_crtc_funcs intel_crtc_funcs = {
14612 .gamma_set = intel_atomic_legacy_gamma_set,
14613 .set_config = drm_atomic_helper_set_config,
14614 .set_property = drm_atomic_helper_crtc_set_property,
14615 .destroy = intel_crtc_destroy,
14616 .page_flip = intel_crtc_page_flip,
14617 .atomic_duplicate_state = intel_crtc_duplicate_state,
14618 .atomic_destroy_state = intel_crtc_destroy_state,
14619 };
14620
14621 /**
14622 * intel_prepare_plane_fb - Prepare fb for usage on plane
14623 * @plane: drm plane to prepare for
14624 * @fb: framebuffer to prepare for presentation
14625 *
14626 * Prepares a framebuffer for usage on a display plane. Generally this
14627 * involves pinning the underlying object and updating the frontbuffer tracking
14628 * bits. Some older platforms need special physical address handling for
14629 * cursor planes.
14630 *
14631 * Must be called with struct_mutex held.
14632 *
14633 * Returns 0 on success, negative error code on failure.
14634 */
14635 int
14636 intel_prepare_plane_fb(struct drm_plane *plane,
14637 struct drm_plane_state *new_state)
14638 {
14639 struct drm_device *dev = plane->dev;
14640 struct drm_framebuffer *fb = new_state->fb;
14641 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14642 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14643 struct reservation_object *resv;
14644 int ret = 0;
14645
14646 if (!obj && !old_obj)
14647 return 0;
14648
14649 if (old_obj) {
14650 struct drm_crtc_state *crtc_state =
14651 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14652
14653 /* Big Hammer, we also need to ensure that any pending
14654 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14655 * current scanout is retired before unpinning the old
14656 * framebuffer. Note that we rely on userspace rendering
14657 * into the buffer attached to the pipe they are waiting
14658 * on. If not, userspace generates a GPU hang with IPEHR
14659 * point to the MI_WAIT_FOR_EVENT.
14660 *
14661 * This should only fail upon a hung GPU, in which case we
14662 * can safely continue.
14663 */
14664 if (needs_modeset(crtc_state))
14665 ret = i915_gem_object_wait_rendering(old_obj, true);
14666 if (ret) {
14667 /* GPU hangs should have been swallowed by the wait */
14668 WARN_ON(ret == -EIO);
14669 return ret;
14670 }
14671 }
14672
14673 if (!obj)
14674 return 0;
14675
14676 /* For framebuffer backed by dmabuf, wait for fence */
14677 resv = i915_gem_object_get_dmabuf_resv(obj);
14678 if (resv) {
14679 long lret;
14680
14681 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14682 MAX_SCHEDULE_TIMEOUT);
14683 if (lret == -ERESTARTSYS)
14684 return lret;
14685
14686 WARN(lret < 0, "waiting returns %li\n", lret);
14687 }
14688
14689 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14690 INTEL_INFO(dev)->cursor_needs_physical) {
14691 int align = IS_I830(dev) ? 16 * 1024 : 256;
14692 ret = i915_gem_object_attach_phys(obj, align);
14693 if (ret)
14694 DRM_DEBUG_KMS("failed to attach phys object\n");
14695 } else {
14696 struct i915_vma *vma;
14697
14698 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14699 if (IS_ERR(vma))
14700 ret = PTR_ERR(vma);
14701 }
14702
14703 if (ret == 0) {
14704 to_intel_plane_state(new_state)->wait_req =
14705 i915_gem_active_get(&obj->last_write,
14706 &obj->base.dev->struct_mutex);
14707 }
14708
14709 return ret;
14710 }
14711
14712 /**
14713 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14714 * @plane: drm plane to clean up for
14715 * @fb: old framebuffer that was on plane
14716 *
14717 * Cleans up a framebuffer that has just been removed from a plane.
14718 *
14719 * Must be called with struct_mutex held.
14720 */
14721 void
14722 intel_cleanup_plane_fb(struct drm_plane *plane,
14723 struct drm_plane_state *old_state)
14724 {
14725 struct drm_device *dev = plane->dev;
14726 struct intel_plane_state *old_intel_state;
14727 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14728 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14729 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14730
14731 old_intel_state = to_intel_plane_state(old_state);
14732
14733 if (!obj && !old_obj)
14734 return;
14735
14736 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14737 !INTEL_INFO(dev)->cursor_needs_physical))
14738 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14739
14740 i915_gem_request_assign(&intel_state->wait_req, NULL);
14741 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14742 }
14743
14744 int
14745 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14746 {
14747 int max_scale;
14748 int crtc_clock, cdclk;
14749
14750 if (!intel_crtc || !crtc_state->base.enable)
14751 return DRM_PLANE_HELPER_NO_SCALING;
14752
14753 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14754 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14755
14756 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14757 return DRM_PLANE_HELPER_NO_SCALING;
14758
14759 /*
14760 * skl max scale is lower of:
14761 * close to 3 but not 3, -1 is for that purpose
14762 * or
14763 * cdclk/crtc_clock
14764 */
14765 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14766
14767 return max_scale;
14768 }
14769
14770 static int
14771 intel_check_primary_plane(struct drm_plane *plane,
14772 struct intel_crtc_state *crtc_state,
14773 struct intel_plane_state *state)
14774 {
14775 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14776 struct drm_crtc *crtc = state->base.crtc;
14777 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14778 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14779 bool can_position = false;
14780 int ret;
14781
14782 if (INTEL_GEN(dev_priv) >= 9) {
14783 /* use scaler when colorkey is not required */
14784 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14785 min_scale = 1;
14786 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14787 }
14788 can_position = true;
14789 }
14790
14791 ret = drm_plane_helper_check_state(&state->base,
14792 &state->clip,
14793 min_scale, max_scale,
14794 can_position, true);
14795 if (ret)
14796 return ret;
14797
14798 if (!state->base.fb)
14799 return 0;
14800
14801 if (INTEL_GEN(dev_priv) >= 9) {
14802 ret = skl_check_plane_surface(state);
14803 if (ret)
14804 return ret;
14805 }
14806
14807 return 0;
14808 }
14809
14810 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14811 struct drm_crtc_state *old_crtc_state)
14812 {
14813 struct drm_device *dev = crtc->dev;
14814 struct drm_i915_private *dev_priv = to_i915(dev);
14815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14816 struct intel_crtc_state *old_intel_state =
14817 to_intel_crtc_state(old_crtc_state);
14818 bool modeset = needs_modeset(crtc->state);
14819 enum pipe pipe = intel_crtc->pipe;
14820
14821 /* Perform vblank evasion around commit operation */
14822 intel_pipe_update_start(intel_crtc);
14823
14824 if (modeset)
14825 return;
14826
14827 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14828 intel_color_set_csc(crtc->state);
14829 intel_color_load_luts(crtc->state);
14830 }
14831
14832 if (to_intel_crtc_state(crtc->state)->update_pipe)
14833 intel_update_pipe_config(intel_crtc, old_intel_state);
14834 else if (INTEL_GEN(dev_priv) >= 9) {
14835 skl_detach_scalers(intel_crtc);
14836
14837 I915_WRITE(PIPE_WM_LINETIME(pipe),
14838 dev_priv->wm.skl_hw.wm_linetime[pipe]);
14839 }
14840 }
14841
14842 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14843 struct drm_crtc_state *old_crtc_state)
14844 {
14845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14846
14847 intel_pipe_update_end(intel_crtc, NULL);
14848 }
14849
14850 /**
14851 * intel_plane_destroy - destroy a plane
14852 * @plane: plane to destroy
14853 *
14854 * Common destruction function for all types of planes (primary, cursor,
14855 * sprite).
14856 */
14857 void intel_plane_destroy(struct drm_plane *plane)
14858 {
14859 if (!plane)
14860 return;
14861
14862 drm_plane_cleanup(plane);
14863 kfree(to_intel_plane(plane));
14864 }
14865
14866 const struct drm_plane_funcs intel_plane_funcs = {
14867 .update_plane = drm_atomic_helper_update_plane,
14868 .disable_plane = drm_atomic_helper_disable_plane,
14869 .destroy = intel_plane_destroy,
14870 .set_property = drm_atomic_helper_plane_set_property,
14871 .atomic_get_property = intel_plane_atomic_get_property,
14872 .atomic_set_property = intel_plane_atomic_set_property,
14873 .atomic_duplicate_state = intel_plane_duplicate_state,
14874 .atomic_destroy_state = intel_plane_destroy_state,
14875
14876 };
14877
14878 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14879 int pipe)
14880 {
14881 struct intel_plane *primary = NULL;
14882 struct intel_plane_state *state = NULL;
14883 const uint32_t *intel_primary_formats;
14884 unsigned int num_formats;
14885 int ret;
14886
14887 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14888 if (!primary)
14889 goto fail;
14890
14891 state = intel_create_plane_state(&primary->base);
14892 if (!state)
14893 goto fail;
14894 primary->base.state = &state->base;
14895
14896 primary->can_scale = false;
14897 primary->max_downscale = 1;
14898 if (INTEL_INFO(dev)->gen >= 9) {
14899 primary->can_scale = true;
14900 state->scaler_id = -1;
14901 }
14902 primary->pipe = pipe;
14903 primary->plane = pipe;
14904 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14905 primary->check_plane = intel_check_primary_plane;
14906 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14907 primary->plane = !pipe;
14908
14909 if (INTEL_INFO(dev)->gen >= 9) {
14910 intel_primary_formats = skl_primary_formats;
14911 num_formats = ARRAY_SIZE(skl_primary_formats);
14912
14913 primary->update_plane = skylake_update_primary_plane;
14914 primary->disable_plane = skylake_disable_primary_plane;
14915 } else if (HAS_PCH_SPLIT(dev)) {
14916 intel_primary_formats = i965_primary_formats;
14917 num_formats = ARRAY_SIZE(i965_primary_formats);
14918
14919 primary->update_plane = ironlake_update_primary_plane;
14920 primary->disable_plane = i9xx_disable_primary_plane;
14921 } else if (INTEL_INFO(dev)->gen >= 4) {
14922 intel_primary_formats = i965_primary_formats;
14923 num_formats = ARRAY_SIZE(i965_primary_formats);
14924
14925 primary->update_plane = i9xx_update_primary_plane;
14926 primary->disable_plane = i9xx_disable_primary_plane;
14927 } else {
14928 intel_primary_formats = i8xx_primary_formats;
14929 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14930
14931 primary->update_plane = i9xx_update_primary_plane;
14932 primary->disable_plane = i9xx_disable_primary_plane;
14933 }
14934
14935 if (INTEL_INFO(dev)->gen >= 9)
14936 ret = drm_universal_plane_init(dev, &primary->base, 0,
14937 &intel_plane_funcs,
14938 intel_primary_formats, num_formats,
14939 DRM_PLANE_TYPE_PRIMARY,
14940 "plane 1%c", pipe_name(pipe));
14941 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14942 ret = drm_universal_plane_init(dev, &primary->base, 0,
14943 &intel_plane_funcs,
14944 intel_primary_formats, num_formats,
14945 DRM_PLANE_TYPE_PRIMARY,
14946 "primary %c", pipe_name(pipe));
14947 else
14948 ret = drm_universal_plane_init(dev, &primary->base, 0,
14949 &intel_plane_funcs,
14950 intel_primary_formats, num_formats,
14951 DRM_PLANE_TYPE_PRIMARY,
14952 "plane %c", plane_name(primary->plane));
14953 if (ret)
14954 goto fail;
14955
14956 if (INTEL_INFO(dev)->gen >= 4)
14957 intel_create_rotation_property(dev, primary);
14958
14959 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14960
14961 return &primary->base;
14962
14963 fail:
14964 kfree(state);
14965 kfree(primary);
14966
14967 return NULL;
14968 }
14969
14970 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14971 {
14972 if (!dev->mode_config.rotation_property) {
14973 unsigned long flags = DRM_ROTATE_0 |
14974 DRM_ROTATE_180;
14975
14976 if (INTEL_INFO(dev)->gen >= 9)
14977 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14978
14979 dev->mode_config.rotation_property =
14980 drm_mode_create_rotation_property(dev, flags);
14981 }
14982 if (dev->mode_config.rotation_property)
14983 drm_object_attach_property(&plane->base.base,
14984 dev->mode_config.rotation_property,
14985 plane->base.state->rotation);
14986 }
14987
14988 static int
14989 intel_check_cursor_plane(struct drm_plane *plane,
14990 struct intel_crtc_state *crtc_state,
14991 struct intel_plane_state *state)
14992 {
14993 struct drm_framebuffer *fb = state->base.fb;
14994 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14995 enum pipe pipe = to_intel_plane(plane)->pipe;
14996 unsigned stride;
14997 int ret;
14998
14999 ret = drm_plane_helper_check_state(&state->base,
15000 &state->clip,
15001 DRM_PLANE_HELPER_NO_SCALING,
15002 DRM_PLANE_HELPER_NO_SCALING,
15003 true, true);
15004 if (ret)
15005 return ret;
15006
15007 /* if we want to turn off the cursor ignore width and height */
15008 if (!obj)
15009 return 0;
15010
15011 /* Check for which cursor types we support */
15012 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15013 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15014 state->base.crtc_w, state->base.crtc_h);
15015 return -EINVAL;
15016 }
15017
15018 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15019 if (obj->base.size < stride * state->base.crtc_h) {
15020 DRM_DEBUG_KMS("buffer is too small\n");
15021 return -ENOMEM;
15022 }
15023
15024 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15025 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15026 return -EINVAL;
15027 }
15028
15029 /*
15030 * There's something wrong with the cursor on CHV pipe C.
15031 * If it straddles the left edge of the screen then
15032 * moving it away from the edge or disabling it often
15033 * results in a pipe underrun, and often that can lead to
15034 * dead pipe (constant underrun reported, and it scans
15035 * out just a solid color). To recover from that, the
15036 * display power well must be turned off and on again.
15037 * Refuse the put the cursor into that compromised position.
15038 */
15039 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15040 state->base.visible && state->base.crtc_x < 0) {
15041 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15042 return -EINVAL;
15043 }
15044
15045 return 0;
15046 }
15047
15048 static void
15049 intel_disable_cursor_plane(struct drm_plane *plane,
15050 struct drm_crtc *crtc)
15051 {
15052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15053
15054 intel_crtc->cursor_addr = 0;
15055 intel_crtc_update_cursor(crtc, NULL);
15056 }
15057
15058 static void
15059 intel_update_cursor_plane(struct drm_plane *plane,
15060 const struct intel_crtc_state *crtc_state,
15061 const struct intel_plane_state *state)
15062 {
15063 struct drm_crtc *crtc = crtc_state->base.crtc;
15064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15065 struct drm_device *dev = plane->dev;
15066 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15067 uint32_t addr;
15068
15069 if (!obj)
15070 addr = 0;
15071 else if (!INTEL_INFO(dev)->cursor_needs_physical)
15072 addr = i915_gem_object_ggtt_offset(obj, NULL);
15073 else
15074 addr = obj->phys_handle->busaddr;
15075
15076 intel_crtc->cursor_addr = addr;
15077 intel_crtc_update_cursor(crtc, state);
15078 }
15079
15080 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15081 int pipe)
15082 {
15083 struct intel_plane *cursor = NULL;
15084 struct intel_plane_state *state = NULL;
15085 int ret;
15086
15087 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15088 if (!cursor)
15089 goto fail;
15090
15091 state = intel_create_plane_state(&cursor->base);
15092 if (!state)
15093 goto fail;
15094 cursor->base.state = &state->base;
15095
15096 cursor->can_scale = false;
15097 cursor->max_downscale = 1;
15098 cursor->pipe = pipe;
15099 cursor->plane = pipe;
15100 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15101 cursor->check_plane = intel_check_cursor_plane;
15102 cursor->update_plane = intel_update_cursor_plane;
15103 cursor->disable_plane = intel_disable_cursor_plane;
15104
15105 ret = drm_universal_plane_init(dev, &cursor->base, 0,
15106 &intel_plane_funcs,
15107 intel_cursor_formats,
15108 ARRAY_SIZE(intel_cursor_formats),
15109 DRM_PLANE_TYPE_CURSOR,
15110 "cursor %c", pipe_name(pipe));
15111 if (ret)
15112 goto fail;
15113
15114 if (INTEL_INFO(dev)->gen >= 4) {
15115 if (!dev->mode_config.rotation_property)
15116 dev->mode_config.rotation_property =
15117 drm_mode_create_rotation_property(dev,
15118 DRM_ROTATE_0 |
15119 DRM_ROTATE_180);
15120 if (dev->mode_config.rotation_property)
15121 drm_object_attach_property(&cursor->base.base,
15122 dev->mode_config.rotation_property,
15123 state->base.rotation);
15124 }
15125
15126 if (INTEL_INFO(dev)->gen >=9)
15127 state->scaler_id = -1;
15128
15129 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15130
15131 return &cursor->base;
15132
15133 fail:
15134 kfree(state);
15135 kfree(cursor);
15136
15137 return NULL;
15138 }
15139
15140 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15141 struct intel_crtc_state *crtc_state)
15142 {
15143 int i;
15144 struct intel_scaler *intel_scaler;
15145 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15146
15147 for (i = 0; i < intel_crtc->num_scalers; i++) {
15148 intel_scaler = &scaler_state->scalers[i];
15149 intel_scaler->in_use = 0;
15150 intel_scaler->mode = PS_SCALER_MODE_DYN;
15151 }
15152
15153 scaler_state->scaler_id = -1;
15154 }
15155
15156 static void intel_crtc_init(struct drm_device *dev, int pipe)
15157 {
15158 struct drm_i915_private *dev_priv = to_i915(dev);
15159 struct intel_crtc *intel_crtc;
15160 struct intel_crtc_state *crtc_state = NULL;
15161 struct drm_plane *primary = NULL;
15162 struct drm_plane *cursor = NULL;
15163 int ret;
15164
15165 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15166 if (intel_crtc == NULL)
15167 return;
15168
15169 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15170 if (!crtc_state)
15171 goto fail;
15172 intel_crtc->config = crtc_state;
15173 intel_crtc->base.state = &crtc_state->base;
15174 crtc_state->base.crtc = &intel_crtc->base;
15175
15176 /* initialize shared scalers */
15177 if (INTEL_INFO(dev)->gen >= 9) {
15178 if (pipe == PIPE_C)
15179 intel_crtc->num_scalers = 1;
15180 else
15181 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15182
15183 skl_init_scalers(dev, intel_crtc, crtc_state);
15184 }
15185
15186 primary = intel_primary_plane_create(dev, pipe);
15187 if (!primary)
15188 goto fail;
15189
15190 cursor = intel_cursor_plane_create(dev, pipe);
15191 if (!cursor)
15192 goto fail;
15193
15194 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15195 cursor, &intel_crtc_funcs,
15196 "pipe %c", pipe_name(pipe));
15197 if (ret)
15198 goto fail;
15199
15200 /*
15201 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15202 * is hooked to pipe B. Hence we want plane A feeding pipe B.
15203 */
15204 intel_crtc->pipe = pipe;
15205 intel_crtc->plane = pipe;
15206 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15207 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15208 intel_crtc->plane = !pipe;
15209 }
15210
15211 intel_crtc->cursor_base = ~0;
15212 intel_crtc->cursor_cntl = ~0;
15213 intel_crtc->cursor_size = ~0;
15214
15215 intel_crtc->wm.cxsr_allowed = true;
15216
15217 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15218 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15219 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15220 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15221
15222 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15223
15224 intel_color_init(&intel_crtc->base);
15225
15226 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15227 return;
15228
15229 fail:
15230 intel_plane_destroy(primary);
15231 intel_plane_destroy(cursor);
15232 kfree(crtc_state);
15233 kfree(intel_crtc);
15234 }
15235
15236 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15237 {
15238 struct drm_encoder *encoder = connector->base.encoder;
15239 struct drm_device *dev = connector->base.dev;
15240
15241 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15242
15243 if (!encoder || WARN_ON(!encoder->crtc))
15244 return INVALID_PIPE;
15245
15246 return to_intel_crtc(encoder->crtc)->pipe;
15247 }
15248
15249 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15250 struct drm_file *file)
15251 {
15252 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15253 struct drm_crtc *drmmode_crtc;
15254 struct intel_crtc *crtc;
15255
15256 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15257 if (!drmmode_crtc)
15258 return -ENOENT;
15259
15260 crtc = to_intel_crtc(drmmode_crtc);
15261 pipe_from_crtc_id->pipe = crtc->pipe;
15262
15263 return 0;
15264 }
15265
15266 static int intel_encoder_clones(struct intel_encoder *encoder)
15267 {
15268 struct drm_device *dev = encoder->base.dev;
15269 struct intel_encoder *source_encoder;
15270 int index_mask = 0;
15271 int entry = 0;
15272
15273 for_each_intel_encoder(dev, source_encoder) {
15274 if (encoders_cloneable(encoder, source_encoder))
15275 index_mask |= (1 << entry);
15276
15277 entry++;
15278 }
15279
15280 return index_mask;
15281 }
15282
15283 static bool has_edp_a(struct drm_device *dev)
15284 {
15285 struct drm_i915_private *dev_priv = to_i915(dev);
15286
15287 if (!IS_MOBILE(dev))
15288 return false;
15289
15290 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15291 return false;
15292
15293 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15294 return false;
15295
15296 return true;
15297 }
15298
15299 static bool intel_crt_present(struct drm_device *dev)
15300 {
15301 struct drm_i915_private *dev_priv = to_i915(dev);
15302
15303 if (INTEL_INFO(dev)->gen >= 9)
15304 return false;
15305
15306 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15307 return false;
15308
15309 if (IS_CHERRYVIEW(dev))
15310 return false;
15311
15312 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15313 return false;
15314
15315 /* DDI E can't be used if DDI A requires 4 lanes */
15316 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15317 return false;
15318
15319 if (!dev_priv->vbt.int_crt_support)
15320 return false;
15321
15322 return true;
15323 }
15324
15325 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15326 {
15327 int pps_num;
15328 int pps_idx;
15329
15330 if (HAS_DDI(dev_priv))
15331 return;
15332 /*
15333 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15334 * everywhere where registers can be write protected.
15335 */
15336 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15337 pps_num = 2;
15338 else
15339 pps_num = 1;
15340
15341 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15342 u32 val = I915_READ(PP_CONTROL(pps_idx));
15343
15344 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15345 I915_WRITE(PP_CONTROL(pps_idx), val);
15346 }
15347 }
15348
15349 static void intel_pps_init(struct drm_i915_private *dev_priv)
15350 {
15351 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15352 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15353 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15354 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15355 else
15356 dev_priv->pps_mmio_base = PPS_BASE;
15357
15358 intel_pps_unlock_regs_wa(dev_priv);
15359 }
15360
15361 static void intel_setup_outputs(struct drm_device *dev)
15362 {
15363 struct drm_i915_private *dev_priv = to_i915(dev);
15364 struct intel_encoder *encoder;
15365 bool dpd_is_edp = false;
15366
15367 intel_pps_init(dev_priv);
15368
15369 /*
15370 * intel_edp_init_connector() depends on this completing first, to
15371 * prevent the registeration of both eDP and LVDS and the incorrect
15372 * sharing of the PPS.
15373 */
15374 intel_lvds_init(dev);
15375
15376 if (intel_crt_present(dev))
15377 intel_crt_init(dev);
15378
15379 if (IS_BROXTON(dev)) {
15380 /*
15381 * FIXME: Broxton doesn't support port detection via the
15382 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15383 * detect the ports.
15384 */
15385 intel_ddi_init(dev, PORT_A);
15386 intel_ddi_init(dev, PORT_B);
15387 intel_ddi_init(dev, PORT_C);
15388
15389 intel_dsi_init(dev);
15390 } else if (HAS_DDI(dev)) {
15391 int found;
15392
15393 /*
15394 * Haswell uses DDI functions to detect digital outputs.
15395 * On SKL pre-D0 the strap isn't connected, so we assume
15396 * it's there.
15397 */
15398 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15399 /* WaIgnoreDDIAStrap: skl */
15400 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15401 intel_ddi_init(dev, PORT_A);
15402
15403 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15404 * register */
15405 found = I915_READ(SFUSE_STRAP);
15406
15407 if (found & SFUSE_STRAP_DDIB_DETECTED)
15408 intel_ddi_init(dev, PORT_B);
15409 if (found & SFUSE_STRAP_DDIC_DETECTED)
15410 intel_ddi_init(dev, PORT_C);
15411 if (found & SFUSE_STRAP_DDID_DETECTED)
15412 intel_ddi_init(dev, PORT_D);
15413 /*
15414 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15415 */
15416 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15417 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15418 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15419 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15420 intel_ddi_init(dev, PORT_E);
15421
15422 } else if (HAS_PCH_SPLIT(dev)) {
15423 int found;
15424 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15425
15426 if (has_edp_a(dev))
15427 intel_dp_init(dev, DP_A, PORT_A);
15428
15429 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15430 /* PCH SDVOB multiplex with HDMIB */
15431 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15432 if (!found)
15433 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15435 intel_dp_init(dev, PCH_DP_B, PORT_B);
15436 }
15437
15438 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15439 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15440
15441 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15442 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15443
15444 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15445 intel_dp_init(dev, PCH_DP_C, PORT_C);
15446
15447 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15448 intel_dp_init(dev, PCH_DP_D, PORT_D);
15449 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15450 bool has_edp, has_port;
15451
15452 /*
15453 * The DP_DETECTED bit is the latched state of the DDC
15454 * SDA pin at boot. However since eDP doesn't require DDC
15455 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15456 * eDP ports may have been muxed to an alternate function.
15457 * Thus we can't rely on the DP_DETECTED bit alone to detect
15458 * eDP ports. Consult the VBT as well as DP_DETECTED to
15459 * detect eDP ports.
15460 *
15461 * Sadly the straps seem to be missing sometimes even for HDMI
15462 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15463 * and VBT for the presence of the port. Additionally we can't
15464 * trust the port type the VBT declares as we've seen at least
15465 * HDMI ports that the VBT claim are DP or eDP.
15466 */
15467 has_edp = intel_dp_is_edp(dev, PORT_B);
15468 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15469 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15470 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15471 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15472 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15473
15474 has_edp = intel_dp_is_edp(dev, PORT_C);
15475 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15476 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15477 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15478 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15479 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15480
15481 if (IS_CHERRYVIEW(dev)) {
15482 /*
15483 * eDP not supported on port D,
15484 * so no need to worry about it
15485 */
15486 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15487 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15488 intel_dp_init(dev, CHV_DP_D, PORT_D);
15489 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15490 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15491 }
15492
15493 intel_dsi_init(dev);
15494 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15495 bool found = false;
15496
15497 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15498 DRM_DEBUG_KMS("probing SDVOB\n");
15499 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15500 if (!found && IS_G4X(dev)) {
15501 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15502 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15503 }
15504
15505 if (!found && IS_G4X(dev))
15506 intel_dp_init(dev, DP_B, PORT_B);
15507 }
15508
15509 /* Before G4X SDVOC doesn't have its own detect register */
15510
15511 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15512 DRM_DEBUG_KMS("probing SDVOC\n");
15513 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15514 }
15515
15516 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15517
15518 if (IS_G4X(dev)) {
15519 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15520 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15521 }
15522 if (IS_G4X(dev))
15523 intel_dp_init(dev, DP_C, PORT_C);
15524 }
15525
15526 if (IS_G4X(dev) &&
15527 (I915_READ(DP_D) & DP_DETECTED))
15528 intel_dp_init(dev, DP_D, PORT_D);
15529 } else if (IS_GEN2(dev))
15530 intel_dvo_init(dev);
15531
15532 if (SUPPORTS_TV(dev))
15533 intel_tv_init(dev);
15534
15535 intel_psr_init(dev);
15536
15537 for_each_intel_encoder(dev, encoder) {
15538 encoder->base.possible_crtcs = encoder->crtc_mask;
15539 encoder->base.possible_clones =
15540 intel_encoder_clones(encoder);
15541 }
15542
15543 intel_init_pch_refclk(dev);
15544
15545 drm_helper_move_panel_connectors_to_head(dev);
15546 }
15547
15548 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15549 {
15550 struct drm_device *dev = fb->dev;
15551 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15552
15553 drm_framebuffer_cleanup(fb);
15554 mutex_lock(&dev->struct_mutex);
15555 WARN_ON(!intel_fb->obj->framebuffer_references--);
15556 i915_gem_object_put(intel_fb->obj);
15557 mutex_unlock(&dev->struct_mutex);
15558 kfree(intel_fb);
15559 }
15560
15561 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15562 struct drm_file *file,
15563 unsigned int *handle)
15564 {
15565 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15566 struct drm_i915_gem_object *obj = intel_fb->obj;
15567
15568 if (obj->userptr.mm) {
15569 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15570 return -EINVAL;
15571 }
15572
15573 return drm_gem_handle_create(file, &obj->base, handle);
15574 }
15575
15576 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15577 struct drm_file *file,
15578 unsigned flags, unsigned color,
15579 struct drm_clip_rect *clips,
15580 unsigned num_clips)
15581 {
15582 struct drm_device *dev = fb->dev;
15583 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15584 struct drm_i915_gem_object *obj = intel_fb->obj;
15585
15586 mutex_lock(&dev->struct_mutex);
15587 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15588 mutex_unlock(&dev->struct_mutex);
15589
15590 return 0;
15591 }
15592
15593 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15594 .destroy = intel_user_framebuffer_destroy,
15595 .create_handle = intel_user_framebuffer_create_handle,
15596 .dirty = intel_user_framebuffer_dirty,
15597 };
15598
15599 static
15600 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15601 uint32_t pixel_format)
15602 {
15603 u32 gen = INTEL_INFO(dev)->gen;
15604
15605 if (gen >= 9) {
15606 int cpp = drm_format_plane_cpp(pixel_format, 0);
15607
15608 /* "The stride in bytes must not exceed the of the size of 8K
15609 * pixels and 32K bytes."
15610 */
15611 return min(8192 * cpp, 32768);
15612 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15613 return 32*1024;
15614 } else if (gen >= 4) {
15615 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15616 return 16*1024;
15617 else
15618 return 32*1024;
15619 } else if (gen >= 3) {
15620 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15621 return 8*1024;
15622 else
15623 return 16*1024;
15624 } else {
15625 /* XXX DSPC is limited to 4k tiled */
15626 return 8*1024;
15627 }
15628 }
15629
15630 static int intel_framebuffer_init(struct drm_device *dev,
15631 struct intel_framebuffer *intel_fb,
15632 struct drm_mode_fb_cmd2 *mode_cmd,
15633 struct drm_i915_gem_object *obj)
15634 {
15635 struct drm_i915_private *dev_priv = to_i915(dev);
15636 unsigned int tiling = i915_gem_object_get_tiling(obj);
15637 int ret;
15638 u32 pitch_limit, stride_alignment;
15639 char *format_name;
15640
15641 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15642
15643 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15644 /*
15645 * If there's a fence, enforce that
15646 * the fb modifier and tiling mode match.
15647 */
15648 if (tiling != I915_TILING_NONE &&
15649 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15650 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15651 return -EINVAL;
15652 }
15653 } else {
15654 if (tiling == I915_TILING_X) {
15655 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15656 } else if (tiling == I915_TILING_Y) {
15657 DRM_DEBUG("No Y tiling for legacy addfb\n");
15658 return -EINVAL;
15659 }
15660 }
15661
15662 /* Passed in modifier sanity checking. */
15663 switch (mode_cmd->modifier[0]) {
15664 case I915_FORMAT_MOD_Y_TILED:
15665 case I915_FORMAT_MOD_Yf_TILED:
15666 if (INTEL_INFO(dev)->gen < 9) {
15667 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15668 mode_cmd->modifier[0]);
15669 return -EINVAL;
15670 }
15671 case DRM_FORMAT_MOD_NONE:
15672 case I915_FORMAT_MOD_X_TILED:
15673 break;
15674 default:
15675 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15676 mode_cmd->modifier[0]);
15677 return -EINVAL;
15678 }
15679
15680 /*
15681 * gen2/3 display engine uses the fence if present,
15682 * so the tiling mode must match the fb modifier exactly.
15683 */
15684 if (INTEL_INFO(dev_priv)->gen < 4 &&
15685 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15686 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15687 return -EINVAL;
15688 }
15689
15690 stride_alignment = intel_fb_stride_alignment(dev_priv,
15691 mode_cmd->modifier[0],
15692 mode_cmd->pixel_format);
15693 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15694 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15695 mode_cmd->pitches[0], stride_alignment);
15696 return -EINVAL;
15697 }
15698
15699 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15700 mode_cmd->pixel_format);
15701 if (mode_cmd->pitches[0] > pitch_limit) {
15702 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15703 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15704 "tiled" : "linear",
15705 mode_cmd->pitches[0], pitch_limit);
15706 return -EINVAL;
15707 }
15708
15709 /*
15710 * If there's a fence, enforce that
15711 * the fb pitch and fence stride match.
15712 */
15713 if (tiling != I915_TILING_NONE &&
15714 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15715 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15716 mode_cmd->pitches[0],
15717 i915_gem_object_get_stride(obj));
15718 return -EINVAL;
15719 }
15720
15721 /* Reject formats not supported by any plane early. */
15722 switch (mode_cmd->pixel_format) {
15723 case DRM_FORMAT_C8:
15724 case DRM_FORMAT_RGB565:
15725 case DRM_FORMAT_XRGB8888:
15726 case DRM_FORMAT_ARGB8888:
15727 break;
15728 case DRM_FORMAT_XRGB1555:
15729 if (INTEL_INFO(dev)->gen > 3) {
15730 format_name = drm_get_format_name(mode_cmd->pixel_format);
15731 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15732 kfree(format_name);
15733 return -EINVAL;
15734 }
15735 break;
15736 case DRM_FORMAT_ABGR8888:
15737 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15738 INTEL_INFO(dev)->gen < 9) {
15739 format_name = drm_get_format_name(mode_cmd->pixel_format);
15740 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15741 kfree(format_name);
15742 return -EINVAL;
15743 }
15744 break;
15745 case DRM_FORMAT_XBGR8888:
15746 case DRM_FORMAT_XRGB2101010:
15747 case DRM_FORMAT_XBGR2101010:
15748 if (INTEL_INFO(dev)->gen < 4) {
15749 format_name = drm_get_format_name(mode_cmd->pixel_format);
15750 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15751 kfree(format_name);
15752 return -EINVAL;
15753 }
15754 break;
15755 case DRM_FORMAT_ABGR2101010:
15756 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15757 format_name = drm_get_format_name(mode_cmd->pixel_format);
15758 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15759 kfree(format_name);
15760 return -EINVAL;
15761 }
15762 break;
15763 case DRM_FORMAT_YUYV:
15764 case DRM_FORMAT_UYVY:
15765 case DRM_FORMAT_YVYU:
15766 case DRM_FORMAT_VYUY:
15767 if (INTEL_INFO(dev)->gen < 5) {
15768 format_name = drm_get_format_name(mode_cmd->pixel_format);
15769 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15770 kfree(format_name);
15771 return -EINVAL;
15772 }
15773 break;
15774 default:
15775 format_name = drm_get_format_name(mode_cmd->pixel_format);
15776 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15777 kfree(format_name);
15778 return -EINVAL;
15779 }
15780
15781 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15782 if (mode_cmd->offsets[0] != 0)
15783 return -EINVAL;
15784
15785 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15786 intel_fb->obj = obj;
15787
15788 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15789 if (ret)
15790 return ret;
15791
15792 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15793 if (ret) {
15794 DRM_ERROR("framebuffer init failed %d\n", ret);
15795 return ret;
15796 }
15797
15798 intel_fb->obj->framebuffer_references++;
15799
15800 return 0;
15801 }
15802
15803 static struct drm_framebuffer *
15804 intel_user_framebuffer_create(struct drm_device *dev,
15805 struct drm_file *filp,
15806 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15807 {
15808 struct drm_framebuffer *fb;
15809 struct drm_i915_gem_object *obj;
15810 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15811
15812 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15813 if (!obj)
15814 return ERR_PTR(-ENOENT);
15815
15816 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15817 if (IS_ERR(fb))
15818 i915_gem_object_put_unlocked(obj);
15819
15820 return fb;
15821 }
15822
15823 #ifndef CONFIG_DRM_FBDEV_EMULATION
15824 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15825 {
15826 }
15827 #endif
15828
15829 static const struct drm_mode_config_funcs intel_mode_funcs = {
15830 .fb_create = intel_user_framebuffer_create,
15831 .output_poll_changed = intel_fbdev_output_poll_changed,
15832 .atomic_check = intel_atomic_check,
15833 .atomic_commit = intel_atomic_commit,
15834 .atomic_state_alloc = intel_atomic_state_alloc,
15835 .atomic_state_clear = intel_atomic_state_clear,
15836 };
15837
15838 /**
15839 * intel_init_display_hooks - initialize the display modesetting hooks
15840 * @dev_priv: device private
15841 */
15842 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15843 {
15844 if (INTEL_INFO(dev_priv)->gen >= 9) {
15845 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15846 dev_priv->display.get_initial_plane_config =
15847 skylake_get_initial_plane_config;
15848 dev_priv->display.crtc_compute_clock =
15849 haswell_crtc_compute_clock;
15850 dev_priv->display.crtc_enable = haswell_crtc_enable;
15851 dev_priv->display.crtc_disable = haswell_crtc_disable;
15852 } else if (HAS_DDI(dev_priv)) {
15853 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15854 dev_priv->display.get_initial_plane_config =
15855 ironlake_get_initial_plane_config;
15856 dev_priv->display.crtc_compute_clock =
15857 haswell_crtc_compute_clock;
15858 dev_priv->display.crtc_enable = haswell_crtc_enable;
15859 dev_priv->display.crtc_disable = haswell_crtc_disable;
15860 } else if (HAS_PCH_SPLIT(dev_priv)) {
15861 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15862 dev_priv->display.get_initial_plane_config =
15863 ironlake_get_initial_plane_config;
15864 dev_priv->display.crtc_compute_clock =
15865 ironlake_crtc_compute_clock;
15866 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15867 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15868 } else if (IS_CHERRYVIEW(dev_priv)) {
15869 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15870 dev_priv->display.get_initial_plane_config =
15871 i9xx_get_initial_plane_config;
15872 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15873 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15874 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15875 } else if (IS_VALLEYVIEW(dev_priv)) {
15876 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15877 dev_priv->display.get_initial_plane_config =
15878 i9xx_get_initial_plane_config;
15879 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15880 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15881 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15882 } else if (IS_G4X(dev_priv)) {
15883 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15884 dev_priv->display.get_initial_plane_config =
15885 i9xx_get_initial_plane_config;
15886 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15887 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15888 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15889 } else if (IS_PINEVIEW(dev_priv)) {
15890 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15891 dev_priv->display.get_initial_plane_config =
15892 i9xx_get_initial_plane_config;
15893 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15894 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15895 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15896 } else if (!IS_GEN2(dev_priv)) {
15897 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15898 dev_priv->display.get_initial_plane_config =
15899 i9xx_get_initial_plane_config;
15900 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15901 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15902 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15903 } else {
15904 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15905 dev_priv->display.get_initial_plane_config =
15906 i9xx_get_initial_plane_config;
15907 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15908 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15909 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15910 }
15911
15912 /* Returns the core display clock speed */
15913 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15914 dev_priv->display.get_display_clock_speed =
15915 skylake_get_display_clock_speed;
15916 else if (IS_BROXTON(dev_priv))
15917 dev_priv->display.get_display_clock_speed =
15918 broxton_get_display_clock_speed;
15919 else if (IS_BROADWELL(dev_priv))
15920 dev_priv->display.get_display_clock_speed =
15921 broadwell_get_display_clock_speed;
15922 else if (IS_HASWELL(dev_priv))
15923 dev_priv->display.get_display_clock_speed =
15924 haswell_get_display_clock_speed;
15925 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15926 dev_priv->display.get_display_clock_speed =
15927 valleyview_get_display_clock_speed;
15928 else if (IS_GEN5(dev_priv))
15929 dev_priv->display.get_display_clock_speed =
15930 ilk_get_display_clock_speed;
15931 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15932 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15933 dev_priv->display.get_display_clock_speed =
15934 i945_get_display_clock_speed;
15935 else if (IS_GM45(dev_priv))
15936 dev_priv->display.get_display_clock_speed =
15937 gm45_get_display_clock_speed;
15938 else if (IS_CRESTLINE(dev_priv))
15939 dev_priv->display.get_display_clock_speed =
15940 i965gm_get_display_clock_speed;
15941 else if (IS_PINEVIEW(dev_priv))
15942 dev_priv->display.get_display_clock_speed =
15943 pnv_get_display_clock_speed;
15944 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15945 dev_priv->display.get_display_clock_speed =
15946 g33_get_display_clock_speed;
15947 else if (IS_I915G(dev_priv))
15948 dev_priv->display.get_display_clock_speed =
15949 i915_get_display_clock_speed;
15950 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15951 dev_priv->display.get_display_clock_speed =
15952 i9xx_misc_get_display_clock_speed;
15953 else if (IS_I915GM(dev_priv))
15954 dev_priv->display.get_display_clock_speed =
15955 i915gm_get_display_clock_speed;
15956 else if (IS_I865G(dev_priv))
15957 dev_priv->display.get_display_clock_speed =
15958 i865_get_display_clock_speed;
15959 else if (IS_I85X(dev_priv))
15960 dev_priv->display.get_display_clock_speed =
15961 i85x_get_display_clock_speed;
15962 else { /* 830 */
15963 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15964 dev_priv->display.get_display_clock_speed =
15965 i830_get_display_clock_speed;
15966 }
15967
15968 if (IS_GEN5(dev_priv)) {
15969 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15970 } else if (IS_GEN6(dev_priv)) {
15971 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15972 } else if (IS_IVYBRIDGE(dev_priv)) {
15973 /* FIXME: detect B0+ stepping and use auto training */
15974 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15975 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15976 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15977 }
15978
15979 if (IS_BROADWELL(dev_priv)) {
15980 dev_priv->display.modeset_commit_cdclk =
15981 broadwell_modeset_commit_cdclk;
15982 dev_priv->display.modeset_calc_cdclk =
15983 broadwell_modeset_calc_cdclk;
15984 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15985 dev_priv->display.modeset_commit_cdclk =
15986 valleyview_modeset_commit_cdclk;
15987 dev_priv->display.modeset_calc_cdclk =
15988 valleyview_modeset_calc_cdclk;
15989 } else if (IS_BROXTON(dev_priv)) {
15990 dev_priv->display.modeset_commit_cdclk =
15991 bxt_modeset_commit_cdclk;
15992 dev_priv->display.modeset_calc_cdclk =
15993 bxt_modeset_calc_cdclk;
15994 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15995 dev_priv->display.modeset_commit_cdclk =
15996 skl_modeset_commit_cdclk;
15997 dev_priv->display.modeset_calc_cdclk =
15998 skl_modeset_calc_cdclk;
15999 }
16000
16001 if (dev_priv->info.gen >= 9)
16002 dev_priv->display.update_crtcs = skl_update_crtcs;
16003 else
16004 dev_priv->display.update_crtcs = intel_update_crtcs;
16005
16006 switch (INTEL_INFO(dev_priv)->gen) {
16007 case 2:
16008 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16009 break;
16010
16011 case 3:
16012 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16013 break;
16014
16015 case 4:
16016 case 5:
16017 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16018 break;
16019
16020 case 6:
16021 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16022 break;
16023 case 7:
16024 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16025 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16026 break;
16027 case 9:
16028 /* Drop through - unsupported since execlist only. */
16029 default:
16030 /* Default just returns -ENODEV to indicate unsupported */
16031 dev_priv->display.queue_flip = intel_default_queue_flip;
16032 }
16033 }
16034
16035 /*
16036 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16037 * resume, or other times. This quirk makes sure that's the case for
16038 * affected systems.
16039 */
16040 static void quirk_pipea_force(struct drm_device *dev)
16041 {
16042 struct drm_i915_private *dev_priv = to_i915(dev);
16043
16044 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16045 DRM_INFO("applying pipe a force quirk\n");
16046 }
16047
16048 static void quirk_pipeb_force(struct drm_device *dev)
16049 {
16050 struct drm_i915_private *dev_priv = to_i915(dev);
16051
16052 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16053 DRM_INFO("applying pipe b force quirk\n");
16054 }
16055
16056 /*
16057 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16058 */
16059 static void quirk_ssc_force_disable(struct drm_device *dev)
16060 {
16061 struct drm_i915_private *dev_priv = to_i915(dev);
16062 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16063 DRM_INFO("applying lvds SSC disable quirk\n");
16064 }
16065
16066 /*
16067 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16068 * brightness value
16069 */
16070 static void quirk_invert_brightness(struct drm_device *dev)
16071 {
16072 struct drm_i915_private *dev_priv = to_i915(dev);
16073 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16074 DRM_INFO("applying inverted panel brightness quirk\n");
16075 }
16076
16077 /* Some VBT's incorrectly indicate no backlight is present */
16078 static void quirk_backlight_present(struct drm_device *dev)
16079 {
16080 struct drm_i915_private *dev_priv = to_i915(dev);
16081 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16082 DRM_INFO("applying backlight present quirk\n");
16083 }
16084
16085 struct intel_quirk {
16086 int device;
16087 int subsystem_vendor;
16088 int subsystem_device;
16089 void (*hook)(struct drm_device *dev);
16090 };
16091
16092 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16093 struct intel_dmi_quirk {
16094 void (*hook)(struct drm_device *dev);
16095 const struct dmi_system_id (*dmi_id_list)[];
16096 };
16097
16098 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16099 {
16100 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16101 return 1;
16102 }
16103
16104 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16105 {
16106 .dmi_id_list = &(const struct dmi_system_id[]) {
16107 {
16108 .callback = intel_dmi_reverse_brightness,
16109 .ident = "NCR Corporation",
16110 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16111 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16112 },
16113 },
16114 { } /* terminating entry */
16115 },
16116 .hook = quirk_invert_brightness,
16117 },
16118 };
16119
16120 static struct intel_quirk intel_quirks[] = {
16121 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16122 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16123
16124 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16125 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16126
16127 /* 830 needs to leave pipe A & dpll A up */
16128 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16129
16130 /* 830 needs to leave pipe B & dpll B up */
16131 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16132
16133 /* Lenovo U160 cannot use SSC on LVDS */
16134 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16135
16136 /* Sony Vaio Y cannot use SSC on LVDS */
16137 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16138
16139 /* Acer Aspire 5734Z must invert backlight brightness */
16140 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16141
16142 /* Acer/eMachines G725 */
16143 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16144
16145 /* Acer/eMachines e725 */
16146 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16147
16148 /* Acer/Packard Bell NCL20 */
16149 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16150
16151 /* Acer Aspire 4736Z */
16152 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16153
16154 /* Acer Aspire 5336 */
16155 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16156
16157 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16158 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16159
16160 /* Acer C720 Chromebook (Core i3 4005U) */
16161 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16162
16163 /* Apple Macbook 2,1 (Core 2 T7400) */
16164 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16165
16166 /* Apple Macbook 4,1 */
16167 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16168
16169 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16170 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16171
16172 /* HP Chromebook 14 (Celeron 2955U) */
16173 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16174
16175 /* Dell Chromebook 11 */
16176 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16177
16178 /* Dell Chromebook 11 (2015 version) */
16179 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16180 };
16181
16182 static void intel_init_quirks(struct drm_device *dev)
16183 {
16184 struct pci_dev *d = dev->pdev;
16185 int i;
16186
16187 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16188 struct intel_quirk *q = &intel_quirks[i];
16189
16190 if (d->device == q->device &&
16191 (d->subsystem_vendor == q->subsystem_vendor ||
16192 q->subsystem_vendor == PCI_ANY_ID) &&
16193 (d->subsystem_device == q->subsystem_device ||
16194 q->subsystem_device == PCI_ANY_ID))
16195 q->hook(dev);
16196 }
16197 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16198 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16199 intel_dmi_quirks[i].hook(dev);
16200 }
16201 }
16202
16203 /* Disable the VGA plane that we never use */
16204 static void i915_disable_vga(struct drm_device *dev)
16205 {
16206 struct drm_i915_private *dev_priv = to_i915(dev);
16207 struct pci_dev *pdev = dev_priv->drm.pdev;
16208 u8 sr1;
16209 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16210
16211 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16212 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16213 outb(SR01, VGA_SR_INDEX);
16214 sr1 = inb(VGA_SR_DATA);
16215 outb(sr1 | 1<<5, VGA_SR_DATA);
16216 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16217 udelay(300);
16218
16219 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16220 POSTING_READ(vga_reg);
16221 }
16222
16223 void intel_modeset_init_hw(struct drm_device *dev)
16224 {
16225 struct drm_i915_private *dev_priv = to_i915(dev);
16226
16227 intel_update_cdclk(dev);
16228
16229 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16230
16231 intel_init_clock_gating(dev);
16232 }
16233
16234 /*
16235 * Calculate what we think the watermarks should be for the state we've read
16236 * out of the hardware and then immediately program those watermarks so that
16237 * we ensure the hardware settings match our internal state.
16238 *
16239 * We can calculate what we think WM's should be by creating a duplicate of the
16240 * current state (which was constructed during hardware readout) and running it
16241 * through the atomic check code to calculate new watermark values in the
16242 * state object.
16243 */
16244 static void sanitize_watermarks(struct drm_device *dev)
16245 {
16246 struct drm_i915_private *dev_priv = to_i915(dev);
16247 struct drm_atomic_state *state;
16248 struct drm_crtc *crtc;
16249 struct drm_crtc_state *cstate;
16250 struct drm_modeset_acquire_ctx ctx;
16251 int ret;
16252 int i;
16253
16254 /* Only supported on platforms that use atomic watermark design */
16255 if (!dev_priv->display.optimize_watermarks)
16256 return;
16257
16258 /*
16259 * We need to hold connection_mutex before calling duplicate_state so
16260 * that the connector loop is protected.
16261 */
16262 drm_modeset_acquire_init(&ctx, 0);
16263 retry:
16264 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16265 if (ret == -EDEADLK) {
16266 drm_modeset_backoff(&ctx);
16267 goto retry;
16268 } else if (WARN_ON(ret)) {
16269 goto fail;
16270 }
16271
16272 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16273 if (WARN_ON(IS_ERR(state)))
16274 goto fail;
16275
16276 /*
16277 * Hardware readout is the only time we don't want to calculate
16278 * intermediate watermarks (since we don't trust the current
16279 * watermarks).
16280 */
16281 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16282
16283 ret = intel_atomic_check(dev, state);
16284 if (ret) {
16285 /*
16286 * If we fail here, it means that the hardware appears to be
16287 * programmed in a way that shouldn't be possible, given our
16288 * understanding of watermark requirements. This might mean a
16289 * mistake in the hardware readout code or a mistake in the
16290 * watermark calculations for a given platform. Raise a WARN
16291 * so that this is noticeable.
16292 *
16293 * If this actually happens, we'll have to just leave the
16294 * BIOS-programmed watermarks untouched and hope for the best.
16295 */
16296 WARN(true, "Could not determine valid watermarks for inherited state\n");
16297 goto fail;
16298 }
16299
16300 /* Write calculated watermark values back */
16301 for_each_crtc_in_state(state, crtc, cstate, i) {
16302 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16303
16304 cs->wm.need_postvbl_update = true;
16305 dev_priv->display.optimize_watermarks(cs);
16306 }
16307
16308 drm_atomic_state_free(state);
16309 fail:
16310 drm_modeset_drop_locks(&ctx);
16311 drm_modeset_acquire_fini(&ctx);
16312 }
16313
16314 void intel_modeset_init(struct drm_device *dev)
16315 {
16316 struct drm_i915_private *dev_priv = to_i915(dev);
16317 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16318 int sprite, ret;
16319 enum pipe pipe;
16320 struct intel_crtc *crtc;
16321
16322 drm_mode_config_init(dev);
16323
16324 dev->mode_config.min_width = 0;
16325 dev->mode_config.min_height = 0;
16326
16327 dev->mode_config.preferred_depth = 24;
16328 dev->mode_config.prefer_shadow = 1;
16329
16330 dev->mode_config.allow_fb_modifiers = true;
16331
16332 dev->mode_config.funcs = &intel_mode_funcs;
16333
16334 intel_init_quirks(dev);
16335
16336 intel_init_pm(dev);
16337
16338 if (INTEL_INFO(dev)->num_pipes == 0)
16339 return;
16340
16341 /*
16342 * There may be no VBT; and if the BIOS enabled SSC we can
16343 * just keep using it to avoid unnecessary flicker. Whereas if the
16344 * BIOS isn't using it, don't assume it will work even if the VBT
16345 * indicates as much.
16346 */
16347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16348 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16349 DREF_SSC1_ENABLE);
16350
16351 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16352 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16353 bios_lvds_use_ssc ? "en" : "dis",
16354 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16355 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16356 }
16357 }
16358
16359 if (IS_GEN2(dev)) {
16360 dev->mode_config.max_width = 2048;
16361 dev->mode_config.max_height = 2048;
16362 } else if (IS_GEN3(dev)) {
16363 dev->mode_config.max_width = 4096;
16364 dev->mode_config.max_height = 4096;
16365 } else {
16366 dev->mode_config.max_width = 8192;
16367 dev->mode_config.max_height = 8192;
16368 }
16369
16370 if (IS_845G(dev) || IS_I865G(dev)) {
16371 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16372 dev->mode_config.cursor_height = 1023;
16373 } else if (IS_GEN2(dev)) {
16374 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16375 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16376 } else {
16377 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16378 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16379 }
16380
16381 dev->mode_config.fb_base = ggtt->mappable_base;
16382
16383 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16384 INTEL_INFO(dev)->num_pipes,
16385 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16386
16387 for_each_pipe(dev_priv, pipe) {
16388 intel_crtc_init(dev, pipe);
16389 for_each_sprite(dev_priv, pipe, sprite) {
16390 ret = intel_plane_init(dev, pipe, sprite);
16391 if (ret)
16392 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16393 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16394 }
16395 }
16396
16397 intel_update_czclk(dev_priv);
16398 intel_update_cdclk(dev);
16399
16400 intel_shared_dpll_init(dev);
16401
16402 if (dev_priv->max_cdclk_freq == 0)
16403 intel_update_max_cdclk(dev);
16404
16405 /* Just disable it once at startup */
16406 i915_disable_vga(dev);
16407 intel_setup_outputs(dev);
16408
16409 drm_modeset_lock_all(dev);
16410 intel_modeset_setup_hw_state(dev);
16411 drm_modeset_unlock_all(dev);
16412
16413 for_each_intel_crtc(dev, crtc) {
16414 struct intel_initial_plane_config plane_config = {};
16415
16416 if (!crtc->active)
16417 continue;
16418
16419 /*
16420 * Note that reserving the BIOS fb up front prevents us
16421 * from stuffing other stolen allocations like the ring
16422 * on top. This prevents some ugliness at boot time, and
16423 * can even allow for smooth boot transitions if the BIOS
16424 * fb is large enough for the active pipe configuration.
16425 */
16426 dev_priv->display.get_initial_plane_config(crtc,
16427 &plane_config);
16428
16429 /*
16430 * If the fb is shared between multiple heads, we'll
16431 * just get the first one.
16432 */
16433 intel_find_initial_plane_obj(crtc, &plane_config);
16434 }
16435
16436 /*
16437 * Make sure hardware watermarks really match the state we read out.
16438 * Note that we need to do this after reconstructing the BIOS fb's
16439 * since the watermark calculation done here will use pstate->fb.
16440 */
16441 sanitize_watermarks(dev);
16442 }
16443
16444 static void intel_enable_pipe_a(struct drm_device *dev)
16445 {
16446 struct intel_connector *connector;
16447 struct drm_connector *crt = NULL;
16448 struct intel_load_detect_pipe load_detect_temp;
16449 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16450
16451 /* We can't just switch on the pipe A, we need to set things up with a
16452 * proper mode and output configuration. As a gross hack, enable pipe A
16453 * by enabling the load detect pipe once. */
16454 for_each_intel_connector(dev, connector) {
16455 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16456 crt = &connector->base;
16457 break;
16458 }
16459 }
16460
16461 if (!crt)
16462 return;
16463
16464 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16465 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16466 }
16467
16468 static bool
16469 intel_check_plane_mapping(struct intel_crtc *crtc)
16470 {
16471 struct drm_device *dev = crtc->base.dev;
16472 struct drm_i915_private *dev_priv = to_i915(dev);
16473 u32 val;
16474
16475 if (INTEL_INFO(dev)->num_pipes == 1)
16476 return true;
16477
16478 val = I915_READ(DSPCNTR(!crtc->plane));
16479
16480 if ((val & DISPLAY_PLANE_ENABLE) &&
16481 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16482 return false;
16483
16484 return true;
16485 }
16486
16487 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16488 {
16489 struct drm_device *dev = crtc->base.dev;
16490 struct intel_encoder *encoder;
16491
16492 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16493 return true;
16494
16495 return false;
16496 }
16497
16498 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16499 {
16500 struct drm_device *dev = encoder->base.dev;
16501 struct intel_connector *connector;
16502
16503 for_each_connector_on_encoder(dev, &encoder->base, connector)
16504 return connector;
16505
16506 return NULL;
16507 }
16508
16509 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16510 enum transcoder pch_transcoder)
16511 {
16512 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16513 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16514 }
16515
16516 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16517 {
16518 struct drm_device *dev = crtc->base.dev;
16519 struct drm_i915_private *dev_priv = to_i915(dev);
16520 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16521
16522 /* Clear any frame start delays used for debugging left by the BIOS */
16523 if (!transcoder_is_dsi(cpu_transcoder)) {
16524 i915_reg_t reg = PIPECONF(cpu_transcoder);
16525
16526 I915_WRITE(reg,
16527 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16528 }
16529
16530 /* restore vblank interrupts to correct state */
16531 drm_crtc_vblank_reset(&crtc->base);
16532 if (crtc->active) {
16533 struct intel_plane *plane;
16534
16535 drm_crtc_vblank_on(&crtc->base);
16536
16537 /* Disable everything but the primary plane */
16538 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16539 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16540 continue;
16541
16542 plane->disable_plane(&plane->base, &crtc->base);
16543 }
16544 }
16545
16546 /* We need to sanitize the plane -> pipe mapping first because this will
16547 * disable the crtc (and hence change the state) if it is wrong. Note
16548 * that gen4+ has a fixed plane -> pipe mapping. */
16549 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16550 bool plane;
16551
16552 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16553 crtc->base.base.id, crtc->base.name);
16554
16555 /* Pipe has the wrong plane attached and the plane is active.
16556 * Temporarily change the plane mapping and disable everything
16557 * ... */
16558 plane = crtc->plane;
16559 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16560 crtc->plane = !plane;
16561 intel_crtc_disable_noatomic(&crtc->base);
16562 crtc->plane = plane;
16563 }
16564
16565 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16566 crtc->pipe == PIPE_A && !crtc->active) {
16567 /* BIOS forgot to enable pipe A, this mostly happens after
16568 * resume. Force-enable the pipe to fix this, the update_dpms
16569 * call below we restore the pipe to the right state, but leave
16570 * the required bits on. */
16571 intel_enable_pipe_a(dev);
16572 }
16573
16574 /* Adjust the state of the output pipe according to whether we
16575 * have active connectors/encoders. */
16576 if (crtc->active && !intel_crtc_has_encoders(crtc))
16577 intel_crtc_disable_noatomic(&crtc->base);
16578
16579 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16580 /*
16581 * We start out with underrun reporting disabled to avoid races.
16582 * For correct bookkeeping mark this on active crtcs.
16583 *
16584 * Also on gmch platforms we dont have any hardware bits to
16585 * disable the underrun reporting. Which means we need to start
16586 * out with underrun reporting disabled also on inactive pipes,
16587 * since otherwise we'll complain about the garbage we read when
16588 * e.g. coming up after runtime pm.
16589 *
16590 * No protection against concurrent access is required - at
16591 * worst a fifo underrun happens which also sets this to false.
16592 */
16593 crtc->cpu_fifo_underrun_disabled = true;
16594 /*
16595 * We track the PCH trancoder underrun reporting state
16596 * within the crtc. With crtc for pipe A housing the underrun
16597 * reporting state for PCH transcoder A, crtc for pipe B housing
16598 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16599 * and marking underrun reporting as disabled for the non-existing
16600 * PCH transcoders B and C would prevent enabling the south
16601 * error interrupt (see cpt_can_enable_serr_int()).
16602 */
16603 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16604 crtc->pch_fifo_underrun_disabled = true;
16605 }
16606 }
16607
16608 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16609 {
16610 struct intel_connector *connector;
16611
16612 /* We need to check both for a crtc link (meaning that the
16613 * encoder is active and trying to read from a pipe) and the
16614 * pipe itself being active. */
16615 bool has_active_crtc = encoder->base.crtc &&
16616 to_intel_crtc(encoder->base.crtc)->active;
16617
16618 connector = intel_encoder_find_connector(encoder);
16619 if (connector && !has_active_crtc) {
16620 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16621 encoder->base.base.id,
16622 encoder->base.name);
16623
16624 /* Connector is active, but has no active pipe. This is
16625 * fallout from our resume register restoring. Disable
16626 * the encoder manually again. */
16627 if (encoder->base.crtc) {
16628 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16629
16630 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16631 encoder->base.base.id,
16632 encoder->base.name);
16633 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16634 if (encoder->post_disable)
16635 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16636 }
16637 encoder->base.crtc = NULL;
16638
16639 /* Inconsistent output/port/pipe state happens presumably due to
16640 * a bug in one of the get_hw_state functions. Or someplace else
16641 * in our code, like the register restore mess on resume. Clamp
16642 * things to off as a safer default. */
16643
16644 connector->base.dpms = DRM_MODE_DPMS_OFF;
16645 connector->base.encoder = NULL;
16646 }
16647 /* Enabled encoders without active connectors will be fixed in
16648 * the crtc fixup. */
16649 }
16650
16651 void i915_redisable_vga_power_on(struct drm_device *dev)
16652 {
16653 struct drm_i915_private *dev_priv = to_i915(dev);
16654 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16655
16656 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16657 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16658 i915_disable_vga(dev);
16659 }
16660 }
16661
16662 void i915_redisable_vga(struct drm_device *dev)
16663 {
16664 struct drm_i915_private *dev_priv = to_i915(dev);
16665
16666 /* This function can be called both from intel_modeset_setup_hw_state or
16667 * at a very early point in our resume sequence, where the power well
16668 * structures are not yet restored. Since this function is at a very
16669 * paranoid "someone might have enabled VGA while we were not looking"
16670 * level, just check if the power well is enabled instead of trying to
16671 * follow the "don't touch the power well if we don't need it" policy
16672 * the rest of the driver uses. */
16673 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16674 return;
16675
16676 i915_redisable_vga_power_on(dev);
16677
16678 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16679 }
16680
16681 static bool primary_get_hw_state(struct intel_plane *plane)
16682 {
16683 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16684
16685 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16686 }
16687
16688 /* FIXME read out full plane state for all planes */
16689 static void readout_plane_state(struct intel_crtc *crtc)
16690 {
16691 struct drm_plane *primary = crtc->base.primary;
16692 struct intel_plane_state *plane_state =
16693 to_intel_plane_state(primary->state);
16694
16695 plane_state->base.visible = crtc->active &&
16696 primary_get_hw_state(to_intel_plane(primary));
16697
16698 if (plane_state->base.visible)
16699 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16700 }
16701
16702 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16703 {
16704 struct drm_i915_private *dev_priv = to_i915(dev);
16705 enum pipe pipe;
16706 struct intel_crtc *crtc;
16707 struct intel_encoder *encoder;
16708 struct intel_connector *connector;
16709 int i;
16710
16711 dev_priv->active_crtcs = 0;
16712
16713 for_each_intel_crtc(dev, crtc) {
16714 struct intel_crtc_state *crtc_state = crtc->config;
16715 int pixclk = 0;
16716
16717 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16718 memset(crtc_state, 0, sizeof(*crtc_state));
16719 crtc_state->base.crtc = &crtc->base;
16720
16721 crtc_state->base.active = crtc_state->base.enable =
16722 dev_priv->display.get_pipe_config(crtc, crtc_state);
16723
16724 crtc->base.enabled = crtc_state->base.enable;
16725 crtc->active = crtc_state->base.active;
16726
16727 if (crtc_state->base.active) {
16728 dev_priv->active_crtcs |= 1 << crtc->pipe;
16729
16730 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16731 pixclk = ilk_pipe_pixel_rate(crtc_state);
16732 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16733 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16734 else
16735 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16736
16737 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16738 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16739 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16740 }
16741
16742 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16743
16744 readout_plane_state(crtc);
16745
16746 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16747 crtc->base.base.id, crtc->base.name,
16748 crtc->active ? "enabled" : "disabled");
16749 }
16750
16751 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16752 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16753
16754 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16755 &pll->config.hw_state);
16756 pll->config.crtc_mask = 0;
16757 for_each_intel_crtc(dev, crtc) {
16758 if (crtc->active && crtc->config->shared_dpll == pll)
16759 pll->config.crtc_mask |= 1 << crtc->pipe;
16760 }
16761 pll->active_mask = pll->config.crtc_mask;
16762
16763 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16764 pll->name, pll->config.crtc_mask, pll->on);
16765 }
16766
16767 for_each_intel_encoder(dev, encoder) {
16768 pipe = 0;
16769
16770 if (encoder->get_hw_state(encoder, &pipe)) {
16771 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16772 encoder->base.crtc = &crtc->base;
16773 crtc->config->output_types |= 1 << encoder->type;
16774 encoder->get_config(encoder, crtc->config);
16775 } else {
16776 encoder->base.crtc = NULL;
16777 }
16778
16779 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16780 encoder->base.base.id,
16781 encoder->base.name,
16782 encoder->base.crtc ? "enabled" : "disabled",
16783 pipe_name(pipe));
16784 }
16785
16786 for_each_intel_connector(dev, connector) {
16787 if (connector->get_hw_state(connector)) {
16788 connector->base.dpms = DRM_MODE_DPMS_ON;
16789
16790 encoder = connector->encoder;
16791 connector->base.encoder = &encoder->base;
16792
16793 if (encoder->base.crtc &&
16794 encoder->base.crtc->state->active) {
16795 /*
16796 * This has to be done during hardware readout
16797 * because anything calling .crtc_disable may
16798 * rely on the connector_mask being accurate.
16799 */
16800 encoder->base.crtc->state->connector_mask |=
16801 1 << drm_connector_index(&connector->base);
16802 encoder->base.crtc->state->encoder_mask |=
16803 1 << drm_encoder_index(&encoder->base);
16804 }
16805
16806 } else {
16807 connector->base.dpms = DRM_MODE_DPMS_OFF;
16808 connector->base.encoder = NULL;
16809 }
16810 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16811 connector->base.base.id,
16812 connector->base.name,
16813 connector->base.encoder ? "enabled" : "disabled");
16814 }
16815
16816 for_each_intel_crtc(dev, crtc) {
16817 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16818
16819 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16820 if (crtc->base.state->active) {
16821 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16822 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16823 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16824
16825 /*
16826 * The initial mode needs to be set in order to keep
16827 * the atomic core happy. It wants a valid mode if the
16828 * crtc's enabled, so we do the above call.
16829 *
16830 * At this point some state updated by the connectors
16831 * in their ->detect() callback has not run yet, so
16832 * no recalculation can be done yet.
16833 *
16834 * Even if we could do a recalculation and modeset
16835 * right now it would cause a double modeset if
16836 * fbdev or userspace chooses a different initial mode.
16837 *
16838 * If that happens, someone indicated they wanted a
16839 * mode change, which means it's safe to do a full
16840 * recalculation.
16841 */
16842 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16843
16844 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16845 update_scanline_offset(crtc);
16846 }
16847
16848 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16849 }
16850 }
16851
16852 /* Scan out the current hw modeset state,
16853 * and sanitizes it to the current state
16854 */
16855 static void
16856 intel_modeset_setup_hw_state(struct drm_device *dev)
16857 {
16858 struct drm_i915_private *dev_priv = to_i915(dev);
16859 enum pipe pipe;
16860 struct intel_crtc *crtc;
16861 struct intel_encoder *encoder;
16862 int i;
16863
16864 intel_modeset_readout_hw_state(dev);
16865
16866 /* HW state is read out, now we need to sanitize this mess. */
16867 for_each_intel_encoder(dev, encoder) {
16868 intel_sanitize_encoder(encoder);
16869 }
16870
16871 for_each_pipe(dev_priv, pipe) {
16872 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16873 intel_sanitize_crtc(crtc);
16874 intel_dump_pipe_config(crtc, crtc->config,
16875 "[setup_hw_state]");
16876 }
16877
16878 intel_modeset_update_connector_atomic_state(dev);
16879
16880 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16881 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16882
16883 if (!pll->on || pll->active_mask)
16884 continue;
16885
16886 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16887
16888 pll->funcs.disable(dev_priv, pll);
16889 pll->on = false;
16890 }
16891
16892 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16893 vlv_wm_get_hw_state(dev);
16894 else if (IS_GEN9(dev))
16895 skl_wm_get_hw_state(dev);
16896 else if (HAS_PCH_SPLIT(dev))
16897 ilk_wm_get_hw_state(dev);
16898
16899 for_each_intel_crtc(dev, crtc) {
16900 unsigned long put_domains;
16901
16902 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16903 if (WARN_ON(put_domains))
16904 modeset_put_power_domains(dev_priv, put_domains);
16905 }
16906 intel_display_set_init_power(dev_priv, false);
16907
16908 intel_fbc_init_pipe_state(dev_priv);
16909 }
16910
16911 void intel_display_resume(struct drm_device *dev)
16912 {
16913 struct drm_i915_private *dev_priv = to_i915(dev);
16914 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16915 struct drm_modeset_acquire_ctx ctx;
16916 int ret;
16917
16918 dev_priv->modeset_restore_state = NULL;
16919 if (state)
16920 state->acquire_ctx = &ctx;
16921
16922 /*
16923 * This is a cludge because with real atomic modeset mode_config.mutex
16924 * won't be taken. Unfortunately some probed state like
16925 * audio_codec_enable is still protected by mode_config.mutex, so lock
16926 * it here for now.
16927 */
16928 mutex_lock(&dev->mode_config.mutex);
16929 drm_modeset_acquire_init(&ctx, 0);
16930
16931 while (1) {
16932 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16933 if (ret != -EDEADLK)
16934 break;
16935
16936 drm_modeset_backoff(&ctx);
16937 }
16938
16939 if (!ret)
16940 ret = __intel_display_resume(dev, state);
16941
16942 drm_modeset_drop_locks(&ctx);
16943 drm_modeset_acquire_fini(&ctx);
16944 mutex_unlock(&dev->mode_config.mutex);
16945
16946 if (ret) {
16947 DRM_ERROR("Restoring old state failed with %i\n", ret);
16948 drm_atomic_state_free(state);
16949 }
16950 }
16951
16952 void intel_modeset_gem_init(struct drm_device *dev)
16953 {
16954 struct drm_i915_private *dev_priv = to_i915(dev);
16955 struct drm_crtc *c;
16956 struct drm_i915_gem_object *obj;
16957
16958 intel_init_gt_powersave(dev_priv);
16959
16960 intel_modeset_init_hw(dev);
16961
16962 intel_setup_overlay(dev_priv);
16963
16964 /*
16965 * Make sure any fbs we allocated at startup are properly
16966 * pinned & fenced. When we do the allocation it's too early
16967 * for this.
16968 */
16969 for_each_crtc(dev, c) {
16970 struct i915_vma *vma;
16971
16972 obj = intel_fb_obj(c->primary->fb);
16973 if (obj == NULL)
16974 continue;
16975
16976 mutex_lock(&dev->struct_mutex);
16977 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
16978 c->primary->state->rotation);
16979 mutex_unlock(&dev->struct_mutex);
16980 if (IS_ERR(vma)) {
16981 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16982 to_intel_crtc(c)->pipe);
16983 drm_framebuffer_unreference(c->primary->fb);
16984 c->primary->fb = NULL;
16985 c->primary->crtc = c->primary->state->crtc = NULL;
16986 update_state_fb(c->primary);
16987 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16988 }
16989 }
16990 }
16991
16992 int intel_connector_register(struct drm_connector *connector)
16993 {
16994 struct intel_connector *intel_connector = to_intel_connector(connector);
16995 int ret;
16996
16997 ret = intel_backlight_device_register(intel_connector);
16998 if (ret)
16999 goto err;
17000
17001 return 0;
17002
17003 err:
17004 return ret;
17005 }
17006
17007 void intel_connector_unregister(struct drm_connector *connector)
17008 {
17009 struct intel_connector *intel_connector = to_intel_connector(connector);
17010
17011 intel_backlight_device_unregister(intel_connector);
17012 intel_panel_destroy_backlight(connector);
17013 }
17014
17015 void intel_modeset_cleanup(struct drm_device *dev)
17016 {
17017 struct drm_i915_private *dev_priv = to_i915(dev);
17018
17019 intel_disable_gt_powersave(dev_priv);
17020
17021 /*
17022 * Interrupts and polling as the first thing to avoid creating havoc.
17023 * Too much stuff here (turning of connectors, ...) would
17024 * experience fancy races otherwise.
17025 */
17026 intel_irq_uninstall(dev_priv);
17027
17028 /*
17029 * Due to the hpd irq storm handling the hotplug work can re-arm the
17030 * poll handlers. Hence disable polling after hpd handling is shut down.
17031 */
17032 drm_kms_helper_poll_fini(dev);
17033
17034 intel_unregister_dsm_handler();
17035
17036 intel_fbc_global_disable(dev_priv);
17037
17038 /* flush any delayed tasks or pending work */
17039 flush_scheduled_work();
17040
17041 drm_mode_config_cleanup(dev);
17042
17043 intel_cleanup_overlay(dev_priv);
17044
17045 intel_cleanup_gt_powersave(dev_priv);
17046
17047 intel_teardown_gmbus(dev);
17048 }
17049
17050 void intel_connector_attach_encoder(struct intel_connector *connector,
17051 struct intel_encoder *encoder)
17052 {
17053 connector->encoder = encoder;
17054 drm_mode_connector_attach_encoder(&connector->base,
17055 &encoder->base);
17056 }
17057
17058 /*
17059 * set vga decode state - true == enable VGA decode
17060 */
17061 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17062 {
17063 struct drm_i915_private *dev_priv = to_i915(dev);
17064 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17065 u16 gmch_ctrl;
17066
17067 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17068 DRM_ERROR("failed to read control word\n");
17069 return -EIO;
17070 }
17071
17072 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17073 return 0;
17074
17075 if (state)
17076 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17077 else
17078 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17079
17080 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17081 DRM_ERROR("failed to write control word\n");
17082 return -EIO;
17083 }
17084
17085 return 0;
17086 }
17087
17088 struct intel_display_error_state {
17089
17090 u32 power_well_driver;
17091
17092 int num_transcoders;
17093
17094 struct intel_cursor_error_state {
17095 u32 control;
17096 u32 position;
17097 u32 base;
17098 u32 size;
17099 } cursor[I915_MAX_PIPES];
17100
17101 struct intel_pipe_error_state {
17102 bool power_domain_on;
17103 u32 source;
17104 u32 stat;
17105 } pipe[I915_MAX_PIPES];
17106
17107 struct intel_plane_error_state {
17108 u32 control;
17109 u32 stride;
17110 u32 size;
17111 u32 pos;
17112 u32 addr;
17113 u32 surface;
17114 u32 tile_offset;
17115 } plane[I915_MAX_PIPES];
17116
17117 struct intel_transcoder_error_state {
17118 bool power_domain_on;
17119 enum transcoder cpu_transcoder;
17120
17121 u32 conf;
17122
17123 u32 htotal;
17124 u32 hblank;
17125 u32 hsync;
17126 u32 vtotal;
17127 u32 vblank;
17128 u32 vsync;
17129 } transcoder[4];
17130 };
17131
17132 struct intel_display_error_state *
17133 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17134 {
17135 struct intel_display_error_state *error;
17136 int transcoders[] = {
17137 TRANSCODER_A,
17138 TRANSCODER_B,
17139 TRANSCODER_C,
17140 TRANSCODER_EDP,
17141 };
17142 int i;
17143
17144 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17145 return NULL;
17146
17147 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17148 if (error == NULL)
17149 return NULL;
17150
17151 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17152 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17153
17154 for_each_pipe(dev_priv, i) {
17155 error->pipe[i].power_domain_on =
17156 __intel_display_power_is_enabled(dev_priv,
17157 POWER_DOMAIN_PIPE(i));
17158 if (!error->pipe[i].power_domain_on)
17159 continue;
17160
17161 error->cursor[i].control = I915_READ(CURCNTR(i));
17162 error->cursor[i].position = I915_READ(CURPOS(i));
17163 error->cursor[i].base = I915_READ(CURBASE(i));
17164
17165 error->plane[i].control = I915_READ(DSPCNTR(i));
17166 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17167 if (INTEL_GEN(dev_priv) <= 3) {
17168 error->plane[i].size = I915_READ(DSPSIZE(i));
17169 error->plane[i].pos = I915_READ(DSPPOS(i));
17170 }
17171 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17172 error->plane[i].addr = I915_READ(DSPADDR(i));
17173 if (INTEL_GEN(dev_priv) >= 4) {
17174 error->plane[i].surface = I915_READ(DSPSURF(i));
17175 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17176 }
17177
17178 error->pipe[i].source = I915_READ(PIPESRC(i));
17179
17180 if (HAS_GMCH_DISPLAY(dev_priv))
17181 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17182 }
17183
17184 /* Note: this does not include DSI transcoders. */
17185 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17186 if (HAS_DDI(dev_priv))
17187 error->num_transcoders++; /* Account for eDP. */
17188
17189 for (i = 0; i < error->num_transcoders; i++) {
17190 enum transcoder cpu_transcoder = transcoders[i];
17191
17192 error->transcoder[i].power_domain_on =
17193 __intel_display_power_is_enabled(dev_priv,
17194 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17195 if (!error->transcoder[i].power_domain_on)
17196 continue;
17197
17198 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17199
17200 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17201 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17202 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17203 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17204 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17205 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17206 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17207 }
17208
17209 return error;
17210 }
17211
17212 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17213
17214 void
17215 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17216 struct drm_device *dev,
17217 struct intel_display_error_state *error)
17218 {
17219 struct drm_i915_private *dev_priv = to_i915(dev);
17220 int i;
17221
17222 if (!error)
17223 return;
17224
17225 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17226 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17227 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17228 error->power_well_driver);
17229 for_each_pipe(dev_priv, i) {
17230 err_printf(m, "Pipe [%d]:\n", i);
17231 err_printf(m, " Power: %s\n",
17232 onoff(error->pipe[i].power_domain_on));
17233 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17234 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17235
17236 err_printf(m, "Plane [%d]:\n", i);
17237 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17238 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17239 if (INTEL_INFO(dev)->gen <= 3) {
17240 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17241 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17242 }
17243 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17244 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17245 if (INTEL_INFO(dev)->gen >= 4) {
17246 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17247 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17248 }
17249
17250 err_printf(m, "Cursor [%d]:\n", i);
17251 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17252 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17253 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17254 }
17255
17256 for (i = 0; i < error->num_transcoders; i++) {
17257 err_printf(m, "CPU transcoder: %s\n",
17258 transcoder_name(error->transcoder[i].cpu_transcoder));
17259 err_printf(m, " Power: %s\n",
17260 onoff(error->transcoder[i].power_domain_on));
17261 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17262 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17263 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17264 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17265 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17266 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17267 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
17268 }
17269 }
Linux kernel - Deliverables
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