2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_gem_dmabuf.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
51 static bool is_mmio_work(struct intel_flip_work
*work
)
53 return work
->mmio_work
.func
;
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats
[] = {
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats
[] = {
70 DRM_FORMAT_XRGB2101010
,
71 DRM_FORMAT_XBGR2101010
,
74 static const uint32_t skl_primary_formats
[] = {
81 DRM_FORMAT_XRGB2101010
,
82 DRM_FORMAT_XBGR2101010
,
90 static const uint32_t intel_cursor_formats
[] = {
94 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
95 struct intel_crtc_state
*pipe_config
);
96 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
97 struct intel_crtc_state
*pipe_config
);
99 static int intel_framebuffer_init(struct drm_device
*dev
,
100 struct intel_framebuffer
*ifb
,
101 struct drm_mode_fb_cmd2
*mode_cmd
,
102 struct drm_i915_gem_object
*obj
);
103 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
104 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
105 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
107 struct intel_link_m_n
*m_n
,
108 struct intel_link_m_n
*m2_n2
);
109 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
110 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
111 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
112 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
113 const struct intel_crtc_state
*pipe_config
);
114 static void chv_prepare_pll(struct intel_crtc
*crtc
,
115 const struct intel_crtc_state
*pipe_config
);
116 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
117 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
118 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
119 struct intel_crtc_state
*crtc_state
);
120 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
121 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
122 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
123 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
125 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
);
126 static int bxt_calc_cdclk(int max_pixclk
);
131 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 int p2_slow
, p2_fast
;
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
142 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv
->sb_lock
);
146 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
147 CCK_FUSE_HPLL_FREQ_MASK
;
148 mutex_unlock(&dev_priv
->sb_lock
);
150 return vco_freq
[hpll_freq
] * 1000;
153 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
154 const char *name
, u32 reg
, int ref_freq
)
159 mutex_lock(&dev_priv
->sb_lock
);
160 val
= vlv_cck_read(dev_priv
, reg
);
161 mutex_unlock(&dev_priv
->sb_lock
);
163 divider
= val
& CCK_FREQUENCY_VALUES
;
165 WARN((val
& CCK_FREQUENCY_STATUS
) !=
166 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
167 "%s change in progress\n", name
);
169 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
173 const char *name
, u32 reg
)
175 if (dev_priv
->hpll_freq
== 0)
176 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
178 return vlv_get_cck_clock(dev_priv
, name
, reg
,
179 dev_priv
->hpll_freq
);
183 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
185 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
189 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL
);
197 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg
= I915_READ(CLKCFG
);
203 switch (clkcfg
& CLKCFG_FSB_MASK
) {
212 case CLKCFG_FSB_1067
:
214 case CLKCFG_FSB_1333
:
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600
:
218 case CLKCFG_FSB_1600_ALT
:
225 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
227 if (HAS_PCH_SPLIT(dev_priv
))
228 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
229 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
230 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
231 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
232 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
234 return; /* no rawclk on other platforms, or no need to know it */
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
239 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
241 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
244 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
245 CCK_CZ_CLOCK_CONTROL
);
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
250 static inline u32
/* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
252 const struct intel_crtc_state
*pipe_config
)
254 if (HAS_DDI(dev_priv
))
255 return pipe_config
->port_clock
; /* SPLL */
256 else if (IS_GEN5(dev_priv
))
257 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
262 static const struct intel_limit intel_limits_i8xx_dac
= {
263 .dot
= { .min
= 25000, .max
= 350000 },
264 .vco
= { .min
= 908000, .max
= 1512000 },
265 .n
= { .min
= 2, .max
= 16 },
266 .m
= { .min
= 96, .max
= 140 },
267 .m1
= { .min
= 18, .max
= 26 },
268 .m2
= { .min
= 6, .max
= 16 },
269 .p
= { .min
= 4, .max
= 128 },
270 .p1
= { .min
= 2, .max
= 33 },
271 .p2
= { .dot_limit
= 165000,
272 .p2_slow
= 4, .p2_fast
= 2 },
275 static const struct intel_limit intel_limits_i8xx_dvo
= {
276 .dot
= { .min
= 25000, .max
= 350000 },
277 .vco
= { .min
= 908000, .max
= 1512000 },
278 .n
= { .min
= 2, .max
= 16 },
279 .m
= { .min
= 96, .max
= 140 },
280 .m1
= { .min
= 18, .max
= 26 },
281 .m2
= { .min
= 6, .max
= 16 },
282 .p
= { .min
= 4, .max
= 128 },
283 .p1
= { .min
= 2, .max
= 33 },
284 .p2
= { .dot_limit
= 165000,
285 .p2_slow
= 4, .p2_fast
= 4 },
288 static const struct intel_limit intel_limits_i8xx_lvds
= {
289 .dot
= { .min
= 25000, .max
= 350000 },
290 .vco
= { .min
= 908000, .max
= 1512000 },
291 .n
= { .min
= 2, .max
= 16 },
292 .m
= { .min
= 96, .max
= 140 },
293 .m1
= { .min
= 18, .max
= 26 },
294 .m2
= { .min
= 6, .max
= 16 },
295 .p
= { .min
= 4, .max
= 128 },
296 .p1
= { .min
= 1, .max
= 6 },
297 .p2
= { .dot_limit
= 165000,
298 .p2_slow
= 14, .p2_fast
= 7 },
301 static const struct intel_limit intel_limits_i9xx_sdvo
= {
302 .dot
= { .min
= 20000, .max
= 400000 },
303 .vco
= { .min
= 1400000, .max
= 2800000 },
304 .n
= { .min
= 1, .max
= 6 },
305 .m
= { .min
= 70, .max
= 120 },
306 .m1
= { .min
= 8, .max
= 18 },
307 .m2
= { .min
= 3, .max
= 7 },
308 .p
= { .min
= 5, .max
= 80 },
309 .p1
= { .min
= 1, .max
= 8 },
310 .p2
= { .dot_limit
= 200000,
311 .p2_slow
= 10, .p2_fast
= 5 },
314 static const struct intel_limit intel_limits_i9xx_lvds
= {
315 .dot
= { .min
= 20000, .max
= 400000 },
316 .vco
= { .min
= 1400000, .max
= 2800000 },
317 .n
= { .min
= 1, .max
= 6 },
318 .m
= { .min
= 70, .max
= 120 },
319 .m1
= { .min
= 8, .max
= 18 },
320 .m2
= { .min
= 3, .max
= 7 },
321 .p
= { .min
= 7, .max
= 98 },
322 .p1
= { .min
= 1, .max
= 8 },
323 .p2
= { .dot_limit
= 112000,
324 .p2_slow
= 14, .p2_fast
= 7 },
328 static const struct intel_limit intel_limits_g4x_sdvo
= {
329 .dot
= { .min
= 25000, .max
= 270000 },
330 .vco
= { .min
= 1750000, .max
= 3500000},
331 .n
= { .min
= 1, .max
= 4 },
332 .m
= { .min
= 104, .max
= 138 },
333 .m1
= { .min
= 17, .max
= 23 },
334 .m2
= { .min
= 5, .max
= 11 },
335 .p
= { .min
= 10, .max
= 30 },
336 .p1
= { .min
= 1, .max
= 3},
337 .p2
= { .dot_limit
= 270000,
343 static const struct intel_limit intel_limits_g4x_hdmi
= {
344 .dot
= { .min
= 22000, .max
= 400000 },
345 .vco
= { .min
= 1750000, .max
= 3500000},
346 .n
= { .min
= 1, .max
= 4 },
347 .m
= { .min
= 104, .max
= 138 },
348 .m1
= { .min
= 16, .max
= 23 },
349 .m2
= { .min
= 5, .max
= 11 },
350 .p
= { .min
= 5, .max
= 80 },
351 .p1
= { .min
= 1, .max
= 8},
352 .p2
= { .dot_limit
= 165000,
353 .p2_slow
= 10, .p2_fast
= 5 },
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
357 .dot
= { .min
= 20000, .max
= 115000 },
358 .vco
= { .min
= 1750000, .max
= 3500000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 104, .max
= 138 },
361 .m1
= { .min
= 17, .max
= 23 },
362 .m2
= { .min
= 5, .max
= 11 },
363 .p
= { .min
= 28, .max
= 112 },
364 .p1
= { .min
= 2, .max
= 8 },
365 .p2
= { .dot_limit
= 0,
366 .p2_slow
= 14, .p2_fast
= 14
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
371 .dot
= { .min
= 80000, .max
= 224000 },
372 .vco
= { .min
= 1750000, .max
= 3500000 },
373 .n
= { .min
= 1, .max
= 3 },
374 .m
= { .min
= 104, .max
= 138 },
375 .m1
= { .min
= 17, .max
= 23 },
376 .m2
= { .min
= 5, .max
= 11 },
377 .p
= { .min
= 14, .max
= 42 },
378 .p1
= { .min
= 2, .max
= 6 },
379 .p2
= { .dot_limit
= 0,
380 .p2_slow
= 7, .p2_fast
= 7
384 static const struct intel_limit intel_limits_pineview_sdvo
= {
385 .dot
= { .min
= 20000, .max
= 400000},
386 .vco
= { .min
= 1700000, .max
= 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n
= { .min
= 3, .max
= 6 },
389 .m
= { .min
= 2, .max
= 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1
= { .min
= 0, .max
= 0 },
392 .m2
= { .min
= 0, .max
= 254 },
393 .p
= { .min
= 5, .max
= 80 },
394 .p1
= { .min
= 1, .max
= 8 },
395 .p2
= { .dot_limit
= 200000,
396 .p2_slow
= 10, .p2_fast
= 5 },
399 static const struct intel_limit intel_limits_pineview_lvds
= {
400 .dot
= { .min
= 20000, .max
= 400000 },
401 .vco
= { .min
= 1700000, .max
= 3500000 },
402 .n
= { .min
= 3, .max
= 6 },
403 .m
= { .min
= 2, .max
= 256 },
404 .m1
= { .min
= 0, .max
= 0 },
405 .m2
= { .min
= 0, .max
= 254 },
406 .p
= { .min
= 7, .max
= 112 },
407 .p1
= { .min
= 1, .max
= 8 },
408 .p2
= { .dot_limit
= 112000,
409 .p2_slow
= 14, .p2_fast
= 14 },
412 /* Ironlake / Sandybridge
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
417 static const struct intel_limit intel_limits_ironlake_dac
= {
418 .dot
= { .min
= 25000, .max
= 350000 },
419 .vco
= { .min
= 1760000, .max
= 3510000 },
420 .n
= { .min
= 1, .max
= 5 },
421 .m
= { .min
= 79, .max
= 127 },
422 .m1
= { .min
= 12, .max
= 22 },
423 .m2
= { .min
= 5, .max
= 9 },
424 .p
= { .min
= 5, .max
= 80 },
425 .p1
= { .min
= 1, .max
= 8 },
426 .p2
= { .dot_limit
= 225000,
427 .p2_slow
= 10, .p2_fast
= 5 },
430 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
431 .dot
= { .min
= 25000, .max
= 350000 },
432 .vco
= { .min
= 1760000, .max
= 3510000 },
433 .n
= { .min
= 1, .max
= 3 },
434 .m
= { .min
= 79, .max
= 118 },
435 .m1
= { .min
= 12, .max
= 22 },
436 .m2
= { .min
= 5, .max
= 9 },
437 .p
= { .min
= 28, .max
= 112 },
438 .p1
= { .min
= 2, .max
= 8 },
439 .p2
= { .dot_limit
= 225000,
440 .p2_slow
= 14, .p2_fast
= 14 },
443 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
444 .dot
= { .min
= 25000, .max
= 350000 },
445 .vco
= { .min
= 1760000, .max
= 3510000 },
446 .n
= { .min
= 1, .max
= 3 },
447 .m
= { .min
= 79, .max
= 127 },
448 .m1
= { .min
= 12, .max
= 22 },
449 .m2
= { .min
= 5, .max
= 9 },
450 .p
= { .min
= 14, .max
= 56 },
451 .p1
= { .min
= 2, .max
= 8 },
452 .p2
= { .dot_limit
= 225000,
453 .p2_slow
= 7, .p2_fast
= 7 },
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
458 .dot
= { .min
= 25000, .max
= 350000 },
459 .vco
= { .min
= 1760000, .max
= 3510000 },
460 .n
= { .min
= 1, .max
= 2 },
461 .m
= { .min
= 79, .max
= 126 },
462 .m1
= { .min
= 12, .max
= 22 },
463 .m2
= { .min
= 5, .max
= 9 },
464 .p
= { .min
= 28, .max
= 112 },
465 .p1
= { .min
= 2, .max
= 8 },
466 .p2
= { .dot_limit
= 225000,
467 .p2_slow
= 14, .p2_fast
= 14 },
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
471 .dot
= { .min
= 25000, .max
= 350000 },
472 .vco
= { .min
= 1760000, .max
= 3510000 },
473 .n
= { .min
= 1, .max
= 3 },
474 .m
= { .min
= 79, .max
= 126 },
475 .m1
= { .min
= 12, .max
= 22 },
476 .m2
= { .min
= 5, .max
= 9 },
477 .p
= { .min
= 14, .max
= 42 },
478 .p1
= { .min
= 2, .max
= 6 },
479 .p2
= { .dot_limit
= 225000,
480 .p2_slow
= 7, .p2_fast
= 7 },
483 static const struct intel_limit intel_limits_vlv
= {
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
490 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
491 .vco
= { .min
= 4000000, .max
= 6000000 },
492 .n
= { .min
= 1, .max
= 7 },
493 .m1
= { .min
= 2, .max
= 3 },
494 .m2
= { .min
= 11, .max
= 156 },
495 .p1
= { .min
= 2, .max
= 3 },
496 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
499 static const struct intel_limit intel_limits_chv
= {
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
506 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
507 .vco
= { .min
= 4800000, .max
= 6480000 },
508 .n
= { .min
= 1, .max
= 1 },
509 .m1
= { .min
= 2, .max
= 2 },
510 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
511 .p1
= { .min
= 2, .max
= 4 },
512 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
515 static const struct intel_limit intel_limits_bxt
= {
516 /* FIXME: find real dot limits */
517 .dot
= { .min
= 0, .max
= INT_MAX
},
518 .vco
= { .min
= 4800000, .max
= 6700000 },
519 .n
= { .min
= 1, .max
= 1 },
520 .m1
= { .min
= 2, .max
= 2 },
521 /* FIXME: find real m2 limits */
522 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
523 .p1
= { .min
= 2, .max
= 4 },
524 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
528 needs_modeset(struct drm_crtc_state
*state
)
530 return drm_atomic_crtc_needs_modeset(state
);
534 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
535 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
536 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
537 * The helpers' return value is the rate of the clock that is fed to the
538 * display engine's pipe which can be the above fast dot clock rate or a
539 * divided-down version of it.
541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
542 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
544 clock
->m
= clock
->m2
+ 2;
545 clock
->p
= clock
->p1
* clock
->p2
;
546 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
548 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
549 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
554 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
556 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
559 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
561 clock
->m
= i9xx_dpll_compute_m(clock
);
562 clock
->p
= clock
->p1
* clock
->p2
;
563 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
565 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
566 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
571 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
573 clock
->m
= clock
->m1
* clock
->m2
;
574 clock
->p
= clock
->p1
* clock
->p2
;
575 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
577 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
578 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
580 return clock
->dot
/ 5;
583 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
585 clock
->m
= clock
->m1
* clock
->m2
;
586 clock
->p
= clock
->p1
* clock
->p2
;
587 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
589 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
591 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
593 return clock
->dot
/ 5;
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
602 static bool intel_PLL_is_valid(struct drm_device
*dev
,
603 const struct intel_limit
*limit
,
604 const struct dpll
*clock
)
606 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
607 INTELPllInvalid("n out of range\n");
608 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
613 INTELPllInvalid("m1 out of range\n");
615 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) &&
616 !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
))
617 if (clock
->m1
<= clock
->m2
)
618 INTELPllInvalid("m1 <= m2\n");
620 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
)) {
621 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
622 INTELPllInvalid("p out of range\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 i9xx_select_p2_div(const struct intel_limit
*limit
,
640 const struct intel_crtc_state
*crtc_state
,
643 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
645 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
647 * For LVDS just rely on its current settings for dual-channel.
648 * We haven't figured out how to reliably set up different
649 * single/dual channel state, if we even can.
651 if (intel_is_dual_link_lvds(dev
))
652 return limit
->p2
.p2_fast
;
654 return limit
->p2
.p2_slow
;
656 if (target
< limit
->p2
.dot_limit
)
657 return limit
->p2
.p2_slow
;
659 return limit
->p2
.p2_fast
;
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 * Target and reference clocks are specified in kHz.
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
674 i9xx_find_best_dpll(const struct intel_limit
*limit
,
675 struct intel_crtc_state
*crtc_state
,
676 int target
, int refclk
, struct dpll
*match_clock
,
677 struct dpll
*best_clock
)
679 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
683 memset(best_clock
, 0, sizeof(*best_clock
));
685 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
687 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
689 for (clock
.m2
= limit
->m2
.min
;
690 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
691 if (clock
.m2
>= clock
.m1
)
693 for (clock
.n
= limit
->n
.min
;
694 clock
.n
<= limit
->n
.max
; clock
.n
++) {
695 for (clock
.p1
= limit
->p1
.min
;
696 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
699 i9xx_calc_dpll_params(refclk
, &clock
);
700 if (!intel_PLL_is_valid(dev
, limit
,
704 clock
.p
!= match_clock
->p
)
707 this_err
= abs(clock
.dot
- target
);
708 if (this_err
< err
) {
717 return (err
!= target
);
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 * Target and reference clocks are specified in kHz.
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
731 pnv_find_best_dpll(const struct intel_limit
*limit
,
732 struct intel_crtc_state
*crtc_state
,
733 int target
, int refclk
, struct dpll
*match_clock
,
734 struct dpll
*best_clock
)
736 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
740 memset(best_clock
, 0, sizeof(*best_clock
));
742 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
744 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
746 for (clock
.m2
= limit
->m2
.min
;
747 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
748 for (clock
.n
= limit
->n
.min
;
749 clock
.n
<= limit
->n
.max
; clock
.n
++) {
750 for (clock
.p1
= limit
->p1
.min
;
751 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
754 pnv_calc_dpll_params(refclk
, &clock
);
755 if (!intel_PLL_is_valid(dev
, limit
,
759 clock
.p
!= match_clock
->p
)
762 this_err
= abs(clock
.dot
- target
);
763 if (this_err
< err
) {
772 return (err
!= target
);
776 * Returns a set of divisors for the desired target clock with the given
777 * refclk, or FALSE. The returned values represent the clock equation:
778 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 * Target and reference clocks are specified in kHz.
782 * If match_clock is provided, then best_clock P divider must match the P
783 * divider from @match_clock used for LVDS downclocking.
786 g4x_find_best_dpll(const struct intel_limit
*limit
,
787 struct intel_crtc_state
*crtc_state
,
788 int target
, int refclk
, struct dpll
*match_clock
,
789 struct dpll
*best_clock
)
791 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
795 /* approximately equals target * 0.00585 */
796 int err_most
= (target
>> 8) + (target
>> 9);
798 memset(best_clock
, 0, sizeof(*best_clock
));
800 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
802 max_n
= limit
->n
.max
;
803 /* based on hardware requirement, prefer smaller n to precision */
804 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
805 /* based on hardware requirement, prefere larger m1,m2 */
806 for (clock
.m1
= limit
->m1
.max
;
807 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
808 for (clock
.m2
= limit
->m2
.max
;
809 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
810 for (clock
.p1
= limit
->p1
.max
;
811 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
814 i9xx_calc_dpll_params(refclk
, &clock
);
815 if (!intel_PLL_is_valid(dev
, limit
,
819 this_err
= abs(clock
.dot
- target
);
820 if (this_err
< err_most
) {
834 * Check if the calculated PLL configuration is more optimal compared to the
835 * best configuration and error found so far. Return the calculated error.
837 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
838 const struct dpll
*calculated_clock
,
839 const struct dpll
*best_clock
,
840 unsigned int best_error_ppm
,
841 unsigned int *error_ppm
)
844 * For CHV ignore the error and consider only the P value.
845 * Prefer a bigger P value based on HW requirements.
847 if (IS_CHERRYVIEW(dev
)) {
850 return calculated_clock
->p
> best_clock
->p
;
853 if (WARN_ON_ONCE(!target_freq
))
856 *error_ppm
= div_u64(1000000ULL *
857 abs(target_freq
- calculated_clock
->dot
),
860 * Prefer a better P value over a better (smaller) error if the error
861 * is small. Ensure this preference for future configurations too by
862 * setting the error to 0.
864 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
870 return *error_ppm
+ 10 < best_error_ppm
;
874 * Returns a set of divisors for the desired target clock with the given
875 * refclk, or FALSE. The returned values represent the clock equation:
876 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
879 vlv_find_best_dpll(const struct intel_limit
*limit
,
880 struct intel_crtc_state
*crtc_state
,
881 int target
, int refclk
, struct dpll
*match_clock
,
882 struct dpll
*best_clock
)
884 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
885 struct drm_device
*dev
= crtc
->base
.dev
;
887 unsigned int bestppm
= 1000000;
888 /* min update 19.2 MHz */
889 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
892 target
*= 5; /* fast clock */
894 memset(best_clock
, 0, sizeof(*best_clock
));
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
898 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
899 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
900 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
901 clock
.p
= clock
.p1
* clock
.p2
;
902 /* based on hardware requirement, prefer bigger m1,m2 values */
903 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
906 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
909 vlv_calc_dpll_params(refclk
, &clock
);
911 if (!intel_PLL_is_valid(dev
, limit
,
915 if (!vlv_PLL_is_optimal(dev
, target
,
933 * Returns a set of divisors for the desired target clock with the given
934 * refclk, or FALSE. The returned values represent the clock equation:
935 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
938 chv_find_best_dpll(const struct intel_limit
*limit
,
939 struct intel_crtc_state
*crtc_state
,
940 int target
, int refclk
, struct dpll
*match_clock
,
941 struct dpll
*best_clock
)
943 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
944 struct drm_device
*dev
= crtc
->base
.dev
;
945 unsigned int best_error_ppm
;
950 memset(best_clock
, 0, sizeof(*best_clock
));
951 best_error_ppm
= 1000000;
954 * Based on hardware doc, the n always set to 1, and m1 always
955 * set to 2. If requires to support 200Mhz refclk, we need to
956 * revisit this because n may not 1 anymore.
958 clock
.n
= 1, clock
.m1
= 2;
959 target
*= 5; /* fast clock */
961 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
962 for (clock
.p2
= limit
->p2
.p2_fast
;
963 clock
.p2
>= limit
->p2
.p2_slow
;
964 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
965 unsigned int error_ppm
;
967 clock
.p
= clock
.p1
* clock
.p2
;
969 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
970 clock
.n
) << 22, refclk
* clock
.m1
);
972 if (m2
> INT_MAX
/clock
.m1
)
977 chv_calc_dpll_params(refclk
, &clock
);
979 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
982 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
983 best_error_ppm
, &error_ppm
))
987 best_error_ppm
= error_ppm
;
995 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
996 struct dpll
*best_clock
)
999 const struct intel_limit
*limit
= &intel_limits_bxt
;
1001 return chv_find_best_dpll(limit
, crtc_state
,
1002 target_clock
, refclk
, NULL
, best_clock
);
1005 bool intel_crtc_active(struct drm_crtc
*crtc
)
1007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1009 /* Be paranoid as we can arrive here with only partial
1010 * state retrieved from the hardware during setup.
1012 * We can ditch the adjusted_mode.crtc_clock check as soon
1013 * as Haswell has gained clock readout/fastboot support.
1015 * We can ditch the crtc->primary->fb check as soon as we can
1016 * properly reconstruct framebuffers.
1018 * FIXME: The intel_crtc->active here should be switched to
1019 * crtc->state->active once we have proper CRTC states wired up
1022 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1023 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1026 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1029 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1030 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1032 return intel_crtc
->config
->cpu_transcoder
;
1035 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1038 i915_reg_t reg
= PIPEDSL(pipe
);
1043 line_mask
= DSL_LINEMASK_GEN2
;
1045 line_mask
= DSL_LINEMASK_GEN3
;
1047 line1
= I915_READ(reg
) & line_mask
;
1049 line2
= I915_READ(reg
) & line_mask
;
1051 return line1
== line2
;
1055 * intel_wait_for_pipe_off - wait for pipe to turn off
1056 * @crtc: crtc whose pipe to wait for
1058 * After disabling a pipe, we can't wait for vblank in the usual way,
1059 * spinning on the vblank interrupt status bit, since we won't actually
1060 * see an interrupt when the pipe is disabled.
1062 * On Gen4 and above:
1063 * wait for the pipe register state bit to turn off
1066 * wait for the display line value to settle (it usually
1067 * ends up stopping at the start of the next frame).
1070 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1072 struct drm_device
*dev
= crtc
->base
.dev
;
1073 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1074 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1075 enum pipe pipe
= crtc
->pipe
;
1077 if (INTEL_INFO(dev
)->gen
>= 4) {
1078 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1080 /* Wait for the Pipe State to go off */
1081 if (intel_wait_for_register(dev_priv
,
1082 reg
, I965_PIPECONF_ACTIVE
, 0,
1084 WARN(1, "pipe_off wait timed out\n");
1086 /* Wait for the display line to settle */
1087 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1088 WARN(1, "pipe_off wait timed out\n");
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
)
1099 val
= I915_READ(DPLL(pipe
));
1100 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1101 I915_STATE_WARN(cur_state
!= state
,
1102 "PLL state assertion failure (expected %s, current %s)\n",
1103 onoff(state
), onoff(cur_state
));
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1112 mutex_lock(&dev_priv
->sb_lock
);
1113 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1114 mutex_unlock(&dev_priv
->sb_lock
);
1116 cur_state
= val
& DSI_PLL_VCO_EN
;
1117 I915_STATE_WARN(cur_state
!= state
,
1118 "DSI PLL state assertion failure (expected %s, current %s)\n",
1119 onoff(state
), onoff(cur_state
));
1122 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1123 enum pipe pipe
, bool state
)
1126 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1129 if (HAS_DDI(dev_priv
)) {
1130 /* DDI does not have a specific FDI_TX register */
1131 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1132 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1134 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 I915_STATE_WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 onoff(state
), onoff(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1150 val
= I915_READ(FDI_RX_CTL(pipe
));
1151 cur_state
= !!(val
& FDI_RX_ENABLE
);
1152 I915_STATE_WARN(cur_state
!= state
,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 onoff(state
), onoff(cur_state
));
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (IS_GEN5(dev_priv
))
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
))
1172 val
= I915_READ(FDI_TX_CTL(pipe
));
1173 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1177 enum pipe pipe
, bool state
)
1182 val
= I915_READ(FDI_RX_CTL(pipe
));
1183 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1184 I915_STATE_WARN(cur_state
!= state
,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 onoff(state
), onoff(cur_state
));
1189 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1192 struct drm_device
*dev
= &dev_priv
->drm
;
1195 enum pipe panel_pipe
= PIPE_A
;
1198 if (WARN_ON(HAS_DDI(dev
)))
1201 if (HAS_PCH_SPLIT(dev
)) {
1204 pp_reg
= PCH_PP_CONTROL
;
1205 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1207 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1208 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1209 panel_pipe
= PIPE_B
;
1210 /* XXX: else fix for eDP */
1211 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1212 /* presumably write lock depends on pipe, not port select */
1213 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1216 pp_reg
= PP_CONTROL
;
1217 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1218 panel_pipe
= PIPE_B
;
1221 val
= I915_READ(pp_reg
);
1222 if (!(val
& PANEL_POWER_ON
) ||
1223 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1226 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1227 "panel assertion failure, pipe %c regs locked\n",
1231 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1232 enum pipe pipe
, bool state
)
1234 struct drm_device
*dev
= &dev_priv
->drm
;
1237 if (IS_845G(dev
) || IS_I865G(dev
))
1238 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1240 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1242 I915_STATE_WARN(cur_state
!= state
,
1243 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249 void assert_pipe(struct drm_i915_private
*dev_priv
,
1250 enum pipe pipe
, bool state
)
1253 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1255 enum intel_display_power_domain power_domain
;
1257 /* if we need the pipe quirk it must be always on */
1258 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1259 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1262 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1263 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1264 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1265 cur_state
= !!(val
& PIPECONF_ENABLE
);
1267 intel_display_power_put(dev_priv
, power_domain
);
1272 I915_STATE_WARN(cur_state
!= state
,
1273 "pipe %c assertion failure (expected %s, current %s)\n",
1274 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1277 static void assert_plane(struct drm_i915_private
*dev_priv
,
1278 enum plane plane
, bool state
)
1283 val
= I915_READ(DSPCNTR(plane
));
1284 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1285 I915_STATE_WARN(cur_state
!= state
,
1286 "plane %c assertion failure (expected %s, current %s)\n",
1287 plane_name(plane
), onoff(state
), onoff(cur_state
));
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1296 struct drm_device
*dev
= &dev_priv
->drm
;
1299 /* Primary planes are fixed to pipes on gen4+ */
1300 if (INTEL_INFO(dev
)->gen
>= 4) {
1301 u32 val
= I915_READ(DSPCNTR(pipe
));
1302 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1303 "plane %c assertion failure, should be disabled but not\n",
1308 /* Need to check both planes against the pipe */
1309 for_each_pipe(dev_priv
, i
) {
1310 u32 val
= I915_READ(DSPCNTR(i
));
1311 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1312 DISPPLANE_SEL_PIPE_SHIFT
;
1313 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1314 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315 plane_name(i
), pipe_name(pipe
));
1319 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1322 struct drm_device
*dev
= &dev_priv
->drm
;
1325 if (INTEL_INFO(dev
)->gen
>= 9) {
1326 for_each_sprite(dev_priv
, pipe
, sprite
) {
1327 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1328 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1329 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330 sprite
, pipe_name(pipe
));
1332 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1333 for_each_sprite(dev_priv
, pipe
, sprite
) {
1334 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1335 I915_STATE_WARN(val
& SP_ENABLE
,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1339 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1340 u32 val
= I915_READ(SPRCTL(pipe
));
1341 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 plane_name(pipe
), pipe_name(pipe
));
1344 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1345 u32 val
= I915_READ(DVSCNTR(pipe
));
1346 I915_STATE_WARN(val
& DVS_ENABLE
,
1347 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348 plane_name(pipe
), pipe_name(pipe
));
1352 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1354 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1355 drm_crtc_vblank_put(crtc
);
1358 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1364 val
= I915_READ(PCH_TRANSCONF(pipe
));
1365 enabled
= !!(val
& TRANS_ENABLE
);
1366 I915_STATE_WARN(enabled
,
1367 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1371 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, u32 port_sel
, u32 val
)
1374 if ((val
& DP_PORT_EN
) == 0)
1377 if (HAS_PCH_CPT(dev_priv
)) {
1378 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1379 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1381 } else if (IS_CHERRYVIEW(dev_priv
)) {
1382 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1385 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1391 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1392 enum pipe pipe
, u32 val
)
1394 if ((val
& SDVO_ENABLE
) == 0)
1397 if (HAS_PCH_CPT(dev_priv
)) {
1398 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1400 } else if (IS_CHERRYVIEW(dev_priv
)) {
1401 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1404 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1410 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1411 enum pipe pipe
, u32 val
)
1413 if ((val
& LVDS_PORT_EN
) == 0)
1416 if (HAS_PCH_CPT(dev_priv
)) {
1417 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1420 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1426 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1427 enum pipe pipe
, u32 val
)
1429 if ((val
& ADPA_DAC_ENABLE
) == 0)
1431 if (HAS_PCH_CPT(dev_priv
)) {
1432 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1435 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1441 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1442 enum pipe pipe
, i915_reg_t reg
,
1445 u32 val
= I915_READ(reg
);
1446 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1447 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1450 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1451 && (val
& DP_PIPEB_SELECT
),
1452 "IBX PCH dp port still using transcoder B\n");
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1456 enum pipe pipe
, i915_reg_t reg
)
1458 u32 val
= I915_READ(reg
);
1459 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1460 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1463 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1464 && (val
& SDVO_PIPE_B_SELECT
),
1465 "IBX PCH hdmi port still using transcoder B\n");
1468 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1473 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1474 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1475 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1477 val
= I915_READ(PCH_ADPA
);
1478 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1482 val
= I915_READ(PCH_LVDS
);
1483 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1484 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1488 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1489 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1492 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1493 const struct intel_crtc_state
*pipe_config
)
1495 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1496 enum pipe pipe
= crtc
->pipe
;
1498 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1499 POSTING_READ(DPLL(pipe
));
1502 if (intel_wait_for_register(dev_priv
,
1507 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1510 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1511 const struct intel_crtc_state
*pipe_config
)
1513 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1514 enum pipe pipe
= crtc
->pipe
;
1516 assert_pipe_disabled(dev_priv
, pipe
);
1518 /* PLL is protected by panel, make sure we can write it */
1519 assert_panel_unlocked(dev_priv
, pipe
);
1521 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1522 _vlv_enable_pll(crtc
, pipe_config
);
1524 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1525 POSTING_READ(DPLL_MD(pipe
));
1529 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1530 const struct intel_crtc_state
*pipe_config
)
1532 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1533 enum pipe pipe
= crtc
->pipe
;
1534 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1537 mutex_lock(&dev_priv
->sb_lock
);
1539 /* Enable back the 10bit clock to display controller */
1540 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1541 tmp
|= DPIO_DCLKP_EN
;
1542 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1544 mutex_unlock(&dev_priv
->sb_lock
);
1547 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1552 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1554 /* Check PLL is locked */
1555 if (intel_wait_for_register(dev_priv
,
1556 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1558 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1561 static void chv_enable_pll(struct intel_crtc
*crtc
,
1562 const struct intel_crtc_state
*pipe_config
)
1564 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1565 enum pipe pipe
= crtc
->pipe
;
1567 assert_pipe_disabled(dev_priv
, pipe
);
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv
, pipe
);
1572 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1573 _chv_enable_pll(crtc
, pipe_config
);
1575 if (pipe
!= PIPE_A
) {
1577 * WaPixelRepeatModeFixForC0:chv
1579 * DPLLCMD is AWOL. Use chicken bits to propagate
1580 * the value from DPLLBMD to either pipe B or C.
1582 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1583 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1584 I915_WRITE(CBR4_VLV
, 0);
1585 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1588 * DPLLB VGA mode also seems to cause problems.
1589 * We should always have it disabled.
1591 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1593 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1594 POSTING_READ(DPLL_MD(pipe
));
1598 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1600 struct intel_crtc
*crtc
;
1603 for_each_intel_crtc(dev
, crtc
) {
1604 count
+= crtc
->base
.state
->active
&&
1605 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1611 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1613 struct drm_device
*dev
= crtc
->base
.dev
;
1614 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1615 i915_reg_t reg
= DPLL(crtc
->pipe
);
1616 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1618 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1622 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1624 /* Enable DVO 2x clock on both PLLs if necessary */
1625 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1627 * It appears to be important that we don't enable this
1628 * for the current pipe before otherwise configuring the
1629 * PLL. No idea how this should be handled if multiple
1630 * DVO outputs are enabled simultaneosly.
1632 dpll
|= DPLL_DVO_2X_MODE
;
1633 I915_WRITE(DPLL(!crtc
->pipe
),
1634 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1638 * Apparently we need to have VGA mode enabled prior to changing
1639 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640 * dividers, even though the register value does change.
1644 I915_WRITE(reg
, dpll
);
1646 /* Wait for the clocks to stabilize. */
1650 if (INTEL_INFO(dev
)->gen
>= 4) {
1651 I915_WRITE(DPLL_MD(crtc
->pipe
),
1652 crtc
->config
->dpll_hw_state
.dpll_md
);
1654 /* The pixel multiplier can only be updated once the
1655 * DPLL is enabled and the clocks are stable.
1657 * So write it again.
1659 I915_WRITE(reg
, dpll
);
1662 /* We do this three times for luck */
1663 I915_WRITE(reg
, dpll
);
1665 udelay(150); /* wait for warmup */
1666 I915_WRITE(reg
, dpll
);
1668 udelay(150); /* wait for warmup */
1669 I915_WRITE(reg
, dpll
);
1671 udelay(150); /* wait for warmup */
1675 * i9xx_disable_pll - disable a PLL
1676 * @dev_priv: i915 private structure
1677 * @pipe: pipe PLL to disable
1679 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 * Note! This is for pre-ILK only.
1683 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1685 struct drm_device
*dev
= crtc
->base
.dev
;
1686 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1687 enum pipe pipe
= crtc
->pipe
;
1689 /* Disable DVO 2x clock on both PLLs if necessary */
1691 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1692 !intel_num_dvo_pipes(dev
)) {
1693 I915_WRITE(DPLL(PIPE_B
),
1694 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1695 I915_WRITE(DPLL(PIPE_A
),
1696 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1699 /* Don't disable pipe or pipe PLLs if needed */
1700 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1701 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1704 /* Make sure the pipe isn't still relying on us */
1705 assert_pipe_disabled(dev_priv
, pipe
);
1707 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1708 POSTING_READ(DPLL(pipe
));
1711 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1715 /* Make sure the pipe isn't still relying on us */
1716 assert_pipe_disabled(dev_priv
, pipe
);
1718 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1719 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1721 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1723 I915_WRITE(DPLL(pipe
), val
);
1724 POSTING_READ(DPLL(pipe
));
1727 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1729 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv
, pipe
);
1735 val
= DPLL_SSC_REF_CLK_CHV
|
1736 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1738 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1740 I915_WRITE(DPLL(pipe
), val
);
1741 POSTING_READ(DPLL(pipe
));
1743 mutex_lock(&dev_priv
->sb_lock
);
1745 /* Disable 10bit clock to display controller */
1746 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1747 val
&= ~DPIO_DCLKP_EN
;
1748 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1750 mutex_unlock(&dev_priv
->sb_lock
);
1753 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1754 struct intel_digital_port
*dport
,
1755 unsigned int expected_mask
)
1758 i915_reg_t dpll_reg
;
1760 switch (dport
->port
) {
1762 port_mask
= DPLL_PORTB_READY_MASK
;
1766 port_mask
= DPLL_PORTC_READY_MASK
;
1768 expected_mask
<<= 4;
1771 port_mask
= DPLL_PORTD_READY_MASK
;
1772 dpll_reg
= DPIO_PHY_STATUS
;
1778 if (intel_wait_for_register(dev_priv
,
1779 dpll_reg
, port_mask
, expected_mask
,
1781 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1788 struct drm_device
*dev
= &dev_priv
->drm
;
1789 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1790 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1792 uint32_t val
, pipeconf_val
;
1794 /* Make sure PCH DPLL is enabled */
1795 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1797 /* FDI must be feeding us bits for PCH ports */
1798 assert_fdi_tx_enabled(dev_priv
, pipe
);
1799 assert_fdi_rx_enabled(dev_priv
, pipe
);
1801 if (HAS_PCH_CPT(dev
)) {
1802 /* Workaround: Set the timing override bit before enabling the
1803 * pch transcoder. */
1804 reg
= TRANS_CHICKEN2(pipe
);
1805 val
= I915_READ(reg
);
1806 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1807 I915_WRITE(reg
, val
);
1810 reg
= PCH_TRANSCONF(pipe
);
1811 val
= I915_READ(reg
);
1812 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1814 if (HAS_PCH_IBX(dev_priv
)) {
1816 * Make the BPC in transcoder be consistent with
1817 * that in pipeconf reg. For HDMI we must use 8bpc
1818 * here for both 8bpc and 12bpc.
1820 val
&= ~PIPECONF_BPC_MASK
;
1821 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1822 val
|= PIPECONF_8BPC
;
1824 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1827 val
&= ~TRANS_INTERLACE_MASK
;
1828 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1829 if (HAS_PCH_IBX(dev_priv
) &&
1830 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1831 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1833 val
|= TRANS_INTERLACED
;
1835 val
|= TRANS_PROGRESSIVE
;
1837 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1838 if (intel_wait_for_register(dev_priv
,
1839 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1841 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1845 enum transcoder cpu_transcoder
)
1847 u32 val
, pipeconf_val
;
1849 /* FDI must be feeding us bits for PCH ports */
1850 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1851 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1853 /* Workaround: set timing override bit. */
1854 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1855 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1856 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1859 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1861 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1862 PIPECONF_INTERLACED_ILK
)
1863 val
|= TRANS_INTERLACED
;
1865 val
|= TRANS_PROGRESSIVE
;
1867 I915_WRITE(LPT_TRANSCONF
, val
);
1868 if (intel_wait_for_register(dev_priv
,
1873 DRM_ERROR("Failed to enable PCH transcoder\n");
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1879 struct drm_device
*dev
= &dev_priv
->drm
;
1883 /* FDI relies on the transcoder */
1884 assert_fdi_tx_disabled(dev_priv
, pipe
);
1885 assert_fdi_rx_disabled(dev_priv
, pipe
);
1887 /* Ports must be off as well */
1888 assert_pch_ports_disabled(dev_priv
, pipe
);
1890 reg
= PCH_TRANSCONF(pipe
);
1891 val
= I915_READ(reg
);
1892 val
&= ~TRANS_ENABLE
;
1893 I915_WRITE(reg
, val
);
1894 /* wait for PCH transcoder off, transcoder state */
1895 if (intel_wait_for_register(dev_priv
,
1896 reg
, TRANS_STATE_ENABLE
, 0,
1898 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1900 if (HAS_PCH_CPT(dev
)) {
1901 /* Workaround: Clear the timing override chicken bit again. */
1902 reg
= TRANS_CHICKEN2(pipe
);
1903 val
= I915_READ(reg
);
1904 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1905 I915_WRITE(reg
, val
);
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1913 val
= I915_READ(LPT_TRANSCONF
);
1914 val
&= ~TRANS_ENABLE
;
1915 I915_WRITE(LPT_TRANSCONF
, val
);
1916 /* wait for PCH transcoder off, transcoder state */
1917 if (intel_wait_for_register(dev_priv
,
1918 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1920 DRM_ERROR("Failed to disable PCH transcoder\n");
1922 /* Workaround: clear timing override bit. */
1923 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1924 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1925 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1929 * intel_enable_pipe - enable a pipe, asserting requirements
1930 * @crtc: crtc responsible for the pipe
1932 * Enable @crtc's pipe, making sure that various hardware specific requirements
1933 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1937 struct drm_device
*dev
= crtc
->base
.dev
;
1938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1939 enum pipe pipe
= crtc
->pipe
;
1940 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1941 enum pipe pch_transcoder
;
1945 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1947 assert_planes_disabled(dev_priv
, pipe
);
1948 assert_cursor_disabled(dev_priv
, pipe
);
1949 assert_sprites_disabled(dev_priv
, pipe
);
1951 if (HAS_PCH_LPT(dev_priv
))
1952 pch_transcoder
= TRANSCODER_A
;
1954 pch_transcoder
= pipe
;
1957 * A pipe without a PLL won't actually be able to drive bits from
1958 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1961 if (HAS_GMCH_DISPLAY(dev_priv
))
1962 if (intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DSI
))
1963 assert_dsi_pll_enabled(dev_priv
);
1965 assert_pll_enabled(dev_priv
, pipe
);
1967 if (crtc
->config
->has_pch_encoder
) {
1968 /* if driving the PCH, we need FDI enabled */
1969 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1970 assert_fdi_tx_pll_enabled(dev_priv
,
1971 (enum pipe
) cpu_transcoder
);
1973 /* FIXME: assert CPU port conditions for SNB+ */
1976 reg
= PIPECONF(cpu_transcoder
);
1977 val
= I915_READ(reg
);
1978 if (val
& PIPECONF_ENABLE
) {
1979 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1980 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
1984 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1988 * Until the pipe starts DSL will read as 0, which would cause
1989 * an apparent vblank timestamp jump, which messes up also the
1990 * frame count when it's derived from the timestamps. So let's
1991 * wait for the pipe to start properly before we call
1992 * drm_crtc_vblank_on()
1994 if (dev
->max_vblank_count
== 0 &&
1995 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
1996 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2000 * intel_disable_pipe - disable a pipe, asserting requirements
2001 * @crtc: crtc whose pipes is to be disabled
2003 * Disable the pipe of @crtc, making sure that various hardware
2004 * specific requirements are met, if applicable, e.g. plane
2005 * disabled, panel fitter off, etc.
2007 * Will wait until the pipe has shut down before returning.
2009 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2011 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2012 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2013 enum pipe pipe
= crtc
->pipe
;
2017 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2020 * Make sure planes won't keep trying to pump pixels to us,
2021 * or we might hang the display.
2023 assert_planes_disabled(dev_priv
, pipe
);
2024 assert_cursor_disabled(dev_priv
, pipe
);
2025 assert_sprites_disabled(dev_priv
, pipe
);
2027 reg
= PIPECONF(cpu_transcoder
);
2028 val
= I915_READ(reg
);
2029 if ((val
& PIPECONF_ENABLE
) == 0)
2033 * Double wide has implications for planes
2034 * so best keep it disabled when not needed.
2036 if (crtc
->config
->double_wide
)
2037 val
&= ~PIPECONF_DOUBLE_WIDE
;
2039 /* Don't disable pipe or pipe PLLs if needed */
2040 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2041 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2042 val
&= ~PIPECONF_ENABLE
;
2044 I915_WRITE(reg
, val
);
2045 if ((val
& PIPECONF_ENABLE
) == 0)
2046 intel_wait_for_pipe_off(crtc
);
2049 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2051 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2055 uint64_t fb_modifier
, unsigned int cpp
)
2057 switch (fb_modifier
) {
2058 case DRM_FORMAT_MOD_NONE
:
2060 case I915_FORMAT_MOD_X_TILED
:
2061 if (IS_GEN2(dev_priv
))
2065 case I915_FORMAT_MOD_Y_TILED
:
2066 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2070 case I915_FORMAT_MOD_Yf_TILED
:
2086 MISSING_CASE(fb_modifier
);
2091 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2092 uint64_t fb_modifier
, unsigned int cpp
)
2094 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2097 return intel_tile_size(dev_priv
) /
2098 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2103 unsigned int *tile_width
,
2104 unsigned int *tile_height
,
2105 uint64_t fb_modifier
,
2108 unsigned int tile_width_bytes
=
2109 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2111 *tile_width
= tile_width_bytes
/ cpp
;
2112 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2116 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2117 uint32_t pixel_format
, uint64_t fb_modifier
)
2119 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2120 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2122 return ALIGN(height
, tile_height
);
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2127 unsigned int size
= 0;
2130 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2131 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2138 const struct drm_framebuffer
*fb
,
2139 unsigned int rotation
)
2141 if (intel_rotation_90_or_270(rotation
)) {
2142 *view
= i915_ggtt_view_rotated
;
2143 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2145 *view
= i915_ggtt_view_normal
;
2150 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2151 struct drm_framebuffer
*fb
)
2153 struct intel_rotation_info
*info
= &to_intel_framebuffer(fb
)->rot_info
;
2154 unsigned int tile_size
, tile_width
, tile_height
, cpp
;
2156 tile_size
= intel_tile_size(dev_priv
);
2158 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2159 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2160 fb
->modifier
[0], cpp
);
2162 info
->plane
[0].width
= DIV_ROUND_UP(fb
->pitches
[0], tile_width
* cpp
);
2163 info
->plane
[0].height
= DIV_ROUND_UP(fb
->height
, tile_height
);
2165 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2166 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
2167 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2168 fb
->modifier
[1], cpp
);
2170 info
->uv_offset
= fb
->offsets
[1];
2171 info
->plane
[1].width
= DIV_ROUND_UP(fb
->pitches
[1], tile_width
* cpp
);
2172 info
->plane
[1].height
= DIV_ROUND_UP(fb
->height
/ 2, tile_height
);
2176 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2178 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2180 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2181 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2183 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2189 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2190 uint64_t fb_modifier
)
2192 switch (fb_modifier
) {
2193 case DRM_FORMAT_MOD_NONE
:
2194 return intel_linear_alignment(dev_priv
);
2195 case I915_FORMAT_MOD_X_TILED
:
2196 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2199 case I915_FORMAT_MOD_Y_TILED
:
2200 case I915_FORMAT_MOD_Yf_TILED
:
2201 return 1 * 1024 * 1024;
2203 MISSING_CASE(fb_modifier
);
2209 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2210 unsigned int rotation
)
2212 struct drm_device
*dev
= fb
->dev
;
2213 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2214 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2215 struct i915_ggtt_view view
;
2219 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2221 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
[0]);
2223 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2225 /* Note that the w/a also requires 64 PTE of padding following the
2226 * bo. We currently fill all unused PTE with the shadow page and so
2227 * we should always have valid PTE following the scanout preventing
2230 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2231 alignment
= 256 * 1024;
2234 * Global gtt pte registers are special registers which actually forward
2235 * writes to a chunk of system memory. Which means that there is no risk
2236 * that the register values disappear as soon as we call
2237 * intel_runtime_pm_put(), so it is correct to wrap only the
2238 * pin/unpin/fence and not more.
2240 intel_runtime_pm_get(dev_priv
);
2242 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
,
2247 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2248 * fence, whereas 965+ only requires a fence if using
2249 * framebuffer compression. For simplicity, we always install
2250 * a fence as the cost is not that onerous.
2252 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2253 ret
= i915_gem_object_get_fence(obj
);
2254 if (ret
== -EDEADLK
) {
2256 * -EDEADLK means there are no free fences
2259 * This is propagated to atomic, but it uses
2260 * -EDEADLK to force a locking recovery, so
2261 * change the returned error to -EBUSY.
2268 i915_gem_object_pin_fence(obj
);
2271 intel_runtime_pm_put(dev_priv
);
2275 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2277 intel_runtime_pm_put(dev_priv
);
2281 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2283 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2284 struct i915_ggtt_view view
;
2286 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2288 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2290 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2291 i915_gem_object_unpin_fence(obj
);
2293 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2297 * Adjust the tile offset by moving the difference into
2300 * Input tile dimensions and pitch must already be
2301 * rotated to match x and y, and in pixel units.
2303 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2304 unsigned int tile_width
,
2305 unsigned int tile_height
,
2306 unsigned int tile_size
,
2307 unsigned int pitch_tiles
,
2313 WARN_ON(old_offset
& (tile_size
- 1));
2314 WARN_ON(new_offset
& (tile_size
- 1));
2315 WARN_ON(new_offset
> old_offset
);
2317 tiles
= (old_offset
- new_offset
) / tile_size
;
2319 *y
+= tiles
/ pitch_tiles
* tile_height
;
2320 *x
+= tiles
% pitch_tiles
* tile_width
;
2326 * Computes the linear offset to the base tile and adjusts
2327 * x, y. bytes per pixel is assumed to be a power-of-two.
2329 * In the 90/270 rotated case, x and y are assumed
2330 * to be already rotated to match the rotated GTT view, and
2331 * pitch is the tile_height aligned framebuffer height.
2333 u32
intel_compute_tile_offset(int *x
, int *y
,
2334 const struct drm_framebuffer
*fb
, int plane
,
2336 unsigned int rotation
)
2338 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2339 uint64_t fb_modifier
= fb
->modifier
[plane
];
2340 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2341 u32 offset
, offset_aligned
, alignment
;
2343 alignment
= intel_surf_alignment(dev_priv
, fb_modifier
);
2347 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2348 unsigned int tile_size
, tile_width
, tile_height
;
2349 unsigned int tile_rows
, tiles
, pitch_tiles
;
2351 tile_size
= intel_tile_size(dev_priv
);
2352 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2355 if (intel_rotation_90_or_270(rotation
)) {
2356 pitch_tiles
= pitch
/ tile_height
;
2357 swap(tile_width
, tile_height
);
2359 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2362 tile_rows
= *y
/ tile_height
;
2365 tiles
= *x
/ tile_width
;
2368 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2369 offset_aligned
= offset
& ~alignment
;
2371 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2372 tile_size
, pitch_tiles
,
2373 offset
, offset_aligned
);
2375 offset
= *y
* pitch
+ *x
* cpp
;
2376 offset_aligned
= offset
& ~alignment
;
2378 *y
= (offset
& alignment
) / pitch
;
2379 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2382 return offset_aligned
;
2385 static int i9xx_format_to_fourcc(int format
)
2388 case DISPPLANE_8BPP
:
2389 return DRM_FORMAT_C8
;
2390 case DISPPLANE_BGRX555
:
2391 return DRM_FORMAT_XRGB1555
;
2392 case DISPPLANE_BGRX565
:
2393 return DRM_FORMAT_RGB565
;
2395 case DISPPLANE_BGRX888
:
2396 return DRM_FORMAT_XRGB8888
;
2397 case DISPPLANE_RGBX888
:
2398 return DRM_FORMAT_XBGR8888
;
2399 case DISPPLANE_BGRX101010
:
2400 return DRM_FORMAT_XRGB2101010
;
2401 case DISPPLANE_RGBX101010
:
2402 return DRM_FORMAT_XBGR2101010
;
2406 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2409 case PLANE_CTL_FORMAT_RGB_565
:
2410 return DRM_FORMAT_RGB565
;
2412 case PLANE_CTL_FORMAT_XRGB_8888
:
2415 return DRM_FORMAT_ABGR8888
;
2417 return DRM_FORMAT_XBGR8888
;
2420 return DRM_FORMAT_ARGB8888
;
2422 return DRM_FORMAT_XRGB8888
;
2424 case PLANE_CTL_FORMAT_XRGB_2101010
:
2426 return DRM_FORMAT_XBGR2101010
;
2428 return DRM_FORMAT_XRGB2101010
;
2433 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2434 struct intel_initial_plane_config
*plane_config
)
2436 struct drm_device
*dev
= crtc
->base
.dev
;
2437 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2438 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2439 struct drm_i915_gem_object
*obj
= NULL
;
2440 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2441 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2442 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2443 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2446 size_aligned
-= base_aligned
;
2448 if (plane_config
->size
== 0)
2451 /* If the FB is too big, just don't use it since fbdev is not very
2452 * important and we should probably use that space with FBC or other
2454 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2457 mutex_lock(&dev
->struct_mutex
);
2459 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2464 mutex_unlock(&dev
->struct_mutex
);
2468 obj
->tiling_mode
= plane_config
->tiling
;
2469 if (obj
->tiling_mode
== I915_TILING_X
)
2470 obj
->stride
= fb
->pitches
[0];
2472 mode_cmd
.pixel_format
= fb
->pixel_format
;
2473 mode_cmd
.width
= fb
->width
;
2474 mode_cmd
.height
= fb
->height
;
2475 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2476 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2477 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2479 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2481 DRM_DEBUG_KMS("intel fb init failed\n");
2485 mutex_unlock(&dev
->struct_mutex
);
2487 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2491 drm_gem_object_unreference(&obj
->base
);
2492 mutex_unlock(&dev
->struct_mutex
);
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2498 update_state_fb(struct drm_plane
*plane
)
2500 if (plane
->fb
== plane
->state
->fb
)
2503 if (plane
->state
->fb
)
2504 drm_framebuffer_unreference(plane
->state
->fb
);
2505 plane
->state
->fb
= plane
->fb
;
2506 if (plane
->state
->fb
)
2507 drm_framebuffer_reference(plane
->state
->fb
);
2511 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2512 struct intel_initial_plane_config
*plane_config
)
2514 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2515 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2517 struct intel_crtc
*i
;
2518 struct drm_i915_gem_object
*obj
;
2519 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2520 struct drm_plane_state
*plane_state
= primary
->state
;
2521 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2522 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2523 struct intel_plane_state
*intel_state
=
2524 to_intel_plane_state(plane_state
);
2525 struct drm_framebuffer
*fb
;
2527 if (!plane_config
->fb
)
2530 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2531 fb
= &plane_config
->fb
->base
;
2535 kfree(plane_config
->fb
);
2538 * Failed to alloc the obj, check to see if we should share
2539 * an fb with another CRTC instead
2541 for_each_crtc(dev
, c
) {
2542 i
= to_intel_crtc(c
);
2544 if (c
== &intel_crtc
->base
)
2550 fb
= c
->primary
->fb
;
2554 obj
= intel_fb_obj(fb
);
2555 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2556 drm_framebuffer_reference(fb
);
2562 * We've failed to reconstruct the BIOS FB. Current display state
2563 * indicates that the primary plane is visible, but has a NULL FB,
2564 * which will lead to problems later if we don't fix it up. The
2565 * simplest solution is to just disable the primary plane now and
2566 * pretend the BIOS never had it enabled.
2568 to_intel_plane_state(plane_state
)->visible
= false;
2569 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2570 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2571 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2576 plane_state
->src_x
= 0;
2577 plane_state
->src_y
= 0;
2578 plane_state
->src_w
= fb
->width
<< 16;
2579 plane_state
->src_h
= fb
->height
<< 16;
2581 plane_state
->crtc_x
= 0;
2582 plane_state
->crtc_y
= 0;
2583 plane_state
->crtc_w
= fb
->width
;
2584 plane_state
->crtc_h
= fb
->height
;
2586 intel_state
->src
.x1
= plane_state
->src_x
;
2587 intel_state
->src
.y1
= plane_state
->src_y
;
2588 intel_state
->src
.x2
= plane_state
->src_x
+ plane_state
->src_w
;
2589 intel_state
->src
.y2
= plane_state
->src_y
+ plane_state
->src_h
;
2590 intel_state
->dst
.x1
= plane_state
->crtc_x
;
2591 intel_state
->dst
.y1
= plane_state
->crtc_y
;
2592 intel_state
->dst
.x2
= plane_state
->crtc_x
+ plane_state
->crtc_w
;
2593 intel_state
->dst
.y2
= plane_state
->crtc_y
+ plane_state
->crtc_h
;
2595 obj
= intel_fb_obj(fb
);
2596 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2597 dev_priv
->preserve_bios_swizzle
= true;
2599 drm_framebuffer_reference(fb
);
2600 primary
->fb
= primary
->state
->fb
= fb
;
2601 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2602 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2603 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2606 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2607 const struct intel_crtc_state
*crtc_state
,
2608 const struct intel_plane_state
*plane_state
)
2610 struct drm_device
*dev
= primary
->dev
;
2611 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2612 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2613 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2614 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2615 int plane
= intel_crtc
->plane
;
2618 i915_reg_t reg
= DSPCNTR(plane
);
2619 unsigned int rotation
= plane_state
->base
.rotation
;
2620 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2621 int x
= plane_state
->src
.x1
>> 16;
2622 int y
= plane_state
->src
.y1
>> 16;
2624 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2626 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2628 if (INTEL_INFO(dev
)->gen
< 4) {
2629 if (intel_crtc
->pipe
== PIPE_B
)
2630 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2632 /* pipesrc and dspsize control the size that is scaled from,
2633 * which should always be the user's requested size.
2635 I915_WRITE(DSPSIZE(plane
),
2636 ((crtc_state
->pipe_src_h
- 1) << 16) |
2637 (crtc_state
->pipe_src_w
- 1));
2638 I915_WRITE(DSPPOS(plane
), 0);
2639 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2640 I915_WRITE(PRIMSIZE(plane
),
2641 ((crtc_state
->pipe_src_h
- 1) << 16) |
2642 (crtc_state
->pipe_src_w
- 1));
2643 I915_WRITE(PRIMPOS(plane
), 0);
2644 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2647 switch (fb
->pixel_format
) {
2649 dspcntr
|= DISPPLANE_8BPP
;
2651 case DRM_FORMAT_XRGB1555
:
2652 dspcntr
|= DISPPLANE_BGRX555
;
2654 case DRM_FORMAT_RGB565
:
2655 dspcntr
|= DISPPLANE_BGRX565
;
2657 case DRM_FORMAT_XRGB8888
:
2658 dspcntr
|= DISPPLANE_BGRX888
;
2660 case DRM_FORMAT_XBGR8888
:
2661 dspcntr
|= DISPPLANE_RGBX888
;
2663 case DRM_FORMAT_XRGB2101010
:
2664 dspcntr
|= DISPPLANE_BGRX101010
;
2666 case DRM_FORMAT_XBGR2101010
:
2667 dspcntr
|= DISPPLANE_RGBX101010
;
2673 if (INTEL_INFO(dev
)->gen
>= 4 &&
2674 obj
->tiling_mode
!= I915_TILING_NONE
)
2675 dspcntr
|= DISPPLANE_TILED
;
2678 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2680 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2682 if (INTEL_INFO(dev
)->gen
>= 4) {
2683 intel_crtc
->dspaddr_offset
=
2684 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2685 fb
->pitches
[0], rotation
);
2686 linear_offset
-= intel_crtc
->dspaddr_offset
;
2688 intel_crtc
->dspaddr_offset
= linear_offset
;
2691 if (rotation
== BIT(DRM_ROTATE_180
)) {
2692 dspcntr
|= DISPPLANE_ROTATE_180
;
2694 x
+= (crtc_state
->pipe_src_w
- 1);
2695 y
+= (crtc_state
->pipe_src_h
- 1);
2697 /* Finding the last pixel of the last line of the display
2698 data and adding to linear_offset*/
2700 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2701 (crtc_state
->pipe_src_w
- 1) * cpp
;
2704 intel_crtc
->adjusted_x
= x
;
2705 intel_crtc
->adjusted_y
= y
;
2707 I915_WRITE(reg
, dspcntr
);
2709 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2710 if (INTEL_INFO(dev
)->gen
>= 4) {
2711 I915_WRITE(DSPSURF(plane
),
2712 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2713 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2714 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2716 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2720 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
2721 struct drm_crtc
*crtc
)
2723 struct drm_device
*dev
= crtc
->dev
;
2724 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2726 int plane
= intel_crtc
->plane
;
2728 I915_WRITE(DSPCNTR(plane
), 0);
2729 if (INTEL_INFO(dev_priv
)->gen
>= 4)
2730 I915_WRITE(DSPSURF(plane
), 0);
2732 I915_WRITE(DSPADDR(plane
), 0);
2733 POSTING_READ(DSPCNTR(plane
));
2736 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
2737 const struct intel_crtc_state
*crtc_state
,
2738 const struct intel_plane_state
*plane_state
)
2740 struct drm_device
*dev
= primary
->dev
;
2741 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2743 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2744 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2745 int plane
= intel_crtc
->plane
;
2748 i915_reg_t reg
= DSPCNTR(plane
);
2749 unsigned int rotation
= plane_state
->base
.rotation
;
2750 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2751 int x
= plane_state
->src
.x1
>> 16;
2752 int y
= plane_state
->src
.y1
>> 16;
2754 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2755 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2757 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2758 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2760 switch (fb
->pixel_format
) {
2762 dspcntr
|= DISPPLANE_8BPP
;
2764 case DRM_FORMAT_RGB565
:
2765 dspcntr
|= DISPPLANE_BGRX565
;
2767 case DRM_FORMAT_XRGB8888
:
2768 dspcntr
|= DISPPLANE_BGRX888
;
2770 case DRM_FORMAT_XBGR8888
:
2771 dspcntr
|= DISPPLANE_RGBX888
;
2773 case DRM_FORMAT_XRGB2101010
:
2774 dspcntr
|= DISPPLANE_BGRX101010
;
2776 case DRM_FORMAT_XBGR2101010
:
2777 dspcntr
|= DISPPLANE_RGBX101010
;
2783 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2784 dspcntr
|= DISPPLANE_TILED
;
2786 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2787 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2789 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2790 intel_crtc
->dspaddr_offset
=
2791 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2792 fb
->pitches
[0], rotation
);
2793 linear_offset
-= intel_crtc
->dspaddr_offset
;
2794 if (rotation
== BIT(DRM_ROTATE_180
)) {
2795 dspcntr
|= DISPPLANE_ROTATE_180
;
2797 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2798 x
+= (crtc_state
->pipe_src_w
- 1);
2799 y
+= (crtc_state
->pipe_src_h
- 1);
2801 /* Finding the last pixel of the last line of the display
2802 data and adding to linear_offset*/
2804 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2805 (crtc_state
->pipe_src_w
- 1) * cpp
;
2809 intel_crtc
->adjusted_x
= x
;
2810 intel_crtc
->adjusted_y
= y
;
2812 I915_WRITE(reg
, dspcntr
);
2814 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2815 I915_WRITE(DSPSURF(plane
),
2816 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2817 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2818 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2820 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2821 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2826 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
2827 uint64_t fb_modifier
, uint32_t pixel_format
)
2829 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
2832 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2834 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2838 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2839 struct drm_i915_gem_object
*obj
,
2842 struct i915_ggtt_view view
;
2843 struct i915_vma
*vma
;
2846 intel_fill_fb_ggtt_view(&view
, intel_plane
->base
.state
->fb
,
2847 intel_plane
->base
.state
->rotation
);
2849 vma
= i915_gem_obj_to_ggtt_view(obj
, &view
);
2850 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2854 offset
= vma
->node
.start
;
2857 offset
+= vma
->ggtt_view
.params
.rotated
.uv_start_page
*
2861 WARN_ON(upper_32_bits(offset
));
2863 return lower_32_bits(offset
);
2866 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2868 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2869 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2871 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2872 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2873 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2877 * This function detaches (aka. unbinds) unused scalers in hardware
2879 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2881 struct intel_crtc_scaler_state
*scaler_state
;
2884 scaler_state
= &intel_crtc
->config
->scaler_state
;
2886 /* loop through and disable scalers that aren't in use */
2887 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2888 if (!scaler_state
->scalers
[i
].in_use
)
2889 skl_detach_scaler(intel_crtc
, i
);
2893 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2895 switch (pixel_format
) {
2897 return PLANE_CTL_FORMAT_INDEXED
;
2898 case DRM_FORMAT_RGB565
:
2899 return PLANE_CTL_FORMAT_RGB_565
;
2900 case DRM_FORMAT_XBGR8888
:
2901 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2902 case DRM_FORMAT_XRGB8888
:
2903 return PLANE_CTL_FORMAT_XRGB_8888
;
2905 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2906 * to be already pre-multiplied. We need to add a knob (or a different
2907 * DRM_FORMAT) for user-space to configure that.
2909 case DRM_FORMAT_ABGR8888
:
2910 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2911 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2912 case DRM_FORMAT_ARGB8888
:
2913 return PLANE_CTL_FORMAT_XRGB_8888
|
2914 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2915 case DRM_FORMAT_XRGB2101010
:
2916 return PLANE_CTL_FORMAT_XRGB_2101010
;
2917 case DRM_FORMAT_XBGR2101010
:
2918 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2919 case DRM_FORMAT_YUYV
:
2920 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2921 case DRM_FORMAT_YVYU
:
2922 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2923 case DRM_FORMAT_UYVY
:
2924 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2925 case DRM_FORMAT_VYUY
:
2926 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2928 MISSING_CASE(pixel_format
);
2934 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2936 switch (fb_modifier
) {
2937 case DRM_FORMAT_MOD_NONE
:
2939 case I915_FORMAT_MOD_X_TILED
:
2940 return PLANE_CTL_TILED_X
;
2941 case I915_FORMAT_MOD_Y_TILED
:
2942 return PLANE_CTL_TILED_Y
;
2943 case I915_FORMAT_MOD_Yf_TILED
:
2944 return PLANE_CTL_TILED_YF
;
2946 MISSING_CASE(fb_modifier
);
2952 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2955 case BIT(DRM_ROTATE_0
):
2958 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2959 * while i915 HW rotation is clockwise, thats why this swapping.
2961 case BIT(DRM_ROTATE_90
):
2962 return PLANE_CTL_ROTATE_270
;
2963 case BIT(DRM_ROTATE_180
):
2964 return PLANE_CTL_ROTATE_180
;
2965 case BIT(DRM_ROTATE_270
):
2966 return PLANE_CTL_ROTATE_90
;
2968 MISSING_CASE(rotation
);
2974 static void skylake_update_primary_plane(struct drm_plane
*plane
,
2975 const struct intel_crtc_state
*crtc_state
,
2976 const struct intel_plane_state
*plane_state
)
2978 struct drm_device
*dev
= plane
->dev
;
2979 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2980 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2981 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2982 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2983 int pipe
= intel_crtc
->pipe
;
2984 u32 plane_ctl
, stride_div
, stride
;
2985 u32 tile_height
, plane_offset
, plane_size
;
2986 unsigned int rotation
= plane_state
->base
.rotation
;
2987 int x_offset
, y_offset
;
2989 int scaler_id
= plane_state
->scaler_id
;
2990 int src_x
= plane_state
->src
.x1
>> 16;
2991 int src_y
= plane_state
->src
.y1
>> 16;
2992 int src_w
= drm_rect_width(&plane_state
->src
) >> 16;
2993 int src_h
= drm_rect_height(&plane_state
->src
) >> 16;
2994 int dst_x
= plane_state
->dst
.x1
;
2995 int dst_y
= plane_state
->dst
.y1
;
2996 int dst_w
= drm_rect_width(&plane_state
->dst
);
2997 int dst_h
= drm_rect_height(&plane_state
->dst
);
2999 plane_ctl
= PLANE_CTL_ENABLE
|
3000 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3001 PLANE_CTL_PIPE_CSC_ENABLE
;
3003 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3004 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3005 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3006 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3008 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
3010 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3012 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3014 if (intel_rotation_90_or_270(rotation
)) {
3015 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3017 /* stride = Surface height in tiles */
3018 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
3019 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3020 x_offset
= stride
* tile_height
- src_y
- src_h
;
3022 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3024 stride
= fb
->pitches
[0] / stride_div
;
3027 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3029 plane_offset
= y_offset
<< 16 | x_offset
;
3031 intel_crtc
->adjusted_x
= x_offset
;
3032 intel_crtc
->adjusted_y
= y_offset
;
3034 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3035 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3036 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3037 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3039 if (scaler_id
>= 0) {
3040 uint32_t ps_ctrl
= 0;
3042 WARN_ON(!dst_w
|| !dst_h
);
3043 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3044 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3045 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3046 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3047 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3048 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3049 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3051 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3054 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3056 POSTING_READ(PLANE_SURF(pipe
, 0));
3059 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3060 struct drm_crtc
*crtc
)
3062 struct drm_device
*dev
= crtc
->dev
;
3063 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3064 int pipe
= to_intel_crtc(crtc
)->pipe
;
3066 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3067 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3068 POSTING_READ(PLANE_SURF(pipe
, 0));
3071 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3073 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3074 int x
, int y
, enum mode_set_atomic state
)
3076 /* Support for kgdboc is disabled, this needs a major rework. */
3077 DRM_ERROR("legacy panic handler not supported any more.\n");
3082 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3084 struct intel_crtc
*crtc
;
3086 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
3087 intel_finish_page_flip_cs(dev_priv
, crtc
->pipe
);
3090 static void intel_update_primary_planes(struct drm_device
*dev
)
3092 struct drm_crtc
*crtc
;
3094 for_each_crtc(dev
, crtc
) {
3095 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3096 struct intel_plane_state
*plane_state
;
3098 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3099 plane_state
= to_intel_plane_state(plane
->base
.state
);
3101 if (plane_state
->visible
)
3102 plane
->update_plane(&plane
->base
,
3103 to_intel_crtc_state(crtc
->state
),
3106 drm_modeset_unlock_crtc(crtc
);
3110 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3112 /* no reset support for gen2 */
3113 if (IS_GEN2(dev_priv
))
3116 /* reset doesn't touch the display */
3117 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
3120 drm_modeset_lock_all(&dev_priv
->drm
);
3122 * Disabling the crtcs gracefully seems nicer. Also the
3123 * g33 docs say we should at least disable all the planes.
3125 intel_display_suspend(&dev_priv
->drm
);
3128 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3131 * Flips in the rings will be nuked by the reset,
3132 * so complete all pending flips so that user space
3133 * will get its events and not get stuck.
3135 intel_complete_page_flips(dev_priv
);
3137 /* no reset support for gen2 */
3138 if (IS_GEN2(dev_priv
))
3141 /* reset doesn't touch the display */
3142 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
3144 * Flips in the rings have been nuked by the reset,
3145 * so update the base address of all primary
3146 * planes to the the last fb to make sure we're
3147 * showing the correct fb after a reset.
3149 * FIXME: Atomic will make this obsolete since we won't schedule
3150 * CS-based flips (which might get lost in gpu resets) any more.
3152 intel_update_primary_planes(&dev_priv
->drm
);
3157 * The display has been reset as well,
3158 * so need a full re-initialization.
3160 intel_runtime_pm_disable_interrupts(dev_priv
);
3161 intel_runtime_pm_enable_interrupts(dev_priv
);
3163 intel_modeset_init_hw(&dev_priv
->drm
);
3165 spin_lock_irq(&dev_priv
->irq_lock
);
3166 if (dev_priv
->display
.hpd_irq_setup
)
3167 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3168 spin_unlock_irq(&dev_priv
->irq_lock
);
3170 intel_display_resume(&dev_priv
->drm
);
3172 intel_hpd_init(dev_priv
);
3174 drm_modeset_unlock_all(&dev_priv
->drm
);
3177 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3179 struct drm_device
*dev
= crtc
->dev
;
3180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3181 unsigned reset_counter
;
3184 reset_counter
= i915_reset_counter(&to_i915(dev
)->gpu_error
);
3185 if (intel_crtc
->reset_counter
!= reset_counter
)
3188 spin_lock_irq(&dev
->event_lock
);
3189 pending
= to_intel_crtc(crtc
)->flip_work
!= NULL
;
3190 spin_unlock_irq(&dev
->event_lock
);
3195 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3196 struct intel_crtc_state
*old_crtc_state
)
3198 struct drm_device
*dev
= crtc
->base
.dev
;
3199 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3200 struct intel_crtc_state
*pipe_config
=
3201 to_intel_crtc_state(crtc
->base
.state
);
3203 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3204 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3206 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3207 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3208 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3211 * Update pipe size and adjust fitter if needed: the reason for this is
3212 * that in compute_mode_changes we check the native mode (not the pfit
3213 * mode) to see if we can flip rather than do a full mode set. In the
3214 * fastboot case, we'll flip, but if we don't update the pipesrc and
3215 * pfit state, we'll end up with a big fb scanned out into the wrong
3219 I915_WRITE(PIPESRC(crtc
->pipe
),
3220 ((pipe_config
->pipe_src_w
- 1) << 16) |
3221 (pipe_config
->pipe_src_h
- 1));
3223 /* on skylake this is done by detaching scalers */
3224 if (INTEL_INFO(dev
)->gen
>= 9) {
3225 skl_detach_scalers(crtc
);
3227 if (pipe_config
->pch_pfit
.enabled
)
3228 skylake_pfit_enable(crtc
);
3229 } else if (HAS_PCH_SPLIT(dev
)) {
3230 if (pipe_config
->pch_pfit
.enabled
)
3231 ironlake_pfit_enable(crtc
);
3232 else if (old_crtc_state
->pch_pfit
.enabled
)
3233 ironlake_pfit_disable(crtc
, true);
3237 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3239 struct drm_device
*dev
= crtc
->dev
;
3240 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3242 int pipe
= intel_crtc
->pipe
;
3246 /* enable normal train */
3247 reg
= FDI_TX_CTL(pipe
);
3248 temp
= I915_READ(reg
);
3249 if (IS_IVYBRIDGE(dev
)) {
3250 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3251 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3253 temp
&= ~FDI_LINK_TRAIN_NONE
;
3254 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3256 I915_WRITE(reg
, temp
);
3258 reg
= FDI_RX_CTL(pipe
);
3259 temp
= I915_READ(reg
);
3260 if (HAS_PCH_CPT(dev
)) {
3261 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3262 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3264 temp
&= ~FDI_LINK_TRAIN_NONE
;
3265 temp
|= FDI_LINK_TRAIN_NONE
;
3267 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3269 /* wait one idle pattern time */
3273 /* IVB wants error correction enabled */
3274 if (IS_IVYBRIDGE(dev
))
3275 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3276 FDI_FE_ERRC_ENABLE
);
3279 /* The FDI link training functions for ILK/Ibexpeak. */
3280 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3282 struct drm_device
*dev
= crtc
->dev
;
3283 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3285 int pipe
= intel_crtc
->pipe
;
3289 /* FDI needs bits from pipe first */
3290 assert_pipe_enabled(dev_priv
, pipe
);
3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3294 reg
= FDI_RX_IMR(pipe
);
3295 temp
= I915_READ(reg
);
3296 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3297 temp
&= ~FDI_RX_BIT_LOCK
;
3298 I915_WRITE(reg
, temp
);
3302 /* enable CPU FDI TX and PCH FDI RX */
3303 reg
= FDI_TX_CTL(pipe
);
3304 temp
= I915_READ(reg
);
3305 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3306 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3307 temp
&= ~FDI_LINK_TRAIN_NONE
;
3308 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3309 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3311 reg
= FDI_RX_CTL(pipe
);
3312 temp
= I915_READ(reg
);
3313 temp
&= ~FDI_LINK_TRAIN_NONE
;
3314 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3315 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3320 /* Ironlake workaround, enable clock pointer after FDI enable*/
3321 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3322 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3323 FDI_RX_PHASE_SYNC_POINTER_EN
);
3325 reg
= FDI_RX_IIR(pipe
);
3326 for (tries
= 0; tries
< 5; tries
++) {
3327 temp
= I915_READ(reg
);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3330 if ((temp
& FDI_RX_BIT_LOCK
)) {
3331 DRM_DEBUG_KMS("FDI train 1 done.\n");
3332 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3337 DRM_ERROR("FDI train 1 fail!\n");
3340 reg
= FDI_TX_CTL(pipe
);
3341 temp
= I915_READ(reg
);
3342 temp
&= ~FDI_LINK_TRAIN_NONE
;
3343 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3344 I915_WRITE(reg
, temp
);
3346 reg
= FDI_RX_CTL(pipe
);
3347 temp
= I915_READ(reg
);
3348 temp
&= ~FDI_LINK_TRAIN_NONE
;
3349 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3350 I915_WRITE(reg
, temp
);
3355 reg
= FDI_RX_IIR(pipe
);
3356 for (tries
= 0; tries
< 5; tries
++) {
3357 temp
= I915_READ(reg
);
3358 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3360 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3361 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3362 DRM_DEBUG_KMS("FDI train 2 done.\n");
3367 DRM_ERROR("FDI train 2 fail!\n");
3369 DRM_DEBUG_KMS("FDI train done\n");
3373 static const int snb_b_fdi_train_param
[] = {
3374 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3375 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3376 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3377 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3380 /* The FDI link training functions for SNB/Cougarpoint. */
3381 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3383 struct drm_device
*dev
= crtc
->dev
;
3384 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3386 int pipe
= intel_crtc
->pipe
;
3390 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392 reg
= FDI_RX_IMR(pipe
);
3393 temp
= I915_READ(reg
);
3394 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3395 temp
&= ~FDI_RX_BIT_LOCK
;
3396 I915_WRITE(reg
, temp
);
3401 /* enable CPU FDI TX and PCH FDI RX */
3402 reg
= FDI_TX_CTL(pipe
);
3403 temp
= I915_READ(reg
);
3404 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3405 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3406 temp
&= ~FDI_LINK_TRAIN_NONE
;
3407 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3408 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3410 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3411 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3413 I915_WRITE(FDI_RX_MISC(pipe
),
3414 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3416 reg
= FDI_RX_CTL(pipe
);
3417 temp
= I915_READ(reg
);
3418 if (HAS_PCH_CPT(dev
)) {
3419 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3420 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3422 temp
&= ~FDI_LINK_TRAIN_NONE
;
3423 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3425 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3430 for (i
= 0; i
< 4; i
++) {
3431 reg
= FDI_TX_CTL(pipe
);
3432 temp
= I915_READ(reg
);
3433 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3434 temp
|= snb_b_fdi_train_param
[i
];
3435 I915_WRITE(reg
, temp
);
3440 for (retry
= 0; retry
< 5; retry
++) {
3441 reg
= FDI_RX_IIR(pipe
);
3442 temp
= I915_READ(reg
);
3443 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3444 if (temp
& FDI_RX_BIT_LOCK
) {
3445 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3446 DRM_DEBUG_KMS("FDI train 1 done.\n");
3455 DRM_ERROR("FDI train 1 fail!\n");
3458 reg
= FDI_TX_CTL(pipe
);
3459 temp
= I915_READ(reg
);
3460 temp
&= ~FDI_LINK_TRAIN_NONE
;
3461 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3463 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3465 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3467 I915_WRITE(reg
, temp
);
3469 reg
= FDI_RX_CTL(pipe
);
3470 temp
= I915_READ(reg
);
3471 if (HAS_PCH_CPT(dev
)) {
3472 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3473 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3475 temp
&= ~FDI_LINK_TRAIN_NONE
;
3476 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3478 I915_WRITE(reg
, temp
);
3483 for (i
= 0; i
< 4; i
++) {
3484 reg
= FDI_TX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3487 temp
|= snb_b_fdi_train_param
[i
];
3488 I915_WRITE(reg
, temp
);
3493 for (retry
= 0; retry
< 5; retry
++) {
3494 reg
= FDI_RX_IIR(pipe
);
3495 temp
= I915_READ(reg
);
3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3497 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3498 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3499 DRM_DEBUG_KMS("FDI train 2 done.\n");
3508 DRM_ERROR("FDI train 2 fail!\n");
3510 DRM_DEBUG_KMS("FDI train done.\n");
3513 /* Manual link training for Ivy Bridge A0 parts */
3514 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3516 struct drm_device
*dev
= crtc
->dev
;
3517 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3519 int pipe
= intel_crtc
->pipe
;
3523 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3525 reg
= FDI_RX_IMR(pipe
);
3526 temp
= I915_READ(reg
);
3527 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3528 temp
&= ~FDI_RX_BIT_LOCK
;
3529 I915_WRITE(reg
, temp
);
3534 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3535 I915_READ(FDI_RX_IIR(pipe
)));
3537 /* Try each vswing and preemphasis setting twice before moving on */
3538 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3539 /* disable first in case we need to retry */
3540 reg
= FDI_TX_CTL(pipe
);
3541 temp
= I915_READ(reg
);
3542 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3543 temp
&= ~FDI_TX_ENABLE
;
3544 I915_WRITE(reg
, temp
);
3546 reg
= FDI_RX_CTL(pipe
);
3547 temp
= I915_READ(reg
);
3548 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3549 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3550 temp
&= ~FDI_RX_ENABLE
;
3551 I915_WRITE(reg
, temp
);
3553 /* enable CPU FDI TX and PCH FDI RX */
3554 reg
= FDI_TX_CTL(pipe
);
3555 temp
= I915_READ(reg
);
3556 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3557 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3558 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3559 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3560 temp
|= snb_b_fdi_train_param
[j
/2];
3561 temp
|= FDI_COMPOSITE_SYNC
;
3562 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3564 I915_WRITE(FDI_RX_MISC(pipe
),
3565 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3567 reg
= FDI_RX_CTL(pipe
);
3568 temp
= I915_READ(reg
);
3569 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3570 temp
|= FDI_COMPOSITE_SYNC
;
3571 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3574 udelay(1); /* should be 0.5us */
3576 for (i
= 0; i
< 4; i
++) {
3577 reg
= FDI_RX_IIR(pipe
);
3578 temp
= I915_READ(reg
);
3579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3581 if (temp
& FDI_RX_BIT_LOCK
||
3582 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3583 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3584 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3588 udelay(1); /* should be 0.5us */
3591 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3596 reg
= FDI_TX_CTL(pipe
);
3597 temp
= I915_READ(reg
);
3598 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3599 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3600 I915_WRITE(reg
, temp
);
3602 reg
= FDI_RX_CTL(pipe
);
3603 temp
= I915_READ(reg
);
3604 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3605 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3606 I915_WRITE(reg
, temp
);
3609 udelay(2); /* should be 1.5us */
3611 for (i
= 0; i
< 4; i
++) {
3612 reg
= FDI_RX_IIR(pipe
);
3613 temp
= I915_READ(reg
);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3616 if (temp
& FDI_RX_SYMBOL_LOCK
||
3617 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3618 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3619 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3623 udelay(2); /* should be 1.5us */
3626 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3630 DRM_DEBUG_KMS("FDI train done.\n");
3633 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3635 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3636 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3637 int pipe
= intel_crtc
->pipe
;
3641 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3642 reg
= FDI_RX_CTL(pipe
);
3643 temp
= I915_READ(reg
);
3644 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3645 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3646 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3647 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3652 /* Switch from Rawclk to PCDclk */
3653 temp
= I915_READ(reg
);
3654 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3659 /* Enable CPU FDI TX PLL, always on for Ironlake */
3660 reg
= FDI_TX_CTL(pipe
);
3661 temp
= I915_READ(reg
);
3662 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3663 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3670 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3672 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3673 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3674 int pipe
= intel_crtc
->pipe
;
3678 /* Switch from PCDclk to Rawclk */
3679 reg
= FDI_RX_CTL(pipe
);
3680 temp
= I915_READ(reg
);
3681 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3683 /* Disable CPU FDI TX PLL */
3684 reg
= FDI_TX_CTL(pipe
);
3685 temp
= I915_READ(reg
);
3686 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3691 reg
= FDI_RX_CTL(pipe
);
3692 temp
= I915_READ(reg
);
3693 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3695 /* Wait for the clocks to turn off. */
3700 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3702 struct drm_device
*dev
= crtc
->dev
;
3703 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3704 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3705 int pipe
= intel_crtc
->pipe
;
3709 /* disable CPU FDI tx and PCH FDI rx */
3710 reg
= FDI_TX_CTL(pipe
);
3711 temp
= I915_READ(reg
);
3712 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3715 reg
= FDI_RX_CTL(pipe
);
3716 temp
= I915_READ(reg
);
3717 temp
&= ~(0x7 << 16);
3718 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3719 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3724 /* Ironlake workaround, disable clock pointer after downing FDI */
3725 if (HAS_PCH_IBX(dev
))
3726 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3728 /* still set train pattern 1 */
3729 reg
= FDI_TX_CTL(pipe
);
3730 temp
= I915_READ(reg
);
3731 temp
&= ~FDI_LINK_TRAIN_NONE
;
3732 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3733 I915_WRITE(reg
, temp
);
3735 reg
= FDI_RX_CTL(pipe
);
3736 temp
= I915_READ(reg
);
3737 if (HAS_PCH_CPT(dev
)) {
3738 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3739 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3741 temp
&= ~FDI_LINK_TRAIN_NONE
;
3742 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3744 /* BPC in FDI rx is consistent with that in PIPECONF */
3745 temp
&= ~(0x07 << 16);
3746 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3747 I915_WRITE(reg
, temp
);
3753 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3755 struct intel_crtc
*crtc
;
3757 /* Note that we don't need to be called with mode_config.lock here
3758 * as our list of CRTC objects is static for the lifetime of the
3759 * device and so cannot disappear as we iterate. Similarly, we can
3760 * happily treat the predicates as racy, atomic checks as userspace
3761 * cannot claim and pin a new fb without at least acquring the
3762 * struct_mutex and so serialising with us.
3764 for_each_intel_crtc(dev
, crtc
) {
3765 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3768 if (crtc
->flip_work
)
3769 intel_wait_for_vblank(dev
, crtc
->pipe
);
3777 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3779 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3780 struct intel_flip_work
*work
= intel_crtc
->flip_work
;
3782 intel_crtc
->flip_work
= NULL
;
3785 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
3787 drm_crtc_vblank_put(&intel_crtc
->base
);
3789 wake_up_all(&dev_priv
->pending_flip_queue
);
3790 queue_work(dev_priv
->wq
, &work
->unpin_work
);
3792 trace_i915_flip_complete(intel_crtc
->plane
,
3793 work
->pending_flip_obj
);
3796 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3798 struct drm_device
*dev
= crtc
->dev
;
3799 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3802 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3804 ret
= wait_event_interruptible_timeout(
3805 dev_priv
->pending_flip_queue
,
3806 !intel_crtc_has_pending_flip(crtc
),
3813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3814 struct intel_flip_work
*work
;
3816 spin_lock_irq(&dev
->event_lock
);
3817 work
= intel_crtc
->flip_work
;
3818 if (work
&& !is_mmio_work(work
)) {
3819 WARN_ONCE(1, "Removing stuck page flip\n");
3820 page_flip_completed(intel_crtc
);
3822 spin_unlock_irq(&dev
->event_lock
);
3828 static void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
3832 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3834 mutex_lock(&dev_priv
->sb_lock
);
3836 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3837 temp
|= SBI_SSCCTL_DISABLE
;
3838 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3840 mutex_unlock(&dev_priv
->sb_lock
);
3843 /* Program iCLKIP clock to the desired frequency */
3844 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3846 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3847 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3848 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3851 lpt_disable_iclkip(dev_priv
);
3853 /* The iCLK virtual clock root frequency is in MHz,
3854 * but the adjusted_mode->crtc_clock in in KHz. To get the
3855 * divisors, it is necessary to divide one by another, so we
3856 * convert the virtual clock precision to KHz here for higher
3859 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
3860 u32 iclk_virtual_root_freq
= 172800 * 1000;
3861 u32 iclk_pi_range
= 64;
3862 u32 desired_divisor
;
3864 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3866 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
3867 phaseinc
= desired_divisor
% iclk_pi_range
;
3870 * Near 20MHz is a corner case which is
3871 * out of range for the 7-bit divisor
3877 /* This should not happen with any sane values */
3878 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3879 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3880 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3881 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3883 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3890 mutex_lock(&dev_priv
->sb_lock
);
3892 /* Program SSCDIVINTPHASE6 */
3893 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3894 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3895 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3896 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3897 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3898 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3899 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3900 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3902 /* Program SSCAUXDIV */
3903 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3904 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3905 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3906 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3908 /* Enable modulator and associated divider */
3909 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3910 temp
&= ~SBI_SSCCTL_DISABLE
;
3911 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3913 mutex_unlock(&dev_priv
->sb_lock
);
3915 /* Wait for initialization time */
3918 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3921 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
3923 u32 divsel
, phaseinc
, auxdiv
;
3924 u32 iclk_virtual_root_freq
= 172800 * 1000;
3925 u32 iclk_pi_range
= 64;
3926 u32 desired_divisor
;
3929 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
3932 mutex_lock(&dev_priv
->sb_lock
);
3934 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3935 if (temp
& SBI_SSCCTL_DISABLE
) {
3936 mutex_unlock(&dev_priv
->sb_lock
);
3940 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3941 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
3942 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
3943 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
3944 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
3946 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3947 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
3948 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
3950 mutex_unlock(&dev_priv
->sb_lock
);
3952 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
3954 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3955 desired_divisor
<< auxdiv
);
3958 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3959 enum pipe pch_transcoder
)
3961 struct drm_device
*dev
= crtc
->base
.dev
;
3962 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3963 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3965 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3966 I915_READ(HTOTAL(cpu_transcoder
)));
3967 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3968 I915_READ(HBLANK(cpu_transcoder
)));
3969 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3970 I915_READ(HSYNC(cpu_transcoder
)));
3972 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3973 I915_READ(VTOTAL(cpu_transcoder
)));
3974 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3975 I915_READ(VBLANK(cpu_transcoder
)));
3976 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3977 I915_READ(VSYNC(cpu_transcoder
)));
3978 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3979 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3982 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
3984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3987 temp
= I915_READ(SOUTH_CHICKEN1
);
3988 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
3991 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3992 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3994 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3996 temp
|= FDI_BC_BIFURCATION_SELECT
;
3998 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
3999 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4000 POSTING_READ(SOUTH_CHICKEN1
);
4003 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4005 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4007 switch (intel_crtc
->pipe
) {
4011 if (intel_crtc
->config
->fdi_lanes
> 2)
4012 cpt_set_fdi_bc_bifurcation(dev
, false);
4014 cpt_set_fdi_bc_bifurcation(dev
, true);
4018 cpt_set_fdi_bc_bifurcation(dev
, true);
4026 /* Return which DP Port should be selected for Transcoder DP control */
4028 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4030 struct drm_device
*dev
= crtc
->dev
;
4031 struct intel_encoder
*encoder
;
4033 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4034 if (encoder
->type
== INTEL_OUTPUT_DP
||
4035 encoder
->type
== INTEL_OUTPUT_EDP
)
4036 return enc_to_dig_port(&encoder
->base
)->port
;
4043 * Enable PCH resources required for PCH ports:
4045 * - FDI training & RX/TX
4046 * - update transcoder timings
4047 * - DP transcoding bits
4050 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4052 struct drm_device
*dev
= crtc
->dev
;
4053 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4055 int pipe
= intel_crtc
->pipe
;
4058 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4060 if (IS_IVYBRIDGE(dev
))
4061 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4063 /* Write the TU size bits before fdi link training, so that error
4064 * detection works. */
4065 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4066 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4068 /* For PCH output, training FDI link */
4069 dev_priv
->display
.fdi_link_train(crtc
);
4071 /* We need to program the right clock selection before writing the pixel
4072 * mutliplier into the DPLL. */
4073 if (HAS_PCH_CPT(dev
)) {
4076 temp
= I915_READ(PCH_DPLL_SEL
);
4077 temp
|= TRANS_DPLL_ENABLE(pipe
);
4078 sel
= TRANS_DPLLB_SEL(pipe
);
4079 if (intel_crtc
->config
->shared_dpll
==
4080 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4084 I915_WRITE(PCH_DPLL_SEL
, temp
);
4087 /* XXX: pch pll's can be enabled any time before we enable the PCH
4088 * transcoder, and we actually should do this to not upset any PCH
4089 * transcoder that already use the clock when we share it.
4091 * Note that enable_shared_dpll tries to do the right thing, but
4092 * get_shared_dpll unconditionally resets the pll - we need that to have
4093 * the right LVDS enable sequence. */
4094 intel_enable_shared_dpll(intel_crtc
);
4096 /* set transcoder timing, panel must allow it */
4097 assert_panel_unlocked(dev_priv
, pipe
);
4098 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4100 intel_fdi_normal_train(crtc
);
4102 /* For PCH DP, enable TRANS_DP_CTL */
4103 if (HAS_PCH_CPT(dev
) && intel_crtc_has_dp_encoder(intel_crtc
->config
)) {
4104 const struct drm_display_mode
*adjusted_mode
=
4105 &intel_crtc
->config
->base
.adjusted_mode
;
4106 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4107 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4108 temp
= I915_READ(reg
);
4109 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4110 TRANS_DP_SYNC_MASK
|
4112 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4113 temp
|= bpc
<< 9; /* same format but at 11:9 */
4115 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4116 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4117 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4118 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4120 switch (intel_trans_dp_port_sel(crtc
)) {
4122 temp
|= TRANS_DP_PORT_SEL_B
;
4125 temp
|= TRANS_DP_PORT_SEL_C
;
4128 temp
|= TRANS_DP_PORT_SEL_D
;
4134 I915_WRITE(reg
, temp
);
4137 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4140 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4142 struct drm_device
*dev
= crtc
->dev
;
4143 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4145 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4147 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4149 lpt_program_iclkip(crtc
);
4151 /* Set transcoder timing. */
4152 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4154 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4157 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4159 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4160 i915_reg_t dslreg
= PIPEDSL(pipe
);
4163 temp
= I915_READ(dslreg
);
4165 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4166 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4167 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4172 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4173 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4174 int src_w
, int src_h
, int dst_w
, int dst_h
)
4176 struct intel_crtc_scaler_state
*scaler_state
=
4177 &crtc_state
->scaler_state
;
4178 struct intel_crtc
*intel_crtc
=
4179 to_intel_crtc(crtc_state
->base
.crtc
);
4182 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4183 (src_h
!= dst_w
|| src_w
!= dst_h
):
4184 (src_w
!= dst_w
|| src_h
!= dst_h
);
4187 * if plane is being disabled or scaler is no more required or force detach
4188 * - free scaler binded to this plane/crtc
4189 * - in order to do this, update crtc->scaler_usage
4191 * Here scaler state in crtc_state is set free so that
4192 * scaler can be assigned to other user. Actual register
4193 * update to free the scaler is done in plane/panel-fit programming.
4194 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4196 if (force_detach
|| !need_scaling
) {
4197 if (*scaler_id
>= 0) {
4198 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4199 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4201 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4202 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4203 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4204 scaler_state
->scaler_users
);
4211 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4212 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4214 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4215 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4216 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4217 "size is out of scaler range\n",
4218 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4222 /* mark this plane as a scaler user in crtc_state */
4223 scaler_state
->scaler_users
|= (1 << scaler_user
);
4224 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4225 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4226 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4227 scaler_state
->scaler_users
);
4233 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4235 * @state: crtc's scaler state
4238 * 0 - scaler_usage updated successfully
4239 * error - requested scaling cannot be supported or other error condition
4241 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4243 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4244 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4246 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4247 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
4248 intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4250 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4251 &state
->scaler_state
.scaler_id
, BIT(DRM_ROTATE_0
),
4252 state
->pipe_src_w
, state
->pipe_src_h
,
4253 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4257 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4259 * @state: crtc's scaler state
4260 * @plane_state: atomic plane state to update
4263 * 0 - scaler_usage updated successfully
4264 * error - requested scaling cannot be supported or other error condition
4266 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4267 struct intel_plane_state
*plane_state
)
4270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4271 struct intel_plane
*intel_plane
=
4272 to_intel_plane(plane_state
->base
.plane
);
4273 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4276 bool force_detach
= !fb
|| !plane_state
->visible
;
4278 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4279 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4280 intel_crtc
->pipe
, drm_plane_index(&intel_plane
->base
));
4282 ret
= skl_update_scaler(crtc_state
, force_detach
,
4283 drm_plane_index(&intel_plane
->base
),
4284 &plane_state
->scaler_id
,
4285 plane_state
->base
.rotation
,
4286 drm_rect_width(&plane_state
->src
) >> 16,
4287 drm_rect_height(&plane_state
->src
) >> 16,
4288 drm_rect_width(&plane_state
->dst
),
4289 drm_rect_height(&plane_state
->dst
));
4291 if (ret
|| plane_state
->scaler_id
< 0)
4294 /* check colorkey */
4295 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4296 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4297 intel_plane
->base
.base
.id
,
4298 intel_plane
->base
.name
);
4302 /* Check src format */
4303 switch (fb
->pixel_format
) {
4304 case DRM_FORMAT_RGB565
:
4305 case DRM_FORMAT_XBGR8888
:
4306 case DRM_FORMAT_XRGB8888
:
4307 case DRM_FORMAT_ABGR8888
:
4308 case DRM_FORMAT_ARGB8888
:
4309 case DRM_FORMAT_XRGB2101010
:
4310 case DRM_FORMAT_XBGR2101010
:
4311 case DRM_FORMAT_YUYV
:
4312 case DRM_FORMAT_YVYU
:
4313 case DRM_FORMAT_UYVY
:
4314 case DRM_FORMAT_VYUY
:
4317 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4318 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4319 fb
->base
.id
, fb
->pixel_format
);
4326 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4330 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4331 skl_detach_scaler(crtc
, i
);
4334 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4336 struct drm_device
*dev
= crtc
->base
.dev
;
4337 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4338 int pipe
= crtc
->pipe
;
4339 struct intel_crtc_scaler_state
*scaler_state
=
4340 &crtc
->config
->scaler_state
;
4342 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4344 if (crtc
->config
->pch_pfit
.enabled
) {
4347 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4348 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4352 id
= scaler_state
->scaler_id
;
4353 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4354 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4355 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4356 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4358 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4362 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4364 struct drm_device
*dev
= crtc
->base
.dev
;
4365 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4366 int pipe
= crtc
->pipe
;
4368 if (crtc
->config
->pch_pfit
.enabled
) {
4369 /* Force use of hard-coded filter coefficients
4370 * as some pre-programmed values are broken,
4373 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4374 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4375 PF_PIPE_SEL_IVB(pipe
));
4377 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4378 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4379 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4383 void hsw_enable_ips(struct intel_crtc
*crtc
)
4385 struct drm_device
*dev
= crtc
->base
.dev
;
4386 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4388 if (!crtc
->config
->ips_enabled
)
4392 * We can only enable IPS after we enable a plane and wait for a vblank
4393 * This function is called from post_plane_update, which is run after
4397 assert_plane_enabled(dev_priv
, crtc
->plane
);
4398 if (IS_BROADWELL(dev
)) {
4399 mutex_lock(&dev_priv
->rps
.hw_lock
);
4400 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4401 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4402 /* Quoting Art Runyan: "its not safe to expect any particular
4403 * value in IPS_CTL bit 31 after enabling IPS through the
4404 * mailbox." Moreover, the mailbox may return a bogus state,
4405 * so we need to just enable it and continue on.
4408 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4409 /* The bit only becomes 1 in the next vblank, so this wait here
4410 * is essentially intel_wait_for_vblank. If we don't have this
4411 * and don't wait for vblanks until the end of crtc_enable, then
4412 * the HW state readout code will complain that the expected
4413 * IPS_CTL value is not the one we read. */
4414 if (intel_wait_for_register(dev_priv
,
4415 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4417 DRM_ERROR("Timed out waiting for IPS enable\n");
4421 void hsw_disable_ips(struct intel_crtc
*crtc
)
4423 struct drm_device
*dev
= crtc
->base
.dev
;
4424 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4426 if (!crtc
->config
->ips_enabled
)
4429 assert_plane_enabled(dev_priv
, crtc
->plane
);
4430 if (IS_BROADWELL(dev
)) {
4431 mutex_lock(&dev_priv
->rps
.hw_lock
);
4432 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4433 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4434 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4435 if (intel_wait_for_register(dev_priv
,
4436 IPS_CTL
, IPS_ENABLE
, 0,
4438 DRM_ERROR("Timed out waiting for IPS disable\n");
4440 I915_WRITE(IPS_CTL
, 0);
4441 POSTING_READ(IPS_CTL
);
4444 /* We need to wait for a vblank before we can disable the plane. */
4445 intel_wait_for_vblank(dev
, crtc
->pipe
);
4448 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4450 if (intel_crtc
->overlay
) {
4451 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4452 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4454 mutex_lock(&dev
->struct_mutex
);
4455 dev_priv
->mm
.interruptible
= false;
4456 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4457 dev_priv
->mm
.interruptible
= true;
4458 mutex_unlock(&dev
->struct_mutex
);
4461 /* Let userspace switch the overlay on again. In most cases userspace
4462 * has to recompute where to put it anyway.
4467 * intel_post_enable_primary - Perform operations after enabling primary plane
4468 * @crtc: the CRTC whose primary plane was just enabled
4470 * Performs potentially sleeping operations that must be done after the primary
4471 * plane is enabled, such as updating FBC and IPS. Note that this may be
4472 * called due to an explicit primary plane update, or due to an implicit
4473 * re-enable that is caused when a sprite plane is updated to no longer
4474 * completely hide the primary plane.
4477 intel_post_enable_primary(struct drm_crtc
*crtc
)
4479 struct drm_device
*dev
= crtc
->dev
;
4480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4482 int pipe
= intel_crtc
->pipe
;
4485 * FIXME IPS should be fine as long as one plane is
4486 * enabled, but in practice it seems to have problems
4487 * when going from primary only to sprite only and vice
4490 hsw_enable_ips(intel_crtc
);
4493 * Gen2 reports pipe underruns whenever all planes are disabled.
4494 * So don't enable underrun reporting before at least some planes
4496 * FIXME: Need to fix the logic to work when we turn off all planes
4497 * but leave the pipe running.
4500 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4502 /* Underruns don't always raise interrupts, so check manually. */
4503 intel_check_cpu_fifo_underruns(dev_priv
);
4504 intel_check_pch_fifo_underruns(dev_priv
);
4507 /* FIXME move all this to pre_plane_update() with proper state tracking */
4509 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4511 struct drm_device
*dev
= crtc
->dev
;
4512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4514 int pipe
= intel_crtc
->pipe
;
4517 * Gen2 reports pipe underruns whenever all planes are disabled.
4518 * So diasble underrun reporting before all the planes get disabled.
4519 * FIXME: Need to fix the logic to work when we turn off all planes
4520 * but leave the pipe running.
4523 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4526 * FIXME IPS should be fine as long as one plane is
4527 * enabled, but in practice it seems to have problems
4528 * when going from primary only to sprite only and vice
4531 hsw_disable_ips(intel_crtc
);
4534 /* FIXME get rid of this and use pre_plane_update */
4536 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4538 struct drm_device
*dev
= crtc
->dev
;
4539 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4541 int pipe
= intel_crtc
->pipe
;
4543 intel_pre_disable_primary(crtc
);
4546 * Vblank time updates from the shadow to live plane control register
4547 * are blocked if the memory self-refresh mode is active at that
4548 * moment. So to make sure the plane gets truly disabled, disable
4549 * first the self-refresh mode. The self-refresh enable bit in turn
4550 * will be checked/applied by the HW only at the next frame start
4551 * event which is after the vblank start event, so we need to have a
4552 * wait-for-vblank between disabling the plane and the pipe.
4554 if (HAS_GMCH_DISPLAY(dev
)) {
4555 intel_set_memory_cxsr(dev_priv
, false);
4556 dev_priv
->wm
.vlv
.cxsr
= false;
4557 intel_wait_for_vblank(dev
, pipe
);
4561 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
4563 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4564 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4565 struct intel_crtc_state
*pipe_config
=
4566 to_intel_crtc_state(crtc
->base
.state
);
4567 struct drm_device
*dev
= crtc
->base
.dev
;
4568 struct drm_plane
*primary
= crtc
->base
.primary
;
4569 struct drm_plane_state
*old_pri_state
=
4570 drm_atomic_get_existing_plane_state(old_state
, primary
);
4572 intel_frontbuffer_flip(dev
, pipe_config
->fb_bits
);
4574 crtc
->wm
.cxsr_allowed
= true;
4576 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
4577 intel_update_watermarks(&crtc
->base
);
4579 if (old_pri_state
) {
4580 struct intel_plane_state
*primary_state
=
4581 to_intel_plane_state(primary
->state
);
4582 struct intel_plane_state
*old_primary_state
=
4583 to_intel_plane_state(old_pri_state
);
4585 intel_fbc_post_update(crtc
);
4587 if (primary_state
->visible
&&
4588 (needs_modeset(&pipe_config
->base
) ||
4589 !old_primary_state
->visible
))
4590 intel_post_enable_primary(&crtc
->base
);
4594 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
4596 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4597 struct drm_device
*dev
= crtc
->base
.dev
;
4598 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4599 struct intel_crtc_state
*pipe_config
=
4600 to_intel_crtc_state(crtc
->base
.state
);
4601 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4602 struct drm_plane
*primary
= crtc
->base
.primary
;
4603 struct drm_plane_state
*old_pri_state
=
4604 drm_atomic_get_existing_plane_state(old_state
, primary
);
4605 bool modeset
= needs_modeset(&pipe_config
->base
);
4607 if (old_pri_state
) {
4608 struct intel_plane_state
*primary_state
=
4609 to_intel_plane_state(primary
->state
);
4610 struct intel_plane_state
*old_primary_state
=
4611 to_intel_plane_state(old_pri_state
);
4613 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
4615 if (old_primary_state
->visible
&&
4616 (modeset
|| !primary_state
->visible
))
4617 intel_pre_disable_primary(&crtc
->base
);
4620 if (pipe_config
->disable_cxsr
&& HAS_GMCH_DISPLAY(dev
)) {
4621 crtc
->wm
.cxsr_allowed
= false;
4624 * Vblank time updates from the shadow to live plane control register
4625 * are blocked if the memory self-refresh mode is active at that
4626 * moment. So to make sure the plane gets truly disabled, disable
4627 * first the self-refresh mode. The self-refresh enable bit in turn
4628 * will be checked/applied by the HW only at the next frame start
4629 * event which is after the vblank start event, so we need to have a
4630 * wait-for-vblank between disabling the plane and the pipe.
4632 if (old_crtc_state
->base
.active
) {
4633 intel_set_memory_cxsr(dev_priv
, false);
4634 dev_priv
->wm
.vlv
.cxsr
= false;
4635 intel_wait_for_vblank(dev
, crtc
->pipe
);
4640 * IVB workaround: must disable low power watermarks for at least
4641 * one frame before enabling scaling. LP watermarks can be re-enabled
4642 * when scaling is disabled.
4644 * WaCxSRDisabledForSpriteScaling:ivb
4646 if (pipe_config
->disable_lp_wm
) {
4647 ilk_disable_lp_wm(dev
);
4648 intel_wait_for_vblank(dev
, crtc
->pipe
);
4652 * If we're doing a modeset, we're done. No need to do any pre-vblank
4653 * watermark programming here.
4655 if (needs_modeset(&pipe_config
->base
))
4659 * For platforms that support atomic watermarks, program the
4660 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4661 * will be the intermediate values that are safe for both pre- and
4662 * post- vblank; when vblank happens, the 'active' values will be set
4663 * to the final 'target' values and we'll do this again to get the
4664 * optimal watermarks. For gen9+ platforms, the values we program here
4665 * will be the final target values which will get automatically latched
4666 * at vblank time; no further programming will be necessary.
4668 * If a platform hasn't been transitioned to atomic watermarks yet,
4669 * we'll continue to update watermarks the old way, if flags tell
4672 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4673 dev_priv
->display
.initial_watermarks(pipe_config
);
4674 else if (pipe_config
->update_wm_pre
)
4675 intel_update_watermarks(&crtc
->base
);
4678 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4680 struct drm_device
*dev
= crtc
->dev
;
4681 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4682 struct drm_plane
*p
;
4683 int pipe
= intel_crtc
->pipe
;
4685 intel_crtc_dpms_overlay_disable(intel_crtc
);
4687 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4688 to_intel_plane(p
)->disable_plane(p
, crtc
);
4691 * FIXME: Once we grow proper nuclear flip support out of this we need
4692 * to compute the mask of flip planes precisely. For the time being
4693 * consider this a flip to a NULL plane.
4695 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4698 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4700 struct drm_device
*dev
= crtc
->dev
;
4701 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4703 struct intel_encoder
*encoder
;
4704 int pipe
= intel_crtc
->pipe
;
4705 struct intel_crtc_state
*pipe_config
=
4706 to_intel_crtc_state(crtc
->state
);
4708 if (WARN_ON(intel_crtc
->active
))
4712 * Sometimes spurious CPU pipe underruns happen during FDI
4713 * training, at least with VGA+HDMI cloning. Suppress them.
4715 * On ILK we get an occasional spurious CPU pipe underruns
4716 * between eDP port A enable and vdd enable. Also PCH port
4717 * enable seems to result in the occasional CPU pipe underrun.
4719 * Spurious PCH underruns also occur during PCH enabling.
4721 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
4722 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4723 if (intel_crtc
->config
->has_pch_encoder
)
4724 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4726 if (intel_crtc
->config
->has_pch_encoder
)
4727 intel_prepare_shared_dpll(intel_crtc
);
4729 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
4730 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4732 intel_set_pipe_timings(intel_crtc
);
4733 intel_set_pipe_src_size(intel_crtc
);
4735 if (intel_crtc
->config
->has_pch_encoder
) {
4736 intel_cpu_transcoder_set_m_n(intel_crtc
,
4737 &intel_crtc
->config
->fdi_m_n
, NULL
);
4740 ironlake_set_pipeconf(crtc
);
4742 intel_crtc
->active
= true;
4744 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4745 if (encoder
->pre_enable
)
4746 encoder
->pre_enable(encoder
);
4748 if (intel_crtc
->config
->has_pch_encoder
) {
4749 /* Note: FDI PLL enabling _must_ be done before we enable the
4750 * cpu pipes, hence this is separate from all the other fdi/pch
4752 ironlake_fdi_pll_enable(intel_crtc
);
4754 assert_fdi_tx_disabled(dev_priv
, pipe
);
4755 assert_fdi_rx_disabled(dev_priv
, pipe
);
4758 ironlake_pfit_enable(intel_crtc
);
4761 * On ILK+ LUT must be loaded before the pipe is running but with
4764 intel_color_load_luts(&pipe_config
->base
);
4766 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4767 dev_priv
->display
.initial_watermarks(intel_crtc
->config
);
4768 intel_enable_pipe(intel_crtc
);
4770 if (intel_crtc
->config
->has_pch_encoder
)
4771 ironlake_pch_enable(crtc
);
4773 assert_vblank_disabled(crtc
);
4774 drm_crtc_vblank_on(crtc
);
4776 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4777 encoder
->enable(encoder
);
4779 if (HAS_PCH_CPT(dev
))
4780 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4782 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4783 if (intel_crtc
->config
->has_pch_encoder
)
4784 intel_wait_for_vblank(dev
, pipe
);
4785 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4786 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4789 /* IPS only exists on ULT machines and is tied to pipe A. */
4790 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4792 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4795 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4797 struct drm_device
*dev
= crtc
->dev
;
4798 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4799 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4800 struct intel_encoder
*encoder
;
4801 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4802 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4803 struct intel_crtc_state
*pipe_config
=
4804 to_intel_crtc_state(crtc
->state
);
4806 if (WARN_ON(intel_crtc
->active
))
4809 if (intel_crtc
->config
->has_pch_encoder
)
4810 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4813 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4814 if (encoder
->pre_pll_enable
)
4815 encoder
->pre_pll_enable(encoder
);
4817 if (intel_crtc
->config
->shared_dpll
)
4818 intel_enable_shared_dpll(intel_crtc
);
4820 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
4821 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4823 if (!transcoder_is_dsi(cpu_transcoder
))
4824 intel_set_pipe_timings(intel_crtc
);
4826 intel_set_pipe_src_size(intel_crtc
);
4828 if (cpu_transcoder
!= TRANSCODER_EDP
&&
4829 !transcoder_is_dsi(cpu_transcoder
)) {
4830 I915_WRITE(PIPE_MULT(cpu_transcoder
),
4831 intel_crtc
->config
->pixel_multiplier
- 1);
4834 if (intel_crtc
->config
->has_pch_encoder
) {
4835 intel_cpu_transcoder_set_m_n(intel_crtc
,
4836 &intel_crtc
->config
->fdi_m_n
, NULL
);
4839 if (!transcoder_is_dsi(cpu_transcoder
))
4840 haswell_set_pipeconf(crtc
);
4842 haswell_set_pipemisc(crtc
);
4844 intel_color_set_csc(&pipe_config
->base
);
4846 intel_crtc
->active
= true;
4848 if (intel_crtc
->config
->has_pch_encoder
)
4849 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4851 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4853 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4854 if (encoder
->pre_enable
)
4855 encoder
->pre_enable(encoder
);
4858 if (intel_crtc
->config
->has_pch_encoder
)
4859 dev_priv
->display
.fdi_link_train(crtc
);
4861 if (!transcoder_is_dsi(cpu_transcoder
))
4862 intel_ddi_enable_pipe_clock(intel_crtc
);
4864 if (INTEL_INFO(dev
)->gen
>= 9)
4865 skylake_pfit_enable(intel_crtc
);
4867 ironlake_pfit_enable(intel_crtc
);
4870 * On ILK+ LUT must be loaded before the pipe is running but with
4873 intel_color_load_luts(&pipe_config
->base
);
4875 intel_ddi_set_pipe_settings(crtc
);
4876 if (!transcoder_is_dsi(cpu_transcoder
))
4877 intel_ddi_enable_transcoder_func(crtc
);
4879 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4880 dev_priv
->display
.initial_watermarks(pipe_config
);
4882 intel_update_watermarks(crtc
);
4884 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4885 if (!transcoder_is_dsi(cpu_transcoder
))
4886 intel_enable_pipe(intel_crtc
);
4888 if (intel_crtc
->config
->has_pch_encoder
)
4889 lpt_pch_enable(crtc
);
4891 if (intel_crtc
->config
->dp_encoder_is_mst
)
4892 intel_ddi_set_vc_payload_alloc(crtc
, true);
4894 assert_vblank_disabled(crtc
);
4895 drm_crtc_vblank_on(crtc
);
4897 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4898 encoder
->enable(encoder
);
4899 intel_opregion_notify_encoder(encoder
, true);
4902 if (intel_crtc
->config
->has_pch_encoder
) {
4903 intel_wait_for_vblank(dev
, pipe
);
4904 intel_wait_for_vblank(dev
, pipe
);
4905 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4906 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4910 /* If we change the relative order between pipe/planes enabling, we need
4911 * to change the workaround. */
4912 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4913 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4914 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4915 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4919 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
4921 struct drm_device
*dev
= crtc
->base
.dev
;
4922 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4923 int pipe
= crtc
->pipe
;
4925 /* To avoid upsetting the power well on haswell only disable the pfit if
4926 * it's in use. The hw state code will make sure we get this right. */
4927 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
4928 I915_WRITE(PF_CTL(pipe
), 0);
4929 I915_WRITE(PF_WIN_POS(pipe
), 0);
4930 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4934 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4936 struct drm_device
*dev
= crtc
->dev
;
4937 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4939 struct intel_encoder
*encoder
;
4940 int pipe
= intel_crtc
->pipe
;
4943 * Sometimes spurious CPU pipe underruns happen when the
4944 * pipe is already disabled, but FDI RX/TX is still enabled.
4945 * Happens at least with VGA+HDMI cloning. Suppress them.
4947 if (intel_crtc
->config
->has_pch_encoder
) {
4948 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4949 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4952 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4953 encoder
->disable(encoder
);
4955 drm_crtc_vblank_off(crtc
);
4956 assert_vblank_disabled(crtc
);
4958 intel_disable_pipe(intel_crtc
);
4960 ironlake_pfit_disable(intel_crtc
, false);
4962 if (intel_crtc
->config
->has_pch_encoder
)
4963 ironlake_fdi_disable(crtc
);
4965 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4966 if (encoder
->post_disable
)
4967 encoder
->post_disable(encoder
);
4969 if (intel_crtc
->config
->has_pch_encoder
) {
4970 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4972 if (HAS_PCH_CPT(dev
)) {
4976 /* disable TRANS_DP_CTL */
4977 reg
= TRANS_DP_CTL(pipe
);
4978 temp
= I915_READ(reg
);
4979 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4980 TRANS_DP_PORT_SEL_MASK
);
4981 temp
|= TRANS_DP_PORT_SEL_NONE
;
4982 I915_WRITE(reg
, temp
);
4984 /* disable DPLL_SEL */
4985 temp
= I915_READ(PCH_DPLL_SEL
);
4986 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4987 I915_WRITE(PCH_DPLL_SEL
, temp
);
4990 ironlake_fdi_pll_disable(intel_crtc
);
4993 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4994 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4997 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4999 struct drm_device
*dev
= crtc
->dev
;
5000 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5001 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5002 struct intel_encoder
*encoder
;
5003 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5005 if (intel_crtc
->config
->has_pch_encoder
)
5006 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5009 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5010 intel_opregion_notify_encoder(encoder
, false);
5011 encoder
->disable(encoder
);
5014 drm_crtc_vblank_off(crtc
);
5015 assert_vblank_disabled(crtc
);
5017 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5018 if (!transcoder_is_dsi(cpu_transcoder
))
5019 intel_disable_pipe(intel_crtc
);
5021 if (intel_crtc
->config
->dp_encoder_is_mst
)
5022 intel_ddi_set_vc_payload_alloc(crtc
, false);
5024 if (!transcoder_is_dsi(cpu_transcoder
))
5025 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5027 if (INTEL_INFO(dev
)->gen
>= 9)
5028 skylake_scaler_disable(intel_crtc
);
5030 ironlake_pfit_disable(intel_crtc
, false);
5032 if (!transcoder_is_dsi(cpu_transcoder
))
5033 intel_ddi_disable_pipe_clock(intel_crtc
);
5035 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5036 if (encoder
->post_disable
)
5037 encoder
->post_disable(encoder
);
5039 if (intel_crtc
->config
->has_pch_encoder
) {
5040 lpt_disable_pch_transcoder(dev_priv
);
5041 lpt_disable_iclkip(dev_priv
);
5042 intel_ddi_fdi_disable(crtc
);
5044 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5049 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5051 struct drm_device
*dev
= crtc
->base
.dev
;
5052 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5053 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5055 if (!pipe_config
->gmch_pfit
.control
)
5059 * The panel fitter should only be adjusted whilst the pipe is disabled,
5060 * according to register description and PRM.
5062 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5063 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5065 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5066 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5068 /* Border color in case we don't scale up to the full screen. Black by
5069 * default, change to something else for debugging. */
5070 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5073 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5077 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5079 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5081 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5083 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5085 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5088 return POWER_DOMAIN_PORT_OTHER
;
5092 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5096 return POWER_DOMAIN_AUX_A
;
5098 return POWER_DOMAIN_AUX_B
;
5100 return POWER_DOMAIN_AUX_C
;
5102 return POWER_DOMAIN_AUX_D
;
5104 /* FIXME: Check VBT for actual wiring of PORT E */
5105 return POWER_DOMAIN_AUX_D
;
5108 return POWER_DOMAIN_AUX_A
;
5112 enum intel_display_power_domain
5113 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5115 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5116 struct intel_digital_port
*intel_dig_port
;
5118 switch (intel_encoder
->type
) {
5119 case INTEL_OUTPUT_UNKNOWN
:
5120 /* Only DDI platforms should ever use this output type */
5121 WARN_ON_ONCE(!HAS_DDI(dev
));
5122 case INTEL_OUTPUT_DP
:
5123 case INTEL_OUTPUT_HDMI
:
5124 case INTEL_OUTPUT_EDP
:
5125 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5126 return port_to_power_domain(intel_dig_port
->port
);
5127 case INTEL_OUTPUT_DP_MST
:
5128 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5129 return port_to_power_domain(intel_dig_port
->port
);
5130 case INTEL_OUTPUT_ANALOG
:
5131 return POWER_DOMAIN_PORT_CRT
;
5132 case INTEL_OUTPUT_DSI
:
5133 return POWER_DOMAIN_PORT_DSI
;
5135 return POWER_DOMAIN_PORT_OTHER
;
5139 enum intel_display_power_domain
5140 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5142 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5143 struct intel_digital_port
*intel_dig_port
;
5145 switch (intel_encoder
->type
) {
5146 case INTEL_OUTPUT_UNKNOWN
:
5147 case INTEL_OUTPUT_HDMI
:
5149 * Only DDI platforms should ever use these output types.
5150 * We can get here after the HDMI detect code has already set
5151 * the type of the shared encoder. Since we can't be sure
5152 * what's the status of the given connectors, play safe and
5153 * run the DP detection too.
5155 WARN_ON_ONCE(!HAS_DDI(dev
));
5156 case INTEL_OUTPUT_DP
:
5157 case INTEL_OUTPUT_EDP
:
5158 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5159 return port_to_aux_power_domain(intel_dig_port
->port
);
5160 case INTEL_OUTPUT_DP_MST
:
5161 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5162 return port_to_aux_power_domain(intel_dig_port
->port
);
5164 MISSING_CASE(intel_encoder
->type
);
5165 return POWER_DOMAIN_AUX_A
;
5169 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5170 struct intel_crtc_state
*crtc_state
)
5172 struct drm_device
*dev
= crtc
->dev
;
5173 struct drm_encoder
*encoder
;
5174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5175 enum pipe pipe
= intel_crtc
->pipe
;
5177 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5179 if (!crtc_state
->base
.active
)
5182 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5183 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5184 if (crtc_state
->pch_pfit
.enabled
||
5185 crtc_state
->pch_pfit
.force_thru
)
5186 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5188 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5189 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5191 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5194 if (crtc_state
->shared_dpll
)
5195 mask
|= BIT(POWER_DOMAIN_PLLS
);
5200 static unsigned long
5201 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5202 struct intel_crtc_state
*crtc_state
)
5204 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5206 enum intel_display_power_domain domain
;
5207 unsigned long domains
, new_domains
, old_domains
;
5209 old_domains
= intel_crtc
->enabled_power_domains
;
5210 intel_crtc
->enabled_power_domains
= new_domains
=
5211 get_crtc_power_domains(crtc
, crtc_state
);
5213 domains
= new_domains
& ~old_domains
;
5215 for_each_power_domain(domain
, domains
)
5216 intel_display_power_get(dev_priv
, domain
);
5218 return old_domains
& ~new_domains
;
5221 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5222 unsigned long domains
)
5224 enum intel_display_power_domain domain
;
5226 for_each_power_domain(domain
, domains
)
5227 intel_display_power_put(dev_priv
, domain
);
5230 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5232 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5234 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5235 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5236 return max_cdclk_freq
;
5237 else if (IS_CHERRYVIEW(dev_priv
))
5238 return max_cdclk_freq
*95/100;
5239 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5240 return 2*max_cdclk_freq
*90/100;
5242 return max_cdclk_freq
*90/100;
5245 static int skl_calc_cdclk(int max_pixclk
, int vco
);
5247 static void intel_update_max_cdclk(struct drm_device
*dev
)
5249 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5251 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
5252 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5255 vco
= dev_priv
->skl_preferred_vco_freq
;
5256 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5259 * Use the lower (vco 8640) cdclk values as a
5260 * first guess. skl_calc_cdclk() will correct it
5261 * if the preferred vco is 8100 instead.
5263 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5265 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5267 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5272 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
5273 } else if (IS_BROXTON(dev
)) {
5274 dev_priv
->max_cdclk_freq
= 624000;
5275 } else if (IS_BROADWELL(dev
)) {
5277 * FIXME with extra cooling we can allow
5278 * 540 MHz for ULX and 675 Mhz for ULT.
5279 * How can we know if extra cooling is
5280 * available? PCI ID, VTB, something else?
5282 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5283 dev_priv
->max_cdclk_freq
= 450000;
5284 else if (IS_BDW_ULX(dev
))
5285 dev_priv
->max_cdclk_freq
= 450000;
5286 else if (IS_BDW_ULT(dev
))
5287 dev_priv
->max_cdclk_freq
= 540000;
5289 dev_priv
->max_cdclk_freq
= 675000;
5290 } else if (IS_CHERRYVIEW(dev
)) {
5291 dev_priv
->max_cdclk_freq
= 320000;
5292 } else if (IS_VALLEYVIEW(dev
)) {
5293 dev_priv
->max_cdclk_freq
= 400000;
5295 /* otherwise assume cdclk is fixed */
5296 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5299 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5301 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302 dev_priv
->max_cdclk_freq
);
5304 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5305 dev_priv
->max_dotclk_freq
);
5308 static void intel_update_cdclk(struct drm_device
*dev
)
5310 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5312 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5314 if (INTEL_GEN(dev_priv
) >= 9)
5315 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5316 dev_priv
->cdclk_freq
, dev_priv
->cdclk_pll
.vco
,
5317 dev_priv
->cdclk_pll
.ref
);
5319 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5320 dev_priv
->cdclk_freq
);
5323 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5324 * Programmng [sic] note: bit[9:2] should be programmed to the number
5325 * of cdclk that generates 4MHz reference clock freq which is used to
5326 * generate GMBus clock. This will vary with the cdclk freq.
5328 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5329 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5332 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5333 static int skl_cdclk_decimal(int cdclk
)
5335 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
5338 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5342 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5347 MISSING_CASE(cdclk
);
5359 return dev_priv
->cdclk_pll
.ref
* ratio
;
5362 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
5364 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
5367 if (intel_wait_for_register(dev_priv
,
5368 BXT_DE_PLL_ENABLE
, BXT_DE_PLL_LOCK
, 0,
5370 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5372 dev_priv
->cdclk_pll
.vco
= 0;
5375 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
5377 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk_pll
.ref
);
5380 val
= I915_READ(BXT_DE_PLL_CTL
);
5381 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5382 val
|= BXT_DE_PLL_RATIO(ratio
);
5383 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5385 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5388 if (intel_wait_for_register(dev_priv
,
5393 DRM_ERROR("timeout waiting for DE PLL lock\n");
5395 dev_priv
->cdclk_pll
.vco
= vco
;
5398 static void bxt_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
)
5403 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
5405 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5407 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5408 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
5410 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5413 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5416 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5419 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5422 WARN_ON(cdclk
!= dev_priv
->cdclk_pll
.ref
);
5425 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5429 /* Inform power controller of upcoming frequency change */
5430 mutex_lock(&dev_priv
->rps
.hw_lock
);
5431 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5433 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5436 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5441 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5442 dev_priv
->cdclk_pll
.vco
!= vco
)
5443 bxt_de_pll_disable(dev_priv
);
5445 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5446 bxt_de_pll_enable(dev_priv
, vco
);
5448 val
= divider
| skl_cdclk_decimal(cdclk
);
5450 * FIXME if only the cd2x divider needs changing, it could be done
5451 * without shutting off the pipe (if only one pipe is active).
5453 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
5455 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458 if (cdclk
>= 500000)
5459 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5460 I915_WRITE(CDCLK_CTL
, val
);
5462 mutex_lock(&dev_priv
->rps
.hw_lock
);
5463 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5464 DIV_ROUND_UP(cdclk
, 25000));
5465 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5468 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5473 intel_update_cdclk(&dev_priv
->drm
);
5476 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5478 u32 cdctl
, expected
;
5480 intel_update_cdclk(&dev_priv
->drm
);
5482 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5483 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5486 /* DPLL okay; verify the cdclock
5488 * Some BIOS versions leave an incorrect decimal frequency value and
5489 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5490 * so sanitize this register.
5492 cdctl
= I915_READ(CDCLK_CTL
);
5494 * Let's ignore the pipe field, since BIOS could have configured the
5495 * dividers both synching to an active pipe, or asynchronously
5498 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
5500 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
5501 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5503 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5506 if (dev_priv
->cdclk_freq
>= 500000)
5507 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5509 if (cdctl
== expected
)
5510 /* All well; nothing to sanitize */
5514 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5516 /* force cdclk programming */
5517 dev_priv
->cdclk_freq
= 0;
5519 /* force full PLL disable + enable */
5520 dev_priv
->cdclk_pll
.vco
= -1;
5523 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
)
5525 bxt_sanitize_cdclk(dev_priv
);
5527 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0)
5532 * - The initial CDCLK needs to be read from VBT.
5533 * Need to make this change after VBT has changes for BXT.
5535 bxt_set_cdclk(dev_priv
, bxt_calc_cdclk(0));
5538 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5540 bxt_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
);
5543 static int skl_calc_cdclk(int max_pixclk
, int vco
)
5545 if (vco
== 8640000) {
5546 if (max_pixclk
> 540000)
5548 else if (max_pixclk
> 432000)
5550 else if (max_pixclk
> 308571)
5555 if (max_pixclk
> 540000)
5557 else if (max_pixclk
> 450000)
5559 else if (max_pixclk
> 337500)
5567 skl_dpll0_update(struct drm_i915_private
*dev_priv
)
5571 dev_priv
->cdclk_pll
.ref
= 24000;
5572 dev_priv
->cdclk_pll
.vco
= 0;
5574 val
= I915_READ(LCPLL1_CTL
);
5575 if ((val
& LCPLL_PLL_ENABLE
) == 0)
5578 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
5581 val
= I915_READ(DPLL_CTRL1
);
5583 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
5584 DPLL_CTRL1_SSC(SKL_DPLL0
) |
5585 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
5586 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
5589 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
5590 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
5591 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
5592 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
5593 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
5594 dev_priv
->cdclk_pll
.vco
= 8100000;
5596 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
5597 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
5598 dev_priv
->cdclk_pll
.vco
= 8640000;
5601 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5606 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
)
5608 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
5610 dev_priv
->skl_preferred_vco_freq
= vco
;
5613 intel_update_max_cdclk(&dev_priv
->drm
);
5617 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
5619 int min_cdclk
= skl_calc_cdclk(0, vco
);
5622 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5624 /* select the minimum CDCLK before enabling DPLL 0 */
5625 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_cdclk
);
5626 I915_WRITE(CDCLK_CTL
, val
);
5627 POSTING_READ(CDCLK_CTL
);
5630 * We always enable DPLL0 with the lowest link rate possible, but still
5631 * taking into account the VCO required to operate the eDP panel at the
5632 * desired frequency. The usual DP link rates operate with a VCO of
5633 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5634 * The modeset code is responsible for the selection of the exact link
5635 * rate later on, with the constraint of choosing a frequency that
5638 val
= I915_READ(DPLL_CTRL1
);
5640 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5641 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5642 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5644 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5647 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5650 I915_WRITE(DPLL_CTRL1
, val
);
5651 POSTING_READ(DPLL_CTRL1
);
5653 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5655 if (intel_wait_for_register(dev_priv
,
5656 LCPLL1_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
5658 DRM_ERROR("DPLL0 not locked\n");
5660 dev_priv
->cdclk_pll
.vco
= vco
;
5662 /* We'll want to keep using the current vco from now on. */
5663 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
5667 skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
5669 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5670 if (intel_wait_for_register(dev_priv
,
5671 LCPLL1_CTL
, LCPLL_PLL_LOCK
, 0,
5673 DRM_ERROR("Couldn't disable DPLL0\n");
5675 dev_priv
->cdclk_pll
.vco
= 0;
5678 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5683 /* inform PCU we want to change CDCLK */
5684 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5685 mutex_lock(&dev_priv
->rps
.hw_lock
);
5686 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5687 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5689 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5692 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5694 return _wait_for(skl_cdclk_pcu_ready(dev_priv
), 3000, 10) == 0;
5697 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
, int vco
)
5699 struct drm_device
*dev
= &dev_priv
->drm
;
5700 u32 freq_select
, pcu_ack
;
5702 WARN_ON((cdclk
== 24000) != (vco
== 0));
5704 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5706 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5707 DRM_ERROR("failed to inform PCU about cdclk change\n");
5715 freq_select
= CDCLK_FREQ_450_432
;
5719 freq_select
= CDCLK_FREQ_540
;
5725 freq_select
= CDCLK_FREQ_337_308
;
5730 freq_select
= CDCLK_FREQ_675_617
;
5735 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5736 dev_priv
->cdclk_pll
.vco
!= vco
)
5737 skl_dpll0_disable(dev_priv
);
5739 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5740 skl_dpll0_enable(dev_priv
, vco
);
5742 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(cdclk
));
5743 POSTING_READ(CDCLK_CTL
);
5745 /* inform PCU of the change */
5746 mutex_lock(&dev_priv
->rps
.hw_lock
);
5747 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5748 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5750 intel_update_cdclk(dev
);
5753 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
5755 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5757 skl_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
, 0);
5760 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5764 skl_sanitize_cdclk(dev_priv
);
5766 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0) {
5768 * Use the current vco as our initial
5769 * guess as to what the preferred vco is.
5771 if (dev_priv
->skl_preferred_vco_freq
== 0)
5772 skl_set_preferred_cdclk_vco(dev_priv
,
5773 dev_priv
->cdclk_pll
.vco
);
5777 vco
= dev_priv
->skl_preferred_vco_freq
;
5780 cdclk
= skl_calc_cdclk(0, vco
);
5782 skl_set_cdclk(dev_priv
, cdclk
, vco
);
5785 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5787 uint32_t cdctl
, expected
;
5790 * check if the pre-os intialized the display
5791 * There is SWF18 scratchpad register defined which is set by the
5792 * pre-os which can be used by the OS drivers to check the status
5794 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5797 intel_update_cdclk(&dev_priv
->drm
);
5798 /* Is PLL enabled and locked ? */
5799 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5800 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5803 /* DPLL okay; verify the cdclock
5805 * Noticed in some instances that the freq selection is correct but
5806 * decimal part is programmed wrong from BIOS where pre-os does not
5807 * enable display. Verify the same as well.
5809 cdctl
= I915_READ(CDCLK_CTL
);
5810 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
5811 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5812 if (cdctl
== expected
)
5813 /* All well; nothing to sanitize */
5817 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5819 /* force cdclk programming */
5820 dev_priv
->cdclk_freq
= 0;
5821 /* force full PLL disable + enable */
5822 dev_priv
->cdclk_pll
.vco
= -1;
5825 /* Adjust CDclk dividers to allow high res or save power if possible */
5826 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5828 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5831 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5832 != dev_priv
->cdclk_freq
);
5834 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5836 else if (cdclk
== 266667)
5841 mutex_lock(&dev_priv
->rps
.hw_lock
);
5842 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5843 val
&= ~DSPFREQGUAR_MASK
;
5844 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5845 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5846 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5847 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5849 DRM_ERROR("timed out waiting for CDclk change\n");
5851 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5853 mutex_lock(&dev_priv
->sb_lock
);
5855 if (cdclk
== 400000) {
5858 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5860 /* adjust cdclk divider */
5861 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5862 val
&= ~CCK_FREQUENCY_VALUES
;
5864 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5866 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5867 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5869 DRM_ERROR("timed out waiting for CDclk change\n");
5872 /* adjust self-refresh exit latency value */
5873 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5877 * For high bandwidth configs, we set a higher latency in the bunit
5878 * so that the core display fetch happens in time to avoid underruns.
5880 if (cdclk
== 400000)
5881 val
|= 4500 / 250; /* 4.5 usec */
5883 val
|= 3000 / 250; /* 3.0 usec */
5884 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5886 mutex_unlock(&dev_priv
->sb_lock
);
5888 intel_update_cdclk(dev
);
5891 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5893 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5896 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5897 != dev_priv
->cdclk_freq
);
5906 MISSING_CASE(cdclk
);
5911 * Specs are full of misinformation, but testing on actual
5912 * hardware has shown that we just need to write the desired
5913 * CCK divider into the Punit register.
5915 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5917 mutex_lock(&dev_priv
->rps
.hw_lock
);
5918 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5919 val
&= ~DSPFREQGUAR_MASK_CHV
;
5920 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5921 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5922 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5923 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5925 DRM_ERROR("timed out waiting for CDclk change\n");
5927 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5929 intel_update_cdclk(dev
);
5932 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5935 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5936 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5939 * Really only a few cases to deal with, as only 4 CDclks are supported:
5942 * 320/333MHz (depends on HPLL freq)
5944 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5945 * of the lower bin and adjust if needed.
5947 * We seem to get an unstable or solid color picture at 200MHz.
5948 * Not sure what's wrong. For now use 200MHz only when all pipes
5951 if (!IS_CHERRYVIEW(dev_priv
) &&
5952 max_pixclk
> freq_320
*limit
/100)
5954 else if (max_pixclk
> 266667*limit
/100)
5956 else if (max_pixclk
> 0)
5962 static int bxt_calc_cdclk(int max_pixclk
)
5964 if (max_pixclk
> 576000)
5966 else if (max_pixclk
> 384000)
5968 else if (max_pixclk
> 288000)
5970 else if (max_pixclk
> 144000)
5976 /* Compute the max pixel clock for new configuration. */
5977 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5978 struct drm_atomic_state
*state
)
5980 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5981 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5982 struct drm_crtc
*crtc
;
5983 struct drm_crtc_state
*crtc_state
;
5984 unsigned max_pixclk
= 0, i
;
5987 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
5988 sizeof(intel_state
->min_pixclk
));
5990 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5993 if (crtc_state
->enable
)
5994 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
5996 intel_state
->min_pixclk
[i
] = pixclk
;
5999 for_each_pipe(dev_priv
, pipe
)
6000 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
6005 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6007 struct drm_device
*dev
= state
->dev
;
6008 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6009 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6010 struct intel_atomic_state
*intel_state
=
6011 to_intel_atomic_state(state
);
6013 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6014 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6016 if (!intel_state
->active_crtcs
)
6017 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
6022 static int bxt_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6024 int max_pixclk
= ilk_max_pixel_rate(state
);
6025 struct intel_atomic_state
*intel_state
=
6026 to_intel_atomic_state(state
);
6028 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6029 bxt_calc_cdclk(max_pixclk
);
6031 if (!intel_state
->active_crtcs
)
6032 intel_state
->dev_cdclk
= bxt_calc_cdclk(0);
6037 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6039 unsigned int credits
, default_credits
;
6041 if (IS_CHERRYVIEW(dev_priv
))
6042 default_credits
= PFI_CREDIT(12);
6044 default_credits
= PFI_CREDIT(8);
6046 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6047 /* CHV suggested value is 31 or 63 */
6048 if (IS_CHERRYVIEW(dev_priv
))
6049 credits
= PFI_CREDIT_63
;
6051 credits
= PFI_CREDIT(15);
6053 credits
= default_credits
;
6057 * WA - write default credits before re-programming
6058 * FIXME: should we also set the resend bit here?
6060 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6063 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6064 credits
| PFI_CREDIT_RESEND
);
6067 * FIXME is this guaranteed to clear
6068 * immediately or should we poll for it?
6070 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6073 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6075 struct drm_device
*dev
= old_state
->dev
;
6076 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6077 struct intel_atomic_state
*old_intel_state
=
6078 to_intel_atomic_state(old_state
);
6079 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6082 * FIXME: We can end up here with all power domains off, yet
6083 * with a CDCLK frequency other than the minimum. To account
6084 * for this take the PIPE-A power domain, which covers the HW
6085 * blocks needed for the following programming. This can be
6086 * removed once it's guaranteed that we get here either with
6087 * the minimum CDCLK set, or the required power domains
6090 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6092 if (IS_CHERRYVIEW(dev
))
6093 cherryview_set_cdclk(dev
, req_cdclk
);
6095 valleyview_set_cdclk(dev
, req_cdclk
);
6097 vlv_program_pfi_credits(dev_priv
);
6099 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6102 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6104 struct drm_device
*dev
= crtc
->dev
;
6105 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6106 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6107 struct intel_encoder
*encoder
;
6108 struct intel_crtc_state
*pipe_config
=
6109 to_intel_crtc_state(crtc
->state
);
6110 int pipe
= intel_crtc
->pipe
;
6112 if (WARN_ON(intel_crtc
->active
))
6115 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6116 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6118 intel_set_pipe_timings(intel_crtc
);
6119 intel_set_pipe_src_size(intel_crtc
);
6121 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6122 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6124 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6125 I915_WRITE(CHV_CANVAS(pipe
), 0);
6128 i9xx_set_pipeconf(intel_crtc
);
6130 intel_crtc
->active
= true;
6132 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6134 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6135 if (encoder
->pre_pll_enable
)
6136 encoder
->pre_pll_enable(encoder
);
6138 if (IS_CHERRYVIEW(dev
)) {
6139 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6140 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6142 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6143 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6146 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6147 if (encoder
->pre_enable
)
6148 encoder
->pre_enable(encoder
);
6150 i9xx_pfit_enable(intel_crtc
);
6152 intel_color_load_luts(&pipe_config
->base
);
6154 intel_update_watermarks(crtc
);
6155 intel_enable_pipe(intel_crtc
);
6157 assert_vblank_disabled(crtc
);
6158 drm_crtc_vblank_on(crtc
);
6160 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6161 encoder
->enable(encoder
);
6164 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6166 struct drm_device
*dev
= crtc
->base
.dev
;
6167 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6169 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6170 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6173 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6175 struct drm_device
*dev
= crtc
->dev
;
6176 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6177 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6178 struct intel_encoder
*encoder
;
6179 struct intel_crtc_state
*pipe_config
=
6180 to_intel_crtc_state(crtc
->state
);
6181 enum pipe pipe
= intel_crtc
->pipe
;
6183 if (WARN_ON(intel_crtc
->active
))
6186 i9xx_set_pll_dividers(intel_crtc
);
6188 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6189 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6191 intel_set_pipe_timings(intel_crtc
);
6192 intel_set_pipe_src_size(intel_crtc
);
6194 i9xx_set_pipeconf(intel_crtc
);
6196 intel_crtc
->active
= true;
6199 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6201 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6202 if (encoder
->pre_enable
)
6203 encoder
->pre_enable(encoder
);
6205 i9xx_enable_pll(intel_crtc
);
6207 i9xx_pfit_enable(intel_crtc
);
6209 intel_color_load_luts(&pipe_config
->base
);
6211 intel_update_watermarks(crtc
);
6212 intel_enable_pipe(intel_crtc
);
6214 assert_vblank_disabled(crtc
);
6215 drm_crtc_vblank_on(crtc
);
6217 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6218 encoder
->enable(encoder
);
6221 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6223 struct drm_device
*dev
= crtc
->base
.dev
;
6224 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6226 if (!crtc
->config
->gmch_pfit
.control
)
6229 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6231 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6232 I915_READ(PFIT_CONTROL
));
6233 I915_WRITE(PFIT_CONTROL
, 0);
6236 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6238 struct drm_device
*dev
= crtc
->dev
;
6239 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6240 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6241 struct intel_encoder
*encoder
;
6242 int pipe
= intel_crtc
->pipe
;
6245 * On gen2 planes are double buffered but the pipe isn't, so we must
6246 * wait for planes to fully turn off before disabling the pipe.
6249 intel_wait_for_vblank(dev
, pipe
);
6251 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6252 encoder
->disable(encoder
);
6254 drm_crtc_vblank_off(crtc
);
6255 assert_vblank_disabled(crtc
);
6257 intel_disable_pipe(intel_crtc
);
6259 i9xx_pfit_disable(intel_crtc
);
6261 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6262 if (encoder
->post_disable
)
6263 encoder
->post_disable(encoder
);
6265 if (!intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DSI
)) {
6266 if (IS_CHERRYVIEW(dev
))
6267 chv_disable_pll(dev_priv
, pipe
);
6268 else if (IS_VALLEYVIEW(dev
))
6269 vlv_disable_pll(dev_priv
, pipe
);
6271 i9xx_disable_pll(intel_crtc
);
6274 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6275 if (encoder
->post_pll_disable
)
6276 encoder
->post_pll_disable(encoder
);
6279 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6282 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6284 struct intel_encoder
*encoder
;
6285 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6286 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6287 enum intel_display_power_domain domain
;
6288 unsigned long domains
;
6290 if (!intel_crtc
->active
)
6293 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6294 WARN_ON(intel_crtc
->flip_work
);
6296 intel_pre_disable_primary_noatomic(crtc
);
6298 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6299 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6302 dev_priv
->display
.crtc_disable(crtc
);
6304 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6305 crtc
->base
.id
, crtc
->name
);
6307 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6308 crtc
->state
->active
= false;
6309 intel_crtc
->active
= false;
6310 crtc
->enabled
= false;
6311 crtc
->state
->connector_mask
= 0;
6312 crtc
->state
->encoder_mask
= 0;
6314 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6315 encoder
->base
.crtc
= NULL
;
6317 intel_fbc_disable(intel_crtc
);
6318 intel_update_watermarks(crtc
);
6319 intel_disable_shared_dpll(intel_crtc
);
6321 domains
= intel_crtc
->enabled_power_domains
;
6322 for_each_power_domain(domain
, domains
)
6323 intel_display_power_put(dev_priv
, domain
);
6324 intel_crtc
->enabled_power_domains
= 0;
6326 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6327 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6331 * turn all crtc's off, but do not adjust state
6332 * This has to be paired with a call to intel_modeset_setup_hw_state.
6334 int intel_display_suspend(struct drm_device
*dev
)
6336 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6337 struct drm_atomic_state
*state
;
6340 state
= drm_atomic_helper_suspend(dev
);
6341 ret
= PTR_ERR_OR_ZERO(state
);
6343 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6345 dev_priv
->modeset_restore_state
= state
;
6349 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6351 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6353 drm_encoder_cleanup(encoder
);
6354 kfree(intel_encoder
);
6357 /* Cross check the actual hw state with our own modeset state tracking (and it's
6358 * internal consistency). */
6359 static void intel_connector_verify_state(struct intel_connector
*connector
)
6361 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6363 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6364 connector
->base
.base
.id
,
6365 connector
->base
.name
);
6367 if (connector
->get_hw_state(connector
)) {
6368 struct intel_encoder
*encoder
= connector
->encoder
;
6369 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6371 I915_STATE_WARN(!crtc
,
6372 "connector enabled without attached crtc\n");
6377 I915_STATE_WARN(!crtc
->state
->active
,
6378 "connector is active, but attached crtc isn't\n");
6380 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6383 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6384 "atomic encoder doesn't match attached encoder\n");
6386 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6387 "attached encoder crtc differs from connector crtc\n");
6389 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6390 "attached crtc is active, but connector isn't\n");
6391 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6392 "best encoder set without crtc!\n");
6396 int intel_connector_init(struct intel_connector
*connector
)
6398 drm_atomic_helper_connector_reset(&connector
->base
);
6400 if (!connector
->base
.state
)
6406 struct intel_connector
*intel_connector_alloc(void)
6408 struct intel_connector
*connector
;
6410 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6414 if (intel_connector_init(connector
) < 0) {
6422 /* Simple connector->get_hw_state implementation for encoders that support only
6423 * one connector and no cloning and hence the encoder state determines the state
6424 * of the connector. */
6425 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6428 struct intel_encoder
*encoder
= connector
->encoder
;
6430 return encoder
->get_hw_state(encoder
, &pipe
);
6433 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6435 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6436 return crtc_state
->fdi_lanes
;
6441 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6442 struct intel_crtc_state
*pipe_config
)
6444 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6445 struct intel_crtc
*other_crtc
;
6446 struct intel_crtc_state
*other_crtc_state
;
6448 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6449 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6450 if (pipe_config
->fdi_lanes
> 4) {
6451 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6452 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6456 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6457 if (pipe_config
->fdi_lanes
> 2) {
6458 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6459 pipe_config
->fdi_lanes
);
6466 if (INTEL_INFO(dev
)->num_pipes
== 2)
6469 /* Ivybridge 3 pipe is really complicated */
6474 if (pipe_config
->fdi_lanes
<= 2)
6477 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6479 intel_atomic_get_crtc_state(state
, other_crtc
);
6480 if (IS_ERR(other_crtc_state
))
6481 return PTR_ERR(other_crtc_state
);
6483 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6484 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6485 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6490 if (pipe_config
->fdi_lanes
> 2) {
6491 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6492 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6496 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6498 intel_atomic_get_crtc_state(state
, other_crtc
);
6499 if (IS_ERR(other_crtc_state
))
6500 return PTR_ERR(other_crtc_state
);
6502 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6503 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6513 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6514 struct intel_crtc_state
*pipe_config
)
6516 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6517 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6518 int lane
, link_bw
, fdi_dotclock
, ret
;
6519 bool needs_recompute
= false;
6522 /* FDI is a binary signal running at ~2.7GHz, encoding
6523 * each output octet as 10 bits. The actual frequency
6524 * is stored as a divider into a 100MHz clock, and the
6525 * mode pixel clock is stored in units of 1KHz.
6526 * Hence the bw of each lane in terms of the mode signal
6529 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6531 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6533 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6534 pipe_config
->pipe_bpp
);
6536 pipe_config
->fdi_lanes
= lane
;
6538 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6539 link_bw
, &pipe_config
->fdi_m_n
);
6541 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6542 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6543 pipe_config
->pipe_bpp
-= 2*3;
6544 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6545 pipe_config
->pipe_bpp
);
6546 needs_recompute
= true;
6547 pipe_config
->bw_constrained
= true;
6552 if (needs_recompute
)
6558 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6559 struct intel_crtc_state
*pipe_config
)
6561 if (pipe_config
->pipe_bpp
> 24)
6564 /* HSW can handle pixel rate up to cdclk? */
6565 if (IS_HASWELL(dev_priv
))
6569 * We compare against max which means we must take
6570 * the increased cdclk requirement into account when
6571 * calculating the new cdclk.
6573 * Should measure whether using a lower cdclk w/o IPS
6575 return ilk_pipe_pixel_rate(pipe_config
) <=
6576 dev_priv
->max_cdclk_freq
* 95 / 100;
6579 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6580 struct intel_crtc_state
*pipe_config
)
6582 struct drm_device
*dev
= crtc
->base
.dev
;
6583 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6585 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6586 hsw_crtc_supports_ips(crtc
) &&
6587 pipe_config_supports_ips(dev_priv
, pipe_config
);
6590 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6592 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6594 /* GDG double wide on either pipe, otherwise pipe A only */
6595 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6596 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6599 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6600 struct intel_crtc_state
*pipe_config
)
6602 struct drm_device
*dev
= crtc
->base
.dev
;
6603 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6604 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6605 int clock_limit
= dev_priv
->max_dotclk_freq
;
6607 if (INTEL_INFO(dev
)->gen
< 4) {
6608 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6611 * Enable double wide mode when the dot clock
6612 * is > 90% of the (display) core speed.
6614 if (intel_crtc_supports_double_wide(crtc
) &&
6615 adjusted_mode
->crtc_clock
> clock_limit
) {
6616 clock_limit
= dev_priv
->max_dotclk_freq
;
6617 pipe_config
->double_wide
= true;
6621 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6622 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6623 adjusted_mode
->crtc_clock
, clock_limit
,
6624 yesno(pipe_config
->double_wide
));
6629 * Pipe horizontal size must be even in:
6631 * - LVDS dual channel mode
6632 * - Double wide pipe
6634 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6635 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6636 pipe_config
->pipe_src_w
&= ~1;
6638 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6639 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6641 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6642 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6646 hsw_compute_ips_config(crtc
, pipe_config
);
6648 if (pipe_config
->has_pch_encoder
)
6649 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6654 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6656 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6659 skl_dpll0_update(dev_priv
);
6661 if (dev_priv
->cdclk_pll
.vco
== 0)
6662 return dev_priv
->cdclk_pll
.ref
;
6664 cdctl
= I915_READ(CDCLK_CTL
);
6666 if (dev_priv
->cdclk_pll
.vco
== 8640000) {
6667 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6668 case CDCLK_FREQ_450_432
:
6670 case CDCLK_FREQ_337_308
:
6672 case CDCLK_FREQ_540
:
6674 case CDCLK_FREQ_675_617
:
6677 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6680 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6681 case CDCLK_FREQ_450_432
:
6683 case CDCLK_FREQ_337_308
:
6685 case CDCLK_FREQ_540
:
6687 case CDCLK_FREQ_675_617
:
6690 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6694 return dev_priv
->cdclk_pll
.ref
;
6697 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
)
6701 dev_priv
->cdclk_pll
.ref
= 19200;
6702 dev_priv
->cdclk_pll
.vco
= 0;
6704 val
= I915_READ(BXT_DE_PLL_ENABLE
);
6705 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
6708 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
6711 val
= I915_READ(BXT_DE_PLL_CTL
);
6712 dev_priv
->cdclk_pll
.vco
= (val
& BXT_DE_PLL_RATIO_MASK
) *
6713 dev_priv
->cdclk_pll
.ref
;
6716 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6718 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6722 bxt_de_pll_update(dev_priv
);
6724 vco
= dev_priv
->cdclk_pll
.vco
;
6726 return dev_priv
->cdclk_pll
.ref
;
6728 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
6731 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6734 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6737 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6740 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6744 MISSING_CASE(divider
);
6745 return dev_priv
->cdclk_pll
.ref
;
6748 return DIV_ROUND_CLOSEST(vco
, div
);
6751 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6753 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6754 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6755 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6757 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6759 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6761 else if (freq
== LCPLL_CLK_FREQ_450
)
6763 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6765 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6771 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6773 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6774 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6775 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6777 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6779 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6781 else if (freq
== LCPLL_CLK_FREQ_450
)
6783 else if (IS_HSW_ULT(dev
))
6789 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6791 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6792 CCK_DISPLAY_CLOCK_CONTROL
);
6795 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6800 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6805 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6810 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6815 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6819 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6821 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6822 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6824 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6826 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6828 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6831 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6832 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6834 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6839 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6843 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6845 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6848 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6849 case GC_DISPLAY_CLOCK_333_MHZ
:
6852 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6858 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6863 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6868 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6869 * encoding is different :(
6870 * FIXME is this the right way to detect 852GM/852GMV?
6872 if (dev
->pdev
->revision
== 0x1)
6875 pci_bus_read_config_word(dev
->pdev
->bus
,
6876 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6878 /* Assume that the hardware is in the high speed state. This
6879 * should be the default.
6881 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6882 case GC_CLOCK_133_200
:
6883 case GC_CLOCK_133_200_2
:
6884 case GC_CLOCK_100_200
:
6886 case GC_CLOCK_166_250
:
6888 case GC_CLOCK_100_133
:
6890 case GC_CLOCK_133_266
:
6891 case GC_CLOCK_133_266_2
:
6892 case GC_CLOCK_166_266
:
6896 /* Shouldn't happen */
6900 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6905 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6907 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6908 static const unsigned int blb_vco
[8] = {
6915 static const unsigned int pnv_vco
[8] = {
6922 static const unsigned int cl_vco
[8] = {
6931 static const unsigned int elk_vco
[8] = {
6937 static const unsigned int ctg_vco
[8] = {
6945 const unsigned int *vco_table
;
6949 /* FIXME other chipsets? */
6951 vco_table
= ctg_vco
;
6952 else if (IS_G4X(dev
))
6953 vco_table
= elk_vco
;
6954 else if (IS_CRESTLINE(dev
))
6956 else if (IS_PINEVIEW(dev
))
6957 vco_table
= pnv_vco
;
6958 else if (IS_G33(dev
))
6959 vco_table
= blb_vco
;
6963 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6965 vco
= vco_table
[tmp
& 0x7];
6967 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6969 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6974 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6976 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6979 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6981 cdclk_sel
= (tmp
>> 12) & 0x1;
6987 return cdclk_sel
? 333333 : 222222;
6989 return cdclk_sel
? 320000 : 228571;
6991 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
6996 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
6998 static const uint8_t div_3200
[] = { 16, 10, 8 };
6999 static const uint8_t div_4000
[] = { 20, 12, 10 };
7000 static const uint8_t div_5333
[] = { 24, 16, 14 };
7001 const uint8_t *div_table
;
7002 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7005 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7007 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7009 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7014 div_table
= div_3200
;
7017 div_table
= div_4000
;
7020 div_table
= div_5333
;
7026 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7029 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7033 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7035 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7036 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7037 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7038 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7039 const uint8_t *div_table
;
7040 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7043 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7045 cdclk_sel
= (tmp
>> 4) & 0x7;
7047 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7052 div_table
= div_3200
;
7055 div_table
= div_4000
;
7058 div_table
= div_4800
;
7061 div_table
= div_5333
;
7067 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7070 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7075 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7077 while (*num
> DATA_LINK_M_N_MASK
||
7078 *den
> DATA_LINK_M_N_MASK
) {
7084 static void compute_m_n(unsigned int m
, unsigned int n
,
7085 uint32_t *ret_m
, uint32_t *ret_n
)
7087 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7088 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7089 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7093 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7094 int pixel_clock
, int link_clock
,
7095 struct intel_link_m_n
*m_n
)
7099 compute_m_n(bits_per_pixel
* pixel_clock
,
7100 link_clock
* nlanes
* 8,
7101 &m_n
->gmch_m
, &m_n
->gmch_n
);
7103 compute_m_n(pixel_clock
, link_clock
,
7104 &m_n
->link_m
, &m_n
->link_n
);
7107 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7109 if (i915
.panel_use_ssc
>= 0)
7110 return i915
.panel_use_ssc
!= 0;
7111 return dev_priv
->vbt
.lvds_use_ssc
7112 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7115 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7117 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7120 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7122 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7125 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7126 struct intel_crtc_state
*crtc_state
,
7127 struct dpll
*reduced_clock
)
7129 struct drm_device
*dev
= crtc
->base
.dev
;
7132 if (IS_PINEVIEW(dev
)) {
7133 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7135 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7137 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7139 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7142 crtc_state
->dpll_hw_state
.fp0
= fp
;
7144 crtc
->lowfreq_avail
= false;
7145 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7147 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7148 crtc
->lowfreq_avail
= true;
7150 crtc_state
->dpll_hw_state
.fp1
= fp
;
7154 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7160 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7161 * and set it to a reasonable value instead.
7163 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7164 reg_val
&= 0xffffff00;
7165 reg_val
|= 0x00000030;
7166 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7168 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7169 reg_val
&= 0x8cffffff;
7170 reg_val
= 0x8c000000;
7171 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7173 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7174 reg_val
&= 0xffffff00;
7175 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7177 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7178 reg_val
&= 0x00ffffff;
7179 reg_val
|= 0xb0000000;
7180 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7183 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7184 struct intel_link_m_n
*m_n
)
7186 struct drm_device
*dev
= crtc
->base
.dev
;
7187 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7188 int pipe
= crtc
->pipe
;
7190 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7191 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7192 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7193 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7196 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7197 struct intel_link_m_n
*m_n
,
7198 struct intel_link_m_n
*m2_n2
)
7200 struct drm_device
*dev
= crtc
->base
.dev
;
7201 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7202 int pipe
= crtc
->pipe
;
7203 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7205 if (INTEL_INFO(dev
)->gen
>= 5) {
7206 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7207 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7208 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7209 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7210 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7211 * for gen < 8) and if DRRS is supported (to make sure the
7212 * registers are not unnecessarily accessed).
7214 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7215 crtc
->config
->has_drrs
) {
7216 I915_WRITE(PIPE_DATA_M2(transcoder
),
7217 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7218 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7219 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7220 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7223 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7224 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7225 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7226 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7230 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7232 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7235 dp_m_n
= &crtc
->config
->dp_m_n
;
7236 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7237 } else if (m_n
== M2_N2
) {
7240 * M2_N2 registers are not supported. Hence m2_n2 divider value
7241 * needs to be programmed into M1_N1.
7243 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7245 DRM_ERROR("Unsupported divider value\n");
7249 if (crtc
->config
->has_pch_encoder
)
7250 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7252 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7255 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7256 struct intel_crtc_state
*pipe_config
)
7258 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7259 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7260 if (crtc
->pipe
!= PIPE_A
)
7261 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7263 /* DPLL not used with DSI, but still need the rest set up */
7264 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7265 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7266 DPLL_EXT_BUFFER_ENABLE_VLV
;
7268 pipe_config
->dpll_hw_state
.dpll_md
=
7269 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7272 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7273 struct intel_crtc_state
*pipe_config
)
7275 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7276 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7277 if (crtc
->pipe
!= PIPE_A
)
7278 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7280 /* DPLL not used with DSI, but still need the rest set up */
7281 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7282 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7284 pipe_config
->dpll_hw_state
.dpll_md
=
7285 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7288 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7289 const struct intel_crtc_state
*pipe_config
)
7291 struct drm_device
*dev
= crtc
->base
.dev
;
7292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7293 enum pipe pipe
= crtc
->pipe
;
7295 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7296 u32 coreclk
, reg_val
;
7299 I915_WRITE(DPLL(pipe
),
7300 pipe_config
->dpll_hw_state
.dpll
&
7301 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7303 /* No need to actually set up the DPLL with DSI */
7304 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7307 mutex_lock(&dev_priv
->sb_lock
);
7309 bestn
= pipe_config
->dpll
.n
;
7310 bestm1
= pipe_config
->dpll
.m1
;
7311 bestm2
= pipe_config
->dpll
.m2
;
7312 bestp1
= pipe_config
->dpll
.p1
;
7313 bestp2
= pipe_config
->dpll
.p2
;
7315 /* See eDP HDMI DPIO driver vbios notes doc */
7317 /* PLL B needs special handling */
7319 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7321 /* Set up Tx target for periodic Rcomp update */
7322 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7324 /* Disable target IRef on PLL */
7325 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7326 reg_val
&= 0x00ffffff;
7327 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7329 /* Disable fast lock */
7330 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7332 /* Set idtafcrecal before PLL is enabled */
7333 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7334 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7335 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7336 mdiv
|= (1 << DPIO_K_SHIFT
);
7339 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7340 * but we don't support that).
7341 * Note: don't use the DAC post divider as it seems unstable.
7343 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7344 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7346 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7347 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7349 /* Set HBR and RBR LPF coefficients */
7350 if (pipe_config
->port_clock
== 162000 ||
7351 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
7352 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
7353 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7356 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7359 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7360 /* Use SSC source */
7362 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7365 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7367 } else { /* HDMI or VGA */
7368 /* Use bend source */
7370 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7373 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7377 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7378 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7379 if (intel_crtc_has_dp_encoder(crtc
->config
))
7380 coreclk
|= 0x01000000;
7381 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7383 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7384 mutex_unlock(&dev_priv
->sb_lock
);
7387 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7388 const struct intel_crtc_state
*pipe_config
)
7390 struct drm_device
*dev
= crtc
->base
.dev
;
7391 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7392 enum pipe pipe
= crtc
->pipe
;
7393 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7394 u32 loopfilter
, tribuf_calcntr
;
7395 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7399 /* Enable Refclk and SSC */
7400 I915_WRITE(DPLL(pipe
),
7401 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7403 /* No need to actually set up the DPLL with DSI */
7404 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7407 bestn
= pipe_config
->dpll
.n
;
7408 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7409 bestm1
= pipe_config
->dpll
.m1
;
7410 bestm2
= pipe_config
->dpll
.m2
>> 22;
7411 bestp1
= pipe_config
->dpll
.p1
;
7412 bestp2
= pipe_config
->dpll
.p2
;
7413 vco
= pipe_config
->dpll
.vco
;
7417 mutex_lock(&dev_priv
->sb_lock
);
7419 /* p1 and p2 divider */
7420 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7421 5 << DPIO_CHV_S1_DIV_SHIFT
|
7422 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7423 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7424 1 << DPIO_CHV_K_DIV_SHIFT
);
7426 /* Feedback post-divider - m2 */
7427 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7429 /* Feedback refclk divider - n and m1 */
7430 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7431 DPIO_CHV_M1_DIV_BY_2
|
7432 1 << DPIO_CHV_N_DIV_SHIFT
);
7434 /* M2 fraction division */
7435 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7437 /* M2 fraction division enable */
7438 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7439 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7440 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7442 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7443 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7445 /* Program digital lock detect threshold */
7446 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7447 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7448 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7449 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7451 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7452 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7455 if (vco
== 5400000) {
7456 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7457 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7458 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7459 tribuf_calcntr
= 0x9;
7460 } else if (vco
<= 6200000) {
7461 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7462 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7463 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7464 tribuf_calcntr
= 0x9;
7465 } else if (vco
<= 6480000) {
7466 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7467 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7468 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7469 tribuf_calcntr
= 0x8;
7471 /* Not supported. Apply the same limits as in the max case */
7472 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7473 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7474 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7477 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7479 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7480 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7481 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7482 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7485 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7486 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7489 mutex_unlock(&dev_priv
->sb_lock
);
7493 * vlv_force_pll_on - forcibly enable just the PLL
7494 * @dev_priv: i915 private structure
7495 * @pipe: pipe PLL to enable
7496 * @dpll: PLL configuration
7498 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7499 * in cases where we need the PLL enabled even when @pipe is not going to
7502 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7503 const struct dpll
*dpll
)
7505 struct intel_crtc
*crtc
=
7506 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7507 struct intel_crtc_state
*pipe_config
;
7509 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7513 pipe_config
->base
.crtc
= &crtc
->base
;
7514 pipe_config
->pixel_multiplier
= 1;
7515 pipe_config
->dpll
= *dpll
;
7517 if (IS_CHERRYVIEW(dev
)) {
7518 chv_compute_dpll(crtc
, pipe_config
);
7519 chv_prepare_pll(crtc
, pipe_config
);
7520 chv_enable_pll(crtc
, pipe_config
);
7522 vlv_compute_dpll(crtc
, pipe_config
);
7523 vlv_prepare_pll(crtc
, pipe_config
);
7524 vlv_enable_pll(crtc
, pipe_config
);
7533 * vlv_force_pll_off - forcibly disable just the PLL
7534 * @dev_priv: i915 private structure
7535 * @pipe: pipe PLL to disable
7537 * Disable the PLL for @pipe. To be used in cases where we need
7538 * the PLL enabled even when @pipe is not going to be enabled.
7540 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7542 if (IS_CHERRYVIEW(dev
))
7543 chv_disable_pll(to_i915(dev
), pipe
);
7545 vlv_disable_pll(to_i915(dev
), pipe
);
7548 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7549 struct intel_crtc_state
*crtc_state
,
7550 struct dpll
*reduced_clock
)
7552 struct drm_device
*dev
= crtc
->base
.dev
;
7553 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7555 struct dpll
*clock
= &crtc_state
->dpll
;
7557 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7559 dpll
= DPLL_VGA_MODE_DIS
;
7561 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7562 dpll
|= DPLLB_MODE_LVDS
;
7564 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7566 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7567 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7568 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7571 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7572 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7573 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7575 if (intel_crtc_has_dp_encoder(crtc_state
))
7576 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7578 /* compute bitmask from p1 value */
7579 if (IS_PINEVIEW(dev
))
7580 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7582 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7583 if (IS_G4X(dev
) && reduced_clock
)
7584 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7586 switch (clock
->p2
) {
7588 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7591 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7594 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7597 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7600 if (INTEL_INFO(dev
)->gen
>= 4)
7601 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7603 if (crtc_state
->sdvo_tv_clock
)
7604 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7605 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7606 intel_panel_use_ssc(dev_priv
))
7607 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7609 dpll
|= PLL_REF_INPUT_DREFCLK
;
7611 dpll
|= DPLL_VCO_ENABLE
;
7612 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7614 if (INTEL_INFO(dev
)->gen
>= 4) {
7615 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7616 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7617 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7621 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7622 struct intel_crtc_state
*crtc_state
,
7623 struct dpll
*reduced_clock
)
7625 struct drm_device
*dev
= crtc
->base
.dev
;
7626 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7628 struct dpll
*clock
= &crtc_state
->dpll
;
7630 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7632 dpll
= DPLL_VGA_MODE_DIS
;
7634 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7635 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7638 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7640 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7642 dpll
|= PLL_P2_DIVIDE_BY_4
;
7645 if (!IS_I830(dev
) && intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7646 dpll
|= DPLL_DVO_2X_MODE
;
7648 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7649 intel_panel_use_ssc(dev_priv
))
7650 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7652 dpll
|= PLL_REF_INPUT_DREFCLK
;
7654 dpll
|= DPLL_VCO_ENABLE
;
7655 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7658 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7660 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7661 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7662 enum pipe pipe
= intel_crtc
->pipe
;
7663 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7664 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7665 uint32_t crtc_vtotal
, crtc_vblank_end
;
7668 /* We need to be careful not to changed the adjusted mode, for otherwise
7669 * the hw state checker will get angry at the mismatch. */
7670 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7671 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7673 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7674 /* the chip adds 2 halflines automatically */
7676 crtc_vblank_end
-= 1;
7678 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7679 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7681 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7682 adjusted_mode
->crtc_htotal
/ 2;
7684 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7687 if (INTEL_INFO(dev
)->gen
> 3)
7688 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7690 I915_WRITE(HTOTAL(cpu_transcoder
),
7691 (adjusted_mode
->crtc_hdisplay
- 1) |
7692 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7693 I915_WRITE(HBLANK(cpu_transcoder
),
7694 (adjusted_mode
->crtc_hblank_start
- 1) |
7695 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7696 I915_WRITE(HSYNC(cpu_transcoder
),
7697 (adjusted_mode
->crtc_hsync_start
- 1) |
7698 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7700 I915_WRITE(VTOTAL(cpu_transcoder
),
7701 (adjusted_mode
->crtc_vdisplay
- 1) |
7702 ((crtc_vtotal
- 1) << 16));
7703 I915_WRITE(VBLANK(cpu_transcoder
),
7704 (adjusted_mode
->crtc_vblank_start
- 1) |
7705 ((crtc_vblank_end
- 1) << 16));
7706 I915_WRITE(VSYNC(cpu_transcoder
),
7707 (adjusted_mode
->crtc_vsync_start
- 1) |
7708 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7710 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7711 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7712 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7714 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7715 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7716 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7720 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7722 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7723 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7724 enum pipe pipe
= intel_crtc
->pipe
;
7726 /* pipesrc controls the size that is scaled from, which should
7727 * always be the user's requested size.
7729 I915_WRITE(PIPESRC(pipe
),
7730 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7731 (intel_crtc
->config
->pipe_src_h
- 1));
7734 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7735 struct intel_crtc_state
*pipe_config
)
7737 struct drm_device
*dev
= crtc
->base
.dev
;
7738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7739 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7742 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7743 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7744 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7745 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7746 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7747 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7748 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7749 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7750 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7752 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7753 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7754 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7755 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7756 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7757 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7758 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7759 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7760 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7762 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7763 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7764 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7765 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7769 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7770 struct intel_crtc_state
*pipe_config
)
7772 struct drm_device
*dev
= crtc
->base
.dev
;
7773 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7776 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7777 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7778 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7780 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7781 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7784 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7785 struct intel_crtc_state
*pipe_config
)
7787 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7788 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7789 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7790 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7792 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7793 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7794 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7795 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7797 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7798 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7800 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7801 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7803 mode
->hsync
= drm_mode_hsync(mode
);
7804 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7805 drm_mode_set_name(mode
);
7808 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7810 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7811 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7816 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7817 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7818 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7820 if (intel_crtc
->config
->double_wide
)
7821 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7823 /* only g4x and later have fancy bpc/dither controls */
7824 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
7825 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7826 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7827 pipeconf
|= PIPECONF_DITHER_EN
|
7828 PIPECONF_DITHER_TYPE_SP
;
7830 switch (intel_crtc
->config
->pipe_bpp
) {
7832 pipeconf
|= PIPECONF_6BPC
;
7835 pipeconf
|= PIPECONF_8BPC
;
7838 pipeconf
|= PIPECONF_10BPC
;
7841 /* Case prevented by intel_choose_pipe_bpp_dither. */
7846 if (HAS_PIPE_CXSR(dev
)) {
7847 if (intel_crtc
->lowfreq_avail
) {
7848 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7849 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7851 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7855 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7856 if (INTEL_INFO(dev
)->gen
< 4 ||
7857 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7858 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7860 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7862 pipeconf
|= PIPECONF_PROGRESSIVE
;
7864 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
7865 intel_crtc
->config
->limited_color_range
)
7866 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7868 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7869 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7872 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7873 struct intel_crtc_state
*crtc_state
)
7875 struct drm_device
*dev
= crtc
->base
.dev
;
7876 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7877 const struct intel_limit
*limit
;
7880 memset(&crtc_state
->dpll_hw_state
, 0,
7881 sizeof(crtc_state
->dpll_hw_state
));
7883 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7884 if (intel_panel_use_ssc(dev_priv
)) {
7885 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7886 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7889 limit
= &intel_limits_i8xx_lvds
;
7890 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7891 limit
= &intel_limits_i8xx_dvo
;
7893 limit
= &intel_limits_i8xx_dac
;
7896 if (!crtc_state
->clock_set
&&
7897 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7898 refclk
, NULL
, &crtc_state
->dpll
)) {
7899 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7903 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7908 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7909 struct intel_crtc_state
*crtc_state
)
7911 struct drm_device
*dev
= crtc
->base
.dev
;
7912 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7913 const struct intel_limit
*limit
;
7916 memset(&crtc_state
->dpll_hw_state
, 0,
7917 sizeof(crtc_state
->dpll_hw_state
));
7919 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7920 if (intel_panel_use_ssc(dev_priv
)) {
7921 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7922 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7925 if (intel_is_dual_link_lvds(dev
))
7926 limit
= &intel_limits_g4x_dual_channel_lvds
;
7928 limit
= &intel_limits_g4x_single_channel_lvds
;
7929 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7930 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7931 limit
= &intel_limits_g4x_hdmi
;
7932 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7933 limit
= &intel_limits_g4x_sdvo
;
7935 /* The option is for other outputs */
7936 limit
= &intel_limits_i9xx_sdvo
;
7939 if (!crtc_state
->clock_set
&&
7940 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7941 refclk
, NULL
, &crtc_state
->dpll
)) {
7942 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7946 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7951 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7952 struct intel_crtc_state
*crtc_state
)
7954 struct drm_device
*dev
= crtc
->base
.dev
;
7955 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7956 const struct intel_limit
*limit
;
7959 memset(&crtc_state
->dpll_hw_state
, 0,
7960 sizeof(crtc_state
->dpll_hw_state
));
7962 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7963 if (intel_panel_use_ssc(dev_priv
)) {
7964 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7965 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7968 limit
= &intel_limits_pineview_lvds
;
7970 limit
= &intel_limits_pineview_sdvo
;
7973 if (!crtc_state
->clock_set
&&
7974 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7975 refclk
, NULL
, &crtc_state
->dpll
)) {
7976 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7980 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7985 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7986 struct intel_crtc_state
*crtc_state
)
7988 struct drm_device
*dev
= crtc
->base
.dev
;
7989 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7990 const struct intel_limit
*limit
;
7993 memset(&crtc_state
->dpll_hw_state
, 0,
7994 sizeof(crtc_state
->dpll_hw_state
));
7996 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7997 if (intel_panel_use_ssc(dev_priv
)) {
7998 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7999 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8002 limit
= &intel_limits_i9xx_lvds
;
8004 limit
= &intel_limits_i9xx_sdvo
;
8007 if (!crtc_state
->clock_set
&&
8008 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8009 refclk
, NULL
, &crtc_state
->dpll
)) {
8010 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8014 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8019 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8020 struct intel_crtc_state
*crtc_state
)
8022 int refclk
= 100000;
8023 const struct intel_limit
*limit
= &intel_limits_chv
;
8025 memset(&crtc_state
->dpll_hw_state
, 0,
8026 sizeof(crtc_state
->dpll_hw_state
));
8028 if (!crtc_state
->clock_set
&&
8029 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8030 refclk
, NULL
, &crtc_state
->dpll
)) {
8031 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8035 chv_compute_dpll(crtc
, crtc_state
);
8040 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8041 struct intel_crtc_state
*crtc_state
)
8043 int refclk
= 100000;
8044 const struct intel_limit
*limit
= &intel_limits_vlv
;
8046 memset(&crtc_state
->dpll_hw_state
, 0,
8047 sizeof(crtc_state
->dpll_hw_state
));
8049 if (!crtc_state
->clock_set
&&
8050 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8051 refclk
, NULL
, &crtc_state
->dpll
)) {
8052 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8056 vlv_compute_dpll(crtc
, crtc_state
);
8061 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8062 struct intel_crtc_state
*pipe_config
)
8064 struct drm_device
*dev
= crtc
->base
.dev
;
8065 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8068 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
8071 tmp
= I915_READ(PFIT_CONTROL
);
8072 if (!(tmp
& PFIT_ENABLE
))
8075 /* Check whether the pfit is attached to our pipe. */
8076 if (INTEL_INFO(dev
)->gen
< 4) {
8077 if (crtc
->pipe
!= PIPE_B
)
8080 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8084 pipe_config
->gmch_pfit
.control
= tmp
;
8085 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8088 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8089 struct intel_crtc_state
*pipe_config
)
8091 struct drm_device
*dev
= crtc
->base
.dev
;
8092 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8093 int pipe
= pipe_config
->cpu_transcoder
;
8096 int refclk
= 100000;
8098 /* In case of DSI, DPLL will not be used */
8099 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8102 mutex_lock(&dev_priv
->sb_lock
);
8103 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8104 mutex_unlock(&dev_priv
->sb_lock
);
8106 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8107 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8108 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8109 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8110 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8112 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8116 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8117 struct intel_initial_plane_config
*plane_config
)
8119 struct drm_device
*dev
= crtc
->base
.dev
;
8120 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8121 u32 val
, base
, offset
;
8122 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8123 int fourcc
, pixel_format
;
8124 unsigned int aligned_height
;
8125 struct drm_framebuffer
*fb
;
8126 struct intel_framebuffer
*intel_fb
;
8128 val
= I915_READ(DSPCNTR(plane
));
8129 if (!(val
& DISPLAY_PLANE_ENABLE
))
8132 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8134 DRM_DEBUG_KMS("failed to alloc fb\n");
8138 fb
= &intel_fb
->base
;
8140 if (INTEL_INFO(dev
)->gen
>= 4) {
8141 if (val
& DISPPLANE_TILED
) {
8142 plane_config
->tiling
= I915_TILING_X
;
8143 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8147 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8148 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8149 fb
->pixel_format
= fourcc
;
8150 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8152 if (INTEL_INFO(dev
)->gen
>= 4) {
8153 if (plane_config
->tiling
)
8154 offset
= I915_READ(DSPTILEOFF(plane
));
8156 offset
= I915_READ(DSPLINOFF(plane
));
8157 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8159 base
= I915_READ(DSPADDR(plane
));
8161 plane_config
->base
= base
;
8163 val
= I915_READ(PIPESRC(pipe
));
8164 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8165 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8167 val
= I915_READ(DSPSTRIDE(pipe
));
8168 fb
->pitches
[0] = val
& 0xffffffc0;
8170 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8174 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8176 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8177 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8178 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8179 plane_config
->size
);
8181 plane_config
->fb
= intel_fb
;
8184 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8185 struct intel_crtc_state
*pipe_config
)
8187 struct drm_device
*dev
= crtc
->base
.dev
;
8188 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8189 int pipe
= pipe_config
->cpu_transcoder
;
8190 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8192 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8193 int refclk
= 100000;
8195 /* In case of DSI, DPLL will not be used */
8196 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8199 mutex_lock(&dev_priv
->sb_lock
);
8200 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8201 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8202 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8203 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8204 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8205 mutex_unlock(&dev_priv
->sb_lock
);
8207 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8208 clock
.m2
= (pll_dw0
& 0xff) << 22;
8209 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8210 clock
.m2
|= pll_dw2
& 0x3fffff;
8211 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8212 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8213 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8215 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8218 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8219 struct intel_crtc_state
*pipe_config
)
8221 struct drm_device
*dev
= crtc
->base
.dev
;
8222 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8223 enum intel_display_power_domain power_domain
;
8227 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8228 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8231 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8232 pipe_config
->shared_dpll
= NULL
;
8236 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8237 if (!(tmp
& PIPECONF_ENABLE
))
8240 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
8241 switch (tmp
& PIPECONF_BPC_MASK
) {
8243 pipe_config
->pipe_bpp
= 18;
8246 pipe_config
->pipe_bpp
= 24;
8248 case PIPECONF_10BPC
:
8249 pipe_config
->pipe_bpp
= 30;
8256 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
8257 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8258 pipe_config
->limited_color_range
= true;
8260 if (INTEL_INFO(dev
)->gen
< 4)
8261 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8263 intel_get_pipe_timings(crtc
, pipe_config
);
8264 intel_get_pipe_src_size(crtc
, pipe_config
);
8266 i9xx_get_pfit_config(crtc
, pipe_config
);
8268 if (INTEL_INFO(dev
)->gen
>= 4) {
8269 /* No way to read it out on pipes B and C */
8270 if (IS_CHERRYVIEW(dev
) && crtc
->pipe
!= PIPE_A
)
8271 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8273 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8274 pipe_config
->pixel_multiplier
=
8275 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8276 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8277 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8278 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8279 tmp
= I915_READ(DPLL(crtc
->pipe
));
8280 pipe_config
->pixel_multiplier
=
8281 ((tmp
& SDVO_MULTIPLIER_MASK
)
8282 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8284 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8285 * port and will be fixed up in the encoder->get_config
8287 pipe_config
->pixel_multiplier
= 1;
8289 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8290 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
8292 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8293 * on 830. Filter it out here so that we don't
8294 * report errors due to that.
8297 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8299 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8300 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8302 /* Mask out read-only status bits. */
8303 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8304 DPLL_PORTC_READY_MASK
|
8305 DPLL_PORTB_READY_MASK
);
8308 if (IS_CHERRYVIEW(dev
))
8309 chv_crtc_clock_get(crtc
, pipe_config
);
8310 else if (IS_VALLEYVIEW(dev
))
8311 vlv_crtc_clock_get(crtc
, pipe_config
);
8313 i9xx_crtc_clock_get(crtc
, pipe_config
);
8316 * Normally the dotclock is filled in by the encoder .get_config()
8317 * but in case the pipe is enabled w/o any ports we need a sane
8320 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8321 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8326 intel_display_power_put(dev_priv
, power_domain
);
8331 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8333 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8334 struct intel_encoder
*encoder
;
8337 bool has_lvds
= false;
8338 bool has_cpu_edp
= false;
8339 bool has_panel
= false;
8340 bool has_ck505
= false;
8341 bool can_ssc
= false;
8342 bool using_ssc_source
= false;
8344 /* We need to take the global config into account */
8345 for_each_intel_encoder(dev
, encoder
) {
8346 switch (encoder
->type
) {
8347 case INTEL_OUTPUT_LVDS
:
8351 case INTEL_OUTPUT_EDP
:
8353 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8361 if (HAS_PCH_IBX(dev
)) {
8362 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8363 can_ssc
= has_ck505
;
8369 /* Check if any DPLLs are using the SSC source */
8370 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8371 u32 temp
= I915_READ(PCH_DPLL(i
));
8373 if (!(temp
& DPLL_VCO_ENABLE
))
8376 if ((temp
& PLL_REF_INPUT_MASK
) ==
8377 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8378 using_ssc_source
= true;
8383 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8384 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8386 /* Ironlake: try to setup display ref clock before DPLL
8387 * enabling. This is only under driver's control after
8388 * PCH B stepping, previous chipset stepping should be
8389 * ignoring this setting.
8391 val
= I915_READ(PCH_DREF_CONTROL
);
8393 /* As we must carefully and slowly disable/enable each source in turn,
8394 * compute the final state we want first and check if we need to
8395 * make any changes at all.
8398 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8400 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8402 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8404 final
&= ~DREF_SSC_SOURCE_MASK
;
8405 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8406 final
&= ~DREF_SSC1_ENABLE
;
8409 final
|= DREF_SSC_SOURCE_ENABLE
;
8411 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8412 final
|= DREF_SSC1_ENABLE
;
8415 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8416 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8418 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8420 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8421 } else if (using_ssc_source
) {
8422 final
|= DREF_SSC_SOURCE_ENABLE
;
8423 final
|= DREF_SSC1_ENABLE
;
8429 /* Always enable nonspread source */
8430 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8433 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8435 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8438 val
&= ~DREF_SSC_SOURCE_MASK
;
8439 val
|= DREF_SSC_SOURCE_ENABLE
;
8441 /* SSC must be turned on before enabling the CPU output */
8442 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8443 DRM_DEBUG_KMS("Using SSC on panel\n");
8444 val
|= DREF_SSC1_ENABLE
;
8446 val
&= ~DREF_SSC1_ENABLE
;
8448 /* Get SSC going before enabling the outputs */
8449 I915_WRITE(PCH_DREF_CONTROL
, val
);
8450 POSTING_READ(PCH_DREF_CONTROL
);
8453 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8455 /* Enable CPU source on CPU attached eDP */
8457 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8458 DRM_DEBUG_KMS("Using SSC on eDP\n");
8459 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8461 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8463 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8465 I915_WRITE(PCH_DREF_CONTROL
, val
);
8466 POSTING_READ(PCH_DREF_CONTROL
);
8469 DRM_DEBUG_KMS("Disabling CPU source output\n");
8471 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8473 /* Turn off CPU output */
8474 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8476 I915_WRITE(PCH_DREF_CONTROL
, val
);
8477 POSTING_READ(PCH_DREF_CONTROL
);
8480 if (!using_ssc_source
) {
8481 DRM_DEBUG_KMS("Disabling SSC source\n");
8483 /* Turn off the SSC source */
8484 val
&= ~DREF_SSC_SOURCE_MASK
;
8485 val
|= DREF_SSC_SOURCE_DISABLE
;
8488 val
&= ~DREF_SSC1_ENABLE
;
8490 I915_WRITE(PCH_DREF_CONTROL
, val
);
8491 POSTING_READ(PCH_DREF_CONTROL
);
8496 BUG_ON(val
!= final
);
8499 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8503 tmp
= I915_READ(SOUTH_CHICKEN2
);
8504 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8505 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8507 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8508 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8509 DRM_ERROR("FDI mPHY reset assert timeout\n");
8511 tmp
= I915_READ(SOUTH_CHICKEN2
);
8512 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8513 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8515 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8516 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8517 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8520 /* WaMPhyProgramming:hsw */
8521 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8525 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8526 tmp
&= ~(0xFF << 24);
8527 tmp
|= (0x12 << 24);
8528 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8530 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8532 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8534 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8536 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8538 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8539 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8540 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8542 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8543 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8544 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8546 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8549 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8551 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8554 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8556 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8559 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8561 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8564 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8566 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8567 tmp
&= ~(0xFF << 16);
8568 tmp
|= (0x1C << 16);
8569 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8571 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8572 tmp
&= ~(0xFF << 16);
8573 tmp
|= (0x1C << 16);
8574 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8576 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8578 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8580 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8582 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8584 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8585 tmp
&= ~(0xF << 28);
8587 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8589 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8590 tmp
&= ~(0xF << 28);
8592 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8595 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8596 * Programming" based on the parameters passed:
8597 * - Sequence to enable CLKOUT_DP
8598 * - Sequence to enable CLKOUT_DP without spread
8599 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8601 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8604 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8607 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8609 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8612 mutex_lock(&dev_priv
->sb_lock
);
8614 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8615 tmp
&= ~SBI_SSCCTL_DISABLE
;
8616 tmp
|= SBI_SSCCTL_PATHALT
;
8617 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8622 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8623 tmp
&= ~SBI_SSCCTL_PATHALT
;
8624 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8627 lpt_reset_fdi_mphy(dev_priv
);
8628 lpt_program_fdi_mphy(dev_priv
);
8632 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8633 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8634 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8635 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8637 mutex_unlock(&dev_priv
->sb_lock
);
8640 /* Sequence to disable CLKOUT_DP */
8641 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8643 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8646 mutex_lock(&dev_priv
->sb_lock
);
8648 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8649 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8650 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8651 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8653 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8654 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8655 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8656 tmp
|= SBI_SSCCTL_PATHALT
;
8657 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8660 tmp
|= SBI_SSCCTL_DISABLE
;
8661 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8664 mutex_unlock(&dev_priv
->sb_lock
);
8667 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8669 static const uint16_t sscdivintphase
[] = {
8670 [BEND_IDX( 50)] = 0x3B23,
8671 [BEND_IDX( 45)] = 0x3B23,
8672 [BEND_IDX( 40)] = 0x3C23,
8673 [BEND_IDX( 35)] = 0x3C23,
8674 [BEND_IDX( 30)] = 0x3D23,
8675 [BEND_IDX( 25)] = 0x3D23,
8676 [BEND_IDX( 20)] = 0x3E23,
8677 [BEND_IDX( 15)] = 0x3E23,
8678 [BEND_IDX( 10)] = 0x3F23,
8679 [BEND_IDX( 5)] = 0x3F23,
8680 [BEND_IDX( 0)] = 0x0025,
8681 [BEND_IDX( -5)] = 0x0025,
8682 [BEND_IDX(-10)] = 0x0125,
8683 [BEND_IDX(-15)] = 0x0125,
8684 [BEND_IDX(-20)] = 0x0225,
8685 [BEND_IDX(-25)] = 0x0225,
8686 [BEND_IDX(-30)] = 0x0325,
8687 [BEND_IDX(-35)] = 0x0325,
8688 [BEND_IDX(-40)] = 0x0425,
8689 [BEND_IDX(-45)] = 0x0425,
8690 [BEND_IDX(-50)] = 0x0525,
8695 * steps -50 to 50 inclusive, in steps of 5
8696 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8697 * change in clock period = -(steps / 10) * 5.787 ps
8699 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8702 int idx
= BEND_IDX(steps
);
8704 if (WARN_ON(steps
% 5 != 0))
8707 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8710 mutex_lock(&dev_priv
->sb_lock
);
8712 if (steps
% 10 != 0)
8716 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8718 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8720 tmp
|= sscdivintphase
[idx
];
8721 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8723 mutex_unlock(&dev_priv
->sb_lock
);
8728 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8730 struct intel_encoder
*encoder
;
8731 bool has_vga
= false;
8733 for_each_intel_encoder(dev
, encoder
) {
8734 switch (encoder
->type
) {
8735 case INTEL_OUTPUT_ANALOG
:
8744 lpt_bend_clkout_dp(to_i915(dev
), 0);
8745 lpt_enable_clkout_dp(dev
, true, true);
8747 lpt_disable_clkout_dp(dev
);
8752 * Initialize reference clocks when the driver loads
8754 void intel_init_pch_refclk(struct drm_device
*dev
)
8756 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8757 ironlake_init_pch_refclk(dev
);
8758 else if (HAS_PCH_LPT(dev
))
8759 lpt_init_pch_refclk(dev
);
8762 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8764 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8765 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8766 int pipe
= intel_crtc
->pipe
;
8771 switch (intel_crtc
->config
->pipe_bpp
) {
8773 val
|= PIPECONF_6BPC
;
8776 val
|= PIPECONF_8BPC
;
8779 val
|= PIPECONF_10BPC
;
8782 val
|= PIPECONF_12BPC
;
8785 /* Case prevented by intel_choose_pipe_bpp_dither. */
8789 if (intel_crtc
->config
->dither
)
8790 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8792 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8793 val
|= PIPECONF_INTERLACED_ILK
;
8795 val
|= PIPECONF_PROGRESSIVE
;
8797 if (intel_crtc
->config
->limited_color_range
)
8798 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8800 I915_WRITE(PIPECONF(pipe
), val
);
8801 POSTING_READ(PIPECONF(pipe
));
8804 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8806 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8807 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8808 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8811 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8812 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8814 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8815 val
|= PIPECONF_INTERLACED_ILK
;
8817 val
|= PIPECONF_PROGRESSIVE
;
8819 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8820 POSTING_READ(PIPECONF(cpu_transcoder
));
8823 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8825 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8828 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8831 switch (intel_crtc
->config
->pipe_bpp
) {
8833 val
|= PIPEMISC_DITHER_6_BPC
;
8836 val
|= PIPEMISC_DITHER_8_BPC
;
8839 val
|= PIPEMISC_DITHER_10_BPC
;
8842 val
|= PIPEMISC_DITHER_12_BPC
;
8845 /* Case prevented by pipe_config_set_bpp. */
8849 if (intel_crtc
->config
->dither
)
8850 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8852 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8856 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8859 * Account for spread spectrum to avoid
8860 * oversubscribing the link. Max center spread
8861 * is 2.5%; use 5% for safety's sake.
8863 u32 bps
= target_clock
* bpp
* 21 / 20;
8864 return DIV_ROUND_UP(bps
, link_bw
* 8);
8867 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8869 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8872 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8873 struct intel_crtc_state
*crtc_state
,
8874 struct dpll
*reduced_clock
)
8876 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8877 struct drm_device
*dev
= crtc
->dev
;
8878 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8882 /* Enable autotuning of the PLL clock (if permissible) */
8884 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8885 if ((intel_panel_use_ssc(dev_priv
) &&
8886 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8887 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8889 } else if (crtc_state
->sdvo_tv_clock
)
8892 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8894 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8897 if (reduced_clock
) {
8898 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8900 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8908 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8909 dpll
|= DPLLB_MODE_LVDS
;
8911 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8913 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8914 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8916 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8917 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8918 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8920 if (intel_crtc_has_dp_encoder(crtc_state
))
8921 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8923 /* compute bitmask from p1 value */
8924 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8926 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8928 switch (crtc_state
->dpll
.p2
) {
8930 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8933 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8936 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8939 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8943 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8944 intel_panel_use_ssc(dev_priv
))
8945 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8947 dpll
|= PLL_REF_INPUT_DREFCLK
;
8949 dpll
|= DPLL_VCO_ENABLE
;
8951 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8952 crtc_state
->dpll_hw_state
.fp0
= fp
;
8953 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8956 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8957 struct intel_crtc_state
*crtc_state
)
8959 struct drm_device
*dev
= crtc
->base
.dev
;
8960 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8961 struct dpll reduced_clock
;
8962 bool has_reduced_clock
= false;
8963 struct intel_shared_dpll
*pll
;
8964 const struct intel_limit
*limit
;
8965 int refclk
= 120000;
8967 memset(&crtc_state
->dpll_hw_state
, 0,
8968 sizeof(crtc_state
->dpll_hw_state
));
8970 crtc
->lowfreq_avail
= false;
8972 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8973 if (!crtc_state
->has_pch_encoder
)
8976 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8977 if (intel_panel_use_ssc(dev_priv
)) {
8978 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8979 dev_priv
->vbt
.lvds_ssc_freq
);
8980 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8983 if (intel_is_dual_link_lvds(dev
)) {
8984 if (refclk
== 100000)
8985 limit
= &intel_limits_ironlake_dual_lvds_100m
;
8987 limit
= &intel_limits_ironlake_dual_lvds
;
8989 if (refclk
== 100000)
8990 limit
= &intel_limits_ironlake_single_lvds_100m
;
8992 limit
= &intel_limits_ironlake_single_lvds
;
8995 limit
= &intel_limits_ironlake_dac
;
8998 if (!crtc_state
->clock_set
&&
8999 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9000 refclk
, NULL
, &crtc_state
->dpll
)) {
9001 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9005 ironlake_compute_dpll(crtc
, crtc_state
,
9006 has_reduced_clock
? &reduced_clock
: NULL
);
9008 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
9010 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9011 pipe_name(crtc
->pipe
));
9015 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9017 crtc
->lowfreq_avail
= true;
9022 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9023 struct intel_link_m_n
*m_n
)
9025 struct drm_device
*dev
= crtc
->base
.dev
;
9026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9027 enum pipe pipe
= crtc
->pipe
;
9029 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9030 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9031 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9033 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9034 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9035 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9038 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9039 enum transcoder transcoder
,
9040 struct intel_link_m_n
*m_n
,
9041 struct intel_link_m_n
*m2_n2
)
9043 struct drm_device
*dev
= crtc
->base
.dev
;
9044 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9045 enum pipe pipe
= crtc
->pipe
;
9047 if (INTEL_INFO(dev
)->gen
>= 5) {
9048 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9049 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9050 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9052 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9053 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9054 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9055 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9056 * gen < 8) and if DRRS is supported (to make sure the
9057 * registers are not unnecessarily read).
9059 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9060 crtc
->config
->has_drrs
) {
9061 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9062 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9063 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9065 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9066 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9067 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9070 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9071 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9072 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9074 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9075 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9076 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9080 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9081 struct intel_crtc_state
*pipe_config
)
9083 if (pipe_config
->has_pch_encoder
)
9084 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9086 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9087 &pipe_config
->dp_m_n
,
9088 &pipe_config
->dp_m2_n2
);
9091 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9092 struct intel_crtc_state
*pipe_config
)
9094 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9095 &pipe_config
->fdi_m_n
, NULL
);
9098 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9099 struct intel_crtc_state
*pipe_config
)
9101 struct drm_device
*dev
= crtc
->base
.dev
;
9102 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9103 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9104 uint32_t ps_ctrl
= 0;
9108 /* find scaler attached to this pipe */
9109 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9110 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9111 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9113 pipe_config
->pch_pfit
.enabled
= true;
9114 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9115 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9120 scaler_state
->scaler_id
= id
;
9122 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9124 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9129 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9130 struct intel_initial_plane_config
*plane_config
)
9132 struct drm_device
*dev
= crtc
->base
.dev
;
9133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9134 u32 val
, base
, offset
, stride_mult
, tiling
;
9135 int pipe
= crtc
->pipe
;
9136 int fourcc
, pixel_format
;
9137 unsigned int aligned_height
;
9138 struct drm_framebuffer
*fb
;
9139 struct intel_framebuffer
*intel_fb
;
9141 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9143 DRM_DEBUG_KMS("failed to alloc fb\n");
9147 fb
= &intel_fb
->base
;
9149 val
= I915_READ(PLANE_CTL(pipe
, 0));
9150 if (!(val
& PLANE_CTL_ENABLE
))
9153 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9154 fourcc
= skl_format_to_fourcc(pixel_format
,
9155 val
& PLANE_CTL_ORDER_RGBX
,
9156 val
& PLANE_CTL_ALPHA_MASK
);
9157 fb
->pixel_format
= fourcc
;
9158 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9160 tiling
= val
& PLANE_CTL_TILED_MASK
;
9162 case PLANE_CTL_TILED_LINEAR
:
9163 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9165 case PLANE_CTL_TILED_X
:
9166 plane_config
->tiling
= I915_TILING_X
;
9167 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9169 case PLANE_CTL_TILED_Y
:
9170 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9172 case PLANE_CTL_TILED_YF
:
9173 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9176 MISSING_CASE(tiling
);
9180 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9181 plane_config
->base
= base
;
9183 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9185 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9186 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9187 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9189 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9190 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
9192 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9194 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9198 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9200 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9201 pipe_name(pipe
), fb
->width
, fb
->height
,
9202 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9203 plane_config
->size
);
9205 plane_config
->fb
= intel_fb
;
9212 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9213 struct intel_crtc_state
*pipe_config
)
9215 struct drm_device
*dev
= crtc
->base
.dev
;
9216 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9219 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9221 if (tmp
& PF_ENABLE
) {
9222 pipe_config
->pch_pfit
.enabled
= true;
9223 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9224 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9226 /* We currently do not free assignements of panel fitters on
9227 * ivb/hsw (since we don't use the higher upscaling modes which
9228 * differentiates them) so just WARN about this case for now. */
9230 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9231 PF_PIPE_SEL_IVB(crtc
->pipe
));
9237 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9238 struct intel_initial_plane_config
*plane_config
)
9240 struct drm_device
*dev
= crtc
->base
.dev
;
9241 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9242 u32 val
, base
, offset
;
9243 int pipe
= crtc
->pipe
;
9244 int fourcc
, pixel_format
;
9245 unsigned int aligned_height
;
9246 struct drm_framebuffer
*fb
;
9247 struct intel_framebuffer
*intel_fb
;
9249 val
= I915_READ(DSPCNTR(pipe
));
9250 if (!(val
& DISPLAY_PLANE_ENABLE
))
9253 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9255 DRM_DEBUG_KMS("failed to alloc fb\n");
9259 fb
= &intel_fb
->base
;
9261 if (INTEL_INFO(dev
)->gen
>= 4) {
9262 if (val
& DISPPLANE_TILED
) {
9263 plane_config
->tiling
= I915_TILING_X
;
9264 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9268 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9269 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9270 fb
->pixel_format
= fourcc
;
9271 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9273 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9274 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9275 offset
= I915_READ(DSPOFFSET(pipe
));
9277 if (plane_config
->tiling
)
9278 offset
= I915_READ(DSPTILEOFF(pipe
));
9280 offset
= I915_READ(DSPLINOFF(pipe
));
9282 plane_config
->base
= base
;
9284 val
= I915_READ(PIPESRC(pipe
));
9285 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9286 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9288 val
= I915_READ(DSPSTRIDE(pipe
));
9289 fb
->pitches
[0] = val
& 0xffffffc0;
9291 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9295 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9297 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9298 pipe_name(pipe
), fb
->width
, fb
->height
,
9299 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9300 plane_config
->size
);
9302 plane_config
->fb
= intel_fb
;
9305 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9306 struct intel_crtc_state
*pipe_config
)
9308 struct drm_device
*dev
= crtc
->base
.dev
;
9309 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9310 enum intel_display_power_domain power_domain
;
9314 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9315 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9318 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9319 pipe_config
->shared_dpll
= NULL
;
9322 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9323 if (!(tmp
& PIPECONF_ENABLE
))
9326 switch (tmp
& PIPECONF_BPC_MASK
) {
9328 pipe_config
->pipe_bpp
= 18;
9331 pipe_config
->pipe_bpp
= 24;
9333 case PIPECONF_10BPC
:
9334 pipe_config
->pipe_bpp
= 30;
9336 case PIPECONF_12BPC
:
9337 pipe_config
->pipe_bpp
= 36;
9343 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9344 pipe_config
->limited_color_range
= true;
9346 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9347 struct intel_shared_dpll
*pll
;
9348 enum intel_dpll_id pll_id
;
9350 pipe_config
->has_pch_encoder
= true;
9352 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9353 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9354 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9356 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9358 if (HAS_PCH_IBX(dev_priv
)) {
9360 * The pipe->pch transcoder and pch transcoder->pll
9363 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9365 tmp
= I915_READ(PCH_DPLL_SEL
);
9366 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9367 pll_id
= DPLL_ID_PCH_PLL_B
;
9369 pll_id
= DPLL_ID_PCH_PLL_A
;
9372 pipe_config
->shared_dpll
=
9373 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9374 pll
= pipe_config
->shared_dpll
;
9376 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9377 &pipe_config
->dpll_hw_state
));
9379 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9380 pipe_config
->pixel_multiplier
=
9381 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9382 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9384 ironlake_pch_clock_get(crtc
, pipe_config
);
9386 pipe_config
->pixel_multiplier
= 1;
9389 intel_get_pipe_timings(crtc
, pipe_config
);
9390 intel_get_pipe_src_size(crtc
, pipe_config
);
9392 ironlake_get_pfit_config(crtc
, pipe_config
);
9397 intel_display_power_put(dev_priv
, power_domain
);
9402 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9404 struct drm_device
*dev
= &dev_priv
->drm
;
9405 struct intel_crtc
*crtc
;
9407 for_each_intel_crtc(dev
, crtc
)
9408 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9409 pipe_name(crtc
->pipe
));
9411 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9412 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9413 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9414 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9415 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9416 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9417 "CPU PWM1 enabled\n");
9418 if (IS_HASWELL(dev
))
9419 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9420 "CPU PWM2 enabled\n");
9421 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9422 "PCH PWM1 enabled\n");
9423 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9424 "Utility pin enabled\n");
9425 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9428 * In theory we can still leave IRQs enabled, as long as only the HPD
9429 * interrupts remain enabled. We used to check for that, but since it's
9430 * gen-specific and since we only disable LCPLL after we fully disable
9431 * the interrupts, the check below should be enough.
9433 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9436 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9438 struct drm_device
*dev
= &dev_priv
->drm
;
9440 if (IS_HASWELL(dev
))
9441 return I915_READ(D_COMP_HSW
);
9443 return I915_READ(D_COMP_BDW
);
9446 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9448 struct drm_device
*dev
= &dev_priv
->drm
;
9450 if (IS_HASWELL(dev
)) {
9451 mutex_lock(&dev_priv
->rps
.hw_lock
);
9452 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9454 DRM_ERROR("Failed to write to D_COMP\n");
9455 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9457 I915_WRITE(D_COMP_BDW
, val
);
9458 POSTING_READ(D_COMP_BDW
);
9463 * This function implements pieces of two sequences from BSpec:
9464 * - Sequence for display software to disable LCPLL
9465 * - Sequence for display software to allow package C8+
9466 * The steps implemented here are just the steps that actually touch the LCPLL
9467 * register. Callers should take care of disabling all the display engine
9468 * functions, doing the mode unset, fixing interrupts, etc.
9470 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9471 bool switch_to_fclk
, bool allow_power_down
)
9475 assert_can_disable_lcpll(dev_priv
);
9477 val
= I915_READ(LCPLL_CTL
);
9479 if (switch_to_fclk
) {
9480 val
|= LCPLL_CD_SOURCE_FCLK
;
9481 I915_WRITE(LCPLL_CTL
, val
);
9483 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9484 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9485 DRM_ERROR("Switching to FCLK failed\n");
9487 val
= I915_READ(LCPLL_CTL
);
9490 val
|= LCPLL_PLL_DISABLE
;
9491 I915_WRITE(LCPLL_CTL
, val
);
9492 POSTING_READ(LCPLL_CTL
);
9494 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
9495 DRM_ERROR("LCPLL still locked\n");
9497 val
= hsw_read_dcomp(dev_priv
);
9498 val
|= D_COMP_COMP_DISABLE
;
9499 hsw_write_dcomp(dev_priv
, val
);
9502 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9504 DRM_ERROR("D_COMP RCOMP still in progress\n");
9506 if (allow_power_down
) {
9507 val
= I915_READ(LCPLL_CTL
);
9508 val
|= LCPLL_POWER_DOWN_ALLOW
;
9509 I915_WRITE(LCPLL_CTL
, val
);
9510 POSTING_READ(LCPLL_CTL
);
9515 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9518 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9522 val
= I915_READ(LCPLL_CTL
);
9524 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9525 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9529 * Make sure we're not on PC8 state before disabling PC8, otherwise
9530 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9532 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9534 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9535 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9536 I915_WRITE(LCPLL_CTL
, val
);
9537 POSTING_READ(LCPLL_CTL
);
9540 val
= hsw_read_dcomp(dev_priv
);
9541 val
|= D_COMP_COMP_FORCE
;
9542 val
&= ~D_COMP_COMP_DISABLE
;
9543 hsw_write_dcomp(dev_priv
, val
);
9545 val
= I915_READ(LCPLL_CTL
);
9546 val
&= ~LCPLL_PLL_DISABLE
;
9547 I915_WRITE(LCPLL_CTL
, val
);
9549 if (intel_wait_for_register(dev_priv
,
9550 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
9552 DRM_ERROR("LCPLL not locked yet\n");
9554 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9555 val
= I915_READ(LCPLL_CTL
);
9556 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9557 I915_WRITE(LCPLL_CTL
, val
);
9559 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9560 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9561 DRM_ERROR("Switching back to LCPLL failed\n");
9564 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9565 intel_update_cdclk(&dev_priv
->drm
);
9569 * Package states C8 and deeper are really deep PC states that can only be
9570 * reached when all the devices on the system allow it, so even if the graphics
9571 * device allows PC8+, it doesn't mean the system will actually get to these
9572 * states. Our driver only allows PC8+ when going into runtime PM.
9574 * The requirements for PC8+ are that all the outputs are disabled, the power
9575 * well is disabled and most interrupts are disabled, and these are also
9576 * requirements for runtime PM. When these conditions are met, we manually do
9577 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9578 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9581 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9582 * the state of some registers, so when we come back from PC8+ we need to
9583 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9584 * need to take care of the registers kept by RC6. Notice that this happens even
9585 * if we don't put the device in PCI D3 state (which is what currently happens
9586 * because of the runtime PM support).
9588 * For more, read "Display Sequences for Package C8" on the hardware
9591 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9593 struct drm_device
*dev
= &dev_priv
->drm
;
9596 DRM_DEBUG_KMS("Enabling package C8+\n");
9598 if (HAS_PCH_LPT_LP(dev
)) {
9599 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9600 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9601 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9604 lpt_disable_clkout_dp(dev
);
9605 hsw_disable_lcpll(dev_priv
, true, true);
9608 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9610 struct drm_device
*dev
= &dev_priv
->drm
;
9613 DRM_DEBUG_KMS("Disabling package C8+\n");
9615 hsw_restore_lcpll(dev_priv
);
9616 lpt_init_pch_refclk(dev
);
9618 if (HAS_PCH_LPT_LP(dev
)) {
9619 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9620 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9621 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9625 static void bxt_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9627 struct drm_device
*dev
= old_state
->dev
;
9628 struct intel_atomic_state
*old_intel_state
=
9629 to_intel_atomic_state(old_state
);
9630 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
9632 bxt_set_cdclk(to_i915(dev
), req_cdclk
);
9635 /* compute the max rate for new configuration */
9636 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9638 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9639 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9640 struct drm_crtc
*crtc
;
9641 struct drm_crtc_state
*cstate
;
9642 struct intel_crtc_state
*crtc_state
;
9643 unsigned max_pixel_rate
= 0, i
;
9646 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
9647 sizeof(intel_state
->min_pixclk
));
9649 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
9652 crtc_state
= to_intel_crtc_state(cstate
);
9653 if (!crtc_state
->base
.enable
) {
9654 intel_state
->min_pixclk
[i
] = 0;
9658 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9660 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9661 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
9662 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9664 intel_state
->min_pixclk
[i
] = pixel_rate
;
9667 for_each_pipe(dev_priv
, pipe
)
9668 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
9670 return max_pixel_rate
;
9673 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9675 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9679 if (WARN((I915_READ(LCPLL_CTL
) &
9680 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9681 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9682 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9683 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9684 "trying to change cdclk frequency with cdclk not enabled\n"))
9687 mutex_lock(&dev_priv
->rps
.hw_lock
);
9688 ret
= sandybridge_pcode_write(dev_priv
,
9689 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9690 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9692 DRM_ERROR("failed to inform pcode about cdclk change\n");
9696 val
= I915_READ(LCPLL_CTL
);
9697 val
|= LCPLL_CD_SOURCE_FCLK
;
9698 I915_WRITE(LCPLL_CTL
, val
);
9700 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9701 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9702 DRM_ERROR("Switching to FCLK failed\n");
9704 val
= I915_READ(LCPLL_CTL
);
9705 val
&= ~LCPLL_CLK_FREQ_MASK
;
9709 val
|= LCPLL_CLK_FREQ_450
;
9713 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9717 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9721 val
|= LCPLL_CLK_FREQ_675_BDW
;
9725 WARN(1, "invalid cdclk frequency\n");
9729 I915_WRITE(LCPLL_CTL
, val
);
9731 val
= I915_READ(LCPLL_CTL
);
9732 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9733 I915_WRITE(LCPLL_CTL
, val
);
9735 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9736 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9737 DRM_ERROR("Switching back to LCPLL failed\n");
9739 mutex_lock(&dev_priv
->rps
.hw_lock
);
9740 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9741 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9743 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
9745 intel_update_cdclk(dev
);
9747 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9748 "cdclk requested %d kHz but got %d kHz\n",
9749 cdclk
, dev_priv
->cdclk_freq
);
9752 static int broadwell_calc_cdclk(int max_pixclk
)
9754 if (max_pixclk
> 540000)
9756 else if (max_pixclk
> 450000)
9758 else if (max_pixclk
> 337500)
9764 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9766 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9767 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9768 int max_pixclk
= ilk_max_pixel_rate(state
);
9772 * FIXME should also account for plane ratio
9773 * once 64bpp pixel formats are supported.
9775 cdclk
= broadwell_calc_cdclk(max_pixclk
);
9777 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9778 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9779 cdclk
, dev_priv
->max_cdclk_freq
);
9783 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9784 if (!intel_state
->active_crtcs
)
9785 intel_state
->dev_cdclk
= broadwell_calc_cdclk(0);
9790 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9792 struct drm_device
*dev
= old_state
->dev
;
9793 struct intel_atomic_state
*old_intel_state
=
9794 to_intel_atomic_state(old_state
);
9795 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
9797 broadwell_set_cdclk(dev
, req_cdclk
);
9800 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9802 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9803 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9804 const int max_pixclk
= ilk_max_pixel_rate(state
);
9805 int vco
= intel_state
->cdclk_pll_vco
;
9809 * FIXME should also account for plane ratio
9810 * once 64bpp pixel formats are supported.
9812 cdclk
= skl_calc_cdclk(max_pixclk
, vco
);
9815 * FIXME move the cdclk caclulation to
9816 * compute_config() so we can fail gracegully.
9818 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9819 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9820 cdclk
, dev_priv
->max_cdclk_freq
);
9821 cdclk
= dev_priv
->max_cdclk_freq
;
9824 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9825 if (!intel_state
->active_crtcs
)
9826 intel_state
->dev_cdclk
= skl_calc_cdclk(0, vco
);
9831 static void skl_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9833 struct drm_i915_private
*dev_priv
= to_i915(old_state
->dev
);
9834 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(old_state
);
9835 unsigned int req_cdclk
= intel_state
->dev_cdclk
;
9836 unsigned int req_vco
= intel_state
->cdclk_pll_vco
;
9838 skl_set_cdclk(dev_priv
, req_cdclk
, req_vco
);
9841 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9842 struct intel_crtc_state
*crtc_state
)
9844 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
)) {
9845 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9849 crtc
->lowfreq_avail
= false;
9854 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9856 struct intel_crtc_state
*pipe_config
)
9858 enum intel_dpll_id id
;
9862 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9863 id
= DPLL_ID_SKL_DPLL0
;
9866 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9867 id
= DPLL_ID_SKL_DPLL1
;
9870 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9871 id
= DPLL_ID_SKL_DPLL2
;
9874 DRM_ERROR("Incorrect port type\n");
9878 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9881 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9883 struct intel_crtc_state
*pipe_config
)
9885 enum intel_dpll_id id
;
9888 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9889 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9891 switch (pipe_config
->ddi_pll_sel
) {
9893 id
= DPLL_ID_SKL_DPLL0
;
9896 id
= DPLL_ID_SKL_DPLL1
;
9899 id
= DPLL_ID_SKL_DPLL2
;
9902 id
= DPLL_ID_SKL_DPLL3
;
9905 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9909 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9912 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9914 struct intel_crtc_state
*pipe_config
)
9916 enum intel_dpll_id id
;
9918 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9920 switch (pipe_config
->ddi_pll_sel
) {
9921 case PORT_CLK_SEL_WRPLL1
:
9922 id
= DPLL_ID_WRPLL1
;
9924 case PORT_CLK_SEL_WRPLL2
:
9925 id
= DPLL_ID_WRPLL2
;
9927 case PORT_CLK_SEL_SPLL
:
9930 case PORT_CLK_SEL_LCPLL_810
:
9931 id
= DPLL_ID_LCPLL_810
;
9933 case PORT_CLK_SEL_LCPLL_1350
:
9934 id
= DPLL_ID_LCPLL_1350
;
9936 case PORT_CLK_SEL_LCPLL_2700
:
9937 id
= DPLL_ID_LCPLL_2700
;
9940 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9942 case PORT_CLK_SEL_NONE
:
9946 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9949 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9950 struct intel_crtc_state
*pipe_config
,
9951 unsigned long *power_domain_mask
)
9953 struct drm_device
*dev
= crtc
->base
.dev
;
9954 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9955 enum intel_display_power_domain power_domain
;
9959 * The pipe->transcoder mapping is fixed with the exception of the eDP
9960 * transcoder handled below.
9962 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9965 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9966 * consistency and less surprising code; it's in always on power).
9968 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9969 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9970 enum pipe trans_edp_pipe
;
9971 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9973 WARN(1, "unknown pipe linked to edp transcoder\n");
9974 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9975 case TRANS_DDI_EDP_INPUT_A_ON
:
9976 trans_edp_pipe
= PIPE_A
;
9978 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9979 trans_edp_pipe
= PIPE_B
;
9981 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9982 trans_edp_pipe
= PIPE_C
;
9986 if (trans_edp_pipe
== crtc
->pipe
)
9987 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9990 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9991 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9993 *power_domain_mask
|= BIT(power_domain
);
9995 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9997 return tmp
& PIPECONF_ENABLE
;
10000 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10001 struct intel_crtc_state
*pipe_config
,
10002 unsigned long *power_domain_mask
)
10004 struct drm_device
*dev
= crtc
->base
.dev
;
10005 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10006 enum intel_display_power_domain power_domain
;
10008 enum transcoder cpu_transcoder
;
10011 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10012 if (port
== PORT_A
)
10013 cpu_transcoder
= TRANSCODER_DSI_A
;
10015 cpu_transcoder
= TRANSCODER_DSI_C
;
10017 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10018 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10020 *power_domain_mask
|= BIT(power_domain
);
10023 * The PLL needs to be enabled with a valid divider
10024 * configuration, otherwise accessing DSI registers will hang
10025 * the machine. See BSpec North Display Engine
10026 * registers/MIPI[BXT]. We can break out here early, since we
10027 * need the same DSI PLL to be enabled for both DSI ports.
10029 if (!intel_dsi_pll_is_enabled(dev_priv
))
10032 /* XXX: this works for video mode only */
10033 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10034 if (!(tmp
& DPI_ENABLE
))
10037 tmp
= I915_READ(MIPI_CTRL(port
));
10038 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10041 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10045 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
10048 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10049 struct intel_crtc_state
*pipe_config
)
10051 struct drm_device
*dev
= crtc
->base
.dev
;
10052 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10053 struct intel_shared_dpll
*pll
;
10057 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10059 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10061 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
10062 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10063 else if (IS_BROXTON(dev
))
10064 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10066 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10068 pll
= pipe_config
->shared_dpll
;
10070 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10071 &pipe_config
->dpll_hw_state
));
10075 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10076 * DDI E. So just check whether this pipe is wired to DDI E and whether
10077 * the PCH transcoder is on.
10079 if (INTEL_INFO(dev
)->gen
< 9 &&
10080 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10081 pipe_config
->has_pch_encoder
= true;
10083 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10084 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10085 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10087 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10091 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10092 struct intel_crtc_state
*pipe_config
)
10094 struct drm_device
*dev
= crtc
->base
.dev
;
10095 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10096 enum intel_display_power_domain power_domain
;
10097 unsigned long power_domain_mask
;
10100 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10101 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10103 power_domain_mask
= BIT(power_domain
);
10105 pipe_config
->shared_dpll
= NULL
;
10107 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
10109 if (IS_BROXTON(dev_priv
) &&
10110 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &power_domain_mask
)) {
10118 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10119 haswell_get_ddi_port_state(crtc
, pipe_config
);
10120 intel_get_pipe_timings(crtc
, pipe_config
);
10123 intel_get_pipe_src_size(crtc
, pipe_config
);
10125 pipe_config
->gamma_mode
=
10126 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10128 if (INTEL_INFO(dev
)->gen
>= 9) {
10129 skl_init_scalers(dev
, crtc
, pipe_config
);
10132 if (INTEL_INFO(dev
)->gen
>= 9) {
10133 pipe_config
->scaler_state
.scaler_id
= -1;
10134 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10137 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10138 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10139 power_domain_mask
|= BIT(power_domain
);
10140 if (INTEL_INFO(dev
)->gen
>= 9)
10141 skylake_get_pfit_config(crtc
, pipe_config
);
10143 ironlake_get_pfit_config(crtc
, pipe_config
);
10146 if (IS_HASWELL(dev
))
10147 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10148 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10150 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10151 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10152 pipe_config
->pixel_multiplier
=
10153 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10155 pipe_config
->pixel_multiplier
= 1;
10159 for_each_power_domain(power_domain
, power_domain_mask
)
10160 intel_display_power_put(dev_priv
, power_domain
);
10165 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10166 const struct intel_plane_state
*plane_state
)
10168 struct drm_device
*dev
= crtc
->dev
;
10169 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10171 uint32_t cntl
= 0, size
= 0;
10173 if (plane_state
&& plane_state
->visible
) {
10174 unsigned int width
= plane_state
->base
.crtc_w
;
10175 unsigned int height
= plane_state
->base
.crtc_h
;
10176 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10180 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10191 cntl
|= CURSOR_ENABLE
|
10192 CURSOR_GAMMA_ENABLE
|
10193 CURSOR_FORMAT_ARGB
|
10194 CURSOR_STRIDE(stride
);
10196 size
= (height
<< 12) | width
;
10199 if (intel_crtc
->cursor_cntl
!= 0 &&
10200 (intel_crtc
->cursor_base
!= base
||
10201 intel_crtc
->cursor_size
!= size
||
10202 intel_crtc
->cursor_cntl
!= cntl
)) {
10203 /* On these chipsets we can only modify the base/size/stride
10204 * whilst the cursor is disabled.
10206 I915_WRITE(CURCNTR(PIPE_A
), 0);
10207 POSTING_READ(CURCNTR(PIPE_A
));
10208 intel_crtc
->cursor_cntl
= 0;
10211 if (intel_crtc
->cursor_base
!= base
) {
10212 I915_WRITE(CURBASE(PIPE_A
), base
);
10213 intel_crtc
->cursor_base
= base
;
10216 if (intel_crtc
->cursor_size
!= size
) {
10217 I915_WRITE(CURSIZE
, size
);
10218 intel_crtc
->cursor_size
= size
;
10221 if (intel_crtc
->cursor_cntl
!= cntl
) {
10222 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10223 POSTING_READ(CURCNTR(PIPE_A
));
10224 intel_crtc
->cursor_cntl
= cntl
;
10228 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10229 const struct intel_plane_state
*plane_state
)
10231 struct drm_device
*dev
= crtc
->dev
;
10232 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10233 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10234 int pipe
= intel_crtc
->pipe
;
10237 if (plane_state
&& plane_state
->visible
) {
10238 cntl
= MCURSOR_GAMMA_ENABLE
;
10239 switch (plane_state
->base
.crtc_w
) {
10241 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10244 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10247 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10250 MISSING_CASE(plane_state
->base
.crtc_w
);
10253 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10256 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10258 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
))
10259 cntl
|= CURSOR_ROTATE_180
;
10262 if (intel_crtc
->cursor_cntl
!= cntl
) {
10263 I915_WRITE(CURCNTR(pipe
), cntl
);
10264 POSTING_READ(CURCNTR(pipe
));
10265 intel_crtc
->cursor_cntl
= cntl
;
10268 /* and commit changes on next vblank */
10269 I915_WRITE(CURBASE(pipe
), base
);
10270 POSTING_READ(CURBASE(pipe
));
10272 intel_crtc
->cursor_base
= base
;
10275 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10276 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10277 const struct intel_plane_state
*plane_state
)
10279 struct drm_device
*dev
= crtc
->dev
;
10280 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10282 int pipe
= intel_crtc
->pipe
;
10283 u32 base
= intel_crtc
->cursor_addr
;
10287 int x
= plane_state
->base
.crtc_x
;
10288 int y
= plane_state
->base
.crtc_y
;
10291 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10294 pos
|= x
<< CURSOR_X_SHIFT
;
10297 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10300 pos
|= y
<< CURSOR_Y_SHIFT
;
10302 /* ILK+ do this automagically */
10303 if (HAS_GMCH_DISPLAY(dev
) &&
10304 plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
10305 base
+= (plane_state
->base
.crtc_h
*
10306 plane_state
->base
.crtc_w
- 1) * 4;
10310 I915_WRITE(CURPOS(pipe
), pos
);
10312 if (IS_845G(dev
) || IS_I865G(dev
))
10313 i845_update_cursor(crtc
, base
, plane_state
);
10315 i9xx_update_cursor(crtc
, base
, plane_state
);
10318 static bool cursor_size_ok(struct drm_device
*dev
,
10319 uint32_t width
, uint32_t height
)
10321 if (width
== 0 || height
== 0)
10325 * 845g/865g are special in that they are only limited by
10326 * the width of their cursors, the height is arbitrary up to
10327 * the precision of the register. Everything else requires
10328 * square cursors, limited to a few power-of-two sizes.
10330 if (IS_845G(dev
) || IS_I865G(dev
)) {
10331 if ((width
& 63) != 0)
10334 if (width
> (IS_845G(dev
) ? 64 : 512))
10340 switch (width
| height
) {
10355 /* VESA 640x480x72Hz mode to set on the pipe */
10356 static struct drm_display_mode load_detect_mode
= {
10357 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10358 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10361 struct drm_framebuffer
*
10362 __intel_framebuffer_create(struct drm_device
*dev
,
10363 struct drm_mode_fb_cmd2
*mode_cmd
,
10364 struct drm_i915_gem_object
*obj
)
10366 struct intel_framebuffer
*intel_fb
;
10369 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10371 return ERR_PTR(-ENOMEM
);
10373 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10377 return &intel_fb
->base
;
10381 return ERR_PTR(ret
);
10384 static struct drm_framebuffer
*
10385 intel_framebuffer_create(struct drm_device
*dev
,
10386 struct drm_mode_fb_cmd2
*mode_cmd
,
10387 struct drm_i915_gem_object
*obj
)
10389 struct drm_framebuffer
*fb
;
10392 ret
= i915_mutex_lock_interruptible(dev
);
10394 return ERR_PTR(ret
);
10395 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10396 mutex_unlock(&dev
->struct_mutex
);
10402 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10404 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10405 return ALIGN(pitch
, 64);
10409 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10411 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10412 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10415 static struct drm_framebuffer
*
10416 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10417 struct drm_display_mode
*mode
,
10418 int depth
, int bpp
)
10420 struct drm_framebuffer
*fb
;
10421 struct drm_i915_gem_object
*obj
;
10422 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10424 obj
= i915_gem_object_create(dev
,
10425 intel_framebuffer_size_for_mode(mode
, bpp
));
10427 return ERR_CAST(obj
);
10429 mode_cmd
.width
= mode
->hdisplay
;
10430 mode_cmd
.height
= mode
->vdisplay
;
10431 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10433 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10435 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10437 drm_gem_object_unreference_unlocked(&obj
->base
);
10442 static struct drm_framebuffer
*
10443 mode_fits_in_fbdev(struct drm_device
*dev
,
10444 struct drm_display_mode
*mode
)
10446 #ifdef CONFIG_DRM_FBDEV_EMULATION
10447 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10448 struct drm_i915_gem_object
*obj
;
10449 struct drm_framebuffer
*fb
;
10451 if (!dev_priv
->fbdev
)
10454 if (!dev_priv
->fbdev
->fb
)
10457 obj
= dev_priv
->fbdev
->fb
->obj
;
10460 fb
= &dev_priv
->fbdev
->fb
->base
;
10461 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10462 fb
->bits_per_pixel
))
10465 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10468 drm_framebuffer_reference(fb
);
10475 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10476 struct drm_crtc
*crtc
,
10477 struct drm_display_mode
*mode
,
10478 struct drm_framebuffer
*fb
,
10481 struct drm_plane_state
*plane_state
;
10482 int hdisplay
, vdisplay
;
10485 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10486 if (IS_ERR(plane_state
))
10487 return PTR_ERR(plane_state
);
10490 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10492 hdisplay
= vdisplay
= 0;
10494 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10497 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10498 plane_state
->crtc_x
= 0;
10499 plane_state
->crtc_y
= 0;
10500 plane_state
->crtc_w
= hdisplay
;
10501 plane_state
->crtc_h
= vdisplay
;
10502 plane_state
->src_x
= x
<< 16;
10503 plane_state
->src_y
= y
<< 16;
10504 plane_state
->src_w
= hdisplay
<< 16;
10505 plane_state
->src_h
= vdisplay
<< 16;
10510 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10511 struct drm_display_mode
*mode
,
10512 struct intel_load_detect_pipe
*old
,
10513 struct drm_modeset_acquire_ctx
*ctx
)
10515 struct intel_crtc
*intel_crtc
;
10516 struct intel_encoder
*intel_encoder
=
10517 intel_attached_encoder(connector
);
10518 struct drm_crtc
*possible_crtc
;
10519 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10520 struct drm_crtc
*crtc
= NULL
;
10521 struct drm_device
*dev
= encoder
->dev
;
10522 struct drm_framebuffer
*fb
;
10523 struct drm_mode_config
*config
= &dev
->mode_config
;
10524 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10525 struct drm_connector_state
*connector_state
;
10526 struct intel_crtc_state
*crtc_state
;
10529 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10530 connector
->base
.id
, connector
->name
,
10531 encoder
->base
.id
, encoder
->name
);
10533 old
->restore_state
= NULL
;
10536 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10541 * Algorithm gets a little messy:
10543 * - if the connector already has an assigned crtc, use it (but make
10544 * sure it's on first)
10546 * - try to find the first unused crtc that can drive this connector,
10547 * and use that if we find one
10550 /* See if we already have a CRTC for this connector */
10551 if (connector
->state
->crtc
) {
10552 crtc
= connector
->state
->crtc
;
10554 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10558 /* Make sure the crtc and connector are running */
10562 /* Find an unused one (if possible) */
10563 for_each_crtc(dev
, possible_crtc
) {
10565 if (!(encoder
->possible_crtcs
& (1 << i
)))
10568 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10572 if (possible_crtc
->state
->enable
) {
10573 drm_modeset_unlock(&possible_crtc
->mutex
);
10577 crtc
= possible_crtc
;
10582 * If we didn't find an unused CRTC, don't use any.
10585 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10590 intel_crtc
= to_intel_crtc(crtc
);
10592 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10596 state
= drm_atomic_state_alloc(dev
);
10597 restore_state
= drm_atomic_state_alloc(dev
);
10598 if (!state
|| !restore_state
) {
10603 state
->acquire_ctx
= ctx
;
10604 restore_state
->acquire_ctx
= ctx
;
10606 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10607 if (IS_ERR(connector_state
)) {
10608 ret
= PTR_ERR(connector_state
);
10612 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10616 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10617 if (IS_ERR(crtc_state
)) {
10618 ret
= PTR_ERR(crtc_state
);
10622 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10625 mode
= &load_detect_mode
;
10627 /* We need a framebuffer large enough to accommodate all accesses
10628 * that the plane may generate whilst we perform load detection.
10629 * We can not rely on the fbcon either being present (we get called
10630 * during its initialisation to detect all boot displays, or it may
10631 * not even exist) or that it is large enough to satisfy the
10634 fb
= mode_fits_in_fbdev(dev
, mode
);
10636 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10637 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10639 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10641 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10645 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10649 drm_framebuffer_unreference(fb
);
10651 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10655 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10657 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10659 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10661 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10665 ret
= drm_atomic_commit(state
);
10667 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10671 old
->restore_state
= restore_state
;
10673 /* let the connector get through one full cycle before testing */
10674 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10678 drm_atomic_state_free(state
);
10679 drm_atomic_state_free(restore_state
);
10680 restore_state
= state
= NULL
;
10682 if (ret
== -EDEADLK
) {
10683 drm_modeset_backoff(ctx
);
10690 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10691 struct intel_load_detect_pipe
*old
,
10692 struct drm_modeset_acquire_ctx
*ctx
)
10694 struct intel_encoder
*intel_encoder
=
10695 intel_attached_encoder(connector
);
10696 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10697 struct drm_atomic_state
*state
= old
->restore_state
;
10700 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10701 connector
->base
.id
, connector
->name
,
10702 encoder
->base
.id
, encoder
->name
);
10707 ret
= drm_atomic_commit(state
);
10709 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10710 drm_atomic_state_free(state
);
10714 static int i9xx_pll_refclk(struct drm_device
*dev
,
10715 const struct intel_crtc_state
*pipe_config
)
10717 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10718 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10720 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10721 return dev_priv
->vbt
.lvds_ssc_freq
;
10722 else if (HAS_PCH_SPLIT(dev
))
10724 else if (!IS_GEN2(dev
))
10730 /* Returns the clock of the currently programmed mode of the given pipe. */
10731 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10732 struct intel_crtc_state
*pipe_config
)
10734 struct drm_device
*dev
= crtc
->base
.dev
;
10735 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10736 int pipe
= pipe_config
->cpu_transcoder
;
10737 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10741 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10743 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10744 fp
= pipe_config
->dpll_hw_state
.fp0
;
10746 fp
= pipe_config
->dpll_hw_state
.fp1
;
10748 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10749 if (IS_PINEVIEW(dev
)) {
10750 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10751 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10753 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10754 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10757 if (!IS_GEN2(dev
)) {
10758 if (IS_PINEVIEW(dev
))
10759 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10760 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10762 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10763 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10765 switch (dpll
& DPLL_MODE_MASK
) {
10766 case DPLLB_MODE_DAC_SERIAL
:
10767 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10770 case DPLLB_MODE_LVDS
:
10771 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10775 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10776 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10780 if (IS_PINEVIEW(dev
))
10781 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10783 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10785 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10786 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10789 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10790 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10792 if (lvds
& LVDS_CLKB_POWER_UP
)
10797 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10800 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10801 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10803 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10809 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10813 * This value includes pixel_multiplier. We will use
10814 * port_clock to compute adjusted_mode.crtc_clock in the
10815 * encoder's get_config() function.
10817 pipe_config
->port_clock
= port_clock
;
10820 int intel_dotclock_calculate(int link_freq
,
10821 const struct intel_link_m_n
*m_n
)
10824 * The calculation for the data clock is:
10825 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10826 * But we want to avoid losing precison if possible, so:
10827 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10829 * and the link clock is simpler:
10830 * link_clock = (m * link_clock) / n
10836 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10839 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10840 struct intel_crtc_state
*pipe_config
)
10842 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10844 /* read out port_clock from the DPLL */
10845 i9xx_crtc_clock_get(crtc
, pipe_config
);
10848 * In case there is an active pipe without active ports,
10849 * we may need some idea for the dotclock anyway.
10850 * Calculate one based on the FDI configuration.
10852 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10853 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10854 &pipe_config
->fdi_m_n
);
10857 /** Returns the currently programmed mode of the given pipe. */
10858 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10859 struct drm_crtc
*crtc
)
10861 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10863 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10864 struct drm_display_mode
*mode
;
10865 struct intel_crtc_state
*pipe_config
;
10866 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10867 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10868 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10869 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10870 enum pipe pipe
= intel_crtc
->pipe
;
10872 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10876 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10877 if (!pipe_config
) {
10883 * Construct a pipe_config sufficient for getting the clock info
10884 * back out of crtc_clock_get.
10886 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10887 * to use a real value here instead.
10889 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10890 pipe_config
->pixel_multiplier
= 1;
10891 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10892 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10893 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10894 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10896 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10897 mode
->hdisplay
= (htot
& 0xffff) + 1;
10898 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10899 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10900 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10901 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10902 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10903 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10904 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10906 drm_mode_set_name(mode
);
10908 kfree(pipe_config
);
10913 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10916 struct drm_device
*dev
= crtc
->dev
;
10917 struct intel_flip_work
*work
;
10919 spin_lock_irq(&dev
->event_lock
);
10920 work
= intel_crtc
->flip_work
;
10921 intel_crtc
->flip_work
= NULL
;
10922 spin_unlock_irq(&dev
->event_lock
);
10925 cancel_work_sync(&work
->mmio_work
);
10926 cancel_work_sync(&work
->unpin_work
);
10930 drm_crtc_cleanup(crtc
);
10935 static void intel_unpin_work_fn(struct work_struct
*__work
)
10937 struct intel_flip_work
*work
=
10938 container_of(__work
, struct intel_flip_work
, unpin_work
);
10939 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10940 struct drm_device
*dev
= crtc
->base
.dev
;
10941 struct drm_plane
*primary
= crtc
->base
.primary
;
10943 if (is_mmio_work(work
))
10944 flush_work(&work
->mmio_work
);
10946 mutex_lock(&dev
->struct_mutex
);
10947 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
10948 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10950 if (work
->flip_queued_req
)
10951 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10952 mutex_unlock(&dev
->struct_mutex
);
10954 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10955 intel_fbc_post_update(crtc
);
10956 drm_framebuffer_unreference(work
->old_fb
);
10958 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10959 atomic_dec(&crtc
->unpin_work_count
);
10964 /* Is 'a' after or equal to 'b'? */
10965 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10967 return !((a
- b
) & 0x80000000);
10970 static bool __pageflip_finished_cs(struct intel_crtc
*crtc
,
10971 struct intel_flip_work
*work
)
10973 struct drm_device
*dev
= crtc
->base
.dev
;
10974 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10975 unsigned reset_counter
;
10977 reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
10978 if (crtc
->reset_counter
!= reset_counter
)
10982 * The relevant registers doen't exist on pre-ctg.
10983 * As the flip done interrupt doesn't trigger for mmio
10984 * flips on gmch platforms, a flip count check isn't
10985 * really needed there. But since ctg has the registers,
10986 * include it in the check anyway.
10988 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10992 * BDW signals flip done immediately if the plane
10993 * is disabled, even if the plane enable is already
10994 * armed to occur at the next vblank :(
10998 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10999 * used the same base address. In that case the mmio flip might
11000 * have completed, but the CS hasn't even executed the flip yet.
11002 * A flip count check isn't enough as the CS might have updated
11003 * the base address just after start of vblank, but before we
11004 * managed to process the interrupt. This means we'd complete the
11005 * CS flip too soon.
11007 * Combining both checks should get us a good enough result. It may
11008 * still happen that the CS flip has been executed, but has not
11009 * yet actually completed. But in case the base address is the same
11010 * anyway, we don't really care.
11012 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11013 crtc
->flip_work
->gtt_offset
&&
11014 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
11015 crtc
->flip_work
->flip_count
);
11019 __pageflip_finished_mmio(struct intel_crtc
*crtc
,
11020 struct intel_flip_work
*work
)
11023 * MMIO work completes when vblank is different from
11024 * flip_queued_vblank.
11026 * Reset counter value doesn't matter, this is handled by
11027 * i915_wait_request finishing early, so no need to handle
11030 return intel_crtc_get_vblank_counter(crtc
) != work
->flip_queued_vblank
;
11034 static bool pageflip_finished(struct intel_crtc
*crtc
,
11035 struct intel_flip_work
*work
)
11037 if (!atomic_read(&work
->pending
))
11042 if (is_mmio_work(work
))
11043 return __pageflip_finished_mmio(crtc
, work
);
11045 return __pageflip_finished_cs(crtc
, work
);
11048 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
)
11050 struct drm_device
*dev
= &dev_priv
->drm
;
11051 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11053 struct intel_flip_work
*work
;
11054 unsigned long flags
;
11056 /* Ignore early vblank irqs */
11061 * This is called both by irq handlers and the reset code (to complete
11062 * lost pageflips) so needs the full irqsave spinlocks.
11064 spin_lock_irqsave(&dev
->event_lock
, flags
);
11065 work
= intel_crtc
->flip_work
;
11067 if (work
!= NULL
&&
11068 !is_mmio_work(work
) &&
11069 pageflip_finished(intel_crtc
, work
))
11070 page_flip_completed(intel_crtc
);
11072 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11075 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
)
11077 struct drm_device
*dev
= &dev_priv
->drm
;
11078 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11079 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11080 struct intel_flip_work
*work
;
11081 unsigned long flags
;
11083 /* Ignore early vblank irqs */
11088 * This is called both by irq handlers and the reset code (to complete
11089 * lost pageflips) so needs the full irqsave spinlocks.
11091 spin_lock_irqsave(&dev
->event_lock
, flags
);
11092 work
= intel_crtc
->flip_work
;
11094 if (work
!= NULL
&&
11095 is_mmio_work(work
) &&
11096 pageflip_finished(intel_crtc
, work
))
11097 page_flip_completed(intel_crtc
);
11099 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11102 static inline void intel_mark_page_flip_active(struct intel_crtc
*crtc
,
11103 struct intel_flip_work
*work
)
11105 work
->flip_queued_vblank
= intel_crtc_get_vblank_counter(crtc
);
11107 /* Ensure that the work item is consistent when activating it ... */
11108 smp_mb__before_atomic();
11109 atomic_set(&work
->pending
, 1);
11112 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11113 struct drm_crtc
*crtc
,
11114 struct drm_framebuffer
*fb
,
11115 struct drm_i915_gem_object
*obj
,
11116 struct drm_i915_gem_request
*req
,
11119 struct intel_engine_cs
*engine
= req
->engine
;
11120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11124 ret
= intel_ring_begin(req
, 6);
11128 /* Can't queue multiple flips, so wait for the previous
11129 * one to finish before executing the next.
11131 if (intel_crtc
->plane
)
11132 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11134 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11135 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11136 intel_ring_emit(engine
, MI_NOOP
);
11137 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11139 intel_ring_emit(engine
, fb
->pitches
[0]);
11140 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11141 intel_ring_emit(engine
, 0); /* aux display base address, unused */
11146 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11147 struct drm_crtc
*crtc
,
11148 struct drm_framebuffer
*fb
,
11149 struct drm_i915_gem_object
*obj
,
11150 struct drm_i915_gem_request
*req
,
11153 struct intel_engine_cs
*engine
= req
->engine
;
11154 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11158 ret
= intel_ring_begin(req
, 6);
11162 if (intel_crtc
->plane
)
11163 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11165 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11166 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11167 intel_ring_emit(engine
, MI_NOOP
);
11168 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
|
11169 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11170 intel_ring_emit(engine
, fb
->pitches
[0]);
11171 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11172 intel_ring_emit(engine
, MI_NOOP
);
11177 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11178 struct drm_crtc
*crtc
,
11179 struct drm_framebuffer
*fb
,
11180 struct drm_i915_gem_object
*obj
,
11181 struct drm_i915_gem_request
*req
,
11184 struct intel_engine_cs
*engine
= req
->engine
;
11185 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11187 uint32_t pf
, pipesrc
;
11190 ret
= intel_ring_begin(req
, 4);
11194 /* i965+ uses the linear or tiled offsets from the
11195 * Display Registers (which do not change across a page-flip)
11196 * so we need only reprogram the base address.
11198 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11199 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11200 intel_ring_emit(engine
, fb
->pitches
[0]);
11201 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
|
11204 /* XXX Enabling the panel-fitter across page-flip is so far
11205 * untested on non-native modes, so ignore it for now.
11206 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11209 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11210 intel_ring_emit(engine
, pf
| pipesrc
);
11215 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11216 struct drm_crtc
*crtc
,
11217 struct drm_framebuffer
*fb
,
11218 struct drm_i915_gem_object
*obj
,
11219 struct drm_i915_gem_request
*req
,
11222 struct intel_engine_cs
*engine
= req
->engine
;
11223 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11225 uint32_t pf
, pipesrc
;
11228 ret
= intel_ring_begin(req
, 4);
11232 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11233 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11234 intel_ring_emit(engine
, fb
->pitches
[0] | obj
->tiling_mode
);
11235 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11237 /* Contrary to the suggestions in the documentation,
11238 * "Enable Panel Fitter" does not seem to be required when page
11239 * flipping with a non-native mode, and worse causes a normal
11241 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11244 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11245 intel_ring_emit(engine
, pf
| pipesrc
);
11250 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11251 struct drm_crtc
*crtc
,
11252 struct drm_framebuffer
*fb
,
11253 struct drm_i915_gem_object
*obj
,
11254 struct drm_i915_gem_request
*req
,
11257 struct intel_engine_cs
*engine
= req
->engine
;
11258 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11259 uint32_t plane_bit
= 0;
11262 switch (intel_crtc
->plane
) {
11264 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11267 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11270 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11273 WARN_ONCE(1, "unknown plane in flip command\n");
11278 if (engine
->id
== RCS
) {
11281 * On Gen 8, SRM is now taking an extra dword to accommodate
11282 * 48bits addresses, and we need a NOOP for the batch size to
11290 * BSpec MI_DISPLAY_FLIP for IVB:
11291 * "The full packet must be contained within the same cache line."
11293 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11294 * cacheline, if we ever start emitting more commands before
11295 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11296 * then do the cacheline alignment, and finally emit the
11299 ret
= intel_ring_cacheline_align(req
);
11303 ret
= intel_ring_begin(req
, len
);
11307 /* Unmask the flip-done completion message. Note that the bspec says that
11308 * we should do this for both the BCS and RCS, and that we must not unmask
11309 * more than one flip event at any time (or ensure that one flip message
11310 * can be sent by waiting for flip-done prior to queueing new flips).
11311 * Experimentation says that BCS works despite DERRMR masking all
11312 * flip-done completion events and that unmasking all planes at once
11313 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11314 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11316 if (engine
->id
== RCS
) {
11317 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
11318 intel_ring_emit_reg(engine
, DERRMR
);
11319 intel_ring_emit(engine
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11320 DERRMR_PIPEB_PRI_FLIP_DONE
|
11321 DERRMR_PIPEC_PRI_FLIP_DONE
));
11323 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM_GEN8
|
11324 MI_SRM_LRM_GLOBAL_GTT
);
11326 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM
|
11327 MI_SRM_LRM_GLOBAL_GTT
);
11328 intel_ring_emit_reg(engine
, DERRMR
);
11329 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
+ 256);
11330 if (IS_GEN8(dev
)) {
11331 intel_ring_emit(engine
, 0);
11332 intel_ring_emit(engine
, MI_NOOP
);
11336 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11337 intel_ring_emit(engine
, (fb
->pitches
[0] | obj
->tiling_mode
));
11338 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11339 intel_ring_emit(engine
, (MI_NOOP
));
11344 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11345 struct drm_i915_gem_object
*obj
)
11347 struct reservation_object
*resv
;
11350 * This is not being used for older platforms, because
11351 * non-availability of flip done interrupt forces us to use
11352 * CS flips. Older platforms derive flip done using some clever
11353 * tricks involving the flip_pending status bits and vblank irqs.
11354 * So using MMIO flips there would disrupt this mechanism.
11357 if (engine
== NULL
)
11360 if (INTEL_GEN(engine
->i915
) < 5)
11363 if (i915
.use_mmio_flip
< 0)
11365 else if (i915
.use_mmio_flip
> 0)
11367 else if (i915
.enable_execlists
)
11370 resv
= i915_gem_object_get_dmabuf_resv(obj
);
11371 if (resv
&& !reservation_object_test_signaled_rcu(resv
, false))
11374 return engine
!= i915_gem_request_get_engine(obj
->last_write_req
);
11377 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11378 unsigned int rotation
,
11379 struct intel_flip_work
*work
)
11381 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11382 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11383 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11384 const enum pipe pipe
= intel_crtc
->pipe
;
11385 u32 ctl
, stride
, tile_height
;
11387 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11388 ctl
&= ~PLANE_CTL_TILED_MASK
;
11389 switch (fb
->modifier
[0]) {
11390 case DRM_FORMAT_MOD_NONE
:
11392 case I915_FORMAT_MOD_X_TILED
:
11393 ctl
|= PLANE_CTL_TILED_X
;
11395 case I915_FORMAT_MOD_Y_TILED
:
11396 ctl
|= PLANE_CTL_TILED_Y
;
11398 case I915_FORMAT_MOD_Yf_TILED
:
11399 ctl
|= PLANE_CTL_TILED_YF
;
11402 MISSING_CASE(fb
->modifier
[0]);
11406 * The stride is either expressed as a multiple of 64 bytes chunks for
11407 * linear buffers or in number of tiles for tiled buffers.
11409 if (intel_rotation_90_or_270(rotation
)) {
11410 /* stride = Surface height in tiles */
11411 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], 0);
11412 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
11414 stride
= fb
->pitches
[0] /
11415 intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
11420 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11421 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11423 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11424 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11426 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11427 POSTING_READ(PLANE_SURF(pipe
, 0));
11430 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11431 struct intel_flip_work
*work
)
11433 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11434 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11435 struct intel_framebuffer
*intel_fb
=
11436 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11437 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11438 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
11441 dspcntr
= I915_READ(reg
);
11443 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11444 dspcntr
|= DISPPLANE_TILED
;
11446 dspcntr
&= ~DISPPLANE_TILED
;
11448 I915_WRITE(reg
, dspcntr
);
11450 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11451 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11454 static void intel_mmio_flip_work_func(struct work_struct
*w
)
11456 struct intel_flip_work
*work
=
11457 container_of(w
, struct intel_flip_work
, mmio_work
);
11458 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11459 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11460 struct intel_framebuffer
*intel_fb
=
11461 to_intel_framebuffer(crtc
->base
.primary
->fb
);
11462 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11463 struct reservation_object
*resv
;
11465 if (work
->flip_queued_req
)
11466 WARN_ON(__i915_wait_request(work
->flip_queued_req
,
11468 &dev_priv
->rps
.mmioflips
));
11470 /* For framebuffer backed by dmabuf, wait for fence */
11471 resv
= i915_gem_object_get_dmabuf_resv(obj
);
11473 WARN_ON(reservation_object_wait_timeout_rcu(resv
, false, false,
11474 MAX_SCHEDULE_TIMEOUT
) < 0);
11476 intel_pipe_update_start(crtc
);
11478 if (INTEL_GEN(dev_priv
) >= 9)
11479 skl_do_mmio_flip(crtc
, work
->rotation
, work
);
11481 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11482 ilk_do_mmio_flip(crtc
, work
);
11484 intel_pipe_update_end(crtc
, work
);
11487 static int intel_default_queue_flip(struct drm_device
*dev
,
11488 struct drm_crtc
*crtc
,
11489 struct drm_framebuffer
*fb
,
11490 struct drm_i915_gem_object
*obj
,
11491 struct drm_i915_gem_request
*req
,
11497 static bool __pageflip_stall_check_cs(struct drm_i915_private
*dev_priv
,
11498 struct intel_crtc
*intel_crtc
,
11499 struct intel_flip_work
*work
)
11503 if (!atomic_read(&work
->pending
))
11508 vblank
= intel_crtc_get_vblank_counter(intel_crtc
);
11509 if (work
->flip_ready_vblank
== 0) {
11510 if (work
->flip_queued_req
&&
11511 !i915_gem_request_completed(work
->flip_queued_req
))
11514 work
->flip_ready_vblank
= vblank
;
11517 if (vblank
- work
->flip_ready_vblank
< 3)
11520 /* Potential stall - if we see that the flip has happened,
11521 * assume a missed interrupt. */
11522 if (INTEL_GEN(dev_priv
) >= 4)
11523 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11525 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11527 /* There is a potential issue here with a false positive after a flip
11528 * to the same address. We could address this by checking for a
11529 * non-incrementing frame counter.
11531 return addr
== work
->gtt_offset
;
11534 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
11536 struct drm_device
*dev
= &dev_priv
->drm
;
11537 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11538 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11539 struct intel_flip_work
*work
;
11541 WARN_ON(!in_interrupt());
11546 spin_lock(&dev
->event_lock
);
11547 work
= intel_crtc
->flip_work
;
11549 if (work
!= NULL
&& !is_mmio_work(work
) &&
11550 __pageflip_stall_check_cs(dev_priv
, intel_crtc
, work
)) {
11552 "Kicking stuck page flip: queued at %d, now %d\n",
11553 work
->flip_queued_vblank
, intel_crtc_get_vblank_counter(intel_crtc
));
11554 page_flip_completed(intel_crtc
);
11558 if (work
!= NULL
&& !is_mmio_work(work
) &&
11559 intel_crtc_get_vblank_counter(intel_crtc
) - work
->flip_queued_vblank
> 1)
11560 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
11561 spin_unlock(&dev
->event_lock
);
11564 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11565 struct drm_framebuffer
*fb
,
11566 struct drm_pending_vblank_event
*event
,
11567 uint32_t page_flip_flags
)
11569 struct drm_device
*dev
= crtc
->dev
;
11570 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11571 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11572 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11574 struct drm_plane
*primary
= crtc
->primary
;
11575 enum pipe pipe
= intel_crtc
->pipe
;
11576 struct intel_flip_work
*work
;
11577 struct intel_engine_cs
*engine
;
11579 struct drm_i915_gem_request
*request
= NULL
;
11583 * drm_mode_page_flip_ioctl() should already catch this, but double
11584 * check to be safe. In the future we may enable pageflipping from
11585 * a disabled primary plane.
11587 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11590 /* Can't change pixel format via MI display flips. */
11591 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11595 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11596 * Note that pitch changes could also affect these register.
11598 if (INTEL_INFO(dev
)->gen
> 3 &&
11599 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11600 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11603 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11606 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11610 work
->event
= event
;
11612 work
->old_fb
= old_fb
;
11613 INIT_WORK(&work
->unpin_work
, intel_unpin_work_fn
);
11615 ret
= drm_crtc_vblank_get(crtc
);
11619 /* We borrow the event spin lock for protecting flip_work */
11620 spin_lock_irq(&dev
->event_lock
);
11621 if (intel_crtc
->flip_work
) {
11622 /* Before declaring the flip queue wedged, check if
11623 * the hardware completed the operation behind our backs.
11625 if (pageflip_finished(intel_crtc
, intel_crtc
->flip_work
)) {
11626 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11627 page_flip_completed(intel_crtc
);
11629 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11630 spin_unlock_irq(&dev
->event_lock
);
11632 drm_crtc_vblank_put(crtc
);
11637 intel_crtc
->flip_work
= work
;
11638 spin_unlock_irq(&dev
->event_lock
);
11640 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11641 flush_workqueue(dev_priv
->wq
);
11643 /* Reference the objects for the scheduled work. */
11644 drm_framebuffer_reference(work
->old_fb
);
11645 drm_gem_object_reference(&obj
->base
);
11647 crtc
->primary
->fb
= fb
;
11648 update_state_fb(crtc
->primary
);
11650 intel_fbc_pre_update(intel_crtc
, intel_crtc
->config
,
11651 to_intel_plane_state(primary
->state
));
11653 work
->pending_flip_obj
= obj
;
11655 ret
= i915_mutex_lock_interruptible(dev
);
11659 intel_crtc
->reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11660 if (__i915_reset_in_progress_or_wedged(intel_crtc
->reset_counter
)) {
11665 atomic_inc(&intel_crtc
->unpin_work_count
);
11667 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11668 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11670 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
11671 engine
= &dev_priv
->engine
[BCS
];
11672 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11673 /* vlv: DISPLAY_FLIP fails to change tiling */
11675 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11676 engine
= &dev_priv
->engine
[BCS
];
11677 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11678 engine
= i915_gem_request_get_engine(obj
->last_write_req
);
11679 if (engine
== NULL
|| engine
->id
!= RCS
)
11680 engine
= &dev_priv
->engine
[BCS
];
11682 engine
= &dev_priv
->engine
[RCS
];
11685 mmio_flip
= use_mmio_flip(engine
, obj
);
11687 /* When using CS flips, we want to emit semaphores between rings.
11688 * However, when using mmio flips we will create a task to do the
11689 * synchronisation, so all we want here is to pin the framebuffer
11690 * into the display plane and skip any waits.
11693 ret
= i915_gem_object_sync(obj
, engine
, &request
);
11694 if (!ret
&& !request
) {
11695 request
= i915_gem_request_alloc(engine
, NULL
);
11696 ret
= PTR_ERR_OR_ZERO(request
);
11700 goto cleanup_pending
;
11703 ret
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
11705 goto cleanup_pending
;
11707 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11709 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11710 work
->rotation
= crtc
->primary
->state
->rotation
;
11713 INIT_WORK(&work
->mmio_work
, intel_mmio_flip_work_func
);
11715 i915_gem_request_assign(&work
->flip_queued_req
,
11716 obj
->last_write_req
);
11718 schedule_work(&work
->mmio_work
);
11720 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11721 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11724 goto cleanup_unpin
;
11726 intel_mark_page_flip_active(intel_crtc
, work
);
11728 i915_add_request_no_flush(request
);
11731 i915_gem_track_fb(intel_fb_obj(old_fb
), obj
,
11732 to_intel_plane(primary
)->frontbuffer_bit
);
11733 mutex_unlock(&dev
->struct_mutex
);
11735 intel_frontbuffer_flip_prepare(dev
,
11736 to_intel_plane(primary
)->frontbuffer_bit
);
11738 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11743 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
11745 if (!IS_ERR_OR_NULL(request
))
11746 i915_add_request_no_flush(request
);
11747 atomic_dec(&intel_crtc
->unpin_work_count
);
11748 mutex_unlock(&dev
->struct_mutex
);
11750 crtc
->primary
->fb
= old_fb
;
11751 update_state_fb(crtc
->primary
);
11753 drm_gem_object_unreference_unlocked(&obj
->base
);
11754 drm_framebuffer_unreference(work
->old_fb
);
11756 spin_lock_irq(&dev
->event_lock
);
11757 intel_crtc
->flip_work
= NULL
;
11758 spin_unlock_irq(&dev
->event_lock
);
11760 drm_crtc_vblank_put(crtc
);
11765 struct drm_atomic_state
*state
;
11766 struct drm_plane_state
*plane_state
;
11769 state
= drm_atomic_state_alloc(dev
);
11772 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11775 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11776 ret
= PTR_ERR_OR_ZERO(plane_state
);
11778 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11780 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11782 ret
= drm_atomic_commit(state
);
11785 if (ret
== -EDEADLK
) {
11786 drm_modeset_backoff(state
->acquire_ctx
);
11787 drm_atomic_state_clear(state
);
11792 drm_atomic_state_free(state
);
11794 if (ret
== 0 && event
) {
11795 spin_lock_irq(&dev
->event_lock
);
11796 drm_crtc_send_vblank_event(crtc
, event
);
11797 spin_unlock_irq(&dev
->event_lock
);
11805 * intel_wm_need_update - Check whether watermarks need updating
11806 * @plane: drm plane
11807 * @state: new plane state
11809 * Check current plane state versus the new one to determine whether
11810 * watermarks need to be recalculated.
11812 * Returns true or false.
11814 static bool intel_wm_need_update(struct drm_plane
*plane
,
11815 struct drm_plane_state
*state
)
11817 struct intel_plane_state
*new = to_intel_plane_state(state
);
11818 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
11820 /* Update watermarks on tiling or size changes. */
11821 if (new->visible
!= cur
->visible
)
11824 if (!cur
->base
.fb
|| !new->base
.fb
)
11827 if (cur
->base
.fb
->modifier
[0] != new->base
.fb
->modifier
[0] ||
11828 cur
->base
.rotation
!= new->base
.rotation
||
11829 drm_rect_width(&new->src
) != drm_rect_width(&cur
->src
) ||
11830 drm_rect_height(&new->src
) != drm_rect_height(&cur
->src
) ||
11831 drm_rect_width(&new->dst
) != drm_rect_width(&cur
->dst
) ||
11832 drm_rect_height(&new->dst
) != drm_rect_height(&cur
->dst
))
11838 static bool needs_scaling(struct intel_plane_state
*state
)
11840 int src_w
= drm_rect_width(&state
->src
) >> 16;
11841 int src_h
= drm_rect_height(&state
->src
) >> 16;
11842 int dst_w
= drm_rect_width(&state
->dst
);
11843 int dst_h
= drm_rect_height(&state
->dst
);
11845 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11848 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11849 struct drm_plane_state
*plane_state
)
11851 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11852 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11854 struct drm_plane
*plane
= plane_state
->plane
;
11855 struct drm_device
*dev
= crtc
->dev
;
11856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11857 struct intel_plane_state
*old_plane_state
=
11858 to_intel_plane_state(plane
->state
);
11859 bool mode_changed
= needs_modeset(crtc_state
);
11860 bool was_crtc_enabled
= crtc
->state
->active
;
11861 bool is_crtc_enabled
= crtc_state
->active
;
11862 bool turn_off
, turn_on
, visible
, was_visible
;
11863 struct drm_framebuffer
*fb
= plane_state
->fb
;
11866 if (INTEL_GEN(dev
) >= 9 && plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11867 ret
= skl_update_scaler_plane(
11868 to_intel_crtc_state(crtc_state
),
11869 to_intel_plane_state(plane_state
));
11874 was_visible
= old_plane_state
->visible
;
11875 visible
= to_intel_plane_state(plane_state
)->visible
;
11877 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11878 was_visible
= false;
11881 * Visibility is calculated as if the crtc was on, but
11882 * after scaler setup everything depends on it being off
11883 * when the crtc isn't active.
11885 * FIXME this is wrong for watermarks. Watermarks should also
11886 * be computed as if the pipe would be active. Perhaps move
11887 * per-plane wm computation to the .check_plane() hook, and
11888 * only combine the results from all planes in the current place?
11890 if (!is_crtc_enabled
)
11891 to_intel_plane_state(plane_state
)->visible
= visible
= false;
11893 if (!was_visible
&& !visible
)
11896 if (fb
!= old_plane_state
->base
.fb
)
11897 pipe_config
->fb_changed
= true;
11899 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11900 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11902 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11903 intel_crtc
->base
.base
.id
,
11904 intel_crtc
->base
.name
,
11905 plane
->base
.id
, plane
->name
,
11906 fb
? fb
->base
.id
: -1);
11908 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11909 plane
->base
.id
, plane
->name
,
11910 was_visible
, visible
,
11911 turn_off
, turn_on
, mode_changed
);
11914 pipe_config
->update_wm_pre
= true;
11916 /* must disable cxsr around plane enable/disable */
11917 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11918 pipe_config
->disable_cxsr
= true;
11919 } else if (turn_off
) {
11920 pipe_config
->update_wm_post
= true;
11922 /* must disable cxsr around plane enable/disable */
11923 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11924 pipe_config
->disable_cxsr
= true;
11925 } else if (intel_wm_need_update(plane
, plane_state
)) {
11926 /* FIXME bollocks */
11927 pipe_config
->update_wm_pre
= true;
11928 pipe_config
->update_wm_post
= true;
11931 /* Pre-gen9 platforms need two-step watermark updates */
11932 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
11933 INTEL_INFO(dev
)->gen
< 9 && dev_priv
->display
.optimize_watermarks
)
11934 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
11936 if (visible
|| was_visible
)
11937 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
11940 * WaCxSRDisabledForSpriteScaling:ivb
11942 * cstate->update_wm was already set above, so this flag will
11943 * take effect when we commit and program watermarks.
11945 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev
) &&
11946 needs_scaling(to_intel_plane_state(plane_state
)) &&
11947 !needs_scaling(old_plane_state
))
11948 pipe_config
->disable_lp_wm
= true;
11953 static bool encoders_cloneable(const struct intel_encoder
*a
,
11954 const struct intel_encoder
*b
)
11956 /* masks could be asymmetric, so check both ways */
11957 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11958 b
->cloneable
& (1 << a
->type
));
11961 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11962 struct intel_crtc
*crtc
,
11963 struct intel_encoder
*encoder
)
11965 struct intel_encoder
*source_encoder
;
11966 struct drm_connector
*connector
;
11967 struct drm_connector_state
*connector_state
;
11970 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11971 if (connector_state
->crtc
!= &crtc
->base
)
11975 to_intel_encoder(connector_state
->best_encoder
);
11976 if (!encoders_cloneable(encoder
, source_encoder
))
11983 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11984 struct drm_crtc_state
*crtc_state
)
11986 struct drm_device
*dev
= crtc
->dev
;
11987 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11989 struct intel_crtc_state
*pipe_config
=
11990 to_intel_crtc_state(crtc_state
);
11991 struct drm_atomic_state
*state
= crtc_state
->state
;
11993 bool mode_changed
= needs_modeset(crtc_state
);
11995 if (mode_changed
&& !crtc_state
->active
)
11996 pipe_config
->update_wm_post
= true;
11998 if (mode_changed
&& crtc_state
->enable
&&
11999 dev_priv
->display
.crtc_compute_clock
&&
12000 !WARN_ON(pipe_config
->shared_dpll
)) {
12001 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12007 if (crtc_state
->color_mgmt_changed
) {
12008 ret
= intel_color_check(crtc
, crtc_state
);
12013 * Changing color management on Intel hardware is
12014 * handled as part of planes update.
12016 crtc_state
->planes_changed
= true;
12020 if (dev_priv
->display
.compute_pipe_wm
) {
12021 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
12023 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12028 if (dev_priv
->display
.compute_intermediate_wm
&&
12029 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
12030 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
12034 * Calculate 'intermediate' watermarks that satisfy both the
12035 * old state and the new state. We can program these
12038 ret
= dev_priv
->display
.compute_intermediate_wm(crtc
->dev
,
12042 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12045 } else if (dev_priv
->display
.compute_intermediate_wm
) {
12046 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
12047 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
12050 if (INTEL_INFO(dev
)->gen
>= 9) {
12052 ret
= skl_update_scaler_crtc(pipe_config
);
12055 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12062 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12063 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12064 .atomic_begin
= intel_begin_crtc_commit
,
12065 .atomic_flush
= intel_finish_crtc_commit
,
12066 .atomic_check
= intel_crtc_atomic_check
,
12069 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12071 struct intel_connector
*connector
;
12073 for_each_intel_connector(dev
, connector
) {
12074 if (connector
->base
.state
->crtc
)
12075 drm_connector_unreference(&connector
->base
);
12077 if (connector
->base
.encoder
) {
12078 connector
->base
.state
->best_encoder
=
12079 connector
->base
.encoder
;
12080 connector
->base
.state
->crtc
=
12081 connector
->base
.encoder
->crtc
;
12083 drm_connector_reference(&connector
->base
);
12085 connector
->base
.state
->best_encoder
= NULL
;
12086 connector
->base
.state
->crtc
= NULL
;
12092 connected_sink_compute_bpp(struct intel_connector
*connector
,
12093 struct intel_crtc_state
*pipe_config
)
12095 int bpp
= pipe_config
->pipe_bpp
;
12097 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12098 connector
->base
.base
.id
,
12099 connector
->base
.name
);
12101 /* Don't use an invalid EDID bpc value */
12102 if (connector
->base
.display_info
.bpc
&&
12103 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12104 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12105 bpp
, connector
->base
.display_info
.bpc
*3);
12106 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12109 /* Clamp bpp to 8 on screens without EDID 1.4 */
12110 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
12111 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12113 pipe_config
->pipe_bpp
= 24;
12118 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12119 struct intel_crtc_state
*pipe_config
)
12121 struct drm_device
*dev
= crtc
->base
.dev
;
12122 struct drm_atomic_state
*state
;
12123 struct drm_connector
*connector
;
12124 struct drm_connector_state
*connector_state
;
12127 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)))
12129 else if (INTEL_INFO(dev
)->gen
>= 5)
12135 pipe_config
->pipe_bpp
= bpp
;
12137 state
= pipe_config
->base
.state
;
12139 /* Clamp display bpp to EDID value */
12140 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12141 if (connector_state
->crtc
!= &crtc
->base
)
12144 connected_sink_compute_bpp(to_intel_connector(connector
),
12151 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12153 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12154 "type: 0x%x flags: 0x%x\n",
12156 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12157 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12158 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12159 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12162 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12163 struct intel_crtc_state
*pipe_config
,
12164 const char *context
)
12166 struct drm_device
*dev
= crtc
->base
.dev
;
12167 struct drm_plane
*plane
;
12168 struct intel_plane
*intel_plane
;
12169 struct intel_plane_state
*state
;
12170 struct drm_framebuffer
*fb
;
12172 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12173 crtc
->base
.base
.id
, crtc
->base
.name
,
12174 context
, pipe_config
, pipe_name(crtc
->pipe
));
12176 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config
->cpu_transcoder
));
12177 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12178 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12179 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12180 pipe_config
->has_pch_encoder
,
12181 pipe_config
->fdi_lanes
,
12182 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12183 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12184 pipe_config
->fdi_m_n
.tu
);
12185 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12186 intel_crtc_has_dp_encoder(pipe_config
),
12187 pipe_config
->lane_count
,
12188 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12189 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12190 pipe_config
->dp_m_n
.tu
);
12192 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12193 intel_crtc_has_dp_encoder(pipe_config
),
12194 pipe_config
->lane_count
,
12195 pipe_config
->dp_m2_n2
.gmch_m
,
12196 pipe_config
->dp_m2_n2
.gmch_n
,
12197 pipe_config
->dp_m2_n2
.link_m
,
12198 pipe_config
->dp_m2_n2
.link_n
,
12199 pipe_config
->dp_m2_n2
.tu
);
12201 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12202 pipe_config
->has_audio
,
12203 pipe_config
->has_infoframe
);
12205 DRM_DEBUG_KMS("requested mode:\n");
12206 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12207 DRM_DEBUG_KMS("adjusted mode:\n");
12208 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12209 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12210 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12211 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12212 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12213 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12215 pipe_config
->scaler_state
.scaler_users
,
12216 pipe_config
->scaler_state
.scaler_id
);
12217 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12218 pipe_config
->gmch_pfit
.control
,
12219 pipe_config
->gmch_pfit
.pgm_ratios
,
12220 pipe_config
->gmch_pfit
.lvds_border_bits
);
12221 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12222 pipe_config
->pch_pfit
.pos
,
12223 pipe_config
->pch_pfit
.size
,
12224 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12225 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12226 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12228 if (IS_BROXTON(dev
)) {
12229 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12230 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12231 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12232 pipe_config
->ddi_pll_sel
,
12233 pipe_config
->dpll_hw_state
.ebb0
,
12234 pipe_config
->dpll_hw_state
.ebb4
,
12235 pipe_config
->dpll_hw_state
.pll0
,
12236 pipe_config
->dpll_hw_state
.pll1
,
12237 pipe_config
->dpll_hw_state
.pll2
,
12238 pipe_config
->dpll_hw_state
.pll3
,
12239 pipe_config
->dpll_hw_state
.pll6
,
12240 pipe_config
->dpll_hw_state
.pll8
,
12241 pipe_config
->dpll_hw_state
.pll9
,
12242 pipe_config
->dpll_hw_state
.pll10
,
12243 pipe_config
->dpll_hw_state
.pcsdw12
);
12244 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
12245 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12246 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12247 pipe_config
->ddi_pll_sel
,
12248 pipe_config
->dpll_hw_state
.ctrl1
,
12249 pipe_config
->dpll_hw_state
.cfgcr1
,
12250 pipe_config
->dpll_hw_state
.cfgcr2
);
12251 } else if (HAS_DDI(dev
)) {
12252 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12253 pipe_config
->ddi_pll_sel
,
12254 pipe_config
->dpll_hw_state
.wrpll
,
12255 pipe_config
->dpll_hw_state
.spll
);
12257 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12258 "fp0: 0x%x, fp1: 0x%x\n",
12259 pipe_config
->dpll_hw_state
.dpll
,
12260 pipe_config
->dpll_hw_state
.dpll_md
,
12261 pipe_config
->dpll_hw_state
.fp0
,
12262 pipe_config
->dpll_hw_state
.fp1
);
12265 DRM_DEBUG_KMS("planes on this crtc\n");
12266 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12267 intel_plane
= to_intel_plane(plane
);
12268 if (intel_plane
->pipe
!= crtc
->pipe
)
12271 state
= to_intel_plane_state(plane
->state
);
12272 fb
= state
->base
.fb
;
12274 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12275 plane
->base
.id
, plane
->name
, state
->scaler_id
);
12279 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12280 plane
->base
.id
, plane
->name
);
12281 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12282 fb
->base
.id
, fb
->width
, fb
->height
,
12283 drm_get_format_name(fb
->pixel_format
));
12284 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12286 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12287 drm_rect_width(&state
->src
) >> 16,
12288 drm_rect_height(&state
->src
) >> 16,
12289 state
->dst
.x1
, state
->dst
.y1
,
12290 drm_rect_width(&state
->dst
),
12291 drm_rect_height(&state
->dst
));
12295 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12297 struct drm_device
*dev
= state
->dev
;
12298 struct drm_connector
*connector
;
12299 unsigned int used_ports
= 0;
12302 * Walk the connector list instead of the encoder
12303 * list to detect the problem on ddi platforms
12304 * where there's just one encoder per digital port.
12306 drm_for_each_connector(connector
, dev
) {
12307 struct drm_connector_state
*connector_state
;
12308 struct intel_encoder
*encoder
;
12310 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12311 if (!connector_state
)
12312 connector_state
= connector
->state
;
12314 if (!connector_state
->best_encoder
)
12317 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12319 WARN_ON(!connector_state
->crtc
);
12321 switch (encoder
->type
) {
12322 unsigned int port_mask
;
12323 case INTEL_OUTPUT_UNKNOWN
:
12324 if (WARN_ON(!HAS_DDI(dev
)))
12326 case INTEL_OUTPUT_DP
:
12327 case INTEL_OUTPUT_HDMI
:
12328 case INTEL_OUTPUT_EDP
:
12329 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12331 /* the same port mustn't appear more than once */
12332 if (used_ports
& port_mask
)
12335 used_ports
|= port_mask
;
12345 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12347 struct drm_crtc_state tmp_state
;
12348 struct intel_crtc_scaler_state scaler_state
;
12349 struct intel_dpll_hw_state dpll_hw_state
;
12350 struct intel_shared_dpll
*shared_dpll
;
12351 uint32_t ddi_pll_sel
;
12354 /* FIXME: before the switch to atomic started, a new pipe_config was
12355 * kzalloc'd. Code that depends on any field being zero should be
12356 * fixed, so that the crtc_state can be safely duplicated. For now,
12357 * only fields that are know to not cause problems are preserved. */
12359 tmp_state
= crtc_state
->base
;
12360 scaler_state
= crtc_state
->scaler_state
;
12361 shared_dpll
= crtc_state
->shared_dpll
;
12362 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12363 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12364 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12366 memset(crtc_state
, 0, sizeof *crtc_state
);
12368 crtc_state
->base
= tmp_state
;
12369 crtc_state
->scaler_state
= scaler_state
;
12370 crtc_state
->shared_dpll
= shared_dpll
;
12371 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12372 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12373 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12377 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12378 struct intel_crtc_state
*pipe_config
)
12380 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12381 struct intel_encoder
*encoder
;
12382 struct drm_connector
*connector
;
12383 struct drm_connector_state
*connector_state
;
12384 int base_bpp
, ret
= -EINVAL
;
12388 clear_intel_crtc_state(pipe_config
);
12390 pipe_config
->cpu_transcoder
=
12391 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12394 * Sanitize sync polarity flags based on requested ones. If neither
12395 * positive or negative polarity is requested, treat this as meaning
12396 * negative polarity.
12398 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12399 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12400 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12402 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12403 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12404 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12406 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12412 * Determine the real pipe dimensions. Note that stereo modes can
12413 * increase the actual pipe size due to the frame doubling and
12414 * insertion of additional space for blanks between the frame. This
12415 * is stored in the crtc timings. We use the requested mode to do this
12416 * computation to clearly distinguish it from the adjusted mode, which
12417 * can be changed by the connectors in the below retry loop.
12419 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12420 &pipe_config
->pipe_src_w
,
12421 &pipe_config
->pipe_src_h
);
12423 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12424 if (connector_state
->crtc
!= crtc
)
12427 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12429 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
12430 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12435 * Determine output_types before calling the .compute_config()
12436 * hooks so that the hooks can use this information safely.
12438 pipe_config
->output_types
|= 1 << encoder
->type
;
12442 /* Ensure the port clock defaults are reset when retrying. */
12443 pipe_config
->port_clock
= 0;
12444 pipe_config
->pixel_multiplier
= 1;
12446 /* Fill in default crtc timings, allow encoders to overwrite them. */
12447 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12448 CRTC_STEREO_DOUBLE
);
12450 /* Pass our mode to the connectors and the CRTC to give them a chance to
12451 * adjust it according to limitations or connector properties, and also
12452 * a chance to reject the mode entirely.
12454 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12455 if (connector_state
->crtc
!= crtc
)
12458 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12460 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12461 DRM_DEBUG_KMS("Encoder config failure\n");
12466 /* Set default port clock if not overwritten by the encoder. Needs to be
12467 * done afterwards in case the encoder adjusts the mode. */
12468 if (!pipe_config
->port_clock
)
12469 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12470 * pipe_config
->pixel_multiplier
;
12472 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12474 DRM_DEBUG_KMS("CRTC fixup failed\n");
12478 if (ret
== RETRY
) {
12479 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12484 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12486 goto encoder_retry
;
12489 /* Dithering seems to not pass-through bits correctly when it should, so
12490 * only enable it on 6bpc panels. */
12491 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12492 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12493 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12500 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12502 struct drm_crtc
*crtc
;
12503 struct drm_crtc_state
*crtc_state
;
12506 /* Double check state. */
12507 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12508 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12510 /* Update hwmode for vblank functions */
12511 if (crtc
->state
->active
)
12512 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12514 crtc
->hwmode
.crtc_clock
= 0;
12517 * Update legacy state to satisfy fbc code. This can
12518 * be removed when fbc uses the atomic state.
12520 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12521 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
12523 crtc
->primary
->fb
= plane_state
->fb
;
12524 crtc
->x
= plane_state
->src_x
>> 16;
12525 crtc
->y
= plane_state
->src_y
>> 16;
12530 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12534 if (clock1
== clock2
)
12537 if (!clock1
|| !clock2
)
12540 diff
= abs(clock1
- clock2
);
12542 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12548 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12549 list_for_each_entry((intel_crtc), \
12550 &(dev)->mode_config.crtc_list, \
12552 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12555 intel_compare_m_n(unsigned int m
, unsigned int n
,
12556 unsigned int m2
, unsigned int n2
,
12559 if (m
== m2
&& n
== n2
)
12562 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12565 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12572 } else if (n
< n2
) {
12582 return intel_fuzzy_clock_check(m
, m2
);
12586 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12587 struct intel_link_m_n
*m2_n2
,
12590 if (m_n
->tu
== m2_n2
->tu
&&
12591 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12592 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12593 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12594 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12605 intel_pipe_config_compare(struct drm_device
*dev
,
12606 struct intel_crtc_state
*current_config
,
12607 struct intel_crtc_state
*pipe_config
,
12612 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12615 DRM_ERROR(fmt, ##__VA_ARGS__); \
12617 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12620 #define PIPE_CONF_CHECK_X(name) \
12621 if (current_config->name != pipe_config->name) { \
12622 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12623 "(expected 0x%08x, found 0x%08x)\n", \
12624 current_config->name, \
12625 pipe_config->name); \
12629 #define PIPE_CONF_CHECK_I(name) \
12630 if (current_config->name != pipe_config->name) { \
12631 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12632 "(expected %i, found %i)\n", \
12633 current_config->name, \
12634 pipe_config->name); \
12638 #define PIPE_CONF_CHECK_P(name) \
12639 if (current_config->name != pipe_config->name) { \
12640 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12641 "(expected %p, found %p)\n", \
12642 current_config->name, \
12643 pipe_config->name); \
12647 #define PIPE_CONF_CHECK_M_N(name) \
12648 if (!intel_compare_link_m_n(¤t_config->name, \
12649 &pipe_config->name,\
12651 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12652 "(expected tu %i gmch %i/%i link %i/%i, " \
12653 "found tu %i, gmch %i/%i link %i/%i)\n", \
12654 current_config->name.tu, \
12655 current_config->name.gmch_m, \
12656 current_config->name.gmch_n, \
12657 current_config->name.link_m, \
12658 current_config->name.link_n, \
12659 pipe_config->name.tu, \
12660 pipe_config->name.gmch_m, \
12661 pipe_config->name.gmch_n, \
12662 pipe_config->name.link_m, \
12663 pipe_config->name.link_n); \
12667 /* This is required for BDW+ where there is only one set of registers for
12668 * switching between high and low RR.
12669 * This macro can be used whenever a comparison has to be made between one
12670 * hw state and multiple sw state variables.
12672 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12673 if (!intel_compare_link_m_n(¤t_config->name, \
12674 &pipe_config->name, adjust) && \
12675 !intel_compare_link_m_n(¤t_config->alt_name, \
12676 &pipe_config->name, adjust)) { \
12677 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12678 "(expected tu %i gmch %i/%i link %i/%i, " \
12679 "or tu %i gmch %i/%i link %i/%i, " \
12680 "found tu %i, gmch %i/%i link %i/%i)\n", \
12681 current_config->name.tu, \
12682 current_config->name.gmch_m, \
12683 current_config->name.gmch_n, \
12684 current_config->name.link_m, \
12685 current_config->name.link_n, \
12686 current_config->alt_name.tu, \
12687 current_config->alt_name.gmch_m, \
12688 current_config->alt_name.gmch_n, \
12689 current_config->alt_name.link_m, \
12690 current_config->alt_name.link_n, \
12691 pipe_config->name.tu, \
12692 pipe_config->name.gmch_m, \
12693 pipe_config->name.gmch_n, \
12694 pipe_config->name.link_m, \
12695 pipe_config->name.link_n); \
12699 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12700 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12701 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12702 "(expected %i, found %i)\n", \
12703 current_config->name & (mask), \
12704 pipe_config->name & (mask)); \
12708 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12709 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12710 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12711 "(expected %i, found %i)\n", \
12712 current_config->name, \
12713 pipe_config->name); \
12717 #define PIPE_CONF_QUIRK(quirk) \
12718 ((current_config->quirks | pipe_config->quirks) & (quirk))
12720 PIPE_CONF_CHECK_I(cpu_transcoder
);
12722 PIPE_CONF_CHECK_I(has_pch_encoder
);
12723 PIPE_CONF_CHECK_I(fdi_lanes
);
12724 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12726 PIPE_CONF_CHECK_I(lane_count
);
12727 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12729 if (INTEL_INFO(dev
)->gen
< 8) {
12730 PIPE_CONF_CHECK_M_N(dp_m_n
);
12732 if (current_config
->has_drrs
)
12733 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12735 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12737 PIPE_CONF_CHECK_X(output_types
);
12739 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12740 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12741 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12742 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12743 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12744 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12746 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12747 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12748 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12749 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12750 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12751 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12753 PIPE_CONF_CHECK_I(pixel_multiplier
);
12754 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12755 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12756 IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
12757 PIPE_CONF_CHECK_I(limited_color_range
);
12758 PIPE_CONF_CHECK_I(has_infoframe
);
12760 PIPE_CONF_CHECK_I(has_audio
);
12762 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12763 DRM_MODE_FLAG_INTERLACE
);
12765 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12766 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12767 DRM_MODE_FLAG_PHSYNC
);
12768 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12769 DRM_MODE_FLAG_NHSYNC
);
12770 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12771 DRM_MODE_FLAG_PVSYNC
);
12772 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12773 DRM_MODE_FLAG_NVSYNC
);
12776 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12777 /* pfit ratios are autocomputed by the hw on gen4+ */
12778 if (INTEL_INFO(dev
)->gen
< 4)
12779 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12780 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12783 PIPE_CONF_CHECK_I(pipe_src_w
);
12784 PIPE_CONF_CHECK_I(pipe_src_h
);
12786 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12787 if (current_config
->pch_pfit
.enabled
) {
12788 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12789 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12792 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12795 /* BDW+ don't expose a synchronous way to read the state */
12796 if (IS_HASWELL(dev
))
12797 PIPE_CONF_CHECK_I(ips_enabled
);
12799 PIPE_CONF_CHECK_I(double_wide
);
12801 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12803 PIPE_CONF_CHECK_P(shared_dpll
);
12804 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12805 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12806 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12807 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12808 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12809 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12810 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12811 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12812 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12814 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12815 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12817 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12818 PIPE_CONF_CHECK_I(pipe_bpp
);
12820 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12821 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12823 #undef PIPE_CONF_CHECK_X
12824 #undef PIPE_CONF_CHECK_I
12825 #undef PIPE_CONF_CHECK_P
12826 #undef PIPE_CONF_CHECK_FLAGS
12827 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12828 #undef PIPE_CONF_QUIRK
12829 #undef INTEL_ERR_OR_DBG_KMS
12834 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12835 const struct intel_crtc_state
*pipe_config
)
12837 if (pipe_config
->has_pch_encoder
) {
12838 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12839 &pipe_config
->fdi_m_n
);
12840 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12843 * FDI already provided one idea for the dotclock.
12844 * Yell if the encoder disagrees.
12846 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12847 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12848 fdi_dotclock
, dotclock
);
12852 static void verify_wm_state(struct drm_crtc
*crtc
,
12853 struct drm_crtc_state
*new_state
)
12855 struct drm_device
*dev
= crtc
->dev
;
12856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12857 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12858 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12860 const enum pipe pipe
= intel_crtc
->pipe
;
12863 if (INTEL_INFO(dev
)->gen
< 9 || !new_state
->active
)
12866 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12867 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12870 for_each_plane(dev_priv
, pipe
, plane
) {
12871 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12872 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12874 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12877 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12878 "(expected (%u,%u), found (%u,%u))\n",
12879 pipe_name(pipe
), plane
+ 1,
12880 sw_entry
->start
, sw_entry
->end
,
12881 hw_entry
->start
, hw_entry
->end
);
12885 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12886 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12888 if (!skl_ddb_entry_equal(hw_entry
, sw_entry
)) {
12889 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12890 "(expected (%u,%u), found (%u,%u))\n",
12892 sw_entry
->start
, sw_entry
->end
,
12893 hw_entry
->start
, hw_entry
->end
);
12898 verify_connector_state(struct drm_device
*dev
, struct drm_crtc
*crtc
)
12900 struct drm_connector
*connector
;
12902 drm_for_each_connector(connector
, dev
) {
12903 struct drm_encoder
*encoder
= connector
->encoder
;
12904 struct drm_connector_state
*state
= connector
->state
;
12906 if (state
->crtc
!= crtc
)
12909 intel_connector_verify_state(to_intel_connector(connector
));
12911 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12912 "connector's atomic encoder doesn't match legacy encoder\n");
12917 verify_encoder_state(struct drm_device
*dev
)
12919 struct intel_encoder
*encoder
;
12920 struct intel_connector
*connector
;
12922 for_each_intel_encoder(dev
, encoder
) {
12923 bool enabled
= false;
12926 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12927 encoder
->base
.base
.id
,
12928 encoder
->base
.name
);
12930 for_each_intel_connector(dev
, connector
) {
12931 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12935 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12936 encoder
->base
.crtc
,
12937 "connector's crtc doesn't match encoder crtc\n");
12940 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12941 "encoder's enabled state mismatch "
12942 "(expected %i, found %i)\n",
12943 !!encoder
->base
.crtc
, enabled
);
12945 if (!encoder
->base
.crtc
) {
12948 active
= encoder
->get_hw_state(encoder
, &pipe
);
12949 I915_STATE_WARN(active
,
12950 "encoder detached but still enabled on pipe %c.\n",
12957 verify_crtc_state(struct drm_crtc
*crtc
,
12958 struct drm_crtc_state
*old_crtc_state
,
12959 struct drm_crtc_state
*new_crtc_state
)
12961 struct drm_device
*dev
= crtc
->dev
;
12962 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12963 struct intel_encoder
*encoder
;
12964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12965 struct intel_crtc_state
*pipe_config
, *sw_config
;
12966 struct drm_atomic_state
*old_state
;
12969 old_state
= old_crtc_state
->state
;
12970 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
12971 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12972 memset(pipe_config
, 0, sizeof(*pipe_config
));
12973 pipe_config
->base
.crtc
= crtc
;
12974 pipe_config
->base
.state
= old_state
;
12976 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
12978 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12980 /* hw state is inconsistent with the pipe quirk */
12981 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12982 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12983 active
= new_crtc_state
->active
;
12985 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12986 "crtc active state doesn't match with hw state "
12987 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12989 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12990 "transitional active state does not match atomic hw state "
12991 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12993 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12996 active
= encoder
->get_hw_state(encoder
, &pipe
);
12997 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12998 "[ENCODER:%i] active %i with crtc active %i\n",
12999 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
13001 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
13002 "Encoder connected to wrong pipe %c\n",
13006 pipe_config
->output_types
|= 1 << encoder
->type
;
13007 encoder
->get_config(encoder
, pipe_config
);
13011 if (!new_crtc_state
->active
)
13014 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
13016 sw_config
= to_intel_crtc_state(crtc
->state
);
13017 if (!intel_pipe_config_compare(dev
, sw_config
,
13018 pipe_config
, false)) {
13019 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13020 intel_dump_pipe_config(intel_crtc
, pipe_config
,
13022 intel_dump_pipe_config(intel_crtc
, sw_config
,
13028 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
13029 struct intel_shared_dpll
*pll
,
13030 struct drm_crtc
*crtc
,
13031 struct drm_crtc_state
*new_state
)
13033 struct intel_dpll_hw_state dpll_hw_state
;
13034 unsigned crtc_mask
;
13037 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
13039 DRM_DEBUG_KMS("%s\n", pll
->name
);
13041 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
13043 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
13044 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
13045 "pll in active use but not on in sw tracking\n");
13046 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
13047 "pll is on but not used by any active crtc\n");
13048 I915_STATE_WARN(pll
->on
!= active
,
13049 "pll on state mismatch (expected %i, found %i)\n",
13054 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
13055 "more active pll users than references: %x vs %x\n",
13056 pll
->active_mask
, pll
->config
.crtc_mask
);
13061 crtc_mask
= 1 << drm_crtc_index(crtc
);
13063 if (new_state
->active
)
13064 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13065 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13066 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13068 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13069 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13070 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13072 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
13073 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13074 crtc_mask
, pll
->config
.crtc_mask
);
13076 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
13078 sizeof(dpll_hw_state
)),
13079 "pll hw state mismatch\n");
13083 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13084 struct drm_crtc_state
*old_crtc_state
,
13085 struct drm_crtc_state
*new_crtc_state
)
13087 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13088 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13089 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13091 if (new_state
->shared_dpll
)
13092 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13094 if (old_state
->shared_dpll
&&
13095 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13096 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13097 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13099 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13100 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13101 pipe_name(drm_crtc_index(crtc
)));
13102 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13103 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13104 pipe_name(drm_crtc_index(crtc
)));
13109 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13110 struct drm_crtc_state
*old_state
,
13111 struct drm_crtc_state
*new_state
)
13113 if (!needs_modeset(new_state
) &&
13114 !to_intel_crtc_state(new_state
)->update_pipe
)
13117 verify_wm_state(crtc
, new_state
);
13118 verify_connector_state(crtc
->dev
, crtc
);
13119 verify_crtc_state(crtc
, old_state
, new_state
);
13120 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13124 verify_disabled_dpll_state(struct drm_device
*dev
)
13126 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13129 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13130 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13134 intel_modeset_verify_disabled(struct drm_device
*dev
)
13136 verify_encoder_state(dev
);
13137 verify_connector_state(dev
, NULL
);
13138 verify_disabled_dpll_state(dev
);
13141 static void update_scanline_offset(struct intel_crtc
*crtc
)
13143 struct drm_device
*dev
= crtc
->base
.dev
;
13146 * The scanline counter increments at the leading edge of hsync.
13148 * On most platforms it starts counting from vtotal-1 on the
13149 * first active line. That means the scanline counter value is
13150 * always one less than what we would expect. Ie. just after
13151 * start of vblank, which also occurs at start of hsync (on the
13152 * last active line), the scanline counter will read vblank_start-1.
13154 * On gen2 the scanline counter starts counting from 1 instead
13155 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13156 * to keep the value positive), instead of adding one.
13158 * On HSW+ the behaviour of the scanline counter depends on the output
13159 * type. For DP ports it behaves like most other platforms, but on HDMI
13160 * there's an extra 1 line difference. So we need to add two instead of
13161 * one to the value.
13163 if (IS_GEN2(dev
)) {
13164 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13167 vtotal
= adjusted_mode
->crtc_vtotal
;
13168 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13171 crtc
->scanline_offset
= vtotal
- 1;
13172 } else if (HAS_DDI(dev
) &&
13173 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
13174 crtc
->scanline_offset
= 2;
13176 crtc
->scanline_offset
= 1;
13179 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13181 struct drm_device
*dev
= state
->dev
;
13182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13183 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13184 struct drm_crtc
*crtc
;
13185 struct drm_crtc_state
*crtc_state
;
13188 if (!dev_priv
->display
.crtc_compute_clock
)
13191 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13193 struct intel_shared_dpll
*old_dpll
=
13194 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13196 if (!needs_modeset(crtc_state
))
13199 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13205 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13207 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13212 * This implements the workaround described in the "notes" section of the mode
13213 * set sequence documentation. When going from no pipes or single pipe to
13214 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13215 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13217 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13219 struct drm_crtc_state
*crtc_state
;
13220 struct intel_crtc
*intel_crtc
;
13221 struct drm_crtc
*crtc
;
13222 struct intel_crtc_state
*first_crtc_state
= NULL
;
13223 struct intel_crtc_state
*other_crtc_state
= NULL
;
13224 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13227 /* look at all crtc's that are going to be enabled in during modeset */
13228 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13229 intel_crtc
= to_intel_crtc(crtc
);
13231 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13234 if (first_crtc_state
) {
13235 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13238 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13239 first_pipe
= intel_crtc
->pipe
;
13243 /* No workaround needed? */
13244 if (!first_crtc_state
)
13247 /* w/a possibly needed, check how many crtc's are already enabled. */
13248 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13249 struct intel_crtc_state
*pipe_config
;
13251 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13252 if (IS_ERR(pipe_config
))
13253 return PTR_ERR(pipe_config
);
13255 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13257 if (!pipe_config
->base
.active
||
13258 needs_modeset(&pipe_config
->base
))
13261 /* 2 or more enabled crtcs means no need for w/a */
13262 if (enabled_pipe
!= INVALID_PIPE
)
13265 enabled_pipe
= intel_crtc
->pipe
;
13268 if (enabled_pipe
!= INVALID_PIPE
)
13269 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13270 else if (other_crtc_state
)
13271 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13276 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13278 struct drm_crtc
*crtc
;
13279 struct drm_crtc_state
*crtc_state
;
13282 /* add all active pipes to the state */
13283 for_each_crtc(state
->dev
, crtc
) {
13284 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13285 if (IS_ERR(crtc_state
))
13286 return PTR_ERR(crtc_state
);
13288 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13291 crtc_state
->mode_changed
= true;
13293 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13297 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13305 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13307 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13308 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13309 struct drm_crtc
*crtc
;
13310 struct drm_crtc_state
*crtc_state
;
13313 if (!check_digital_port_conflicts(state
)) {
13314 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13318 intel_state
->modeset
= true;
13319 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13321 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13322 if (crtc_state
->active
)
13323 intel_state
->active_crtcs
|= 1 << i
;
13325 intel_state
->active_crtcs
&= ~(1 << i
);
13327 if (crtc_state
->active
!= crtc
->state
->active
)
13328 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13332 * See if the config requires any additional preparation, e.g.
13333 * to adjust global state with pipes off. We need to do this
13334 * here so we can get the modeset_pipe updated config for the new
13335 * mode set on this crtc. For other crtcs we need to use the
13336 * adjusted_mode bits in the crtc directly.
13338 if (dev_priv
->display
.modeset_calc_cdclk
) {
13339 if (!intel_state
->cdclk_pll_vco
)
13340 intel_state
->cdclk_pll_vco
= dev_priv
->cdclk_pll
.vco
;
13341 if (!intel_state
->cdclk_pll_vco
)
13342 intel_state
->cdclk_pll_vco
= dev_priv
->skl_preferred_vco_freq
;
13344 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13348 if (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13349 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
)
13350 ret
= intel_modeset_all_pipes(state
);
13355 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13356 intel_state
->cdclk
, intel_state
->dev_cdclk
);
13358 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
13360 intel_modeset_clear_plls(state
);
13362 if (IS_HASWELL(dev_priv
))
13363 return haswell_mode_set_planes_workaround(state
);
13369 * Handle calculation of various watermark data at the end of the atomic check
13370 * phase. The code here should be run after the per-crtc and per-plane 'check'
13371 * handlers to ensure that all derived state has been updated.
13373 static int calc_watermark_data(struct drm_atomic_state
*state
)
13375 struct drm_device
*dev
= state
->dev
;
13376 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13378 /* Is there platform-specific watermark information to calculate? */
13379 if (dev_priv
->display
.compute_global_watermarks
)
13380 return dev_priv
->display
.compute_global_watermarks(state
);
13386 * intel_atomic_check - validate state object
13388 * @state: state to validate
13390 static int intel_atomic_check(struct drm_device
*dev
,
13391 struct drm_atomic_state
*state
)
13393 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13394 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13395 struct drm_crtc
*crtc
;
13396 struct drm_crtc_state
*crtc_state
;
13398 bool any_ms
= false;
13400 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13404 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13405 struct intel_crtc_state
*pipe_config
=
13406 to_intel_crtc_state(crtc_state
);
13408 /* Catch I915_MODE_FLAG_INHERITED */
13409 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13410 crtc_state
->mode_changed
= true;
13412 if (!needs_modeset(crtc_state
))
13415 if (!crtc_state
->enable
) {
13420 /* FIXME: For only active_changed we shouldn't need to do any
13421 * state recomputation at all. */
13423 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13427 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13429 intel_dump_pipe_config(to_intel_crtc(crtc
),
13430 pipe_config
, "[failed]");
13434 if (i915
.fastboot
&&
13435 intel_pipe_config_compare(dev
,
13436 to_intel_crtc_state(crtc
->state
),
13437 pipe_config
, true)) {
13438 crtc_state
->mode_changed
= false;
13439 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13442 if (needs_modeset(crtc_state
))
13445 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13449 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13450 needs_modeset(crtc_state
) ?
13451 "[modeset]" : "[fastset]");
13455 ret
= intel_modeset_checks(state
);
13460 intel_state
->cdclk
= dev_priv
->cdclk_freq
;
13462 ret
= drm_atomic_helper_check_planes(dev
, state
);
13466 intel_fbc_choose_crtc(dev_priv
, state
);
13467 return calc_watermark_data(state
);
13470 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13471 struct drm_atomic_state
*state
,
13474 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13475 struct drm_plane_state
*plane_state
;
13476 struct drm_crtc_state
*crtc_state
;
13477 struct drm_plane
*plane
;
13478 struct drm_crtc
*crtc
;
13481 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13482 if (state
->legacy_cursor_update
)
13485 ret
= intel_crtc_wait_for_pending_flips(crtc
);
13489 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
13490 flush_workqueue(dev_priv
->wq
);
13493 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
13497 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13498 mutex_unlock(&dev
->struct_mutex
);
13500 if (!ret
&& !nonblock
) {
13501 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13502 struct intel_plane_state
*intel_plane_state
=
13503 to_intel_plane_state(plane_state
);
13505 if (!intel_plane_state
->wait_req
)
13508 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13511 /* Any hang should be swallowed by the wait */
13512 WARN_ON(ret
== -EIO
);
13513 mutex_lock(&dev
->struct_mutex
);
13514 drm_atomic_helper_cleanup_planes(dev
, state
);
13515 mutex_unlock(&dev
->struct_mutex
);
13524 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13526 struct drm_device
*dev
= crtc
->base
.dev
;
13528 if (!dev
->max_vblank_count
)
13529 return drm_accurate_vblank_count(&crtc
->base
);
13531 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13534 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
13535 struct drm_i915_private
*dev_priv
,
13536 unsigned crtc_mask
)
13538 unsigned last_vblank_count
[I915_MAX_PIPES
];
13545 for_each_pipe(dev_priv
, pipe
) {
13546 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13548 if (!((1 << pipe
) & crtc_mask
))
13551 ret
= drm_crtc_vblank_get(crtc
);
13552 if (WARN_ON(ret
!= 0)) {
13553 crtc_mask
&= ~(1 << pipe
);
13557 last_vblank_count
[pipe
] = drm_crtc_vblank_count(crtc
);
13560 for_each_pipe(dev_priv
, pipe
) {
13561 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13564 if (!((1 << pipe
) & crtc_mask
))
13567 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
13568 last_vblank_count
[pipe
] !=
13569 drm_crtc_vblank_count(crtc
),
13570 msecs_to_jiffies(50));
13572 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
13574 drm_crtc_vblank_put(crtc
);
13578 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
13580 /* fb updated, need to unpin old fb */
13581 if (crtc_state
->fb_changed
)
13584 /* wm changes, need vblank before final wm's */
13585 if (crtc_state
->update_wm_post
)
13589 * cxsr is re-enabled after vblank.
13590 * This is already handled by crtc_state->update_wm_post,
13591 * but added for clarity.
13593 if (crtc_state
->disable_cxsr
)
13599 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13601 struct drm_device
*dev
= state
->dev
;
13602 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13603 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13604 struct drm_crtc_state
*old_crtc_state
;
13605 struct drm_crtc
*crtc
;
13606 struct intel_crtc_state
*intel_cstate
;
13607 struct drm_plane
*plane
;
13608 struct drm_plane_state
*plane_state
;
13609 bool hw_check
= intel_state
->modeset
;
13610 unsigned long put_domains
[I915_MAX_PIPES
] = {};
13611 unsigned crtc_vblank_mask
= 0;
13614 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13615 struct intel_plane_state
*intel_plane_state
=
13616 to_intel_plane_state(plane_state
);
13618 if (!intel_plane_state
->wait_req
)
13621 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13623 /* EIO should be eaten, and we can't get interrupted in the
13624 * worker, and blocking commits have waited already. */
13628 drm_atomic_helper_wait_for_dependencies(state
);
13630 if (intel_state
->modeset
) {
13631 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
13632 sizeof(intel_state
->min_pixclk
));
13633 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13634 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
13636 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13639 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13640 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13642 if (needs_modeset(crtc
->state
) ||
13643 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13646 put_domains
[to_intel_crtc(crtc
)->pipe
] =
13647 modeset_get_crtc_power_domains(crtc
,
13648 to_intel_crtc_state(crtc
->state
));
13651 if (!needs_modeset(crtc
->state
))
13654 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13656 if (old_crtc_state
->active
) {
13657 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
13658 dev_priv
->display
.crtc_disable(crtc
);
13659 intel_crtc
->active
= false;
13660 intel_fbc_disable(intel_crtc
);
13661 intel_disable_shared_dpll(intel_crtc
);
13664 * Underruns don't always raise
13665 * interrupts, so check manually.
13667 intel_check_cpu_fifo_underruns(dev_priv
);
13668 intel_check_pch_fifo_underruns(dev_priv
);
13670 if (!crtc
->state
->active
)
13671 intel_update_watermarks(crtc
);
13675 /* Only after disabling all output pipelines that will be changed can we
13676 * update the the output configuration. */
13677 intel_modeset_update_crtc_state(state
);
13679 if (intel_state
->modeset
) {
13680 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13682 if (dev_priv
->display
.modeset_commit_cdclk
&&
13683 (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13684 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
))
13685 dev_priv
->display
.modeset_commit_cdclk(state
);
13687 intel_modeset_verify_disabled(dev
);
13690 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13691 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13692 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13693 bool modeset
= needs_modeset(crtc
->state
);
13694 struct intel_crtc_state
*pipe_config
=
13695 to_intel_crtc_state(crtc
->state
);
13697 if (modeset
&& crtc
->state
->active
) {
13698 update_scanline_offset(to_intel_crtc(crtc
));
13699 dev_priv
->display
.crtc_enable(crtc
);
13702 /* Complete events for now disable pipes here. */
13703 if (modeset
&& !crtc
->state
->active
&& crtc
->state
->event
) {
13704 spin_lock_irq(&dev
->event_lock
);
13705 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
13706 spin_unlock_irq(&dev
->event_lock
);
13708 crtc
->state
->event
= NULL
;
13712 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13714 if (crtc
->state
->active
&&
13715 drm_atomic_get_existing_plane_state(state
, crtc
->primary
))
13716 intel_fbc_enable(intel_crtc
, pipe_config
, to_intel_plane_state(crtc
->primary
->state
));
13718 if (crtc
->state
->active
)
13719 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
13721 if (pipe_config
->base
.active
&& needs_vblank_wait(pipe_config
))
13722 crtc_vblank_mask
|= 1 << i
;
13725 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13726 * already, but still need the state for the delayed optimization. To
13728 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13729 * - schedule that vblank worker _before_ calling hw_done
13730 * - at the start of commit_tail, cancel it _synchrously
13731 * - switch over to the vblank wait helper in the core after that since
13732 * we don't need out special handling any more.
13734 if (!state
->legacy_cursor_update
)
13735 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
13738 * Now that the vblank has passed, we can go ahead and program the
13739 * optimal watermarks on platforms that need two-step watermark
13742 * TODO: Move this (and other cleanup) to an async worker eventually.
13744 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13745 intel_cstate
= to_intel_crtc_state(crtc
->state
);
13747 if (dev_priv
->display
.optimize_watermarks
)
13748 dev_priv
->display
.optimize_watermarks(intel_cstate
);
13751 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13752 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13754 if (put_domains
[i
])
13755 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13757 intel_modeset_verify_crtc(crtc
, old_crtc_state
, crtc
->state
);
13760 drm_atomic_helper_commit_hw_done(state
);
13762 if (intel_state
->modeset
)
13763 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
13765 mutex_lock(&dev
->struct_mutex
);
13766 drm_atomic_helper_cleanup_planes(dev
, state
);
13767 mutex_unlock(&dev
->struct_mutex
);
13769 drm_atomic_helper_commit_cleanup_done(state
);
13771 drm_atomic_state_free(state
);
13773 /* As one of the primary mmio accessors, KMS has a high likelihood
13774 * of triggering bugs in unclaimed access. After we finish
13775 * modesetting, see if an error has been flagged, and if so
13776 * enable debugging for the next modeset - and hope we catch
13779 * XXX note that we assume display power is on at this point.
13780 * This might hold true now but we need to add pm helper to check
13781 * unclaimed only when the hardware is on, as atomic commits
13782 * can happen also when the device is completely off.
13784 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
13787 static void intel_atomic_commit_work(struct work_struct
*work
)
13789 struct drm_atomic_state
*state
= container_of(work
,
13790 struct drm_atomic_state
,
13792 intel_atomic_commit_tail(state
);
13795 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13797 struct drm_plane_state
*old_plane_state
;
13798 struct drm_plane
*plane
;
13799 struct drm_i915_gem_object
*obj
, *old_obj
;
13800 struct intel_plane
*intel_plane
;
13803 mutex_lock(&state
->dev
->struct_mutex
);
13804 for_each_plane_in_state(state
, plane
, old_plane_state
, i
) {
13805 obj
= intel_fb_obj(plane
->state
->fb
);
13806 old_obj
= intel_fb_obj(old_plane_state
->fb
);
13807 intel_plane
= to_intel_plane(plane
);
13809 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13811 mutex_unlock(&state
->dev
->struct_mutex
);
13815 * intel_atomic_commit - commit validated state object
13817 * @state: the top-level driver state object
13818 * @nonblock: nonblocking commit
13820 * This function commits a top-level state object that has been validated
13821 * with drm_atomic_helper_check().
13823 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13824 * nonblocking commits are only safe for pure plane updates. Everything else
13825 * should work though.
13828 * Zero for success or -errno.
13830 static int intel_atomic_commit(struct drm_device
*dev
,
13831 struct drm_atomic_state
*state
,
13834 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13835 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13838 if (intel_state
->modeset
&& nonblock
) {
13839 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13843 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13847 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
13849 ret
= intel_atomic_prepare_commit(dev
, state
, nonblock
);
13851 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13855 drm_atomic_helper_swap_state(state
, true);
13856 dev_priv
->wm
.distrust_bios_wm
= false;
13857 dev_priv
->wm
.skl_results
= intel_state
->wm_results
;
13858 intel_shared_dpll_commit(state
);
13859 intel_atomic_track_fbs(state
);
13862 queue_work(system_unbound_wq
, &state
->commit_work
);
13864 intel_atomic_commit_tail(state
);
13869 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13871 struct drm_device
*dev
= crtc
->dev
;
13872 struct drm_atomic_state
*state
;
13873 struct drm_crtc_state
*crtc_state
;
13876 state
= drm_atomic_state_alloc(dev
);
13878 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13879 crtc
->base
.id
, crtc
->name
);
13883 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13886 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13887 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13889 if (!crtc_state
->active
)
13892 crtc_state
->mode_changed
= true;
13893 ret
= drm_atomic_commit(state
);
13896 if (ret
== -EDEADLK
) {
13897 drm_atomic_state_clear(state
);
13898 drm_modeset_backoff(state
->acquire_ctx
);
13904 drm_atomic_state_free(state
);
13907 #undef for_each_intel_crtc_masked
13910 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13911 * drm_atomic_helper_legacy_gamma_set() directly.
13913 static int intel_atomic_legacy_gamma_set(struct drm_crtc
*crtc
,
13914 u16
*red
, u16
*green
, u16
*blue
,
13917 struct drm_device
*dev
= crtc
->dev
;
13918 struct drm_mode_config
*config
= &dev
->mode_config
;
13919 struct drm_crtc_state
*state
;
13922 ret
= drm_atomic_helper_legacy_gamma_set(crtc
, red
, green
, blue
, size
);
13927 * Make sure we update the legacy properties so this works when
13928 * atomic is not enabled.
13931 state
= crtc
->state
;
13933 drm_object_property_set_value(&crtc
->base
,
13934 config
->degamma_lut_property
,
13935 (state
->degamma_lut
) ?
13936 state
->degamma_lut
->base
.id
: 0);
13938 drm_object_property_set_value(&crtc
->base
,
13939 config
->ctm_property
,
13941 state
->ctm
->base
.id
: 0);
13943 drm_object_property_set_value(&crtc
->base
,
13944 config
->gamma_lut_property
,
13945 (state
->gamma_lut
) ?
13946 state
->gamma_lut
->base
.id
: 0);
13951 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13952 .gamma_set
= intel_atomic_legacy_gamma_set
,
13953 .set_config
= drm_atomic_helper_set_config
,
13954 .set_property
= drm_atomic_helper_crtc_set_property
,
13955 .destroy
= intel_crtc_destroy
,
13956 .page_flip
= intel_crtc_page_flip
,
13957 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13958 .atomic_destroy_state
= intel_crtc_destroy_state
,
13962 * intel_prepare_plane_fb - Prepare fb for usage on plane
13963 * @plane: drm plane to prepare for
13964 * @fb: framebuffer to prepare for presentation
13966 * Prepares a framebuffer for usage on a display plane. Generally this
13967 * involves pinning the underlying object and updating the frontbuffer tracking
13968 * bits. Some older platforms need special physical address handling for
13971 * Must be called with struct_mutex held.
13973 * Returns 0 on success, negative error code on failure.
13976 intel_prepare_plane_fb(struct drm_plane
*plane
,
13977 const struct drm_plane_state
*new_state
)
13979 struct drm_device
*dev
= plane
->dev
;
13980 struct drm_framebuffer
*fb
= new_state
->fb
;
13981 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13982 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13983 struct reservation_object
*resv
;
13986 if (!obj
&& !old_obj
)
13990 struct drm_crtc_state
*crtc_state
=
13991 drm_atomic_get_existing_crtc_state(new_state
->state
, plane
->state
->crtc
);
13993 /* Big Hammer, we also need to ensure that any pending
13994 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13995 * current scanout is retired before unpinning the old
13996 * framebuffer. Note that we rely on userspace rendering
13997 * into the buffer attached to the pipe they are waiting
13998 * on. If not, userspace generates a GPU hang with IPEHR
13999 * point to the MI_WAIT_FOR_EVENT.
14001 * This should only fail upon a hung GPU, in which case we
14002 * can safely continue.
14004 if (needs_modeset(crtc_state
))
14005 ret
= i915_gem_object_wait_rendering(old_obj
, true);
14007 /* GPU hangs should have been swallowed by the wait */
14008 WARN_ON(ret
== -EIO
);
14016 /* For framebuffer backed by dmabuf, wait for fence */
14017 resv
= i915_gem_object_get_dmabuf_resv(obj
);
14021 lret
= reservation_object_wait_timeout_rcu(resv
, false, true,
14022 MAX_SCHEDULE_TIMEOUT
);
14023 if (lret
== -ERESTARTSYS
)
14026 WARN(lret
< 0, "waiting returns %li\n", lret
);
14029 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
14030 INTEL_INFO(dev
)->cursor_needs_physical
) {
14031 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
14032 ret
= i915_gem_object_attach_phys(obj
, align
);
14034 DRM_DEBUG_KMS("failed to attach phys object\n");
14036 ret
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
14040 struct intel_plane_state
*plane_state
=
14041 to_intel_plane_state(new_state
);
14043 i915_gem_request_assign(&plane_state
->wait_req
,
14044 obj
->last_write_req
);
14051 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14052 * @plane: drm plane to clean up for
14053 * @fb: old framebuffer that was on plane
14055 * Cleans up a framebuffer that has just been removed from a plane.
14057 * Must be called with struct_mutex held.
14060 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14061 const struct drm_plane_state
*old_state
)
14063 struct drm_device
*dev
= plane
->dev
;
14064 struct intel_plane_state
*old_intel_state
;
14065 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
14066 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
14068 old_intel_state
= to_intel_plane_state(old_state
);
14070 if (!obj
&& !old_obj
)
14073 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
14074 !INTEL_INFO(dev
)->cursor_needs_physical
))
14075 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
14077 i915_gem_request_assign(&old_intel_state
->wait_req
, NULL
);
14081 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
14084 int crtc_clock
, cdclk
;
14086 if (!intel_crtc
|| !crtc_state
->base
.enable
)
14087 return DRM_PLANE_HELPER_NO_SCALING
;
14089 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14090 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
14092 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
14093 return DRM_PLANE_HELPER_NO_SCALING
;
14096 * skl max scale is lower of:
14097 * close to 3 but not 3, -1 is for that purpose
14101 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
14107 intel_check_primary_plane(struct drm_plane
*plane
,
14108 struct intel_crtc_state
*crtc_state
,
14109 struct intel_plane_state
*state
)
14111 struct drm_crtc
*crtc
= state
->base
.crtc
;
14112 struct drm_framebuffer
*fb
= state
->base
.fb
;
14113 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14114 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14115 bool can_position
= false;
14117 if (INTEL_INFO(plane
->dev
)->gen
>= 9) {
14118 /* use scaler when colorkey is not required */
14119 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
14121 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
14123 can_position
= true;
14126 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14127 &state
->dst
, &state
->clip
,
14128 state
->base
.rotation
,
14129 min_scale
, max_scale
,
14130 can_position
, true,
14134 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
14135 struct drm_crtc_state
*old_crtc_state
)
14137 struct drm_device
*dev
= crtc
->dev
;
14138 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14139 struct intel_crtc_state
*old_intel_state
=
14140 to_intel_crtc_state(old_crtc_state
);
14141 bool modeset
= needs_modeset(crtc
->state
);
14143 /* Perform vblank evasion around commit operation */
14144 intel_pipe_update_start(intel_crtc
);
14149 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14150 intel_color_set_csc(crtc
->state
);
14151 intel_color_load_luts(crtc
->state
);
14154 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
14155 intel_update_pipe_config(intel_crtc
, old_intel_state
);
14156 else if (INTEL_INFO(dev
)->gen
>= 9)
14157 skl_detach_scalers(intel_crtc
);
14160 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
14161 struct drm_crtc_state
*old_crtc_state
)
14163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14165 intel_pipe_update_end(intel_crtc
, NULL
);
14169 * intel_plane_destroy - destroy a plane
14170 * @plane: plane to destroy
14172 * Common destruction function for all types of planes (primary, cursor,
14175 void intel_plane_destroy(struct drm_plane
*plane
)
14180 drm_plane_cleanup(plane
);
14181 kfree(to_intel_plane(plane
));
14184 const struct drm_plane_funcs intel_plane_funcs
= {
14185 .update_plane
= drm_atomic_helper_update_plane
,
14186 .disable_plane
= drm_atomic_helper_disable_plane
,
14187 .destroy
= intel_plane_destroy
,
14188 .set_property
= drm_atomic_helper_plane_set_property
,
14189 .atomic_get_property
= intel_plane_atomic_get_property
,
14190 .atomic_set_property
= intel_plane_atomic_set_property
,
14191 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14192 .atomic_destroy_state
= intel_plane_destroy_state
,
14196 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
14199 struct intel_plane
*primary
= NULL
;
14200 struct intel_plane_state
*state
= NULL
;
14201 const uint32_t *intel_primary_formats
;
14202 unsigned int num_formats
;
14205 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
14209 state
= intel_create_plane_state(&primary
->base
);
14212 primary
->base
.state
= &state
->base
;
14214 primary
->can_scale
= false;
14215 primary
->max_downscale
= 1;
14216 if (INTEL_INFO(dev
)->gen
>= 9) {
14217 primary
->can_scale
= true;
14218 state
->scaler_id
= -1;
14220 primary
->pipe
= pipe
;
14221 primary
->plane
= pipe
;
14222 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
14223 primary
->check_plane
= intel_check_primary_plane
;
14224 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
14225 primary
->plane
= !pipe
;
14227 if (INTEL_INFO(dev
)->gen
>= 9) {
14228 intel_primary_formats
= skl_primary_formats
;
14229 num_formats
= ARRAY_SIZE(skl_primary_formats
);
14231 primary
->update_plane
= skylake_update_primary_plane
;
14232 primary
->disable_plane
= skylake_disable_primary_plane
;
14233 } else if (HAS_PCH_SPLIT(dev
)) {
14234 intel_primary_formats
= i965_primary_formats
;
14235 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14237 primary
->update_plane
= ironlake_update_primary_plane
;
14238 primary
->disable_plane
= i9xx_disable_primary_plane
;
14239 } else if (INTEL_INFO(dev
)->gen
>= 4) {
14240 intel_primary_formats
= i965_primary_formats
;
14241 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14243 primary
->update_plane
= i9xx_update_primary_plane
;
14244 primary
->disable_plane
= i9xx_disable_primary_plane
;
14246 intel_primary_formats
= i8xx_primary_formats
;
14247 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14249 primary
->update_plane
= i9xx_update_primary_plane
;
14250 primary
->disable_plane
= i9xx_disable_primary_plane
;
14253 if (INTEL_INFO(dev
)->gen
>= 9)
14254 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14255 &intel_plane_funcs
,
14256 intel_primary_formats
, num_formats
,
14257 DRM_PLANE_TYPE_PRIMARY
,
14258 "plane 1%c", pipe_name(pipe
));
14259 else if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
14260 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14261 &intel_plane_funcs
,
14262 intel_primary_formats
, num_formats
,
14263 DRM_PLANE_TYPE_PRIMARY
,
14264 "primary %c", pipe_name(pipe
));
14266 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14267 &intel_plane_funcs
,
14268 intel_primary_formats
, num_formats
,
14269 DRM_PLANE_TYPE_PRIMARY
,
14270 "plane %c", plane_name(primary
->plane
));
14274 if (INTEL_INFO(dev
)->gen
>= 4)
14275 intel_create_rotation_property(dev
, primary
);
14277 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
14279 return &primary
->base
;
14288 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
14290 if (!dev
->mode_config
.rotation_property
) {
14291 unsigned long flags
= BIT(DRM_ROTATE_0
) |
14292 BIT(DRM_ROTATE_180
);
14294 if (INTEL_INFO(dev
)->gen
>= 9)
14295 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
14297 dev
->mode_config
.rotation_property
=
14298 drm_mode_create_rotation_property(dev
, flags
);
14300 if (dev
->mode_config
.rotation_property
)
14301 drm_object_attach_property(&plane
->base
.base
,
14302 dev
->mode_config
.rotation_property
,
14303 plane
->base
.state
->rotation
);
14307 intel_check_cursor_plane(struct drm_plane
*plane
,
14308 struct intel_crtc_state
*crtc_state
,
14309 struct intel_plane_state
*state
)
14311 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14312 struct drm_framebuffer
*fb
= state
->base
.fb
;
14313 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14314 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
14318 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14319 &state
->dst
, &state
->clip
,
14320 state
->base
.rotation
,
14321 DRM_PLANE_HELPER_NO_SCALING
,
14322 DRM_PLANE_HELPER_NO_SCALING
,
14323 true, true, &state
->visible
);
14327 /* if we want to turn off the cursor ignore width and height */
14331 /* Check for which cursor types we support */
14332 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14333 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14334 state
->base
.crtc_w
, state
->base
.crtc_h
);
14338 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14339 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14340 DRM_DEBUG_KMS("buffer is too small\n");
14344 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14345 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14350 * There's something wrong with the cursor on CHV pipe C.
14351 * If it straddles the left edge of the screen then
14352 * moving it away from the edge or disabling it often
14353 * results in a pipe underrun, and often that can lead to
14354 * dead pipe (constant underrun reported, and it scans
14355 * out just a solid color). To recover from that, the
14356 * display power well must be turned off and on again.
14357 * Refuse the put the cursor into that compromised position.
14359 if (IS_CHERRYVIEW(plane
->dev
) && pipe
== PIPE_C
&&
14360 state
->visible
&& state
->base
.crtc_x
< 0) {
14361 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14369 intel_disable_cursor_plane(struct drm_plane
*plane
,
14370 struct drm_crtc
*crtc
)
14372 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14374 intel_crtc
->cursor_addr
= 0;
14375 intel_crtc_update_cursor(crtc
, NULL
);
14379 intel_update_cursor_plane(struct drm_plane
*plane
,
14380 const struct intel_crtc_state
*crtc_state
,
14381 const struct intel_plane_state
*state
)
14383 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14385 struct drm_device
*dev
= plane
->dev
;
14386 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14391 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14392 addr
= i915_gem_obj_ggtt_offset(obj
);
14394 addr
= obj
->phys_handle
->busaddr
;
14396 intel_crtc
->cursor_addr
= addr
;
14397 intel_crtc_update_cursor(crtc
, state
);
14400 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14403 struct intel_plane
*cursor
= NULL
;
14404 struct intel_plane_state
*state
= NULL
;
14407 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14411 state
= intel_create_plane_state(&cursor
->base
);
14414 cursor
->base
.state
= &state
->base
;
14416 cursor
->can_scale
= false;
14417 cursor
->max_downscale
= 1;
14418 cursor
->pipe
= pipe
;
14419 cursor
->plane
= pipe
;
14420 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
14421 cursor
->check_plane
= intel_check_cursor_plane
;
14422 cursor
->update_plane
= intel_update_cursor_plane
;
14423 cursor
->disable_plane
= intel_disable_cursor_plane
;
14425 ret
= drm_universal_plane_init(dev
, &cursor
->base
, 0,
14426 &intel_plane_funcs
,
14427 intel_cursor_formats
,
14428 ARRAY_SIZE(intel_cursor_formats
),
14429 DRM_PLANE_TYPE_CURSOR
,
14430 "cursor %c", pipe_name(pipe
));
14434 if (INTEL_INFO(dev
)->gen
>= 4) {
14435 if (!dev
->mode_config
.rotation_property
)
14436 dev
->mode_config
.rotation_property
=
14437 drm_mode_create_rotation_property(dev
,
14438 BIT(DRM_ROTATE_0
) |
14439 BIT(DRM_ROTATE_180
));
14440 if (dev
->mode_config
.rotation_property
)
14441 drm_object_attach_property(&cursor
->base
.base
,
14442 dev
->mode_config
.rotation_property
,
14443 state
->base
.rotation
);
14446 if (INTEL_INFO(dev
)->gen
>=9)
14447 state
->scaler_id
= -1;
14449 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14451 return &cursor
->base
;
14460 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14461 struct intel_crtc_state
*crtc_state
)
14464 struct intel_scaler
*intel_scaler
;
14465 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14467 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14468 intel_scaler
= &scaler_state
->scalers
[i
];
14469 intel_scaler
->in_use
= 0;
14470 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14473 scaler_state
->scaler_id
= -1;
14476 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14478 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14479 struct intel_crtc
*intel_crtc
;
14480 struct intel_crtc_state
*crtc_state
= NULL
;
14481 struct drm_plane
*primary
= NULL
;
14482 struct drm_plane
*cursor
= NULL
;
14485 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14486 if (intel_crtc
== NULL
)
14489 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14492 intel_crtc
->config
= crtc_state
;
14493 intel_crtc
->base
.state
= &crtc_state
->base
;
14494 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14496 /* initialize shared scalers */
14497 if (INTEL_INFO(dev
)->gen
>= 9) {
14498 if (pipe
== PIPE_C
)
14499 intel_crtc
->num_scalers
= 1;
14501 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14503 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14506 primary
= intel_primary_plane_create(dev
, pipe
);
14510 cursor
= intel_cursor_plane_create(dev
, pipe
);
14514 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14515 cursor
, &intel_crtc_funcs
,
14516 "pipe %c", pipe_name(pipe
));
14521 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14522 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14524 intel_crtc
->pipe
= pipe
;
14525 intel_crtc
->plane
= pipe
;
14526 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14527 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14528 intel_crtc
->plane
= !pipe
;
14531 intel_crtc
->cursor_base
= ~0;
14532 intel_crtc
->cursor_cntl
= ~0;
14533 intel_crtc
->cursor_size
= ~0;
14535 intel_crtc
->wm
.cxsr_allowed
= true;
14537 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14538 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14539 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14540 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14542 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14544 intel_color_init(&intel_crtc
->base
);
14546 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14550 intel_plane_destroy(primary
);
14551 intel_plane_destroy(cursor
);
14556 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14558 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14559 struct drm_device
*dev
= connector
->base
.dev
;
14561 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14563 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14564 return INVALID_PIPE
;
14566 return to_intel_crtc(encoder
->crtc
)->pipe
;
14569 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14570 struct drm_file
*file
)
14572 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14573 struct drm_crtc
*drmmode_crtc
;
14574 struct intel_crtc
*crtc
;
14576 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14580 crtc
= to_intel_crtc(drmmode_crtc
);
14581 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14586 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14588 struct drm_device
*dev
= encoder
->base
.dev
;
14589 struct intel_encoder
*source_encoder
;
14590 int index_mask
= 0;
14593 for_each_intel_encoder(dev
, source_encoder
) {
14594 if (encoders_cloneable(encoder
, source_encoder
))
14595 index_mask
|= (1 << entry
);
14603 static bool has_edp_a(struct drm_device
*dev
)
14605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14607 if (!IS_MOBILE(dev
))
14610 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14613 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14619 static bool intel_crt_present(struct drm_device
*dev
)
14621 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14623 if (INTEL_INFO(dev
)->gen
>= 9)
14626 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14629 if (IS_CHERRYVIEW(dev
))
14632 if (HAS_PCH_LPT_H(dev
) && I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14635 /* DDI E can't be used if DDI A requires 4 lanes */
14636 if (HAS_DDI(dev
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14639 if (!dev_priv
->vbt
.int_crt_support
)
14645 static void intel_setup_outputs(struct drm_device
*dev
)
14647 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14648 struct intel_encoder
*encoder
;
14649 bool dpd_is_edp
= false;
14652 * intel_edp_init_connector() depends on this completing first, to
14653 * prevent the registeration of both eDP and LVDS and the incorrect
14654 * sharing of the PPS.
14656 intel_lvds_init(dev
);
14658 if (intel_crt_present(dev
))
14659 intel_crt_init(dev
);
14661 if (IS_BROXTON(dev
)) {
14663 * FIXME: Broxton doesn't support port detection via the
14664 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14665 * detect the ports.
14667 intel_ddi_init(dev
, PORT_A
);
14668 intel_ddi_init(dev
, PORT_B
);
14669 intel_ddi_init(dev
, PORT_C
);
14671 intel_dsi_init(dev
);
14672 } else if (HAS_DDI(dev
)) {
14676 * Haswell uses DDI functions to detect digital outputs.
14677 * On SKL pre-D0 the strap isn't connected, so we assume
14680 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14681 /* WaIgnoreDDIAStrap: skl */
14682 if (found
|| IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
14683 intel_ddi_init(dev
, PORT_A
);
14685 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14687 found
= I915_READ(SFUSE_STRAP
);
14689 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14690 intel_ddi_init(dev
, PORT_B
);
14691 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14692 intel_ddi_init(dev
, PORT_C
);
14693 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14694 intel_ddi_init(dev
, PORT_D
);
14696 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14698 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) &&
14699 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14700 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14701 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14702 intel_ddi_init(dev
, PORT_E
);
14704 } else if (HAS_PCH_SPLIT(dev
)) {
14706 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14708 if (has_edp_a(dev
))
14709 intel_dp_init(dev
, DP_A
, PORT_A
);
14711 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14712 /* PCH SDVOB multiplex with HDMIB */
14713 found
= intel_sdvo_init(dev
, PCH_SDVOB
, PORT_B
);
14715 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14716 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14717 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14720 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14721 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14723 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14724 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14726 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14727 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14729 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14730 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14731 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
14732 bool has_edp
, has_port
;
14735 * The DP_DETECTED bit is the latched state of the DDC
14736 * SDA pin at boot. However since eDP doesn't require DDC
14737 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14738 * eDP ports may have been muxed to an alternate function.
14739 * Thus we can't rely on the DP_DETECTED bit alone to detect
14740 * eDP ports. Consult the VBT as well as DP_DETECTED to
14741 * detect eDP ports.
14743 * Sadly the straps seem to be missing sometimes even for HDMI
14744 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14745 * and VBT for the presence of the port. Additionally we can't
14746 * trust the port type the VBT declares as we've seen at least
14747 * HDMI ports that the VBT claim are DP or eDP.
14749 has_edp
= intel_dp_is_edp(dev
, PORT_B
);
14750 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
14751 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
14752 has_edp
&= intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14753 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14754 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14756 has_edp
= intel_dp_is_edp(dev
, PORT_C
);
14757 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
14758 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
14759 has_edp
&= intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14760 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14761 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14763 if (IS_CHERRYVIEW(dev
)) {
14765 * eDP not supported on port D,
14766 * so no need to worry about it
14768 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
14769 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
14770 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14771 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
14772 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14775 intel_dsi_init(dev
);
14776 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14777 bool found
= false;
14779 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14780 DRM_DEBUG_KMS("probing SDVOB\n");
14781 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, PORT_B
);
14782 if (!found
&& IS_G4X(dev
)) {
14783 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14784 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14787 if (!found
&& IS_G4X(dev
))
14788 intel_dp_init(dev
, DP_B
, PORT_B
);
14791 /* Before G4X SDVOC doesn't have its own detect register */
14793 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14794 DRM_DEBUG_KMS("probing SDVOC\n");
14795 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, PORT_C
);
14798 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14801 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14802 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14805 intel_dp_init(dev
, DP_C
, PORT_C
);
14809 (I915_READ(DP_D
) & DP_DETECTED
))
14810 intel_dp_init(dev
, DP_D
, PORT_D
);
14811 } else if (IS_GEN2(dev
))
14812 intel_dvo_init(dev
);
14814 if (SUPPORTS_TV(dev
))
14815 intel_tv_init(dev
);
14817 intel_psr_init(dev
);
14819 for_each_intel_encoder(dev
, encoder
) {
14820 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14821 encoder
->base
.possible_clones
=
14822 intel_encoder_clones(encoder
);
14825 intel_init_pch_refclk(dev
);
14827 drm_helper_move_panel_connectors_to_head(dev
);
14830 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14832 struct drm_device
*dev
= fb
->dev
;
14833 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14835 drm_framebuffer_cleanup(fb
);
14836 mutex_lock(&dev
->struct_mutex
);
14837 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14838 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14839 mutex_unlock(&dev
->struct_mutex
);
14843 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14844 struct drm_file
*file
,
14845 unsigned int *handle
)
14847 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14848 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14850 if (obj
->userptr
.mm
) {
14851 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14855 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14858 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14859 struct drm_file
*file
,
14860 unsigned flags
, unsigned color
,
14861 struct drm_clip_rect
*clips
,
14862 unsigned num_clips
)
14864 struct drm_device
*dev
= fb
->dev
;
14865 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14866 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14868 mutex_lock(&dev
->struct_mutex
);
14869 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14870 mutex_unlock(&dev
->struct_mutex
);
14875 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14876 .destroy
= intel_user_framebuffer_destroy
,
14877 .create_handle
= intel_user_framebuffer_create_handle
,
14878 .dirty
= intel_user_framebuffer_dirty
,
14882 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14883 uint32_t pixel_format
)
14885 u32 gen
= INTEL_INFO(dev
)->gen
;
14888 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
14890 /* "The stride in bytes must not exceed the of the size of 8K
14891 * pixels and 32K bytes."
14893 return min(8192 * cpp
, 32768);
14894 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14896 } else if (gen
>= 4) {
14897 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14901 } else if (gen
>= 3) {
14902 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14907 /* XXX DSPC is limited to 4k tiled */
14912 static int intel_framebuffer_init(struct drm_device
*dev
,
14913 struct intel_framebuffer
*intel_fb
,
14914 struct drm_mode_fb_cmd2
*mode_cmd
,
14915 struct drm_i915_gem_object
*obj
)
14917 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14918 unsigned int aligned_height
;
14920 u32 pitch_limit
, stride_alignment
;
14922 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14924 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14925 /* Enforce that fb modifier and tiling mode match, but only for
14926 * X-tiled. This is needed for FBC. */
14927 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14928 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14929 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14933 if (obj
->tiling_mode
== I915_TILING_X
)
14934 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14935 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14936 DRM_DEBUG("No Y tiling for legacy addfb\n");
14941 /* Passed in modifier sanity checking. */
14942 switch (mode_cmd
->modifier
[0]) {
14943 case I915_FORMAT_MOD_Y_TILED
:
14944 case I915_FORMAT_MOD_Yf_TILED
:
14945 if (INTEL_INFO(dev
)->gen
< 9) {
14946 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14947 mode_cmd
->modifier
[0]);
14950 case DRM_FORMAT_MOD_NONE
:
14951 case I915_FORMAT_MOD_X_TILED
:
14954 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14955 mode_cmd
->modifier
[0]);
14959 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
14960 mode_cmd
->modifier
[0],
14961 mode_cmd
->pixel_format
);
14962 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14963 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14964 mode_cmd
->pitches
[0], stride_alignment
);
14968 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14969 mode_cmd
->pixel_format
);
14970 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14971 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14972 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14973 "tiled" : "linear",
14974 mode_cmd
->pitches
[0], pitch_limit
);
14978 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14979 mode_cmd
->pitches
[0] != obj
->stride
) {
14980 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14981 mode_cmd
->pitches
[0], obj
->stride
);
14985 /* Reject formats not supported by any plane early. */
14986 switch (mode_cmd
->pixel_format
) {
14987 case DRM_FORMAT_C8
:
14988 case DRM_FORMAT_RGB565
:
14989 case DRM_FORMAT_XRGB8888
:
14990 case DRM_FORMAT_ARGB8888
:
14992 case DRM_FORMAT_XRGB1555
:
14993 if (INTEL_INFO(dev
)->gen
> 3) {
14994 DRM_DEBUG("unsupported pixel format: %s\n",
14995 drm_get_format_name(mode_cmd
->pixel_format
));
14999 case DRM_FORMAT_ABGR8888
:
15000 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
15001 INTEL_INFO(dev
)->gen
< 9) {
15002 DRM_DEBUG("unsupported pixel format: %s\n",
15003 drm_get_format_name(mode_cmd
->pixel_format
));
15007 case DRM_FORMAT_XBGR8888
:
15008 case DRM_FORMAT_XRGB2101010
:
15009 case DRM_FORMAT_XBGR2101010
:
15010 if (INTEL_INFO(dev
)->gen
< 4) {
15011 DRM_DEBUG("unsupported pixel format: %s\n",
15012 drm_get_format_name(mode_cmd
->pixel_format
));
15016 case DRM_FORMAT_ABGR2101010
:
15017 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
15018 DRM_DEBUG("unsupported pixel format: %s\n",
15019 drm_get_format_name(mode_cmd
->pixel_format
));
15023 case DRM_FORMAT_YUYV
:
15024 case DRM_FORMAT_UYVY
:
15025 case DRM_FORMAT_YVYU
:
15026 case DRM_FORMAT_VYUY
:
15027 if (INTEL_INFO(dev
)->gen
< 5) {
15028 DRM_DEBUG("unsupported pixel format: %s\n",
15029 drm_get_format_name(mode_cmd
->pixel_format
));
15034 DRM_DEBUG("unsupported pixel format: %s\n",
15035 drm_get_format_name(mode_cmd
->pixel_format
));
15039 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15040 if (mode_cmd
->offsets
[0] != 0)
15043 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
15044 mode_cmd
->pixel_format
,
15045 mode_cmd
->modifier
[0]);
15046 /* FIXME drm helper for size checks (especially planar formats)? */
15047 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
15050 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
15051 intel_fb
->obj
= obj
;
15053 intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
15055 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
15057 DRM_ERROR("framebuffer init failed %d\n", ret
);
15061 intel_fb
->obj
->framebuffer_references
++;
15066 static struct drm_framebuffer
*
15067 intel_user_framebuffer_create(struct drm_device
*dev
,
15068 struct drm_file
*filp
,
15069 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15071 struct drm_framebuffer
*fb
;
15072 struct drm_i915_gem_object
*obj
;
15073 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15075 obj
= to_intel_bo(drm_gem_object_lookup(filp
, mode_cmd
.handles
[0]));
15076 if (&obj
->base
== NULL
)
15077 return ERR_PTR(-ENOENT
);
15079 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
15081 drm_gem_object_unreference_unlocked(&obj
->base
);
15086 #ifndef CONFIG_DRM_FBDEV_EMULATION
15087 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
15092 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15093 .fb_create
= intel_user_framebuffer_create
,
15094 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15095 .atomic_check
= intel_atomic_check
,
15096 .atomic_commit
= intel_atomic_commit
,
15097 .atomic_state_alloc
= intel_atomic_state_alloc
,
15098 .atomic_state_clear
= intel_atomic_state_clear
,
15102 * intel_init_display_hooks - initialize the display modesetting hooks
15103 * @dev_priv: device private
15105 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15107 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
15108 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15109 dev_priv
->display
.get_initial_plane_config
=
15110 skylake_get_initial_plane_config
;
15111 dev_priv
->display
.crtc_compute_clock
=
15112 haswell_crtc_compute_clock
;
15113 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15114 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15115 } else if (HAS_DDI(dev_priv
)) {
15116 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15117 dev_priv
->display
.get_initial_plane_config
=
15118 ironlake_get_initial_plane_config
;
15119 dev_priv
->display
.crtc_compute_clock
=
15120 haswell_crtc_compute_clock
;
15121 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15122 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15123 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15124 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15125 dev_priv
->display
.get_initial_plane_config
=
15126 ironlake_get_initial_plane_config
;
15127 dev_priv
->display
.crtc_compute_clock
=
15128 ironlake_crtc_compute_clock
;
15129 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15130 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15131 } else if (IS_CHERRYVIEW(dev_priv
)) {
15132 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15133 dev_priv
->display
.get_initial_plane_config
=
15134 i9xx_get_initial_plane_config
;
15135 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15136 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15137 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15138 } else if (IS_VALLEYVIEW(dev_priv
)) {
15139 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15140 dev_priv
->display
.get_initial_plane_config
=
15141 i9xx_get_initial_plane_config
;
15142 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15143 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15144 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15145 } else if (IS_G4X(dev_priv
)) {
15146 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15147 dev_priv
->display
.get_initial_plane_config
=
15148 i9xx_get_initial_plane_config
;
15149 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15150 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15151 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15152 } else if (IS_PINEVIEW(dev_priv
)) {
15153 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15154 dev_priv
->display
.get_initial_plane_config
=
15155 i9xx_get_initial_plane_config
;
15156 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15157 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15158 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15159 } else if (!IS_GEN2(dev_priv
)) {
15160 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15161 dev_priv
->display
.get_initial_plane_config
=
15162 i9xx_get_initial_plane_config
;
15163 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15164 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15165 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15167 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15168 dev_priv
->display
.get_initial_plane_config
=
15169 i9xx_get_initial_plane_config
;
15170 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15171 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15172 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15175 /* Returns the core display clock speed */
15176 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
15177 dev_priv
->display
.get_display_clock_speed
=
15178 skylake_get_display_clock_speed
;
15179 else if (IS_BROXTON(dev_priv
))
15180 dev_priv
->display
.get_display_clock_speed
=
15181 broxton_get_display_clock_speed
;
15182 else if (IS_BROADWELL(dev_priv
))
15183 dev_priv
->display
.get_display_clock_speed
=
15184 broadwell_get_display_clock_speed
;
15185 else if (IS_HASWELL(dev_priv
))
15186 dev_priv
->display
.get_display_clock_speed
=
15187 haswell_get_display_clock_speed
;
15188 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15189 dev_priv
->display
.get_display_clock_speed
=
15190 valleyview_get_display_clock_speed
;
15191 else if (IS_GEN5(dev_priv
))
15192 dev_priv
->display
.get_display_clock_speed
=
15193 ilk_get_display_clock_speed
;
15194 else if (IS_I945G(dev_priv
) || IS_BROADWATER(dev_priv
) ||
15195 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
15196 dev_priv
->display
.get_display_clock_speed
=
15197 i945_get_display_clock_speed
;
15198 else if (IS_GM45(dev_priv
))
15199 dev_priv
->display
.get_display_clock_speed
=
15200 gm45_get_display_clock_speed
;
15201 else if (IS_CRESTLINE(dev_priv
))
15202 dev_priv
->display
.get_display_clock_speed
=
15203 i965gm_get_display_clock_speed
;
15204 else if (IS_PINEVIEW(dev_priv
))
15205 dev_priv
->display
.get_display_clock_speed
=
15206 pnv_get_display_clock_speed
;
15207 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
15208 dev_priv
->display
.get_display_clock_speed
=
15209 g33_get_display_clock_speed
;
15210 else if (IS_I915G(dev_priv
))
15211 dev_priv
->display
.get_display_clock_speed
=
15212 i915_get_display_clock_speed
;
15213 else if (IS_I945GM(dev_priv
) || IS_845G(dev_priv
))
15214 dev_priv
->display
.get_display_clock_speed
=
15215 i9xx_misc_get_display_clock_speed
;
15216 else if (IS_I915GM(dev_priv
))
15217 dev_priv
->display
.get_display_clock_speed
=
15218 i915gm_get_display_clock_speed
;
15219 else if (IS_I865G(dev_priv
))
15220 dev_priv
->display
.get_display_clock_speed
=
15221 i865_get_display_clock_speed
;
15222 else if (IS_I85X(dev_priv
))
15223 dev_priv
->display
.get_display_clock_speed
=
15224 i85x_get_display_clock_speed
;
15226 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
15227 dev_priv
->display
.get_display_clock_speed
=
15228 i830_get_display_clock_speed
;
15231 if (IS_GEN5(dev_priv
)) {
15232 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15233 } else if (IS_GEN6(dev_priv
)) {
15234 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15235 } else if (IS_IVYBRIDGE(dev_priv
)) {
15236 /* FIXME: detect B0+ stepping and use auto training */
15237 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15238 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15239 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15242 if (IS_BROADWELL(dev_priv
)) {
15243 dev_priv
->display
.modeset_commit_cdclk
=
15244 broadwell_modeset_commit_cdclk
;
15245 dev_priv
->display
.modeset_calc_cdclk
=
15246 broadwell_modeset_calc_cdclk
;
15247 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15248 dev_priv
->display
.modeset_commit_cdclk
=
15249 valleyview_modeset_commit_cdclk
;
15250 dev_priv
->display
.modeset_calc_cdclk
=
15251 valleyview_modeset_calc_cdclk
;
15252 } else if (IS_BROXTON(dev_priv
)) {
15253 dev_priv
->display
.modeset_commit_cdclk
=
15254 bxt_modeset_commit_cdclk
;
15255 dev_priv
->display
.modeset_calc_cdclk
=
15256 bxt_modeset_calc_cdclk
;
15257 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
15258 dev_priv
->display
.modeset_commit_cdclk
=
15259 skl_modeset_commit_cdclk
;
15260 dev_priv
->display
.modeset_calc_cdclk
=
15261 skl_modeset_calc_cdclk
;
15264 switch (INTEL_INFO(dev_priv
)->gen
) {
15266 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
15270 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
15275 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
15279 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
15282 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15283 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
15286 /* Drop through - unsupported since execlist only. */
15288 /* Default just returns -ENODEV to indicate unsupported */
15289 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
15294 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15295 * resume, or other times. This quirk makes sure that's the case for
15296 * affected systems.
15298 static void quirk_pipea_force(struct drm_device
*dev
)
15300 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15302 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
15303 DRM_INFO("applying pipe a force quirk\n");
15306 static void quirk_pipeb_force(struct drm_device
*dev
)
15308 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15310 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
15311 DRM_INFO("applying pipe b force quirk\n");
15315 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15317 static void quirk_ssc_force_disable(struct drm_device
*dev
)
15319 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15320 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
15321 DRM_INFO("applying lvds SSC disable quirk\n");
15325 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15328 static void quirk_invert_brightness(struct drm_device
*dev
)
15330 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15331 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
15332 DRM_INFO("applying inverted panel brightness quirk\n");
15335 /* Some VBT's incorrectly indicate no backlight is present */
15336 static void quirk_backlight_present(struct drm_device
*dev
)
15338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15339 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
15340 DRM_INFO("applying backlight present quirk\n");
15343 struct intel_quirk
{
15345 int subsystem_vendor
;
15346 int subsystem_device
;
15347 void (*hook
)(struct drm_device
*dev
);
15350 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15351 struct intel_dmi_quirk
{
15352 void (*hook
)(struct drm_device
*dev
);
15353 const struct dmi_system_id (*dmi_id_list
)[];
15356 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
15358 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
15362 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15364 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15366 .callback
= intel_dmi_reverse_brightness
,
15367 .ident
= "NCR Corporation",
15368 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15369 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15372 { } /* terminating entry */
15374 .hook
= quirk_invert_brightness
,
15378 static struct intel_quirk intel_quirks
[] = {
15379 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15380 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15382 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15383 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15385 /* 830 needs to leave pipe A & dpll A up */
15386 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15388 /* 830 needs to leave pipe B & dpll B up */
15389 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15391 /* Lenovo U160 cannot use SSC on LVDS */
15392 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15394 /* Sony Vaio Y cannot use SSC on LVDS */
15395 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15397 /* Acer Aspire 5734Z must invert backlight brightness */
15398 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15400 /* Acer/eMachines G725 */
15401 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15403 /* Acer/eMachines e725 */
15404 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15406 /* Acer/Packard Bell NCL20 */
15407 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15409 /* Acer Aspire 4736Z */
15410 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15412 /* Acer Aspire 5336 */
15413 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15415 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15416 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15418 /* Acer C720 Chromebook (Core i3 4005U) */
15419 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15421 /* Apple Macbook 2,1 (Core 2 T7400) */
15422 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15424 /* Apple Macbook 4,1 */
15425 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
15427 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15428 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15430 /* HP Chromebook 14 (Celeron 2955U) */
15431 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15433 /* Dell Chromebook 11 */
15434 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15436 /* Dell Chromebook 11 (2015 version) */
15437 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
15440 static void intel_init_quirks(struct drm_device
*dev
)
15442 struct pci_dev
*d
= dev
->pdev
;
15445 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15446 struct intel_quirk
*q
= &intel_quirks
[i
];
15448 if (d
->device
== q
->device
&&
15449 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15450 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15451 (d
->subsystem_device
== q
->subsystem_device
||
15452 q
->subsystem_device
== PCI_ANY_ID
))
15455 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15456 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15457 intel_dmi_quirks
[i
].hook(dev
);
15461 /* Disable the VGA plane that we never use */
15462 static void i915_disable_vga(struct drm_device
*dev
)
15464 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15466 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15468 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15469 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15470 outb(SR01
, VGA_SR_INDEX
);
15471 sr1
= inb(VGA_SR_DATA
);
15472 outb(sr1
| 1<<5, VGA_SR_DATA
);
15473 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15476 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15477 POSTING_READ(vga_reg
);
15480 void intel_modeset_init_hw(struct drm_device
*dev
)
15482 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15484 intel_update_cdclk(dev
);
15486 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
15488 intel_init_clock_gating(dev
);
15489 intel_enable_gt_powersave(dev_priv
);
15493 * Calculate what we think the watermarks should be for the state we've read
15494 * out of the hardware and then immediately program those watermarks so that
15495 * we ensure the hardware settings match our internal state.
15497 * We can calculate what we think WM's should be by creating a duplicate of the
15498 * current state (which was constructed during hardware readout) and running it
15499 * through the atomic check code to calculate new watermark values in the
15502 static void sanitize_watermarks(struct drm_device
*dev
)
15504 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15505 struct drm_atomic_state
*state
;
15506 struct drm_crtc
*crtc
;
15507 struct drm_crtc_state
*cstate
;
15508 struct drm_modeset_acquire_ctx ctx
;
15512 /* Only supported on platforms that use atomic watermark design */
15513 if (!dev_priv
->display
.optimize_watermarks
)
15517 * We need to hold connection_mutex before calling duplicate_state so
15518 * that the connector loop is protected.
15520 drm_modeset_acquire_init(&ctx
, 0);
15522 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15523 if (ret
== -EDEADLK
) {
15524 drm_modeset_backoff(&ctx
);
15526 } else if (WARN_ON(ret
)) {
15530 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15531 if (WARN_ON(IS_ERR(state
)))
15535 * Hardware readout is the only time we don't want to calculate
15536 * intermediate watermarks (since we don't trust the current
15539 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
15541 ret
= intel_atomic_check(dev
, state
);
15544 * If we fail here, it means that the hardware appears to be
15545 * programmed in a way that shouldn't be possible, given our
15546 * understanding of watermark requirements. This might mean a
15547 * mistake in the hardware readout code or a mistake in the
15548 * watermark calculations for a given platform. Raise a WARN
15549 * so that this is noticeable.
15551 * If this actually happens, we'll have to just leave the
15552 * BIOS-programmed watermarks untouched and hope for the best.
15554 WARN(true, "Could not determine valid watermarks for inherited state\n");
15558 /* Write calculated watermark values back */
15559 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
15560 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15562 cs
->wm
.need_postvbl_update
= true;
15563 dev_priv
->display
.optimize_watermarks(cs
);
15566 drm_atomic_state_free(state
);
15568 drm_modeset_drop_locks(&ctx
);
15569 drm_modeset_acquire_fini(&ctx
);
15572 void intel_modeset_init(struct drm_device
*dev
)
15574 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15575 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15578 struct intel_crtc
*crtc
;
15580 drm_mode_config_init(dev
);
15582 dev
->mode_config
.min_width
= 0;
15583 dev
->mode_config
.min_height
= 0;
15585 dev
->mode_config
.preferred_depth
= 24;
15586 dev
->mode_config
.prefer_shadow
= 1;
15588 dev
->mode_config
.allow_fb_modifiers
= true;
15590 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15592 intel_init_quirks(dev
);
15594 intel_init_pm(dev
);
15596 if (INTEL_INFO(dev
)->num_pipes
== 0)
15600 * There may be no VBT; and if the BIOS enabled SSC we can
15601 * just keep using it to avoid unnecessary flicker. Whereas if the
15602 * BIOS isn't using it, don't assume it will work even if the VBT
15603 * indicates as much.
15605 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
15606 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15609 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15610 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15611 bios_lvds_use_ssc
? "en" : "dis",
15612 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15613 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15617 if (IS_GEN2(dev
)) {
15618 dev
->mode_config
.max_width
= 2048;
15619 dev
->mode_config
.max_height
= 2048;
15620 } else if (IS_GEN3(dev
)) {
15621 dev
->mode_config
.max_width
= 4096;
15622 dev
->mode_config
.max_height
= 4096;
15624 dev
->mode_config
.max_width
= 8192;
15625 dev
->mode_config
.max_height
= 8192;
15628 if (IS_845G(dev
) || IS_I865G(dev
)) {
15629 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15630 dev
->mode_config
.cursor_height
= 1023;
15631 } else if (IS_GEN2(dev
)) {
15632 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15633 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15635 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15636 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15639 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
15641 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15642 INTEL_INFO(dev
)->num_pipes
,
15643 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15645 for_each_pipe(dev_priv
, pipe
) {
15646 intel_crtc_init(dev
, pipe
);
15647 for_each_sprite(dev_priv
, pipe
, sprite
) {
15648 ret
= intel_plane_init(dev
, pipe
, sprite
);
15650 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15651 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15655 intel_update_czclk(dev_priv
);
15656 intel_update_cdclk(dev
);
15658 intel_shared_dpll_init(dev
);
15660 if (dev_priv
->max_cdclk_freq
== 0)
15661 intel_update_max_cdclk(dev
);
15663 /* Just disable it once at startup */
15664 i915_disable_vga(dev
);
15665 intel_setup_outputs(dev
);
15667 drm_modeset_lock_all(dev
);
15668 intel_modeset_setup_hw_state(dev
);
15669 drm_modeset_unlock_all(dev
);
15671 for_each_intel_crtc(dev
, crtc
) {
15672 struct intel_initial_plane_config plane_config
= {};
15678 * Note that reserving the BIOS fb up front prevents us
15679 * from stuffing other stolen allocations like the ring
15680 * on top. This prevents some ugliness at boot time, and
15681 * can even allow for smooth boot transitions if the BIOS
15682 * fb is large enough for the active pipe configuration.
15684 dev_priv
->display
.get_initial_plane_config(crtc
,
15688 * If the fb is shared between multiple heads, we'll
15689 * just get the first one.
15691 intel_find_initial_plane_obj(crtc
, &plane_config
);
15695 * Make sure hardware watermarks really match the state we read out.
15696 * Note that we need to do this after reconstructing the BIOS fb's
15697 * since the watermark calculation done here will use pstate->fb.
15699 sanitize_watermarks(dev
);
15702 static void intel_enable_pipe_a(struct drm_device
*dev
)
15704 struct intel_connector
*connector
;
15705 struct drm_connector
*crt
= NULL
;
15706 struct intel_load_detect_pipe load_detect_temp
;
15707 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15709 /* We can't just switch on the pipe A, we need to set things up with a
15710 * proper mode and output configuration. As a gross hack, enable pipe A
15711 * by enabling the load detect pipe once. */
15712 for_each_intel_connector(dev
, connector
) {
15713 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15714 crt
= &connector
->base
;
15722 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15723 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15727 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15729 struct drm_device
*dev
= crtc
->base
.dev
;
15730 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15733 if (INTEL_INFO(dev
)->num_pipes
== 1)
15736 val
= I915_READ(DSPCNTR(!crtc
->plane
));
15738 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15739 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15745 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15747 struct drm_device
*dev
= crtc
->base
.dev
;
15748 struct intel_encoder
*encoder
;
15750 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15756 static bool intel_encoder_has_connectors(struct intel_encoder
*encoder
)
15758 struct drm_device
*dev
= encoder
->base
.dev
;
15759 struct intel_connector
*connector
;
15761 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15767 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15769 struct drm_device
*dev
= crtc
->base
.dev
;
15770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15771 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
15773 /* Clear any frame start delays used for debugging left by the BIOS */
15774 if (!transcoder_is_dsi(cpu_transcoder
)) {
15775 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15778 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15781 /* restore vblank interrupts to correct state */
15782 drm_crtc_vblank_reset(&crtc
->base
);
15783 if (crtc
->active
) {
15784 struct intel_plane
*plane
;
15786 drm_crtc_vblank_on(&crtc
->base
);
15788 /* Disable everything but the primary plane */
15789 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15790 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15793 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15797 /* We need to sanitize the plane -> pipe mapping first because this will
15798 * disable the crtc (and hence change the state) if it is wrong. Note
15799 * that gen4+ has a fixed plane -> pipe mapping. */
15800 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15803 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15804 crtc
->base
.base
.id
, crtc
->base
.name
);
15806 /* Pipe has the wrong plane attached and the plane is active.
15807 * Temporarily change the plane mapping and disable everything
15809 plane
= crtc
->plane
;
15810 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15811 crtc
->plane
= !plane
;
15812 intel_crtc_disable_noatomic(&crtc
->base
);
15813 crtc
->plane
= plane
;
15816 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15817 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15818 /* BIOS forgot to enable pipe A, this mostly happens after
15819 * resume. Force-enable the pipe to fix this, the update_dpms
15820 * call below we restore the pipe to the right state, but leave
15821 * the required bits on. */
15822 intel_enable_pipe_a(dev
);
15825 /* Adjust the state of the output pipe according to whether we
15826 * have active connectors/encoders. */
15827 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
15828 intel_crtc_disable_noatomic(&crtc
->base
);
15830 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15832 * We start out with underrun reporting disabled to avoid races.
15833 * For correct bookkeeping mark this on active crtcs.
15835 * Also on gmch platforms we dont have any hardware bits to
15836 * disable the underrun reporting. Which means we need to start
15837 * out with underrun reporting disabled also on inactive pipes,
15838 * since otherwise we'll complain about the garbage we read when
15839 * e.g. coming up after runtime pm.
15841 * No protection against concurrent access is required - at
15842 * worst a fifo underrun happens which also sets this to false.
15844 crtc
->cpu_fifo_underrun_disabled
= true;
15845 crtc
->pch_fifo_underrun_disabled
= true;
15849 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15851 struct intel_connector
*connector
;
15852 struct drm_device
*dev
= encoder
->base
.dev
;
15854 /* We need to check both for a crtc link (meaning that the
15855 * encoder is active and trying to read from a pipe) and the
15856 * pipe itself being active. */
15857 bool has_active_crtc
= encoder
->base
.crtc
&&
15858 to_intel_crtc(encoder
->base
.crtc
)->active
;
15860 if (intel_encoder_has_connectors(encoder
) && !has_active_crtc
) {
15861 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15862 encoder
->base
.base
.id
,
15863 encoder
->base
.name
);
15865 /* Connector is active, but has no active pipe. This is
15866 * fallout from our resume register restoring. Disable
15867 * the encoder manually again. */
15868 if (encoder
->base
.crtc
) {
15869 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15870 encoder
->base
.base
.id
,
15871 encoder
->base
.name
);
15872 encoder
->disable(encoder
);
15873 if (encoder
->post_disable
)
15874 encoder
->post_disable(encoder
);
15876 encoder
->base
.crtc
= NULL
;
15878 /* Inconsistent output/port/pipe state happens presumably due to
15879 * a bug in one of the get_hw_state functions. Or someplace else
15880 * in our code, like the register restore mess on resume. Clamp
15881 * things to off as a safer default. */
15882 for_each_intel_connector(dev
, connector
) {
15883 if (connector
->encoder
!= encoder
)
15885 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15886 connector
->base
.encoder
= NULL
;
15889 /* Enabled encoders without active connectors will be fixed in
15890 * the crtc fixup. */
15893 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15895 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15896 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15898 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15899 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15900 i915_disable_vga(dev
);
15904 void i915_redisable_vga(struct drm_device
*dev
)
15906 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15908 /* This function can be called both from intel_modeset_setup_hw_state or
15909 * at a very early point in our resume sequence, where the power well
15910 * structures are not yet restored. Since this function is at a very
15911 * paranoid "someone might have enabled VGA while we were not looking"
15912 * level, just check if the power well is enabled instead of trying to
15913 * follow the "don't touch the power well if we don't need it" policy
15914 * the rest of the driver uses. */
15915 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15918 i915_redisable_vga_power_on(dev
);
15920 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
15923 static bool primary_get_hw_state(struct intel_plane
*plane
)
15925 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15927 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15930 /* FIXME read out full plane state for all planes */
15931 static void readout_plane_state(struct intel_crtc
*crtc
)
15933 struct drm_plane
*primary
= crtc
->base
.primary
;
15934 struct intel_plane_state
*plane_state
=
15935 to_intel_plane_state(primary
->state
);
15937 plane_state
->visible
= crtc
->active
&&
15938 primary_get_hw_state(to_intel_plane(primary
));
15940 if (plane_state
->visible
)
15941 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15944 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15948 struct intel_crtc
*crtc
;
15949 struct intel_encoder
*encoder
;
15950 struct intel_connector
*connector
;
15953 dev_priv
->active_crtcs
= 0;
15955 for_each_intel_crtc(dev
, crtc
) {
15956 struct intel_crtc_state
*crtc_state
= crtc
->config
;
15959 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
15960 memset(crtc_state
, 0, sizeof(*crtc_state
));
15961 crtc_state
->base
.crtc
= &crtc
->base
;
15963 crtc_state
->base
.active
= crtc_state
->base
.enable
=
15964 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
15966 crtc
->base
.enabled
= crtc_state
->base
.enable
;
15967 crtc
->active
= crtc_state
->base
.active
;
15969 if (crtc_state
->base
.active
) {
15970 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
15972 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
15973 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
15974 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15975 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
15977 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15979 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15980 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
15981 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15984 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15986 readout_plane_state(crtc
);
15988 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15989 crtc
->base
.base
.id
, crtc
->base
.name
,
15990 crtc
->active
? "enabled" : "disabled");
15993 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15994 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15996 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
15997 &pll
->config
.hw_state
);
15998 pll
->config
.crtc_mask
= 0;
15999 for_each_intel_crtc(dev
, crtc
) {
16000 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
16001 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
16003 pll
->active_mask
= pll
->config
.crtc_mask
;
16005 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16006 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
16009 for_each_intel_encoder(dev
, encoder
) {
16012 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16013 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
16014 encoder
->base
.crtc
= &crtc
->base
;
16015 crtc
->config
->output_types
|= 1 << encoder
->type
;
16016 encoder
->get_config(encoder
, crtc
->config
);
16018 encoder
->base
.crtc
= NULL
;
16021 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16022 encoder
->base
.base
.id
,
16023 encoder
->base
.name
,
16024 encoder
->base
.crtc
? "enabled" : "disabled",
16028 for_each_intel_connector(dev
, connector
) {
16029 if (connector
->get_hw_state(connector
)) {
16030 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16032 encoder
= connector
->encoder
;
16033 connector
->base
.encoder
= &encoder
->base
;
16035 if (encoder
->base
.crtc
&&
16036 encoder
->base
.crtc
->state
->active
) {
16038 * This has to be done during hardware readout
16039 * because anything calling .crtc_disable may
16040 * rely on the connector_mask being accurate.
16042 encoder
->base
.crtc
->state
->connector_mask
|=
16043 1 << drm_connector_index(&connector
->base
);
16044 encoder
->base
.crtc
->state
->encoder_mask
|=
16045 1 << drm_encoder_index(&encoder
->base
);
16049 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16050 connector
->base
.encoder
= NULL
;
16052 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16053 connector
->base
.base
.id
,
16054 connector
->base
.name
,
16055 connector
->base
.encoder
? "enabled" : "disabled");
16058 for_each_intel_crtc(dev
, crtc
) {
16059 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
16061 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16062 if (crtc
->base
.state
->active
) {
16063 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
16064 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
16065 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16068 * The initial mode needs to be set in order to keep
16069 * the atomic core happy. It wants a valid mode if the
16070 * crtc's enabled, so we do the above call.
16072 * At this point some state updated by the connectors
16073 * in their ->detect() callback has not run yet, so
16074 * no recalculation can be done yet.
16076 * Even if we could do a recalculation and modeset
16077 * right now it would cause a double modeset if
16078 * fbdev or userspace chooses a different initial mode.
16080 * If that happens, someone indicated they wanted a
16081 * mode change, which means it's safe to do a full
16084 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16086 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
16087 update_scanline_offset(crtc
);
16090 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
16094 /* Scan out the current hw modeset state,
16095 * and sanitizes it to the current state
16098 intel_modeset_setup_hw_state(struct drm_device
*dev
)
16100 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16102 struct intel_crtc
*crtc
;
16103 struct intel_encoder
*encoder
;
16106 intel_modeset_readout_hw_state(dev
);
16108 /* HW state is read out, now we need to sanitize this mess. */
16109 for_each_intel_encoder(dev
, encoder
) {
16110 intel_sanitize_encoder(encoder
);
16113 for_each_pipe(dev_priv
, pipe
) {
16114 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
16115 intel_sanitize_crtc(crtc
);
16116 intel_dump_pipe_config(crtc
, crtc
->config
,
16117 "[setup_hw_state]");
16120 intel_modeset_update_connector_atomic_state(dev
);
16122 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16123 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16125 if (!pll
->on
|| pll
->active_mask
)
16128 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
16130 pll
->funcs
.disable(dev_priv
, pll
);
16134 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
16135 vlv_wm_get_hw_state(dev
);
16136 else if (IS_GEN9(dev
))
16137 skl_wm_get_hw_state(dev
);
16138 else if (HAS_PCH_SPLIT(dev
))
16139 ilk_wm_get_hw_state(dev
);
16141 for_each_intel_crtc(dev
, crtc
) {
16142 unsigned long put_domains
;
16144 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
16145 if (WARN_ON(put_domains
))
16146 modeset_put_power_domains(dev_priv
, put_domains
);
16148 intel_display_set_init_power(dev_priv
, false);
16150 intel_fbc_init_pipe_state(dev_priv
);
16153 void intel_display_resume(struct drm_device
*dev
)
16155 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16156 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16157 struct drm_modeset_acquire_ctx ctx
;
16159 bool setup
= false;
16161 dev_priv
->modeset_restore_state
= NULL
;
16164 * This is a cludge because with real atomic modeset mode_config.mutex
16165 * won't be taken. Unfortunately some probed state like
16166 * audio_codec_enable is still protected by mode_config.mutex, so lock
16169 mutex_lock(&dev
->mode_config
.mutex
);
16170 drm_modeset_acquire_init(&ctx
, 0);
16173 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16175 if (ret
== 0 && !setup
) {
16178 intel_modeset_setup_hw_state(dev
);
16179 i915_redisable_vga(dev
);
16182 if (ret
== 0 && state
) {
16183 struct drm_crtc_state
*crtc_state
;
16184 struct drm_crtc
*crtc
;
16187 state
->acquire_ctx
= &ctx
;
16189 /* ignore any reset values/BIOS leftovers in the WM registers */
16190 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
16192 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
16194 * Force recalculation even if we restore
16195 * current state. With fast modeset this may not result
16196 * in a modeset when the state is compatible.
16198 crtc_state
->mode_changed
= true;
16201 ret
= drm_atomic_commit(state
);
16204 if (ret
== -EDEADLK
) {
16205 drm_modeset_backoff(&ctx
);
16209 drm_modeset_drop_locks(&ctx
);
16210 drm_modeset_acquire_fini(&ctx
);
16211 mutex_unlock(&dev
->mode_config
.mutex
);
16214 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16215 drm_atomic_state_free(state
);
16219 void intel_modeset_gem_init(struct drm_device
*dev
)
16221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16222 struct drm_crtc
*c
;
16223 struct drm_i915_gem_object
*obj
;
16226 intel_init_gt_powersave(dev_priv
);
16228 intel_modeset_init_hw(dev
);
16230 intel_setup_overlay(dev_priv
);
16233 * Make sure any fbs we allocated at startup are properly
16234 * pinned & fenced. When we do the allocation it's too early
16237 for_each_crtc(dev
, c
) {
16238 obj
= intel_fb_obj(c
->primary
->fb
);
16242 mutex_lock(&dev
->struct_mutex
);
16243 ret
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
16244 c
->primary
->state
->rotation
);
16245 mutex_unlock(&dev
->struct_mutex
);
16247 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16248 to_intel_crtc(c
)->pipe
);
16249 drm_framebuffer_unreference(c
->primary
->fb
);
16250 c
->primary
->fb
= NULL
;
16251 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
16252 update_state_fb(c
->primary
);
16253 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
16258 int intel_connector_register(struct drm_connector
*connector
)
16260 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
16263 ret
= intel_backlight_device_register(intel_connector
);
16273 void intel_connector_unregister(struct drm_connector
*connector
)
16275 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
16277 intel_backlight_device_unregister(intel_connector
);
16278 intel_panel_destroy_backlight(connector
);
16281 void intel_modeset_cleanup(struct drm_device
*dev
)
16283 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16285 intel_disable_gt_powersave(dev_priv
);
16288 * Interrupts and polling as the first thing to avoid creating havoc.
16289 * Too much stuff here (turning of connectors, ...) would
16290 * experience fancy races otherwise.
16292 intel_irq_uninstall(dev_priv
);
16295 * Due to the hpd irq storm handling the hotplug work can re-arm the
16296 * poll handlers. Hence disable polling after hpd handling is shut down.
16298 drm_kms_helper_poll_fini(dev
);
16300 intel_unregister_dsm_handler();
16302 intel_fbc_global_disable(dev_priv
);
16304 /* flush any delayed tasks or pending work */
16305 flush_scheduled_work();
16307 drm_mode_config_cleanup(dev
);
16309 intel_cleanup_overlay(dev_priv
);
16311 intel_cleanup_gt_powersave(dev_priv
);
16313 intel_teardown_gmbus(dev
);
16316 void intel_connector_attach_encoder(struct intel_connector
*connector
,
16317 struct intel_encoder
*encoder
)
16319 connector
->encoder
= encoder
;
16320 drm_mode_connector_attach_encoder(&connector
->base
,
16325 * set vga decode state - true == enable VGA decode
16327 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
16329 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16330 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16333 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16334 DRM_ERROR("failed to read control word\n");
16338 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16342 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16344 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16346 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16347 DRM_ERROR("failed to write control word\n");
16354 struct intel_display_error_state
{
16356 u32 power_well_driver
;
16358 int num_transcoders
;
16360 struct intel_cursor_error_state
{
16365 } cursor
[I915_MAX_PIPES
];
16367 struct intel_pipe_error_state
{
16368 bool power_domain_on
;
16371 } pipe
[I915_MAX_PIPES
];
16373 struct intel_plane_error_state
{
16381 } plane
[I915_MAX_PIPES
];
16383 struct intel_transcoder_error_state
{
16384 bool power_domain_on
;
16385 enum transcoder cpu_transcoder
;
16398 struct intel_display_error_state
*
16399 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16401 struct intel_display_error_state
*error
;
16402 int transcoders
[] = {
16410 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16413 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16417 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16418 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
16420 for_each_pipe(dev_priv
, i
) {
16421 error
->pipe
[i
].power_domain_on
=
16422 __intel_display_power_is_enabled(dev_priv
,
16423 POWER_DOMAIN_PIPE(i
));
16424 if (!error
->pipe
[i
].power_domain_on
)
16427 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16428 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16429 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16431 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16432 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16433 if (INTEL_GEN(dev_priv
) <= 3) {
16434 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16435 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16437 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16438 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16439 if (INTEL_GEN(dev_priv
) >= 4) {
16440 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16441 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16444 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16446 if (HAS_GMCH_DISPLAY(dev_priv
))
16447 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16450 /* Note: this does not include DSI transcoders. */
16451 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
16452 if (HAS_DDI(dev_priv
))
16453 error
->num_transcoders
++; /* Account for eDP. */
16455 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16456 enum transcoder cpu_transcoder
= transcoders
[i
];
16458 error
->transcoder
[i
].power_domain_on
=
16459 __intel_display_power_is_enabled(dev_priv
,
16460 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16461 if (!error
->transcoder
[i
].power_domain_on
)
16464 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16466 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16467 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16468 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16469 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16470 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16471 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16472 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16478 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16481 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16482 struct drm_device
*dev
,
16483 struct intel_display_error_state
*error
)
16485 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16491 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
16492 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16493 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16494 error
->power_well_driver
);
16495 for_each_pipe(dev_priv
, i
) {
16496 err_printf(m
, "Pipe [%d]:\n", i
);
16497 err_printf(m
, " Power: %s\n",
16498 onoff(error
->pipe
[i
].power_domain_on
));
16499 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16500 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16502 err_printf(m
, "Plane [%d]:\n", i
);
16503 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16504 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16505 if (INTEL_INFO(dev
)->gen
<= 3) {
16506 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16507 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16509 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16510 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16511 if (INTEL_INFO(dev
)->gen
>= 4) {
16512 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16513 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16516 err_printf(m
, "Cursor [%d]:\n", i
);
16517 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16518 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16519 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16522 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16523 err_printf(m
, "CPU transcoder: %s\n",
16524 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16525 err_printf(m
, " Power: %s\n",
16526 onoff(error
->transcoder
[i
].power_domain_on
));
16527 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16528 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16529 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16530 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16531 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16532 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16533 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);