projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drm-vc4-next-2016-02-17' of github.com:anholt/linux into drm-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152 {
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170 }
171
172 int
173 intel_pch_rawclk(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176
177 WARN_ON(!HAS_PCH_SPLIT(dev));
178
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180 }
181
182 /* hrawclock is 1/4 the FSB frequency */
183 int intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
190 return 200;
191
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
194 case CLKCFG_FSB_400:
195 return 100;
196 case CLKCFG_FSB_533:
197 return 133;
198 case CLKCFG_FSB_667:
199 return 166;
200 case CLKCFG_FSB_800:
201 return 200;
202 case CLKCFG_FSB_1067:
203 return 266;
204 case CLKCFG_FSB_1333:
205 return 333;
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
209 return 400;
210 default:
211 return 133;
212 }
213 }
214
215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 {
217 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
218 return;
219
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221 CCK_CZ_CLOCK_CONTROL);
222
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224 }
225
226 static inline u32 /* units of 100MHz */
227 intel_fdi_link_freq(struct drm_device *dev)
228 {
229 if (IS_GEN5(dev)) {
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232 } else
233 return 27;
234 }
235
236 static const intel_limit_t intel_limits_i8xx_dac = {
237 .dot = { .min = 25000, .max = 350000 },
238 .vco = { .min = 908000, .max = 1512000 },
239 .n = { .min = 2, .max = 16 },
240 .m = { .min = 96, .max = 140 },
241 .m1 = { .min = 18, .max = 26 },
242 .m2 = { .min = 6, .max = 16 },
243 .p = { .min = 4, .max = 128 },
244 .p1 = { .min = 2, .max = 33 },
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 4, .p2_fast = 2 },
247 };
248
249 static const intel_limit_t intel_limits_i8xx_dvo = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 908000, .max = 1512000 },
252 .n = { .min = 2, .max = 16 },
253 .m = { .min = 96, .max = 140 },
254 .m1 = { .min = 18, .max = 26 },
255 .m2 = { .min = 6, .max = 16 },
256 .p = { .min = 4, .max = 128 },
257 .p1 = { .min = 2, .max = 33 },
258 .p2 = { .dot_limit = 165000,
259 .p2_slow = 4, .p2_fast = 4 },
260 };
261
262 static const intel_limit_t intel_limits_i8xx_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 1, .max = 6 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 14, .p2_fast = 7 },
273 };
274
275 static const intel_limit_t intel_limits_i9xx_sdvo = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1400000, .max = 2800000 },
278 .n = { .min = 1, .max = 6 },
279 .m = { .min = 70, .max = 120 },
280 .m1 = { .min = 8, .max = 18 },
281 .m2 = { .min = 3, .max = 7 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_i9xx_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1400000, .max = 2800000 },
291 .n = { .min = 1, .max = 6 },
292 .m = { .min = 70, .max = 120 },
293 .m1 = { .min = 8, .max = 18 },
294 .m2 = { .min = 3, .max = 7 },
295 .p = { .min = 7, .max = 98 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301
302 static const intel_limit_t intel_limits_g4x_sdvo = {
303 .dot = { .min = 25000, .max = 270000 },
304 .vco = { .min = 1750000, .max = 3500000},
305 .n = { .min = 1, .max = 4 },
306 .m = { .min = 104, .max = 138 },
307 .m1 = { .min = 17, .max = 23 },
308 .m2 = { .min = 5, .max = 11 },
309 .p = { .min = 10, .max = 30 },
310 .p1 = { .min = 1, .max = 3},
311 .p2 = { .dot_limit = 270000,
312 .p2_slow = 10,
313 .p2_fast = 10
314 },
315 };
316
317 static const intel_limit_t intel_limits_g4x_hdmi = {
318 .dot = { .min = 22000, .max = 400000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 16, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 5, .max = 80 },
325 .p1 = { .min = 1, .max = 8},
326 .p2 = { .dot_limit = 165000,
327 .p2_slow = 10, .p2_fast = 5 },
328 };
329
330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331 .dot = { .min = 20000, .max = 115000 },
332 .vco = { .min = 1750000, .max = 3500000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 104, .max = 138 },
335 .m1 = { .min = 17, .max = 23 },
336 .m2 = { .min = 5, .max = 11 },
337 .p = { .min = 28, .max = 112 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 0,
340 .p2_slow = 14, .p2_fast = 14
341 },
342 };
343
344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345 .dot = { .min = 80000, .max = 224000 },
346 .vco = { .min = 1750000, .max = 3500000 },
347 .n = { .min = 1, .max = 3 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 17, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 14, .max = 42 },
352 .p1 = { .min = 2, .max = 6 },
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 7, .p2_fast = 7
355 },
356 };
357
358 static const intel_limit_t intel_limits_pineview_sdvo = {
359 .dot = { .min = 20000, .max = 400000},
360 .vco = { .min = 1700000, .max = 3500000 },
361 /* Pineview's Ncounter is a ring counter */
362 .n = { .min = 3, .max = 6 },
363 .m = { .min = 2, .max = 256 },
364 /* Pineview only has one combined m divider, which we treat as m2. */
365 .m1 = { .min = 0, .max = 0 },
366 .m2 = { .min = 0, .max = 254 },
367 .p = { .min = 5, .max = 80 },
368 .p1 = { .min = 1, .max = 8 },
369 .p2 = { .dot_limit = 200000,
370 .p2_slow = 10, .p2_fast = 5 },
371 };
372
373 static const intel_limit_t intel_limits_pineview_lvds = {
374 .dot = { .min = 20000, .max = 400000 },
375 .vco = { .min = 1700000, .max = 3500000 },
376 .n = { .min = 3, .max = 6 },
377 .m = { .min = 2, .max = 256 },
378 .m1 = { .min = 0, .max = 0 },
379 .m2 = { .min = 0, .max = 254 },
380 .p = { .min = 7, .max = 112 },
381 .p1 = { .min = 1, .max = 8 },
382 .p2 = { .dot_limit = 112000,
383 .p2_slow = 14, .p2_fast = 14 },
384 };
385
386 /* Ironlake / Sandybridge
387 *
388 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389 * the range value for them is (actual_value - 2).
390 */
391 static const intel_limit_t intel_limits_ironlake_dac = {
392 .dot = { .min = 25000, .max = 350000 },
393 .vco = { .min = 1760000, .max = 3510000 },
394 .n = { .min = 1, .max = 5 },
395 .m = { .min = 79, .max = 127 },
396 .m1 = { .min = 12, .max = 22 },
397 .m2 = { .min = 5, .max = 9 },
398 .p = { .min = 5, .max = 80 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 225000,
401 .p2_slow = 10, .p2_fast = 5 },
402 };
403
404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
405 .dot = { .min = 25000, .max = 350000 },
406 .vco = { .min = 1760000, .max = 3510000 },
407 .n = { .min = 1, .max = 3 },
408 .m = { .min = 79, .max = 118 },
409 .m1 = { .min = 12, .max = 22 },
410 .m2 = { .min = 5, .max = 9 },
411 .p = { .min = 28, .max = 112 },
412 .p1 = { .min = 2, .max = 8 },
413 .p2 = { .dot_limit = 225000,
414 .p2_slow = 14, .p2_fast = 14 },
415 };
416
417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 3 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 14, .max = 56 },
425 .p1 = { .min = 2, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 7, .p2_fast = 7 },
428 };
429
430 /* LVDS 100mhz refclk limits. */
431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 2 },
435 .m = { .min = 79, .max = 126 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 126 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 42 },
452 .p1 = { .min = 2, .max = 6 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 static const intel_limit_t intel_limits_vlv = {
458 /*
459 * These are the data rate limits (measured in fast clocks)
460 * since those are the strictest limits we have. The fast
461 * clock and actual rate limits are more relaxed, so checking
462 * them would make no difference.
463 */
464 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
465 .vco = { .min = 4000000, .max = 6000000 },
466 .n = { .min = 1, .max = 7 },
467 .m1 = { .min = 2, .max = 3 },
468 .m2 = { .min = 11, .max = 156 },
469 .p1 = { .min = 2, .max = 3 },
470 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
471 };
472
473 static const intel_limit_t intel_limits_chv = {
474 /*
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
479 */
480 .dot = { .min = 25000 * 5, .max = 540000 * 5},
481 .vco = { .min = 4800000, .max = 6480000 },
482 .n = { .min = 1, .max = 1 },
483 .m1 = { .min = 2, .max = 2 },
484 .m2 = { .min = 24 << 22, .max = 175 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 14 },
487 };
488
489 static const intel_limit_t intel_limits_bxt = {
490 /* FIXME: find real dot limits */
491 .dot = { .min = 0, .max = INT_MAX },
492 .vco = { .min = 4800000, .max = 6700000 },
493 .n = { .min = 1, .max = 1 },
494 .m1 = { .min = 2, .max = 2 },
495 /* FIXME: find real m2 limits */
496 .m2 = { .min = 2 << 22, .max = 255 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 20 },
499 };
500
501 static bool
502 needs_modeset(struct drm_crtc_state *state)
503 {
504 return drm_atomic_crtc_needs_modeset(state);
505 }
506
507 /**
508 * Returns whether any output on the specified pipe is of the specified type
509 */
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 {
512 struct drm_device *dev = crtc->base.dev;
513 struct intel_encoder *encoder;
514
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
516 if (encoder->type == type)
517 return true;
518
519 return false;
520 }
521
522 /**
523 * Returns whether any output on the specified pipe will have the specified
524 * type after a staged modeset is complete, i.e., the same as
525 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526 * encoder->crtc.
527 */
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529 int type)
530 {
531 struct drm_atomic_state *state = crtc_state->base.state;
532 struct drm_connector *connector;
533 struct drm_connector_state *connector_state;
534 struct intel_encoder *encoder;
535 int i, num_connectors = 0;
536
537 for_each_connector_in_state(state, connector, connector_state, i) {
538 if (connector_state->crtc != crtc_state->base.crtc)
539 continue;
540
541 num_connectors++;
542
543 encoder = to_intel_encoder(connector_state->best_encoder);
544 if (encoder->type == type)
545 return true;
546 }
547
548 WARN_ON(num_connectors == 0);
549
550 return false;
551 }
552
553 static const intel_limit_t *
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 {
556 struct drm_device *dev = crtc_state->base.crtc->dev;
557 const intel_limit_t *limit;
558
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
560 if (intel_is_dual_link_lvds(dev)) {
561 if (refclk == 100000)
562 limit = &intel_limits_ironlake_dual_lvds_100m;
563 else
564 limit = &intel_limits_ironlake_dual_lvds;
565 } else {
566 if (refclk == 100000)
567 limit = &intel_limits_ironlake_single_lvds_100m;
568 else
569 limit = &intel_limits_ironlake_single_lvds;
570 }
571 } else
572 limit = &intel_limits_ironlake_dac;
573
574 return limit;
575 }
576
577 static const intel_limit_t *
578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 {
580 struct drm_device *dev = crtc_state->base.crtc->dev;
581 const intel_limit_t *limit;
582
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 if (intel_is_dual_link_lvds(dev))
585 limit = &intel_limits_g4x_dual_channel_lvds;
586 else
587 limit = &intel_limits_g4x_single_channel_lvds;
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
590 limit = &intel_limits_g4x_hdmi;
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
592 limit = &intel_limits_g4x_sdvo;
593 } else /* The option is for other outputs */
594 limit = &intel_limits_i9xx_sdvo;
595
596 return limit;
597 }
598
599 static const intel_limit_t *
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 {
602 struct drm_device *dev = crtc_state->base.crtc->dev;
603 const intel_limit_t *limit;
604
605 if (IS_BROXTON(dev))
606 limit = &intel_limits_bxt;
607 else if (HAS_PCH_SPLIT(dev))
608 limit = intel_ironlake_limit(crtc_state, refclk);
609 else if (IS_G4X(dev)) {
610 limit = intel_g4x_limit(crtc_state);
611 } else if (IS_PINEVIEW(dev)) {
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
613 limit = &intel_limits_pineview_lvds;
614 else
615 limit = &intel_limits_pineview_sdvo;
616 } else if (IS_CHERRYVIEW(dev)) {
617 limit = &intel_limits_chv;
618 } else if (IS_VALLEYVIEW(dev)) {
619 limit = &intel_limits_vlv;
620 } else if (!IS_GEN2(dev)) {
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
622 limit = &intel_limits_i9xx_lvds;
623 else
624 limit = &intel_limits_i9xx_sdvo;
625 } else {
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
627 limit = &intel_limits_i8xx_lvds;
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
629 limit = &intel_limits_i8xx_dvo;
630 else
631 limit = &intel_limits_i8xx_dac;
632 }
633 return limit;
634 }
635
636 /*
637 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640 * The helpers' return value is the rate of the clock that is fed to the
641 * display engine's pipe which can be the above fast dot clock rate or a
642 * divided-down version of it.
643 */
644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 {
647 clock->m = clock->m2 + 2;
648 clock->p = clock->p1 * clock->p2;
649 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 return 0;
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
653
654 return clock->dot;
655 }
656
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 {
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660 }
661
662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 {
664 clock->m = i9xx_dpll_compute_m(clock);
665 clock->p = clock->p1 * clock->p2;
666 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 return 0;
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
670
671 return clock->dot;
672 }
673
674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 {
676 clock->m = clock->m1 * clock->m2;
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot / 5;
684 }
685
686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 {
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->n << 22);
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695
696 return clock->dot / 5;
697 }
698
699 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 /**
701 * Returns whether the given set of divisors are valid for a given refclk with
702 * the given connectors.
703 */
704
705 static bool intel_PLL_is_valid(struct drm_device *dev,
706 const intel_limit_t *limit,
707 const intel_clock_t *clock)
708 {
709 if (clock->n < limit->n.min || limit->n.max < clock->n)
710 INTELPllInvalid("n out of range\n");
711 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
712 INTELPllInvalid("p1 out of range\n");
713 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
714 INTELPllInvalid("m2 out of range\n");
715 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
716 INTELPllInvalid("m1 out of range\n");
717
718 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
719 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
720 if (clock->m1 <= clock->m2)
721 INTELPllInvalid("m1 <= m2\n");
722
723 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
724 if (clock->p < limit->p.min || limit->p.max < clock->p)
725 INTELPllInvalid("p out of range\n");
726 if (clock->m < limit->m.min || limit->m.max < clock->m)
727 INTELPllInvalid("m out of range\n");
728 }
729
730 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
731 INTELPllInvalid("vco out of range\n");
732 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
733 * connector, etc., rather than just a single range.
734 */
735 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
736 INTELPllInvalid("dot out of range\n");
737
738 return true;
739 }
740
741 static int
742 i9xx_select_p2_div(const intel_limit_t *limit,
743 const struct intel_crtc_state *crtc_state,
744 int target)
745 {
746 struct drm_device *dev = crtc_state->base.crtc->dev;
747
748 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
749 /*
750 * For LVDS just rely on its current settings for dual-channel.
751 * We haven't figured out how to reliably set up different
752 * single/dual channel state, if we even can.
753 */
754 if (intel_is_dual_link_lvds(dev))
755 return limit->p2.p2_fast;
756 else
757 return limit->p2.p2_slow;
758 } else {
759 if (target < limit->p2.dot_limit)
760 return limit->p2.p2_slow;
761 else
762 return limit->p2.p2_fast;
763 }
764 }
765
766 static bool
767 i9xx_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc_state->base.crtc->dev;
773 intel_clock_t clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 if (clock.m2 >= clock.m1)
785 break;
786 for (clock.n = limit->n.min;
787 clock.n <= limit->n.max; clock.n++) {
788 for (clock.p1 = limit->p1.min;
789 clock.p1 <= limit->p1.max; clock.p1++) {
790 int this_err;
791
792 i9xx_calc_dpll_params(refclk, &clock);
793 if (!intel_PLL_is_valid(dev, limit,
794 &clock))
795 continue;
796 if (match_clock &&
797 clock.p != match_clock->p)
798 continue;
799
800 this_err = abs(clock.dot - target);
801 if (this_err < err) {
802 *best_clock = clock;
803 err = this_err;
804 }
805 }
806 }
807 }
808 }
809
810 return (err != target);
811 }
812
813 static bool
814 pnv_find_best_dpll(const intel_limit_t *limit,
815 struct intel_crtc_state *crtc_state,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc_state->base.crtc->dev;
820 intel_clock_t clock;
821 int err = target;
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826
827 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
828 clock.m1++) {
829 for (clock.m2 = limit->m2.min;
830 clock.m2 <= limit->m2.max; clock.m2++) {
831 for (clock.n = limit->n.min;
832 clock.n <= limit->n.max; clock.n++) {
833 for (clock.p1 = limit->p1.min;
834 clock.p1 <= limit->p1.max; clock.p1++) {
835 int this_err;
836
837 pnv_calc_dpll_params(refclk, &clock);
838 if (!intel_PLL_is_valid(dev, limit,
839 &clock))
840 continue;
841 if (match_clock &&
842 clock.p != match_clock->p)
843 continue;
844
845 this_err = abs(clock.dot - target);
846 if (this_err < err) {
847 *best_clock = clock;
848 err = this_err;
849 }
850 }
851 }
852 }
853 }
854
855 return (err != target);
856 }
857
858 static bool
859 g4x_find_best_dpll(const intel_limit_t *limit,
860 struct intel_crtc_state *crtc_state,
861 int target, int refclk, intel_clock_t *match_clock,
862 intel_clock_t *best_clock)
863 {
864 struct drm_device *dev = crtc_state->base.crtc->dev;
865 intel_clock_t clock;
866 int max_n;
867 bool found = false;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
874
875 max_n = limit->n.max;
876 /* based on hardware requirement, prefer smaller n to precision */
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
878 /* based on hardware requirement, prefere larger m1,m2 */
879 for (clock.m1 = limit->m1.max;
880 clock.m1 >= limit->m1.min; clock.m1--) {
881 for (clock.m2 = limit->m2.max;
882 clock.m2 >= limit->m2.min; clock.m2--) {
883 for (clock.p1 = limit->p1.max;
884 clock.p1 >= limit->p1.min; clock.p1--) {
885 int this_err;
886
887 i9xx_calc_dpll_params(refclk, &clock);
888 if (!intel_PLL_is_valid(dev, limit,
889 &clock))
890 continue;
891
892 this_err = abs(clock.dot - target);
893 if (this_err < err_most) {
894 *best_clock = clock;
895 err_most = this_err;
896 max_n = clock.n;
897 found = true;
898 }
899 }
900 }
901 }
902 }
903 return found;
904 }
905
906 /*
907 * Check if the calculated PLL configuration is more optimal compared to the
908 * best configuration and error found so far. Return the calculated error.
909 */
910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
911 const intel_clock_t *calculated_clock,
912 const intel_clock_t *best_clock,
913 unsigned int best_error_ppm,
914 unsigned int *error_ppm)
915 {
916 /*
917 * For CHV ignore the error and consider only the P value.
918 * Prefer a bigger P value based on HW requirements.
919 */
920 if (IS_CHERRYVIEW(dev)) {
921 *error_ppm = 0;
922
923 return calculated_clock->p > best_clock->p;
924 }
925
926 if (WARN_ON_ONCE(!target_freq))
927 return false;
928
929 *error_ppm = div_u64(1000000ULL *
930 abs(target_freq - calculated_clock->dot),
931 target_freq);
932 /*
933 * Prefer a better P value over a better (smaller) error if the error
934 * is small. Ensure this preference for future configurations too by
935 * setting the error to 0.
936 */
937 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
938 *error_ppm = 0;
939
940 return true;
941 }
942
943 return *error_ppm + 10 < best_error_ppm;
944 }
945
946 static bool
947 vlv_find_best_dpll(const intel_limit_t *limit,
948 struct intel_crtc_state *crtc_state,
949 int target, int refclk, intel_clock_t *match_clock,
950 intel_clock_t *best_clock)
951 {
952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
953 struct drm_device *dev = crtc->base.dev;
954 intel_clock_t clock;
955 unsigned int bestppm = 1000000;
956 /* min update 19.2 MHz */
957 int max_n = min(limit->n.max, refclk / 19200);
958 bool found = false;
959
960 target *= 5; /* fast clock */
961
962 memset(best_clock, 0, sizeof(*best_clock));
963
964 /* based on hardware requirement, prefer smaller n to precision */
965 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
966 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
967 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
968 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
969 clock.p = clock.p1 * clock.p2;
970 /* based on hardware requirement, prefer bigger m1,m2 values */
971 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 unsigned int ppm;
973
974 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 refclk * clock.m1);
976
977 vlv_calc_dpll_params(refclk, &clock);
978
979 if (!intel_PLL_is_valid(dev, limit,
980 &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target,
984 &clock,
985 best_clock,
986 bestppm, &ppm))
987 continue;
988
989 *best_clock = clock;
990 bestppm = ppm;
991 found = true;
992 }
993 }
994 }
995 }
996
997 return found;
998 }
999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002 struct intel_crtc_state *crtc_state,
1003 int target, int refclk, intel_clock_t *match_clock,
1004 intel_clock_t *best_clock)
1005 {
1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007 struct drm_device *dev = crtc->base.dev;
1008 unsigned int best_error_ppm;
1009 intel_clock_t clock;
1010 uint64_t m2;
1011 int found = false;
1012
1013 memset(best_clock, 0, sizeof(*best_clock));
1014 best_error_ppm = 1000000;
1015
1016 /*
1017 * Based on hardware doc, the n always set to 1, and m1 always
1018 * set to 2. If requires to support 200Mhz refclk, we need to
1019 * revisit this because n may not 1 anymore.
1020 */
1021 clock.n = 1, clock.m1 = 2;
1022 target *= 5; /* fast clock */
1023
1024 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025 for (clock.p2 = limit->p2.p2_fast;
1026 clock.p2 >= limit->p2.p2_slow;
1027 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028 unsigned int error_ppm;
1029
1030 clock.p = clock.p1 * clock.p2;
1031
1032 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033 clock.n) << 22, refclk * clock.m1);
1034
1035 if (m2 > INT_MAX/clock.m1)
1036 continue;
1037
1038 clock.m2 = m2;
1039
1040 chv_calc_dpll_params(refclk, &clock);
1041
1042 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 continue;
1044
1045 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046 best_error_ppm, &error_ppm))
1047 continue;
1048
1049 *best_clock = clock;
1050 best_error_ppm = error_ppm;
1051 found = true;
1052 }
1053 }
1054
1055 return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059 intel_clock_t *best_clock)
1060 {
1061 int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064 target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 /* Be paranoid as we can arrive here with only partial
1072 * state retrieved from the hardware during setup.
1073 *
1074 * We can ditch the adjusted_mode.crtc_clock check as soon
1075 * as Haswell has gained clock readout/fastboot support.
1076 *
1077 * We can ditch the crtc->primary->fb check as soon as we can
1078 * properly reconstruct framebuffers.
1079 *
1080 * FIXME: The intel_crtc->active here should be switched to
1081 * crtc->state->active once we have proper CRTC states wired up
1082 * for atomic.
1083 */
1084 return intel_crtc->active && crtc->primary->state->fb &&
1085 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090 {
1091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094 return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 i915_reg_t reg = PIPEDSL(pipe);
1101 u32 line1, line2;
1102 u32 line_mask;
1103
1104 if (IS_GEN2(dev))
1105 line_mask = DSL_LINEMASK_GEN2;
1106 else
1107 line_mask = DSL_LINEMASK_GEN3;
1108
1109 line1 = I915_READ(reg) & line_mask;
1110 msleep(5);
1111 line2 = I915_READ(reg) & line_mask;
1112
1113 return line1 == line2;
1114 }
1115
1116 /*
1117 * intel_wait_for_pipe_off - wait for pipe to turn off
1118 * @crtc: crtc whose pipe to wait for
1119 *
1120 * After disabling a pipe, we can't wait for vblank in the usual way,
1121 * spinning on the vblank interrupt status bit, since we won't actually
1122 * see an interrupt when the pipe is disabled.
1123 *
1124 * On Gen4 and above:
1125 * wait for the pipe register state bit to turn off
1126 *
1127 * Otherwise:
1128 * wait for the display line value to settle (it usually
1129 * ends up stopping at the start of the next frame).
1130 *
1131 */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134 struct drm_device *dev = crtc->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137 enum pipe pipe = crtc->pipe;
1138
1139 if (INTEL_INFO(dev)->gen >= 4) {
1140 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142 /* Wait for the Pipe State to go off */
1143 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144 100))
1145 WARN(1, "pipe_off wait timed out\n");
1146 } else {
1147 /* Wait for the display line to settle */
1148 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149 WARN(1, "pipe_off wait timed out\n");
1150 }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155 enum pipe pipe, bool state)
1156 {
1157 u32 val;
1158 bool cur_state;
1159
1160 val = I915_READ(DPLL(pipe));
1161 cur_state = !!(val & DPLL_VCO_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170 u32 val;
1171 bool cur_state;
1172
1173 mutex_lock(&dev_priv->sb_lock);
1174 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175 mutex_unlock(&dev_priv->sb_lock);
1176
1177 cur_state = val & DSI_PLL_VCO_EN;
1178 I915_STATE_WARN(cur_state != state,
1179 "DSI PLL state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190 if (crtc->config->shared_dpll < 0)
1191 return NULL;
1192
1193 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198 struct intel_shared_dpll *pll,
1199 bool state)
1200 {
1201 bool cur_state;
1202 struct intel_dpll_hw_state hw_state;
1203
1204 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205 return;
1206
1207 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208 I915_STATE_WARN(cur_state != state,
1209 "%s assertion failure (expected %s, current %s)\n",
1210 pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 bool cur_state;
1217 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218 pipe);
1219
1220 if (HAS_DDI(dev_priv->dev)) {
1221 /* DDI does not have a specific FDI_TX register */
1222 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224 } else {
1225 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226 cur_state = !!(val & FDI_TX_ENABLE);
1227 }
1228 I915_STATE_WARN(cur_state != state,
1229 "FDI TX state assertion failure (expected %s, current %s)\n",
1230 onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 u32 val;
1239 bool cur_state;
1240
1241 val = I915_READ(FDI_RX_CTL(pipe));
1242 cur_state = !!(val & FDI_RX_ENABLE);
1243 I915_STATE_WARN(cur_state != state,
1244 "FDI RX state assertion failure (expected %s, current %s)\n",
1245 onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252 {
1253 u32 val;
1254
1255 /* ILK FDI PLL is always enabled */
1256 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257 return;
1258
1259 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260 if (HAS_DDI(dev_priv->dev))
1261 return;
1262
1263 val = I915_READ(FDI_TX_CTL(pipe));
1264 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, bool state)
1269 {
1270 u32 val;
1271 bool cur_state;
1272
1273 val = I915_READ(FDI_RX_CTL(pipe));
1274 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275 I915_STATE_WARN(cur_state != state,
1276 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277 onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 i915_reg_t pp_reg;
1285 u32 val;
1286 enum pipe panel_pipe = PIPE_A;
1287 bool locked = true;
1288
1289 if (WARN_ON(HAS_DDI(dev)))
1290 return;
1291
1292 if (HAS_PCH_SPLIT(dev)) {
1293 u32 port_sel;
1294
1295 pp_reg = PCH_PP_CONTROL;
1296 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300 panel_pipe = PIPE_B;
1301 /* XXX: else fix for eDP */
1302 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303 /* presumably write lock depends on pipe, not port select */
1304 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305 panel_pipe = pipe;
1306 } else {
1307 pp_reg = PP_CONTROL;
1308 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309 panel_pipe = PIPE_B;
1310 }
1311
1312 val = I915_READ(pp_reg);
1313 if (!(val & PANEL_POWER_ON) ||
1314 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315 locked = false;
1316
1317 I915_STATE_WARN(panel_pipe == pipe && locked,
1318 "panel assertion failure, pipe %c regs locked\n",
1319 pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 struct drm_device *dev = dev_priv->dev;
1326 bool cur_state;
1327
1328 if (IS_845G(dev) || IS_I865G(dev))
1329 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330 else
1331 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333 I915_STATE_WARN(cur_state != state,
1334 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335 pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, bool state)
1342 {
1343 bool cur_state;
1344 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345 pipe);
1346
1347 /* if we need the pipe quirk it must be always on */
1348 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1349 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1350 state = true;
1351
1352 if (!intel_display_power_is_enabled(dev_priv,
1353 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1354 cur_state = false;
1355 } else {
1356 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1357 cur_state = !!(val & PIPECONF_ENABLE);
1358 }
1359
1360 I915_STATE_WARN(cur_state != state,
1361 "pipe %c assertion failure (expected %s, current %s)\n",
1362 pipe_name(pipe), onoff(state), onoff(cur_state));
1363 }
1364
1365 static void assert_plane(struct drm_i915_private *dev_priv,
1366 enum plane plane, bool state)
1367 {
1368 u32 val;
1369 bool cur_state;
1370
1371 val = I915_READ(DSPCNTR(plane));
1372 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1373 I915_STATE_WARN(cur_state != state,
1374 "plane %c assertion failure (expected %s, current %s)\n",
1375 plane_name(plane), onoff(state), onoff(cur_state));
1376 }
1377
1378 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1379 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1380
1381 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe)
1383 {
1384 struct drm_device *dev = dev_priv->dev;
1385 int i;
1386
1387 /* Primary planes are fixed to pipes on gen4+ */
1388 if (INTEL_INFO(dev)->gen >= 4) {
1389 u32 val = I915_READ(DSPCNTR(pipe));
1390 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1391 "plane %c assertion failure, should be disabled but not\n",
1392 plane_name(pipe));
1393 return;
1394 }
1395
1396 /* Need to check both planes against the pipe */
1397 for_each_pipe(dev_priv, i) {
1398 u32 val = I915_READ(DSPCNTR(i));
1399 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1400 DISPPLANE_SEL_PIPE_SHIFT;
1401 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1402 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1403 plane_name(i), pipe_name(pipe));
1404 }
1405 }
1406
1407 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe)
1409 {
1410 struct drm_device *dev = dev_priv->dev;
1411 int sprite;
1412
1413 if (INTEL_INFO(dev)->gen >= 9) {
1414 for_each_sprite(dev_priv, pipe, sprite) {
1415 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1416 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1417 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1418 sprite, pipe_name(pipe));
1419 }
1420 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1421 for_each_sprite(dev_priv, pipe, sprite) {
1422 u32 val = I915_READ(SPCNTR(pipe, sprite));
1423 I915_STATE_WARN(val & SP_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 sprite_name(pipe, sprite), pipe_name(pipe));
1426 }
1427 } else if (INTEL_INFO(dev)->gen >= 7) {
1428 u32 val = I915_READ(SPRCTL(pipe));
1429 I915_STATE_WARN(val & SPRITE_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1432 } else if (INTEL_INFO(dev)->gen >= 5) {
1433 u32 val = I915_READ(DVSCNTR(pipe));
1434 I915_STATE_WARN(val & DVS_ENABLE,
1435 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436 plane_name(pipe), pipe_name(pipe));
1437 }
1438 }
1439
1440 static void assert_vblank_disabled(struct drm_crtc *crtc)
1441 {
1442 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1443 drm_crtc_vblank_put(crtc);
1444 }
1445
1446 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1447 {
1448 u32 val;
1449 bool enabled;
1450
1451 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1452
1453 val = I915_READ(PCH_DREF_CONTROL);
1454 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455 DREF_SUPERSPREAD_SOURCE_MASK));
1456 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1457 }
1458
1459 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461 {
1462 u32 val;
1463 bool enabled;
1464
1465 val = I915_READ(PCH_TRANSCONF(pipe));
1466 enabled = !!(val & TRANS_ENABLE);
1467 I915_STATE_WARN(enabled,
1468 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469 pipe_name(pipe));
1470 }
1471
1472 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 port_sel, u32 val)
1474 {
1475 if ((val & DP_PORT_EN) == 0)
1476 return false;
1477
1478 if (HAS_PCH_CPT(dev_priv->dev)) {
1479 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1480 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1481 return false;
1482 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1483 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 return false;
1485 } else {
1486 if ((val & DP_PIPE_MASK) != (pipe << 30))
1487 return false;
1488 }
1489 return true;
1490 }
1491
1492 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe, u32 val)
1494 {
1495 if ((val & SDVO_ENABLE) == 0)
1496 return false;
1497
1498 if (HAS_PCH_CPT(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1500 return false;
1501 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1502 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 return false;
1504 } else {
1505 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1506 return false;
1507 }
1508 return true;
1509 }
1510
1511 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1512 enum pipe pipe, u32 val)
1513 {
1514 if ((val & LVDS_PORT_EN) == 0)
1515 return false;
1516
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1522 return false;
1523 }
1524 return true;
1525 }
1526
1527 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, u32 val)
1529 {
1530 if ((val & ADPA_DAC_ENABLE) == 0)
1531 return false;
1532 if (HAS_PCH_CPT(dev_priv->dev)) {
1533 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 return false;
1535 } else {
1536 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1537 return false;
1538 }
1539 return true;
1540 }
1541
1542 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1543 enum pipe pipe, i915_reg_t reg,
1544 u32 port_sel)
1545 {
1546 u32 val = I915_READ(reg);
1547 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1548 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1549 i915_mmio_reg_offset(reg), pipe_name(pipe));
1550
1551 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1552 && (val & DP_PIPEB_SELECT),
1553 "IBX PCH dp port still using transcoder B\n");
1554 }
1555
1556 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1557 enum pipe pipe, i915_reg_t reg)
1558 {
1559 u32 val = I915_READ(reg);
1560 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1561 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1562 i915_mmio_reg_offset(reg), pipe_name(pipe));
1563
1564 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1565 && (val & SDVO_PIPE_B_SELECT),
1566 "IBX PCH hdmi port still using transcoder B\n");
1567 }
1568
1569 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1570 enum pipe pipe)
1571 {
1572 u32 val;
1573
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577
1578 val = I915_READ(PCH_ADPA);
1579 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1580 "PCH VGA enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 val = I915_READ(PCH_LVDS);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586 pipe_name(pipe));
1587
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void vlv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 i915_reg_t reg = DPLL(crtc->pipe);
1599 u32 dpll = pipe_config->dpll_hw_state.dpll;
1600
1601 assert_pipe_disabled(dev_priv, crtc->pipe);
1602
1603 /* PLL is protected by panel, make sure we can write it */
1604 if (IS_MOBILE(dev_priv->dev))
1605 assert_panel_unlocked(dev_priv, crtc->pipe);
1606
1607 I915_WRITE(reg, dpll);
1608 POSTING_READ(reg);
1609 udelay(150);
1610
1611 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1612 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1613
1614 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(crtc->pipe));
1616
1617 /* We do this three times for luck */
1618 I915_WRITE(reg, dpll);
1619 POSTING_READ(reg);
1620 udelay(150); /* wait for warmup */
1621 I915_WRITE(reg, dpll);
1622 POSTING_READ(reg);
1623 udelay(150); /* wait for warmup */
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 }
1628
1629 static void chv_enable_pll(struct intel_crtc *crtc,
1630 const struct intel_crtc_state *pipe_config)
1631 {
1632 struct drm_device *dev = crtc->base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int pipe = crtc->pipe;
1635 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1636 u32 tmp;
1637
1638 assert_pipe_disabled(dev_priv, crtc->pipe);
1639
1640 mutex_lock(&dev_priv->sb_lock);
1641
1642 /* Enable back the 10bit clock to display controller */
1643 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1644 tmp |= DPIO_DCLKP_EN;
1645 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1646
1647 mutex_unlock(&dev_priv->sb_lock);
1648
1649 /*
1650 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1651 */
1652 udelay(1);
1653
1654 /* Enable PLL */
1655 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1656
1657 /* Check PLL is locked */
1658 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1659 DRM_ERROR("PLL %d failed to lock\n", pipe);
1660
1661 /* not sure when this should be written */
1662 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1663 POSTING_READ(DPLL_MD(pipe));
1664 }
1665
1666 static int intel_num_dvo_pipes(struct drm_device *dev)
1667 {
1668 struct intel_crtc *crtc;
1669 int count = 0;
1670
1671 for_each_intel_crtc(dev, crtc)
1672 count += crtc->base.state->active &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1674
1675 return count;
1676 }
1677
1678 static void i9xx_enable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_device *dev = crtc->base.dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 i915_reg_t reg = DPLL(crtc->pipe);
1683 u32 dpll = crtc->config->dpll_hw_state.dpll;
1684
1685 assert_pipe_disabled(dev_priv, crtc->pipe);
1686
1687 /* No really, not for ILK+ */
1688 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1689
1690 /* PLL is protected by panel, make sure we can write it */
1691 if (IS_MOBILE(dev) && !IS_I830(dev))
1692 assert_panel_unlocked(dev_priv, crtc->pipe);
1693
1694 /* Enable DVO 2x clock on both PLLs if necessary */
1695 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1696 /*
1697 * It appears to be important that we don't enable this
1698 * for the current pipe before otherwise configuring the
1699 * PLL. No idea how this should be handled if multiple
1700 * DVO outputs are enabled simultaneosly.
1701 */
1702 dpll |= DPLL_DVO_2X_MODE;
1703 I915_WRITE(DPLL(!crtc->pipe),
1704 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1705 }
1706
1707 /*
1708 * Apparently we need to have VGA mode enabled prior to changing
1709 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1710 * dividers, even though the register value does change.
1711 */
1712 I915_WRITE(reg, 0);
1713
1714 I915_WRITE(reg, dpll);
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 val = DPLL_VGA_MODE_DIS;
1793 if (pipe == PIPE_B)
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803 u32 val;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1815
1816 mutex_lock(&dev_priv->sb_lock);
1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823 mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1829 {
1830 u32 port_mask;
1831 i915_reg_t dpll_reg;
1832
1833 switch (dport->port) {
1834 case PORT_B:
1835 port_mask = DPLL_PORTB_READY_MASK;
1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_C:
1839 port_mask = DPLL_PORTC_READY_MASK;
1840 dpll_reg = DPLL(0);
1841 expected_mask <<= 4;
1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1846 break;
1847 default:
1848 BUG();
1849 }
1850
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862 if (WARN_ON(pll == NULL))
1863 return;
1864
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873 }
1874
1875 /**
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1893 return;
1894
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1898
1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 return;
1903 }
1904 WARN_ON(pll->on);
1905
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1910 pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
1923 if (pll == NULL)
1924 return;
1925
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927 return;
1928
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1932
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1935 return;
1936 }
1937
1938 assert_shared_dpll_enabled(dev_priv, pll);
1939 WARN_ON(!pll->on);
1940 if (--pll->active)
1941 return;
1942
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1945 pll->on = false;
1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
1952 {
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 i915_reg_t reg;
1957 uint32_t val, pipeconf_val;
1958
1959 /* PCH only available on ILK+ */
1960 BUG_ON(!HAS_PCH_SPLIT(dev));
1961
1962 /* Make sure PCH DPLL is enabled */
1963 assert_shared_dpll_enabled(dev_priv,
1964 intel_crtc_to_shared_dpll(intel_crtc));
1965
1966 /* FDI must be feeding us bits for PCH ports */
1967 assert_fdi_tx_enabled(dev_priv, pipe);
1968 assert_fdi_rx_enabled(dev_priv, pipe);
1969
1970 if (HAS_PCH_CPT(dev)) {
1971 /* Workaround: Set the timing override bit before enabling the
1972 * pch transcoder. */
1973 reg = TRANS_CHICKEN2(pipe);
1974 val = I915_READ(reg);
1975 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1976 I915_WRITE(reg, val);
1977 }
1978
1979 reg = PCH_TRANSCONF(pipe);
1980 val = I915_READ(reg);
1981 pipeconf_val = I915_READ(PIPECONF(pipe));
1982
1983 if (HAS_PCH_IBX(dev_priv->dev)) {
1984 /*
1985 * Make the BPC in transcoder be consistent with
1986 * that in pipeconf reg. For HDMI we must use 8bpc
1987 * here for both 8bpc and 12bpc.
1988 */
1989 val &= ~PIPECONF_BPC_MASK;
1990 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1991 val |= PIPECONF_8BPC;
1992 else
1993 val |= pipeconf_val & PIPECONF_BPC_MASK;
1994 }
1995
1996 val &= ~TRANS_INTERLACE_MASK;
1997 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1998 if (HAS_PCH_IBX(dev_priv->dev) &&
1999 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2000 val |= TRANS_LEGACY_INTERLACED_ILK;
2001 else
2002 val |= TRANS_INTERLACED;
2003 else
2004 val |= TRANS_PROGRESSIVE;
2005
2006 I915_WRITE(reg, val | TRANS_ENABLE);
2007 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2008 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2009 }
2010
2011 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2012 enum transcoder cpu_transcoder)
2013 {
2014 u32 val, pipeconf_val;
2015
2016 /* PCH only available on ILK+ */
2017 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018
2019 /* FDI must be feeding us bits for PCH ports */
2020 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2021 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022
2023 /* Workaround: set timing override bit. */
2024 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2025 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2027
2028 val = TRANS_ENABLE;
2029 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030
2031 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2032 PIPECONF_INTERLACED_ILK)
2033 val |= TRANS_INTERLACED;
2034 else
2035 val |= TRANS_PROGRESSIVE;
2036
2037 I915_WRITE(LPT_TRANSCONF, val);
2038 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2039 DRM_ERROR("Failed to enable PCH transcoder\n");
2040 }
2041
2042 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2043 enum pipe pipe)
2044 {
2045 struct drm_device *dev = dev_priv->dev;
2046 i915_reg_t reg;
2047 uint32_t val;
2048
2049 /* FDI relies on the transcoder */
2050 assert_fdi_tx_disabled(dev_priv, pipe);
2051 assert_fdi_rx_disabled(dev_priv, pipe);
2052
2053 /* Ports must be off as well */
2054 assert_pch_ports_disabled(dev_priv, pipe);
2055
2056 reg = PCH_TRANSCONF(pipe);
2057 val = I915_READ(reg);
2058 val &= ~TRANS_ENABLE;
2059 I915_WRITE(reg, val);
2060 /* wait for PCH transcoder off, transcoder state */
2061 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2062 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2063
2064 if (HAS_PCH_CPT(dev)) {
2065 /* Workaround: Clear the timing override chicken bit again. */
2066 reg = TRANS_CHICKEN2(pipe);
2067 val = I915_READ(reg);
2068 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2069 I915_WRITE(reg, val);
2070 }
2071 }
2072
2073 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2074 {
2075 u32 val;
2076
2077 val = I915_READ(LPT_TRANSCONF);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(LPT_TRANSCONF, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2082 DRM_ERROR("Failed to disable PCH transcoder\n");
2083
2084 /* Workaround: clear timing override bit. */
2085 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2086 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2087 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2088 }
2089
2090 /**
2091 * intel_enable_pipe - enable a pipe, asserting requirements
2092 * @crtc: crtc responsible for the pipe
2093 *
2094 * Enable @crtc's pipe, making sure that various hardware specific requirements
2095 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2096 */
2097 static void intel_enable_pipe(struct intel_crtc *crtc)
2098 {
2099 struct drm_device *dev = crtc->base.dev;
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 enum pipe pipe = crtc->pipe;
2102 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2103 enum pipe pch_transcoder;
2104 i915_reg_t reg;
2105 u32 val;
2106
2107 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108
2109 assert_planes_disabled(dev_priv, pipe);
2110 assert_cursor_disabled(dev_priv, pipe);
2111 assert_sprites_disabled(dev_priv, pipe);
2112
2113 if (HAS_PCH_LPT(dev_priv->dev))
2114 pch_transcoder = TRANSCODER_A;
2115 else
2116 pch_transcoder = pipe;
2117
2118 /*
2119 * A pipe without a PLL won't actually be able to drive bits from
2120 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2121 * need the check.
2122 */
2123 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2124 if (crtc->config->has_dsi_encoder)
2125 assert_dsi_pll_enabled(dev_priv);
2126 else
2127 assert_pll_enabled(dev_priv, pipe);
2128 else {
2129 if (crtc->config->has_pch_encoder) {
2130 /* if driving the PCH, we need FDI enabled */
2131 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2132 assert_fdi_tx_pll_enabled(dev_priv,
2133 (enum pipe) cpu_transcoder);
2134 }
2135 /* FIXME: assert CPU port conditions for SNB+ */
2136 }
2137
2138 reg = PIPECONF(cpu_transcoder);
2139 val = I915_READ(reg);
2140 if (val & PIPECONF_ENABLE) {
2141 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2142 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2143 return;
2144 }
2145
2146 I915_WRITE(reg, val | PIPECONF_ENABLE);
2147 POSTING_READ(reg);
2148
2149 /*
2150 * Until the pipe starts DSL will read as 0, which would cause
2151 * an apparent vblank timestamp jump, which messes up also the
2152 * frame count when it's derived from the timestamps. So let's
2153 * wait for the pipe to start properly before we call
2154 * drm_crtc_vblank_on()
2155 */
2156 if (dev->max_vblank_count == 0 &&
2157 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2158 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 i915_reg_t reg;
2177 u32 val;
2178
2179 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181 /*
2182 * Make sure planes won't keep trying to pump pixels to us,
2183 * or we might hang the display.
2184 */
2185 assert_planes_disabled(dev_priv, pipe);
2186 assert_cursor_disabled(dev_priv, pipe);
2187 assert_sprites_disabled(dev_priv, pipe);
2188
2189 reg = PIPECONF(cpu_transcoder);
2190 val = I915_READ(reg);
2191 if ((val & PIPECONF_ENABLE) == 0)
2192 return;
2193
2194 /*
2195 * Double wide has implications for planes
2196 * so best keep it disabled when not needed.
2197 */
2198 if (crtc->config->double_wide)
2199 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201 /* Don't disable pipe or pipe PLLs if needed */
2202 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204 val &= ~PIPECONF_ENABLE;
2205
2206 I915_WRITE(reg, val);
2207 if ((val & PIPECONF_ENABLE) == 0)
2208 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215 return true;
2216 #endif
2217 return false;
2218 }
2219
2220 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2221 {
2222 return IS_GEN2(dev_priv) ? 2048 : 4096;
2223 }
2224
2225 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2226 uint64_t fb_modifier, unsigned int cpp)
2227 {
2228 switch (fb_modifier) {
2229 case DRM_FORMAT_MOD_NONE:
2230 return cpp;
2231 case I915_FORMAT_MOD_X_TILED:
2232 if (IS_GEN2(dev_priv))
2233 return 128;
2234 else
2235 return 512;
2236 case I915_FORMAT_MOD_Y_TILED:
2237 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2238 return 128;
2239 else
2240 return 512;
2241 case I915_FORMAT_MOD_Yf_TILED:
2242 switch (cpp) {
2243 case 1:
2244 return 64;
2245 case 2:
2246 case 4:
2247 return 128;
2248 case 8:
2249 case 16:
2250 return 256;
2251 default:
2252 MISSING_CASE(cpp);
2253 return cpp;
2254 }
2255 break;
2256 default:
2257 MISSING_CASE(fb_modifier);
2258 return cpp;
2259 }
2260 }
2261
2262 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2263 uint64_t fb_modifier, unsigned int cpp)
2264 {
2265 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2266 return 1;
2267 else
2268 return intel_tile_size(dev_priv) /
2269 intel_tile_width(dev_priv, fb_modifier, cpp);
2270 }
2271
2272 unsigned int
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_modifier)
2275 {
2276 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2277 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2278
2279 return ALIGN(height, tile_height);
2280 }
2281
2282 static void
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285 {
2286 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2287 struct intel_rotation_info *info = &view->params.rotation_info;
2288 unsigned int tile_size, tile_width, tile_height, cpp;
2289
2290 *view = i915_ggtt_view_normal;
2291
2292 if (!plane_state)
2293 return;
2294
2295 if (!intel_rotation_90_or_270(plane_state->rotation))
2296 return;
2297
2298 *view = i915_ggtt_view_rotated;
2299
2300 info->height = fb->height;
2301 info->pixel_format = fb->pixel_format;
2302 info->pitch = fb->pitches[0];
2303 info->uv_offset = fb->offsets[1];
2304 info->fb_modifier = fb->modifier[0];
2305
2306 tile_size = intel_tile_size(dev_priv);
2307
2308 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2309 tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
2310 tile_height = tile_size / tile_width;
2311
2312 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
2313 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2314 info->size = info->width_pages * info->height_pages * tile_size;
2315
2316 if (info->pixel_format == DRM_FORMAT_NV12) {
2317 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2318 tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
2319 tile_height = tile_size / tile_width;
2320
2321 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
2322 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2323 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2324 }
2325 }
2326
2327 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2328 {
2329 if (INTEL_INFO(dev_priv)->gen >= 9)
2330 return 256 * 1024;
2331 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2332 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2333 return 128 * 1024;
2334 else if (INTEL_INFO(dev_priv)->gen >= 4)
2335 return 4 * 1024;
2336 else
2337 return 0;
2338 }
2339
2340 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2341 uint64_t fb_modifier)
2342 {
2343 switch (fb_modifier) {
2344 case DRM_FORMAT_MOD_NONE:
2345 return intel_linear_alignment(dev_priv);
2346 case I915_FORMAT_MOD_X_TILED:
2347 if (INTEL_INFO(dev_priv)->gen >= 9)
2348 return 256 * 1024;
2349 return 0;
2350 case I915_FORMAT_MOD_Y_TILED:
2351 case I915_FORMAT_MOD_Yf_TILED:
2352 return 1 * 1024 * 1024;
2353 default:
2354 MISSING_CASE(fb_modifier);
2355 return 0;
2356 }
2357 }
2358
2359 int
2360 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2361 struct drm_framebuffer *fb,
2362 const struct drm_plane_state *plane_state)
2363 {
2364 struct drm_device *dev = fb->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2367 struct i915_ggtt_view view;
2368 u32 alignment;
2369 int ret;
2370
2371 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2372
2373 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2374
2375 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376
2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
2394 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2395 &view);
2396 if (ret)
2397 goto err_pm;
2398
2399 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2400 * fence, whereas 965+ only requires a fence if using
2401 * framebuffer compression. For simplicity, we always install
2402 * a fence as the cost is not that onerous.
2403 */
2404 if (view.type == I915_GGTT_VIEW_NORMAL) {
2405 ret = i915_gem_object_get_fence(obj);
2406 if (ret == -EDEADLK) {
2407 /*
2408 * -EDEADLK means there are no free fences
2409 * no pending flips.
2410 *
2411 * This is propagated to atomic, but it uses
2412 * -EDEADLK to force a locking recovery, so
2413 * change the returned error to -EBUSY.
2414 */
2415 ret = -EBUSY;
2416 goto err_unpin;
2417 } else if (ret)
2418 goto err_unpin;
2419
2420 i915_gem_object_pin_fence(obj);
2421 }
2422
2423 intel_runtime_pm_put(dev_priv);
2424 return 0;
2425
2426 err_unpin:
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_pm:
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435 {
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438
2439 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442
2443 if (view.type == I915_GGTT_VIEW_NORMAL)
2444 i915_gem_object_unpin_fence(obj);
2445
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451 unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2452 int *x, int *y,
2453 uint64_t fb_modifier,
2454 unsigned int cpp,
2455 unsigned int pitch)
2456 {
2457 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2458 unsigned int tile_size, tile_width, tile_height;
2459 unsigned int tile_rows, tiles;
2460
2461 tile_size = intel_tile_size(dev_priv);
2462 tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
2463 tile_height = tile_size / tile_width;
2464
2465 tile_rows = *y / tile_height;
2466 *y %= tile_height;
2467
2468 tiles = *x / (tile_width/cpp);
2469 *x %= tile_width/cpp;
2470
2471 return tile_rows * pitch * tile_height + tiles * tile_size;
2472 } else {
2473 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2474 unsigned int offset;
2475
2476 offset = *y * pitch + *x * cpp;
2477 *y = (offset & alignment) / pitch;
2478 *x = ((offset & alignment) - *y * pitch) / cpp;
2479 return offset & ~alignment;
2480 }
2481 }
2482
2483 static int i9xx_format_to_fourcc(int format)
2484 {
2485 switch (format) {
2486 case DISPPLANE_8BPP:
2487 return DRM_FORMAT_C8;
2488 case DISPPLANE_BGRX555:
2489 return DRM_FORMAT_XRGB1555;
2490 case DISPPLANE_BGRX565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case DISPPLANE_BGRX888:
2494 return DRM_FORMAT_XRGB8888;
2495 case DISPPLANE_RGBX888:
2496 return DRM_FORMAT_XBGR8888;
2497 case DISPPLANE_BGRX101010:
2498 return DRM_FORMAT_XRGB2101010;
2499 case DISPPLANE_RGBX101010:
2500 return DRM_FORMAT_XBGR2101010;
2501 }
2502 }
2503
2504 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2505 {
2506 switch (format) {
2507 case PLANE_CTL_FORMAT_RGB_565:
2508 return DRM_FORMAT_RGB565;
2509 default:
2510 case PLANE_CTL_FORMAT_XRGB_8888:
2511 if (rgb_order) {
2512 if (alpha)
2513 return DRM_FORMAT_ABGR8888;
2514 else
2515 return DRM_FORMAT_XBGR8888;
2516 } else {
2517 if (alpha)
2518 return DRM_FORMAT_ARGB8888;
2519 else
2520 return DRM_FORMAT_XRGB8888;
2521 }
2522 case PLANE_CTL_FORMAT_XRGB_2101010:
2523 if (rgb_order)
2524 return DRM_FORMAT_XBGR2101010;
2525 else
2526 return DRM_FORMAT_XRGB2101010;
2527 }
2528 }
2529
2530 static bool
2531 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2532 struct intel_initial_plane_config *plane_config)
2533 {
2534 struct drm_device *dev = crtc->base.dev;
2535 struct drm_i915_private *dev_priv = to_i915(dev);
2536 struct drm_i915_gem_object *obj = NULL;
2537 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2538 struct drm_framebuffer *fb = &plane_config->fb->base;
2539 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2540 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2541 PAGE_SIZE);
2542
2543 size_aligned -= base_aligned;
2544
2545 if (plane_config->size == 0)
2546 return false;
2547
2548 /* If the FB is too big, just don't use it since fbdev is not very
2549 * important and we should probably use that space with FBC or other
2550 * features. */
2551 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2552 return false;
2553
2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
2558 if (!obj)
2559 return false;
2560
2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
2563 obj->stride = fb->pitches[0];
2564
2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572 mutex_lock(&dev->struct_mutex);
2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574 &mode_cmd, obj)) {
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
2578 mutex_unlock(&dev->struct_mutex);
2579
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581 return true;
2582
2583 out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
2586 return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
2606 {
2607 struct drm_device *dev = intel_crtc->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2611 struct drm_i915_gem_object *obj;
2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_plane_state *plane_state = primary->state;
2614 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2615 struct intel_plane *intel_plane = to_intel_plane(primary);
2616 struct intel_plane_state *intel_state =
2617 to_intel_plane_state(plane_state);
2618 struct drm_framebuffer *fb;
2619
2620 if (!plane_config->fb)
2621 return;
2622
2623 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2624 fb = &plane_config->fb->base;
2625 goto valid_fb;
2626 }
2627
2628 kfree(plane_config->fb);
2629
2630 /*
2631 * Failed to alloc the obj, check to see if we should share
2632 * an fb with another CRTC instead
2633 */
2634 for_each_crtc(dev, c) {
2635 i = to_intel_crtc(c);
2636
2637 if (c == &intel_crtc->base)
2638 continue;
2639
2640 if (!i->active)
2641 continue;
2642
2643 fb = c->primary->fb;
2644 if (!fb)
2645 continue;
2646
2647 obj = intel_fb_obj(fb);
2648 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2649 drm_framebuffer_reference(fb);
2650 goto valid_fb;
2651 }
2652 }
2653
2654 /*
2655 * We've failed to reconstruct the BIOS FB. Current display state
2656 * indicates that the primary plane is visible, but has a NULL FB,
2657 * which will lead to problems later if we don't fix it up. The
2658 * simplest solution is to just disable the primary plane now and
2659 * pretend the BIOS never had it enabled.
2660 */
2661 to_intel_plane_state(plane_state)->visible = false;
2662 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2663 intel_pre_disable_primary(&intel_crtc->base);
2664 intel_plane->disable_plane(primary, &intel_crtc->base);
2665
2666 return;
2667
2668 valid_fb:
2669 plane_state->src_x = 0;
2670 plane_state->src_y = 0;
2671 plane_state->src_w = fb->width << 16;
2672 plane_state->src_h = fb->height << 16;
2673
2674 plane_state->crtc_x = 0;
2675 plane_state->crtc_y = 0;
2676 plane_state->crtc_w = fb->width;
2677 plane_state->crtc_h = fb->height;
2678
2679 intel_state->src.x1 = plane_state->src_x;
2680 intel_state->src.y1 = plane_state->src_y;
2681 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2682 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2683 intel_state->dst.x1 = plane_state->crtc_x;
2684 intel_state->dst.y1 = plane_state->crtc_y;
2685 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2686 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2687
2688 obj = intel_fb_obj(fb);
2689 if (obj->tiling_mode != I915_TILING_NONE)
2690 dev_priv->preserve_bios_swizzle = true;
2691
2692 drm_framebuffer_reference(fb);
2693 primary->fb = primary->state->fb = fb;
2694 primary->crtc = primary->state->crtc = &intel_crtc->base;
2695 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2696 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2697 }
2698
2699 static void i9xx_update_primary_plane(struct drm_plane *primary,
2700 const struct intel_crtc_state *crtc_state,
2701 const struct intel_plane_state *plane_state)
2702 {
2703 struct drm_device *dev = primary->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2706 struct drm_framebuffer *fb = plane_state->base.fb;
2707 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2708 int plane = intel_crtc->plane;
2709 unsigned long linear_offset;
2710 int x = plane_state->src.x1 >> 16;
2711 int y = plane_state->src.y1 >> 16;
2712 u32 dspcntr;
2713 i915_reg_t reg = DSPCNTR(plane);
2714 int pixel_size;
2715
2716 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2717
2718 dspcntr = DISPPLANE_GAMMA_ENABLE;
2719
2720 dspcntr |= DISPLAY_PLANE_ENABLE;
2721
2722 if (INTEL_INFO(dev)->gen < 4) {
2723 if (intel_crtc->pipe == PIPE_B)
2724 dspcntr |= DISPPLANE_SEL_PIPE_B;
2725
2726 /* pipesrc and dspsize control the size that is scaled from,
2727 * which should always be the user's requested size.
2728 */
2729 I915_WRITE(DSPSIZE(plane),
2730 ((crtc_state->pipe_src_h - 1) << 16) |
2731 (crtc_state->pipe_src_w - 1));
2732 I915_WRITE(DSPPOS(plane), 0);
2733 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2734 I915_WRITE(PRIMSIZE(plane),
2735 ((crtc_state->pipe_src_h - 1) << 16) |
2736 (crtc_state->pipe_src_w - 1));
2737 I915_WRITE(PRIMPOS(plane), 0);
2738 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2739 }
2740
2741 switch (fb->pixel_format) {
2742 case DRM_FORMAT_C8:
2743 dspcntr |= DISPPLANE_8BPP;
2744 break;
2745 case DRM_FORMAT_XRGB1555:
2746 dspcntr |= DISPPLANE_BGRX555;
2747 break;
2748 case DRM_FORMAT_RGB565:
2749 dspcntr |= DISPPLANE_BGRX565;
2750 break;
2751 case DRM_FORMAT_XRGB8888:
2752 dspcntr |= DISPPLANE_BGRX888;
2753 break;
2754 case DRM_FORMAT_XBGR8888:
2755 dspcntr |= DISPPLANE_RGBX888;
2756 break;
2757 case DRM_FORMAT_XRGB2101010:
2758 dspcntr |= DISPPLANE_BGRX101010;
2759 break;
2760 case DRM_FORMAT_XBGR2101010:
2761 dspcntr |= DISPPLANE_RGBX101010;
2762 break;
2763 default:
2764 BUG();
2765 }
2766
2767 if (INTEL_INFO(dev)->gen >= 4 &&
2768 obj->tiling_mode != I915_TILING_NONE)
2769 dspcntr |= DISPPLANE_TILED;
2770
2771 if (IS_G4X(dev))
2772 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2773
2774 linear_offset = y * fb->pitches[0] + x * pixel_size;
2775
2776 if (INTEL_INFO(dev)->gen >= 4) {
2777 intel_crtc->dspaddr_offset =
2778 intel_compute_tile_offset(dev_priv, &x, &y,
2779 fb->modifier[0],
2780 pixel_size,
2781 fb->pitches[0]);
2782 linear_offset -= intel_crtc->dspaddr_offset;
2783 } else {
2784 intel_crtc->dspaddr_offset = linear_offset;
2785 }
2786
2787 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2788 dspcntr |= DISPPLANE_ROTATE_180;
2789
2790 x += (crtc_state->pipe_src_w - 1);
2791 y += (crtc_state->pipe_src_h - 1);
2792
2793 /* Finding the last pixel of the last line of the display
2794 data and adding to linear_offset*/
2795 linear_offset +=
2796 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2797 (crtc_state->pipe_src_w - 1) * pixel_size;
2798 }
2799
2800 intel_crtc->adjusted_x = x;
2801 intel_crtc->adjusted_y = y;
2802
2803 I915_WRITE(reg, dspcntr);
2804
2805 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2806 if (INTEL_INFO(dev)->gen >= 4) {
2807 I915_WRITE(DSPSURF(plane),
2808 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2809 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2810 I915_WRITE(DSPLINOFF(plane), linear_offset);
2811 } else
2812 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2813 POSTING_READ(reg);
2814 }
2815
2816 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2817 struct drm_crtc *crtc)
2818 {
2819 struct drm_device *dev = crtc->dev;
2820 struct drm_i915_private *dev_priv = dev->dev_private;
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822 int plane = intel_crtc->plane;
2823
2824 I915_WRITE(DSPCNTR(plane), 0);
2825 if (INTEL_INFO(dev_priv)->gen >= 4)
2826 I915_WRITE(DSPSURF(plane), 0);
2827 else
2828 I915_WRITE(DSPADDR(plane), 0);
2829 POSTING_READ(DSPCNTR(plane));
2830 }
2831
2832 static void ironlake_update_primary_plane(struct drm_plane *primary,
2833 const struct intel_crtc_state *crtc_state,
2834 const struct intel_plane_state *plane_state)
2835 {
2836 struct drm_device *dev = primary->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2839 struct drm_framebuffer *fb = plane_state->base.fb;
2840 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2841 int plane = intel_crtc->plane;
2842 unsigned long linear_offset;
2843 u32 dspcntr;
2844 i915_reg_t reg = DSPCNTR(plane);
2845 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2846 int x = plane_state->src.x1 >> 16;
2847 int y = plane_state->src.y1 >> 16;
2848
2849 dspcntr = DISPPLANE_GAMMA_ENABLE;
2850 dspcntr |= DISPLAY_PLANE_ENABLE;
2851
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2853 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2854
2855 switch (fb->pixel_format) {
2856 case DRM_FORMAT_C8:
2857 dspcntr |= DISPPLANE_8BPP;
2858 break;
2859 case DRM_FORMAT_RGB565:
2860 dspcntr |= DISPPLANE_BGRX565;
2861 break;
2862 case DRM_FORMAT_XRGB8888:
2863 dspcntr |= DISPPLANE_BGRX888;
2864 break;
2865 case DRM_FORMAT_XBGR8888:
2866 dspcntr |= DISPPLANE_RGBX888;
2867 break;
2868 case DRM_FORMAT_XRGB2101010:
2869 dspcntr |= DISPPLANE_BGRX101010;
2870 break;
2871 case DRM_FORMAT_XBGR2101010:
2872 dspcntr |= DISPPLANE_RGBX101010;
2873 break;
2874 default:
2875 BUG();
2876 }
2877
2878 if (obj->tiling_mode != I915_TILING_NONE)
2879 dspcntr |= DISPPLANE_TILED;
2880
2881 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2882 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2883
2884 linear_offset = y * fb->pitches[0] + x * pixel_size;
2885 intel_crtc->dspaddr_offset =
2886 intel_compute_tile_offset(dev_priv, &x, &y,
2887 fb->modifier[0],
2888 pixel_size,
2889 fb->pitches[0]);
2890 linear_offset -= intel_crtc->dspaddr_offset;
2891 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2892 dspcntr |= DISPPLANE_ROTATE_180;
2893
2894 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2895 x += (crtc_state->pipe_src_w - 1);
2896 y += (crtc_state->pipe_src_h - 1);
2897
2898 /* Finding the last pixel of the last line of the display
2899 data and adding to linear_offset*/
2900 linear_offset +=
2901 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2902 (crtc_state->pipe_src_w - 1) * pixel_size;
2903 }
2904 }
2905
2906 intel_crtc->adjusted_x = x;
2907 intel_crtc->adjusted_y = y;
2908
2909 I915_WRITE(reg, dspcntr);
2910
2911 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2912 I915_WRITE(DSPSURF(plane),
2913 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2914 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2915 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2916 } else {
2917 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2918 I915_WRITE(DSPLINOFF(plane), linear_offset);
2919 }
2920 POSTING_READ(reg);
2921 }
2922
2923 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2924 uint64_t fb_modifier, uint32_t pixel_format)
2925 {
2926 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2927 return 64;
2928 } else {
2929 int cpp = drm_format_plane_cpp(pixel_format, 0);
2930
2931 return intel_tile_width(dev_priv, fb_modifier, cpp);
2932 }
2933 }
2934
2935 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2936 struct drm_i915_gem_object *obj,
2937 unsigned int plane)
2938 {
2939 struct i915_ggtt_view view;
2940 struct i915_vma *vma;
2941 u64 offset;
2942
2943 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2944 intel_plane->base.state);
2945
2946 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2947 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2948 view.type))
2949 return -1;
2950
2951 offset = vma->node.start;
2952
2953 if (plane == 1) {
2954 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2955 PAGE_SIZE;
2956 }
2957
2958 WARN_ON(upper_32_bits(offset));
2959
2960 return lower_32_bits(offset);
2961 }
2962
2963 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2964 {
2965 struct drm_device *dev = intel_crtc->base.dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967
2968 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2969 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2970 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2971 }
2972
2973 /*
2974 * This function detaches (aka. unbinds) unused scalers in hardware
2975 */
2976 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2977 {
2978 struct intel_crtc_scaler_state *scaler_state;
2979 int i;
2980
2981 scaler_state = &intel_crtc->config->scaler_state;
2982
2983 /* loop through and disable scalers that aren't in use */
2984 for (i = 0; i < intel_crtc->num_scalers; i++) {
2985 if (!scaler_state->scalers[i].in_use)
2986 skl_detach_scaler(intel_crtc, i);
2987 }
2988 }
2989
2990 u32 skl_plane_ctl_format(uint32_t pixel_format)
2991 {
2992 switch (pixel_format) {
2993 case DRM_FORMAT_C8:
2994 return PLANE_CTL_FORMAT_INDEXED;
2995 case DRM_FORMAT_RGB565:
2996 return PLANE_CTL_FORMAT_RGB_565;
2997 case DRM_FORMAT_XBGR8888:
2998 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2999 case DRM_FORMAT_XRGB8888:
3000 return PLANE_CTL_FORMAT_XRGB_8888;
3001 /*
3002 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3003 * to be already pre-multiplied. We need to add a knob (or a different
3004 * DRM_FORMAT) for user-space to configure that.
3005 */
3006 case DRM_FORMAT_ABGR8888:
3007 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3008 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3009 case DRM_FORMAT_ARGB8888:
3010 return PLANE_CTL_FORMAT_XRGB_8888 |
3011 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3012 case DRM_FORMAT_XRGB2101010:
3013 return PLANE_CTL_FORMAT_XRGB_2101010;
3014 case DRM_FORMAT_XBGR2101010:
3015 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3016 case DRM_FORMAT_YUYV:
3017 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3018 case DRM_FORMAT_YVYU:
3019 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3020 case DRM_FORMAT_UYVY:
3021 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3022 case DRM_FORMAT_VYUY:
3023 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3024 default:
3025 MISSING_CASE(pixel_format);
3026 }
3027
3028 return 0;
3029 }
3030
3031 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3032 {
3033 switch (fb_modifier) {
3034 case DRM_FORMAT_MOD_NONE:
3035 break;
3036 case I915_FORMAT_MOD_X_TILED:
3037 return PLANE_CTL_TILED_X;
3038 case I915_FORMAT_MOD_Y_TILED:
3039 return PLANE_CTL_TILED_Y;
3040 case I915_FORMAT_MOD_Yf_TILED:
3041 return PLANE_CTL_TILED_YF;
3042 default:
3043 MISSING_CASE(fb_modifier);
3044 }
3045
3046 return 0;
3047 }
3048
3049 u32 skl_plane_ctl_rotation(unsigned int rotation)
3050 {
3051 switch (rotation) {
3052 case BIT(DRM_ROTATE_0):
3053 break;
3054 /*
3055 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3056 * while i915 HW rotation is clockwise, thats why this swapping.
3057 */
3058 case BIT(DRM_ROTATE_90):
3059 return PLANE_CTL_ROTATE_270;
3060 case BIT(DRM_ROTATE_180):
3061 return PLANE_CTL_ROTATE_180;
3062 case BIT(DRM_ROTATE_270):
3063 return PLANE_CTL_ROTATE_90;
3064 default:
3065 MISSING_CASE(rotation);
3066 }
3067
3068 return 0;
3069 }
3070
3071 static void skylake_update_primary_plane(struct drm_plane *plane,
3072 const struct intel_crtc_state *crtc_state,
3073 const struct intel_plane_state *plane_state)
3074 {
3075 struct drm_device *dev = plane->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3078 struct drm_framebuffer *fb = plane_state->base.fb;
3079 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3080 int pipe = intel_crtc->pipe;
3081 u32 plane_ctl, stride_div, stride;
3082 u32 tile_height, plane_offset, plane_size;
3083 unsigned int rotation = plane_state->base.rotation;
3084 int x_offset, y_offset;
3085 u32 surf_addr;
3086 int scaler_id = plane_state->scaler_id;
3087 int src_x = plane_state->src.x1 >> 16;
3088 int src_y = plane_state->src.y1 >> 16;
3089 int src_w = drm_rect_width(&plane_state->src) >> 16;
3090 int src_h = drm_rect_height(&plane_state->src) >> 16;
3091 int dst_x = plane_state->dst.x1;
3092 int dst_y = plane_state->dst.y1;
3093 int dst_w = drm_rect_width(&plane_state->dst);
3094 int dst_h = drm_rect_height(&plane_state->dst);
3095
3096 plane_ctl = PLANE_CTL_ENABLE |
3097 PLANE_CTL_PIPE_GAMMA_ENABLE |
3098 PLANE_CTL_PIPE_CSC_ENABLE;
3099
3100 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3101 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3102 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3103 plane_ctl |= skl_plane_ctl_rotation(rotation);
3104
3105 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3106 fb->pixel_format);
3107 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3108
3109 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3110
3111 if (intel_rotation_90_or_270(rotation)) {
3112 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3113
3114 /* stride = Surface height in tiles */
3115 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3116 stride = DIV_ROUND_UP(fb->height, tile_height);
3117 x_offset = stride * tile_height - src_y - src_h;
3118 y_offset = src_x;
3119 plane_size = (src_w - 1) << 16 | (src_h - 1);
3120 } else {
3121 stride = fb->pitches[0] / stride_div;
3122 x_offset = src_x;
3123 y_offset = src_y;
3124 plane_size = (src_h - 1) << 16 | (src_w - 1);
3125 }
3126 plane_offset = y_offset << 16 | x_offset;
3127
3128 intel_crtc->adjusted_x = x_offset;
3129 intel_crtc->adjusted_y = y_offset;
3130
3131 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3132 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3133 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3134 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3135
3136 if (scaler_id >= 0) {
3137 uint32_t ps_ctrl = 0;
3138
3139 WARN_ON(!dst_w || !dst_h);
3140 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3141 crtc_state->scaler_state.scalers[scaler_id].mode;
3142 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3143 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3144 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3145 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3146 I915_WRITE(PLANE_POS(pipe, 0), 0);
3147 } else {
3148 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3149 }
3150
3151 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3152
3153 POSTING_READ(PLANE_SURF(pipe, 0));
3154 }
3155
3156 static void skylake_disable_primary_plane(struct drm_plane *primary,
3157 struct drm_crtc *crtc)
3158 {
3159 struct drm_device *dev = crtc->dev;
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 int pipe = to_intel_crtc(crtc)->pipe;
3162
3163 if (dev_priv->fbc.deactivate)
3164 dev_priv->fbc.deactivate(dev_priv);
3165
3166 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3167 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3168 POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174 int x, int y, enum mode_set_atomic state)
3175 {
3176 /* Support for kgdboc is disabled, this needs a major rework. */
3177 DRM_ERROR("legacy panic handler not supported any more.\n");
3178
3179 return -ENODEV;
3180 }
3181
3182 static void intel_complete_page_flips(struct drm_device *dev)
3183 {
3184 struct drm_crtc *crtc;
3185
3186 for_each_crtc(dev, crtc) {
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 enum plane plane = intel_crtc->plane;
3189
3190 intel_prepare_page_flip(dev, plane);
3191 intel_finish_page_flip_plane(dev, plane);
3192 }
3193 }
3194
3195 static void intel_update_primary_planes(struct drm_device *dev)
3196 {
3197 struct drm_crtc *crtc;
3198
3199 for_each_crtc(dev, crtc) {
3200 struct intel_plane *plane = to_intel_plane(crtc->primary);
3201 struct intel_plane_state *plane_state;
3202
3203 drm_modeset_lock_crtc(crtc, &plane->base);
3204 plane_state = to_intel_plane_state(plane->base.state);
3205
3206 if (plane_state->visible)
3207 plane->update_plane(&plane->base,
3208 to_intel_crtc_state(crtc->state),
3209 plane_state);
3210
3211 drm_modeset_unlock_crtc(crtc);
3212 }
3213 }
3214
3215 void intel_prepare_reset(struct drm_device *dev)
3216 {
3217 /* no reset support for gen2 */
3218 if (IS_GEN2(dev))
3219 return;
3220
3221 /* reset doesn't touch the display */
3222 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3223 return;
3224
3225 drm_modeset_lock_all(dev);
3226 /*
3227 * Disabling the crtcs gracefully seems nicer. Also the
3228 * g33 docs say we should at least disable all the planes.
3229 */
3230 intel_display_suspend(dev);
3231 }
3232
3233 void intel_finish_reset(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 *
3256 * FIXME: Atomic will make this obsolete since we won't schedule
3257 * CS-based flips (which might get lost in gpu resets) any more.
3258 */
3259 intel_update_primary_planes(dev);
3260 return;
3261 }
3262
3263 /*
3264 * The display has been reset as well,
3265 * so need a full re-initialization.
3266 */
3267 intel_runtime_pm_disable_interrupts(dev_priv);
3268 intel_runtime_pm_enable_interrupts(dev_priv);
3269
3270 intel_modeset_init_hw(dev);
3271
3272 spin_lock_irq(&dev_priv->irq_lock);
3273 if (dev_priv->display.hpd_irq_setup)
3274 dev_priv->display.hpd_irq_setup(dev);
3275 spin_unlock_irq(&dev_priv->irq_lock);
3276
3277 intel_display_resume(dev);
3278
3279 intel_hpd_init(dev_priv);
3280
3281 drm_modeset_unlock_all(dev);
3282 }
3283
3284 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3285 {
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 bool pending;
3290
3291 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3292 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3293 return false;
3294
3295 spin_lock_irq(&dev->event_lock);
3296 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3297 spin_unlock_irq(&dev->event_lock);
3298
3299 return pending;
3300 }
3301
3302 static void intel_update_pipe_config(struct intel_crtc *crtc,
3303 struct intel_crtc_state *old_crtc_state)
3304 {
3305 struct drm_device *dev = crtc->base.dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct intel_crtc_state *pipe_config =
3308 to_intel_crtc_state(crtc->base.state);
3309
3310 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3311 crtc->base.mode = crtc->base.state->mode;
3312
3313 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3314 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3315 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3316
3317 if (HAS_DDI(dev))
3318 intel_set_pipe_csc(&crtc->base);
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 */
3328
3329 I915_WRITE(PIPESRC(crtc->pipe),
3330 ((pipe_config->pipe_src_w - 1) << 16) |
3331 (pipe_config->pipe_src_h - 1));
3332
3333 /* on skylake this is done by detaching scalers */
3334 if (INTEL_INFO(dev)->gen >= 9) {
3335 skl_detach_scalers(crtc);
3336
3337 if (pipe_config->pch_pfit.enabled)
3338 skylake_pfit_enable(crtc);
3339 } else if (HAS_PCH_SPLIT(dev)) {
3340 if (pipe_config->pch_pfit.enabled)
3341 ironlake_pfit_enable(crtc);
3342 else if (old_crtc_state->pch_pfit.enabled)
3343 ironlake_pfit_disable(crtc, true);
3344 }
3345 }
3346
3347 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348 {
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352 int pipe = intel_crtc->pipe;
3353 i915_reg_t reg;
3354 u32 temp;
3355
3356 /* enable normal train */
3357 reg = FDI_TX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 if (IS_IVYBRIDGE(dev)) {
3360 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3361 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3362 } else {
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3365 }
3366 I915_WRITE(reg, temp);
3367
3368 reg = FDI_RX_CTL(pipe);
3369 temp = I915_READ(reg);
3370 if (HAS_PCH_CPT(dev)) {
3371 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3372 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3373 } else {
3374 temp &= ~FDI_LINK_TRAIN_NONE;
3375 temp |= FDI_LINK_TRAIN_NONE;
3376 }
3377 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3378
3379 /* wait one idle pattern time */
3380 POSTING_READ(reg);
3381 udelay(1000);
3382
3383 /* IVB wants error correction enabled */
3384 if (IS_IVYBRIDGE(dev))
3385 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3386 FDI_FE_ERRC_ENABLE);
3387 }
3388
3389 /* The FDI link training functions for ILK/Ibexpeak. */
3390 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3391 {
3392 struct drm_device *dev = crtc->dev;
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395 int pipe = intel_crtc->pipe;
3396 i915_reg_t reg;
3397 u32 temp, tries;
3398
3399 /* FDI needs bits from pipe first */
3400 assert_pipe_enabled(dev_priv, pipe);
3401
3402 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403 for train result */
3404 reg = FDI_RX_IMR(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~FDI_RX_SYMBOL_LOCK;
3407 temp &= ~FDI_RX_BIT_LOCK;
3408 I915_WRITE(reg, temp);
3409 I915_READ(reg);
3410 udelay(150);
3411
3412 /* enable CPU FDI TX and PCH FDI RX */
3413 reg = FDI_TX_CTL(pipe);
3414 temp = I915_READ(reg);
3415 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3416 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3420
3421 reg = FDI_RX_CTL(pipe);
3422 temp = I915_READ(reg);
3423 temp &= ~FDI_LINK_TRAIN_NONE;
3424 temp |= FDI_LINK_TRAIN_PATTERN_1;
3425 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427 POSTING_READ(reg);
3428 udelay(150);
3429
3430 /* Ironlake workaround, enable clock pointer after FDI enable*/
3431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433 FDI_RX_PHASE_SYNC_POINTER_EN);
3434
3435 reg = FDI_RX_IIR(pipe);
3436 for (tries = 0; tries < 5; tries++) {
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440 if ((temp & FDI_RX_BIT_LOCK)) {
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443 break;
3444 }
3445 }
3446 if (tries == 5)
3447 DRM_ERROR("FDI train 1 fail!\n");
3448
3449 /* Train 2 */
3450 reg = FDI_TX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_2;
3454 I915_WRITE(reg, temp);
3455
3456 reg = FDI_RX_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~FDI_LINK_TRAIN_NONE;
3459 temp |= FDI_LINK_TRAIN_PATTERN_2;
3460 I915_WRITE(reg, temp);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 reg = FDI_RX_IIR(pipe);
3466 for (tries = 0; tries < 5; tries++) {
3467 temp = I915_READ(reg);
3468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470 if (temp & FDI_RX_SYMBOL_LOCK) {
3471 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3472 DRM_DEBUG_KMS("FDI train 2 done.\n");
3473 break;
3474 }
3475 }
3476 if (tries == 5)
3477 DRM_ERROR("FDI train 2 fail!\n");
3478
3479 DRM_DEBUG_KMS("FDI train done\n");
3480
3481 }
3482
3483 static const int snb_b_fdi_train_param[] = {
3484 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488 };
3489
3490 /* The FDI link training functions for SNB/Cougarpoint. */
3491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492 {
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496 int pipe = intel_crtc->pipe;
3497 i915_reg_t reg;
3498 u32 temp, i, retry;
3499
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
3509 udelay(150);
3510
3511 /* enable CPU FDI TX and PCH FDI RX */
3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3522
3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
3538 udelay(150);
3539
3540 for (i = 0; i < 4; i++) {
3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
3548 udelay(500);
3549
3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
3560 }
3561 if (retry < 5)
3562 break;
3563 }
3564 if (i == 4)
3565 DRM_ERROR("FDI train 1 fail!\n");
3566
3567 /* Train 2 */
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
3577 I915_WRITE(reg, temp);
3578
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
3591 udelay(150);
3592
3593 for (i = 0; i < 4; i++) {
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(500);
3602
3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
3613 }
3614 if (retry < 5)
3615 break;
3616 }
3617 if (i == 4)
3618 DRM_ERROR("FDI train 2 fail!\n");
3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621 }
3622
3623 /* Manual link training for Ivy Bridge A0 parts */
3624 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625 {
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
3630 i915_reg_t reg;
3631 u32 temp, i, j;
3632
3633 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3634 for train result */
3635 reg = FDI_RX_IMR(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_RX_SYMBOL_LOCK;
3638 temp &= ~FDI_RX_BIT_LOCK;
3639 I915_WRITE(reg, temp);
3640
3641 POSTING_READ(reg);
3642 udelay(150);
3643
3644 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3645 I915_READ(FDI_RX_IIR(pipe)));
3646
3647 /* Try each vswing and preemphasis setting twice before moving on */
3648 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3649 /* disable first in case we need to retry */
3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3653 temp &= ~FDI_TX_ENABLE;
3654 I915_WRITE(reg, temp);
3655
3656 reg = FDI_RX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 temp &= ~FDI_LINK_TRAIN_AUTO;
3659 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3660 temp &= ~FDI_RX_ENABLE;
3661 I915_WRITE(reg, temp);
3662
3663 /* enable CPU FDI TX and PCH FDI RX */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3667 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3668 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3670 temp |= snb_b_fdi_train_param[j/2];
3671 temp |= FDI_COMPOSITE_SYNC;
3672 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3673
3674 I915_WRITE(FDI_RX_MISC(pipe),
3675 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3676
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3680 temp |= FDI_COMPOSITE_SYNC;
3681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3682
3683 POSTING_READ(reg);
3684 udelay(1); /* should be 0.5us */
3685
3686 for (i = 0; i < 4; i++) {
3687 reg = FDI_RX_IIR(pipe);
3688 temp = I915_READ(reg);
3689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3690
3691 if (temp & FDI_RX_BIT_LOCK ||
3692 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3693 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3694 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3695 i);
3696 break;
3697 }
3698 udelay(1); /* should be 0.5us */
3699 }
3700 if (i == 4) {
3701 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3702 continue;
3703 }
3704
3705 /* Train 2 */
3706 reg = FDI_TX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3709 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3710 I915_WRITE(reg, temp);
3711
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3715 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3716 I915_WRITE(reg, temp);
3717
3718 POSTING_READ(reg);
3719 udelay(2); /* should be 1.5us */
3720
3721 for (i = 0; i < 4; i++) {
3722 reg = FDI_RX_IIR(pipe);
3723 temp = I915_READ(reg);
3724 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3725
3726 if (temp & FDI_RX_SYMBOL_LOCK ||
3727 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3728 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3729 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3730 i);
3731 goto train_done;
3732 }
3733 udelay(2); /* should be 1.5us */
3734 }
3735 if (i == 4)
3736 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3737 }
3738
3739 train_done:
3740 DRM_DEBUG_KMS("FDI train done.\n");
3741 }
3742
3743 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3744 {
3745 struct drm_device *dev = intel_crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 int pipe = intel_crtc->pipe;
3748 i915_reg_t reg;
3749 u32 temp;
3750
3751 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3752 reg = FDI_RX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3755 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3756 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3757 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3758
3759 POSTING_READ(reg);
3760 udelay(200);
3761
3762 /* Switch from Rawclk to PCDclk */
3763 temp = I915_READ(reg);
3764 I915_WRITE(reg, temp | FDI_PCDCLK);
3765
3766 POSTING_READ(reg);
3767 udelay(200);
3768
3769 /* Enable CPU FDI TX PLL, always on for Ironlake */
3770 reg = FDI_TX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3773 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3774
3775 POSTING_READ(reg);
3776 udelay(100);
3777 }
3778 }
3779
3780 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3781 {
3782 struct drm_device *dev = intel_crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 int pipe = intel_crtc->pipe;
3785 i915_reg_t reg;
3786 u32 temp;
3787
3788 /* Switch from PCDclk to Rawclk */
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793 /* Disable CPU FDI TX PLL */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798 POSTING_READ(reg);
3799 udelay(100);
3800
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805 /* Wait for the clocks to turn off. */
3806 POSTING_READ(reg);
3807 udelay(100);
3808 }
3809
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811 {
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 int pipe = intel_crtc->pipe;
3816 i915_reg_t reg;
3817 u32 temp;
3818
3819 /* disable CPU FDI tx and PCH FDI rx */
3820 reg = FDI_TX_CTL(pipe);
3821 temp = I915_READ(reg);
3822 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3823 POSTING_READ(reg);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 temp &= ~(0x7 << 16);
3828 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3829 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3830
3831 POSTING_READ(reg);
3832 udelay(100);
3833
3834 /* Ironlake workaround, disable clock pointer after downing FDI */
3835 if (HAS_PCH_IBX(dev))
3836 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3837
3838 /* still set train pattern 1 */
3839 reg = FDI_TX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 temp &= ~FDI_LINK_TRAIN_NONE;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1;
3843 I915_WRITE(reg, temp);
3844
3845 reg = FDI_RX_CTL(pipe);
3846 temp = I915_READ(reg);
3847 if (HAS_PCH_CPT(dev)) {
3848 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850 } else {
3851 temp &= ~FDI_LINK_TRAIN_NONE;
3852 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853 }
3854 /* BPC in FDI rx is consistent with that in PIPECONF */
3855 temp &= ~(0x07 << 16);
3856 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3857 I915_WRITE(reg, temp);
3858
3859 POSTING_READ(reg);
3860 udelay(100);
3861 }
3862
3863 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3864 {
3865 struct intel_crtc *crtc;
3866
3867 /* Note that we don't need to be called with mode_config.lock here
3868 * as our list of CRTC objects is static for the lifetime of the
3869 * device and so cannot disappear as we iterate. Similarly, we can
3870 * happily treat the predicates as racy, atomic checks as userspace
3871 * cannot claim and pin a new fb without at least acquring the
3872 * struct_mutex and so serialising with us.
3873 */
3874 for_each_intel_crtc(dev, crtc) {
3875 if (atomic_read(&crtc->unpin_work_count) == 0)
3876 continue;
3877
3878 if (crtc->unpin_work)
3879 intel_wait_for_vblank(dev, crtc->pipe);
3880
3881 return true;
3882 }
3883
3884 return false;
3885 }
3886
3887 static void page_flip_completed(struct intel_crtc *intel_crtc)
3888 {
3889 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3890 struct intel_unpin_work *work = intel_crtc->unpin_work;
3891
3892 /* ensure that the unpin work is consistent wrt ->pending. */
3893 smp_rmb();
3894 intel_crtc->unpin_work = NULL;
3895
3896 if (work->event)
3897 drm_send_vblank_event(intel_crtc->base.dev,
3898 intel_crtc->pipe,
3899 work->event);
3900
3901 drm_crtc_vblank_put(&intel_crtc->base);
3902
3903 wake_up_all(&dev_priv->pending_flip_queue);
3904 queue_work(dev_priv->wq, &work->work);
3905
3906 trace_i915_flip_complete(intel_crtc->plane,
3907 work->pending_flip_obj);
3908 }
3909
3910 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3911 {
3912 struct drm_device *dev = crtc->dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 long ret;
3915
3916 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3917
3918 ret = wait_event_interruptible_timeout(
3919 dev_priv->pending_flip_queue,
3920 !intel_crtc_has_pending_flip(crtc),
3921 60*HZ);
3922
3923 if (ret < 0)
3924 return ret;
3925
3926 if (ret == 0) {
3927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928
3929 spin_lock_irq(&dev->event_lock);
3930 if (intel_crtc->unpin_work) {
3931 WARN_ONCE(1, "Removing stuck page flip\n");
3932 page_flip_completed(intel_crtc);
3933 }
3934 spin_unlock_irq(&dev->event_lock);
3935 }
3936
3937 return 0;
3938 }
3939
3940 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3941 {
3942 u32 temp;
3943
3944 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945
3946 mutex_lock(&dev_priv->sb_lock);
3947
3948 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3949 temp |= SBI_SSCCTL_DISABLE;
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3951
3952 mutex_unlock(&dev_priv->sb_lock);
3953 }
3954
3955 /* Program iCLKIP clock to the desired frequency */
3956 static void lpt_program_iclkip(struct drm_crtc *crtc)
3957 {
3958 struct drm_device *dev = crtc->dev;
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3960 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3961 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3962 u32 temp;
3963
3964 lpt_disable_iclkip(dev_priv);
3965
3966 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3967 if (clock == 20000) {
3968 auxdiv = 1;
3969 divsel = 0x41;
3970 phaseinc = 0x20;
3971 } else {
3972 /* The iCLK virtual clock root frequency is in MHz,
3973 * but the adjusted_mode->crtc_clock in in KHz. To get the
3974 * divisors, it is necessary to divide one by another, so we
3975 * convert the virtual clock precision to KHz here for higher
3976 * precision.
3977 */
3978 u32 iclk_virtual_root_freq = 172800 * 1000;
3979 u32 iclk_pi_range = 64;
3980 u32 desired_divisor, msb_divisor_value, pi_value;
3981
3982 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3983 msb_divisor_value = desired_divisor / iclk_pi_range;
3984 pi_value = desired_divisor % iclk_pi_range;
3985
3986 auxdiv = 0;
3987 divsel = msb_divisor_value - 2;
3988 phaseinc = pi_value;
3989 }
3990
3991 /* This should not happen with any sane values */
3992 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3993 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3994 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3995 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3996
3997 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3998 clock,
3999 auxdiv,
4000 divsel,
4001 phasedir,
4002 phaseinc);
4003
4004 mutex_lock(&dev_priv->sb_lock);
4005
4006 /* Program SSCDIVINTPHASE6 */
4007 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4008 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4009 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4010 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4011 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4012 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4013 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4014 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4015
4016 /* Program SSCAUXDIV */
4017 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4018 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4019 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4020 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4021
4022 /* Enable modulator and associated divider */
4023 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4024 temp &= ~SBI_SSCCTL_DISABLE;
4025 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4026
4027 mutex_unlock(&dev_priv->sb_lock);
4028
4029 /* Wait for initialization time */
4030 udelay(24);
4031
4032 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4033 }
4034
4035 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4036 enum pipe pch_transcoder)
4037 {
4038 struct drm_device *dev = crtc->base.dev;
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4041
4042 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4043 I915_READ(HTOTAL(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4045 I915_READ(HBLANK(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4047 I915_READ(HSYNC(cpu_transcoder)));
4048
4049 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4050 I915_READ(VTOTAL(cpu_transcoder)));
4051 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4052 I915_READ(VBLANK(cpu_transcoder)));
4053 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4054 I915_READ(VSYNC(cpu_transcoder)));
4055 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4056 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4057 }
4058
4059 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4060 {
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 uint32_t temp;
4063
4064 temp = I915_READ(SOUTH_CHICKEN1);
4065 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4066 return;
4067
4068 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4070
4071 temp &= ~FDI_BC_BIFURCATION_SELECT;
4072 if (enable)
4073 temp |= FDI_BC_BIFURCATION_SELECT;
4074
4075 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4076 I915_WRITE(SOUTH_CHICKEN1, temp);
4077 POSTING_READ(SOUTH_CHICKEN1);
4078 }
4079
4080 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4081 {
4082 struct drm_device *dev = intel_crtc->base.dev;
4083
4084 switch (intel_crtc->pipe) {
4085 case PIPE_A:
4086 break;
4087 case PIPE_B:
4088 if (intel_crtc->config->fdi_lanes > 2)
4089 cpt_set_fdi_bc_bifurcation(dev, false);
4090 else
4091 cpt_set_fdi_bc_bifurcation(dev, true);
4092
4093 break;
4094 case PIPE_C:
4095 cpt_set_fdi_bc_bifurcation(dev, true);
4096
4097 break;
4098 default:
4099 BUG();
4100 }
4101 }
4102
4103 /* Return which DP Port should be selected for Transcoder DP control */
4104 static enum port
4105 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4106 {
4107 struct drm_device *dev = crtc->dev;
4108 struct intel_encoder *encoder;
4109
4110 for_each_encoder_on_crtc(dev, crtc, encoder) {
4111 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4112 encoder->type == INTEL_OUTPUT_EDP)
4113 return enc_to_dig_port(&encoder->base)->port;
4114 }
4115
4116 return -1;
4117 }
4118
4119 /*
4120 * Enable PCH resources required for PCH ports:
4121 * - PCH PLLs
4122 * - FDI training & RX/TX
4123 * - update transcoder timings
4124 * - DP transcoding bits
4125 * - transcoder
4126 */
4127 static void ironlake_pch_enable(struct drm_crtc *crtc)
4128 {
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132 int pipe = intel_crtc->pipe;
4133 u32 temp;
4134
4135 assert_pch_transcoder_disabled(dev_priv, pipe);
4136
4137 if (IS_IVYBRIDGE(dev))
4138 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4139
4140 /* Write the TU size bits before fdi link training, so that error
4141 * detection works. */
4142 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4143 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4144
4145 /*
4146 * Sometimes spurious CPU pipe underruns happen during FDI
4147 * training, at least with VGA+HDMI cloning. Suppress them.
4148 */
4149 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4150
4151 /* For PCH output, training FDI link */
4152 dev_priv->display.fdi_link_train(crtc);
4153
4154 /* We need to program the right clock selection before writing the pixel
4155 * mutliplier into the DPLL. */
4156 if (HAS_PCH_CPT(dev)) {
4157 u32 sel;
4158
4159 temp = I915_READ(PCH_DPLL_SEL);
4160 temp |= TRANS_DPLL_ENABLE(pipe);
4161 sel = TRANS_DPLLB_SEL(pipe);
4162 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4163 temp |= sel;
4164 else
4165 temp &= ~sel;
4166 I915_WRITE(PCH_DPLL_SEL, temp);
4167 }
4168
4169 /* XXX: pch pll's can be enabled any time before we enable the PCH
4170 * transcoder, and we actually should do this to not upset any PCH
4171 * transcoder that already use the clock when we share it.
4172 *
4173 * Note that enable_shared_dpll tries to do the right thing, but
4174 * get_shared_dpll unconditionally resets the pll - we need that to have
4175 * the right LVDS enable sequence. */
4176 intel_enable_shared_dpll(intel_crtc);
4177
4178 /* set transcoder timing, panel must allow it */
4179 assert_panel_unlocked(dev_priv, pipe);
4180 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4181
4182 intel_fdi_normal_train(crtc);
4183
4184 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4185
4186 /* For PCH DP, enable TRANS_DP_CTL */
4187 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4188 const struct drm_display_mode *adjusted_mode =
4189 &intel_crtc->config->base.adjusted_mode;
4190 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4191 i915_reg_t reg = TRANS_DP_CTL(pipe);
4192 temp = I915_READ(reg);
4193 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4194 TRANS_DP_SYNC_MASK |
4195 TRANS_DP_BPC_MASK);
4196 temp |= TRANS_DP_OUTPUT_ENABLE;
4197 temp |= bpc << 9; /* same format but at 11:9 */
4198
4199 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4200 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4201 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4202 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4203
4204 switch (intel_trans_dp_port_sel(crtc)) {
4205 case PORT_B:
4206 temp |= TRANS_DP_PORT_SEL_B;
4207 break;
4208 case PORT_C:
4209 temp |= TRANS_DP_PORT_SEL_C;
4210 break;
4211 case PORT_D:
4212 temp |= TRANS_DP_PORT_SEL_D;
4213 break;
4214 default:
4215 BUG();
4216 }
4217
4218 I915_WRITE(reg, temp);
4219 }
4220
4221 ironlake_enable_pch_transcoder(dev_priv, pipe);
4222 }
4223
4224 static void lpt_pch_enable(struct drm_crtc *crtc)
4225 {
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4230
4231 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4232
4233 lpt_program_iclkip(crtc);
4234
4235 /* Set transcoder timing. */
4236 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4237
4238 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4239 }
4240
4241 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4242 struct intel_crtc_state *crtc_state)
4243 {
4244 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4245 struct intel_shared_dpll *pll;
4246 struct intel_shared_dpll_config *shared_dpll;
4247 enum intel_dpll_id i;
4248 int max = dev_priv->num_shared_dpll;
4249
4250 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4251
4252 if (HAS_PCH_IBX(dev_priv->dev)) {
4253 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4254 i = (enum intel_dpll_id) crtc->pipe;
4255 pll = &dev_priv->shared_dplls[i];
4256
4257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4258 crtc->base.base.id, pll->name);
4259
4260 WARN_ON(shared_dpll[i].crtc_mask);
4261
4262 goto found;
4263 }
4264
4265 if (IS_BROXTON(dev_priv->dev)) {
4266 /* PLL is attached to port in bxt */
4267 struct intel_encoder *encoder;
4268 struct intel_digital_port *intel_dig_port;
4269
4270 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4271 if (WARN_ON(!encoder))
4272 return NULL;
4273
4274 intel_dig_port = enc_to_dig_port(&encoder->base);
4275 /* 1:1 mapping between ports and PLLs */
4276 i = (enum intel_dpll_id)intel_dig_port->port;
4277 pll = &dev_priv->shared_dplls[i];
4278 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4279 crtc->base.base.id, pll->name);
4280 WARN_ON(shared_dpll[i].crtc_mask);
4281
4282 goto found;
4283 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4284 /* Do not consider SPLL */
4285 max = 2;
4286
4287 for (i = 0; i < max; i++) {
4288 pll = &dev_priv->shared_dplls[i];
4289
4290 /* Only want to check enabled timings first */
4291 if (shared_dpll[i].crtc_mask == 0)
4292 continue;
4293
4294 if (memcmp(&crtc_state->dpll_hw_state,
4295 &shared_dpll[i].hw_state,
4296 sizeof(crtc_state->dpll_hw_state)) == 0) {
4297 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4298 crtc->base.base.id, pll->name,
4299 shared_dpll[i].crtc_mask,
4300 pll->active);
4301 goto found;
4302 }
4303 }
4304
4305 /* Ok no matching timings, maybe there's a free one? */
4306 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4307 pll = &dev_priv->shared_dplls[i];
4308 if (shared_dpll[i].crtc_mask == 0) {
4309 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4310 crtc->base.base.id, pll->name);
4311 goto found;
4312 }
4313 }
4314
4315 return NULL;
4316
4317 found:
4318 if (shared_dpll[i].crtc_mask == 0)
4319 shared_dpll[i].hw_state =
4320 crtc_state->dpll_hw_state;
4321
4322 crtc_state->shared_dpll = i;
4323 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4324 pipe_name(crtc->pipe));
4325
4326 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4327
4328 return pll;
4329 }
4330
4331 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4332 {
4333 struct drm_i915_private *dev_priv = to_i915(state->dev);
4334 struct intel_shared_dpll_config *shared_dpll;
4335 struct intel_shared_dpll *pll;
4336 enum intel_dpll_id i;
4337
4338 if (!to_intel_atomic_state(state)->dpll_set)
4339 return;
4340
4341 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4342 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4343 pll = &dev_priv->shared_dplls[i];
4344 pll->config = shared_dpll[i];
4345 }
4346 }
4347
4348 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4349 {
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4351 i915_reg_t dslreg = PIPEDSL(pipe);
4352 u32 temp;
4353
4354 temp = I915_READ(dslreg);
4355 udelay(500);
4356 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4357 if (wait_for(I915_READ(dslreg) != temp, 5))
4358 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4359 }
4360 }
4361
4362 static int
4363 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4364 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4365 int src_w, int src_h, int dst_w, int dst_h)
4366 {
4367 struct intel_crtc_scaler_state *scaler_state =
4368 &crtc_state->scaler_state;
4369 struct intel_crtc *intel_crtc =
4370 to_intel_crtc(crtc_state->base.crtc);
4371 int need_scaling;
4372
4373 need_scaling = intel_rotation_90_or_270(rotation) ?
4374 (src_h != dst_w || src_w != dst_h):
4375 (src_w != dst_w || src_h != dst_h);
4376
4377 /*
4378 * if plane is being disabled or scaler is no more required or force detach
4379 * - free scaler binded to this plane/crtc
4380 * - in order to do this, update crtc->scaler_usage
4381 *
4382 * Here scaler state in crtc_state is set free so that
4383 * scaler can be assigned to other user. Actual register
4384 * update to free the scaler is done in plane/panel-fit programming.
4385 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386 */
4387 if (force_detach || !need_scaling) {
4388 if (*scaler_id >= 0) {
4389 scaler_state->scaler_users &= ~(1 << scaler_user);
4390 scaler_state->scalers[*scaler_id].in_use = 0;
4391
4392 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4393 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4394 intel_crtc->pipe, scaler_user, *scaler_id,
4395 scaler_state->scaler_users);
4396 *scaler_id = -1;
4397 }
4398 return 0;
4399 }
4400
4401 /* range checks */
4402 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4403 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4404
4405 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4406 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4407 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4408 "size is out of scaler range\n",
4409 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4410 return -EINVAL;
4411 }
4412
4413 /* mark this plane as a scaler user in crtc_state */
4414 scaler_state->scaler_users |= (1 << scaler_user);
4415 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4416 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4417 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4418 scaler_state->scaler_users);
4419
4420 return 0;
4421 }
4422
4423 /**
4424 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4425 *
4426 * @state: crtc's scaler state
4427 *
4428 * Return
4429 * 0 - scaler_usage updated successfully
4430 * error - requested scaling cannot be supported or other error condition
4431 */
4432 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4433 {
4434 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4435 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4436
4437 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4438 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4439
4440 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4441 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4442 state->pipe_src_w, state->pipe_src_h,
4443 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4444 }
4445
4446 /**
4447 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4448 *
4449 * @state: crtc's scaler state
4450 * @plane_state: atomic plane state to update
4451 *
4452 * Return
4453 * 0 - scaler_usage updated successfully
4454 * error - requested scaling cannot be supported or other error condition
4455 */
4456 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4457 struct intel_plane_state *plane_state)
4458 {
4459
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4461 struct intel_plane *intel_plane =
4462 to_intel_plane(plane_state->base.plane);
4463 struct drm_framebuffer *fb = plane_state->base.fb;
4464 int ret;
4465
4466 bool force_detach = !fb || !plane_state->visible;
4467
4468 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4469 intel_plane->base.base.id, intel_crtc->pipe,
4470 drm_plane_index(&intel_plane->base));
4471
4472 ret = skl_update_scaler(crtc_state, force_detach,
4473 drm_plane_index(&intel_plane->base),
4474 &plane_state->scaler_id,
4475 plane_state->base.rotation,
4476 drm_rect_width(&plane_state->src) >> 16,
4477 drm_rect_height(&plane_state->src) >> 16,
4478 drm_rect_width(&plane_state->dst),
4479 drm_rect_height(&plane_state->dst));
4480
4481 if (ret || plane_state->scaler_id < 0)
4482 return ret;
4483
4484 /* check colorkey */
4485 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4486 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4487 intel_plane->base.base.id);
4488 return -EINVAL;
4489 }
4490
4491 /* Check src format */
4492 switch (fb->pixel_format) {
4493 case DRM_FORMAT_RGB565:
4494 case DRM_FORMAT_XBGR8888:
4495 case DRM_FORMAT_XRGB8888:
4496 case DRM_FORMAT_ABGR8888:
4497 case DRM_FORMAT_ARGB8888:
4498 case DRM_FORMAT_XRGB2101010:
4499 case DRM_FORMAT_XBGR2101010:
4500 case DRM_FORMAT_YUYV:
4501 case DRM_FORMAT_YVYU:
4502 case DRM_FORMAT_UYVY:
4503 case DRM_FORMAT_VYUY:
4504 break;
4505 default:
4506 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4507 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4508 return -EINVAL;
4509 }
4510
4511 return 0;
4512 }
4513
4514 static void skylake_scaler_disable(struct intel_crtc *crtc)
4515 {
4516 int i;
4517
4518 for (i = 0; i < crtc->num_scalers; i++)
4519 skl_detach_scaler(crtc, i);
4520 }
4521
4522 static void skylake_pfit_enable(struct intel_crtc *crtc)
4523 {
4524 struct drm_device *dev = crtc->base.dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 int pipe = crtc->pipe;
4527 struct intel_crtc_scaler_state *scaler_state =
4528 &crtc->config->scaler_state;
4529
4530 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4531
4532 if (crtc->config->pch_pfit.enabled) {
4533 int id;
4534
4535 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4536 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4537 return;
4538 }
4539
4540 id = scaler_state->scaler_id;
4541 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4542 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4543 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4544 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4545
4546 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4547 }
4548 }
4549
4550 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4551 {
4552 struct drm_device *dev = crtc->base.dev;
4553 struct drm_i915_private *dev_priv = dev->dev_private;
4554 int pipe = crtc->pipe;
4555
4556 if (crtc->config->pch_pfit.enabled) {
4557 /* Force use of hard-coded filter coefficients
4558 * as some pre-programmed values are broken,
4559 * e.g. x201.
4560 */
4561 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4562 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4563 PF_PIPE_SEL_IVB(pipe));
4564 else
4565 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4566 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4567 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4568 }
4569 }
4570
4571 void hsw_enable_ips(struct intel_crtc *crtc)
4572 {
4573 struct drm_device *dev = crtc->base.dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575
4576 if (!crtc->config->ips_enabled)
4577 return;
4578
4579 /* We can only enable IPS after we enable a plane and wait for a vblank */
4580 intel_wait_for_vblank(dev, crtc->pipe);
4581
4582 assert_plane_enabled(dev_priv, crtc->plane);
4583 if (IS_BROADWELL(dev)) {
4584 mutex_lock(&dev_priv->rps.hw_lock);
4585 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4586 mutex_unlock(&dev_priv->rps.hw_lock);
4587 /* Quoting Art Runyan: "its not safe to expect any particular
4588 * value in IPS_CTL bit 31 after enabling IPS through the
4589 * mailbox." Moreover, the mailbox may return a bogus state,
4590 * so we need to just enable it and continue on.
4591 */
4592 } else {
4593 I915_WRITE(IPS_CTL, IPS_ENABLE);
4594 /* The bit only becomes 1 in the next vblank, so this wait here
4595 * is essentially intel_wait_for_vblank. If we don't have this
4596 * and don't wait for vblanks until the end of crtc_enable, then
4597 * the HW state readout code will complain that the expected
4598 * IPS_CTL value is not the one we read. */
4599 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4600 DRM_ERROR("Timed out waiting for IPS enable\n");
4601 }
4602 }
4603
4604 void hsw_disable_ips(struct intel_crtc *crtc)
4605 {
4606 struct drm_device *dev = crtc->base.dev;
4607 struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609 if (!crtc->config->ips_enabled)
4610 return;
4611
4612 assert_plane_enabled(dev_priv, crtc->plane);
4613 if (IS_BROADWELL(dev)) {
4614 mutex_lock(&dev_priv->rps.hw_lock);
4615 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4616 mutex_unlock(&dev_priv->rps.hw_lock);
4617 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4618 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4619 DRM_ERROR("Timed out waiting for IPS disable\n");
4620 } else {
4621 I915_WRITE(IPS_CTL, 0);
4622 POSTING_READ(IPS_CTL);
4623 }
4624
4625 /* We need to wait for a vblank before we can disable the plane. */
4626 intel_wait_for_vblank(dev, crtc->pipe);
4627 }
4628
4629 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4630 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4631 {
4632 struct drm_device *dev = crtc->dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635 enum pipe pipe = intel_crtc->pipe;
4636 int i;
4637 bool reenable_ips = false;
4638
4639 /* The clocks have to be on to load the palette. */
4640 if (!crtc->state->active)
4641 return;
4642
4643 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4644 if (intel_crtc->config->has_dsi_encoder)
4645 assert_dsi_pll_enabled(dev_priv);
4646 else
4647 assert_pll_enabled(dev_priv, pipe);
4648 }
4649
4650 /* Workaround : Do not read or write the pipe palette/gamma data while
4651 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4652 */
4653 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4654 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4655 GAMMA_MODE_MODE_SPLIT)) {
4656 hsw_disable_ips(intel_crtc);
4657 reenable_ips = true;
4658 }
4659
4660 for (i = 0; i < 256; i++) {
4661 i915_reg_t palreg;
4662
4663 if (HAS_GMCH_DISPLAY(dev))
4664 palreg = PALETTE(pipe, i);
4665 else
4666 palreg = LGC_PALETTE(pipe, i);
4667
4668 I915_WRITE(palreg,
4669 (intel_crtc->lut_r[i] << 16) |
4670 (intel_crtc->lut_g[i] << 8) |
4671 intel_crtc->lut_b[i]);
4672 }
4673
4674 if (reenable_ips)
4675 hsw_enable_ips(intel_crtc);
4676 }
4677
4678 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4679 {
4680 if (intel_crtc->overlay) {
4681 struct drm_device *dev = intel_crtc->base.dev;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684 mutex_lock(&dev->struct_mutex);
4685 dev_priv->mm.interruptible = false;
4686 (void) intel_overlay_switch_off(intel_crtc->overlay);
4687 dev_priv->mm.interruptible = true;
4688 mutex_unlock(&dev->struct_mutex);
4689 }
4690
4691 /* Let userspace switch the overlay on again. In most cases userspace
4692 * has to recompute where to put it anyway.
4693 */
4694 }
4695
4696 /**
4697 * intel_post_enable_primary - Perform operations after enabling primary plane
4698 * @crtc: the CRTC whose primary plane was just enabled
4699 *
4700 * Performs potentially sleeping operations that must be done after the primary
4701 * plane is enabled, such as updating FBC and IPS. Note that this may be
4702 * called due to an explicit primary plane update, or due to an implicit
4703 * re-enable that is caused when a sprite plane is updated to no longer
4704 * completely hide the primary plane.
4705 */
4706 static void
4707 intel_post_enable_primary(struct drm_crtc *crtc)
4708 {
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
4713
4714 /*
4715 * FIXME IPS should be fine as long as one plane is
4716 * enabled, but in practice it seems to have problems
4717 * when going from primary only to sprite only and vice
4718 * versa.
4719 */
4720 hsw_enable_ips(intel_crtc);
4721
4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So don't enable underrun reporting before at least some planes
4725 * are enabled.
4726 * FIXME: Need to fix the logic to work when we turn off all planes
4727 * but leave the pipe running.
4728 */
4729 if (IS_GEN2(dev))
4730 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4731
4732 /* Underruns don't always raise interrupts, so check manually. */
4733 intel_check_cpu_fifo_underruns(dev_priv);
4734 intel_check_pch_fifo_underruns(dev_priv);
4735 }
4736
4737 /**
4738 * intel_pre_disable_primary - Perform operations before disabling primary plane
4739 * @crtc: the CRTC whose primary plane is to be disabled
4740 *
4741 * Performs potentially sleeping operations that must be done before the
4742 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4743 * be called due to an explicit primary plane update, or due to an implicit
4744 * disable that is caused when a sprite plane completely hides the primary
4745 * plane.
4746 */
4747 static void
4748 intel_pre_disable_primary(struct drm_crtc *crtc)
4749 {
4750 struct drm_device *dev = crtc->dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
4754
4755 /*
4756 * Gen2 reports pipe underruns whenever all planes are disabled.
4757 * So diasble underrun reporting before all the planes get disabled.
4758 * FIXME: Need to fix the logic to work when we turn off all planes
4759 * but leave the pipe running.
4760 */
4761 if (IS_GEN2(dev))
4762 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4763
4764 /*
4765 * Vblank time updates from the shadow to live plane control register
4766 * are blocked if the memory self-refresh mode is active at that
4767 * moment. So to make sure the plane gets truly disabled, disable
4768 * first the self-refresh mode. The self-refresh enable bit in turn
4769 * will be checked/applied by the HW only at the next frame start
4770 * event which is after the vblank start event, so we need to have a
4771 * wait-for-vblank between disabling the plane and the pipe.
4772 */
4773 if (HAS_GMCH_DISPLAY(dev)) {
4774 intel_set_memory_cxsr(dev_priv, false);
4775 dev_priv->wm.vlv.cxsr = false;
4776 intel_wait_for_vblank(dev, pipe);
4777 }
4778
4779 /*
4780 * FIXME IPS should be fine as long as one plane is
4781 * enabled, but in practice it seems to have problems
4782 * when going from primary only to sprite only and vice
4783 * versa.
4784 */
4785 hsw_disable_ips(intel_crtc);
4786 }
4787
4788 static void intel_post_plane_update(struct intel_crtc *crtc)
4789 {
4790 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791 struct intel_crtc_state *pipe_config =
4792 to_intel_crtc_state(crtc->base.state);
4793 struct drm_device *dev = crtc->base.dev;
4794
4795 if (atomic->wait_vblank)
4796 intel_wait_for_vblank(dev, crtc->pipe);
4797
4798 intel_frontbuffer_flip(dev, atomic->fb_bits);
4799
4800 crtc->wm.cxsr_allowed = true;
4801
4802 if (pipe_config->wm_changed && pipe_config->base.active)
4803 intel_update_watermarks(&crtc->base);
4804
4805 if (atomic->update_fbc)
4806 intel_fbc_update(crtc);
4807
4808 if (atomic->post_enable_primary)
4809 intel_post_enable_primary(&crtc->base);
4810
4811 memset(atomic, 0, sizeof(*atomic));
4812 }
4813
4814 static void intel_pre_plane_update(struct intel_crtc *crtc)
4815 {
4816 struct drm_device *dev = crtc->base.dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4819 struct intel_crtc_state *pipe_config =
4820 to_intel_crtc_state(crtc->base.state);
4821
4822 if (atomic->disable_fbc)
4823 intel_fbc_deactivate(crtc);
4824
4825 if (crtc->atomic.disable_ips)
4826 hsw_disable_ips(crtc);
4827
4828 if (atomic->pre_disable_primary)
4829 intel_pre_disable_primary(&crtc->base);
4830
4831 if (pipe_config->disable_cxsr) {
4832 crtc->wm.cxsr_allowed = false;
4833 intel_set_memory_cxsr(dev_priv, false);
4834 }
4835
4836 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4837 intel_update_watermarks(&crtc->base);
4838 }
4839
4840 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4841 {
4842 struct drm_device *dev = crtc->dev;
4843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844 struct drm_plane *p;
4845 int pipe = intel_crtc->pipe;
4846
4847 intel_crtc_dpms_overlay_disable(intel_crtc);
4848
4849 drm_for_each_plane_mask(p, dev, plane_mask)
4850 to_intel_plane(p)->disable_plane(p, crtc);
4851
4852 /*
4853 * FIXME: Once we grow proper nuclear flip support out of this we need
4854 * to compute the mask of flip planes precisely. For the time being
4855 * consider this a flip to a NULL plane.
4856 */
4857 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4858 }
4859
4860 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4861 {
4862 struct drm_device *dev = crtc->dev;
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4865 struct intel_encoder *encoder;
4866 int pipe = intel_crtc->pipe;
4867
4868 if (WARN_ON(intel_crtc->active))
4869 return;
4870
4871 if (intel_crtc->config->has_pch_encoder)
4872 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4873
4874 if (intel_crtc->config->has_pch_encoder)
4875 intel_prepare_shared_dpll(intel_crtc);
4876
4877 if (intel_crtc->config->has_dp_encoder)
4878 intel_dp_set_m_n(intel_crtc, M1_N1);
4879
4880 intel_set_pipe_timings(intel_crtc);
4881
4882 if (intel_crtc->config->has_pch_encoder) {
4883 intel_cpu_transcoder_set_m_n(intel_crtc,
4884 &intel_crtc->config->fdi_m_n, NULL);
4885 }
4886
4887 ironlake_set_pipeconf(crtc);
4888
4889 intel_crtc->active = true;
4890
4891 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4892
4893 for_each_encoder_on_crtc(dev, crtc, encoder)
4894 if (encoder->pre_enable)
4895 encoder->pre_enable(encoder);
4896
4897 if (intel_crtc->config->has_pch_encoder) {
4898 /* Note: FDI PLL enabling _must_ be done before we enable the
4899 * cpu pipes, hence this is separate from all the other fdi/pch
4900 * enabling. */
4901 ironlake_fdi_pll_enable(intel_crtc);
4902 } else {
4903 assert_fdi_tx_disabled(dev_priv, pipe);
4904 assert_fdi_rx_disabled(dev_priv, pipe);
4905 }
4906
4907 ironlake_pfit_enable(intel_crtc);
4908
4909 /*
4910 * On ILK+ LUT must be loaded before the pipe is running but with
4911 * clocks enabled
4912 */
4913 intel_crtc_load_lut(crtc);
4914
4915 intel_update_watermarks(crtc);
4916 intel_enable_pipe(intel_crtc);
4917
4918 if (intel_crtc->config->has_pch_encoder)
4919 ironlake_pch_enable(crtc);
4920
4921 assert_vblank_disabled(crtc);
4922 drm_crtc_vblank_on(crtc);
4923
4924 for_each_encoder_on_crtc(dev, crtc, encoder)
4925 encoder->enable(encoder);
4926
4927 if (HAS_PCH_CPT(dev))
4928 cpt_verify_modeset(dev, intel_crtc->pipe);
4929
4930 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4931 if (intel_crtc->config->has_pch_encoder)
4932 intel_wait_for_vblank(dev, pipe);
4933 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4934
4935 intel_fbc_enable(intel_crtc);
4936 }
4937
4938 /* IPS only exists on ULT machines and is tied to pipe A. */
4939 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4940 {
4941 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4942 }
4943
4944 static void haswell_crtc_enable(struct drm_crtc *crtc)
4945 {
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_i915_private *dev_priv = dev->dev_private;
4948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949 struct intel_encoder *encoder;
4950 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4951 struct intel_crtc_state *pipe_config =
4952 to_intel_crtc_state(crtc->state);
4953
4954 if (WARN_ON(intel_crtc->active))
4955 return;
4956
4957 if (intel_crtc->config->has_pch_encoder)
4958 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4959 false);
4960
4961 if (intel_crtc_to_shared_dpll(intel_crtc))
4962 intel_enable_shared_dpll(intel_crtc);
4963
4964 if (intel_crtc->config->has_dp_encoder)
4965 intel_dp_set_m_n(intel_crtc, M1_N1);
4966
4967 intel_set_pipe_timings(intel_crtc);
4968
4969 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4970 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4971 intel_crtc->config->pixel_multiplier - 1);
4972 }
4973
4974 if (intel_crtc->config->has_pch_encoder) {
4975 intel_cpu_transcoder_set_m_n(intel_crtc,
4976 &intel_crtc->config->fdi_m_n, NULL);
4977 }
4978
4979 haswell_set_pipeconf(crtc);
4980
4981 intel_set_pipe_csc(crtc);
4982
4983 intel_crtc->active = true;
4984
4985 if (intel_crtc->config->has_pch_encoder)
4986 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4987 else
4988 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4989
4990 for_each_encoder_on_crtc(dev, crtc, encoder) {
4991 if (encoder->pre_enable)
4992 encoder->pre_enable(encoder);
4993 }
4994
4995 if (intel_crtc->config->has_pch_encoder)
4996 dev_priv->display.fdi_link_train(crtc);
4997
4998 if (!intel_crtc->config->has_dsi_encoder)
4999 intel_ddi_enable_pipe_clock(intel_crtc);
5000
5001 if (INTEL_INFO(dev)->gen >= 9)
5002 skylake_pfit_enable(intel_crtc);
5003 else
5004 ironlake_pfit_enable(intel_crtc);
5005
5006 /*
5007 * On ILK+ LUT must be loaded before the pipe is running but with
5008 * clocks enabled
5009 */
5010 intel_crtc_load_lut(crtc);
5011
5012 intel_ddi_set_pipe_settings(crtc);
5013 if (!intel_crtc->config->has_dsi_encoder)
5014 intel_ddi_enable_transcoder_func(crtc);
5015
5016 intel_update_watermarks(crtc);
5017 intel_enable_pipe(intel_crtc);
5018
5019 if (intel_crtc->config->has_pch_encoder)
5020 lpt_pch_enable(crtc);
5021
5022 if (intel_crtc->config->dp_encoder_is_mst)
5023 intel_ddi_set_vc_payload_alloc(crtc, true);
5024
5025 assert_vblank_disabled(crtc);
5026 drm_crtc_vblank_on(crtc);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder) {
5029 encoder->enable(encoder);
5030 intel_opregion_notify_encoder(encoder, true);
5031 }
5032
5033 if (intel_crtc->config->has_pch_encoder) {
5034 intel_wait_for_vblank(dev, pipe);
5035 intel_wait_for_vblank(dev, pipe);
5036 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5037 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5038 true);
5039 }
5040
5041 /* If we change the relative order between pipe/planes enabling, we need
5042 * to change the workaround. */
5043 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5044 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5045 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5047 }
5048
5049 intel_fbc_enable(intel_crtc);
5050 }
5051
5052 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5053 {
5054 struct drm_device *dev = crtc->base.dev;
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 int pipe = crtc->pipe;
5057
5058 /* To avoid upsetting the power well on haswell only disable the pfit if
5059 * it's in use. The hw state code will make sure we get this right. */
5060 if (force || crtc->config->pch_pfit.enabled) {
5061 I915_WRITE(PF_CTL(pipe), 0);
5062 I915_WRITE(PF_WIN_POS(pipe), 0);
5063 I915_WRITE(PF_WIN_SZ(pipe), 0);
5064 }
5065 }
5066
5067 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5068 {
5069 struct drm_device *dev = crtc->dev;
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5072 struct intel_encoder *encoder;
5073 int pipe = intel_crtc->pipe;
5074
5075 if (intel_crtc->config->has_pch_encoder)
5076 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5077
5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 encoder->disable(encoder);
5080
5081 drm_crtc_vblank_off(crtc);
5082 assert_vblank_disabled(crtc);
5083
5084 /*
5085 * Sometimes spurious CPU pipe underruns happen when the
5086 * pipe is already disabled, but FDI RX/TX is still enabled.
5087 * Happens at least with VGA+HDMI cloning. Suppress them.
5088 */
5089 if (intel_crtc->config->has_pch_encoder)
5090 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5091
5092 intel_disable_pipe(intel_crtc);
5093
5094 ironlake_pfit_disable(intel_crtc, false);
5095
5096 if (intel_crtc->config->has_pch_encoder) {
5097 ironlake_fdi_disable(crtc);
5098 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5099 }
5100
5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 if (encoder->post_disable)
5103 encoder->post_disable(encoder);
5104
5105 if (intel_crtc->config->has_pch_encoder) {
5106 ironlake_disable_pch_transcoder(dev_priv, pipe);
5107
5108 if (HAS_PCH_CPT(dev)) {
5109 i915_reg_t reg;
5110 u32 temp;
5111
5112 /* disable TRANS_DP_CTL */
5113 reg = TRANS_DP_CTL(pipe);
5114 temp = I915_READ(reg);
5115 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5116 TRANS_DP_PORT_SEL_MASK);
5117 temp |= TRANS_DP_PORT_SEL_NONE;
5118 I915_WRITE(reg, temp);
5119
5120 /* disable DPLL_SEL */
5121 temp = I915_READ(PCH_DPLL_SEL);
5122 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5123 I915_WRITE(PCH_DPLL_SEL, temp);
5124 }
5125
5126 ironlake_fdi_pll_disable(intel_crtc);
5127 }
5128
5129 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5130
5131 intel_fbc_disable_crtc(intel_crtc);
5132 }
5133
5134 static void haswell_crtc_disable(struct drm_crtc *crtc)
5135 {
5136 struct drm_device *dev = crtc->dev;
5137 struct drm_i915_private *dev_priv = dev->dev_private;
5138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139 struct intel_encoder *encoder;
5140 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5141
5142 if (intel_crtc->config->has_pch_encoder)
5143 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5144 false);
5145
5146 for_each_encoder_on_crtc(dev, crtc, encoder) {
5147 intel_opregion_notify_encoder(encoder, false);
5148 encoder->disable(encoder);
5149 }
5150
5151 drm_crtc_vblank_off(crtc);
5152 assert_vblank_disabled(crtc);
5153
5154 intel_disable_pipe(intel_crtc);
5155
5156 if (intel_crtc->config->dp_encoder_is_mst)
5157 intel_ddi_set_vc_payload_alloc(crtc, false);
5158
5159 if (!intel_crtc->config->has_dsi_encoder)
5160 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5161
5162 if (INTEL_INFO(dev)->gen >= 9)
5163 skylake_scaler_disable(intel_crtc);
5164 else
5165 ironlake_pfit_disable(intel_crtc, false);
5166
5167 if (!intel_crtc->config->has_dsi_encoder)
5168 intel_ddi_disable_pipe_clock(intel_crtc);
5169
5170 for_each_encoder_on_crtc(dev, crtc, encoder)
5171 if (encoder->post_disable)
5172 encoder->post_disable(encoder);
5173
5174 if (intel_crtc->config->has_pch_encoder) {
5175 lpt_disable_pch_transcoder(dev_priv);
5176 lpt_disable_iclkip(dev_priv);
5177 intel_ddi_fdi_disable(crtc);
5178
5179 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5180 true);
5181 }
5182
5183 intel_fbc_disable_crtc(intel_crtc);
5184 }
5185
5186 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5187 {
5188 struct drm_device *dev = crtc->base.dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc_state *pipe_config = crtc->config;
5191
5192 if (!pipe_config->gmch_pfit.control)
5193 return;
5194
5195 /*
5196 * The panel fitter should only be adjusted whilst the pipe is disabled,
5197 * according to register description and PRM.
5198 */
5199 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5200 assert_pipe_disabled(dev_priv, crtc->pipe);
5201
5202 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5203 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5204
5205 /* Border color in case we don't scale up to the full screen. Black by
5206 * default, change to something else for debugging. */
5207 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5208 }
5209
5210 static enum intel_display_power_domain port_to_power_domain(enum port port)
5211 {
5212 switch (port) {
5213 case PORT_A:
5214 return POWER_DOMAIN_PORT_DDI_A_LANES;
5215 case PORT_B:
5216 return POWER_DOMAIN_PORT_DDI_B_LANES;
5217 case PORT_C:
5218 return POWER_DOMAIN_PORT_DDI_C_LANES;
5219 case PORT_D:
5220 return POWER_DOMAIN_PORT_DDI_D_LANES;
5221 case PORT_E:
5222 return POWER_DOMAIN_PORT_DDI_E_LANES;
5223 default:
5224 MISSING_CASE(port);
5225 return POWER_DOMAIN_PORT_OTHER;
5226 }
5227 }
5228
5229 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5230 {
5231 switch (port) {
5232 case PORT_A:
5233 return POWER_DOMAIN_AUX_A;
5234 case PORT_B:
5235 return POWER_DOMAIN_AUX_B;
5236 case PORT_C:
5237 return POWER_DOMAIN_AUX_C;
5238 case PORT_D:
5239 return POWER_DOMAIN_AUX_D;
5240 case PORT_E:
5241 /* FIXME: Check VBT for actual wiring of PORT E */
5242 return POWER_DOMAIN_AUX_D;
5243 default:
5244 MISSING_CASE(port);
5245 return POWER_DOMAIN_AUX_A;
5246 }
5247 }
5248
5249 enum intel_display_power_domain
5250 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5251 {
5252 struct drm_device *dev = intel_encoder->base.dev;
5253 struct intel_digital_port *intel_dig_port;
5254
5255 switch (intel_encoder->type) {
5256 case INTEL_OUTPUT_UNKNOWN:
5257 /* Only DDI platforms should ever use this output type */
5258 WARN_ON_ONCE(!HAS_DDI(dev));
5259 case INTEL_OUTPUT_DISPLAYPORT:
5260 case INTEL_OUTPUT_HDMI:
5261 case INTEL_OUTPUT_EDP:
5262 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5263 return port_to_power_domain(intel_dig_port->port);
5264 case INTEL_OUTPUT_DP_MST:
5265 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5266 return port_to_power_domain(intel_dig_port->port);
5267 case INTEL_OUTPUT_ANALOG:
5268 return POWER_DOMAIN_PORT_CRT;
5269 case INTEL_OUTPUT_DSI:
5270 return POWER_DOMAIN_PORT_DSI;
5271 default:
5272 return POWER_DOMAIN_PORT_OTHER;
5273 }
5274 }
5275
5276 enum intel_display_power_domain
5277 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5278 {
5279 struct drm_device *dev = intel_encoder->base.dev;
5280 struct intel_digital_port *intel_dig_port;
5281
5282 switch (intel_encoder->type) {
5283 case INTEL_OUTPUT_UNKNOWN:
5284 case INTEL_OUTPUT_HDMI:
5285 /*
5286 * Only DDI platforms should ever use these output types.
5287 * We can get here after the HDMI detect code has already set
5288 * the type of the shared encoder. Since we can't be sure
5289 * what's the status of the given connectors, play safe and
5290 * run the DP detection too.
5291 */
5292 WARN_ON_ONCE(!HAS_DDI(dev));
5293 case INTEL_OUTPUT_DISPLAYPORT:
5294 case INTEL_OUTPUT_EDP:
5295 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5296 return port_to_aux_power_domain(intel_dig_port->port);
5297 case INTEL_OUTPUT_DP_MST:
5298 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5299 return port_to_aux_power_domain(intel_dig_port->port);
5300 default:
5301 MISSING_CASE(intel_encoder->type);
5302 return POWER_DOMAIN_AUX_A;
5303 }
5304 }
5305
5306 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5307 {
5308 struct drm_device *dev = crtc->dev;
5309 struct intel_encoder *intel_encoder;
5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311 enum pipe pipe = intel_crtc->pipe;
5312 unsigned long mask;
5313 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5314
5315 if (!crtc->state->active)
5316 return 0;
5317
5318 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5319 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5320 if (intel_crtc->config->pch_pfit.enabled ||
5321 intel_crtc->config->pch_pfit.force_thru)
5322 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5323
5324 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5325 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5326
5327 return mask;
5328 }
5329
5330 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5331 {
5332 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5334 enum intel_display_power_domain domain;
5335 unsigned long domains, new_domains, old_domains;
5336
5337 old_domains = intel_crtc->enabled_power_domains;
5338 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5339
5340 domains = new_domains & ~old_domains;
5341
5342 for_each_power_domain(domain, domains)
5343 intel_display_power_get(dev_priv, domain);
5344
5345 return old_domains & ~new_domains;
5346 }
5347
5348 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5349 unsigned long domains)
5350 {
5351 enum intel_display_power_domain domain;
5352
5353 for_each_power_domain(domain, domains)
5354 intel_display_power_put(dev_priv, domain);
5355 }
5356
5357 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5358 {
5359 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5360 struct drm_device *dev = state->dev;
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 unsigned long put_domains[I915_MAX_PIPES] = {};
5363 struct drm_crtc_state *crtc_state;
5364 struct drm_crtc *crtc;
5365 int i;
5366
5367 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5368 if (needs_modeset(crtc->state))
5369 put_domains[to_intel_crtc(crtc)->pipe] =
5370 modeset_get_crtc_power_domains(crtc);
5371 }
5372
5373 if (dev_priv->display.modeset_commit_cdclk &&
5374 intel_state->dev_cdclk != dev_priv->cdclk_freq)
5375 dev_priv->display.modeset_commit_cdclk(state);
5376
5377 for (i = 0; i < I915_MAX_PIPES; i++)
5378 if (put_domains[i])
5379 modeset_put_power_domains(dev_priv, put_domains[i]);
5380 }
5381
5382 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5383 {
5384 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5385
5386 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5387 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5388 return max_cdclk_freq;
5389 else if (IS_CHERRYVIEW(dev_priv))
5390 return max_cdclk_freq*95/100;
5391 else if (INTEL_INFO(dev_priv)->gen < 4)
5392 return 2*max_cdclk_freq*90/100;
5393 else
5394 return max_cdclk_freq*90/100;
5395 }
5396
5397 static void intel_update_max_cdclk(struct drm_device *dev)
5398 {
5399 struct drm_i915_private *dev_priv = dev->dev_private;
5400
5401 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5402 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5403
5404 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5405 dev_priv->max_cdclk_freq = 675000;
5406 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5407 dev_priv->max_cdclk_freq = 540000;
5408 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5409 dev_priv->max_cdclk_freq = 450000;
5410 else
5411 dev_priv->max_cdclk_freq = 337500;
5412 } else if (IS_BROADWELL(dev)) {
5413 /*
5414 * FIXME with extra cooling we can allow
5415 * 540 MHz for ULX and 675 Mhz for ULT.
5416 * How can we know if extra cooling is
5417 * available? PCI ID, VTB, something else?
5418 */
5419 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5420 dev_priv->max_cdclk_freq = 450000;
5421 else if (IS_BDW_ULX(dev))
5422 dev_priv->max_cdclk_freq = 450000;
5423 else if (IS_BDW_ULT(dev))
5424 dev_priv->max_cdclk_freq = 540000;
5425 else
5426 dev_priv->max_cdclk_freq = 675000;
5427 } else if (IS_CHERRYVIEW(dev)) {
5428 dev_priv->max_cdclk_freq = 320000;
5429 } else if (IS_VALLEYVIEW(dev)) {
5430 dev_priv->max_cdclk_freq = 400000;
5431 } else {
5432 /* otherwise assume cdclk is fixed */
5433 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5434 }
5435
5436 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5437
5438 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5439 dev_priv->max_cdclk_freq);
5440
5441 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5442 dev_priv->max_dotclk_freq);
5443 }
5444
5445 static void intel_update_cdclk(struct drm_device *dev)
5446 {
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448
5449 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5450 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5451 dev_priv->cdclk_freq);
5452
5453 /*
5454 * Program the gmbus_freq based on the cdclk frequency.
5455 * BSpec erroneously claims we should aim for 4MHz, but
5456 * in fact 1MHz is the correct frequency.
5457 */
5458 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5459 /*
5460 * Program the gmbus_freq based on the cdclk frequency.
5461 * BSpec erroneously claims we should aim for 4MHz, but
5462 * in fact 1MHz is the correct frequency.
5463 */
5464 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5465 }
5466
5467 if (dev_priv->max_cdclk_freq == 0)
5468 intel_update_max_cdclk(dev);
5469 }
5470
5471 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5472 {
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 uint32_t divider;
5475 uint32_t ratio;
5476 uint32_t current_freq;
5477 int ret;
5478
5479 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5480 switch (frequency) {
5481 case 144000:
5482 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5483 ratio = BXT_DE_PLL_RATIO(60);
5484 break;
5485 case 288000:
5486 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5487 ratio = BXT_DE_PLL_RATIO(60);
5488 break;
5489 case 384000:
5490 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5491 ratio = BXT_DE_PLL_RATIO(60);
5492 break;
5493 case 576000:
5494 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5495 ratio = BXT_DE_PLL_RATIO(60);
5496 break;
5497 case 624000:
5498 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5499 ratio = BXT_DE_PLL_RATIO(65);
5500 break;
5501 case 19200:
5502 /*
5503 * Bypass frequency with DE PLL disabled. Init ratio, divider
5504 * to suppress GCC warning.
5505 */
5506 ratio = 0;
5507 divider = 0;
5508 break;
5509 default:
5510 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5511
5512 return;
5513 }
5514
5515 mutex_lock(&dev_priv->rps.hw_lock);
5516 /* Inform power controller of upcoming frequency change */
5517 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5518 0x80000000);
5519 mutex_unlock(&dev_priv->rps.hw_lock);
5520
5521 if (ret) {
5522 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5523 ret, frequency);
5524 return;
5525 }
5526
5527 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5528 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5529 current_freq = current_freq * 500 + 1000;
5530
5531 /*
5532 * DE PLL has to be disabled when
5533 * - setting to 19.2MHz (bypass, PLL isn't used)
5534 * - before setting to 624MHz (PLL needs toggling)
5535 * - before setting to any frequency from 624MHz (PLL needs toggling)
5536 */
5537 if (frequency == 19200 || frequency == 624000 ||
5538 current_freq == 624000) {
5539 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5540 /* Timeout 200us */
5541 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5542 1))
5543 DRM_ERROR("timout waiting for DE PLL unlock\n");
5544 }
5545
5546 if (frequency != 19200) {
5547 uint32_t val;
5548
5549 val = I915_READ(BXT_DE_PLL_CTL);
5550 val &= ~BXT_DE_PLL_RATIO_MASK;
5551 val |= ratio;
5552 I915_WRITE(BXT_DE_PLL_CTL, val);
5553
5554 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5555 /* Timeout 200us */
5556 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5557 DRM_ERROR("timeout waiting for DE PLL lock\n");
5558
5559 val = I915_READ(CDCLK_CTL);
5560 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5561 val |= divider;
5562 /*
5563 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5564 * enable otherwise.
5565 */
5566 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5567 if (frequency >= 500000)
5568 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5569
5570 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5571 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5572 val |= (frequency - 1000) / 500;
5573 I915_WRITE(CDCLK_CTL, val);
5574 }
5575
5576 mutex_lock(&dev_priv->rps.hw_lock);
5577 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5578 DIV_ROUND_UP(frequency, 25000));
5579 mutex_unlock(&dev_priv->rps.hw_lock);
5580
5581 if (ret) {
5582 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5583 ret, frequency);
5584 return;
5585 }
5586
5587 intel_update_cdclk(dev);
5588 }
5589
5590 void broxton_init_cdclk(struct drm_device *dev)
5591 {
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 uint32_t val;
5594
5595 /*
5596 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5597 * or else the reset will hang because there is no PCH to respond.
5598 * Move the handshake programming to initialization sequence.
5599 * Previously was left up to BIOS.
5600 */
5601 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5602 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5603 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5604
5605 /* Enable PG1 for cdclk */
5606 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5607
5608 /* check if cd clock is enabled */
5609 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5610 DRM_DEBUG_KMS("Display already initialized\n");
5611 return;
5612 }
5613
5614 /*
5615 * FIXME:
5616 * - The initial CDCLK needs to be read from VBT.
5617 * Need to make this change after VBT has changes for BXT.
5618 * - check if setting the max (or any) cdclk freq is really necessary
5619 * here, it belongs to modeset time
5620 */
5621 broxton_set_cdclk(dev, 624000);
5622
5623 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5624 POSTING_READ(DBUF_CTL);
5625
5626 udelay(10);
5627
5628 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5629 DRM_ERROR("DBuf power enable timeout!\n");
5630 }
5631
5632 void broxton_uninit_cdclk(struct drm_device *dev)
5633 {
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635
5636 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5637 POSTING_READ(DBUF_CTL);
5638
5639 udelay(10);
5640
5641 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5642 DRM_ERROR("DBuf power disable timeout!\n");
5643
5644 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5645 broxton_set_cdclk(dev, 19200);
5646
5647 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5648 }
5649
5650 static const struct skl_cdclk_entry {
5651 unsigned int freq;
5652 unsigned int vco;
5653 } skl_cdclk_frequencies[] = {
5654 { .freq = 308570, .vco = 8640 },
5655 { .freq = 337500, .vco = 8100 },
5656 { .freq = 432000, .vco = 8640 },
5657 { .freq = 450000, .vco = 8100 },
5658 { .freq = 540000, .vco = 8100 },
5659 { .freq = 617140, .vco = 8640 },
5660 { .freq = 675000, .vco = 8100 },
5661 };
5662
5663 static unsigned int skl_cdclk_decimal(unsigned int freq)
5664 {
5665 return (freq - 1000) / 500;
5666 }
5667
5668 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5669 {
5670 unsigned int i;
5671
5672 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5673 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5674
5675 if (e->freq == freq)
5676 return e->vco;
5677 }
5678
5679 return 8100;
5680 }
5681
5682 static void
5683 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5684 {
5685 unsigned int min_freq;
5686 u32 val;
5687
5688 /* select the minimum CDCLK before enabling DPLL 0 */
5689 val = I915_READ(CDCLK_CTL);
5690 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5691 val |= CDCLK_FREQ_337_308;
5692
5693 if (required_vco == 8640)
5694 min_freq = 308570;
5695 else
5696 min_freq = 337500;
5697
5698 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5699
5700 I915_WRITE(CDCLK_CTL, val);
5701 POSTING_READ(CDCLK_CTL);
5702
5703 /*
5704 * We always enable DPLL0 with the lowest link rate possible, but still
5705 * taking into account the VCO required to operate the eDP panel at the
5706 * desired frequency. The usual DP link rates operate with a VCO of
5707 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5708 * The modeset code is responsible for the selection of the exact link
5709 * rate later on, with the constraint of choosing a frequency that
5710 * works with required_vco.
5711 */
5712 val = I915_READ(DPLL_CTRL1);
5713
5714 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5715 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5716 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5717 if (required_vco == 8640)
5718 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5719 SKL_DPLL0);
5720 else
5721 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5722 SKL_DPLL0);
5723
5724 I915_WRITE(DPLL_CTRL1, val);
5725 POSTING_READ(DPLL_CTRL1);
5726
5727 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5728
5729 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5730 DRM_ERROR("DPLL0 not locked\n");
5731 }
5732
5733 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5734 {
5735 int ret;
5736 u32 val;
5737
5738 /* inform PCU we want to change CDCLK */
5739 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5740 mutex_lock(&dev_priv->rps.hw_lock);
5741 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5742 mutex_unlock(&dev_priv->rps.hw_lock);
5743
5744 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5745 }
5746
5747 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5748 {
5749 unsigned int i;
5750
5751 for (i = 0; i < 15; i++) {
5752 if (skl_cdclk_pcu_ready(dev_priv))
5753 return true;
5754 udelay(10);
5755 }
5756
5757 return false;
5758 }
5759
5760 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5761 {
5762 struct drm_device *dev = dev_priv->dev;
5763 u32 freq_select, pcu_ack;
5764
5765 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5766
5767 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5768 DRM_ERROR("failed to inform PCU about cdclk change\n");
5769 return;
5770 }
5771
5772 /* set CDCLK_CTL */
5773 switch(freq) {
5774 case 450000:
5775 case 432000:
5776 freq_select = CDCLK_FREQ_450_432;
5777 pcu_ack = 1;
5778 break;
5779 case 540000:
5780 freq_select = CDCLK_FREQ_540;
5781 pcu_ack = 2;
5782 break;
5783 case 308570:
5784 case 337500:
5785 default:
5786 freq_select = CDCLK_FREQ_337_308;
5787 pcu_ack = 0;
5788 break;
5789 case 617140:
5790 case 675000:
5791 freq_select = CDCLK_FREQ_675_617;
5792 pcu_ack = 3;
5793 break;
5794 }
5795
5796 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5797 POSTING_READ(CDCLK_CTL);
5798
5799 /* inform PCU of the change */
5800 mutex_lock(&dev_priv->rps.hw_lock);
5801 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5802 mutex_unlock(&dev_priv->rps.hw_lock);
5803
5804 intel_update_cdclk(dev);
5805 }
5806
5807 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5808 {
5809 /* disable DBUF power */
5810 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5811 POSTING_READ(DBUF_CTL);
5812
5813 udelay(10);
5814
5815 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5816 DRM_ERROR("DBuf power disable timeout\n");
5817
5818 /* disable DPLL0 */
5819 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5820 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5821 DRM_ERROR("Couldn't disable DPLL0\n");
5822 }
5823
5824 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5825 {
5826 unsigned int required_vco;
5827
5828 /* DPLL0 not enabled (happens on early BIOS versions) */
5829 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5830 /* enable DPLL0 */
5831 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5832 skl_dpll0_enable(dev_priv, required_vco);
5833 }
5834
5835 /* set CDCLK to the frequency the BIOS chose */
5836 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5837
5838 /* enable DBUF power */
5839 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5840 POSTING_READ(DBUF_CTL);
5841
5842 udelay(10);
5843
5844 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5845 DRM_ERROR("DBuf power enable timeout\n");
5846 }
5847
5848 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5849 {
5850 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5851 uint32_t cdctl = I915_READ(CDCLK_CTL);
5852 int freq = dev_priv->skl_boot_cdclk;
5853
5854 /*
5855 * check if the pre-os intialized the display
5856 * There is SWF18 scratchpad register defined which is set by the
5857 * pre-os which can be used by the OS drivers to check the status
5858 */
5859 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5860 goto sanitize;
5861
5862 /* Is PLL enabled and locked ? */
5863 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5864 goto sanitize;
5865
5866 /* DPLL okay; verify the cdclock
5867 *
5868 * Noticed in some instances that the freq selection is correct but
5869 * decimal part is programmed wrong from BIOS where pre-os does not
5870 * enable display. Verify the same as well.
5871 */
5872 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5873 /* All well; nothing to sanitize */
5874 return false;
5875 sanitize:
5876 /*
5877 * As of now initialize with max cdclk till
5878 * we get dynamic cdclk support
5879 * */
5880 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5881 skl_init_cdclk(dev_priv);
5882
5883 /* we did have to sanitize */
5884 return true;
5885 }
5886
5887 /* Adjust CDclk dividers to allow high res or save power if possible */
5888 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5889 {
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 u32 val, cmd;
5892
5893 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5894 != dev_priv->cdclk_freq);
5895
5896 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5897 cmd = 2;
5898 else if (cdclk == 266667)
5899 cmd = 1;
5900 else
5901 cmd = 0;
5902
5903 mutex_lock(&dev_priv->rps.hw_lock);
5904 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5905 val &= ~DSPFREQGUAR_MASK;
5906 val |= (cmd << DSPFREQGUAR_SHIFT);
5907 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5908 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5909 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5910 50)) {
5911 DRM_ERROR("timed out waiting for CDclk change\n");
5912 }
5913 mutex_unlock(&dev_priv->rps.hw_lock);
5914
5915 mutex_lock(&dev_priv->sb_lock);
5916
5917 if (cdclk == 400000) {
5918 u32 divider;
5919
5920 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5921
5922 /* adjust cdclk divider */
5923 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5924 val &= ~CCK_FREQUENCY_VALUES;
5925 val |= divider;
5926 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5927
5928 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5929 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5930 50))
5931 DRM_ERROR("timed out waiting for CDclk change\n");
5932 }
5933
5934 /* adjust self-refresh exit latency value */
5935 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5936 val &= ~0x7f;
5937
5938 /*
5939 * For high bandwidth configs, we set a higher latency in the bunit
5940 * so that the core display fetch happens in time to avoid underruns.
5941 */
5942 if (cdclk == 400000)
5943 val |= 4500 / 250; /* 4.5 usec */
5944 else
5945 val |= 3000 / 250; /* 3.0 usec */
5946 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5947
5948 mutex_unlock(&dev_priv->sb_lock);
5949
5950 intel_update_cdclk(dev);
5951 }
5952
5953 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5954 {
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 u32 val, cmd;
5957
5958 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5959 != dev_priv->cdclk_freq);
5960
5961 switch (cdclk) {
5962 case 333333:
5963 case 320000:
5964 case 266667:
5965 case 200000:
5966 break;
5967 default:
5968 MISSING_CASE(cdclk);
5969 return;
5970 }
5971
5972 /*
5973 * Specs are full of misinformation, but testing on actual
5974 * hardware has shown that we just need to write the desired
5975 * CCK divider into the Punit register.
5976 */
5977 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5978
5979 mutex_lock(&dev_priv->rps.hw_lock);
5980 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5981 val &= ~DSPFREQGUAR_MASK_CHV;
5982 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5983 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5984 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5985 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5986 50)) {
5987 DRM_ERROR("timed out waiting for CDclk change\n");
5988 }
5989 mutex_unlock(&dev_priv->rps.hw_lock);
5990
5991 intel_update_cdclk(dev);
5992 }
5993
5994 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5995 int max_pixclk)
5996 {
5997 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5998 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5999
6000 /*
6001 * Really only a few cases to deal with, as only 4 CDclks are supported:
6002 * 200MHz
6003 * 267MHz
6004 * 320/333MHz (depends on HPLL freq)
6005 * 400MHz (VLV only)
6006 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6007 * of the lower bin and adjust if needed.
6008 *
6009 * We seem to get an unstable or solid color picture at 200MHz.
6010 * Not sure what's wrong. For now use 200MHz only when all pipes
6011 * are off.
6012 */
6013 if (!IS_CHERRYVIEW(dev_priv) &&
6014 max_pixclk > freq_320*limit/100)
6015 return 400000;
6016 else if (max_pixclk > 266667*limit/100)
6017 return freq_320;
6018 else if (max_pixclk > 0)
6019 return 266667;
6020 else
6021 return 200000;
6022 }
6023
6024 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6025 int max_pixclk)
6026 {
6027 /*
6028 * FIXME:
6029 * - remove the guardband, it's not needed on BXT
6030 * - set 19.2MHz bypass frequency if there are no active pipes
6031 */
6032 if (max_pixclk > 576000*9/10)
6033 return 624000;
6034 else if (max_pixclk > 384000*9/10)
6035 return 576000;
6036 else if (max_pixclk > 288000*9/10)
6037 return 384000;
6038 else if (max_pixclk > 144000*9/10)
6039 return 288000;
6040 else
6041 return 144000;
6042 }
6043
6044 /* Compute the max pixel clock for new configuration. Uses atomic state if
6045 * that's non-NULL, look at current state otherwise. */
6046 static int intel_mode_max_pixclk(struct drm_device *dev,
6047 struct drm_atomic_state *state)
6048 {
6049 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051 struct drm_crtc *crtc;
6052 struct drm_crtc_state *crtc_state;
6053 unsigned max_pixclk = 0, i;
6054 enum pipe pipe;
6055
6056 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6057 sizeof(intel_state->min_pixclk));
6058
6059 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6060 int pixclk = 0;
6061
6062 if (crtc_state->enable)
6063 pixclk = crtc_state->adjusted_mode.crtc_clock;
6064
6065 intel_state->min_pixclk[i] = pixclk;
6066 }
6067
6068 if (!intel_state->active_crtcs)
6069 return 0;
6070
6071 for_each_pipe(dev_priv, pipe)
6072 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6073
6074 return max_pixclk;
6075 }
6076
6077 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6078 {
6079 struct drm_device *dev = state->dev;
6080 struct drm_i915_private *dev_priv = dev->dev_private;
6081 int max_pixclk = intel_mode_max_pixclk(dev, state);
6082 struct intel_atomic_state *intel_state =
6083 to_intel_atomic_state(state);
6084
6085 if (max_pixclk < 0)
6086 return max_pixclk;
6087
6088 intel_state->cdclk = intel_state->dev_cdclk =
6089 valleyview_calc_cdclk(dev_priv, max_pixclk);
6090
6091 if (!intel_state->active_crtcs)
6092 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6093
6094 return 0;
6095 }
6096
6097 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6098 {
6099 struct drm_device *dev = state->dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101 int max_pixclk = intel_mode_max_pixclk(dev, state);
6102 struct intel_atomic_state *intel_state =
6103 to_intel_atomic_state(state);
6104
6105 if (max_pixclk < 0)
6106 return max_pixclk;
6107
6108 intel_state->cdclk = intel_state->dev_cdclk =
6109 broxton_calc_cdclk(dev_priv, max_pixclk);
6110
6111 if (!intel_state->active_crtcs)
6112 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6113
6114 return 0;
6115 }
6116
6117 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6118 {
6119 unsigned int credits, default_credits;
6120
6121 if (IS_CHERRYVIEW(dev_priv))
6122 default_credits = PFI_CREDIT(12);
6123 else
6124 default_credits = PFI_CREDIT(8);
6125
6126 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6127 /* CHV suggested value is 31 or 63 */
6128 if (IS_CHERRYVIEW(dev_priv))
6129 credits = PFI_CREDIT_63;
6130 else
6131 credits = PFI_CREDIT(15);
6132 } else {
6133 credits = default_credits;
6134 }
6135
6136 /*
6137 * WA - write default credits before re-programming
6138 * FIXME: should we also set the resend bit here?
6139 */
6140 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6141 default_credits);
6142
6143 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6144 credits | PFI_CREDIT_RESEND);
6145
6146 /*
6147 * FIXME is this guaranteed to clear
6148 * immediately or should we poll for it?
6149 */
6150 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6151 }
6152
6153 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6154 {
6155 struct drm_device *dev = old_state->dev;
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157 struct intel_atomic_state *old_intel_state =
6158 to_intel_atomic_state(old_state);
6159 unsigned req_cdclk = old_intel_state->dev_cdclk;
6160
6161 /*
6162 * FIXME: We can end up here with all power domains off, yet
6163 * with a CDCLK frequency other than the minimum. To account
6164 * for this take the PIPE-A power domain, which covers the HW
6165 * blocks needed for the following programming. This can be
6166 * removed once it's guaranteed that we get here either with
6167 * the minimum CDCLK set, or the required power domains
6168 * enabled.
6169 */
6170 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6171
6172 if (IS_CHERRYVIEW(dev))
6173 cherryview_set_cdclk(dev, req_cdclk);
6174 else
6175 valleyview_set_cdclk(dev, req_cdclk);
6176
6177 vlv_program_pfi_credits(dev_priv);
6178
6179 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6180 }
6181
6182 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6183 {
6184 struct drm_device *dev = crtc->dev;
6185 struct drm_i915_private *dev_priv = to_i915(dev);
6186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187 struct intel_encoder *encoder;
6188 int pipe = intel_crtc->pipe;
6189
6190 if (WARN_ON(intel_crtc->active))
6191 return;
6192
6193 if (intel_crtc->config->has_dp_encoder)
6194 intel_dp_set_m_n(intel_crtc, M1_N1);
6195
6196 intel_set_pipe_timings(intel_crtc);
6197
6198 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6199 struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6202 I915_WRITE(CHV_CANVAS(pipe), 0);
6203 }
6204
6205 i9xx_set_pipeconf(intel_crtc);
6206
6207 intel_crtc->active = true;
6208
6209 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6210
6211 for_each_encoder_on_crtc(dev, crtc, encoder)
6212 if (encoder->pre_pll_enable)
6213 encoder->pre_pll_enable(encoder);
6214
6215 if (!intel_crtc->config->has_dsi_encoder) {
6216 if (IS_CHERRYVIEW(dev)) {
6217 chv_prepare_pll(intel_crtc, intel_crtc->config);
6218 chv_enable_pll(intel_crtc, intel_crtc->config);
6219 } else {
6220 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6221 vlv_enable_pll(intel_crtc, intel_crtc->config);
6222 }
6223 }
6224
6225 for_each_encoder_on_crtc(dev, crtc, encoder)
6226 if (encoder->pre_enable)
6227 encoder->pre_enable(encoder);
6228
6229 i9xx_pfit_enable(intel_crtc);
6230
6231 intel_crtc_load_lut(crtc);
6232
6233 intel_enable_pipe(intel_crtc);
6234
6235 assert_vblank_disabled(crtc);
6236 drm_crtc_vblank_on(crtc);
6237
6238 for_each_encoder_on_crtc(dev, crtc, encoder)
6239 encoder->enable(encoder);
6240 }
6241
6242 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6243 {
6244 struct drm_device *dev = crtc->base.dev;
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246
6247 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6248 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6249 }
6250
6251 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6252 {
6253 struct drm_device *dev = crtc->dev;
6254 struct drm_i915_private *dev_priv = to_i915(dev);
6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256 struct intel_encoder *encoder;
6257 int pipe = intel_crtc->pipe;
6258
6259 if (WARN_ON(intel_crtc->active))
6260 return;
6261
6262 i9xx_set_pll_dividers(intel_crtc);
6263
6264 if (intel_crtc->config->has_dp_encoder)
6265 intel_dp_set_m_n(intel_crtc, M1_N1);
6266
6267 intel_set_pipe_timings(intel_crtc);
6268
6269 i9xx_set_pipeconf(intel_crtc);
6270
6271 intel_crtc->active = true;
6272
6273 if (!IS_GEN2(dev))
6274 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6275
6276 for_each_encoder_on_crtc(dev, crtc, encoder)
6277 if (encoder->pre_enable)
6278 encoder->pre_enable(encoder);
6279
6280 i9xx_enable_pll(intel_crtc);
6281
6282 i9xx_pfit_enable(intel_crtc);
6283
6284 intel_crtc_load_lut(crtc);
6285
6286 intel_update_watermarks(crtc);
6287 intel_enable_pipe(intel_crtc);
6288
6289 assert_vblank_disabled(crtc);
6290 drm_crtc_vblank_on(crtc);
6291
6292 for_each_encoder_on_crtc(dev, crtc, encoder)
6293 encoder->enable(encoder);
6294
6295 intel_fbc_enable(intel_crtc);
6296 }
6297
6298 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6299 {
6300 struct drm_device *dev = crtc->base.dev;
6301 struct drm_i915_private *dev_priv = dev->dev_private;
6302
6303 if (!crtc->config->gmch_pfit.control)
6304 return;
6305
6306 assert_pipe_disabled(dev_priv, crtc->pipe);
6307
6308 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6309 I915_READ(PFIT_CONTROL));
6310 I915_WRITE(PFIT_CONTROL, 0);
6311 }
6312
6313 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6314 {
6315 struct drm_device *dev = crtc->dev;
6316 struct drm_i915_private *dev_priv = dev->dev_private;
6317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6318 struct intel_encoder *encoder;
6319 int pipe = intel_crtc->pipe;
6320
6321 /*
6322 * On gen2 planes are double buffered but the pipe isn't, so we must
6323 * wait for planes to fully turn off before disabling the pipe.
6324 * We also need to wait on all gmch platforms because of the
6325 * self-refresh mode constraint explained above.
6326 */
6327 intel_wait_for_vblank(dev, pipe);
6328
6329 for_each_encoder_on_crtc(dev, crtc, encoder)
6330 encoder->disable(encoder);
6331
6332 drm_crtc_vblank_off(crtc);
6333 assert_vblank_disabled(crtc);
6334
6335 intel_disable_pipe(intel_crtc);
6336
6337 i9xx_pfit_disable(intel_crtc);
6338
6339 for_each_encoder_on_crtc(dev, crtc, encoder)
6340 if (encoder->post_disable)
6341 encoder->post_disable(encoder);
6342
6343 if (!intel_crtc->config->has_dsi_encoder) {
6344 if (IS_CHERRYVIEW(dev))
6345 chv_disable_pll(dev_priv, pipe);
6346 else if (IS_VALLEYVIEW(dev))
6347 vlv_disable_pll(dev_priv, pipe);
6348 else
6349 i9xx_disable_pll(intel_crtc);
6350 }
6351
6352 for_each_encoder_on_crtc(dev, crtc, encoder)
6353 if (encoder->post_pll_disable)
6354 encoder->post_pll_disable(encoder);
6355
6356 if (!IS_GEN2(dev))
6357 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6358
6359 intel_fbc_disable_crtc(intel_crtc);
6360 }
6361
6362 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6363 {
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6366 enum intel_display_power_domain domain;
6367 unsigned long domains;
6368
6369 if (!intel_crtc->active)
6370 return;
6371
6372 if (to_intel_plane_state(crtc->primary->state)->visible) {
6373 WARN_ON(intel_crtc->unpin_work);
6374
6375 intel_pre_disable_primary(crtc);
6376
6377 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6378 to_intel_plane_state(crtc->primary->state)->visible = false;
6379 }
6380
6381 dev_priv->display.crtc_disable(crtc);
6382 intel_crtc->active = false;
6383 intel_update_watermarks(crtc);
6384 intel_disable_shared_dpll(intel_crtc);
6385
6386 domains = intel_crtc->enabled_power_domains;
6387 for_each_power_domain(domain, domains)
6388 intel_display_power_put(dev_priv, domain);
6389 intel_crtc->enabled_power_domains = 0;
6390
6391 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6392 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6393 }
6394
6395 /*
6396 * turn all crtc's off, but do not adjust state
6397 * This has to be paired with a call to intel_modeset_setup_hw_state.
6398 */
6399 int intel_display_suspend(struct drm_device *dev)
6400 {
6401 struct drm_mode_config *config = &dev->mode_config;
6402 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6403 struct drm_atomic_state *state;
6404 struct drm_crtc *crtc;
6405 unsigned crtc_mask = 0;
6406 int ret = 0;
6407
6408 if (WARN_ON(!ctx))
6409 return 0;
6410
6411 lockdep_assert_held(&ctx->ww_ctx);
6412 state = drm_atomic_state_alloc(dev);
6413 if (WARN_ON(!state))
6414 return -ENOMEM;
6415
6416 state->acquire_ctx = ctx;
6417 state->allow_modeset = true;
6418
6419 for_each_crtc(dev, crtc) {
6420 struct drm_crtc_state *crtc_state =
6421 drm_atomic_get_crtc_state(state, crtc);
6422
6423 ret = PTR_ERR_OR_ZERO(crtc_state);
6424 if (ret)
6425 goto free;
6426
6427 if (!crtc_state->active)
6428 continue;
6429
6430 crtc_state->active = false;
6431 crtc_mask |= 1 << drm_crtc_index(crtc);
6432 }
6433
6434 if (crtc_mask) {
6435 ret = drm_atomic_commit(state);
6436
6437 if (!ret) {
6438 for_each_crtc(dev, crtc)
6439 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6440 crtc->state->active = true;
6441
6442 return ret;
6443 }
6444 }
6445
6446 free:
6447 if (ret)
6448 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6449 drm_atomic_state_free(state);
6450 return ret;
6451 }
6452
6453 void intel_encoder_destroy(struct drm_encoder *encoder)
6454 {
6455 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6456
6457 drm_encoder_cleanup(encoder);
6458 kfree(intel_encoder);
6459 }
6460
6461 /* Cross check the actual hw state with our own modeset state tracking (and it's
6462 * internal consistency). */
6463 static void intel_connector_check_state(struct intel_connector *connector)
6464 {
6465 struct drm_crtc *crtc = connector->base.state->crtc;
6466
6467 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6468 connector->base.base.id,
6469 connector->base.name);
6470
6471 if (connector->get_hw_state(connector)) {
6472 struct intel_encoder *encoder = connector->encoder;
6473 struct drm_connector_state *conn_state = connector->base.state;
6474
6475 I915_STATE_WARN(!crtc,
6476 "connector enabled without attached crtc\n");
6477
6478 if (!crtc)
6479 return;
6480
6481 I915_STATE_WARN(!crtc->state->active,
6482 "connector is active, but attached crtc isn't\n");
6483
6484 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6485 return;
6486
6487 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6488 "atomic encoder doesn't match attached encoder\n");
6489
6490 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6491 "attached encoder crtc differs from connector crtc\n");
6492 } else {
6493 I915_STATE_WARN(crtc && crtc->state->active,
6494 "attached crtc is active, but connector isn't\n");
6495 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6496 "best encoder set without crtc!\n");
6497 }
6498 }
6499
6500 int intel_connector_init(struct intel_connector *connector)
6501 {
6502 drm_atomic_helper_connector_reset(&connector->base);
6503
6504 if (!connector->base.state)
6505 return -ENOMEM;
6506
6507 return 0;
6508 }
6509
6510 struct intel_connector *intel_connector_alloc(void)
6511 {
6512 struct intel_connector *connector;
6513
6514 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6515 if (!connector)
6516 return NULL;
6517
6518 if (intel_connector_init(connector) < 0) {
6519 kfree(connector);
6520 return NULL;
6521 }
6522
6523 return connector;
6524 }
6525
6526 /* Simple connector->get_hw_state implementation for encoders that support only
6527 * one connector and no cloning and hence the encoder state determines the state
6528 * of the connector. */
6529 bool intel_connector_get_hw_state(struct intel_connector *connector)
6530 {
6531 enum pipe pipe = 0;
6532 struct intel_encoder *encoder = connector->encoder;
6533
6534 return encoder->get_hw_state(encoder, &pipe);
6535 }
6536
6537 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6538 {
6539 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6540 return crtc_state->fdi_lanes;
6541
6542 return 0;
6543 }
6544
6545 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6546 struct intel_crtc_state *pipe_config)
6547 {
6548 struct drm_atomic_state *state = pipe_config->base.state;
6549 struct intel_crtc *other_crtc;
6550 struct intel_crtc_state *other_crtc_state;
6551
6552 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6553 pipe_name(pipe), pipe_config->fdi_lanes);
6554 if (pipe_config->fdi_lanes > 4) {
6555 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6556 pipe_name(pipe), pipe_config->fdi_lanes);
6557 return -EINVAL;
6558 }
6559
6560 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6561 if (pipe_config->fdi_lanes > 2) {
6562 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6563 pipe_config->fdi_lanes);
6564 return -EINVAL;
6565 } else {
6566 return 0;
6567 }
6568 }
6569
6570 if (INTEL_INFO(dev)->num_pipes == 2)
6571 return 0;
6572
6573 /* Ivybridge 3 pipe is really complicated */
6574 switch (pipe) {
6575 case PIPE_A:
6576 return 0;
6577 case PIPE_B:
6578 if (pipe_config->fdi_lanes <= 2)
6579 return 0;
6580
6581 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6582 other_crtc_state =
6583 intel_atomic_get_crtc_state(state, other_crtc);
6584 if (IS_ERR(other_crtc_state))
6585 return PTR_ERR(other_crtc_state);
6586
6587 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6588 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6589 pipe_name(pipe), pipe_config->fdi_lanes);
6590 return -EINVAL;
6591 }
6592 return 0;
6593 case PIPE_C:
6594 if (pipe_config->fdi_lanes > 2) {
6595 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6596 pipe_name(pipe), pipe_config->fdi_lanes);
6597 return -EINVAL;
6598 }
6599
6600 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6601 other_crtc_state =
6602 intel_atomic_get_crtc_state(state, other_crtc);
6603 if (IS_ERR(other_crtc_state))
6604 return PTR_ERR(other_crtc_state);
6605
6606 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6607 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6608 return -EINVAL;
6609 }
6610 return 0;
6611 default:
6612 BUG();
6613 }
6614 }
6615
6616 #define RETRY 1
6617 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6618 struct intel_crtc_state *pipe_config)
6619 {
6620 struct drm_device *dev = intel_crtc->base.dev;
6621 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6622 int lane, link_bw, fdi_dotclock, ret;
6623 bool needs_recompute = false;
6624
6625 retry:
6626 /* FDI is a binary signal running at ~2.7GHz, encoding
6627 * each output octet as 10 bits. The actual frequency
6628 * is stored as a divider into a 100MHz clock, and the
6629 * mode pixel clock is stored in units of 1KHz.
6630 * Hence the bw of each lane in terms of the mode signal
6631 * is:
6632 */
6633 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6634
6635 fdi_dotclock = adjusted_mode->crtc_clock;
6636
6637 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6638 pipe_config->pipe_bpp);
6639
6640 pipe_config->fdi_lanes = lane;
6641
6642 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6643 link_bw, &pipe_config->fdi_m_n);
6644
6645 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6646 intel_crtc->pipe, pipe_config);
6647 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6648 pipe_config->pipe_bpp -= 2*3;
6649 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6650 pipe_config->pipe_bpp);
6651 needs_recompute = true;
6652 pipe_config->bw_constrained = true;
6653
6654 goto retry;
6655 }
6656
6657 if (needs_recompute)
6658 return RETRY;
6659
6660 return ret;
6661 }
6662
6663 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6664 struct intel_crtc_state *pipe_config)
6665 {
6666 if (pipe_config->pipe_bpp > 24)
6667 return false;
6668
6669 /* HSW can handle pixel rate up to cdclk? */
6670 if (IS_HASWELL(dev_priv->dev))
6671 return true;
6672
6673 /*
6674 * We compare against max which means we must take
6675 * the increased cdclk requirement into account when
6676 * calculating the new cdclk.
6677 *
6678 * Should measure whether using a lower cdclk w/o IPS
6679 */
6680 return ilk_pipe_pixel_rate(pipe_config) <=
6681 dev_priv->max_cdclk_freq * 95 / 100;
6682 }
6683
6684 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6685 struct intel_crtc_state *pipe_config)
6686 {
6687 struct drm_device *dev = crtc->base.dev;
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689
6690 pipe_config->ips_enabled = i915.enable_ips &&
6691 hsw_crtc_supports_ips(crtc) &&
6692 pipe_config_supports_ips(dev_priv, pipe_config);
6693 }
6694
6695 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6696 {
6697 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6698
6699 /* GDG double wide on either pipe, otherwise pipe A only */
6700 return INTEL_INFO(dev_priv)->gen < 4 &&
6701 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6702 }
6703
6704 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6705 struct intel_crtc_state *pipe_config)
6706 {
6707 struct drm_device *dev = crtc->base.dev;
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6710
6711 /* FIXME should check pixel clock limits on all platforms */
6712 if (INTEL_INFO(dev)->gen < 4) {
6713 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6714
6715 /*
6716 * Enable double wide mode when the dot clock
6717 * is > 90% of the (display) core speed.
6718 */
6719 if (intel_crtc_supports_double_wide(crtc) &&
6720 adjusted_mode->crtc_clock > clock_limit) {
6721 clock_limit *= 2;
6722 pipe_config->double_wide = true;
6723 }
6724
6725 if (adjusted_mode->crtc_clock > clock_limit) {
6726 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6727 adjusted_mode->crtc_clock, clock_limit,
6728 yesno(pipe_config->double_wide));
6729 return -EINVAL;
6730 }
6731 }
6732
6733 /*
6734 * Pipe horizontal size must be even in:
6735 * - DVO ganged mode
6736 * - LVDS dual channel mode
6737 * - Double wide pipe
6738 */
6739 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6740 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6741 pipe_config->pipe_src_w &= ~1;
6742
6743 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6744 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6745 */
6746 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6747 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6748 return -EINVAL;
6749
6750 if (HAS_IPS(dev))
6751 hsw_compute_ips_config(crtc, pipe_config);
6752
6753 if (pipe_config->has_pch_encoder)
6754 return ironlake_fdi_compute_config(crtc, pipe_config);
6755
6756 return 0;
6757 }
6758
6759 static int skylake_get_display_clock_speed(struct drm_device *dev)
6760 {
6761 struct drm_i915_private *dev_priv = to_i915(dev);
6762 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6763 uint32_t cdctl = I915_READ(CDCLK_CTL);
6764 uint32_t linkrate;
6765
6766 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6767 return 24000; /* 24MHz is the cd freq with NSSC ref */
6768
6769 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6770 return 540000;
6771
6772 linkrate = (I915_READ(DPLL_CTRL1) &
6773 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6774
6775 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6776 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6777 /* vco 8640 */
6778 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6779 case CDCLK_FREQ_450_432:
6780 return 432000;
6781 case CDCLK_FREQ_337_308:
6782 return 308570;
6783 case CDCLK_FREQ_675_617:
6784 return 617140;
6785 default:
6786 WARN(1, "Unknown cd freq selection\n");
6787 }
6788 } else {
6789 /* vco 8100 */
6790 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6791 case CDCLK_FREQ_450_432:
6792 return 450000;
6793 case CDCLK_FREQ_337_308:
6794 return 337500;
6795 case CDCLK_FREQ_675_617:
6796 return 675000;
6797 default:
6798 WARN(1, "Unknown cd freq selection\n");
6799 }
6800 }
6801
6802 /* error case, do as if DPLL0 isn't enabled */
6803 return 24000;
6804 }
6805
6806 static int broxton_get_display_clock_speed(struct drm_device *dev)
6807 {
6808 struct drm_i915_private *dev_priv = to_i915(dev);
6809 uint32_t cdctl = I915_READ(CDCLK_CTL);
6810 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6811 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6812 int cdclk;
6813
6814 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6815 return 19200;
6816
6817 cdclk = 19200 * pll_ratio / 2;
6818
6819 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6820 case BXT_CDCLK_CD2X_DIV_SEL_1:
6821 return cdclk; /* 576MHz or 624MHz */
6822 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6823 return cdclk * 2 / 3; /* 384MHz */
6824 case BXT_CDCLK_CD2X_DIV_SEL_2:
6825 return cdclk / 2; /* 288MHz */
6826 case BXT_CDCLK_CD2X_DIV_SEL_4:
6827 return cdclk / 4; /* 144MHz */
6828 }
6829
6830 /* error case, do as if DE PLL isn't enabled */
6831 return 19200;
6832 }
6833
6834 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 uint32_t lcpll = I915_READ(LCPLL_CTL);
6838 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6839
6840 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6841 return 800000;
6842 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6843 return 450000;
6844 else if (freq == LCPLL_CLK_FREQ_450)
6845 return 450000;
6846 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6847 return 540000;
6848 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6849 return 337500;
6850 else
6851 return 675000;
6852 }
6853
6854 static int haswell_get_display_clock_speed(struct drm_device *dev)
6855 {
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 uint32_t lcpll = I915_READ(LCPLL_CTL);
6858 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6859
6860 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6861 return 800000;
6862 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6863 return 450000;
6864 else if (freq == LCPLL_CLK_FREQ_450)
6865 return 450000;
6866 else if (IS_HSW_ULT(dev))
6867 return 337500;
6868 else
6869 return 540000;
6870 }
6871
6872 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6873 {
6874 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6875 CCK_DISPLAY_CLOCK_CONTROL);
6876 }
6877
6878 static int ilk_get_display_clock_speed(struct drm_device *dev)
6879 {
6880 return 450000;
6881 }
6882
6883 static int i945_get_display_clock_speed(struct drm_device *dev)
6884 {
6885 return 400000;
6886 }
6887
6888 static int i915_get_display_clock_speed(struct drm_device *dev)
6889 {
6890 return 333333;
6891 }
6892
6893 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6894 {
6895 return 200000;
6896 }
6897
6898 static int pnv_get_display_clock_speed(struct drm_device *dev)
6899 {
6900 u16 gcfgc = 0;
6901
6902 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6903
6904 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6905 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6906 return 266667;
6907 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6908 return 333333;
6909 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6910 return 444444;
6911 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6912 return 200000;
6913 default:
6914 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6915 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6916 return 133333;
6917 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6918 return 166667;
6919 }
6920 }
6921
6922 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6923 {
6924 u16 gcfgc = 0;
6925
6926 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6927
6928 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6929 return 133333;
6930 else {
6931 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6932 case GC_DISPLAY_CLOCK_333_MHZ:
6933 return 333333;
6934 default:
6935 case GC_DISPLAY_CLOCK_190_200_MHZ:
6936 return 190000;
6937 }
6938 }
6939 }
6940
6941 static int i865_get_display_clock_speed(struct drm_device *dev)
6942 {
6943 return 266667;
6944 }
6945
6946 static int i85x_get_display_clock_speed(struct drm_device *dev)
6947 {
6948 u16 hpllcc = 0;
6949
6950 /*
6951 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6952 * encoding is different :(
6953 * FIXME is this the right way to detect 852GM/852GMV?
6954 */
6955 if (dev->pdev->revision == 0x1)
6956 return 133333;
6957
6958 pci_bus_read_config_word(dev->pdev->bus,
6959 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6960
6961 /* Assume that the hardware is in the high speed state. This
6962 * should be the default.
6963 */
6964 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6965 case GC_CLOCK_133_200:
6966 case GC_CLOCK_133_200_2:
6967 case GC_CLOCK_100_200:
6968 return 200000;
6969 case GC_CLOCK_166_250:
6970 return 250000;
6971 case GC_CLOCK_100_133:
6972 return 133333;
6973 case GC_CLOCK_133_266:
6974 case GC_CLOCK_133_266_2:
6975 case GC_CLOCK_166_266:
6976 return 266667;
6977 }
6978
6979 /* Shouldn't happen */
6980 return 0;
6981 }
6982
6983 static int i830_get_display_clock_speed(struct drm_device *dev)
6984 {
6985 return 133333;
6986 }
6987
6988 static unsigned int intel_hpll_vco(struct drm_device *dev)
6989 {
6990 struct drm_i915_private *dev_priv = dev->dev_private;
6991 static const unsigned int blb_vco[8] = {
6992 [0] = 3200000,
6993 [1] = 4000000,
6994 [2] = 5333333,
6995 [3] = 4800000,
6996 [4] = 6400000,
6997 };
6998 static const unsigned int pnv_vco[8] = {
6999 [0] = 3200000,
7000 [1] = 4000000,
7001 [2] = 5333333,
7002 [3] = 4800000,
7003 [4] = 2666667,
7004 };
7005 static const unsigned int cl_vco[8] = {
7006 [0] = 3200000,
7007 [1] = 4000000,
7008 [2] = 5333333,
7009 [3] = 6400000,
7010 [4] = 3333333,
7011 [5] = 3566667,
7012 [6] = 4266667,
7013 };
7014 static const unsigned int elk_vco[8] = {
7015 [0] = 3200000,
7016 [1] = 4000000,
7017 [2] = 5333333,
7018 [3] = 4800000,
7019 };
7020 static const unsigned int ctg_vco[8] = {
7021 [0] = 3200000,
7022 [1] = 4000000,
7023 [2] = 5333333,
7024 [3] = 6400000,
7025 [4] = 2666667,
7026 [5] = 4266667,
7027 };
7028 const unsigned int *vco_table;
7029 unsigned int vco;
7030 uint8_t tmp = 0;
7031
7032 /* FIXME other chipsets? */
7033 if (IS_GM45(dev))
7034 vco_table = ctg_vco;
7035 else if (IS_G4X(dev))
7036 vco_table = elk_vco;
7037 else if (IS_CRESTLINE(dev))
7038 vco_table = cl_vco;
7039 else if (IS_PINEVIEW(dev))
7040 vco_table = pnv_vco;
7041 else if (IS_G33(dev))
7042 vco_table = blb_vco;
7043 else
7044 return 0;
7045
7046 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7047
7048 vco = vco_table[tmp & 0x7];
7049 if (vco == 0)
7050 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7051 else
7052 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7053
7054 return vco;
7055 }
7056
7057 static int gm45_get_display_clock_speed(struct drm_device *dev)
7058 {
7059 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7060 uint16_t tmp = 0;
7061
7062 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7063
7064 cdclk_sel = (tmp >> 12) & 0x1;
7065
7066 switch (vco) {
7067 case 2666667:
7068 case 4000000:
7069 case 5333333:
7070 return cdclk_sel ? 333333 : 222222;
7071 case 3200000:
7072 return cdclk_sel ? 320000 : 228571;
7073 default:
7074 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7075 return 222222;
7076 }
7077 }
7078
7079 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7080 {
7081 static const uint8_t div_3200[] = { 16, 10, 8 };
7082 static const uint8_t div_4000[] = { 20, 12, 10 };
7083 static const uint8_t div_5333[] = { 24, 16, 14 };
7084 const uint8_t *div_table;
7085 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7086 uint16_t tmp = 0;
7087
7088 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7089
7090 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7091
7092 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7093 goto fail;
7094
7095 switch (vco) {
7096 case 3200000:
7097 div_table = div_3200;
7098 break;
7099 case 4000000:
7100 div_table = div_4000;
7101 break;
7102 case 5333333:
7103 div_table = div_5333;
7104 break;
7105 default:
7106 goto fail;
7107 }
7108
7109 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7110
7111 fail:
7112 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7113 return 200000;
7114 }
7115
7116 static int g33_get_display_clock_speed(struct drm_device *dev)
7117 {
7118 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7119 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7120 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7121 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7122 const uint8_t *div_table;
7123 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7124 uint16_t tmp = 0;
7125
7126 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7127
7128 cdclk_sel = (tmp >> 4) & 0x7;
7129
7130 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7131 goto fail;
7132
7133 switch (vco) {
7134 case 3200000:
7135 div_table = div_3200;
7136 break;
7137 case 4000000:
7138 div_table = div_4000;
7139 break;
7140 case 4800000:
7141 div_table = div_4800;
7142 break;
7143 case 5333333:
7144 div_table = div_5333;
7145 break;
7146 default:
7147 goto fail;
7148 }
7149
7150 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7151
7152 fail:
7153 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7154 return 190476;
7155 }
7156
7157 static void
7158 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7159 {
7160 while (*num > DATA_LINK_M_N_MASK ||
7161 *den > DATA_LINK_M_N_MASK) {
7162 *num >>= 1;
7163 *den >>= 1;
7164 }
7165 }
7166
7167 static void compute_m_n(unsigned int m, unsigned int n,
7168 uint32_t *ret_m, uint32_t *ret_n)
7169 {
7170 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7171 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7172 intel_reduce_m_n_ratio(ret_m, ret_n);
7173 }
7174
7175 void
7176 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7177 int pixel_clock, int link_clock,
7178 struct intel_link_m_n *m_n)
7179 {
7180 m_n->tu = 64;
7181
7182 compute_m_n(bits_per_pixel * pixel_clock,
7183 link_clock * nlanes * 8,
7184 &m_n->gmch_m, &m_n->gmch_n);
7185
7186 compute_m_n(pixel_clock, link_clock,
7187 &m_n->link_m, &m_n->link_n);
7188 }
7189
7190 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7191 {
7192 if (i915.panel_use_ssc >= 0)
7193 return i915.panel_use_ssc != 0;
7194 return dev_priv->vbt.lvds_use_ssc
7195 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7196 }
7197
7198 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7199 int num_connectors)
7200 {
7201 struct drm_device *dev = crtc_state->base.crtc->dev;
7202 struct drm_i915_private *dev_priv = dev->dev_private;
7203 int refclk;
7204
7205 WARN_ON(!crtc_state->base.state);
7206
7207 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7208 refclk = 100000;
7209 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7210 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7211 refclk = dev_priv->vbt.lvds_ssc_freq;
7212 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7213 } else if (!IS_GEN2(dev)) {
7214 refclk = 96000;
7215 } else {
7216 refclk = 48000;
7217 }
7218
7219 return refclk;
7220 }
7221
7222 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7223 {
7224 return (1 << dpll->n) << 16 | dpll->m2;
7225 }
7226
7227 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7228 {
7229 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7230 }
7231
7232 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7233 struct intel_crtc_state *crtc_state,
7234 intel_clock_t *reduced_clock)
7235 {
7236 struct drm_device *dev = crtc->base.dev;
7237 u32 fp, fp2 = 0;
7238
7239 if (IS_PINEVIEW(dev)) {
7240 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7241 if (reduced_clock)
7242 fp2 = pnv_dpll_compute_fp(reduced_clock);
7243 } else {
7244 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7245 if (reduced_clock)
7246 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7247 }
7248
7249 crtc_state->dpll_hw_state.fp0 = fp;
7250
7251 crtc->lowfreq_avail = false;
7252 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7253 reduced_clock) {
7254 crtc_state->dpll_hw_state.fp1 = fp2;
7255 crtc->lowfreq_avail = true;
7256 } else {
7257 crtc_state->dpll_hw_state.fp1 = fp;
7258 }
7259 }
7260
7261 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7262 pipe)
7263 {
7264 u32 reg_val;
7265
7266 /*
7267 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7268 * and set it to a reasonable value instead.
7269 */
7270 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7271 reg_val &= 0xffffff00;
7272 reg_val |= 0x00000030;
7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7274
7275 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7276 reg_val &= 0x8cffffff;
7277 reg_val = 0x8c000000;
7278 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7279
7280 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7281 reg_val &= 0xffffff00;
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7283
7284 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7285 reg_val &= 0x00ffffff;
7286 reg_val |= 0xb0000000;
7287 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7288 }
7289
7290 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7291 struct intel_link_m_n *m_n)
7292 {
7293 struct drm_device *dev = crtc->base.dev;
7294 struct drm_i915_private *dev_priv = dev->dev_private;
7295 int pipe = crtc->pipe;
7296
7297 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7298 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7299 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7300 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7301 }
7302
7303 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7304 struct intel_link_m_n *m_n,
7305 struct intel_link_m_n *m2_n2)
7306 {
7307 struct drm_device *dev = crtc->base.dev;
7308 struct drm_i915_private *dev_priv = dev->dev_private;
7309 int pipe = crtc->pipe;
7310 enum transcoder transcoder = crtc->config->cpu_transcoder;
7311
7312 if (INTEL_INFO(dev)->gen >= 5) {
7313 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7314 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7315 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7316 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7317 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7318 * for gen < 8) and if DRRS is supported (to make sure the
7319 * registers are not unnecessarily accessed).
7320 */
7321 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7322 crtc->config->has_drrs) {
7323 I915_WRITE(PIPE_DATA_M2(transcoder),
7324 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7325 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7326 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7327 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7328 }
7329 } else {
7330 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7331 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7332 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7333 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7334 }
7335 }
7336
7337 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7338 {
7339 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7340
7341 if (m_n == M1_N1) {
7342 dp_m_n = &crtc->config->dp_m_n;
7343 dp_m2_n2 = &crtc->config->dp_m2_n2;
7344 } else if (m_n == M2_N2) {
7345
7346 /*
7347 * M2_N2 registers are not supported. Hence m2_n2 divider value
7348 * needs to be programmed into M1_N1.
7349 */
7350 dp_m_n = &crtc->config->dp_m2_n2;
7351 } else {
7352 DRM_ERROR("Unsupported divider value\n");
7353 return;
7354 }
7355
7356 if (crtc->config->has_pch_encoder)
7357 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7358 else
7359 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7360 }
7361
7362 static void vlv_compute_dpll(struct intel_crtc *crtc,
7363 struct intel_crtc_state *pipe_config)
7364 {
7365 u32 dpll, dpll_md;
7366
7367 /*
7368 * Enable DPIO clock input. We should never disable the reference
7369 * clock for pipe B, since VGA hotplug / manual detection depends
7370 * on it.
7371 */
7372 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7373 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7374 /* We should never disable this, set it here for state tracking */
7375 if (crtc->pipe == PIPE_B)
7376 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7377 dpll |= DPLL_VCO_ENABLE;
7378 pipe_config->dpll_hw_state.dpll = dpll;
7379
7380 dpll_md = (pipe_config->pixel_multiplier - 1)
7381 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7382 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7383 }
7384
7385 static void vlv_prepare_pll(struct intel_crtc *crtc,
7386 const struct intel_crtc_state *pipe_config)
7387 {
7388 struct drm_device *dev = crtc->base.dev;
7389 struct drm_i915_private *dev_priv = dev->dev_private;
7390 int pipe = crtc->pipe;
7391 u32 mdiv;
7392 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7393 u32 coreclk, reg_val;
7394
7395 mutex_lock(&dev_priv->sb_lock);
7396
7397 bestn = pipe_config->dpll.n;
7398 bestm1 = pipe_config->dpll.m1;
7399 bestm2 = pipe_config->dpll.m2;
7400 bestp1 = pipe_config->dpll.p1;
7401 bestp2 = pipe_config->dpll.p2;
7402
7403 /* See eDP HDMI DPIO driver vbios notes doc */
7404
7405 /* PLL B needs special handling */
7406 if (pipe == PIPE_B)
7407 vlv_pllb_recal_opamp(dev_priv, pipe);
7408
7409 /* Set up Tx target for periodic Rcomp update */
7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7411
7412 /* Disable target IRef on PLL */
7413 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7414 reg_val &= 0x00ffffff;
7415 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7416
7417 /* Disable fast lock */
7418 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7419
7420 /* Set idtafcrecal before PLL is enabled */
7421 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7422 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7423 mdiv |= ((bestn << DPIO_N_SHIFT));
7424 mdiv |= (1 << DPIO_K_SHIFT);
7425
7426 /*
7427 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7428 * but we don't support that).
7429 * Note: don't use the DAC post divider as it seems unstable.
7430 */
7431 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7433
7434 mdiv |= DPIO_ENABLE_CALIBRATION;
7435 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7436
7437 /* Set HBR and RBR LPF coefficients */
7438 if (pipe_config->port_clock == 162000 ||
7439 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7440 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7441 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7442 0x009f0003);
7443 else
7444 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7445 0x00d0000f);
7446
7447 if (pipe_config->has_dp_encoder) {
7448 /* Use SSC source */
7449 if (pipe == PIPE_A)
7450 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7451 0x0df40000);
7452 else
7453 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7454 0x0df70000);
7455 } else { /* HDMI or VGA */
7456 /* Use bend source */
7457 if (pipe == PIPE_A)
7458 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7459 0x0df70000);
7460 else
7461 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7462 0x0df40000);
7463 }
7464
7465 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7466 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7467 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7468 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7469 coreclk |= 0x01000000;
7470 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7471
7472 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7473 mutex_unlock(&dev_priv->sb_lock);
7474 }
7475
7476 static void chv_compute_dpll(struct intel_crtc *crtc,
7477 struct intel_crtc_state *pipe_config)
7478 {
7479 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7480 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7481 DPLL_VCO_ENABLE;
7482 if (crtc->pipe != PIPE_A)
7483 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7484
7485 pipe_config->dpll_hw_state.dpll_md =
7486 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7487 }
7488
7489 static void chv_prepare_pll(struct intel_crtc *crtc,
7490 const struct intel_crtc_state *pipe_config)
7491 {
7492 struct drm_device *dev = crtc->base.dev;
7493 struct drm_i915_private *dev_priv = dev->dev_private;
7494 int pipe = crtc->pipe;
7495 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7496 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7497 u32 loopfilter, tribuf_calcntr;
7498 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7499 u32 dpio_val;
7500 int vco;
7501
7502 bestn = pipe_config->dpll.n;
7503 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7504 bestm1 = pipe_config->dpll.m1;
7505 bestm2 = pipe_config->dpll.m2 >> 22;
7506 bestp1 = pipe_config->dpll.p1;
7507 bestp2 = pipe_config->dpll.p2;
7508 vco = pipe_config->dpll.vco;
7509 dpio_val = 0;
7510 loopfilter = 0;
7511
7512 /*
7513 * Enable Refclk and SSC
7514 */
7515 I915_WRITE(dpll_reg,
7516 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7517
7518 mutex_lock(&dev_priv->sb_lock);
7519
7520 /* p1 and p2 divider */
7521 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7522 5 << DPIO_CHV_S1_DIV_SHIFT |
7523 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7524 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7525 1 << DPIO_CHV_K_DIV_SHIFT);
7526
7527 /* Feedback post-divider - m2 */
7528 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7529
7530 /* Feedback refclk divider - n and m1 */
7531 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7532 DPIO_CHV_M1_DIV_BY_2 |
7533 1 << DPIO_CHV_N_DIV_SHIFT);
7534
7535 /* M2 fraction division */
7536 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7537
7538 /* M2 fraction division enable */
7539 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7540 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7541 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7542 if (bestm2_frac)
7543 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7544 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7545
7546 /* Program digital lock detect threshold */
7547 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7548 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7549 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7550 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7551 if (!bestm2_frac)
7552 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7553 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7554
7555 /* Loop filter */
7556 if (vco == 5400000) {
7557 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7558 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7559 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7560 tribuf_calcntr = 0x9;
7561 } else if (vco <= 6200000) {
7562 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7563 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7564 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7565 tribuf_calcntr = 0x9;
7566 } else if (vco <= 6480000) {
7567 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7568 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7569 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7570 tribuf_calcntr = 0x8;
7571 } else {
7572 /* Not supported. Apply the same limits as in the max case */
7573 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7574 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7575 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7576 tribuf_calcntr = 0;
7577 }
7578 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7579
7580 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7581 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7582 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7583 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7584
7585 /* AFC Recal */
7586 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7587 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7588 DPIO_AFC_RECAL);
7589
7590 mutex_unlock(&dev_priv->sb_lock);
7591 }
7592
7593 /**
7594 * vlv_force_pll_on - forcibly enable just the PLL
7595 * @dev_priv: i915 private structure
7596 * @pipe: pipe PLL to enable
7597 * @dpll: PLL configuration
7598 *
7599 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7600 * in cases where we need the PLL enabled even when @pipe is not going to
7601 * be enabled.
7602 */
7603 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7604 const struct dpll *dpll)
7605 {
7606 struct intel_crtc *crtc =
7607 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7608 struct intel_crtc_state *pipe_config;
7609
7610 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7611 if (!pipe_config)
7612 return -ENOMEM;
7613
7614 pipe_config->base.crtc = &crtc->base;
7615 pipe_config->pixel_multiplier = 1;
7616 pipe_config->dpll = *dpll;
7617
7618 if (IS_CHERRYVIEW(dev)) {
7619 chv_compute_dpll(crtc, pipe_config);
7620 chv_prepare_pll(crtc, pipe_config);
7621 chv_enable_pll(crtc, pipe_config);
7622 } else {
7623 vlv_compute_dpll(crtc, pipe_config);
7624 vlv_prepare_pll(crtc, pipe_config);
7625 vlv_enable_pll(crtc, pipe_config);
7626 }
7627
7628 kfree(pipe_config);
7629
7630 return 0;
7631 }
7632
7633 /**
7634 * vlv_force_pll_off - forcibly disable just the PLL
7635 * @dev_priv: i915 private structure
7636 * @pipe: pipe PLL to disable
7637 *
7638 * Disable the PLL for @pipe. To be used in cases where we need
7639 * the PLL enabled even when @pipe is not going to be enabled.
7640 */
7641 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7642 {
7643 if (IS_CHERRYVIEW(dev))
7644 chv_disable_pll(to_i915(dev), pipe);
7645 else
7646 vlv_disable_pll(to_i915(dev), pipe);
7647 }
7648
7649 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state,
7651 intel_clock_t *reduced_clock,
7652 int num_connectors)
7653 {
7654 struct drm_device *dev = crtc->base.dev;
7655 struct drm_i915_private *dev_priv = dev->dev_private;
7656 u32 dpll;
7657 bool is_sdvo;
7658 struct dpll *clock = &crtc_state->dpll;
7659
7660 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7661
7662 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7663 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7664
7665 dpll = DPLL_VGA_MODE_DIS;
7666
7667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7668 dpll |= DPLLB_MODE_LVDS;
7669 else
7670 dpll |= DPLLB_MODE_DAC_SERIAL;
7671
7672 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7673 dpll |= (crtc_state->pixel_multiplier - 1)
7674 << SDVO_MULTIPLIER_SHIFT_HIRES;
7675 }
7676
7677 if (is_sdvo)
7678 dpll |= DPLL_SDVO_HIGH_SPEED;
7679
7680 if (crtc_state->has_dp_encoder)
7681 dpll |= DPLL_SDVO_HIGH_SPEED;
7682
7683 /* compute bitmask from p1 value */
7684 if (IS_PINEVIEW(dev))
7685 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7686 else {
7687 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7688 if (IS_G4X(dev) && reduced_clock)
7689 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7690 }
7691 switch (clock->p2) {
7692 case 5:
7693 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7694 break;
7695 case 7:
7696 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7697 break;
7698 case 10:
7699 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7700 break;
7701 case 14:
7702 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7703 break;
7704 }
7705 if (INTEL_INFO(dev)->gen >= 4)
7706 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7707
7708 if (crtc_state->sdvo_tv_clock)
7709 dpll |= PLL_REF_INPUT_TVCLKINBC;
7710 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7711 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7712 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7713 else
7714 dpll |= PLL_REF_INPUT_DREFCLK;
7715
7716 dpll |= DPLL_VCO_ENABLE;
7717 crtc_state->dpll_hw_state.dpll = dpll;
7718
7719 if (INTEL_INFO(dev)->gen >= 4) {
7720 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7721 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7722 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7723 }
7724 }
7725
7726 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7727 struct intel_crtc_state *crtc_state,
7728 intel_clock_t *reduced_clock,
7729 int num_connectors)
7730 {
7731 struct drm_device *dev = crtc->base.dev;
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7733 u32 dpll;
7734 struct dpll *clock = &crtc_state->dpll;
7735
7736 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7737
7738 dpll = DPLL_VGA_MODE_DIS;
7739
7740 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7741 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7742 } else {
7743 if (clock->p1 == 2)
7744 dpll |= PLL_P1_DIVIDE_BY_TWO;
7745 else
7746 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7747 if (clock->p2 == 4)
7748 dpll |= PLL_P2_DIVIDE_BY_4;
7749 }
7750
7751 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7752 dpll |= DPLL_DVO_2X_MODE;
7753
7754 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7755 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7756 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7757 else
7758 dpll |= PLL_REF_INPUT_DREFCLK;
7759
7760 dpll |= DPLL_VCO_ENABLE;
7761 crtc_state->dpll_hw_state.dpll = dpll;
7762 }
7763
7764 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7765 {
7766 struct drm_device *dev = intel_crtc->base.dev;
7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768 enum pipe pipe = intel_crtc->pipe;
7769 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7770 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7771 uint32_t crtc_vtotal, crtc_vblank_end;
7772 int vsyncshift = 0;
7773
7774 /* We need to be careful not to changed the adjusted mode, for otherwise
7775 * the hw state checker will get angry at the mismatch. */
7776 crtc_vtotal = adjusted_mode->crtc_vtotal;
7777 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7778
7779 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7780 /* the chip adds 2 halflines automatically */
7781 crtc_vtotal -= 1;
7782 crtc_vblank_end -= 1;
7783
7784 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7785 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7786 else
7787 vsyncshift = adjusted_mode->crtc_hsync_start -
7788 adjusted_mode->crtc_htotal / 2;
7789 if (vsyncshift < 0)
7790 vsyncshift += adjusted_mode->crtc_htotal;
7791 }
7792
7793 if (INTEL_INFO(dev)->gen > 3)
7794 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7795
7796 I915_WRITE(HTOTAL(cpu_transcoder),
7797 (adjusted_mode->crtc_hdisplay - 1) |
7798 ((adjusted_mode->crtc_htotal - 1) << 16));
7799 I915_WRITE(HBLANK(cpu_transcoder),
7800 (adjusted_mode->crtc_hblank_start - 1) |
7801 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7802 I915_WRITE(HSYNC(cpu_transcoder),
7803 (adjusted_mode->crtc_hsync_start - 1) |
7804 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7805
7806 I915_WRITE(VTOTAL(cpu_transcoder),
7807 (adjusted_mode->crtc_vdisplay - 1) |
7808 ((crtc_vtotal - 1) << 16));
7809 I915_WRITE(VBLANK(cpu_transcoder),
7810 (adjusted_mode->crtc_vblank_start - 1) |
7811 ((crtc_vblank_end - 1) << 16));
7812 I915_WRITE(VSYNC(cpu_transcoder),
7813 (adjusted_mode->crtc_vsync_start - 1) |
7814 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7815
7816 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7817 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7818 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7819 * bits. */
7820 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7821 (pipe == PIPE_B || pipe == PIPE_C))
7822 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7823
7824 /* pipesrc controls the size that is scaled from, which should
7825 * always be the user's requested size.
7826 */
7827 I915_WRITE(PIPESRC(pipe),
7828 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7829 (intel_crtc->config->pipe_src_h - 1));
7830 }
7831
7832 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7833 struct intel_crtc_state *pipe_config)
7834 {
7835 struct drm_device *dev = crtc->base.dev;
7836 struct drm_i915_private *dev_priv = dev->dev_private;
7837 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7838 uint32_t tmp;
7839
7840 tmp = I915_READ(HTOTAL(cpu_transcoder));
7841 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7842 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7843 tmp = I915_READ(HBLANK(cpu_transcoder));
7844 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7845 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7846 tmp = I915_READ(HSYNC(cpu_transcoder));
7847 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7848 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7849
7850 tmp = I915_READ(VTOTAL(cpu_transcoder));
7851 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7852 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7853 tmp = I915_READ(VBLANK(cpu_transcoder));
7854 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7855 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7856 tmp = I915_READ(VSYNC(cpu_transcoder));
7857 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7858 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7859
7860 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7861 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7862 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7863 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7864 }
7865
7866 tmp = I915_READ(PIPESRC(crtc->pipe));
7867 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7868 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7869
7870 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7871 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7872 }
7873
7874 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7875 struct intel_crtc_state *pipe_config)
7876 {
7877 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7878 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7879 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7880 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7881
7882 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7883 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7884 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7885 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7886
7887 mode->flags = pipe_config->base.adjusted_mode.flags;
7888 mode->type = DRM_MODE_TYPE_DRIVER;
7889
7890 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7891 mode->flags |= pipe_config->base.adjusted_mode.flags;
7892
7893 mode->hsync = drm_mode_hsync(mode);
7894 mode->vrefresh = drm_mode_vrefresh(mode);
7895 drm_mode_set_name(mode);
7896 }
7897
7898 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7899 {
7900 struct drm_device *dev = intel_crtc->base.dev;
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7902 uint32_t pipeconf;
7903
7904 pipeconf = 0;
7905
7906 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7907 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7908 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7909
7910 if (intel_crtc->config->double_wide)
7911 pipeconf |= PIPECONF_DOUBLE_WIDE;
7912
7913 /* only g4x and later have fancy bpc/dither controls */
7914 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7915 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7916 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7917 pipeconf |= PIPECONF_DITHER_EN |
7918 PIPECONF_DITHER_TYPE_SP;
7919
7920 switch (intel_crtc->config->pipe_bpp) {
7921 case 18:
7922 pipeconf |= PIPECONF_6BPC;
7923 break;
7924 case 24:
7925 pipeconf |= PIPECONF_8BPC;
7926 break;
7927 case 30:
7928 pipeconf |= PIPECONF_10BPC;
7929 break;
7930 default:
7931 /* Case prevented by intel_choose_pipe_bpp_dither. */
7932 BUG();
7933 }
7934 }
7935
7936 if (HAS_PIPE_CXSR(dev)) {
7937 if (intel_crtc->lowfreq_avail) {
7938 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7939 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7940 } else {
7941 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7942 }
7943 }
7944
7945 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7946 if (INTEL_INFO(dev)->gen < 4 ||
7947 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7948 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7949 else
7950 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7951 } else
7952 pipeconf |= PIPECONF_PROGRESSIVE;
7953
7954 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7955 intel_crtc->config->limited_color_range)
7956 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7957
7958 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7959 POSTING_READ(PIPECONF(intel_crtc->pipe));
7960 }
7961
7962 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7963 struct intel_crtc_state *crtc_state)
7964 {
7965 struct drm_device *dev = crtc->base.dev;
7966 struct drm_i915_private *dev_priv = dev->dev_private;
7967 int refclk, num_connectors = 0;
7968 intel_clock_t clock;
7969 bool ok;
7970 const intel_limit_t *limit;
7971 struct drm_atomic_state *state = crtc_state->base.state;
7972 struct drm_connector *connector;
7973 struct drm_connector_state *connector_state;
7974 int i;
7975
7976 memset(&crtc_state->dpll_hw_state, 0,
7977 sizeof(crtc_state->dpll_hw_state));
7978
7979 if (crtc_state->has_dsi_encoder)
7980 return 0;
7981
7982 for_each_connector_in_state(state, connector, connector_state, i) {
7983 if (connector_state->crtc == &crtc->base)
7984 num_connectors++;
7985 }
7986
7987 if (!crtc_state->clock_set) {
7988 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7989
7990 /*
7991 * Returns a set of divisors for the desired target clock with
7992 * the given refclk, or FALSE. The returned values represent
7993 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7994 * 2) / p1 / p2.
7995 */
7996 limit = intel_limit(crtc_state, refclk);
7997 ok = dev_priv->display.find_dpll(limit, crtc_state,
7998 crtc_state->port_clock,
7999 refclk, NULL, &clock);
8000 if (!ok) {
8001 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8002 return -EINVAL;
8003 }
8004
8005 /* Compat-code for transition, will disappear. */
8006 crtc_state->dpll.n = clock.n;
8007 crtc_state->dpll.m1 = clock.m1;
8008 crtc_state->dpll.m2 = clock.m2;
8009 crtc_state->dpll.p1 = clock.p1;
8010 crtc_state->dpll.p2 = clock.p2;
8011 }
8012
8013 if (IS_GEN2(dev)) {
8014 i8xx_compute_dpll(crtc, crtc_state, NULL,
8015 num_connectors);
8016 } else if (IS_CHERRYVIEW(dev)) {
8017 chv_compute_dpll(crtc, crtc_state);
8018 } else if (IS_VALLEYVIEW(dev)) {
8019 vlv_compute_dpll(crtc, crtc_state);
8020 } else {
8021 i9xx_compute_dpll(crtc, crtc_state, NULL,
8022 num_connectors);
8023 }
8024
8025 return 0;
8026 }
8027
8028 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8029 struct intel_crtc_state *pipe_config)
8030 {
8031 struct drm_device *dev = crtc->base.dev;
8032 struct drm_i915_private *dev_priv = dev->dev_private;
8033 uint32_t tmp;
8034
8035 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8036 return;
8037
8038 tmp = I915_READ(PFIT_CONTROL);
8039 if (!(tmp & PFIT_ENABLE))
8040 return;
8041
8042 /* Check whether the pfit is attached to our pipe. */
8043 if (INTEL_INFO(dev)->gen < 4) {
8044 if (crtc->pipe != PIPE_B)
8045 return;
8046 } else {
8047 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8048 return;
8049 }
8050
8051 pipe_config->gmch_pfit.control = tmp;
8052 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8053 if (INTEL_INFO(dev)->gen < 5)
8054 pipe_config->gmch_pfit.lvds_border_bits =
8055 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8056 }
8057
8058 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8059 struct intel_crtc_state *pipe_config)
8060 {
8061 struct drm_device *dev = crtc->base.dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 int pipe = pipe_config->cpu_transcoder;
8064 intel_clock_t clock;
8065 u32 mdiv;
8066 int refclk = 100000;
8067
8068 /* In case of MIPI DPLL will not even be used */
8069 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8070 return;
8071
8072 mutex_lock(&dev_priv->sb_lock);
8073 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8074 mutex_unlock(&dev_priv->sb_lock);
8075
8076 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8077 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8078 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8079 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8080 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8081
8082 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8083 }
8084
8085 static void
8086 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8087 struct intel_initial_plane_config *plane_config)
8088 {
8089 struct drm_device *dev = crtc->base.dev;
8090 struct drm_i915_private *dev_priv = dev->dev_private;
8091 u32 val, base, offset;
8092 int pipe = crtc->pipe, plane = crtc->plane;
8093 int fourcc, pixel_format;
8094 unsigned int aligned_height;
8095 struct drm_framebuffer *fb;
8096 struct intel_framebuffer *intel_fb;
8097
8098 val = I915_READ(DSPCNTR(plane));
8099 if (!(val & DISPLAY_PLANE_ENABLE))
8100 return;
8101
8102 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8103 if (!intel_fb) {
8104 DRM_DEBUG_KMS("failed to alloc fb\n");
8105 return;
8106 }
8107
8108 fb = &intel_fb->base;
8109
8110 if (INTEL_INFO(dev)->gen >= 4) {
8111 if (val & DISPPLANE_TILED) {
8112 plane_config->tiling = I915_TILING_X;
8113 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8114 }
8115 }
8116
8117 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8118 fourcc = i9xx_format_to_fourcc(pixel_format);
8119 fb->pixel_format = fourcc;
8120 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8121
8122 if (INTEL_INFO(dev)->gen >= 4) {
8123 if (plane_config->tiling)
8124 offset = I915_READ(DSPTILEOFF(plane));
8125 else
8126 offset = I915_READ(DSPLINOFF(plane));
8127 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8128 } else {
8129 base = I915_READ(DSPADDR(plane));
8130 }
8131 plane_config->base = base;
8132
8133 val = I915_READ(PIPESRC(pipe));
8134 fb->width = ((val >> 16) & 0xfff) + 1;
8135 fb->height = ((val >> 0) & 0xfff) + 1;
8136
8137 val = I915_READ(DSPSTRIDE(pipe));
8138 fb->pitches[0] = val & 0xffffffc0;
8139
8140 aligned_height = intel_fb_align_height(dev, fb->height,
8141 fb->pixel_format,
8142 fb->modifier[0]);
8143
8144 plane_config->size = fb->pitches[0] * aligned_height;
8145
8146 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8147 pipe_name(pipe), plane, fb->width, fb->height,
8148 fb->bits_per_pixel, base, fb->pitches[0],
8149 plane_config->size);
8150
8151 plane_config->fb = intel_fb;
8152 }
8153
8154 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8155 struct intel_crtc_state *pipe_config)
8156 {
8157 struct drm_device *dev = crtc->base.dev;
8158 struct drm_i915_private *dev_priv = dev->dev_private;
8159 int pipe = pipe_config->cpu_transcoder;
8160 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8161 intel_clock_t clock;
8162 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8163 int refclk = 100000;
8164
8165 mutex_lock(&dev_priv->sb_lock);
8166 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8167 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8168 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8169 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8170 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8171 mutex_unlock(&dev_priv->sb_lock);
8172
8173 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8174 clock.m2 = (pll_dw0 & 0xff) << 22;
8175 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8176 clock.m2 |= pll_dw2 & 0x3fffff;
8177 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8178 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8179 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8180
8181 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8182 }
8183
8184 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8185 struct intel_crtc_state *pipe_config)
8186 {
8187 struct drm_device *dev = crtc->base.dev;
8188 struct drm_i915_private *dev_priv = dev->dev_private;
8189 uint32_t tmp;
8190
8191 if (!intel_display_power_is_enabled(dev_priv,
8192 POWER_DOMAIN_PIPE(crtc->pipe)))
8193 return false;
8194
8195 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8196 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8197
8198 tmp = I915_READ(PIPECONF(crtc->pipe));
8199 if (!(tmp & PIPECONF_ENABLE))
8200 return false;
8201
8202 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8203 switch (tmp & PIPECONF_BPC_MASK) {
8204 case PIPECONF_6BPC:
8205 pipe_config->pipe_bpp = 18;
8206 break;
8207 case PIPECONF_8BPC:
8208 pipe_config->pipe_bpp = 24;
8209 break;
8210 case PIPECONF_10BPC:
8211 pipe_config->pipe_bpp = 30;
8212 break;
8213 default:
8214 break;
8215 }
8216 }
8217
8218 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8219 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8220 pipe_config->limited_color_range = true;
8221
8222 if (INTEL_INFO(dev)->gen < 4)
8223 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8224
8225 intel_get_pipe_timings(crtc, pipe_config);
8226
8227 i9xx_get_pfit_config(crtc, pipe_config);
8228
8229 if (INTEL_INFO(dev)->gen >= 4) {
8230 tmp = I915_READ(DPLL_MD(crtc->pipe));
8231 pipe_config->pixel_multiplier =
8232 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8233 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8234 pipe_config->dpll_hw_state.dpll_md = tmp;
8235 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8236 tmp = I915_READ(DPLL(crtc->pipe));
8237 pipe_config->pixel_multiplier =
8238 ((tmp & SDVO_MULTIPLIER_MASK)
8239 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8240 } else {
8241 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8242 * port and will be fixed up in the encoder->get_config
8243 * function. */
8244 pipe_config->pixel_multiplier = 1;
8245 }
8246 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8247 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8248 /*
8249 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8250 * on 830. Filter it out here so that we don't
8251 * report errors due to that.
8252 */
8253 if (IS_I830(dev))
8254 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8255
8256 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8257 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8258 } else {
8259 /* Mask out read-only status bits. */
8260 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8261 DPLL_PORTC_READY_MASK |
8262 DPLL_PORTB_READY_MASK);
8263 }
8264
8265 if (IS_CHERRYVIEW(dev))
8266 chv_crtc_clock_get(crtc, pipe_config);
8267 else if (IS_VALLEYVIEW(dev))
8268 vlv_crtc_clock_get(crtc, pipe_config);
8269 else
8270 i9xx_crtc_clock_get(crtc, pipe_config);
8271
8272 /*
8273 * Normally the dotclock is filled in by the encoder .get_config()
8274 * but in case the pipe is enabled w/o any ports we need a sane
8275 * default.
8276 */
8277 pipe_config->base.adjusted_mode.crtc_clock =
8278 pipe_config->port_clock / pipe_config->pixel_multiplier;
8279
8280 return true;
8281 }
8282
8283 static void ironlake_init_pch_refclk(struct drm_device *dev)
8284 {
8285 struct drm_i915_private *dev_priv = dev->dev_private;
8286 struct intel_encoder *encoder;
8287 u32 val, final;
8288 bool has_lvds = false;
8289 bool has_cpu_edp = false;
8290 bool has_panel = false;
8291 bool has_ck505 = false;
8292 bool can_ssc = false;
8293
8294 /* We need to take the global config into account */
8295 for_each_intel_encoder(dev, encoder) {
8296 switch (encoder->type) {
8297 case INTEL_OUTPUT_LVDS:
8298 has_panel = true;
8299 has_lvds = true;
8300 break;
8301 case INTEL_OUTPUT_EDP:
8302 has_panel = true;
8303 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8304 has_cpu_edp = true;
8305 break;
8306 default:
8307 break;
8308 }
8309 }
8310
8311 if (HAS_PCH_IBX(dev)) {
8312 has_ck505 = dev_priv->vbt.display_clock_mode;
8313 can_ssc = has_ck505;
8314 } else {
8315 has_ck505 = false;
8316 can_ssc = true;
8317 }
8318
8319 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8320 has_panel, has_lvds, has_ck505);
8321
8322 /* Ironlake: try to setup display ref clock before DPLL
8323 * enabling. This is only under driver's control after
8324 * PCH B stepping, previous chipset stepping should be
8325 * ignoring this setting.
8326 */
8327 val = I915_READ(PCH_DREF_CONTROL);
8328
8329 /* As we must carefully and slowly disable/enable each source in turn,
8330 * compute the final state we want first and check if we need to
8331 * make any changes at all.
8332 */
8333 final = val;
8334 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8335 if (has_ck505)
8336 final |= DREF_NONSPREAD_CK505_ENABLE;
8337 else
8338 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8339
8340 final &= ~DREF_SSC_SOURCE_MASK;
8341 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8342 final &= ~DREF_SSC1_ENABLE;
8343
8344 if (has_panel) {
8345 final |= DREF_SSC_SOURCE_ENABLE;
8346
8347 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8348 final |= DREF_SSC1_ENABLE;
8349
8350 if (has_cpu_edp) {
8351 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8352 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8353 else
8354 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8355 } else
8356 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8357 } else {
8358 final |= DREF_SSC_SOURCE_DISABLE;
8359 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8360 }
8361
8362 if (final == val)
8363 return;
8364
8365 /* Always enable nonspread source */
8366 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8367
8368 if (has_ck505)
8369 val |= DREF_NONSPREAD_CK505_ENABLE;
8370 else
8371 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8372
8373 if (has_panel) {
8374 val &= ~DREF_SSC_SOURCE_MASK;
8375 val |= DREF_SSC_SOURCE_ENABLE;
8376
8377 /* SSC must be turned on before enabling the CPU output */
8378 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8379 DRM_DEBUG_KMS("Using SSC on panel\n");
8380 val |= DREF_SSC1_ENABLE;
8381 } else
8382 val &= ~DREF_SSC1_ENABLE;
8383
8384 /* Get SSC going before enabling the outputs */
8385 I915_WRITE(PCH_DREF_CONTROL, val);
8386 POSTING_READ(PCH_DREF_CONTROL);
8387 udelay(200);
8388
8389 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8390
8391 /* Enable CPU source on CPU attached eDP */
8392 if (has_cpu_edp) {
8393 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8394 DRM_DEBUG_KMS("Using SSC on eDP\n");
8395 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8396 } else
8397 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8398 } else
8399 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8400
8401 I915_WRITE(PCH_DREF_CONTROL, val);
8402 POSTING_READ(PCH_DREF_CONTROL);
8403 udelay(200);
8404 } else {
8405 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8406
8407 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8408
8409 /* Turn off CPU output */
8410 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8411
8412 I915_WRITE(PCH_DREF_CONTROL, val);
8413 POSTING_READ(PCH_DREF_CONTROL);
8414 udelay(200);
8415
8416 /* Turn off the SSC source */
8417 val &= ~DREF_SSC_SOURCE_MASK;
8418 val |= DREF_SSC_SOURCE_DISABLE;
8419
8420 /* Turn off SSC1 */
8421 val &= ~DREF_SSC1_ENABLE;
8422
8423 I915_WRITE(PCH_DREF_CONTROL, val);
8424 POSTING_READ(PCH_DREF_CONTROL);
8425 udelay(200);
8426 }
8427
8428 BUG_ON(val != final);
8429 }
8430
8431 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8432 {
8433 uint32_t tmp;
8434
8435 tmp = I915_READ(SOUTH_CHICKEN2);
8436 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8437 I915_WRITE(SOUTH_CHICKEN2, tmp);
8438
8439 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8440 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8441 DRM_ERROR("FDI mPHY reset assert timeout\n");
8442
8443 tmp = I915_READ(SOUTH_CHICKEN2);
8444 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8445 I915_WRITE(SOUTH_CHICKEN2, tmp);
8446
8447 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8448 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8449 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8450 }
8451
8452 /* WaMPhyProgramming:hsw */
8453 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8454 {
8455 uint32_t tmp;
8456
8457 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8458 tmp &= ~(0xFF << 24);
8459 tmp |= (0x12 << 24);
8460 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8461
8462 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8463 tmp |= (1 << 11);
8464 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8465
8466 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8467 tmp |= (1 << 11);
8468 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8471 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8472 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8475 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8476 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8479 tmp &= ~(7 << 13);
8480 tmp |= (5 << 13);
8481 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8484 tmp &= ~(7 << 13);
8485 tmp |= (5 << 13);
8486 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8487
8488 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8489 tmp &= ~0xFF;
8490 tmp |= 0x1C;
8491 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8494 tmp &= ~0xFF;
8495 tmp |= 0x1C;
8496 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8497
8498 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8499 tmp &= ~(0xFF << 16);
8500 tmp |= (0x1C << 16);
8501 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8502
8503 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8504 tmp &= ~(0xFF << 16);
8505 tmp |= (0x1C << 16);
8506 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8507
8508 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8509 tmp |= (1 << 27);
8510 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8511
8512 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8513 tmp |= (1 << 27);
8514 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8515
8516 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8517 tmp &= ~(0xF << 28);
8518 tmp |= (4 << 28);
8519 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8520
8521 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8522 tmp &= ~(0xF << 28);
8523 tmp |= (4 << 28);
8524 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8525 }
8526
8527 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8528 * Programming" based on the parameters passed:
8529 * - Sequence to enable CLKOUT_DP
8530 * - Sequence to enable CLKOUT_DP without spread
8531 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8532 */
8533 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8534 bool with_fdi)
8535 {
8536 struct drm_i915_private *dev_priv = dev->dev_private;
8537 uint32_t reg, tmp;
8538
8539 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8540 with_spread = true;
8541 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8542 with_fdi = false;
8543
8544 mutex_lock(&dev_priv->sb_lock);
8545
8546 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8547 tmp &= ~SBI_SSCCTL_DISABLE;
8548 tmp |= SBI_SSCCTL_PATHALT;
8549 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8550
8551 udelay(24);
8552
8553 if (with_spread) {
8554 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8555 tmp &= ~SBI_SSCCTL_PATHALT;
8556 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8557
8558 if (with_fdi) {
8559 lpt_reset_fdi_mphy(dev_priv);
8560 lpt_program_fdi_mphy(dev_priv);
8561 }
8562 }
8563
8564 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8565 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8566 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8567 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8568
8569 mutex_unlock(&dev_priv->sb_lock);
8570 }
8571
8572 /* Sequence to disable CLKOUT_DP */
8573 static void lpt_disable_clkout_dp(struct drm_device *dev)
8574 {
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 uint32_t reg, tmp;
8577
8578 mutex_lock(&dev_priv->sb_lock);
8579
8580 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8581 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8582 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8583 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8584
8585 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8586 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8587 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8588 tmp |= SBI_SSCCTL_PATHALT;
8589 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8590 udelay(32);
8591 }
8592 tmp |= SBI_SSCCTL_DISABLE;
8593 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8594 }
8595
8596 mutex_unlock(&dev_priv->sb_lock);
8597 }
8598
8599 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8600
8601 static const uint16_t sscdivintphase[] = {
8602 [BEND_IDX( 50)] = 0x3B23,
8603 [BEND_IDX( 45)] = 0x3B23,
8604 [BEND_IDX( 40)] = 0x3C23,
8605 [BEND_IDX( 35)] = 0x3C23,
8606 [BEND_IDX( 30)] = 0x3D23,
8607 [BEND_IDX( 25)] = 0x3D23,
8608 [BEND_IDX( 20)] = 0x3E23,
8609 [BEND_IDX( 15)] = 0x3E23,
8610 [BEND_IDX( 10)] = 0x3F23,
8611 [BEND_IDX( 5)] = 0x3F23,
8612 [BEND_IDX( 0)] = 0x0025,
8613 [BEND_IDX( -5)] = 0x0025,
8614 [BEND_IDX(-10)] = 0x0125,
8615 [BEND_IDX(-15)] = 0x0125,
8616 [BEND_IDX(-20)] = 0x0225,
8617 [BEND_IDX(-25)] = 0x0225,
8618 [BEND_IDX(-30)] = 0x0325,
8619 [BEND_IDX(-35)] = 0x0325,
8620 [BEND_IDX(-40)] = 0x0425,
8621 [BEND_IDX(-45)] = 0x0425,
8622 [BEND_IDX(-50)] = 0x0525,
8623 };
8624
8625 /*
8626 * Bend CLKOUT_DP
8627 * steps -50 to 50 inclusive, in steps of 5
8628 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8629 * change in clock period = -(steps / 10) * 5.787 ps
8630 */
8631 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8632 {
8633 uint32_t tmp;
8634 int idx = BEND_IDX(steps);
8635
8636 if (WARN_ON(steps % 5 != 0))
8637 return;
8638
8639 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8640 return;
8641
8642 mutex_lock(&dev_priv->sb_lock);
8643
8644 if (steps % 10 != 0)
8645 tmp = 0xAAAAAAAB;
8646 else
8647 tmp = 0x00000000;
8648 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8649
8650 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8651 tmp &= 0xffff0000;
8652 tmp |= sscdivintphase[idx];
8653 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8654
8655 mutex_unlock(&dev_priv->sb_lock);
8656 }
8657
8658 #undef BEND_IDX
8659
8660 static void lpt_init_pch_refclk(struct drm_device *dev)
8661 {
8662 struct intel_encoder *encoder;
8663 bool has_vga = false;
8664
8665 for_each_intel_encoder(dev, encoder) {
8666 switch (encoder->type) {
8667 case INTEL_OUTPUT_ANALOG:
8668 has_vga = true;
8669 break;
8670 default:
8671 break;
8672 }
8673 }
8674
8675 if (has_vga) {
8676 lpt_bend_clkout_dp(to_i915(dev), 0);
8677 lpt_enable_clkout_dp(dev, true, true);
8678 } else {
8679 lpt_disable_clkout_dp(dev);
8680 }
8681 }
8682
8683 /*
8684 * Initialize reference clocks when the driver loads
8685 */
8686 void intel_init_pch_refclk(struct drm_device *dev)
8687 {
8688 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8689 ironlake_init_pch_refclk(dev);
8690 else if (HAS_PCH_LPT(dev))
8691 lpt_init_pch_refclk(dev);
8692 }
8693
8694 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8695 {
8696 struct drm_device *dev = crtc_state->base.crtc->dev;
8697 struct drm_i915_private *dev_priv = dev->dev_private;
8698 struct drm_atomic_state *state = crtc_state->base.state;
8699 struct drm_connector *connector;
8700 struct drm_connector_state *connector_state;
8701 struct intel_encoder *encoder;
8702 int num_connectors = 0, i;
8703 bool is_lvds = false;
8704
8705 for_each_connector_in_state(state, connector, connector_state, i) {
8706 if (connector_state->crtc != crtc_state->base.crtc)
8707 continue;
8708
8709 encoder = to_intel_encoder(connector_state->best_encoder);
8710
8711 switch (encoder->type) {
8712 case INTEL_OUTPUT_LVDS:
8713 is_lvds = true;
8714 break;
8715 default:
8716 break;
8717 }
8718 num_connectors++;
8719 }
8720
8721 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8722 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8723 dev_priv->vbt.lvds_ssc_freq);
8724 return dev_priv->vbt.lvds_ssc_freq;
8725 }
8726
8727 return 120000;
8728 }
8729
8730 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8731 {
8732 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734 int pipe = intel_crtc->pipe;
8735 uint32_t val;
8736
8737 val = 0;
8738
8739 switch (intel_crtc->config->pipe_bpp) {
8740 case 18:
8741 val |= PIPECONF_6BPC;
8742 break;
8743 case 24:
8744 val |= PIPECONF_8BPC;
8745 break;
8746 case 30:
8747 val |= PIPECONF_10BPC;
8748 break;
8749 case 36:
8750 val |= PIPECONF_12BPC;
8751 break;
8752 default:
8753 /* Case prevented by intel_choose_pipe_bpp_dither. */
8754 BUG();
8755 }
8756
8757 if (intel_crtc->config->dither)
8758 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8759
8760 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8761 val |= PIPECONF_INTERLACED_ILK;
8762 else
8763 val |= PIPECONF_PROGRESSIVE;
8764
8765 if (intel_crtc->config->limited_color_range)
8766 val |= PIPECONF_COLOR_RANGE_SELECT;
8767
8768 I915_WRITE(PIPECONF(pipe), val);
8769 POSTING_READ(PIPECONF(pipe));
8770 }
8771
8772 /*
8773 * Set up the pipe CSC unit.
8774 *
8775 * Currently only full range RGB to limited range RGB conversion
8776 * is supported, but eventually this should handle various
8777 * RGB<->YCbCr scenarios as well.
8778 */
8779 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8780 {
8781 struct drm_device *dev = crtc->dev;
8782 struct drm_i915_private *dev_priv = dev->dev_private;
8783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8784 int pipe = intel_crtc->pipe;
8785 uint16_t coeff = 0x7800; /* 1.0 */
8786
8787 /*
8788 * TODO: Check what kind of values actually come out of the pipe
8789 * with these coeff/postoff values and adjust to get the best
8790 * accuracy. Perhaps we even need to take the bpc value into
8791 * consideration.
8792 */
8793
8794 if (intel_crtc->config->limited_color_range)
8795 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8796
8797 /*
8798 * GY/GU and RY/RU should be the other way around according
8799 * to BSpec, but reality doesn't agree. Just set them up in
8800 * a way that results in the correct picture.
8801 */
8802 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8803 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8804
8805 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8806 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8807
8808 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8809 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8810
8811 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8812 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8813 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8814
8815 if (INTEL_INFO(dev)->gen > 6) {
8816 uint16_t postoff = 0;
8817
8818 if (intel_crtc->config->limited_color_range)
8819 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8820
8821 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8822 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8823 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8824
8825 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8826 } else {
8827 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8828
8829 if (intel_crtc->config->limited_color_range)
8830 mode |= CSC_BLACK_SCREEN_OFFSET;
8831
8832 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8833 }
8834 }
8835
8836 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8837 {
8838 struct drm_device *dev = crtc->dev;
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841 enum pipe pipe = intel_crtc->pipe;
8842 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8843 uint32_t val;
8844
8845 val = 0;
8846
8847 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8848 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8849
8850 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8851 val |= PIPECONF_INTERLACED_ILK;
8852 else
8853 val |= PIPECONF_PROGRESSIVE;
8854
8855 I915_WRITE(PIPECONF(cpu_transcoder), val);
8856 POSTING_READ(PIPECONF(cpu_transcoder));
8857
8858 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8859 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8860
8861 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8862 val = 0;
8863
8864 switch (intel_crtc->config->pipe_bpp) {
8865 case 18:
8866 val |= PIPEMISC_DITHER_6_BPC;
8867 break;
8868 case 24:
8869 val |= PIPEMISC_DITHER_8_BPC;
8870 break;
8871 case 30:
8872 val |= PIPEMISC_DITHER_10_BPC;
8873 break;
8874 case 36:
8875 val |= PIPEMISC_DITHER_12_BPC;
8876 break;
8877 default:
8878 /* Case prevented by pipe_config_set_bpp. */
8879 BUG();
8880 }
8881
8882 if (intel_crtc->config->dither)
8883 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8884
8885 I915_WRITE(PIPEMISC(pipe), val);
8886 }
8887 }
8888
8889 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8890 struct intel_crtc_state *crtc_state,
8891 intel_clock_t *clock,
8892 bool *has_reduced_clock,
8893 intel_clock_t *reduced_clock)
8894 {
8895 struct drm_device *dev = crtc->dev;
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 int refclk;
8898 const intel_limit_t *limit;
8899 bool ret;
8900
8901 refclk = ironlake_get_refclk(crtc_state);
8902
8903 /*
8904 * Returns a set of divisors for the desired target clock with the given
8905 * refclk, or FALSE. The returned values represent the clock equation:
8906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8907 */
8908 limit = intel_limit(crtc_state, refclk);
8909 ret = dev_priv->display.find_dpll(limit, crtc_state,
8910 crtc_state->port_clock,
8911 refclk, NULL, clock);
8912 if (!ret)
8913 return false;
8914
8915 return true;
8916 }
8917
8918 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8919 {
8920 /*
8921 * Account for spread spectrum to avoid
8922 * oversubscribing the link. Max center spread
8923 * is 2.5%; use 5% for safety's sake.
8924 */
8925 u32 bps = target_clock * bpp * 21 / 20;
8926 return DIV_ROUND_UP(bps, link_bw * 8);
8927 }
8928
8929 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8930 {
8931 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8932 }
8933
8934 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8935 struct intel_crtc_state *crtc_state,
8936 u32 *fp,
8937 intel_clock_t *reduced_clock, u32 *fp2)
8938 {
8939 struct drm_crtc *crtc = &intel_crtc->base;
8940 struct drm_device *dev = crtc->dev;
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8942 struct drm_atomic_state *state = crtc_state->base.state;
8943 struct drm_connector *connector;
8944 struct drm_connector_state *connector_state;
8945 struct intel_encoder *encoder;
8946 uint32_t dpll;
8947 int factor, num_connectors = 0, i;
8948 bool is_lvds = false, is_sdvo = false;
8949
8950 for_each_connector_in_state(state, connector, connector_state, i) {
8951 if (connector_state->crtc != crtc_state->base.crtc)
8952 continue;
8953
8954 encoder = to_intel_encoder(connector_state->best_encoder);
8955
8956 switch (encoder->type) {
8957 case INTEL_OUTPUT_LVDS:
8958 is_lvds = true;
8959 break;
8960 case INTEL_OUTPUT_SDVO:
8961 case INTEL_OUTPUT_HDMI:
8962 is_sdvo = true;
8963 break;
8964 default:
8965 break;
8966 }
8967
8968 num_connectors++;
8969 }
8970
8971 /* Enable autotuning of the PLL clock (if permissible) */
8972 factor = 21;
8973 if (is_lvds) {
8974 if ((intel_panel_use_ssc(dev_priv) &&
8975 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8976 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8977 factor = 25;
8978 } else if (crtc_state->sdvo_tv_clock)
8979 factor = 20;
8980
8981 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8982 *fp |= FP_CB_TUNE;
8983
8984 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8985 *fp2 |= FP_CB_TUNE;
8986
8987 dpll = 0;
8988
8989 if (is_lvds)
8990 dpll |= DPLLB_MODE_LVDS;
8991 else
8992 dpll |= DPLLB_MODE_DAC_SERIAL;
8993
8994 dpll |= (crtc_state->pixel_multiplier - 1)
8995 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8996
8997 if (is_sdvo)
8998 dpll |= DPLL_SDVO_HIGH_SPEED;
8999 if (crtc_state->has_dp_encoder)
9000 dpll |= DPLL_SDVO_HIGH_SPEED;
9001
9002 /* compute bitmask from p1 value */
9003 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9004 /* also FPA1 */
9005 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9006
9007 switch (crtc_state->dpll.p2) {
9008 case 5:
9009 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9010 break;
9011 case 7:
9012 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9013 break;
9014 case 10:
9015 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9016 break;
9017 case 14:
9018 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9019 break;
9020 }
9021
9022 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9023 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9024 else
9025 dpll |= PLL_REF_INPUT_DREFCLK;
9026
9027 return dpll | DPLL_VCO_ENABLE;
9028 }
9029
9030 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9031 struct intel_crtc_state *crtc_state)
9032 {
9033 struct drm_device *dev = crtc->base.dev;
9034 intel_clock_t clock, reduced_clock;
9035 u32 dpll = 0, fp = 0, fp2 = 0;
9036 bool ok, has_reduced_clock = false;
9037 bool is_lvds = false;
9038 struct intel_shared_dpll *pll;
9039
9040 memset(&crtc_state->dpll_hw_state, 0,
9041 sizeof(crtc_state->dpll_hw_state));
9042
9043 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9044
9045 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9046 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9047
9048 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9049 &has_reduced_clock, &reduced_clock);
9050 if (!ok && !crtc_state->clock_set) {
9051 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9052 return -EINVAL;
9053 }
9054 /* Compat-code for transition, will disappear. */
9055 if (!crtc_state->clock_set) {
9056 crtc_state->dpll.n = clock.n;
9057 crtc_state->dpll.m1 = clock.m1;
9058 crtc_state->dpll.m2 = clock.m2;
9059 crtc_state->dpll.p1 = clock.p1;
9060 crtc_state->dpll.p2 = clock.p2;
9061 }
9062
9063 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9064 if (crtc_state->has_pch_encoder) {
9065 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9066 if (has_reduced_clock)
9067 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9068
9069 dpll = ironlake_compute_dpll(crtc, crtc_state,
9070 &fp, &reduced_clock,
9071 has_reduced_clock ? &fp2 : NULL);
9072
9073 crtc_state->dpll_hw_state.dpll = dpll;
9074 crtc_state->dpll_hw_state.fp0 = fp;
9075 if (has_reduced_clock)
9076 crtc_state->dpll_hw_state.fp1 = fp2;
9077 else
9078 crtc_state->dpll_hw_state.fp1 = fp;
9079
9080 pll = intel_get_shared_dpll(crtc, crtc_state);
9081 if (pll == NULL) {
9082 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9083 pipe_name(crtc->pipe));
9084 return -EINVAL;
9085 }
9086 }
9087
9088 if (is_lvds && has_reduced_clock)
9089 crtc->lowfreq_avail = true;
9090 else
9091 crtc->lowfreq_avail = false;
9092
9093 return 0;
9094 }
9095
9096 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9097 struct intel_link_m_n *m_n)
9098 {
9099 struct drm_device *dev = crtc->base.dev;
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 enum pipe pipe = crtc->pipe;
9102
9103 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9104 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9105 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9106 & ~TU_SIZE_MASK;
9107 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9108 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9109 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9110 }
9111
9112 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9113 enum transcoder transcoder,
9114 struct intel_link_m_n *m_n,
9115 struct intel_link_m_n *m2_n2)
9116 {
9117 struct drm_device *dev = crtc->base.dev;
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119 enum pipe pipe = crtc->pipe;
9120
9121 if (INTEL_INFO(dev)->gen >= 5) {
9122 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9123 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9124 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9125 & ~TU_SIZE_MASK;
9126 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9127 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9128 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9129 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9130 * gen < 8) and if DRRS is supported (to make sure the
9131 * registers are not unnecessarily read).
9132 */
9133 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9134 crtc->config->has_drrs) {
9135 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9136 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9137 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9138 & ~TU_SIZE_MASK;
9139 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9140 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9141 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9142 }
9143 } else {
9144 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9145 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9146 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9147 & ~TU_SIZE_MASK;
9148 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9149 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9150 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9151 }
9152 }
9153
9154 void intel_dp_get_m_n(struct intel_crtc *crtc,
9155 struct intel_crtc_state *pipe_config)
9156 {
9157 if (pipe_config->has_pch_encoder)
9158 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9159 else
9160 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9161 &pipe_config->dp_m_n,
9162 &pipe_config->dp_m2_n2);
9163 }
9164
9165 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9166 struct intel_crtc_state *pipe_config)
9167 {
9168 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9169 &pipe_config->fdi_m_n, NULL);
9170 }
9171
9172 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9173 struct intel_crtc_state *pipe_config)
9174 {
9175 struct drm_device *dev = crtc->base.dev;
9176 struct drm_i915_private *dev_priv = dev->dev_private;
9177 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9178 uint32_t ps_ctrl = 0;
9179 int id = -1;
9180 int i;
9181
9182 /* find scaler attached to this pipe */
9183 for (i = 0; i < crtc->num_scalers; i++) {
9184 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9185 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9186 id = i;
9187 pipe_config->pch_pfit.enabled = true;
9188 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9189 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9190 break;
9191 }
9192 }
9193
9194 scaler_state->scaler_id = id;
9195 if (id >= 0) {
9196 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9197 } else {
9198 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9199 }
9200 }
9201
9202 static void
9203 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9204 struct intel_initial_plane_config *plane_config)
9205 {
9206 struct drm_device *dev = crtc->base.dev;
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9208 u32 val, base, offset, stride_mult, tiling;
9209 int pipe = crtc->pipe;
9210 int fourcc, pixel_format;
9211 unsigned int aligned_height;
9212 struct drm_framebuffer *fb;
9213 struct intel_framebuffer *intel_fb;
9214
9215 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9216 if (!intel_fb) {
9217 DRM_DEBUG_KMS("failed to alloc fb\n");
9218 return;
9219 }
9220
9221 fb = &intel_fb->base;
9222
9223 val = I915_READ(PLANE_CTL(pipe, 0));
9224 if (!(val & PLANE_CTL_ENABLE))
9225 goto error;
9226
9227 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9228 fourcc = skl_format_to_fourcc(pixel_format,
9229 val & PLANE_CTL_ORDER_RGBX,
9230 val & PLANE_CTL_ALPHA_MASK);
9231 fb->pixel_format = fourcc;
9232 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9233
9234 tiling = val & PLANE_CTL_TILED_MASK;
9235 switch (tiling) {
9236 case PLANE_CTL_TILED_LINEAR:
9237 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9238 break;
9239 case PLANE_CTL_TILED_X:
9240 plane_config->tiling = I915_TILING_X;
9241 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9242 break;
9243 case PLANE_CTL_TILED_Y:
9244 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9245 break;
9246 case PLANE_CTL_TILED_YF:
9247 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9248 break;
9249 default:
9250 MISSING_CASE(tiling);
9251 goto error;
9252 }
9253
9254 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9255 plane_config->base = base;
9256
9257 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9258
9259 val = I915_READ(PLANE_SIZE(pipe, 0));
9260 fb->height = ((val >> 16) & 0xfff) + 1;
9261 fb->width = ((val >> 0) & 0x1fff) + 1;
9262
9263 val = I915_READ(PLANE_STRIDE(pipe, 0));
9264 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9265 fb->pixel_format);
9266 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9267
9268 aligned_height = intel_fb_align_height(dev, fb->height,
9269 fb->pixel_format,
9270 fb->modifier[0]);
9271
9272 plane_config->size = fb->pitches[0] * aligned_height;
9273
9274 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9275 pipe_name(pipe), fb->width, fb->height,
9276 fb->bits_per_pixel, base, fb->pitches[0],
9277 plane_config->size);
9278
9279 plane_config->fb = intel_fb;
9280 return;
9281
9282 error:
9283 kfree(fb);
9284 }
9285
9286 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9287 struct intel_crtc_state *pipe_config)
9288 {
9289 struct drm_device *dev = crtc->base.dev;
9290 struct drm_i915_private *dev_priv = dev->dev_private;
9291 uint32_t tmp;
9292
9293 tmp = I915_READ(PF_CTL(crtc->pipe));
9294
9295 if (tmp & PF_ENABLE) {
9296 pipe_config->pch_pfit.enabled = true;
9297 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9298 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9299
9300 /* We currently do not free assignements of panel fitters on
9301 * ivb/hsw (since we don't use the higher upscaling modes which
9302 * differentiates them) so just WARN about this case for now. */
9303 if (IS_GEN7(dev)) {
9304 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9305 PF_PIPE_SEL_IVB(crtc->pipe));
9306 }
9307 }
9308 }
9309
9310 static void
9311 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9312 struct intel_initial_plane_config *plane_config)
9313 {
9314 struct drm_device *dev = crtc->base.dev;
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 u32 val, base, offset;
9317 int pipe = crtc->pipe;
9318 int fourcc, pixel_format;
9319 unsigned int aligned_height;
9320 struct drm_framebuffer *fb;
9321 struct intel_framebuffer *intel_fb;
9322
9323 val = I915_READ(DSPCNTR(pipe));
9324 if (!(val & DISPLAY_PLANE_ENABLE))
9325 return;
9326
9327 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9328 if (!intel_fb) {
9329 DRM_DEBUG_KMS("failed to alloc fb\n");
9330 return;
9331 }
9332
9333 fb = &intel_fb->base;
9334
9335 if (INTEL_INFO(dev)->gen >= 4) {
9336 if (val & DISPPLANE_TILED) {
9337 plane_config->tiling = I915_TILING_X;
9338 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9339 }
9340 }
9341
9342 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9343 fourcc = i9xx_format_to_fourcc(pixel_format);
9344 fb->pixel_format = fourcc;
9345 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9346
9347 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9348 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9349 offset = I915_READ(DSPOFFSET(pipe));
9350 } else {
9351 if (plane_config->tiling)
9352 offset = I915_READ(DSPTILEOFF(pipe));
9353 else
9354 offset = I915_READ(DSPLINOFF(pipe));
9355 }
9356 plane_config->base = base;
9357
9358 val = I915_READ(PIPESRC(pipe));
9359 fb->width = ((val >> 16) & 0xfff) + 1;
9360 fb->height = ((val >> 0) & 0xfff) + 1;
9361
9362 val = I915_READ(DSPSTRIDE(pipe));
9363 fb->pitches[0] = val & 0xffffffc0;
9364
9365 aligned_height = intel_fb_align_height(dev, fb->height,
9366 fb->pixel_format,
9367 fb->modifier[0]);
9368
9369 plane_config->size = fb->pitches[0] * aligned_height;
9370
9371 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9372 pipe_name(pipe), fb->width, fb->height,
9373 fb->bits_per_pixel, base, fb->pitches[0],
9374 plane_config->size);
9375
9376 plane_config->fb = intel_fb;
9377 }
9378
9379 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9380 struct intel_crtc_state *pipe_config)
9381 {
9382 struct drm_device *dev = crtc->base.dev;
9383 struct drm_i915_private *dev_priv = dev->dev_private;
9384 uint32_t tmp;
9385
9386 if (!intel_display_power_is_enabled(dev_priv,
9387 POWER_DOMAIN_PIPE(crtc->pipe)))
9388 return false;
9389
9390 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9391 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9392
9393 tmp = I915_READ(PIPECONF(crtc->pipe));
9394 if (!(tmp & PIPECONF_ENABLE))
9395 return false;
9396
9397 switch (tmp & PIPECONF_BPC_MASK) {
9398 case PIPECONF_6BPC:
9399 pipe_config->pipe_bpp = 18;
9400 break;
9401 case PIPECONF_8BPC:
9402 pipe_config->pipe_bpp = 24;
9403 break;
9404 case PIPECONF_10BPC:
9405 pipe_config->pipe_bpp = 30;
9406 break;
9407 case PIPECONF_12BPC:
9408 pipe_config->pipe_bpp = 36;
9409 break;
9410 default:
9411 break;
9412 }
9413
9414 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9415 pipe_config->limited_color_range = true;
9416
9417 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9418 struct intel_shared_dpll *pll;
9419
9420 pipe_config->has_pch_encoder = true;
9421
9422 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9423 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9424 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9425
9426 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9427
9428 if (HAS_PCH_IBX(dev_priv->dev)) {
9429 pipe_config->shared_dpll =
9430 (enum intel_dpll_id) crtc->pipe;
9431 } else {
9432 tmp = I915_READ(PCH_DPLL_SEL);
9433 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9434 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9435 else
9436 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9437 }
9438
9439 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9440
9441 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9442 &pipe_config->dpll_hw_state));
9443
9444 tmp = pipe_config->dpll_hw_state.dpll;
9445 pipe_config->pixel_multiplier =
9446 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9447 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9448
9449 ironlake_pch_clock_get(crtc, pipe_config);
9450 } else {
9451 pipe_config->pixel_multiplier = 1;
9452 }
9453
9454 intel_get_pipe_timings(crtc, pipe_config);
9455
9456 ironlake_get_pfit_config(crtc, pipe_config);
9457
9458 return true;
9459 }
9460
9461 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9462 {
9463 struct drm_device *dev = dev_priv->dev;
9464 struct intel_crtc *crtc;
9465
9466 for_each_intel_crtc(dev, crtc)
9467 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9468 pipe_name(crtc->pipe));
9469
9470 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9471 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9472 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9473 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9474 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9475 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9476 "CPU PWM1 enabled\n");
9477 if (IS_HASWELL(dev))
9478 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9479 "CPU PWM2 enabled\n");
9480 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9481 "PCH PWM1 enabled\n");
9482 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9483 "Utility pin enabled\n");
9484 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9485
9486 /*
9487 * In theory we can still leave IRQs enabled, as long as only the HPD
9488 * interrupts remain enabled. We used to check for that, but since it's
9489 * gen-specific and since we only disable LCPLL after we fully disable
9490 * the interrupts, the check below should be enough.
9491 */
9492 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9493 }
9494
9495 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9496 {
9497 struct drm_device *dev = dev_priv->dev;
9498
9499 if (IS_HASWELL(dev))
9500 return I915_READ(D_COMP_HSW);
9501 else
9502 return I915_READ(D_COMP_BDW);
9503 }
9504
9505 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9506 {
9507 struct drm_device *dev = dev_priv->dev;
9508
9509 if (IS_HASWELL(dev)) {
9510 mutex_lock(&dev_priv->rps.hw_lock);
9511 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9512 val))
9513 DRM_ERROR("Failed to write to D_COMP\n");
9514 mutex_unlock(&dev_priv->rps.hw_lock);
9515 } else {
9516 I915_WRITE(D_COMP_BDW, val);
9517 POSTING_READ(D_COMP_BDW);
9518 }
9519 }
9520
9521 /*
9522 * This function implements pieces of two sequences from BSpec:
9523 * - Sequence for display software to disable LCPLL
9524 * - Sequence for display software to allow package C8+
9525 * The steps implemented here are just the steps that actually touch the LCPLL
9526 * register. Callers should take care of disabling all the display engine
9527 * functions, doing the mode unset, fixing interrupts, etc.
9528 */
9529 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9530 bool switch_to_fclk, bool allow_power_down)
9531 {
9532 uint32_t val;
9533
9534 assert_can_disable_lcpll(dev_priv);
9535
9536 val = I915_READ(LCPLL_CTL);
9537
9538 if (switch_to_fclk) {
9539 val |= LCPLL_CD_SOURCE_FCLK;
9540 I915_WRITE(LCPLL_CTL, val);
9541
9542 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9543 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9544 DRM_ERROR("Switching to FCLK failed\n");
9545
9546 val = I915_READ(LCPLL_CTL);
9547 }
9548
9549 val |= LCPLL_PLL_DISABLE;
9550 I915_WRITE(LCPLL_CTL, val);
9551 POSTING_READ(LCPLL_CTL);
9552
9553 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9554 DRM_ERROR("LCPLL still locked\n");
9555
9556 val = hsw_read_dcomp(dev_priv);
9557 val |= D_COMP_COMP_DISABLE;
9558 hsw_write_dcomp(dev_priv, val);
9559 ndelay(100);
9560
9561 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9562 1))
9563 DRM_ERROR("D_COMP RCOMP still in progress\n");
9564
9565 if (allow_power_down) {
9566 val = I915_READ(LCPLL_CTL);
9567 val |= LCPLL_POWER_DOWN_ALLOW;
9568 I915_WRITE(LCPLL_CTL, val);
9569 POSTING_READ(LCPLL_CTL);
9570 }
9571 }
9572
9573 /*
9574 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9575 * source.
9576 */
9577 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9578 {
9579 uint32_t val;
9580
9581 val = I915_READ(LCPLL_CTL);
9582
9583 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9584 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9585 return;
9586
9587 /*
9588 * Make sure we're not on PC8 state before disabling PC8, otherwise
9589 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9590 */
9591 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9592
9593 if (val & LCPLL_POWER_DOWN_ALLOW) {
9594 val &= ~LCPLL_POWER_DOWN_ALLOW;
9595 I915_WRITE(LCPLL_CTL, val);
9596 POSTING_READ(LCPLL_CTL);
9597 }
9598
9599 val = hsw_read_dcomp(dev_priv);
9600 val |= D_COMP_COMP_FORCE;
9601 val &= ~D_COMP_COMP_DISABLE;
9602 hsw_write_dcomp(dev_priv, val);
9603
9604 val = I915_READ(LCPLL_CTL);
9605 val &= ~LCPLL_PLL_DISABLE;
9606 I915_WRITE(LCPLL_CTL, val);
9607
9608 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9609 DRM_ERROR("LCPLL not locked yet\n");
9610
9611 if (val & LCPLL_CD_SOURCE_FCLK) {
9612 val = I915_READ(LCPLL_CTL);
9613 val &= ~LCPLL_CD_SOURCE_FCLK;
9614 I915_WRITE(LCPLL_CTL, val);
9615
9616 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9617 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9618 DRM_ERROR("Switching back to LCPLL failed\n");
9619 }
9620
9621 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9622 intel_update_cdclk(dev_priv->dev);
9623 }
9624
9625 /*
9626 * Package states C8 and deeper are really deep PC states that can only be
9627 * reached when all the devices on the system allow it, so even if the graphics
9628 * device allows PC8+, it doesn't mean the system will actually get to these
9629 * states. Our driver only allows PC8+ when going into runtime PM.
9630 *
9631 * The requirements for PC8+ are that all the outputs are disabled, the power
9632 * well is disabled and most interrupts are disabled, and these are also
9633 * requirements for runtime PM. When these conditions are met, we manually do
9634 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9635 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9636 * hang the machine.
9637 *
9638 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9639 * the state of some registers, so when we come back from PC8+ we need to
9640 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9641 * need to take care of the registers kept by RC6. Notice that this happens even
9642 * if we don't put the device in PCI D3 state (which is what currently happens
9643 * because of the runtime PM support).
9644 *
9645 * For more, read "Display Sequences for Package C8" on the hardware
9646 * documentation.
9647 */
9648 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9649 {
9650 struct drm_device *dev = dev_priv->dev;
9651 uint32_t val;
9652
9653 DRM_DEBUG_KMS("Enabling package C8+\n");
9654
9655 if (HAS_PCH_LPT_LP(dev)) {
9656 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9657 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9658 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9659 }
9660
9661 lpt_disable_clkout_dp(dev);
9662 hsw_disable_lcpll(dev_priv, true, true);
9663 }
9664
9665 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9666 {
9667 struct drm_device *dev = dev_priv->dev;
9668 uint32_t val;
9669
9670 DRM_DEBUG_KMS("Disabling package C8+\n");
9671
9672 hsw_restore_lcpll(dev_priv);
9673 lpt_init_pch_refclk(dev);
9674
9675 if (HAS_PCH_LPT_LP(dev)) {
9676 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9677 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9678 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9679 }
9680 }
9681
9682 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9683 {
9684 struct drm_device *dev = old_state->dev;
9685 struct intel_atomic_state *old_intel_state =
9686 to_intel_atomic_state(old_state);
9687 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9688
9689 broxton_set_cdclk(dev, req_cdclk);
9690 }
9691
9692 /* compute the max rate for new configuration */
9693 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9694 {
9695 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9696 struct drm_i915_private *dev_priv = state->dev->dev_private;
9697 struct drm_crtc *crtc;
9698 struct drm_crtc_state *cstate;
9699 struct intel_crtc_state *crtc_state;
9700 unsigned max_pixel_rate = 0, i;
9701 enum pipe pipe;
9702
9703 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9704 sizeof(intel_state->min_pixclk));
9705
9706 for_each_crtc_in_state(state, crtc, cstate, i) {
9707 int pixel_rate;
9708
9709 crtc_state = to_intel_crtc_state(cstate);
9710 if (!crtc_state->base.enable) {
9711 intel_state->min_pixclk[i] = 0;
9712 continue;
9713 }
9714
9715 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9716
9717 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9718 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9719 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9720
9721 intel_state->min_pixclk[i] = pixel_rate;
9722 }
9723
9724 if (!intel_state->active_crtcs)
9725 return 0;
9726
9727 for_each_pipe(dev_priv, pipe)
9728 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9729
9730 return max_pixel_rate;
9731 }
9732
9733 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9734 {
9735 struct drm_i915_private *dev_priv = dev->dev_private;
9736 uint32_t val, data;
9737 int ret;
9738
9739 if (WARN((I915_READ(LCPLL_CTL) &
9740 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9741 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9742 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9743 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9744 "trying to change cdclk frequency with cdclk not enabled\n"))
9745 return;
9746
9747 mutex_lock(&dev_priv->rps.hw_lock);
9748 ret = sandybridge_pcode_write(dev_priv,
9749 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9750 mutex_unlock(&dev_priv->rps.hw_lock);
9751 if (ret) {
9752 DRM_ERROR("failed to inform pcode about cdclk change\n");
9753 return;
9754 }
9755
9756 val = I915_READ(LCPLL_CTL);
9757 val |= LCPLL_CD_SOURCE_FCLK;
9758 I915_WRITE(LCPLL_CTL, val);
9759
9760 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9761 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9762 DRM_ERROR("Switching to FCLK failed\n");
9763
9764 val = I915_READ(LCPLL_CTL);
9765 val &= ~LCPLL_CLK_FREQ_MASK;
9766
9767 switch (cdclk) {
9768 case 450000:
9769 val |= LCPLL_CLK_FREQ_450;
9770 data = 0;
9771 break;
9772 case 540000:
9773 val |= LCPLL_CLK_FREQ_54O_BDW;
9774 data = 1;
9775 break;
9776 case 337500:
9777 val |= LCPLL_CLK_FREQ_337_5_BDW;
9778 data = 2;
9779 break;
9780 case 675000:
9781 val |= LCPLL_CLK_FREQ_675_BDW;
9782 data = 3;
9783 break;
9784 default:
9785 WARN(1, "invalid cdclk frequency\n");
9786 return;
9787 }
9788
9789 I915_WRITE(LCPLL_CTL, val);
9790
9791 val = I915_READ(LCPLL_CTL);
9792 val &= ~LCPLL_CD_SOURCE_FCLK;
9793 I915_WRITE(LCPLL_CTL, val);
9794
9795 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9796 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9797 DRM_ERROR("Switching back to LCPLL failed\n");
9798
9799 mutex_lock(&dev_priv->rps.hw_lock);
9800 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9801 mutex_unlock(&dev_priv->rps.hw_lock);
9802
9803 intel_update_cdclk(dev);
9804
9805 WARN(cdclk != dev_priv->cdclk_freq,
9806 "cdclk requested %d kHz but got %d kHz\n",
9807 cdclk, dev_priv->cdclk_freq);
9808 }
9809
9810 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9811 {
9812 struct drm_i915_private *dev_priv = to_i915(state->dev);
9813 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9814 int max_pixclk = ilk_max_pixel_rate(state);
9815 int cdclk;
9816
9817 /*
9818 * FIXME should also account for plane ratio
9819 * once 64bpp pixel formats are supported.
9820 */
9821 if (max_pixclk > 540000)
9822 cdclk = 675000;
9823 else if (max_pixclk > 450000)
9824 cdclk = 540000;
9825 else if (max_pixclk > 337500)
9826 cdclk = 450000;
9827 else
9828 cdclk = 337500;
9829
9830 if (cdclk > dev_priv->max_cdclk_freq) {
9831 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9832 cdclk, dev_priv->max_cdclk_freq);
9833 return -EINVAL;
9834 }
9835
9836 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9837 if (!intel_state->active_crtcs)
9838 intel_state->dev_cdclk = 337500;
9839
9840 return 0;
9841 }
9842
9843 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9844 {
9845 struct drm_device *dev = old_state->dev;
9846 struct intel_atomic_state *old_intel_state =
9847 to_intel_atomic_state(old_state);
9848 unsigned req_cdclk = old_intel_state->dev_cdclk;
9849
9850 broadwell_set_cdclk(dev, req_cdclk);
9851 }
9852
9853 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9854 struct intel_crtc_state *crtc_state)
9855 {
9856 if (!intel_ddi_pll_select(crtc, crtc_state))
9857 return -EINVAL;
9858
9859 crtc->lowfreq_avail = false;
9860
9861 return 0;
9862 }
9863
9864 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9865 enum port port,
9866 struct intel_crtc_state *pipe_config)
9867 {
9868 switch (port) {
9869 case PORT_A:
9870 pipe_config->ddi_pll_sel = SKL_DPLL0;
9871 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9872 break;
9873 case PORT_B:
9874 pipe_config->ddi_pll_sel = SKL_DPLL1;
9875 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9876 break;
9877 case PORT_C:
9878 pipe_config->ddi_pll_sel = SKL_DPLL2;
9879 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9880 break;
9881 default:
9882 DRM_ERROR("Incorrect port type\n");
9883 }
9884 }
9885
9886 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9887 enum port port,
9888 struct intel_crtc_state *pipe_config)
9889 {
9890 u32 temp, dpll_ctl1;
9891
9892 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9893 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9894
9895 switch (pipe_config->ddi_pll_sel) {
9896 case SKL_DPLL0:
9897 /*
9898 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9899 * of the shared DPLL framework and thus needs to be read out
9900 * separately
9901 */
9902 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9903 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9904 break;
9905 case SKL_DPLL1:
9906 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9907 break;
9908 case SKL_DPLL2:
9909 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9910 break;
9911 case SKL_DPLL3:
9912 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9913 break;
9914 }
9915 }
9916
9917 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9918 enum port port,
9919 struct intel_crtc_state *pipe_config)
9920 {
9921 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9922
9923 switch (pipe_config->ddi_pll_sel) {
9924 case PORT_CLK_SEL_WRPLL1:
9925 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9926 break;
9927 case PORT_CLK_SEL_WRPLL2:
9928 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9929 break;
9930 case PORT_CLK_SEL_SPLL:
9931 pipe_config->shared_dpll = DPLL_ID_SPLL;
9932 break;
9933 }
9934 }
9935
9936 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9937 struct intel_crtc_state *pipe_config)
9938 {
9939 struct drm_device *dev = crtc->base.dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_shared_dpll *pll;
9942 enum port port;
9943 uint32_t tmp;
9944
9945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9946
9947 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9948
9949 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9950 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9951 else if (IS_BROXTON(dev))
9952 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9953 else
9954 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9955
9956 if (pipe_config->shared_dpll >= 0) {
9957 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9958
9959 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9960 &pipe_config->dpll_hw_state));
9961 }
9962
9963 /*
9964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9965 * DDI E. So just check whether this pipe is wired to DDI E and whether
9966 * the PCH transcoder is on.
9967 */
9968 if (INTEL_INFO(dev)->gen < 9 &&
9969 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9970 pipe_config->has_pch_encoder = true;
9971
9972 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9973 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9974 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9975
9976 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9977 }
9978 }
9979
9980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9981 struct intel_crtc_state *pipe_config)
9982 {
9983 struct drm_device *dev = crtc->base.dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 enum intel_display_power_domain pfit_domain;
9986 uint32_t tmp;
9987
9988 if (!intel_display_power_is_enabled(dev_priv,
9989 POWER_DOMAIN_PIPE(crtc->pipe)))
9990 return false;
9991
9992 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9993 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9994
9995 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9996 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9997 enum pipe trans_edp_pipe;
9998 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9999 default:
10000 WARN(1, "unknown pipe linked to edp transcoder\n");
10001 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10002 case TRANS_DDI_EDP_INPUT_A_ON:
10003 trans_edp_pipe = PIPE_A;
10004 break;
10005 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10006 trans_edp_pipe = PIPE_B;
10007 break;
10008 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10009 trans_edp_pipe = PIPE_C;
10010 break;
10011 }
10012
10013 if (trans_edp_pipe == crtc->pipe)
10014 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10015 }
10016
10017 if (!intel_display_power_is_enabled(dev_priv,
10018 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10019 return false;
10020
10021 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10022 if (!(tmp & PIPECONF_ENABLE))
10023 return false;
10024
10025 haswell_get_ddi_port_state(crtc, pipe_config);
10026
10027 intel_get_pipe_timings(crtc, pipe_config);
10028
10029 if (INTEL_INFO(dev)->gen >= 9) {
10030 skl_init_scalers(dev, crtc, pipe_config);
10031 }
10032
10033 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10034
10035 if (INTEL_INFO(dev)->gen >= 9) {
10036 pipe_config->scaler_state.scaler_id = -1;
10037 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10038 }
10039
10040 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10041 if (INTEL_INFO(dev)->gen >= 9)
10042 skylake_get_pfit_config(crtc, pipe_config);
10043 else
10044 ironlake_get_pfit_config(crtc, pipe_config);
10045 }
10046
10047 if (IS_HASWELL(dev))
10048 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10049 (I915_READ(IPS_CTL) & IPS_ENABLE);
10050
10051 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10052 pipe_config->pixel_multiplier =
10053 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10054 } else {
10055 pipe_config->pixel_multiplier = 1;
10056 }
10057
10058 return true;
10059 }
10060
10061 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10062 const struct intel_plane_state *plane_state)
10063 {
10064 struct drm_device *dev = crtc->dev;
10065 struct drm_i915_private *dev_priv = dev->dev_private;
10066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10067 uint32_t cntl = 0, size = 0;
10068
10069 if (plane_state && plane_state->visible) {
10070 unsigned int width = plane_state->base.crtc_w;
10071 unsigned int height = plane_state->base.crtc_h;
10072 unsigned int stride = roundup_pow_of_two(width) * 4;
10073
10074 switch (stride) {
10075 default:
10076 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10077 width, stride);
10078 stride = 256;
10079 /* fallthrough */
10080 case 256:
10081 case 512:
10082 case 1024:
10083 case 2048:
10084 break;
10085 }
10086
10087 cntl |= CURSOR_ENABLE |
10088 CURSOR_GAMMA_ENABLE |
10089 CURSOR_FORMAT_ARGB |
10090 CURSOR_STRIDE(stride);
10091
10092 size = (height << 12) | width;
10093 }
10094
10095 if (intel_crtc->cursor_cntl != 0 &&
10096 (intel_crtc->cursor_base != base ||
10097 intel_crtc->cursor_size != size ||
10098 intel_crtc->cursor_cntl != cntl)) {
10099 /* On these chipsets we can only modify the base/size/stride
10100 * whilst the cursor is disabled.
10101 */
10102 I915_WRITE(CURCNTR(PIPE_A), 0);
10103 POSTING_READ(CURCNTR(PIPE_A));
10104 intel_crtc->cursor_cntl = 0;
10105 }
10106
10107 if (intel_crtc->cursor_base != base) {
10108 I915_WRITE(CURBASE(PIPE_A), base);
10109 intel_crtc->cursor_base = base;
10110 }
10111
10112 if (intel_crtc->cursor_size != size) {
10113 I915_WRITE(CURSIZE, size);
10114 intel_crtc->cursor_size = size;
10115 }
10116
10117 if (intel_crtc->cursor_cntl != cntl) {
10118 I915_WRITE(CURCNTR(PIPE_A), cntl);
10119 POSTING_READ(CURCNTR(PIPE_A));
10120 intel_crtc->cursor_cntl = cntl;
10121 }
10122 }
10123
10124 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10125 const struct intel_plane_state *plane_state)
10126 {
10127 struct drm_device *dev = crtc->dev;
10128 struct drm_i915_private *dev_priv = dev->dev_private;
10129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10130 int pipe = intel_crtc->pipe;
10131 uint32_t cntl = 0;
10132
10133 if (plane_state && plane_state->visible) {
10134 cntl = MCURSOR_GAMMA_ENABLE;
10135 switch (plane_state->base.crtc_w) {
10136 case 64:
10137 cntl |= CURSOR_MODE_64_ARGB_AX;
10138 break;
10139 case 128:
10140 cntl |= CURSOR_MODE_128_ARGB_AX;
10141 break;
10142 case 256:
10143 cntl |= CURSOR_MODE_256_ARGB_AX;
10144 break;
10145 default:
10146 MISSING_CASE(plane_state->base.crtc_w);
10147 return;
10148 }
10149 cntl |= pipe << 28; /* Connect to correct pipe */
10150
10151 if (HAS_DDI(dev))
10152 cntl |= CURSOR_PIPE_CSC_ENABLE;
10153
10154 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10155 cntl |= CURSOR_ROTATE_180;
10156 }
10157
10158 if (intel_crtc->cursor_cntl != cntl) {
10159 I915_WRITE(CURCNTR(pipe), cntl);
10160 POSTING_READ(CURCNTR(pipe));
10161 intel_crtc->cursor_cntl = cntl;
10162 }
10163
10164 /* and commit changes on next vblank */
10165 I915_WRITE(CURBASE(pipe), base);
10166 POSTING_READ(CURBASE(pipe));
10167
10168 intel_crtc->cursor_base = base;
10169 }
10170
10171 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10172 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10173 const struct intel_plane_state *plane_state)
10174 {
10175 struct drm_device *dev = crtc->dev;
10176 struct drm_i915_private *dev_priv = dev->dev_private;
10177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10178 int pipe = intel_crtc->pipe;
10179 u32 base = intel_crtc->cursor_addr;
10180 u32 pos = 0;
10181
10182 if (plane_state) {
10183 int x = plane_state->base.crtc_x;
10184 int y = plane_state->base.crtc_y;
10185
10186 if (x < 0) {
10187 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10188 x = -x;
10189 }
10190 pos |= x << CURSOR_X_SHIFT;
10191
10192 if (y < 0) {
10193 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10194 y = -y;
10195 }
10196 pos |= y << CURSOR_Y_SHIFT;
10197
10198 /* ILK+ do this automagically */
10199 if (HAS_GMCH_DISPLAY(dev) &&
10200 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10201 base += (plane_state->base.crtc_h *
10202 plane_state->base.crtc_w - 1) * 4;
10203 }
10204 }
10205
10206 I915_WRITE(CURPOS(pipe), pos);
10207
10208 if (IS_845G(dev) || IS_I865G(dev))
10209 i845_update_cursor(crtc, base, plane_state);
10210 else
10211 i9xx_update_cursor(crtc, base, plane_state);
10212 }
10213
10214 static bool cursor_size_ok(struct drm_device *dev,
10215 uint32_t width, uint32_t height)
10216 {
10217 if (width == 0 || height == 0)
10218 return false;
10219
10220 /*
10221 * 845g/865g are special in that they are only limited by
10222 * the width of their cursors, the height is arbitrary up to
10223 * the precision of the register. Everything else requires
10224 * square cursors, limited to a few power-of-two sizes.
10225 */
10226 if (IS_845G(dev) || IS_I865G(dev)) {
10227 if ((width & 63) != 0)
10228 return false;
10229
10230 if (width > (IS_845G(dev) ? 64 : 512))
10231 return false;
10232
10233 if (height > 1023)
10234 return false;
10235 } else {
10236 switch (width | height) {
10237 case 256:
10238 case 128:
10239 if (IS_GEN2(dev))
10240 return false;
10241 case 64:
10242 break;
10243 default:
10244 return false;
10245 }
10246 }
10247
10248 return true;
10249 }
10250
10251 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10252 u16 *blue, uint32_t start, uint32_t size)
10253 {
10254 int end = (start + size > 256) ? 256 : start + size, i;
10255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10256
10257 for (i = start; i < end; i++) {
10258 intel_crtc->lut_r[i] = red[i] >> 8;
10259 intel_crtc->lut_g[i] = green[i] >> 8;
10260 intel_crtc->lut_b[i] = blue[i] >> 8;
10261 }
10262
10263 intel_crtc_load_lut(crtc);
10264 }
10265
10266 /* VESA 640x480x72Hz mode to set on the pipe */
10267 static struct drm_display_mode load_detect_mode = {
10268 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10269 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10270 };
10271
10272 struct drm_framebuffer *
10273 __intel_framebuffer_create(struct drm_device *dev,
10274 struct drm_mode_fb_cmd2 *mode_cmd,
10275 struct drm_i915_gem_object *obj)
10276 {
10277 struct intel_framebuffer *intel_fb;
10278 int ret;
10279
10280 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10281 if (!intel_fb)
10282 return ERR_PTR(-ENOMEM);
10283
10284 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10285 if (ret)
10286 goto err;
10287
10288 return &intel_fb->base;
10289
10290 err:
10291 kfree(intel_fb);
10292 return ERR_PTR(ret);
10293 }
10294
10295 static struct drm_framebuffer *
10296 intel_framebuffer_create(struct drm_device *dev,
10297 struct drm_mode_fb_cmd2 *mode_cmd,
10298 struct drm_i915_gem_object *obj)
10299 {
10300 struct drm_framebuffer *fb;
10301 int ret;
10302
10303 ret = i915_mutex_lock_interruptible(dev);
10304 if (ret)
10305 return ERR_PTR(ret);
10306 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10307 mutex_unlock(&dev->struct_mutex);
10308
10309 return fb;
10310 }
10311
10312 static u32
10313 intel_framebuffer_pitch_for_width(int width, int bpp)
10314 {
10315 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10316 return ALIGN(pitch, 64);
10317 }
10318
10319 static u32
10320 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10321 {
10322 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10323 return PAGE_ALIGN(pitch * mode->vdisplay);
10324 }
10325
10326 static struct drm_framebuffer *
10327 intel_framebuffer_create_for_mode(struct drm_device *dev,
10328 struct drm_display_mode *mode,
10329 int depth, int bpp)
10330 {
10331 struct drm_framebuffer *fb;
10332 struct drm_i915_gem_object *obj;
10333 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10334
10335 obj = i915_gem_alloc_object(dev,
10336 intel_framebuffer_size_for_mode(mode, bpp));
10337 if (obj == NULL)
10338 return ERR_PTR(-ENOMEM);
10339
10340 mode_cmd.width = mode->hdisplay;
10341 mode_cmd.height = mode->vdisplay;
10342 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10343 bpp);
10344 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10345
10346 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10347 if (IS_ERR(fb))
10348 drm_gem_object_unreference_unlocked(&obj->base);
10349
10350 return fb;
10351 }
10352
10353 static struct drm_framebuffer *
10354 mode_fits_in_fbdev(struct drm_device *dev,
10355 struct drm_display_mode *mode)
10356 {
10357 #ifdef CONFIG_DRM_FBDEV_EMULATION
10358 struct drm_i915_private *dev_priv = dev->dev_private;
10359 struct drm_i915_gem_object *obj;
10360 struct drm_framebuffer *fb;
10361
10362 if (!dev_priv->fbdev)
10363 return NULL;
10364
10365 if (!dev_priv->fbdev->fb)
10366 return NULL;
10367
10368 obj = dev_priv->fbdev->fb->obj;
10369 BUG_ON(!obj);
10370
10371 fb = &dev_priv->fbdev->fb->base;
10372 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10373 fb->bits_per_pixel))
10374 return NULL;
10375
10376 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10377 return NULL;
10378
10379 return fb;
10380 #else
10381 return NULL;
10382 #endif
10383 }
10384
10385 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10386 struct drm_crtc *crtc,
10387 struct drm_display_mode *mode,
10388 struct drm_framebuffer *fb,
10389 int x, int y)
10390 {
10391 struct drm_plane_state *plane_state;
10392 int hdisplay, vdisplay;
10393 int ret;
10394
10395 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10396 if (IS_ERR(plane_state))
10397 return PTR_ERR(plane_state);
10398
10399 if (mode)
10400 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10401 else
10402 hdisplay = vdisplay = 0;
10403
10404 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10405 if (ret)
10406 return ret;
10407 drm_atomic_set_fb_for_plane(plane_state, fb);
10408 plane_state->crtc_x = 0;
10409 plane_state->crtc_y = 0;
10410 plane_state->crtc_w = hdisplay;
10411 plane_state->crtc_h = vdisplay;
10412 plane_state->src_x = x << 16;
10413 plane_state->src_y = y << 16;
10414 plane_state->src_w = hdisplay << 16;
10415 plane_state->src_h = vdisplay << 16;
10416
10417 return 0;
10418 }
10419
10420 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10421 struct drm_display_mode *mode,
10422 struct intel_load_detect_pipe *old,
10423 struct drm_modeset_acquire_ctx *ctx)
10424 {
10425 struct intel_crtc *intel_crtc;
10426 struct intel_encoder *intel_encoder =
10427 intel_attached_encoder(connector);
10428 struct drm_crtc *possible_crtc;
10429 struct drm_encoder *encoder = &intel_encoder->base;
10430 struct drm_crtc *crtc = NULL;
10431 struct drm_device *dev = encoder->dev;
10432 struct drm_framebuffer *fb;
10433 struct drm_mode_config *config = &dev->mode_config;
10434 struct drm_atomic_state *state = NULL;
10435 struct drm_connector_state *connector_state;
10436 struct intel_crtc_state *crtc_state;
10437 int ret, i = -1;
10438
10439 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10440 connector->base.id, connector->name,
10441 encoder->base.id, encoder->name);
10442
10443 retry:
10444 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10445 if (ret)
10446 goto fail;
10447
10448 /*
10449 * Algorithm gets a little messy:
10450 *
10451 * - if the connector already has an assigned crtc, use it (but make
10452 * sure it's on first)
10453 *
10454 * - try to find the first unused crtc that can drive this connector,
10455 * and use that if we find one
10456 */
10457
10458 /* See if we already have a CRTC for this connector */
10459 if (encoder->crtc) {
10460 crtc = encoder->crtc;
10461
10462 ret = drm_modeset_lock(&crtc->mutex, ctx);
10463 if (ret)
10464 goto fail;
10465 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10466 if (ret)
10467 goto fail;
10468
10469 old->dpms_mode = connector->dpms;
10470 old->load_detect_temp = false;
10471
10472 /* Make sure the crtc and connector are running */
10473 if (connector->dpms != DRM_MODE_DPMS_ON)
10474 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10475
10476 return true;
10477 }
10478
10479 /* Find an unused one (if possible) */
10480 for_each_crtc(dev, possible_crtc) {
10481 i++;
10482 if (!(encoder->possible_crtcs & (1 << i)))
10483 continue;
10484 if (possible_crtc->state->enable)
10485 continue;
10486
10487 crtc = possible_crtc;
10488 break;
10489 }
10490
10491 /*
10492 * If we didn't find an unused CRTC, don't use any.
10493 */
10494 if (!crtc) {
10495 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10496 goto fail;
10497 }
10498
10499 ret = drm_modeset_lock(&crtc->mutex, ctx);
10500 if (ret)
10501 goto fail;
10502 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10503 if (ret)
10504 goto fail;
10505
10506 intel_crtc = to_intel_crtc(crtc);
10507 old->dpms_mode = connector->dpms;
10508 old->load_detect_temp = true;
10509 old->release_fb = NULL;
10510
10511 state = drm_atomic_state_alloc(dev);
10512 if (!state)
10513 return false;
10514
10515 state->acquire_ctx = ctx;
10516
10517 connector_state = drm_atomic_get_connector_state(state, connector);
10518 if (IS_ERR(connector_state)) {
10519 ret = PTR_ERR(connector_state);
10520 goto fail;
10521 }
10522
10523 connector_state->crtc = crtc;
10524
10525 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10526 if (IS_ERR(crtc_state)) {
10527 ret = PTR_ERR(crtc_state);
10528 goto fail;
10529 }
10530
10531 crtc_state->base.active = crtc_state->base.enable = true;
10532
10533 if (!mode)
10534 mode = &load_detect_mode;
10535
10536 /* We need a framebuffer large enough to accommodate all accesses
10537 * that the plane may generate whilst we perform load detection.
10538 * We can not rely on the fbcon either being present (we get called
10539 * during its initialisation to detect all boot displays, or it may
10540 * not even exist) or that it is large enough to satisfy the
10541 * requested mode.
10542 */
10543 fb = mode_fits_in_fbdev(dev, mode);
10544 if (fb == NULL) {
10545 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10546 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10547 old->release_fb = fb;
10548 } else
10549 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10550 if (IS_ERR(fb)) {
10551 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10552 goto fail;
10553 }
10554
10555 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10556 if (ret)
10557 goto fail;
10558
10559 drm_mode_copy(&crtc_state->base.mode, mode);
10560
10561 if (drm_atomic_commit(state)) {
10562 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10563 if (old->release_fb)
10564 old->release_fb->funcs->destroy(old->release_fb);
10565 goto fail;
10566 }
10567 crtc->primary->crtc = crtc;
10568
10569 /* let the connector get through one full cycle before testing */
10570 intel_wait_for_vblank(dev, intel_crtc->pipe);
10571 return true;
10572
10573 fail:
10574 drm_atomic_state_free(state);
10575 state = NULL;
10576
10577 if (ret == -EDEADLK) {
10578 drm_modeset_backoff(ctx);
10579 goto retry;
10580 }
10581
10582 return false;
10583 }
10584
10585 void intel_release_load_detect_pipe(struct drm_connector *connector,
10586 struct intel_load_detect_pipe *old,
10587 struct drm_modeset_acquire_ctx *ctx)
10588 {
10589 struct drm_device *dev = connector->dev;
10590 struct intel_encoder *intel_encoder =
10591 intel_attached_encoder(connector);
10592 struct drm_encoder *encoder = &intel_encoder->base;
10593 struct drm_crtc *crtc = encoder->crtc;
10594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10595 struct drm_atomic_state *state;
10596 struct drm_connector_state *connector_state;
10597 struct intel_crtc_state *crtc_state;
10598 int ret;
10599
10600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10601 connector->base.id, connector->name,
10602 encoder->base.id, encoder->name);
10603
10604 if (old->load_detect_temp) {
10605 state = drm_atomic_state_alloc(dev);
10606 if (!state)
10607 goto fail;
10608
10609 state->acquire_ctx = ctx;
10610
10611 connector_state = drm_atomic_get_connector_state(state, connector);
10612 if (IS_ERR(connector_state))
10613 goto fail;
10614
10615 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10616 if (IS_ERR(crtc_state))
10617 goto fail;
10618
10619 connector_state->crtc = NULL;
10620
10621 crtc_state->base.enable = crtc_state->base.active = false;
10622
10623 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10624 0, 0);
10625 if (ret)
10626 goto fail;
10627
10628 ret = drm_atomic_commit(state);
10629 if (ret)
10630 goto fail;
10631
10632 if (old->release_fb) {
10633 drm_framebuffer_unregister_private(old->release_fb);
10634 drm_framebuffer_unreference(old->release_fb);
10635 }
10636
10637 return;
10638 }
10639
10640 /* Switch crtc and encoder back off if necessary */
10641 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10642 connector->funcs->dpms(connector, old->dpms_mode);
10643
10644 return;
10645 fail:
10646 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10647 drm_atomic_state_free(state);
10648 }
10649
10650 static int i9xx_pll_refclk(struct drm_device *dev,
10651 const struct intel_crtc_state *pipe_config)
10652 {
10653 struct drm_i915_private *dev_priv = dev->dev_private;
10654 u32 dpll = pipe_config->dpll_hw_state.dpll;
10655
10656 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10657 return dev_priv->vbt.lvds_ssc_freq;
10658 else if (HAS_PCH_SPLIT(dev))
10659 return 120000;
10660 else if (!IS_GEN2(dev))
10661 return 96000;
10662 else
10663 return 48000;
10664 }
10665
10666 /* Returns the clock of the currently programmed mode of the given pipe. */
10667 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10668 struct intel_crtc_state *pipe_config)
10669 {
10670 struct drm_device *dev = crtc->base.dev;
10671 struct drm_i915_private *dev_priv = dev->dev_private;
10672 int pipe = pipe_config->cpu_transcoder;
10673 u32 dpll = pipe_config->dpll_hw_state.dpll;
10674 u32 fp;
10675 intel_clock_t clock;
10676 int port_clock;
10677 int refclk = i9xx_pll_refclk(dev, pipe_config);
10678
10679 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10680 fp = pipe_config->dpll_hw_state.fp0;
10681 else
10682 fp = pipe_config->dpll_hw_state.fp1;
10683
10684 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10685 if (IS_PINEVIEW(dev)) {
10686 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10687 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10688 } else {
10689 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10690 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10691 }
10692
10693 if (!IS_GEN2(dev)) {
10694 if (IS_PINEVIEW(dev))
10695 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10696 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10697 else
10698 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10699 DPLL_FPA01_P1_POST_DIV_SHIFT);
10700
10701 switch (dpll & DPLL_MODE_MASK) {
10702 case DPLLB_MODE_DAC_SERIAL:
10703 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10704 5 : 10;
10705 break;
10706 case DPLLB_MODE_LVDS:
10707 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10708 7 : 14;
10709 break;
10710 default:
10711 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10712 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10713 return;
10714 }
10715
10716 if (IS_PINEVIEW(dev))
10717 port_clock = pnv_calc_dpll_params(refclk, &clock);
10718 else
10719 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10720 } else {
10721 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10722 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10723
10724 if (is_lvds) {
10725 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10726 DPLL_FPA01_P1_POST_DIV_SHIFT);
10727
10728 if (lvds & LVDS_CLKB_POWER_UP)
10729 clock.p2 = 7;
10730 else
10731 clock.p2 = 14;
10732 } else {
10733 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10734 clock.p1 = 2;
10735 else {
10736 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10737 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10738 }
10739 if (dpll & PLL_P2_DIVIDE_BY_4)
10740 clock.p2 = 4;
10741 else
10742 clock.p2 = 2;
10743 }
10744
10745 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10746 }
10747
10748 /*
10749 * This value includes pixel_multiplier. We will use
10750 * port_clock to compute adjusted_mode.crtc_clock in the
10751 * encoder's get_config() function.
10752 */
10753 pipe_config->port_clock = port_clock;
10754 }
10755
10756 int intel_dotclock_calculate(int link_freq,
10757 const struct intel_link_m_n *m_n)
10758 {
10759 /*
10760 * The calculation for the data clock is:
10761 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10762 * But we want to avoid losing precison if possible, so:
10763 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10764 *
10765 * and the link clock is simpler:
10766 * link_clock = (m * link_clock) / n
10767 */
10768
10769 if (!m_n->link_n)
10770 return 0;
10771
10772 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10773 }
10774
10775 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10776 struct intel_crtc_state *pipe_config)
10777 {
10778 struct drm_device *dev = crtc->base.dev;
10779
10780 /* read out port_clock from the DPLL */
10781 i9xx_crtc_clock_get(crtc, pipe_config);
10782
10783 /*
10784 * This value does not include pixel_multiplier.
10785 * We will check that port_clock and adjusted_mode.crtc_clock
10786 * agree once we know their relationship in the encoder's
10787 * get_config() function.
10788 */
10789 pipe_config->base.adjusted_mode.crtc_clock =
10790 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10791 &pipe_config->fdi_m_n);
10792 }
10793
10794 /** Returns the currently programmed mode of the given pipe. */
10795 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10796 struct drm_crtc *crtc)
10797 {
10798 struct drm_i915_private *dev_priv = dev->dev_private;
10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10801 struct drm_display_mode *mode;
10802 struct intel_crtc_state *pipe_config;
10803 int htot = I915_READ(HTOTAL(cpu_transcoder));
10804 int hsync = I915_READ(HSYNC(cpu_transcoder));
10805 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10806 int vsync = I915_READ(VSYNC(cpu_transcoder));
10807 enum pipe pipe = intel_crtc->pipe;
10808
10809 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10810 if (!mode)
10811 return NULL;
10812
10813 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10814 if (!pipe_config) {
10815 kfree(mode);
10816 return NULL;
10817 }
10818
10819 /*
10820 * Construct a pipe_config sufficient for getting the clock info
10821 * back out of crtc_clock_get.
10822 *
10823 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10824 * to use a real value here instead.
10825 */
10826 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10827 pipe_config->pixel_multiplier = 1;
10828 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10829 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10830 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10831 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10832
10833 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10834 mode->hdisplay = (htot & 0xffff) + 1;
10835 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10836 mode->hsync_start = (hsync & 0xffff) + 1;
10837 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10838 mode->vdisplay = (vtot & 0xffff) + 1;
10839 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10840 mode->vsync_start = (vsync & 0xffff) + 1;
10841 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10842
10843 drm_mode_set_name(mode);
10844
10845 kfree(pipe_config);
10846
10847 return mode;
10848 }
10849
10850 void intel_mark_busy(struct drm_device *dev)
10851 {
10852 struct drm_i915_private *dev_priv = dev->dev_private;
10853
10854 if (dev_priv->mm.busy)
10855 return;
10856
10857 intel_runtime_pm_get(dev_priv);
10858 i915_update_gfx_val(dev_priv);
10859 if (INTEL_INFO(dev)->gen >= 6)
10860 gen6_rps_busy(dev_priv);
10861 dev_priv->mm.busy = true;
10862 }
10863
10864 void intel_mark_idle(struct drm_device *dev)
10865 {
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867
10868 if (!dev_priv->mm.busy)
10869 return;
10870
10871 dev_priv->mm.busy = false;
10872
10873 if (INTEL_INFO(dev)->gen >= 6)
10874 gen6_rps_idle(dev->dev_private);
10875
10876 intel_runtime_pm_put(dev_priv);
10877 }
10878
10879 static void intel_crtc_destroy(struct drm_crtc *crtc)
10880 {
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 struct drm_device *dev = crtc->dev;
10883 struct intel_unpin_work *work;
10884
10885 spin_lock_irq(&dev->event_lock);
10886 work = intel_crtc->unpin_work;
10887 intel_crtc->unpin_work = NULL;
10888 spin_unlock_irq(&dev->event_lock);
10889
10890 if (work) {
10891 cancel_work_sync(&work->work);
10892 kfree(work);
10893 }
10894
10895 drm_crtc_cleanup(crtc);
10896
10897 kfree(intel_crtc);
10898 }
10899
10900 static void intel_unpin_work_fn(struct work_struct *__work)
10901 {
10902 struct intel_unpin_work *work =
10903 container_of(__work, struct intel_unpin_work, work);
10904 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10905 struct drm_device *dev = crtc->base.dev;
10906 struct drm_plane *primary = crtc->base.primary;
10907
10908 mutex_lock(&dev->struct_mutex);
10909 intel_unpin_fb_obj(work->old_fb, primary->state);
10910 drm_gem_object_unreference(&work->pending_flip_obj->base);
10911
10912 if (work->flip_queued_req)
10913 i915_gem_request_assign(&work->flip_queued_req, NULL);
10914 mutex_unlock(&dev->struct_mutex);
10915
10916 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10917 drm_framebuffer_unreference(work->old_fb);
10918
10919 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10920 atomic_dec(&crtc->unpin_work_count);
10921
10922 kfree(work);
10923 }
10924
10925 static void do_intel_finish_page_flip(struct drm_device *dev,
10926 struct drm_crtc *crtc)
10927 {
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 struct intel_unpin_work *work;
10930 unsigned long flags;
10931
10932 /* Ignore early vblank irqs */
10933 if (intel_crtc == NULL)
10934 return;
10935
10936 /*
10937 * This is called both by irq handlers and the reset code (to complete
10938 * lost pageflips) so needs the full irqsave spinlocks.
10939 */
10940 spin_lock_irqsave(&dev->event_lock, flags);
10941 work = intel_crtc->unpin_work;
10942
10943 /* Ensure we don't miss a work->pending update ... */
10944 smp_rmb();
10945
10946 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10947 spin_unlock_irqrestore(&dev->event_lock, flags);
10948 return;
10949 }
10950
10951 page_flip_completed(intel_crtc);
10952
10953 spin_unlock_irqrestore(&dev->event_lock, flags);
10954 }
10955
10956 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10957 {
10958 struct drm_i915_private *dev_priv = dev->dev_private;
10959 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10960
10961 do_intel_finish_page_flip(dev, crtc);
10962 }
10963
10964 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10965 {
10966 struct drm_i915_private *dev_priv = dev->dev_private;
10967 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10968
10969 do_intel_finish_page_flip(dev, crtc);
10970 }
10971
10972 /* Is 'a' after or equal to 'b'? */
10973 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10974 {
10975 return !((a - b) & 0x80000000);
10976 }
10977
10978 static bool page_flip_finished(struct intel_crtc *crtc)
10979 {
10980 struct drm_device *dev = crtc->base.dev;
10981 struct drm_i915_private *dev_priv = dev->dev_private;
10982
10983 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10984 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10985 return true;
10986
10987 /*
10988 * The relevant registers doen't exist on pre-ctg.
10989 * As the flip done interrupt doesn't trigger for mmio
10990 * flips on gmch platforms, a flip count check isn't
10991 * really needed there. But since ctg has the registers,
10992 * include it in the check anyway.
10993 */
10994 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10995 return true;
10996
10997 /*
10998 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10999 * used the same base address. In that case the mmio flip might
11000 * have completed, but the CS hasn't even executed the flip yet.
11001 *
11002 * A flip count check isn't enough as the CS might have updated
11003 * the base address just after start of vblank, but before we
11004 * managed to process the interrupt. This means we'd complete the
11005 * CS flip too soon.
11006 *
11007 * Combining both checks should get us a good enough result. It may
11008 * still happen that the CS flip has been executed, but has not
11009 * yet actually completed. But in case the base address is the same
11010 * anyway, we don't really care.
11011 */
11012 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11013 crtc->unpin_work->gtt_offset &&
11014 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11015 crtc->unpin_work->flip_count);
11016 }
11017
11018 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11019 {
11020 struct drm_i915_private *dev_priv = dev->dev_private;
11021 struct intel_crtc *intel_crtc =
11022 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11023 unsigned long flags;
11024
11025
11026 /*
11027 * This is called both by irq handlers and the reset code (to complete
11028 * lost pageflips) so needs the full irqsave spinlocks.
11029 *
11030 * NB: An MMIO update of the plane base pointer will also
11031 * generate a page-flip completion irq, i.e. every modeset
11032 * is also accompanied by a spurious intel_prepare_page_flip().
11033 */
11034 spin_lock_irqsave(&dev->event_lock, flags);
11035 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11036 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11037 spin_unlock_irqrestore(&dev->event_lock, flags);
11038 }
11039
11040 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11041 {
11042 /* Ensure that the work item is consistent when activating it ... */
11043 smp_wmb();
11044 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11045 /* and that it is marked active as soon as the irq could fire. */
11046 smp_wmb();
11047 }
11048
11049 static int intel_gen2_queue_flip(struct drm_device *dev,
11050 struct drm_crtc *crtc,
11051 struct drm_framebuffer *fb,
11052 struct drm_i915_gem_object *obj,
11053 struct drm_i915_gem_request *req,
11054 uint32_t flags)
11055 {
11056 struct intel_engine_cs *ring = req->ring;
11057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11058 u32 flip_mask;
11059 int ret;
11060
11061 ret = intel_ring_begin(req, 6);
11062 if (ret)
11063 return ret;
11064
11065 /* Can't queue multiple flips, so wait for the previous
11066 * one to finish before executing the next.
11067 */
11068 if (intel_crtc->plane)
11069 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11070 else
11071 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11072 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11073 intel_ring_emit(ring, MI_NOOP);
11074 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11075 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11076 intel_ring_emit(ring, fb->pitches[0]);
11077 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11078 intel_ring_emit(ring, 0); /* aux display base address, unused */
11079
11080 intel_mark_page_flip_active(intel_crtc->unpin_work);
11081 return 0;
11082 }
11083
11084 static int intel_gen3_queue_flip(struct drm_device *dev,
11085 struct drm_crtc *crtc,
11086 struct drm_framebuffer *fb,
11087 struct drm_i915_gem_object *obj,
11088 struct drm_i915_gem_request *req,
11089 uint32_t flags)
11090 {
11091 struct intel_engine_cs *ring = req->ring;
11092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11093 u32 flip_mask;
11094 int ret;
11095
11096 ret = intel_ring_begin(req, 6);
11097 if (ret)
11098 return ret;
11099
11100 if (intel_crtc->plane)
11101 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11102 else
11103 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11104 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11105 intel_ring_emit(ring, MI_NOOP);
11106 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11108 intel_ring_emit(ring, fb->pitches[0]);
11109 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11110 intel_ring_emit(ring, MI_NOOP);
11111
11112 intel_mark_page_flip_active(intel_crtc->unpin_work);
11113 return 0;
11114 }
11115
11116 static int intel_gen4_queue_flip(struct drm_device *dev,
11117 struct drm_crtc *crtc,
11118 struct drm_framebuffer *fb,
11119 struct drm_i915_gem_object *obj,
11120 struct drm_i915_gem_request *req,
11121 uint32_t flags)
11122 {
11123 struct intel_engine_cs *ring = req->ring;
11124 struct drm_i915_private *dev_priv = dev->dev_private;
11125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11126 uint32_t pf, pipesrc;
11127 int ret;
11128
11129 ret = intel_ring_begin(req, 4);
11130 if (ret)
11131 return ret;
11132
11133 /* i965+ uses the linear or tiled offsets from the
11134 * Display Registers (which do not change across a page-flip)
11135 * so we need only reprogram the base address.
11136 */
11137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139 intel_ring_emit(ring, fb->pitches[0]);
11140 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11141 obj->tiling_mode);
11142
11143 /* XXX Enabling the panel-fitter across page-flip is so far
11144 * untested on non-native modes, so ignore it for now.
11145 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11146 */
11147 pf = 0;
11148 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11149 intel_ring_emit(ring, pf | pipesrc);
11150
11151 intel_mark_page_flip_active(intel_crtc->unpin_work);
11152 return 0;
11153 }
11154
11155 static int intel_gen6_queue_flip(struct drm_device *dev,
11156 struct drm_crtc *crtc,
11157 struct drm_framebuffer *fb,
11158 struct drm_i915_gem_object *obj,
11159 struct drm_i915_gem_request *req,
11160 uint32_t flags)
11161 {
11162 struct intel_engine_cs *ring = req->ring;
11163 struct drm_i915_private *dev_priv = dev->dev_private;
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 uint32_t pf, pipesrc;
11166 int ret;
11167
11168 ret = intel_ring_begin(req, 4);
11169 if (ret)
11170 return ret;
11171
11172 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11173 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11174 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11175 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11176
11177 /* Contrary to the suggestions in the documentation,
11178 * "Enable Panel Fitter" does not seem to be required when page
11179 * flipping with a non-native mode, and worse causes a normal
11180 * modeset to fail.
11181 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11182 */
11183 pf = 0;
11184 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11185 intel_ring_emit(ring, pf | pipesrc);
11186
11187 intel_mark_page_flip_active(intel_crtc->unpin_work);
11188 return 0;
11189 }
11190
11191 static int intel_gen7_queue_flip(struct drm_device *dev,
11192 struct drm_crtc *crtc,
11193 struct drm_framebuffer *fb,
11194 struct drm_i915_gem_object *obj,
11195 struct drm_i915_gem_request *req,
11196 uint32_t flags)
11197 {
11198 struct intel_engine_cs *ring = req->ring;
11199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11200 uint32_t plane_bit = 0;
11201 int len, ret;
11202
11203 switch (intel_crtc->plane) {
11204 case PLANE_A:
11205 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11206 break;
11207 case PLANE_B:
11208 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11209 break;
11210 case PLANE_C:
11211 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11212 break;
11213 default:
11214 WARN_ONCE(1, "unknown plane in flip command\n");
11215 return -ENODEV;
11216 }
11217
11218 len = 4;
11219 if (ring->id == RCS) {
11220 len += 6;
11221 /*
11222 * On Gen 8, SRM is now taking an extra dword to accommodate
11223 * 48bits addresses, and we need a NOOP for the batch size to
11224 * stay even.
11225 */
11226 if (IS_GEN8(dev))
11227 len += 2;
11228 }
11229
11230 /*
11231 * BSpec MI_DISPLAY_FLIP for IVB:
11232 * "The full packet must be contained within the same cache line."
11233 *
11234 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11235 * cacheline, if we ever start emitting more commands before
11236 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11237 * then do the cacheline alignment, and finally emit the
11238 * MI_DISPLAY_FLIP.
11239 */
11240 ret = intel_ring_cacheline_align(req);
11241 if (ret)
11242 return ret;
11243
11244 ret = intel_ring_begin(req, len);
11245 if (ret)
11246 return ret;
11247
11248 /* Unmask the flip-done completion message. Note that the bspec says that
11249 * we should do this for both the BCS and RCS, and that we must not unmask
11250 * more than one flip event at any time (or ensure that one flip message
11251 * can be sent by waiting for flip-done prior to queueing new flips).
11252 * Experimentation says that BCS works despite DERRMR masking all
11253 * flip-done completion events and that unmasking all planes at once
11254 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11255 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11256 */
11257 if (ring->id == RCS) {
11258 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11259 intel_ring_emit_reg(ring, DERRMR);
11260 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11261 DERRMR_PIPEB_PRI_FLIP_DONE |
11262 DERRMR_PIPEC_PRI_FLIP_DONE));
11263 if (IS_GEN8(dev))
11264 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11265 MI_SRM_LRM_GLOBAL_GTT);
11266 else
11267 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11268 MI_SRM_LRM_GLOBAL_GTT);
11269 intel_ring_emit_reg(ring, DERRMR);
11270 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11271 if (IS_GEN8(dev)) {
11272 intel_ring_emit(ring, 0);
11273 intel_ring_emit(ring, MI_NOOP);
11274 }
11275 }
11276
11277 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11278 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11279 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11280 intel_ring_emit(ring, (MI_NOOP));
11281
11282 intel_mark_page_flip_active(intel_crtc->unpin_work);
11283 return 0;
11284 }
11285
11286 static bool use_mmio_flip(struct intel_engine_cs *ring,
11287 struct drm_i915_gem_object *obj)
11288 {
11289 /*
11290 * This is not being used for older platforms, because
11291 * non-availability of flip done interrupt forces us to use
11292 * CS flips. Older platforms derive flip done using some clever
11293 * tricks involving the flip_pending status bits and vblank irqs.
11294 * So using MMIO flips there would disrupt this mechanism.
11295 */
11296
11297 if (ring == NULL)
11298 return true;
11299
11300 if (INTEL_INFO(ring->dev)->gen < 5)
11301 return false;
11302
11303 if (i915.use_mmio_flip < 0)
11304 return false;
11305 else if (i915.use_mmio_flip > 0)
11306 return true;
11307 else if (i915.enable_execlists)
11308 return true;
11309 else if (obj->base.dma_buf &&
11310 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11311 false))
11312 return true;
11313 else
11314 return ring != i915_gem_request_get_ring(obj->last_write_req);
11315 }
11316
11317 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11318 unsigned int rotation,
11319 struct intel_unpin_work *work)
11320 {
11321 struct drm_device *dev = intel_crtc->base.dev;
11322 struct drm_i915_private *dev_priv = dev->dev_private;
11323 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11324 const enum pipe pipe = intel_crtc->pipe;
11325 u32 ctl, stride, tile_height;
11326
11327 ctl = I915_READ(PLANE_CTL(pipe, 0));
11328 ctl &= ~PLANE_CTL_TILED_MASK;
11329 switch (fb->modifier[0]) {
11330 case DRM_FORMAT_MOD_NONE:
11331 break;
11332 case I915_FORMAT_MOD_X_TILED:
11333 ctl |= PLANE_CTL_TILED_X;
11334 break;
11335 case I915_FORMAT_MOD_Y_TILED:
11336 ctl |= PLANE_CTL_TILED_Y;
11337 break;
11338 case I915_FORMAT_MOD_Yf_TILED:
11339 ctl |= PLANE_CTL_TILED_YF;
11340 break;
11341 default:
11342 MISSING_CASE(fb->modifier[0]);
11343 }
11344
11345 /*
11346 * The stride is either expressed as a multiple of 64 bytes chunks for
11347 * linear buffers or in number of tiles for tiled buffers.
11348 */
11349 if (intel_rotation_90_or_270(rotation)) {
11350 /* stride = Surface height in tiles */
11351 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11352 stride = DIV_ROUND_UP(fb->height, tile_height);
11353 } else {
11354 stride = fb->pitches[0] /
11355 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11356 fb->pixel_format);
11357 }
11358
11359 /*
11360 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11361 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11362 */
11363 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11364 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11365
11366 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11367 POSTING_READ(PLANE_SURF(pipe, 0));
11368 }
11369
11370 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11371 struct intel_unpin_work *work)
11372 {
11373 struct drm_device *dev = intel_crtc->base.dev;
11374 struct drm_i915_private *dev_priv = dev->dev_private;
11375 struct intel_framebuffer *intel_fb =
11376 to_intel_framebuffer(intel_crtc->base.primary->fb);
11377 struct drm_i915_gem_object *obj = intel_fb->obj;
11378 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11379 u32 dspcntr;
11380
11381 dspcntr = I915_READ(reg);
11382
11383 if (obj->tiling_mode != I915_TILING_NONE)
11384 dspcntr |= DISPPLANE_TILED;
11385 else
11386 dspcntr &= ~DISPPLANE_TILED;
11387
11388 I915_WRITE(reg, dspcntr);
11389
11390 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11391 POSTING_READ(DSPSURF(intel_crtc->plane));
11392 }
11393
11394 /*
11395 * XXX: This is the temporary way to update the plane registers until we get
11396 * around to using the usual plane update functions for MMIO flips
11397 */
11398 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11399 {
11400 struct intel_crtc *crtc = mmio_flip->crtc;
11401 struct intel_unpin_work *work;
11402
11403 spin_lock_irq(&crtc->base.dev->event_lock);
11404 work = crtc->unpin_work;
11405 spin_unlock_irq(&crtc->base.dev->event_lock);
11406 if (work == NULL)
11407 return;
11408
11409 intel_mark_page_flip_active(work);
11410
11411 intel_pipe_update_start(crtc);
11412
11413 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11414 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11415 else
11416 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11417 ilk_do_mmio_flip(crtc, work);
11418
11419 intel_pipe_update_end(crtc);
11420 }
11421
11422 static void intel_mmio_flip_work_func(struct work_struct *work)
11423 {
11424 struct intel_mmio_flip *mmio_flip =
11425 container_of(work, struct intel_mmio_flip, work);
11426 struct intel_framebuffer *intel_fb =
11427 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11428 struct drm_i915_gem_object *obj = intel_fb->obj;
11429
11430 if (mmio_flip->req) {
11431 WARN_ON(__i915_wait_request(mmio_flip->req,
11432 mmio_flip->crtc->reset_counter,
11433 false, NULL,
11434 &mmio_flip->i915->rps.mmioflips));
11435 i915_gem_request_unreference__unlocked(mmio_flip->req);
11436 }
11437
11438 /* For framebuffer backed by dmabuf, wait for fence */
11439 if (obj->base.dma_buf)
11440 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11441 false, false,
11442 MAX_SCHEDULE_TIMEOUT) < 0);
11443
11444 intel_do_mmio_flip(mmio_flip);
11445 kfree(mmio_flip);
11446 }
11447
11448 static int intel_queue_mmio_flip(struct drm_device *dev,
11449 struct drm_crtc *crtc,
11450 struct drm_i915_gem_object *obj)
11451 {
11452 struct intel_mmio_flip *mmio_flip;
11453
11454 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11455 if (mmio_flip == NULL)
11456 return -ENOMEM;
11457
11458 mmio_flip->i915 = to_i915(dev);
11459 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11460 mmio_flip->crtc = to_intel_crtc(crtc);
11461 mmio_flip->rotation = crtc->primary->state->rotation;
11462
11463 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11464 schedule_work(&mmio_flip->work);
11465
11466 return 0;
11467 }
11468
11469 static int intel_default_queue_flip(struct drm_device *dev,
11470 struct drm_crtc *crtc,
11471 struct drm_framebuffer *fb,
11472 struct drm_i915_gem_object *obj,
11473 struct drm_i915_gem_request *req,
11474 uint32_t flags)
11475 {
11476 return -ENODEV;
11477 }
11478
11479 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11480 struct drm_crtc *crtc)
11481 {
11482 struct drm_i915_private *dev_priv = dev->dev_private;
11483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11484 struct intel_unpin_work *work = intel_crtc->unpin_work;
11485 u32 addr;
11486
11487 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11488 return true;
11489
11490 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11491 return false;
11492
11493 if (!work->enable_stall_check)
11494 return false;
11495
11496 if (work->flip_ready_vblank == 0) {
11497 if (work->flip_queued_req &&
11498 !i915_gem_request_completed(work->flip_queued_req, true))
11499 return false;
11500
11501 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11502 }
11503
11504 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11505 return false;
11506
11507 /* Potential stall - if we see that the flip has happened,
11508 * assume a missed interrupt. */
11509 if (INTEL_INFO(dev)->gen >= 4)
11510 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11511 else
11512 addr = I915_READ(DSPADDR(intel_crtc->plane));
11513
11514 /* There is a potential issue here with a false positive after a flip
11515 * to the same address. We could address this by checking for a
11516 * non-incrementing frame counter.
11517 */
11518 return addr == work->gtt_offset;
11519 }
11520
11521 void intel_check_page_flip(struct drm_device *dev, int pipe)
11522 {
11523 struct drm_i915_private *dev_priv = dev->dev_private;
11524 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11526 struct intel_unpin_work *work;
11527
11528 WARN_ON(!in_interrupt());
11529
11530 if (crtc == NULL)
11531 return;
11532
11533 spin_lock(&dev->event_lock);
11534 work = intel_crtc->unpin_work;
11535 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11536 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11537 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11538 page_flip_completed(intel_crtc);
11539 work = NULL;
11540 }
11541 if (work != NULL &&
11542 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11543 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11544 spin_unlock(&dev->event_lock);
11545 }
11546
11547 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11548 struct drm_framebuffer *fb,
11549 struct drm_pending_vblank_event *event,
11550 uint32_t page_flip_flags)
11551 {
11552 struct drm_device *dev = crtc->dev;
11553 struct drm_i915_private *dev_priv = dev->dev_private;
11554 struct drm_framebuffer *old_fb = crtc->primary->fb;
11555 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11557 struct drm_plane *primary = crtc->primary;
11558 enum pipe pipe = intel_crtc->pipe;
11559 struct intel_unpin_work *work;
11560 struct intel_engine_cs *ring;
11561 bool mmio_flip;
11562 struct drm_i915_gem_request *request = NULL;
11563 int ret;
11564
11565 /*
11566 * drm_mode_page_flip_ioctl() should already catch this, but double
11567 * check to be safe. In the future we may enable pageflipping from
11568 * a disabled primary plane.
11569 */
11570 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11571 return -EBUSY;
11572
11573 /* Can't change pixel format via MI display flips. */
11574 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11575 return -EINVAL;
11576
11577 /*
11578 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11579 * Note that pitch changes could also affect these register.
11580 */
11581 if (INTEL_INFO(dev)->gen > 3 &&
11582 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11583 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11584 return -EINVAL;
11585
11586 if (i915_terminally_wedged(&dev_priv->gpu_error))
11587 goto out_hang;
11588
11589 work = kzalloc(sizeof(*work), GFP_KERNEL);
11590 if (work == NULL)
11591 return -ENOMEM;
11592
11593 work->event = event;
11594 work->crtc = crtc;
11595 work->old_fb = old_fb;
11596 INIT_WORK(&work->work, intel_unpin_work_fn);
11597
11598 ret = drm_crtc_vblank_get(crtc);
11599 if (ret)
11600 goto free_work;
11601
11602 /* We borrow the event spin lock for protecting unpin_work */
11603 spin_lock_irq(&dev->event_lock);
11604 if (intel_crtc->unpin_work) {
11605 /* Before declaring the flip queue wedged, check if
11606 * the hardware completed the operation behind our backs.
11607 */
11608 if (__intel_pageflip_stall_check(dev, crtc)) {
11609 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11610 page_flip_completed(intel_crtc);
11611 } else {
11612 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11613 spin_unlock_irq(&dev->event_lock);
11614
11615 drm_crtc_vblank_put(crtc);
11616 kfree(work);
11617 return -EBUSY;
11618 }
11619 }
11620 intel_crtc->unpin_work = work;
11621 spin_unlock_irq(&dev->event_lock);
11622
11623 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11624 flush_workqueue(dev_priv->wq);
11625
11626 /* Reference the objects for the scheduled work. */
11627 drm_framebuffer_reference(work->old_fb);
11628 drm_gem_object_reference(&obj->base);
11629
11630 crtc->primary->fb = fb;
11631 update_state_fb(crtc->primary);
11632
11633 work->pending_flip_obj = obj;
11634
11635 ret = i915_mutex_lock_interruptible(dev);
11636 if (ret)
11637 goto cleanup;
11638
11639 atomic_inc(&intel_crtc->unpin_work_count);
11640 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11641
11642 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11643 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11644
11645 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11646 ring = &dev_priv->ring[BCS];
11647 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11648 /* vlv: DISPLAY_FLIP fails to change tiling */
11649 ring = NULL;
11650 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11651 ring = &dev_priv->ring[BCS];
11652 } else if (INTEL_INFO(dev)->gen >= 7) {
11653 ring = i915_gem_request_get_ring(obj->last_write_req);
11654 if (ring == NULL || ring->id != RCS)
11655 ring = &dev_priv->ring[BCS];
11656 } else {
11657 ring = &dev_priv->ring[RCS];
11658 }
11659
11660 mmio_flip = use_mmio_flip(ring, obj);
11661
11662 /* When using CS flips, we want to emit semaphores between rings.
11663 * However, when using mmio flips we will create a task to do the
11664 * synchronisation, so all we want here is to pin the framebuffer
11665 * into the display plane and skip any waits.
11666 */
11667 if (!mmio_flip) {
11668 ret = i915_gem_object_sync(obj, ring, &request);
11669 if (ret)
11670 goto cleanup_pending;
11671 }
11672
11673 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11674 crtc->primary->state);
11675 if (ret)
11676 goto cleanup_pending;
11677
11678 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11679 obj, 0);
11680 work->gtt_offset += intel_crtc->dspaddr_offset;
11681
11682 if (mmio_flip) {
11683 ret = intel_queue_mmio_flip(dev, crtc, obj);
11684 if (ret)
11685 goto cleanup_unpin;
11686
11687 i915_gem_request_assign(&work->flip_queued_req,
11688 obj->last_write_req);
11689 } else {
11690 if (!request) {
11691 request = i915_gem_request_alloc(ring, NULL);
11692 if (IS_ERR(request)) {
11693 ret = PTR_ERR(request);
11694 goto cleanup_unpin;
11695 }
11696 }
11697
11698 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11699 page_flip_flags);
11700 if (ret)
11701 goto cleanup_unpin;
11702
11703 i915_gem_request_assign(&work->flip_queued_req, request);
11704 }
11705
11706 if (request)
11707 i915_add_request_no_flush(request);
11708
11709 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11710 work->enable_stall_check = true;
11711
11712 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11713 to_intel_plane(primary)->frontbuffer_bit);
11714 mutex_unlock(&dev->struct_mutex);
11715
11716 intel_fbc_deactivate(intel_crtc);
11717 intel_frontbuffer_flip_prepare(dev,
11718 to_intel_plane(primary)->frontbuffer_bit);
11719
11720 trace_i915_flip_request(intel_crtc->plane, obj);
11721
11722 return 0;
11723
11724 cleanup_unpin:
11725 intel_unpin_fb_obj(fb, crtc->primary->state);
11726 cleanup_pending:
11727 if (request)
11728 i915_gem_request_cancel(request);
11729 atomic_dec(&intel_crtc->unpin_work_count);
11730 mutex_unlock(&dev->struct_mutex);
11731 cleanup:
11732 crtc->primary->fb = old_fb;
11733 update_state_fb(crtc->primary);
11734
11735 drm_gem_object_unreference_unlocked(&obj->base);
11736 drm_framebuffer_unreference(work->old_fb);
11737
11738 spin_lock_irq(&dev->event_lock);
11739 intel_crtc->unpin_work = NULL;
11740 spin_unlock_irq(&dev->event_lock);
11741
11742 drm_crtc_vblank_put(crtc);
11743 free_work:
11744 kfree(work);
11745
11746 if (ret == -EIO) {
11747 struct drm_atomic_state *state;
11748 struct drm_plane_state *plane_state;
11749
11750 out_hang:
11751 state = drm_atomic_state_alloc(dev);
11752 if (!state)
11753 return -ENOMEM;
11754 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11755
11756 retry:
11757 plane_state = drm_atomic_get_plane_state(state, primary);
11758 ret = PTR_ERR_OR_ZERO(plane_state);
11759 if (!ret) {
11760 drm_atomic_set_fb_for_plane(plane_state, fb);
11761
11762 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11763 if (!ret)
11764 ret = drm_atomic_commit(state);
11765 }
11766
11767 if (ret == -EDEADLK) {
11768 drm_modeset_backoff(state->acquire_ctx);
11769 drm_atomic_state_clear(state);
11770 goto retry;
11771 }
11772
11773 if (ret)
11774 drm_atomic_state_free(state);
11775
11776 if (ret == 0 && event) {
11777 spin_lock_irq(&dev->event_lock);
11778 drm_send_vblank_event(dev, pipe, event);
11779 spin_unlock_irq(&dev->event_lock);
11780 }
11781 }
11782 return ret;
11783 }
11784
11785
11786 /**
11787 * intel_wm_need_update - Check whether watermarks need updating
11788 * @plane: drm plane
11789 * @state: new plane state
11790 *
11791 * Check current plane state versus the new one to determine whether
11792 * watermarks need to be recalculated.
11793 *
11794 * Returns true or false.
11795 */
11796 static bool intel_wm_need_update(struct drm_plane *plane,
11797 struct drm_plane_state *state)
11798 {
11799 struct intel_plane_state *new = to_intel_plane_state(state);
11800 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11801
11802 /* Update watermarks on tiling or size changes. */
11803 if (new->visible != cur->visible)
11804 return true;
11805
11806 if (!cur->base.fb || !new->base.fb)
11807 return false;
11808
11809 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11810 cur->base.rotation != new->base.rotation ||
11811 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11812 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11813 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11814 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11815 return true;
11816
11817 return false;
11818 }
11819
11820 static bool needs_scaling(struct intel_plane_state *state)
11821 {
11822 int src_w = drm_rect_width(&state->src) >> 16;
11823 int src_h = drm_rect_height(&state->src) >> 16;
11824 int dst_w = drm_rect_width(&state->dst);
11825 int dst_h = drm_rect_height(&state->dst);
11826
11827 return (src_w != dst_w || src_h != dst_h);
11828 }
11829
11830 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11831 struct drm_plane_state *plane_state)
11832 {
11833 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11834 struct drm_crtc *crtc = crtc_state->crtc;
11835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11836 struct drm_plane *plane = plane_state->plane;
11837 struct drm_device *dev = crtc->dev;
11838 struct drm_i915_private *dev_priv = dev->dev_private;
11839 struct intel_plane_state *old_plane_state =
11840 to_intel_plane_state(plane->state);
11841 int idx = intel_crtc->base.base.id, ret;
11842 int i = drm_plane_index(plane);
11843 bool mode_changed = needs_modeset(crtc_state);
11844 bool was_crtc_enabled = crtc->state->active;
11845 bool is_crtc_enabled = crtc_state->active;
11846 bool turn_off, turn_on, visible, was_visible;
11847 struct drm_framebuffer *fb = plane_state->fb;
11848
11849 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11850 plane->type != DRM_PLANE_TYPE_CURSOR) {
11851 ret = skl_update_scaler_plane(
11852 to_intel_crtc_state(crtc_state),
11853 to_intel_plane_state(plane_state));
11854 if (ret)
11855 return ret;
11856 }
11857
11858 was_visible = old_plane_state->visible;
11859 visible = to_intel_plane_state(plane_state)->visible;
11860
11861 if (!was_crtc_enabled && WARN_ON(was_visible))
11862 was_visible = false;
11863
11864 /*
11865 * Visibility is calculated as if the crtc was on, but
11866 * after scaler setup everything depends on it being off
11867 * when the crtc isn't active.
11868 */
11869 if (!is_crtc_enabled)
11870 to_intel_plane_state(plane_state)->visible = visible = false;
11871
11872 if (!was_visible && !visible)
11873 return 0;
11874
11875 turn_off = was_visible && (!visible || mode_changed);
11876 turn_on = visible && (!was_visible || mode_changed);
11877
11878 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11879 plane->base.id, fb ? fb->base.id : -1);
11880
11881 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11882 plane->base.id, was_visible, visible,
11883 turn_off, turn_on, mode_changed);
11884
11885 if (turn_on || turn_off) {
11886 pipe_config->wm_changed = true;
11887
11888 /* must disable cxsr around plane enable/disable */
11889 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11890 if (is_crtc_enabled)
11891 intel_crtc->atomic.wait_vblank = true;
11892 pipe_config->disable_cxsr = true;
11893 }
11894 } else if (intel_wm_need_update(plane, plane_state)) {
11895 pipe_config->wm_changed = true;
11896 }
11897
11898 if (visible || was_visible)
11899 intel_crtc->atomic.fb_bits |=
11900 to_intel_plane(plane)->frontbuffer_bit;
11901
11902 switch (plane->type) {
11903 case DRM_PLANE_TYPE_PRIMARY:
11904 intel_crtc->atomic.pre_disable_primary = turn_off;
11905 intel_crtc->atomic.post_enable_primary = turn_on;
11906
11907 if (turn_off) {
11908 /*
11909 * FIXME: Actually if we will still have any other
11910 * plane enabled on the pipe we could let IPS enabled
11911 * still, but for now lets consider that when we make
11912 * primary invisible by setting DSPCNTR to 0 on
11913 * update_primary_plane function IPS needs to be
11914 * disable.
11915 */
11916 intel_crtc->atomic.disable_ips = true;
11917
11918 intel_crtc->atomic.disable_fbc = true;
11919 }
11920
11921 /*
11922 * FBC does not work on some platforms for rotated
11923 * planes, so disable it when rotation is not 0 and
11924 * update it when rotation is set back to 0.
11925 *
11926 * FIXME: This is redundant with the fbc update done in
11927 * the primary plane enable function except that that
11928 * one is done too late. We eventually need to unify
11929 * this.
11930 */
11931
11932 if (visible &&
11933 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11934 dev_priv->fbc.crtc == intel_crtc &&
11935 plane_state->rotation != BIT(DRM_ROTATE_0))
11936 intel_crtc->atomic.disable_fbc = true;
11937
11938 /*
11939 * BDW signals flip done immediately if the plane
11940 * is disabled, even if the plane enable is already
11941 * armed to occur at the next vblank :(
11942 */
11943 if (turn_on && IS_BROADWELL(dev))
11944 intel_crtc->atomic.wait_vblank = true;
11945
11946 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11947 break;
11948 case DRM_PLANE_TYPE_CURSOR:
11949 break;
11950 case DRM_PLANE_TYPE_OVERLAY:
11951 /*
11952 * WaCxSRDisabledForSpriteScaling:ivb
11953 *
11954 * cstate->update_wm was already set above, so this flag will
11955 * take effect when we commit and program watermarks.
11956 */
11957 if (IS_IVYBRIDGE(dev) &&
11958 needs_scaling(to_intel_plane_state(plane_state)) &&
11959 !needs_scaling(old_plane_state)) {
11960 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11961 } else if (turn_off && !mode_changed) {
11962 intel_crtc->atomic.wait_vblank = true;
11963 intel_crtc->atomic.update_sprite_watermarks |=
11964 1 << i;
11965 }
11966
11967 break;
11968 }
11969 return 0;
11970 }
11971
11972 static bool encoders_cloneable(const struct intel_encoder *a,
11973 const struct intel_encoder *b)
11974 {
11975 /* masks could be asymmetric, so check both ways */
11976 return a == b || (a->cloneable & (1 << b->type) &&
11977 b->cloneable & (1 << a->type));
11978 }
11979
11980 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11981 struct intel_crtc *crtc,
11982 struct intel_encoder *encoder)
11983 {
11984 struct intel_encoder *source_encoder;
11985 struct drm_connector *connector;
11986 struct drm_connector_state *connector_state;
11987 int i;
11988
11989 for_each_connector_in_state(state, connector, connector_state, i) {
11990 if (connector_state->crtc != &crtc->base)
11991 continue;
11992
11993 source_encoder =
11994 to_intel_encoder(connector_state->best_encoder);
11995 if (!encoders_cloneable(encoder, source_encoder))
11996 return false;
11997 }
11998
11999 return true;
12000 }
12001
12002 static bool check_encoder_cloning(struct drm_atomic_state *state,
12003 struct intel_crtc *crtc)
12004 {
12005 struct intel_encoder *encoder;
12006 struct drm_connector *connector;
12007 struct drm_connector_state *connector_state;
12008 int i;
12009
12010 for_each_connector_in_state(state, connector, connector_state, i) {
12011 if (connector_state->crtc != &crtc->base)
12012 continue;
12013
12014 encoder = to_intel_encoder(connector_state->best_encoder);
12015 if (!check_single_encoder_cloning(state, crtc, encoder))
12016 return false;
12017 }
12018
12019 return true;
12020 }
12021
12022 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12023 struct drm_crtc_state *crtc_state)
12024 {
12025 struct drm_device *dev = crtc->dev;
12026 struct drm_i915_private *dev_priv = dev->dev_private;
12027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12028 struct intel_crtc_state *pipe_config =
12029 to_intel_crtc_state(crtc_state);
12030 struct drm_atomic_state *state = crtc_state->state;
12031 int ret;
12032 bool mode_changed = needs_modeset(crtc_state);
12033
12034 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12035 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12036 return -EINVAL;
12037 }
12038
12039 if (mode_changed && !crtc_state->active)
12040 pipe_config->wm_changed = true;
12041
12042 if (mode_changed && crtc_state->enable &&
12043 dev_priv->display.crtc_compute_clock &&
12044 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12045 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12046 pipe_config);
12047 if (ret)
12048 return ret;
12049 }
12050
12051 ret = 0;
12052 if (dev_priv->display.compute_pipe_wm) {
12053 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12054 if (ret)
12055 return ret;
12056 }
12057
12058 if (INTEL_INFO(dev)->gen >= 9) {
12059 if (mode_changed)
12060 ret = skl_update_scaler_crtc(pipe_config);
12061
12062 if (!ret)
12063 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12064 pipe_config);
12065 }
12066
12067 return ret;
12068 }
12069
12070 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12071 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12072 .load_lut = intel_crtc_load_lut,
12073 .atomic_begin = intel_begin_crtc_commit,
12074 .atomic_flush = intel_finish_crtc_commit,
12075 .atomic_check = intel_crtc_atomic_check,
12076 };
12077
12078 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12079 {
12080 struct intel_connector *connector;
12081
12082 for_each_intel_connector(dev, connector) {
12083 if (connector->base.encoder) {
12084 connector->base.state->best_encoder =
12085 connector->base.encoder;
12086 connector->base.state->crtc =
12087 connector->base.encoder->crtc;
12088 } else {
12089 connector->base.state->best_encoder = NULL;
12090 connector->base.state->crtc = NULL;
12091 }
12092 }
12093 }
12094
12095 static void
12096 connected_sink_compute_bpp(struct intel_connector *connector,
12097 struct intel_crtc_state *pipe_config)
12098 {
12099 int bpp = pipe_config->pipe_bpp;
12100
12101 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12102 connector->base.base.id,
12103 connector->base.name);
12104
12105 /* Don't use an invalid EDID bpc value */
12106 if (connector->base.display_info.bpc &&
12107 connector->base.display_info.bpc * 3 < bpp) {
12108 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12109 bpp, connector->base.display_info.bpc*3);
12110 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12111 }
12112
12113 /* Clamp bpp to default limit on screens without EDID 1.4 */
12114 if (connector->base.display_info.bpc == 0) {
12115 int type = connector->base.connector_type;
12116 int clamp_bpp = 24;
12117
12118 /* Fall back to 18 bpp when DP sink capability is unknown. */
12119 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12120 type == DRM_MODE_CONNECTOR_eDP)
12121 clamp_bpp = 18;
12122
12123 if (bpp > clamp_bpp) {
12124 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12125 bpp, clamp_bpp);
12126 pipe_config->pipe_bpp = clamp_bpp;
12127 }
12128 }
12129 }
12130
12131 static int
12132 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12133 struct intel_crtc_state *pipe_config)
12134 {
12135 struct drm_device *dev = crtc->base.dev;
12136 struct drm_atomic_state *state;
12137 struct drm_connector *connector;
12138 struct drm_connector_state *connector_state;
12139 int bpp, i;
12140
12141 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12142 bpp = 10*3;
12143 else if (INTEL_INFO(dev)->gen >= 5)
12144 bpp = 12*3;
12145 else
12146 bpp = 8*3;
12147
12148
12149 pipe_config->pipe_bpp = bpp;
12150
12151 state = pipe_config->base.state;
12152
12153 /* Clamp display bpp to EDID value */
12154 for_each_connector_in_state(state, connector, connector_state, i) {
12155 if (connector_state->crtc != &crtc->base)
12156 continue;
12157
12158 connected_sink_compute_bpp(to_intel_connector(connector),
12159 pipe_config);
12160 }
12161
12162 return bpp;
12163 }
12164
12165 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12166 {
12167 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12168 "type: 0x%x flags: 0x%x\n",
12169 mode->crtc_clock,
12170 mode->crtc_hdisplay, mode->crtc_hsync_start,
12171 mode->crtc_hsync_end, mode->crtc_htotal,
12172 mode->crtc_vdisplay, mode->crtc_vsync_start,
12173 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12174 }
12175
12176 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12177 struct intel_crtc_state *pipe_config,
12178 const char *context)
12179 {
12180 struct drm_device *dev = crtc->base.dev;
12181 struct drm_plane *plane;
12182 struct intel_plane *intel_plane;
12183 struct intel_plane_state *state;
12184 struct drm_framebuffer *fb;
12185
12186 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12187 context, pipe_config, pipe_name(crtc->pipe));
12188
12189 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12190 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12191 pipe_config->pipe_bpp, pipe_config->dither);
12192 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12193 pipe_config->has_pch_encoder,
12194 pipe_config->fdi_lanes,
12195 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12196 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12197 pipe_config->fdi_m_n.tu);
12198 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12199 pipe_config->has_dp_encoder,
12200 pipe_config->lane_count,
12201 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12202 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12203 pipe_config->dp_m_n.tu);
12204
12205 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12206 pipe_config->has_dp_encoder,
12207 pipe_config->lane_count,
12208 pipe_config->dp_m2_n2.gmch_m,
12209 pipe_config->dp_m2_n2.gmch_n,
12210 pipe_config->dp_m2_n2.link_m,
12211 pipe_config->dp_m2_n2.link_n,
12212 pipe_config->dp_m2_n2.tu);
12213
12214 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12215 pipe_config->has_audio,
12216 pipe_config->has_infoframe);
12217
12218 DRM_DEBUG_KMS("requested mode:\n");
12219 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12220 DRM_DEBUG_KMS("adjusted mode:\n");
12221 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12222 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12223 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12224 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12225 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12226 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12227 crtc->num_scalers,
12228 pipe_config->scaler_state.scaler_users,
12229 pipe_config->scaler_state.scaler_id);
12230 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12231 pipe_config->gmch_pfit.control,
12232 pipe_config->gmch_pfit.pgm_ratios,
12233 pipe_config->gmch_pfit.lvds_border_bits);
12234 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12235 pipe_config->pch_pfit.pos,
12236 pipe_config->pch_pfit.size,
12237 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12238 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12239 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12240
12241 if (IS_BROXTON(dev)) {
12242 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12243 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12244 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12245 pipe_config->ddi_pll_sel,
12246 pipe_config->dpll_hw_state.ebb0,
12247 pipe_config->dpll_hw_state.ebb4,
12248 pipe_config->dpll_hw_state.pll0,
12249 pipe_config->dpll_hw_state.pll1,
12250 pipe_config->dpll_hw_state.pll2,
12251 pipe_config->dpll_hw_state.pll3,
12252 pipe_config->dpll_hw_state.pll6,
12253 pipe_config->dpll_hw_state.pll8,
12254 pipe_config->dpll_hw_state.pll9,
12255 pipe_config->dpll_hw_state.pll10,
12256 pipe_config->dpll_hw_state.pcsdw12);
12257 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12258 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12259 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12260 pipe_config->ddi_pll_sel,
12261 pipe_config->dpll_hw_state.ctrl1,
12262 pipe_config->dpll_hw_state.cfgcr1,
12263 pipe_config->dpll_hw_state.cfgcr2);
12264 } else if (HAS_DDI(dev)) {
12265 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12266 pipe_config->ddi_pll_sel,
12267 pipe_config->dpll_hw_state.wrpll,
12268 pipe_config->dpll_hw_state.spll);
12269 } else {
12270 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12271 "fp0: 0x%x, fp1: 0x%x\n",
12272 pipe_config->dpll_hw_state.dpll,
12273 pipe_config->dpll_hw_state.dpll_md,
12274 pipe_config->dpll_hw_state.fp0,
12275 pipe_config->dpll_hw_state.fp1);
12276 }
12277
12278 DRM_DEBUG_KMS("planes on this crtc\n");
12279 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12280 intel_plane = to_intel_plane(plane);
12281 if (intel_plane->pipe != crtc->pipe)
12282 continue;
12283
12284 state = to_intel_plane_state(plane->state);
12285 fb = state->base.fb;
12286 if (!fb) {
12287 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12288 "disabled, scaler_id = %d\n",
12289 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12290 plane->base.id, intel_plane->pipe,
12291 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12292 drm_plane_index(plane), state->scaler_id);
12293 continue;
12294 }
12295
12296 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12297 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12298 plane->base.id, intel_plane->pipe,
12299 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12300 drm_plane_index(plane));
12301 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12302 fb->base.id, fb->width, fb->height, fb->pixel_format);
12303 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12304 state->scaler_id,
12305 state->src.x1 >> 16, state->src.y1 >> 16,
12306 drm_rect_width(&state->src) >> 16,
12307 drm_rect_height(&state->src) >> 16,
12308 state->dst.x1, state->dst.y1,
12309 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12310 }
12311 }
12312
12313 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12314 {
12315 struct drm_device *dev = state->dev;
12316 struct drm_connector *connector;
12317 unsigned int used_ports = 0;
12318
12319 /*
12320 * Walk the connector list instead of the encoder
12321 * list to detect the problem on ddi platforms
12322 * where there's just one encoder per digital port.
12323 */
12324 drm_for_each_connector(connector, dev) {
12325 struct drm_connector_state *connector_state;
12326 struct intel_encoder *encoder;
12327
12328 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12329 if (!connector_state)
12330 connector_state = connector->state;
12331
12332 if (!connector_state->best_encoder)
12333 continue;
12334
12335 encoder = to_intel_encoder(connector_state->best_encoder);
12336
12337 WARN_ON(!connector_state->crtc);
12338
12339 switch (encoder->type) {
12340 unsigned int port_mask;
12341 case INTEL_OUTPUT_UNKNOWN:
12342 if (WARN_ON(!HAS_DDI(dev)))
12343 break;
12344 case INTEL_OUTPUT_DISPLAYPORT:
12345 case INTEL_OUTPUT_HDMI:
12346 case INTEL_OUTPUT_EDP:
12347 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12348
12349 /* the same port mustn't appear more than once */
12350 if (used_ports & port_mask)
12351 return false;
12352
12353 used_ports |= port_mask;
12354 default:
12355 break;
12356 }
12357 }
12358
12359 return true;
12360 }
12361
12362 static void
12363 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12364 {
12365 struct drm_crtc_state tmp_state;
12366 struct intel_crtc_scaler_state scaler_state;
12367 struct intel_dpll_hw_state dpll_hw_state;
12368 enum intel_dpll_id shared_dpll;
12369 uint32_t ddi_pll_sel;
12370 bool force_thru;
12371
12372 /* FIXME: before the switch to atomic started, a new pipe_config was
12373 * kzalloc'd. Code that depends on any field being zero should be
12374 * fixed, so that the crtc_state can be safely duplicated. For now,
12375 * only fields that are know to not cause problems are preserved. */
12376
12377 tmp_state = crtc_state->base;
12378 scaler_state = crtc_state->scaler_state;
12379 shared_dpll = crtc_state->shared_dpll;
12380 dpll_hw_state = crtc_state->dpll_hw_state;
12381 ddi_pll_sel = crtc_state->ddi_pll_sel;
12382 force_thru = crtc_state->pch_pfit.force_thru;
12383
12384 memset(crtc_state, 0, sizeof *crtc_state);
12385
12386 crtc_state->base = tmp_state;
12387 crtc_state->scaler_state = scaler_state;
12388 crtc_state->shared_dpll = shared_dpll;
12389 crtc_state->dpll_hw_state = dpll_hw_state;
12390 crtc_state->ddi_pll_sel = ddi_pll_sel;
12391 crtc_state->pch_pfit.force_thru = force_thru;
12392 }
12393
12394 static int
12395 intel_modeset_pipe_config(struct drm_crtc *crtc,
12396 struct intel_crtc_state *pipe_config)
12397 {
12398 struct drm_atomic_state *state = pipe_config->base.state;
12399 struct intel_encoder *encoder;
12400 struct drm_connector *connector;
12401 struct drm_connector_state *connector_state;
12402 int base_bpp, ret = -EINVAL;
12403 int i;
12404 bool retry = true;
12405
12406 clear_intel_crtc_state(pipe_config);
12407
12408 pipe_config->cpu_transcoder =
12409 (enum transcoder) to_intel_crtc(crtc)->pipe;
12410
12411 /*
12412 * Sanitize sync polarity flags based on requested ones. If neither
12413 * positive or negative polarity is requested, treat this as meaning
12414 * negative polarity.
12415 */
12416 if (!(pipe_config->base.adjusted_mode.flags &
12417 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12418 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12419
12420 if (!(pipe_config->base.adjusted_mode.flags &
12421 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12422 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12423
12424 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12425 pipe_config);
12426 if (base_bpp < 0)
12427 goto fail;
12428
12429 /*
12430 * Determine the real pipe dimensions. Note that stereo modes can
12431 * increase the actual pipe size due to the frame doubling and
12432 * insertion of additional space for blanks between the frame. This
12433 * is stored in the crtc timings. We use the requested mode to do this
12434 * computation to clearly distinguish it from the adjusted mode, which
12435 * can be changed by the connectors in the below retry loop.
12436 */
12437 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12438 &pipe_config->pipe_src_w,
12439 &pipe_config->pipe_src_h);
12440
12441 encoder_retry:
12442 /* Ensure the port clock defaults are reset when retrying. */
12443 pipe_config->port_clock = 0;
12444 pipe_config->pixel_multiplier = 1;
12445
12446 /* Fill in default crtc timings, allow encoders to overwrite them. */
12447 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12448 CRTC_STEREO_DOUBLE);
12449
12450 /* Pass our mode to the connectors and the CRTC to give them a chance to
12451 * adjust it according to limitations or connector properties, and also
12452 * a chance to reject the mode entirely.
12453 */
12454 for_each_connector_in_state(state, connector, connector_state, i) {
12455 if (connector_state->crtc != crtc)
12456 continue;
12457
12458 encoder = to_intel_encoder(connector_state->best_encoder);
12459
12460 if (!(encoder->compute_config(encoder, pipe_config))) {
12461 DRM_DEBUG_KMS("Encoder config failure\n");
12462 goto fail;
12463 }
12464 }
12465
12466 /* Set default port clock if not overwritten by the encoder. Needs to be
12467 * done afterwards in case the encoder adjusts the mode. */
12468 if (!pipe_config->port_clock)
12469 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12470 * pipe_config->pixel_multiplier;
12471
12472 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12473 if (ret < 0) {
12474 DRM_DEBUG_KMS("CRTC fixup failed\n");
12475 goto fail;
12476 }
12477
12478 if (ret == RETRY) {
12479 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12480 ret = -EINVAL;
12481 goto fail;
12482 }
12483
12484 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12485 retry = false;
12486 goto encoder_retry;
12487 }
12488
12489 /* Dithering seems to not pass-through bits correctly when it should, so
12490 * only enable it on 6bpc panels. */
12491 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12492 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12493 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12494
12495 fail:
12496 return ret;
12497 }
12498
12499 static void
12500 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12501 {
12502 struct drm_crtc *crtc;
12503 struct drm_crtc_state *crtc_state;
12504 int i;
12505
12506 /* Double check state. */
12507 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12508 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12509
12510 /* Update hwmode for vblank functions */
12511 if (crtc->state->active)
12512 crtc->hwmode = crtc->state->adjusted_mode;
12513 else
12514 crtc->hwmode.crtc_clock = 0;
12515
12516 /*
12517 * Update legacy state to satisfy fbc code. This can
12518 * be removed when fbc uses the atomic state.
12519 */
12520 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12521 struct drm_plane_state *plane_state = crtc->primary->state;
12522
12523 crtc->primary->fb = plane_state->fb;
12524 crtc->x = plane_state->src_x >> 16;
12525 crtc->y = plane_state->src_y >> 16;
12526 }
12527 }
12528 }
12529
12530 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12531 {
12532 int diff;
12533
12534 if (clock1 == clock2)
12535 return true;
12536
12537 if (!clock1 || !clock2)
12538 return false;
12539
12540 diff = abs(clock1 - clock2);
12541
12542 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12543 return true;
12544
12545 return false;
12546 }
12547
12548 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12549 list_for_each_entry((intel_crtc), \
12550 &(dev)->mode_config.crtc_list, \
12551 base.head) \
12552 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12553
12554 static bool
12555 intel_compare_m_n(unsigned int m, unsigned int n,
12556 unsigned int m2, unsigned int n2,
12557 bool exact)
12558 {
12559 if (m == m2 && n == n2)
12560 return true;
12561
12562 if (exact || !m || !n || !m2 || !n2)
12563 return false;
12564
12565 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12566
12567 if (n > n2) {
12568 while (n > n2) {
12569 m2 <<= 1;
12570 n2 <<= 1;
12571 }
12572 } else if (n < n2) {
12573 while (n < n2) {
12574 m <<= 1;
12575 n <<= 1;
12576 }
12577 }
12578
12579 if (n != n2)
12580 return false;
12581
12582 return intel_fuzzy_clock_check(m, m2);
12583 }
12584
12585 static bool
12586 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12587 struct intel_link_m_n *m2_n2,
12588 bool adjust)
12589 {
12590 if (m_n->tu == m2_n2->tu &&
12591 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12592 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12593 intel_compare_m_n(m_n->link_m, m_n->link_n,
12594 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12595 if (adjust)
12596 *m2_n2 = *m_n;
12597
12598 return true;
12599 }
12600
12601 return false;
12602 }
12603
12604 static bool
12605 intel_pipe_config_compare(struct drm_device *dev,
12606 struct intel_crtc_state *current_config,
12607 struct intel_crtc_state *pipe_config,
12608 bool adjust)
12609 {
12610 bool ret = true;
12611
12612 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12613 do { \
12614 if (!adjust) \
12615 DRM_ERROR(fmt, ##__VA_ARGS__); \
12616 else \
12617 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12618 } while (0)
12619
12620 #define PIPE_CONF_CHECK_X(name) \
12621 if (current_config->name != pipe_config->name) { \
12622 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12623 "(expected 0x%08x, found 0x%08x)\n", \
12624 current_config->name, \
12625 pipe_config->name); \
12626 ret = false; \
12627 }
12628
12629 #define PIPE_CONF_CHECK_I(name) \
12630 if (current_config->name != pipe_config->name) { \
12631 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12632 "(expected %i, found %i)\n", \
12633 current_config->name, \
12634 pipe_config->name); \
12635 ret = false; \
12636 }
12637
12638 #define PIPE_CONF_CHECK_M_N(name) \
12639 if (!intel_compare_link_m_n(&current_config->name, \
12640 &pipe_config->name,\
12641 adjust)) { \
12642 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12643 "(expected tu %i gmch %i/%i link %i/%i, " \
12644 "found tu %i, gmch %i/%i link %i/%i)\n", \
12645 current_config->name.tu, \
12646 current_config->name.gmch_m, \
12647 current_config->name.gmch_n, \
12648 current_config->name.link_m, \
12649 current_config->name.link_n, \
12650 pipe_config->name.tu, \
12651 pipe_config->name.gmch_m, \
12652 pipe_config->name.gmch_n, \
12653 pipe_config->name.link_m, \
12654 pipe_config->name.link_n); \
12655 ret = false; \
12656 }
12657
12658 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12659 if (!intel_compare_link_m_n(&current_config->name, \
12660 &pipe_config->name, adjust) && \
12661 !intel_compare_link_m_n(&current_config->alt_name, \
12662 &pipe_config->name, adjust)) { \
12663 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12664 "(expected tu %i gmch %i/%i link %i/%i, " \
12665 "or tu %i gmch %i/%i link %i/%i, " \
12666 "found tu %i, gmch %i/%i link %i/%i)\n", \
12667 current_config->name.tu, \
12668 current_config->name.gmch_m, \
12669 current_config->name.gmch_n, \
12670 current_config->name.link_m, \
12671 current_config->name.link_n, \
12672 current_config->alt_name.tu, \
12673 current_config->alt_name.gmch_m, \
12674 current_config->alt_name.gmch_n, \
12675 current_config->alt_name.link_m, \
12676 current_config->alt_name.link_n, \
12677 pipe_config->name.tu, \
12678 pipe_config->name.gmch_m, \
12679 pipe_config->name.gmch_n, \
12680 pipe_config->name.link_m, \
12681 pipe_config->name.link_n); \
12682 ret = false; \
12683 }
12684
12685 /* This is required for BDW+ where there is only one set of registers for
12686 * switching between high and low RR.
12687 * This macro can be used whenever a comparison has to be made between one
12688 * hw state and multiple sw state variables.
12689 */
12690 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12691 if ((current_config->name != pipe_config->name) && \
12692 (current_config->alt_name != pipe_config->name)) { \
12693 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12694 "(expected %i or %i, found %i)\n", \
12695 current_config->name, \
12696 current_config->alt_name, \
12697 pipe_config->name); \
12698 ret = false; \
12699 }
12700
12701 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12702 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12703 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12704 "(expected %i, found %i)\n", \
12705 current_config->name & (mask), \
12706 pipe_config->name & (mask)); \
12707 ret = false; \
12708 }
12709
12710 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12711 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12712 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12713 "(expected %i, found %i)\n", \
12714 current_config->name, \
12715 pipe_config->name); \
12716 ret = false; \
12717 }
12718
12719 #define PIPE_CONF_QUIRK(quirk) \
12720 ((current_config->quirks | pipe_config->quirks) & (quirk))
12721
12722 PIPE_CONF_CHECK_I(cpu_transcoder);
12723
12724 PIPE_CONF_CHECK_I(has_pch_encoder);
12725 PIPE_CONF_CHECK_I(fdi_lanes);
12726 PIPE_CONF_CHECK_M_N(fdi_m_n);
12727
12728 PIPE_CONF_CHECK_I(has_dp_encoder);
12729 PIPE_CONF_CHECK_I(lane_count);
12730
12731 if (INTEL_INFO(dev)->gen < 8) {
12732 PIPE_CONF_CHECK_M_N(dp_m_n);
12733
12734 if (current_config->has_drrs)
12735 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12736 } else
12737 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12738
12739 PIPE_CONF_CHECK_I(has_dsi_encoder);
12740
12741 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12742 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12745 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12746 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12747
12748 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12749 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12750 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12751 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12752 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12753 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12754
12755 PIPE_CONF_CHECK_I(pixel_multiplier);
12756 PIPE_CONF_CHECK_I(has_hdmi_sink);
12757 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12758 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12759 PIPE_CONF_CHECK_I(limited_color_range);
12760 PIPE_CONF_CHECK_I(has_infoframe);
12761
12762 PIPE_CONF_CHECK_I(has_audio);
12763
12764 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12765 DRM_MODE_FLAG_INTERLACE);
12766
12767 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12768 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12769 DRM_MODE_FLAG_PHSYNC);
12770 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12771 DRM_MODE_FLAG_NHSYNC);
12772 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12773 DRM_MODE_FLAG_PVSYNC);
12774 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12775 DRM_MODE_FLAG_NVSYNC);
12776 }
12777
12778 PIPE_CONF_CHECK_X(gmch_pfit.control);
12779 /* pfit ratios are autocomputed by the hw on gen4+ */
12780 if (INTEL_INFO(dev)->gen < 4)
12781 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12782 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12783
12784 if (!adjust) {
12785 PIPE_CONF_CHECK_I(pipe_src_w);
12786 PIPE_CONF_CHECK_I(pipe_src_h);
12787
12788 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12789 if (current_config->pch_pfit.enabled) {
12790 PIPE_CONF_CHECK_X(pch_pfit.pos);
12791 PIPE_CONF_CHECK_X(pch_pfit.size);
12792 }
12793
12794 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12795 }
12796
12797 /* BDW+ don't expose a synchronous way to read the state */
12798 if (IS_HASWELL(dev))
12799 PIPE_CONF_CHECK_I(ips_enabled);
12800
12801 PIPE_CONF_CHECK_I(double_wide);
12802
12803 PIPE_CONF_CHECK_X(ddi_pll_sel);
12804
12805 PIPE_CONF_CHECK_I(shared_dpll);
12806 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12807 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12808 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12809 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12810 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12811 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12812 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12813 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12814 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12815
12816 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12817 PIPE_CONF_CHECK_I(pipe_bpp);
12818
12819 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12820 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12821
12822 #undef PIPE_CONF_CHECK_X
12823 #undef PIPE_CONF_CHECK_I
12824 #undef PIPE_CONF_CHECK_I_ALT
12825 #undef PIPE_CONF_CHECK_FLAGS
12826 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12827 #undef PIPE_CONF_QUIRK
12828 #undef INTEL_ERR_OR_DBG_KMS
12829
12830 return ret;
12831 }
12832
12833 static void check_wm_state(struct drm_device *dev)
12834 {
12835 struct drm_i915_private *dev_priv = dev->dev_private;
12836 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12837 struct intel_crtc *intel_crtc;
12838 int plane;
12839
12840 if (INTEL_INFO(dev)->gen < 9)
12841 return;
12842
12843 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12844 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12845
12846 for_each_intel_crtc(dev, intel_crtc) {
12847 struct skl_ddb_entry *hw_entry, *sw_entry;
12848 const enum pipe pipe = intel_crtc->pipe;
12849
12850 if (!intel_crtc->active)
12851 continue;
12852
12853 /* planes */
12854 for_each_plane(dev_priv, pipe, plane) {
12855 hw_entry = &hw_ddb.plane[pipe][plane];
12856 sw_entry = &sw_ddb->plane[pipe][plane];
12857
12858 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12859 continue;
12860
12861 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12862 "(expected (%u,%u), found (%u,%u))\n",
12863 pipe_name(pipe), plane + 1,
12864 sw_entry->start, sw_entry->end,
12865 hw_entry->start, hw_entry->end);
12866 }
12867
12868 /* cursor */
12869 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12870 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12871
12872 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12873 continue;
12874
12875 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12876 "(expected (%u,%u), found (%u,%u))\n",
12877 pipe_name(pipe),
12878 sw_entry->start, sw_entry->end,
12879 hw_entry->start, hw_entry->end);
12880 }
12881 }
12882
12883 static void
12884 check_connector_state(struct drm_device *dev,
12885 struct drm_atomic_state *old_state)
12886 {
12887 struct drm_connector_state *old_conn_state;
12888 struct drm_connector *connector;
12889 int i;
12890
12891 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12892 struct drm_encoder *encoder = connector->encoder;
12893 struct drm_connector_state *state = connector->state;
12894
12895 /* This also checks the encoder/connector hw state with the
12896 * ->get_hw_state callbacks. */
12897 intel_connector_check_state(to_intel_connector(connector));
12898
12899 I915_STATE_WARN(state->best_encoder != encoder,
12900 "connector's atomic encoder doesn't match legacy encoder\n");
12901 }
12902 }
12903
12904 static void
12905 check_encoder_state(struct drm_device *dev)
12906 {
12907 struct intel_encoder *encoder;
12908 struct intel_connector *connector;
12909
12910 for_each_intel_encoder(dev, encoder) {
12911 bool enabled = false;
12912 enum pipe pipe;
12913
12914 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12915 encoder->base.base.id,
12916 encoder->base.name);
12917
12918 for_each_intel_connector(dev, connector) {
12919 if (connector->base.state->best_encoder != &encoder->base)
12920 continue;
12921 enabled = true;
12922
12923 I915_STATE_WARN(connector->base.state->crtc !=
12924 encoder->base.crtc,
12925 "connector's crtc doesn't match encoder crtc\n");
12926 }
12927
12928 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12929 "encoder's enabled state mismatch "
12930 "(expected %i, found %i)\n",
12931 !!encoder->base.crtc, enabled);
12932
12933 if (!encoder->base.crtc) {
12934 bool active;
12935
12936 active = encoder->get_hw_state(encoder, &pipe);
12937 I915_STATE_WARN(active,
12938 "encoder detached but still enabled on pipe %c.\n",
12939 pipe_name(pipe));
12940 }
12941 }
12942 }
12943
12944 static void
12945 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12946 {
12947 struct drm_i915_private *dev_priv = dev->dev_private;
12948 struct intel_encoder *encoder;
12949 struct drm_crtc_state *old_crtc_state;
12950 struct drm_crtc *crtc;
12951 int i;
12952
12953 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12955 struct intel_crtc_state *pipe_config, *sw_config;
12956 bool active;
12957
12958 if (!needs_modeset(crtc->state) &&
12959 !to_intel_crtc_state(crtc->state)->update_pipe)
12960 continue;
12961
12962 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12963 pipe_config = to_intel_crtc_state(old_crtc_state);
12964 memset(pipe_config, 0, sizeof(*pipe_config));
12965 pipe_config->base.crtc = crtc;
12966 pipe_config->base.state = old_state;
12967
12968 DRM_DEBUG_KMS("[CRTC:%d]\n",
12969 crtc->base.id);
12970
12971 active = dev_priv->display.get_pipe_config(intel_crtc,
12972 pipe_config);
12973
12974 /* hw state is inconsistent with the pipe quirk */
12975 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12976 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12977 active = crtc->state->active;
12978
12979 I915_STATE_WARN(crtc->state->active != active,
12980 "crtc active state doesn't match with hw state "
12981 "(expected %i, found %i)\n", crtc->state->active, active);
12982
12983 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12984 "transitional active state does not match atomic hw state "
12985 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12986
12987 for_each_encoder_on_crtc(dev, crtc, encoder) {
12988 enum pipe pipe;
12989
12990 active = encoder->get_hw_state(encoder, &pipe);
12991 I915_STATE_WARN(active != crtc->state->active,
12992 "[ENCODER:%i] active %i with crtc active %i\n",
12993 encoder->base.base.id, active, crtc->state->active);
12994
12995 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12996 "Encoder connected to wrong pipe %c\n",
12997 pipe_name(pipe));
12998
12999 if (active)
13000 encoder->get_config(encoder, pipe_config);
13001 }
13002
13003 if (!crtc->state->active)
13004 continue;
13005
13006 sw_config = to_intel_crtc_state(crtc->state);
13007 if (!intel_pipe_config_compare(dev, sw_config,
13008 pipe_config, false)) {
13009 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13010 intel_dump_pipe_config(intel_crtc, pipe_config,
13011 "[hw state]");
13012 intel_dump_pipe_config(intel_crtc, sw_config,
13013 "[sw state]");
13014 }
13015 }
13016 }
13017
13018 static void
13019 check_shared_dpll_state(struct drm_device *dev)
13020 {
13021 struct drm_i915_private *dev_priv = dev->dev_private;
13022 struct intel_crtc *crtc;
13023 struct intel_dpll_hw_state dpll_hw_state;
13024 int i;
13025
13026 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13027 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13028 int enabled_crtcs = 0, active_crtcs = 0;
13029 bool active;
13030
13031 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13032
13033 DRM_DEBUG_KMS("%s\n", pll->name);
13034
13035 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13036
13037 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13038 "more active pll users than references: %i vs %i\n",
13039 pll->active, hweight32(pll->config.crtc_mask));
13040 I915_STATE_WARN(pll->active && !pll->on,
13041 "pll in active use but not on in sw tracking\n");
13042 I915_STATE_WARN(pll->on && !pll->active,
13043 "pll in on but not on in use in sw tracking\n");
13044 I915_STATE_WARN(pll->on != active,
13045 "pll on state mismatch (expected %i, found %i)\n",
13046 pll->on, active);
13047
13048 for_each_intel_crtc(dev, crtc) {
13049 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13050 enabled_crtcs++;
13051 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13052 active_crtcs++;
13053 }
13054 I915_STATE_WARN(pll->active != active_crtcs,
13055 "pll active crtcs mismatch (expected %i, found %i)\n",
13056 pll->active, active_crtcs);
13057 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13058 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13059 hweight32(pll->config.crtc_mask), enabled_crtcs);
13060
13061 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13062 sizeof(dpll_hw_state)),
13063 "pll hw state mismatch\n");
13064 }
13065 }
13066
13067 static void
13068 intel_modeset_check_state(struct drm_device *dev,
13069 struct drm_atomic_state *old_state)
13070 {
13071 check_wm_state(dev);
13072 check_connector_state(dev, old_state);
13073 check_encoder_state(dev);
13074 check_crtc_state(dev, old_state);
13075 check_shared_dpll_state(dev);
13076 }
13077
13078 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13079 int dotclock)
13080 {
13081 /*
13082 * FDI already provided one idea for the dotclock.
13083 * Yell if the encoder disagrees.
13084 */
13085 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13086 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13087 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13088 }
13089
13090 static void update_scanline_offset(struct intel_crtc *crtc)
13091 {
13092 struct drm_device *dev = crtc->base.dev;
13093
13094 /*
13095 * The scanline counter increments at the leading edge of hsync.
13096 *
13097 * On most platforms it starts counting from vtotal-1 on the
13098 * first active line. That means the scanline counter value is
13099 * always one less than what we would expect. Ie. just after
13100 * start of vblank, which also occurs at start of hsync (on the
13101 * last active line), the scanline counter will read vblank_start-1.
13102 *
13103 * On gen2 the scanline counter starts counting from 1 instead
13104 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13105 * to keep the value positive), instead of adding one.
13106 *
13107 * On HSW+ the behaviour of the scanline counter depends on the output
13108 * type. For DP ports it behaves like most other platforms, but on HDMI
13109 * there's an extra 1 line difference. So we need to add two instead of
13110 * one to the value.
13111 */
13112 if (IS_GEN2(dev)) {
13113 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13114 int vtotal;
13115
13116 vtotal = adjusted_mode->crtc_vtotal;
13117 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13118 vtotal /= 2;
13119
13120 crtc->scanline_offset = vtotal - 1;
13121 } else if (HAS_DDI(dev) &&
13122 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13123 crtc->scanline_offset = 2;
13124 } else
13125 crtc->scanline_offset = 1;
13126 }
13127
13128 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13129 {
13130 struct drm_device *dev = state->dev;
13131 struct drm_i915_private *dev_priv = to_i915(dev);
13132 struct intel_shared_dpll_config *shared_dpll = NULL;
13133 struct intel_crtc *intel_crtc;
13134 struct intel_crtc_state *intel_crtc_state;
13135 struct drm_crtc *crtc;
13136 struct drm_crtc_state *crtc_state;
13137 int i;
13138
13139 if (!dev_priv->display.crtc_compute_clock)
13140 return;
13141
13142 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13143 int dpll;
13144
13145 intel_crtc = to_intel_crtc(crtc);
13146 intel_crtc_state = to_intel_crtc_state(crtc_state);
13147 dpll = intel_crtc_state->shared_dpll;
13148
13149 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13150 continue;
13151
13152 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13153
13154 if (!shared_dpll)
13155 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13156
13157 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13158 }
13159 }
13160
13161 /*
13162 * This implements the workaround described in the "notes" section of the mode
13163 * set sequence documentation. When going from no pipes or single pipe to
13164 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13165 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13166 */
13167 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13168 {
13169 struct drm_crtc_state *crtc_state;
13170 struct intel_crtc *intel_crtc;
13171 struct drm_crtc *crtc;
13172 struct intel_crtc_state *first_crtc_state = NULL;
13173 struct intel_crtc_state *other_crtc_state = NULL;
13174 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13175 int i;
13176
13177 /* look at all crtc's that are going to be enabled in during modeset */
13178 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13179 intel_crtc = to_intel_crtc(crtc);
13180
13181 if (!crtc_state->active || !needs_modeset(crtc_state))
13182 continue;
13183
13184 if (first_crtc_state) {
13185 other_crtc_state = to_intel_crtc_state(crtc_state);
13186 break;
13187 } else {
13188 first_crtc_state = to_intel_crtc_state(crtc_state);
13189 first_pipe = intel_crtc->pipe;
13190 }
13191 }
13192
13193 /* No workaround needed? */
13194 if (!first_crtc_state)
13195 return 0;
13196
13197 /* w/a possibly needed, check how many crtc's are already enabled. */
13198 for_each_intel_crtc(state->dev, intel_crtc) {
13199 struct intel_crtc_state *pipe_config;
13200
13201 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13202 if (IS_ERR(pipe_config))
13203 return PTR_ERR(pipe_config);
13204
13205 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13206
13207 if (!pipe_config->base.active ||
13208 needs_modeset(&pipe_config->base))
13209 continue;
13210
13211 /* 2 or more enabled crtcs means no need for w/a */
13212 if (enabled_pipe != INVALID_PIPE)
13213 return 0;
13214
13215 enabled_pipe = intel_crtc->pipe;
13216 }
13217
13218 if (enabled_pipe != INVALID_PIPE)
13219 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13220 else if (other_crtc_state)
13221 other_crtc_state->hsw_workaround_pipe = first_pipe;
13222
13223 return 0;
13224 }
13225
13226 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13227 {
13228 struct drm_crtc *crtc;
13229 struct drm_crtc_state *crtc_state;
13230 int ret = 0;
13231
13232 /* add all active pipes to the state */
13233 for_each_crtc(state->dev, crtc) {
13234 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13235 if (IS_ERR(crtc_state))
13236 return PTR_ERR(crtc_state);
13237
13238 if (!crtc_state->active || needs_modeset(crtc_state))
13239 continue;
13240
13241 crtc_state->mode_changed = true;
13242
13243 ret = drm_atomic_add_affected_connectors(state, crtc);
13244 if (ret)
13245 break;
13246
13247 ret = drm_atomic_add_affected_planes(state, crtc);
13248 if (ret)
13249 break;
13250 }
13251
13252 return ret;
13253 }
13254
13255 static int intel_modeset_checks(struct drm_atomic_state *state)
13256 {
13257 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13258 struct drm_i915_private *dev_priv = state->dev->dev_private;
13259 struct drm_crtc *crtc;
13260 struct drm_crtc_state *crtc_state;
13261 int ret = 0, i;
13262
13263 if (!check_digital_port_conflicts(state)) {
13264 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13265 return -EINVAL;
13266 }
13267
13268 intel_state->modeset = true;
13269 intel_state->active_crtcs = dev_priv->active_crtcs;
13270
13271 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13272 if (crtc_state->active)
13273 intel_state->active_crtcs |= 1 << i;
13274 else
13275 intel_state->active_crtcs &= ~(1 << i);
13276 }
13277
13278 /*
13279 * See if the config requires any additional preparation, e.g.
13280 * to adjust global state with pipes off. We need to do this
13281 * here so we can get the modeset_pipe updated config for the new
13282 * mode set on this crtc. For other crtcs we need to use the
13283 * adjusted_mode bits in the crtc directly.
13284 */
13285 if (dev_priv->display.modeset_calc_cdclk) {
13286 ret = dev_priv->display.modeset_calc_cdclk(state);
13287
13288 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13289 ret = intel_modeset_all_pipes(state);
13290
13291 if (ret < 0)
13292 return ret;
13293 } else
13294 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13295
13296 intel_modeset_clear_plls(state);
13297
13298 if (IS_HASWELL(dev_priv))
13299 return haswell_mode_set_planes_workaround(state);
13300
13301 return 0;
13302 }
13303
13304 /*
13305 * Handle calculation of various watermark data at the end of the atomic check
13306 * phase. The code here should be run after the per-crtc and per-plane 'check'
13307 * handlers to ensure that all derived state has been updated.
13308 */
13309 static void calc_watermark_data(struct drm_atomic_state *state)
13310 {
13311 struct drm_device *dev = state->dev;
13312 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13313 struct drm_crtc *crtc;
13314 struct drm_crtc_state *cstate;
13315 struct drm_plane *plane;
13316 struct drm_plane_state *pstate;
13317
13318 /*
13319 * Calculate watermark configuration details now that derived
13320 * plane/crtc state is all properly updated.
13321 */
13322 drm_for_each_crtc(crtc, dev) {
13323 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13324 crtc->state;
13325
13326 if (cstate->active)
13327 intel_state->wm_config.num_pipes_active++;
13328 }
13329 drm_for_each_legacy_plane(plane, dev) {
13330 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13331 plane->state;
13332
13333 if (!to_intel_plane_state(pstate)->visible)
13334 continue;
13335
13336 intel_state->wm_config.sprites_enabled = true;
13337 if (pstate->crtc_w != pstate->src_w >> 16 ||
13338 pstate->crtc_h != pstate->src_h >> 16)
13339 intel_state->wm_config.sprites_scaled = true;
13340 }
13341 }
13342
13343 /**
13344 * intel_atomic_check - validate state object
13345 * @dev: drm device
13346 * @state: state to validate
13347 */
13348 static int intel_atomic_check(struct drm_device *dev,
13349 struct drm_atomic_state *state)
13350 {
13351 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13352 struct drm_crtc *crtc;
13353 struct drm_crtc_state *crtc_state;
13354 int ret, i;
13355 bool any_ms = false;
13356
13357 ret = drm_atomic_helper_check_modeset(dev, state);
13358 if (ret)
13359 return ret;
13360
13361 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13362 struct intel_crtc_state *pipe_config =
13363 to_intel_crtc_state(crtc_state);
13364
13365 memset(&to_intel_crtc(crtc)->atomic, 0,
13366 sizeof(struct intel_crtc_atomic_commit));
13367
13368 /* Catch I915_MODE_FLAG_INHERITED */
13369 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13370 crtc_state->mode_changed = true;
13371
13372 if (!crtc_state->enable) {
13373 if (needs_modeset(crtc_state))
13374 any_ms = true;
13375 continue;
13376 }
13377
13378 if (!needs_modeset(crtc_state))
13379 continue;
13380
13381 /* FIXME: For only active_changed we shouldn't need to do any
13382 * state recomputation at all. */
13383
13384 ret = drm_atomic_add_affected_connectors(state, crtc);
13385 if (ret)
13386 return ret;
13387
13388 ret = intel_modeset_pipe_config(crtc, pipe_config);
13389 if (ret)
13390 return ret;
13391
13392 if (i915.fastboot &&
13393 intel_pipe_config_compare(state->dev,
13394 to_intel_crtc_state(crtc->state),
13395 pipe_config, true)) {
13396 crtc_state->mode_changed = false;
13397 to_intel_crtc_state(crtc_state)->update_pipe = true;
13398 }
13399
13400 if (needs_modeset(crtc_state)) {
13401 any_ms = true;
13402
13403 ret = drm_atomic_add_affected_planes(state, crtc);
13404 if (ret)
13405 return ret;
13406 }
13407
13408 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13409 needs_modeset(crtc_state) ?
13410 "[modeset]" : "[fastset]");
13411 }
13412
13413 if (any_ms) {
13414 ret = intel_modeset_checks(state);
13415
13416 if (ret)
13417 return ret;
13418 } else
13419 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13420
13421 ret = drm_atomic_helper_check_planes(state->dev, state);
13422 if (ret)
13423 return ret;
13424
13425 calc_watermark_data(state);
13426
13427 return 0;
13428 }
13429
13430 static int intel_atomic_prepare_commit(struct drm_device *dev,
13431 struct drm_atomic_state *state,
13432 bool async)
13433 {
13434 struct drm_i915_private *dev_priv = dev->dev_private;
13435 struct drm_plane_state *plane_state;
13436 struct drm_crtc_state *crtc_state;
13437 struct drm_plane *plane;
13438 struct drm_crtc *crtc;
13439 int i, ret;
13440
13441 if (async) {
13442 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13443 return -EINVAL;
13444 }
13445
13446 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13447 ret = intel_crtc_wait_for_pending_flips(crtc);
13448 if (ret)
13449 return ret;
13450
13451 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13452 flush_workqueue(dev_priv->wq);
13453 }
13454
13455 ret = mutex_lock_interruptible(&dev->struct_mutex);
13456 if (ret)
13457 return ret;
13458
13459 ret = drm_atomic_helper_prepare_planes(dev, state);
13460 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13461 u32 reset_counter;
13462
13463 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13464 mutex_unlock(&dev->struct_mutex);
13465
13466 for_each_plane_in_state(state, plane, plane_state, i) {
13467 struct intel_plane_state *intel_plane_state =
13468 to_intel_plane_state(plane_state);
13469
13470 if (!intel_plane_state->wait_req)
13471 continue;
13472
13473 ret = __i915_wait_request(intel_plane_state->wait_req,
13474 reset_counter, true,
13475 NULL, NULL);
13476
13477 /* Swallow -EIO errors to allow updates during hw lockup. */
13478 if (ret == -EIO)
13479 ret = 0;
13480
13481 if (ret)
13482 break;
13483 }
13484
13485 if (!ret)
13486 return 0;
13487
13488 mutex_lock(&dev->struct_mutex);
13489 drm_atomic_helper_cleanup_planes(dev, state);
13490 }
13491
13492 mutex_unlock(&dev->struct_mutex);
13493 return ret;
13494 }
13495
13496 /**
13497 * intel_atomic_commit - commit validated state object
13498 * @dev: DRM device
13499 * @state: the top-level driver state object
13500 * @async: asynchronous commit
13501 *
13502 * This function commits a top-level state object that has been validated
13503 * with drm_atomic_helper_check().
13504 *
13505 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13506 * we can only handle plane-related operations and do not yet support
13507 * asynchronous commit.
13508 *
13509 * RETURNS
13510 * Zero for success or -errno.
13511 */
13512 static int intel_atomic_commit(struct drm_device *dev,
13513 struct drm_atomic_state *state,
13514 bool async)
13515 {
13516 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13517 struct drm_i915_private *dev_priv = dev->dev_private;
13518 struct drm_crtc_state *crtc_state;
13519 struct drm_crtc *crtc;
13520 int ret = 0, i;
13521 bool hw_check = intel_state->modeset;
13522
13523 ret = intel_atomic_prepare_commit(dev, state, async);
13524 if (ret) {
13525 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13526 return ret;
13527 }
13528
13529 drm_atomic_helper_swap_state(dev, state);
13530 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13531
13532 if (intel_state->modeset) {
13533 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13534 sizeof(intel_state->min_pixclk));
13535 dev_priv->active_crtcs = intel_state->active_crtcs;
13536 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13537 }
13538
13539 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13541
13542 if (!needs_modeset(crtc->state))
13543 continue;
13544
13545 intel_pre_plane_update(intel_crtc);
13546
13547 if (crtc_state->active) {
13548 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13549 dev_priv->display.crtc_disable(crtc);
13550 intel_crtc->active = false;
13551 intel_disable_shared_dpll(intel_crtc);
13552
13553 /*
13554 * Underruns don't always raise
13555 * interrupts, so check manually.
13556 */
13557 intel_check_cpu_fifo_underruns(dev_priv);
13558 intel_check_pch_fifo_underruns(dev_priv);
13559
13560 if (!crtc->state->active)
13561 intel_update_watermarks(crtc);
13562 }
13563 }
13564
13565 /* Only after disabling all output pipelines that will be changed can we
13566 * update the the output configuration. */
13567 intel_modeset_update_crtc_state(state);
13568
13569 if (intel_state->modeset) {
13570 intel_shared_dpll_commit(state);
13571
13572 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13573 modeset_update_crtc_power_domains(state);
13574 }
13575
13576 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13577 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13579 bool modeset = needs_modeset(crtc->state);
13580 bool update_pipe = !modeset &&
13581 to_intel_crtc_state(crtc->state)->update_pipe;
13582 unsigned long put_domains = 0;
13583
13584 if (modeset)
13585 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13586
13587 if (modeset && crtc->state->active) {
13588 update_scanline_offset(to_intel_crtc(crtc));
13589 dev_priv->display.crtc_enable(crtc);
13590 }
13591
13592 if (update_pipe) {
13593 put_domains = modeset_get_crtc_power_domains(crtc);
13594
13595 /* make sure intel_modeset_check_state runs */
13596 hw_check = true;
13597 }
13598
13599 if (!modeset)
13600 intel_pre_plane_update(intel_crtc);
13601
13602 if (crtc->state->active &&
13603 (crtc->state->planes_changed || update_pipe))
13604 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13605
13606 if (put_domains)
13607 modeset_put_power_domains(dev_priv, put_domains);
13608
13609 intel_post_plane_update(intel_crtc);
13610
13611 if (modeset)
13612 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13613 }
13614
13615 /* FIXME: add subpixel order */
13616
13617 drm_atomic_helper_wait_for_vblanks(dev, state);
13618
13619 mutex_lock(&dev->struct_mutex);
13620 drm_atomic_helper_cleanup_planes(dev, state);
13621 mutex_unlock(&dev->struct_mutex);
13622
13623 if (hw_check)
13624 intel_modeset_check_state(dev, state);
13625
13626 drm_atomic_state_free(state);
13627
13628 /* As one of the primary mmio accessors, KMS has a high likelihood
13629 * of triggering bugs in unclaimed access. After we finish
13630 * modesetting, see if an error has been flagged, and if so
13631 * enable debugging for the next modeset - and hope we catch
13632 * the culprit.
13633 *
13634 * XXX note that we assume display power is on at this point.
13635 * This might hold true now but we need to add pm helper to check
13636 * unclaimed only when the hardware is on, as atomic commits
13637 * can happen also when the device is completely off.
13638 */
13639 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13640
13641 return 0;
13642 }
13643
13644 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13645 {
13646 struct drm_device *dev = crtc->dev;
13647 struct drm_atomic_state *state;
13648 struct drm_crtc_state *crtc_state;
13649 int ret;
13650
13651 state = drm_atomic_state_alloc(dev);
13652 if (!state) {
13653 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13654 crtc->base.id);
13655 return;
13656 }
13657
13658 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13659
13660 retry:
13661 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13662 ret = PTR_ERR_OR_ZERO(crtc_state);
13663 if (!ret) {
13664 if (!crtc_state->active)
13665 goto out;
13666
13667 crtc_state->mode_changed = true;
13668 ret = drm_atomic_commit(state);
13669 }
13670
13671 if (ret == -EDEADLK) {
13672 drm_atomic_state_clear(state);
13673 drm_modeset_backoff(state->acquire_ctx);
13674 goto retry;
13675 }
13676
13677 if (ret)
13678 out:
13679 drm_atomic_state_free(state);
13680 }
13681
13682 #undef for_each_intel_crtc_masked
13683
13684 static const struct drm_crtc_funcs intel_crtc_funcs = {
13685 .gamma_set = intel_crtc_gamma_set,
13686 .set_config = drm_atomic_helper_set_config,
13687 .destroy = intel_crtc_destroy,
13688 .page_flip = intel_crtc_page_flip,
13689 .atomic_duplicate_state = intel_crtc_duplicate_state,
13690 .atomic_destroy_state = intel_crtc_destroy_state,
13691 };
13692
13693 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13694 struct intel_shared_dpll *pll,
13695 struct intel_dpll_hw_state *hw_state)
13696 {
13697 uint32_t val;
13698
13699 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13700 return false;
13701
13702 val = I915_READ(PCH_DPLL(pll->id));
13703 hw_state->dpll = val;
13704 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13705 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13706
13707 return val & DPLL_VCO_ENABLE;
13708 }
13709
13710 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13711 struct intel_shared_dpll *pll)
13712 {
13713 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13714 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13715 }
13716
13717 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13718 struct intel_shared_dpll *pll)
13719 {
13720 /* PCH refclock must be enabled first */
13721 ibx_assert_pch_refclk_enabled(dev_priv);
13722
13723 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13724
13725 /* Wait for the clocks to stabilize. */
13726 POSTING_READ(PCH_DPLL(pll->id));
13727 udelay(150);
13728
13729 /* The pixel multiplier can only be updated once the
13730 * DPLL is enabled and the clocks are stable.
13731 *
13732 * So write it again.
13733 */
13734 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13735 POSTING_READ(PCH_DPLL(pll->id));
13736 udelay(200);
13737 }
13738
13739 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13740 struct intel_shared_dpll *pll)
13741 {
13742 struct drm_device *dev = dev_priv->dev;
13743 struct intel_crtc *crtc;
13744
13745 /* Make sure no transcoder isn't still depending on us. */
13746 for_each_intel_crtc(dev, crtc) {
13747 if (intel_crtc_to_shared_dpll(crtc) == pll)
13748 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13749 }
13750
13751 I915_WRITE(PCH_DPLL(pll->id), 0);
13752 POSTING_READ(PCH_DPLL(pll->id));
13753 udelay(200);
13754 }
13755
13756 static char *ibx_pch_dpll_names[] = {
13757 "PCH DPLL A",
13758 "PCH DPLL B",
13759 };
13760
13761 static void ibx_pch_dpll_init(struct drm_device *dev)
13762 {
13763 struct drm_i915_private *dev_priv = dev->dev_private;
13764 int i;
13765
13766 dev_priv->num_shared_dpll = 2;
13767
13768 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13769 dev_priv->shared_dplls[i].id = i;
13770 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13771 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13772 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13773 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13774 dev_priv->shared_dplls[i].get_hw_state =
13775 ibx_pch_dpll_get_hw_state;
13776 }
13777 }
13778
13779 static void intel_shared_dpll_init(struct drm_device *dev)
13780 {
13781 struct drm_i915_private *dev_priv = dev->dev_private;
13782
13783 if (HAS_DDI(dev))
13784 intel_ddi_pll_init(dev);
13785 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13786 ibx_pch_dpll_init(dev);
13787 else
13788 dev_priv->num_shared_dpll = 0;
13789
13790 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13791 }
13792
13793 /**
13794 * intel_prepare_plane_fb - Prepare fb for usage on plane
13795 * @plane: drm plane to prepare for
13796 * @fb: framebuffer to prepare for presentation
13797 *
13798 * Prepares a framebuffer for usage on a display plane. Generally this
13799 * involves pinning the underlying object and updating the frontbuffer tracking
13800 * bits. Some older platforms need special physical address handling for
13801 * cursor planes.
13802 *
13803 * Must be called with struct_mutex held.
13804 *
13805 * Returns 0 on success, negative error code on failure.
13806 */
13807 int
13808 intel_prepare_plane_fb(struct drm_plane *plane,
13809 const struct drm_plane_state *new_state)
13810 {
13811 struct drm_device *dev = plane->dev;
13812 struct drm_framebuffer *fb = new_state->fb;
13813 struct intel_plane *intel_plane = to_intel_plane(plane);
13814 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13815 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13816 int ret = 0;
13817
13818 if (!obj && !old_obj)
13819 return 0;
13820
13821 if (old_obj) {
13822 struct drm_crtc_state *crtc_state =
13823 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13824
13825 /* Big Hammer, we also need to ensure that any pending
13826 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13827 * current scanout is retired before unpinning the old
13828 * framebuffer. Note that we rely on userspace rendering
13829 * into the buffer attached to the pipe they are waiting
13830 * on. If not, userspace generates a GPU hang with IPEHR
13831 * point to the MI_WAIT_FOR_EVENT.
13832 *
13833 * This should only fail upon a hung GPU, in which case we
13834 * can safely continue.
13835 */
13836 if (needs_modeset(crtc_state))
13837 ret = i915_gem_object_wait_rendering(old_obj, true);
13838
13839 /* Swallow -EIO errors to allow updates during hw lockup. */
13840 if (ret && ret != -EIO)
13841 return ret;
13842 }
13843
13844 /* For framebuffer backed by dmabuf, wait for fence */
13845 if (obj && obj->base.dma_buf) {
13846 long lret;
13847
13848 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13849 false, true,
13850 MAX_SCHEDULE_TIMEOUT);
13851 if (lret == -ERESTARTSYS)
13852 return lret;
13853
13854 WARN(lret < 0, "waiting returns %li\n", lret);
13855 }
13856
13857 if (!obj) {
13858 ret = 0;
13859 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13860 INTEL_INFO(dev)->cursor_needs_physical) {
13861 int align = IS_I830(dev) ? 16 * 1024 : 256;
13862 ret = i915_gem_object_attach_phys(obj, align);
13863 if (ret)
13864 DRM_DEBUG_KMS("failed to attach phys object\n");
13865 } else {
13866 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13867 }
13868
13869 if (ret == 0) {
13870 if (obj) {
13871 struct intel_plane_state *plane_state =
13872 to_intel_plane_state(new_state);
13873
13874 i915_gem_request_assign(&plane_state->wait_req,
13875 obj->last_write_req);
13876 }
13877
13878 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13879 }
13880
13881 return ret;
13882 }
13883
13884 /**
13885 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13886 * @plane: drm plane to clean up for
13887 * @fb: old framebuffer that was on plane
13888 *
13889 * Cleans up a framebuffer that has just been removed from a plane.
13890 *
13891 * Must be called with struct_mutex held.
13892 */
13893 void
13894 intel_cleanup_plane_fb(struct drm_plane *plane,
13895 const struct drm_plane_state *old_state)
13896 {
13897 struct drm_device *dev = plane->dev;
13898 struct intel_plane *intel_plane = to_intel_plane(plane);
13899 struct intel_plane_state *old_intel_state;
13900 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13901 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13902
13903 old_intel_state = to_intel_plane_state(old_state);
13904
13905 if (!obj && !old_obj)
13906 return;
13907
13908 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13909 !INTEL_INFO(dev)->cursor_needs_physical))
13910 intel_unpin_fb_obj(old_state->fb, old_state);
13911
13912 /* prepare_fb aborted? */
13913 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13914 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13915 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13916
13917 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13918
13919 }
13920
13921 int
13922 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13923 {
13924 int max_scale;
13925 struct drm_device *dev;
13926 struct drm_i915_private *dev_priv;
13927 int crtc_clock, cdclk;
13928
13929 if (!intel_crtc || !crtc_state->base.enable)
13930 return DRM_PLANE_HELPER_NO_SCALING;
13931
13932 dev = intel_crtc->base.dev;
13933 dev_priv = dev->dev_private;
13934 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13935 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13936
13937 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13938 return DRM_PLANE_HELPER_NO_SCALING;
13939
13940 /*
13941 * skl max scale is lower of:
13942 * close to 3 but not 3, -1 is for that purpose
13943 * or
13944 * cdclk/crtc_clock
13945 */
13946 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13947
13948 return max_scale;
13949 }
13950
13951 static int
13952 intel_check_primary_plane(struct drm_plane *plane,
13953 struct intel_crtc_state *crtc_state,
13954 struct intel_plane_state *state)
13955 {
13956 struct drm_crtc *crtc = state->base.crtc;
13957 struct drm_framebuffer *fb = state->base.fb;
13958 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13959 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13960 bool can_position = false;
13961
13962 if (INTEL_INFO(plane->dev)->gen >= 9) {
13963 /* use scaler when colorkey is not required */
13964 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13965 min_scale = 1;
13966 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13967 }
13968 can_position = true;
13969 }
13970
13971 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13972 &state->dst, &state->clip,
13973 min_scale, max_scale,
13974 can_position, true,
13975 &state->visible);
13976 }
13977
13978 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13979 struct drm_crtc_state *old_crtc_state)
13980 {
13981 struct drm_device *dev = crtc->dev;
13982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13983 struct intel_crtc_state *old_intel_state =
13984 to_intel_crtc_state(old_crtc_state);
13985 bool modeset = needs_modeset(crtc->state);
13986
13987 /* Perform vblank evasion around commit operation */
13988 intel_pipe_update_start(intel_crtc);
13989
13990 if (modeset)
13991 return;
13992
13993 if (to_intel_crtc_state(crtc->state)->update_pipe)
13994 intel_update_pipe_config(intel_crtc, old_intel_state);
13995 else if (INTEL_INFO(dev)->gen >= 9)
13996 skl_detach_scalers(intel_crtc);
13997 }
13998
13999 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14000 struct drm_crtc_state *old_crtc_state)
14001 {
14002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14003
14004 intel_pipe_update_end(intel_crtc);
14005 }
14006
14007 /**
14008 * intel_plane_destroy - destroy a plane
14009 * @plane: plane to destroy
14010 *
14011 * Common destruction function for all types of planes (primary, cursor,
14012 * sprite).
14013 */
14014 void intel_plane_destroy(struct drm_plane *plane)
14015 {
14016 struct intel_plane *intel_plane = to_intel_plane(plane);
14017 drm_plane_cleanup(plane);
14018 kfree(intel_plane);
14019 }
14020
14021 const struct drm_plane_funcs intel_plane_funcs = {
14022 .update_plane = drm_atomic_helper_update_plane,
14023 .disable_plane = drm_atomic_helper_disable_plane,
14024 .destroy = intel_plane_destroy,
14025 .set_property = drm_atomic_helper_plane_set_property,
14026 .atomic_get_property = intel_plane_atomic_get_property,
14027 .atomic_set_property = intel_plane_atomic_set_property,
14028 .atomic_duplicate_state = intel_plane_duplicate_state,
14029 .atomic_destroy_state = intel_plane_destroy_state,
14030
14031 };
14032
14033 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14034 int pipe)
14035 {
14036 struct intel_plane *primary;
14037 struct intel_plane_state *state;
14038 const uint32_t *intel_primary_formats;
14039 unsigned int num_formats;
14040
14041 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14042 if (primary == NULL)
14043 return NULL;
14044
14045 state = intel_create_plane_state(&primary->base);
14046 if (!state) {
14047 kfree(primary);
14048 return NULL;
14049 }
14050 primary->base.state = &state->base;
14051
14052 primary->can_scale = false;
14053 primary->max_downscale = 1;
14054 if (INTEL_INFO(dev)->gen >= 9) {
14055 primary->can_scale = true;
14056 state->scaler_id = -1;
14057 }
14058 primary->pipe = pipe;
14059 primary->plane = pipe;
14060 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14061 primary->check_plane = intel_check_primary_plane;
14062 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14063 primary->plane = !pipe;
14064
14065 if (INTEL_INFO(dev)->gen >= 9) {
14066 intel_primary_formats = skl_primary_formats;
14067 num_formats = ARRAY_SIZE(skl_primary_formats);
14068
14069 primary->update_plane = skylake_update_primary_plane;
14070 primary->disable_plane = skylake_disable_primary_plane;
14071 } else if (HAS_PCH_SPLIT(dev)) {
14072 intel_primary_formats = i965_primary_formats;
14073 num_formats = ARRAY_SIZE(i965_primary_formats);
14074
14075 primary->update_plane = ironlake_update_primary_plane;
14076 primary->disable_plane = i9xx_disable_primary_plane;
14077 } else if (INTEL_INFO(dev)->gen >= 4) {
14078 intel_primary_formats = i965_primary_formats;
14079 num_formats = ARRAY_SIZE(i965_primary_formats);
14080
14081 primary->update_plane = i9xx_update_primary_plane;
14082 primary->disable_plane = i9xx_disable_primary_plane;
14083 } else {
14084 intel_primary_formats = i8xx_primary_formats;
14085 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14086
14087 primary->update_plane = i9xx_update_primary_plane;
14088 primary->disable_plane = i9xx_disable_primary_plane;
14089 }
14090
14091 drm_universal_plane_init(dev, &primary->base, 0,
14092 &intel_plane_funcs,
14093 intel_primary_formats, num_formats,
14094 DRM_PLANE_TYPE_PRIMARY, NULL);
14095
14096 if (INTEL_INFO(dev)->gen >= 4)
14097 intel_create_rotation_property(dev, primary);
14098
14099 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14100
14101 return &primary->base;
14102 }
14103
14104 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14105 {
14106 if (!dev->mode_config.rotation_property) {
14107 unsigned long flags = BIT(DRM_ROTATE_0) |
14108 BIT(DRM_ROTATE_180);
14109
14110 if (INTEL_INFO(dev)->gen >= 9)
14111 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14112
14113 dev->mode_config.rotation_property =
14114 drm_mode_create_rotation_property(dev, flags);
14115 }
14116 if (dev->mode_config.rotation_property)
14117 drm_object_attach_property(&plane->base.base,
14118 dev->mode_config.rotation_property,
14119 plane->base.state->rotation);
14120 }
14121
14122 static int
14123 intel_check_cursor_plane(struct drm_plane *plane,
14124 struct intel_crtc_state *crtc_state,
14125 struct intel_plane_state *state)
14126 {
14127 struct drm_crtc *crtc = crtc_state->base.crtc;
14128 struct drm_framebuffer *fb = state->base.fb;
14129 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14130 enum pipe pipe = to_intel_plane(plane)->pipe;
14131 unsigned stride;
14132 int ret;
14133
14134 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14135 &state->dst, &state->clip,
14136 DRM_PLANE_HELPER_NO_SCALING,
14137 DRM_PLANE_HELPER_NO_SCALING,
14138 true, true, &state->visible);
14139 if (ret)
14140 return ret;
14141
14142 /* if we want to turn off the cursor ignore width and height */
14143 if (!obj)
14144 return 0;
14145
14146 /* Check for which cursor types we support */
14147 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14148 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14149 state->base.crtc_w, state->base.crtc_h);
14150 return -EINVAL;
14151 }
14152
14153 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14154 if (obj->base.size < stride * state->base.crtc_h) {
14155 DRM_DEBUG_KMS("buffer is too small\n");
14156 return -ENOMEM;
14157 }
14158
14159 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14160 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14161 return -EINVAL;
14162 }
14163
14164 /*
14165 * There's something wrong with the cursor on CHV pipe C.
14166 * If it straddles the left edge of the screen then
14167 * moving it away from the edge or disabling it often
14168 * results in a pipe underrun, and often that can lead to
14169 * dead pipe (constant underrun reported, and it scans
14170 * out just a solid color). To recover from that, the
14171 * display power well must be turned off and on again.
14172 * Refuse the put the cursor into that compromised position.
14173 */
14174 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14175 state->visible && state->base.crtc_x < 0) {
14176 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14177 return -EINVAL;
14178 }
14179
14180 return 0;
14181 }
14182
14183 static void
14184 intel_disable_cursor_plane(struct drm_plane *plane,
14185 struct drm_crtc *crtc)
14186 {
14187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14188
14189 intel_crtc->cursor_addr = 0;
14190 intel_crtc_update_cursor(crtc, NULL);
14191 }
14192
14193 static void
14194 intel_update_cursor_plane(struct drm_plane *plane,
14195 const struct intel_crtc_state *crtc_state,
14196 const struct intel_plane_state *state)
14197 {
14198 struct drm_crtc *crtc = crtc_state->base.crtc;
14199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14200 struct drm_device *dev = plane->dev;
14201 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14202 uint32_t addr;
14203
14204 if (!obj)
14205 addr = 0;
14206 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14207 addr = i915_gem_obj_ggtt_offset(obj);
14208 else
14209 addr = obj->phys_handle->busaddr;
14210
14211 intel_crtc->cursor_addr = addr;
14212 intel_crtc_update_cursor(crtc, state);
14213 }
14214
14215 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14216 int pipe)
14217 {
14218 struct intel_plane *cursor;
14219 struct intel_plane_state *state;
14220
14221 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14222 if (cursor == NULL)
14223 return NULL;
14224
14225 state = intel_create_plane_state(&cursor->base);
14226 if (!state) {
14227 kfree(cursor);
14228 return NULL;
14229 }
14230 cursor->base.state = &state->base;
14231
14232 cursor->can_scale = false;
14233 cursor->max_downscale = 1;
14234 cursor->pipe = pipe;
14235 cursor->plane = pipe;
14236 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14237 cursor->check_plane = intel_check_cursor_plane;
14238 cursor->update_plane = intel_update_cursor_plane;
14239 cursor->disable_plane = intel_disable_cursor_plane;
14240
14241 drm_universal_plane_init(dev, &cursor->base, 0,
14242 &intel_plane_funcs,
14243 intel_cursor_formats,
14244 ARRAY_SIZE(intel_cursor_formats),
14245 DRM_PLANE_TYPE_CURSOR, NULL);
14246
14247 if (INTEL_INFO(dev)->gen >= 4) {
14248 if (!dev->mode_config.rotation_property)
14249 dev->mode_config.rotation_property =
14250 drm_mode_create_rotation_property(dev,
14251 BIT(DRM_ROTATE_0) |
14252 BIT(DRM_ROTATE_180));
14253 if (dev->mode_config.rotation_property)
14254 drm_object_attach_property(&cursor->base.base,
14255 dev->mode_config.rotation_property,
14256 state->base.rotation);
14257 }
14258
14259 if (INTEL_INFO(dev)->gen >=9)
14260 state->scaler_id = -1;
14261
14262 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14263
14264 return &cursor->base;
14265 }
14266
14267 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14268 struct intel_crtc_state *crtc_state)
14269 {
14270 int i;
14271 struct intel_scaler *intel_scaler;
14272 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14273
14274 for (i = 0; i < intel_crtc->num_scalers; i++) {
14275 intel_scaler = &scaler_state->scalers[i];
14276 intel_scaler->in_use = 0;
14277 intel_scaler->mode = PS_SCALER_MODE_DYN;
14278 }
14279
14280 scaler_state->scaler_id = -1;
14281 }
14282
14283 static void intel_crtc_init(struct drm_device *dev, int pipe)
14284 {
14285 struct drm_i915_private *dev_priv = dev->dev_private;
14286 struct intel_crtc *intel_crtc;
14287 struct intel_crtc_state *crtc_state = NULL;
14288 struct drm_plane *primary = NULL;
14289 struct drm_plane *cursor = NULL;
14290 int i, ret;
14291
14292 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14293 if (intel_crtc == NULL)
14294 return;
14295
14296 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14297 if (!crtc_state)
14298 goto fail;
14299 intel_crtc->config = crtc_state;
14300 intel_crtc->base.state = &crtc_state->base;
14301 crtc_state->base.crtc = &intel_crtc->base;
14302
14303 /* initialize shared scalers */
14304 if (INTEL_INFO(dev)->gen >= 9) {
14305 if (pipe == PIPE_C)
14306 intel_crtc->num_scalers = 1;
14307 else
14308 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14309
14310 skl_init_scalers(dev, intel_crtc, crtc_state);
14311 }
14312
14313 primary = intel_primary_plane_create(dev, pipe);
14314 if (!primary)
14315 goto fail;
14316
14317 cursor = intel_cursor_plane_create(dev, pipe);
14318 if (!cursor)
14319 goto fail;
14320
14321 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14322 cursor, &intel_crtc_funcs, NULL);
14323 if (ret)
14324 goto fail;
14325
14326 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14327 for (i = 0; i < 256; i++) {
14328 intel_crtc->lut_r[i] = i;
14329 intel_crtc->lut_g[i] = i;
14330 intel_crtc->lut_b[i] = i;
14331 }
14332
14333 /*
14334 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14335 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14336 */
14337 intel_crtc->pipe = pipe;
14338 intel_crtc->plane = pipe;
14339 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14340 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14341 intel_crtc->plane = !pipe;
14342 }
14343
14344 intel_crtc->cursor_base = ~0;
14345 intel_crtc->cursor_cntl = ~0;
14346 intel_crtc->cursor_size = ~0;
14347
14348 intel_crtc->wm.cxsr_allowed = true;
14349
14350 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14351 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14352 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14353 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14354
14355 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14356
14357 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14358 return;
14359
14360 fail:
14361 if (primary)
14362 drm_plane_cleanup(primary);
14363 if (cursor)
14364 drm_plane_cleanup(cursor);
14365 kfree(crtc_state);
14366 kfree(intel_crtc);
14367 }
14368
14369 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14370 {
14371 struct drm_encoder *encoder = connector->base.encoder;
14372 struct drm_device *dev = connector->base.dev;
14373
14374 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14375
14376 if (!encoder || WARN_ON(!encoder->crtc))
14377 return INVALID_PIPE;
14378
14379 return to_intel_crtc(encoder->crtc)->pipe;
14380 }
14381
14382 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14383 struct drm_file *file)
14384 {
14385 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14386 struct drm_crtc *drmmode_crtc;
14387 struct intel_crtc *crtc;
14388
14389 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14390
14391 if (!drmmode_crtc) {
14392 DRM_ERROR("no such CRTC id\n");
14393 return -ENOENT;
14394 }
14395
14396 crtc = to_intel_crtc(drmmode_crtc);
14397 pipe_from_crtc_id->pipe = crtc->pipe;
14398
14399 return 0;
14400 }
14401
14402 static int intel_encoder_clones(struct intel_encoder *encoder)
14403 {
14404 struct drm_device *dev = encoder->base.dev;
14405 struct intel_encoder *source_encoder;
14406 int index_mask = 0;
14407 int entry = 0;
14408
14409 for_each_intel_encoder(dev, source_encoder) {
14410 if (encoders_cloneable(encoder, source_encoder))
14411 index_mask |= (1 << entry);
14412
14413 entry++;
14414 }
14415
14416 return index_mask;
14417 }
14418
14419 static bool has_edp_a(struct drm_device *dev)
14420 {
14421 struct drm_i915_private *dev_priv = dev->dev_private;
14422
14423 if (!IS_MOBILE(dev))
14424 return false;
14425
14426 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14427 return false;
14428
14429 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14430 return false;
14431
14432 return true;
14433 }
14434
14435 static bool intel_crt_present(struct drm_device *dev)
14436 {
14437 struct drm_i915_private *dev_priv = dev->dev_private;
14438
14439 if (INTEL_INFO(dev)->gen >= 9)
14440 return false;
14441
14442 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14443 return false;
14444
14445 if (IS_CHERRYVIEW(dev))
14446 return false;
14447
14448 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14449 return false;
14450
14451 /* DDI E can't be used if DDI A requires 4 lanes */
14452 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14453 return false;
14454
14455 if (!dev_priv->vbt.int_crt_support)
14456 return false;
14457
14458 return true;
14459 }
14460
14461 static void intel_setup_outputs(struct drm_device *dev)
14462 {
14463 struct drm_i915_private *dev_priv = dev->dev_private;
14464 struct intel_encoder *encoder;
14465 bool dpd_is_edp = false;
14466
14467 intel_lvds_init(dev);
14468
14469 if (intel_crt_present(dev))
14470 intel_crt_init(dev);
14471
14472 if (IS_BROXTON(dev)) {
14473 /*
14474 * FIXME: Broxton doesn't support port detection via the
14475 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14476 * detect the ports.
14477 */
14478 intel_ddi_init(dev, PORT_A);
14479 intel_ddi_init(dev, PORT_B);
14480 intel_ddi_init(dev, PORT_C);
14481 } else if (HAS_DDI(dev)) {
14482 int found;
14483
14484 /*
14485 * Haswell uses DDI functions to detect digital outputs.
14486 * On SKL pre-D0 the strap isn't connected, so we assume
14487 * it's there.
14488 */
14489 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14490 /* WaIgnoreDDIAStrap: skl */
14491 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14492 intel_ddi_init(dev, PORT_A);
14493
14494 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14495 * register */
14496 found = I915_READ(SFUSE_STRAP);
14497
14498 if (found & SFUSE_STRAP_DDIB_DETECTED)
14499 intel_ddi_init(dev, PORT_B);
14500 if (found & SFUSE_STRAP_DDIC_DETECTED)
14501 intel_ddi_init(dev, PORT_C);
14502 if (found & SFUSE_STRAP_DDID_DETECTED)
14503 intel_ddi_init(dev, PORT_D);
14504 /*
14505 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14506 */
14507 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14508 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14509 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14510 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14511 intel_ddi_init(dev, PORT_E);
14512
14513 } else if (HAS_PCH_SPLIT(dev)) {
14514 int found;
14515 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14516
14517 if (has_edp_a(dev))
14518 intel_dp_init(dev, DP_A, PORT_A);
14519
14520 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14521 /* PCH SDVOB multiplex with HDMIB */
14522 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14523 if (!found)
14524 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14525 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14526 intel_dp_init(dev, PCH_DP_B, PORT_B);
14527 }
14528
14529 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14530 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14531
14532 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14533 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14534
14535 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14536 intel_dp_init(dev, PCH_DP_C, PORT_C);
14537
14538 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14539 intel_dp_init(dev, PCH_DP_D, PORT_D);
14540 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14541 /*
14542 * The DP_DETECTED bit is the latched state of the DDC
14543 * SDA pin at boot. However since eDP doesn't require DDC
14544 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14545 * eDP ports may have been muxed to an alternate function.
14546 * Thus we can't rely on the DP_DETECTED bit alone to detect
14547 * eDP ports. Consult the VBT as well as DP_DETECTED to
14548 * detect eDP ports.
14549 */
14550 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14551 !intel_dp_is_edp(dev, PORT_B))
14552 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14553 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14554 intel_dp_is_edp(dev, PORT_B))
14555 intel_dp_init(dev, VLV_DP_B, PORT_B);
14556
14557 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14558 !intel_dp_is_edp(dev, PORT_C))
14559 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14560 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14561 intel_dp_is_edp(dev, PORT_C))
14562 intel_dp_init(dev, VLV_DP_C, PORT_C);
14563
14564 if (IS_CHERRYVIEW(dev)) {
14565 /* eDP not supported on port D, so don't check VBT */
14566 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14567 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14568 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14569 intel_dp_init(dev, CHV_DP_D, PORT_D);
14570 }
14571
14572 intel_dsi_init(dev);
14573 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14574 bool found = false;
14575
14576 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14577 DRM_DEBUG_KMS("probing SDVOB\n");
14578 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14579 if (!found && IS_G4X(dev)) {
14580 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14581 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14582 }
14583
14584 if (!found && IS_G4X(dev))
14585 intel_dp_init(dev, DP_B, PORT_B);
14586 }
14587
14588 /* Before G4X SDVOC doesn't have its own detect register */
14589
14590 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14591 DRM_DEBUG_KMS("probing SDVOC\n");
14592 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14593 }
14594
14595 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14596
14597 if (IS_G4X(dev)) {
14598 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14599 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14600 }
14601 if (IS_G4X(dev))
14602 intel_dp_init(dev, DP_C, PORT_C);
14603 }
14604
14605 if (IS_G4X(dev) &&
14606 (I915_READ(DP_D) & DP_DETECTED))
14607 intel_dp_init(dev, DP_D, PORT_D);
14608 } else if (IS_GEN2(dev))
14609 intel_dvo_init(dev);
14610
14611 if (SUPPORTS_TV(dev))
14612 intel_tv_init(dev);
14613
14614 intel_psr_init(dev);
14615
14616 for_each_intel_encoder(dev, encoder) {
14617 encoder->base.possible_crtcs = encoder->crtc_mask;
14618 encoder->base.possible_clones =
14619 intel_encoder_clones(encoder);
14620 }
14621
14622 intel_init_pch_refclk(dev);
14623
14624 drm_helper_move_panel_connectors_to_head(dev);
14625 }
14626
14627 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14628 {
14629 struct drm_device *dev = fb->dev;
14630 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14631
14632 drm_framebuffer_cleanup(fb);
14633 mutex_lock(&dev->struct_mutex);
14634 WARN_ON(!intel_fb->obj->framebuffer_references--);
14635 drm_gem_object_unreference(&intel_fb->obj->base);
14636 mutex_unlock(&dev->struct_mutex);
14637 kfree(intel_fb);
14638 }
14639
14640 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14641 struct drm_file *file,
14642 unsigned int *handle)
14643 {
14644 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14645 struct drm_i915_gem_object *obj = intel_fb->obj;
14646
14647 if (obj->userptr.mm) {
14648 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14649 return -EINVAL;
14650 }
14651
14652 return drm_gem_handle_create(file, &obj->base, handle);
14653 }
14654
14655 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14656 struct drm_file *file,
14657 unsigned flags, unsigned color,
14658 struct drm_clip_rect *clips,
14659 unsigned num_clips)
14660 {
14661 struct drm_device *dev = fb->dev;
14662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14663 struct drm_i915_gem_object *obj = intel_fb->obj;
14664
14665 mutex_lock(&dev->struct_mutex);
14666 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14667 mutex_unlock(&dev->struct_mutex);
14668
14669 return 0;
14670 }
14671
14672 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14673 .destroy = intel_user_framebuffer_destroy,
14674 .create_handle = intel_user_framebuffer_create_handle,
14675 .dirty = intel_user_framebuffer_dirty,
14676 };
14677
14678 static
14679 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14680 uint32_t pixel_format)
14681 {
14682 u32 gen = INTEL_INFO(dev)->gen;
14683
14684 if (gen >= 9) {
14685 /* "The stride in bytes must not exceed the of the size of 8K
14686 * pixels and 32K bytes."
14687 */
14688 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14689 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14690 return 32*1024;
14691 } else if (gen >= 4) {
14692 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14693 return 16*1024;
14694 else
14695 return 32*1024;
14696 } else if (gen >= 3) {
14697 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14698 return 8*1024;
14699 else
14700 return 16*1024;
14701 } else {
14702 /* XXX DSPC is limited to 4k tiled */
14703 return 8*1024;
14704 }
14705 }
14706
14707 static int intel_framebuffer_init(struct drm_device *dev,
14708 struct intel_framebuffer *intel_fb,
14709 struct drm_mode_fb_cmd2 *mode_cmd,
14710 struct drm_i915_gem_object *obj)
14711 {
14712 struct drm_i915_private *dev_priv = to_i915(dev);
14713 unsigned int aligned_height;
14714 int ret;
14715 u32 pitch_limit, stride_alignment;
14716
14717 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14718
14719 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14720 /* Enforce that fb modifier and tiling mode match, but only for
14721 * X-tiled. This is needed for FBC. */
14722 if (!!(obj->tiling_mode == I915_TILING_X) !=
14723 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14724 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14725 return -EINVAL;
14726 }
14727 } else {
14728 if (obj->tiling_mode == I915_TILING_X)
14729 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14730 else if (obj->tiling_mode == I915_TILING_Y) {
14731 DRM_DEBUG("No Y tiling for legacy addfb\n");
14732 return -EINVAL;
14733 }
14734 }
14735
14736 /* Passed in modifier sanity checking. */
14737 switch (mode_cmd->modifier[0]) {
14738 case I915_FORMAT_MOD_Y_TILED:
14739 case I915_FORMAT_MOD_Yf_TILED:
14740 if (INTEL_INFO(dev)->gen < 9) {
14741 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14742 mode_cmd->modifier[0]);
14743 return -EINVAL;
14744 }
14745 case DRM_FORMAT_MOD_NONE:
14746 case I915_FORMAT_MOD_X_TILED:
14747 break;
14748 default:
14749 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14750 mode_cmd->modifier[0]);
14751 return -EINVAL;
14752 }
14753
14754 stride_alignment = intel_fb_stride_alignment(dev_priv,
14755 mode_cmd->modifier[0],
14756 mode_cmd->pixel_format);
14757 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14758 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14759 mode_cmd->pitches[0], stride_alignment);
14760 return -EINVAL;
14761 }
14762
14763 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14764 mode_cmd->pixel_format);
14765 if (mode_cmd->pitches[0] > pitch_limit) {
14766 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14767 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14768 "tiled" : "linear",
14769 mode_cmd->pitches[0], pitch_limit);
14770 return -EINVAL;
14771 }
14772
14773 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14774 mode_cmd->pitches[0] != obj->stride) {
14775 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14776 mode_cmd->pitches[0], obj->stride);
14777 return -EINVAL;
14778 }
14779
14780 /* Reject formats not supported by any plane early. */
14781 switch (mode_cmd->pixel_format) {
14782 case DRM_FORMAT_C8:
14783 case DRM_FORMAT_RGB565:
14784 case DRM_FORMAT_XRGB8888:
14785 case DRM_FORMAT_ARGB8888:
14786 break;
14787 case DRM_FORMAT_XRGB1555:
14788 if (INTEL_INFO(dev)->gen > 3) {
14789 DRM_DEBUG("unsupported pixel format: %s\n",
14790 drm_get_format_name(mode_cmd->pixel_format));
14791 return -EINVAL;
14792 }
14793 break;
14794 case DRM_FORMAT_ABGR8888:
14795 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14796 INTEL_INFO(dev)->gen < 9) {
14797 DRM_DEBUG("unsupported pixel format: %s\n",
14798 drm_get_format_name(mode_cmd->pixel_format));
14799 return -EINVAL;
14800 }
14801 break;
14802 case DRM_FORMAT_XBGR8888:
14803 case DRM_FORMAT_XRGB2101010:
14804 case DRM_FORMAT_XBGR2101010:
14805 if (INTEL_INFO(dev)->gen < 4) {
14806 DRM_DEBUG("unsupported pixel format: %s\n",
14807 drm_get_format_name(mode_cmd->pixel_format));
14808 return -EINVAL;
14809 }
14810 break;
14811 case DRM_FORMAT_ABGR2101010:
14812 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14813 DRM_DEBUG("unsupported pixel format: %s\n",
14814 drm_get_format_name(mode_cmd->pixel_format));
14815 return -EINVAL;
14816 }
14817 break;
14818 case DRM_FORMAT_YUYV:
14819 case DRM_FORMAT_UYVY:
14820 case DRM_FORMAT_YVYU:
14821 case DRM_FORMAT_VYUY:
14822 if (INTEL_INFO(dev)->gen < 5) {
14823 DRM_DEBUG("unsupported pixel format: %s\n",
14824 drm_get_format_name(mode_cmd->pixel_format));
14825 return -EINVAL;
14826 }
14827 break;
14828 default:
14829 DRM_DEBUG("unsupported pixel format: %s\n",
14830 drm_get_format_name(mode_cmd->pixel_format));
14831 return -EINVAL;
14832 }
14833
14834 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14835 if (mode_cmd->offsets[0] != 0)
14836 return -EINVAL;
14837
14838 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14839 mode_cmd->pixel_format,
14840 mode_cmd->modifier[0]);
14841 /* FIXME drm helper for size checks (especially planar formats)? */
14842 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14843 return -EINVAL;
14844
14845 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14846 intel_fb->obj = obj;
14847
14848 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14849 if (ret) {
14850 DRM_ERROR("framebuffer init failed %d\n", ret);
14851 return ret;
14852 }
14853
14854 intel_fb->obj->framebuffer_references++;
14855
14856 return 0;
14857 }
14858
14859 static struct drm_framebuffer *
14860 intel_user_framebuffer_create(struct drm_device *dev,
14861 struct drm_file *filp,
14862 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14863 {
14864 struct drm_framebuffer *fb;
14865 struct drm_i915_gem_object *obj;
14866 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14867
14868 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14869 mode_cmd.handles[0]));
14870 if (&obj->base == NULL)
14871 return ERR_PTR(-ENOENT);
14872
14873 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14874 if (IS_ERR(fb))
14875 drm_gem_object_unreference_unlocked(&obj->base);
14876
14877 return fb;
14878 }
14879
14880 #ifndef CONFIG_DRM_FBDEV_EMULATION
14881 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14882 {
14883 }
14884 #endif
14885
14886 static const struct drm_mode_config_funcs intel_mode_funcs = {
14887 .fb_create = intel_user_framebuffer_create,
14888 .output_poll_changed = intel_fbdev_output_poll_changed,
14889 .atomic_check = intel_atomic_check,
14890 .atomic_commit = intel_atomic_commit,
14891 .atomic_state_alloc = intel_atomic_state_alloc,
14892 .atomic_state_clear = intel_atomic_state_clear,
14893 };
14894
14895 /* Set up chip specific display functions */
14896 static void intel_init_display(struct drm_device *dev)
14897 {
14898 struct drm_i915_private *dev_priv = dev->dev_private;
14899
14900 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14901 dev_priv->display.find_dpll = g4x_find_best_dpll;
14902 else if (IS_CHERRYVIEW(dev))
14903 dev_priv->display.find_dpll = chv_find_best_dpll;
14904 else if (IS_VALLEYVIEW(dev))
14905 dev_priv->display.find_dpll = vlv_find_best_dpll;
14906 else if (IS_PINEVIEW(dev))
14907 dev_priv->display.find_dpll = pnv_find_best_dpll;
14908 else
14909 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14910
14911 if (INTEL_INFO(dev)->gen >= 9) {
14912 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14913 dev_priv->display.get_initial_plane_config =
14914 skylake_get_initial_plane_config;
14915 dev_priv->display.crtc_compute_clock =
14916 haswell_crtc_compute_clock;
14917 dev_priv->display.crtc_enable = haswell_crtc_enable;
14918 dev_priv->display.crtc_disable = haswell_crtc_disable;
14919 } else if (HAS_DDI(dev)) {
14920 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14921 dev_priv->display.get_initial_plane_config =
14922 ironlake_get_initial_plane_config;
14923 dev_priv->display.crtc_compute_clock =
14924 haswell_crtc_compute_clock;
14925 dev_priv->display.crtc_enable = haswell_crtc_enable;
14926 dev_priv->display.crtc_disable = haswell_crtc_disable;
14927 } else if (HAS_PCH_SPLIT(dev)) {
14928 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14929 dev_priv->display.get_initial_plane_config =
14930 ironlake_get_initial_plane_config;
14931 dev_priv->display.crtc_compute_clock =
14932 ironlake_crtc_compute_clock;
14933 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14934 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14935 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14936 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14937 dev_priv->display.get_initial_plane_config =
14938 i9xx_get_initial_plane_config;
14939 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14940 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14941 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14942 } else {
14943 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14944 dev_priv->display.get_initial_plane_config =
14945 i9xx_get_initial_plane_config;
14946 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14947 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14948 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14949 }
14950
14951 /* Returns the core display clock speed */
14952 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14953 dev_priv->display.get_display_clock_speed =
14954 skylake_get_display_clock_speed;
14955 else if (IS_BROXTON(dev))
14956 dev_priv->display.get_display_clock_speed =
14957 broxton_get_display_clock_speed;
14958 else if (IS_BROADWELL(dev))
14959 dev_priv->display.get_display_clock_speed =
14960 broadwell_get_display_clock_speed;
14961 else if (IS_HASWELL(dev))
14962 dev_priv->display.get_display_clock_speed =
14963 haswell_get_display_clock_speed;
14964 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14965 dev_priv->display.get_display_clock_speed =
14966 valleyview_get_display_clock_speed;
14967 else if (IS_GEN5(dev))
14968 dev_priv->display.get_display_clock_speed =
14969 ilk_get_display_clock_speed;
14970 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14971 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14972 dev_priv->display.get_display_clock_speed =
14973 i945_get_display_clock_speed;
14974 else if (IS_GM45(dev))
14975 dev_priv->display.get_display_clock_speed =
14976 gm45_get_display_clock_speed;
14977 else if (IS_CRESTLINE(dev))
14978 dev_priv->display.get_display_clock_speed =
14979 i965gm_get_display_clock_speed;
14980 else if (IS_PINEVIEW(dev))
14981 dev_priv->display.get_display_clock_speed =
14982 pnv_get_display_clock_speed;
14983 else if (IS_G33(dev) || IS_G4X(dev))
14984 dev_priv->display.get_display_clock_speed =
14985 g33_get_display_clock_speed;
14986 else if (IS_I915G(dev))
14987 dev_priv->display.get_display_clock_speed =
14988 i915_get_display_clock_speed;
14989 else if (IS_I945GM(dev) || IS_845G(dev))
14990 dev_priv->display.get_display_clock_speed =
14991 i9xx_misc_get_display_clock_speed;
14992 else if (IS_I915GM(dev))
14993 dev_priv->display.get_display_clock_speed =
14994 i915gm_get_display_clock_speed;
14995 else if (IS_I865G(dev))
14996 dev_priv->display.get_display_clock_speed =
14997 i865_get_display_clock_speed;
14998 else if (IS_I85X(dev))
14999 dev_priv->display.get_display_clock_speed =
15000 i85x_get_display_clock_speed;
15001 else { /* 830 */
15002 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15003 dev_priv->display.get_display_clock_speed =
15004 i830_get_display_clock_speed;
15005 }
15006
15007 if (IS_GEN5(dev)) {
15008 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15009 } else if (IS_GEN6(dev)) {
15010 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15011 } else if (IS_IVYBRIDGE(dev)) {
15012 /* FIXME: detect B0+ stepping and use auto training */
15013 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15014 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15015 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15016 if (IS_BROADWELL(dev)) {
15017 dev_priv->display.modeset_commit_cdclk =
15018 broadwell_modeset_commit_cdclk;
15019 dev_priv->display.modeset_calc_cdclk =
15020 broadwell_modeset_calc_cdclk;
15021 }
15022 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15023 dev_priv->display.modeset_commit_cdclk =
15024 valleyview_modeset_commit_cdclk;
15025 dev_priv->display.modeset_calc_cdclk =
15026 valleyview_modeset_calc_cdclk;
15027 } else if (IS_BROXTON(dev)) {
15028 dev_priv->display.modeset_commit_cdclk =
15029 broxton_modeset_commit_cdclk;
15030 dev_priv->display.modeset_calc_cdclk =
15031 broxton_modeset_calc_cdclk;
15032 }
15033
15034 switch (INTEL_INFO(dev)->gen) {
15035 case 2:
15036 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15037 break;
15038
15039 case 3:
15040 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15041 break;
15042
15043 case 4:
15044 case 5:
15045 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15046 break;
15047
15048 case 6:
15049 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15050 break;
15051 case 7:
15052 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15053 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15054 break;
15055 case 9:
15056 /* Drop through - unsupported since execlist only. */
15057 default:
15058 /* Default just returns -ENODEV to indicate unsupported */
15059 dev_priv->display.queue_flip = intel_default_queue_flip;
15060 }
15061
15062 mutex_init(&dev_priv->pps_mutex);
15063 }
15064
15065 /*
15066 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15067 * resume, or other times. This quirk makes sure that's the case for
15068 * affected systems.
15069 */
15070 static void quirk_pipea_force(struct drm_device *dev)
15071 {
15072 struct drm_i915_private *dev_priv = dev->dev_private;
15073
15074 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15075 DRM_INFO("applying pipe a force quirk\n");
15076 }
15077
15078 static void quirk_pipeb_force(struct drm_device *dev)
15079 {
15080 struct drm_i915_private *dev_priv = dev->dev_private;
15081
15082 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15083 DRM_INFO("applying pipe b force quirk\n");
15084 }
15085
15086 /*
15087 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15088 */
15089 static void quirk_ssc_force_disable(struct drm_device *dev)
15090 {
15091 struct drm_i915_private *dev_priv = dev->dev_private;
15092 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15093 DRM_INFO("applying lvds SSC disable quirk\n");
15094 }
15095
15096 /*
15097 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15098 * brightness value
15099 */
15100 static void quirk_invert_brightness(struct drm_device *dev)
15101 {
15102 struct drm_i915_private *dev_priv = dev->dev_private;
15103 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15104 DRM_INFO("applying inverted panel brightness quirk\n");
15105 }
15106
15107 /* Some VBT's incorrectly indicate no backlight is present */
15108 static void quirk_backlight_present(struct drm_device *dev)
15109 {
15110 struct drm_i915_private *dev_priv = dev->dev_private;
15111 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15112 DRM_INFO("applying backlight present quirk\n");
15113 }
15114
15115 struct intel_quirk {
15116 int device;
15117 int subsystem_vendor;
15118 int subsystem_device;
15119 void (*hook)(struct drm_device *dev);
15120 };
15121
15122 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15123 struct intel_dmi_quirk {
15124 void (*hook)(struct drm_device *dev);
15125 const struct dmi_system_id (*dmi_id_list)[];
15126 };
15127
15128 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15129 {
15130 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15131 return 1;
15132 }
15133
15134 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15135 {
15136 .dmi_id_list = &(const struct dmi_system_id[]) {
15137 {
15138 .callback = intel_dmi_reverse_brightness,
15139 .ident = "NCR Corporation",
15140 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15141 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15142 },
15143 },
15144 { } /* terminating entry */
15145 },
15146 .hook = quirk_invert_brightness,
15147 },
15148 };
15149
15150 static struct intel_quirk intel_quirks[] = {
15151 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15152 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15153
15154 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15155 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15156
15157 /* 830 needs to leave pipe A & dpll A up */
15158 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15159
15160 /* 830 needs to leave pipe B & dpll B up */
15161 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15162
15163 /* Lenovo U160 cannot use SSC on LVDS */
15164 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15165
15166 /* Sony Vaio Y cannot use SSC on LVDS */
15167 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15168
15169 /* Acer Aspire 5734Z must invert backlight brightness */
15170 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15171
15172 /* Acer/eMachines G725 */
15173 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15174
15175 /* Acer/eMachines e725 */
15176 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15177
15178 /* Acer/Packard Bell NCL20 */
15179 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15180
15181 /* Acer Aspire 4736Z */
15182 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15183
15184 /* Acer Aspire 5336 */
15185 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15186
15187 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15188 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15189
15190 /* Acer C720 Chromebook (Core i3 4005U) */
15191 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15192
15193 /* Apple Macbook 2,1 (Core 2 T7400) */
15194 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15195
15196 /* Apple Macbook 4,1 */
15197 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15198
15199 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15200 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15201
15202 /* HP Chromebook 14 (Celeron 2955U) */
15203 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15204
15205 /* Dell Chromebook 11 */
15206 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15207
15208 /* Dell Chromebook 11 (2015 version) */
15209 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15210 };
15211
15212 static void intel_init_quirks(struct drm_device *dev)
15213 {
15214 struct pci_dev *d = dev->pdev;
15215 int i;
15216
15217 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15218 struct intel_quirk *q = &intel_quirks[i];
15219
15220 if (d->device == q->device &&
15221 (d->subsystem_vendor == q->subsystem_vendor ||
15222 q->subsystem_vendor == PCI_ANY_ID) &&
15223 (d->subsystem_device == q->subsystem_device ||
15224 q->subsystem_device == PCI_ANY_ID))
15225 q->hook(dev);
15226 }
15227 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15228 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15229 intel_dmi_quirks[i].hook(dev);
15230 }
15231 }
15232
15233 /* Disable the VGA plane that we never use */
15234 static void i915_disable_vga(struct drm_device *dev)
15235 {
15236 struct drm_i915_private *dev_priv = dev->dev_private;
15237 u8 sr1;
15238 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15239
15240 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15241 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15242 outb(SR01, VGA_SR_INDEX);
15243 sr1 = inb(VGA_SR_DATA);
15244 outb(sr1 | 1<<5, VGA_SR_DATA);
15245 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15246 udelay(300);
15247
15248 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15249 POSTING_READ(vga_reg);
15250 }
15251
15252 void intel_modeset_init_hw(struct drm_device *dev)
15253 {
15254 struct drm_i915_private *dev_priv = dev->dev_private;
15255
15256 intel_update_cdclk(dev);
15257
15258 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15259
15260 intel_init_clock_gating(dev);
15261 intel_enable_gt_powersave(dev);
15262 }
15263
15264 /*
15265 * Calculate what we think the watermarks should be for the state we've read
15266 * out of the hardware and then immediately program those watermarks so that
15267 * we ensure the hardware settings match our internal state.
15268 *
15269 * We can calculate what we think WM's should be by creating a duplicate of the
15270 * current state (which was constructed during hardware readout) and running it
15271 * through the atomic check code to calculate new watermark values in the
15272 * state object.
15273 */
15274 static void sanitize_watermarks(struct drm_device *dev)
15275 {
15276 struct drm_i915_private *dev_priv = to_i915(dev);
15277 struct drm_atomic_state *state;
15278 struct drm_crtc *crtc;
15279 struct drm_crtc_state *cstate;
15280 struct drm_modeset_acquire_ctx ctx;
15281 int ret;
15282 int i;
15283
15284 /* Only supported on platforms that use atomic watermark design */
15285 if (!dev_priv->display.program_watermarks)
15286 return;
15287
15288 /*
15289 * We need to hold connection_mutex before calling duplicate_state so
15290 * that the connector loop is protected.
15291 */
15292 drm_modeset_acquire_init(&ctx, 0);
15293 retry:
15294 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15295 if (ret == -EDEADLK) {
15296 drm_modeset_backoff(&ctx);
15297 goto retry;
15298 } else if (WARN_ON(ret)) {
15299 goto fail;
15300 }
15301
15302 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15303 if (WARN_ON(IS_ERR(state)))
15304 goto fail;
15305
15306 ret = intel_atomic_check(dev, state);
15307 if (ret) {
15308 /*
15309 * If we fail here, it means that the hardware appears to be
15310 * programmed in a way that shouldn't be possible, given our
15311 * understanding of watermark requirements. This might mean a
15312 * mistake in the hardware readout code or a mistake in the
15313 * watermark calculations for a given platform. Raise a WARN
15314 * so that this is noticeable.
15315 *
15316 * If this actually happens, we'll have to just leave the
15317 * BIOS-programmed watermarks untouched and hope for the best.
15318 */
15319 WARN(true, "Could not determine valid watermarks for inherited state\n");
15320 goto fail;
15321 }
15322
15323 /* Write calculated watermark values back */
15324 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15325 for_each_crtc_in_state(state, crtc, cstate, i) {
15326 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15327
15328 dev_priv->display.program_watermarks(cs);
15329 }
15330
15331 drm_atomic_state_free(state);
15332 fail:
15333 drm_modeset_drop_locks(&ctx);
15334 drm_modeset_acquire_fini(&ctx);
15335 }
15336
15337 void intel_modeset_init(struct drm_device *dev)
15338 {
15339 struct drm_i915_private *dev_priv = dev->dev_private;
15340 int sprite, ret;
15341 enum pipe pipe;
15342 struct intel_crtc *crtc;
15343
15344 drm_mode_config_init(dev);
15345
15346 dev->mode_config.min_width = 0;
15347 dev->mode_config.min_height = 0;
15348
15349 dev->mode_config.preferred_depth = 24;
15350 dev->mode_config.prefer_shadow = 1;
15351
15352 dev->mode_config.allow_fb_modifiers = true;
15353
15354 dev->mode_config.funcs = &intel_mode_funcs;
15355
15356 intel_init_quirks(dev);
15357
15358 intel_init_pm(dev);
15359
15360 if (INTEL_INFO(dev)->num_pipes == 0)
15361 return;
15362
15363 /*
15364 * There may be no VBT; and if the BIOS enabled SSC we can
15365 * just keep using it to avoid unnecessary flicker. Whereas if the
15366 * BIOS isn't using it, don't assume it will work even if the VBT
15367 * indicates as much.
15368 */
15369 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15370 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15371 DREF_SSC1_ENABLE);
15372
15373 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15374 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15375 bios_lvds_use_ssc ? "en" : "dis",
15376 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15377 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15378 }
15379 }
15380
15381 intel_init_display(dev);
15382 intel_init_audio(dev);
15383
15384 if (IS_GEN2(dev)) {
15385 dev->mode_config.max_width = 2048;
15386 dev->mode_config.max_height = 2048;
15387 } else if (IS_GEN3(dev)) {
15388 dev->mode_config.max_width = 4096;
15389 dev->mode_config.max_height = 4096;
15390 } else {
15391 dev->mode_config.max_width = 8192;
15392 dev->mode_config.max_height = 8192;
15393 }
15394
15395 if (IS_845G(dev) || IS_I865G(dev)) {
15396 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15397 dev->mode_config.cursor_height = 1023;
15398 } else if (IS_GEN2(dev)) {
15399 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15400 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15401 } else {
15402 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15403 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15404 }
15405
15406 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15407
15408 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15409 INTEL_INFO(dev)->num_pipes,
15410 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15411
15412 for_each_pipe(dev_priv, pipe) {
15413 intel_crtc_init(dev, pipe);
15414 for_each_sprite(dev_priv, pipe, sprite) {
15415 ret = intel_plane_init(dev, pipe, sprite);
15416 if (ret)
15417 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15418 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15419 }
15420 }
15421
15422 intel_update_czclk(dev_priv);
15423 intel_update_cdclk(dev);
15424
15425 intel_shared_dpll_init(dev);
15426
15427 /* Just disable it once at startup */
15428 i915_disable_vga(dev);
15429 intel_setup_outputs(dev);
15430
15431 drm_modeset_lock_all(dev);
15432 intel_modeset_setup_hw_state(dev);
15433 drm_modeset_unlock_all(dev);
15434
15435 for_each_intel_crtc(dev, crtc) {
15436 struct intel_initial_plane_config plane_config = {};
15437
15438 if (!crtc->active)
15439 continue;
15440
15441 /*
15442 * Note that reserving the BIOS fb up front prevents us
15443 * from stuffing other stolen allocations like the ring
15444 * on top. This prevents some ugliness at boot time, and
15445 * can even allow for smooth boot transitions if the BIOS
15446 * fb is large enough for the active pipe configuration.
15447 */
15448 dev_priv->display.get_initial_plane_config(crtc,
15449 &plane_config);
15450
15451 /*
15452 * If the fb is shared between multiple heads, we'll
15453 * just get the first one.
15454 */
15455 intel_find_initial_plane_obj(crtc, &plane_config);
15456 }
15457
15458 /*
15459 * Make sure hardware watermarks really match the state we read out.
15460 * Note that we need to do this after reconstructing the BIOS fb's
15461 * since the watermark calculation done here will use pstate->fb.
15462 */
15463 sanitize_watermarks(dev);
15464 }
15465
15466 static void intel_enable_pipe_a(struct drm_device *dev)
15467 {
15468 struct intel_connector *connector;
15469 struct drm_connector *crt = NULL;
15470 struct intel_load_detect_pipe load_detect_temp;
15471 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15472
15473 /* We can't just switch on the pipe A, we need to set things up with a
15474 * proper mode and output configuration. As a gross hack, enable pipe A
15475 * by enabling the load detect pipe once. */
15476 for_each_intel_connector(dev, connector) {
15477 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15478 crt = &connector->base;
15479 break;
15480 }
15481 }
15482
15483 if (!crt)
15484 return;
15485
15486 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15487 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15488 }
15489
15490 static bool
15491 intel_check_plane_mapping(struct intel_crtc *crtc)
15492 {
15493 struct drm_device *dev = crtc->base.dev;
15494 struct drm_i915_private *dev_priv = dev->dev_private;
15495 u32 val;
15496
15497 if (INTEL_INFO(dev)->num_pipes == 1)
15498 return true;
15499
15500 val = I915_READ(DSPCNTR(!crtc->plane));
15501
15502 if ((val & DISPLAY_PLANE_ENABLE) &&
15503 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15504 return false;
15505
15506 return true;
15507 }
15508
15509 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15510 {
15511 struct drm_device *dev = crtc->base.dev;
15512 struct intel_encoder *encoder;
15513
15514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15515 return true;
15516
15517 return false;
15518 }
15519
15520 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15521 {
15522 struct drm_device *dev = crtc->base.dev;
15523 struct drm_i915_private *dev_priv = dev->dev_private;
15524 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15525
15526 /* Clear any frame start delays used for debugging left by the BIOS */
15527 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15528
15529 /* restore vblank interrupts to correct state */
15530 drm_crtc_vblank_reset(&crtc->base);
15531 if (crtc->active) {
15532 struct intel_plane *plane;
15533
15534 drm_crtc_vblank_on(&crtc->base);
15535
15536 /* Disable everything but the primary plane */
15537 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15538 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15539 continue;
15540
15541 plane->disable_plane(&plane->base, &crtc->base);
15542 }
15543 }
15544
15545 /* We need to sanitize the plane -> pipe mapping first because this will
15546 * disable the crtc (and hence change the state) if it is wrong. Note
15547 * that gen4+ has a fixed plane -> pipe mapping. */
15548 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15549 bool plane;
15550
15551 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15552 crtc->base.base.id);
15553
15554 /* Pipe has the wrong plane attached and the plane is active.
15555 * Temporarily change the plane mapping and disable everything
15556 * ... */
15557 plane = crtc->plane;
15558 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15559 crtc->plane = !plane;
15560 intel_crtc_disable_noatomic(&crtc->base);
15561 crtc->plane = plane;
15562 }
15563
15564 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15565 crtc->pipe == PIPE_A && !crtc->active) {
15566 /* BIOS forgot to enable pipe A, this mostly happens after
15567 * resume. Force-enable the pipe to fix this, the update_dpms
15568 * call below we restore the pipe to the right state, but leave
15569 * the required bits on. */
15570 intel_enable_pipe_a(dev);
15571 }
15572
15573 /* Adjust the state of the output pipe according to whether we
15574 * have active connectors/encoders. */
15575 if (!intel_crtc_has_encoders(crtc))
15576 intel_crtc_disable_noatomic(&crtc->base);
15577
15578 if (crtc->active != crtc->base.state->active) {
15579 struct intel_encoder *encoder;
15580
15581 /* This can happen either due to bugs in the get_hw_state
15582 * functions or because of calls to intel_crtc_disable_noatomic,
15583 * or because the pipe is force-enabled due to the
15584 * pipe A quirk. */
15585 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15586 crtc->base.base.id,
15587 crtc->base.state->enable ? "enabled" : "disabled",
15588 crtc->active ? "enabled" : "disabled");
15589
15590 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15591 crtc->base.state->active = crtc->active;
15592 crtc->base.enabled = crtc->active;
15593 crtc->base.state->connector_mask = 0;
15594 crtc->base.state->encoder_mask = 0;
15595
15596 /* Because we only establish the connector -> encoder ->
15597 * crtc links if something is active, this means the
15598 * crtc is now deactivated. Break the links. connector
15599 * -> encoder links are only establish when things are
15600 * actually up, hence no need to break them. */
15601 WARN_ON(crtc->active);
15602
15603 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15604 encoder->base.crtc = NULL;
15605 }
15606
15607 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15608 /*
15609 * We start out with underrun reporting disabled to avoid races.
15610 * For correct bookkeeping mark this on active crtcs.
15611 *
15612 * Also on gmch platforms we dont have any hardware bits to
15613 * disable the underrun reporting. Which means we need to start
15614 * out with underrun reporting disabled also on inactive pipes,
15615 * since otherwise we'll complain about the garbage we read when
15616 * e.g. coming up after runtime pm.
15617 *
15618 * No protection against concurrent access is required - at
15619 * worst a fifo underrun happens which also sets this to false.
15620 */
15621 crtc->cpu_fifo_underrun_disabled = true;
15622 crtc->pch_fifo_underrun_disabled = true;
15623 }
15624 }
15625
15626 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15627 {
15628 struct intel_connector *connector;
15629 struct drm_device *dev = encoder->base.dev;
15630 bool active = false;
15631
15632 /* We need to check both for a crtc link (meaning that the
15633 * encoder is active and trying to read from a pipe) and the
15634 * pipe itself being active. */
15635 bool has_active_crtc = encoder->base.crtc &&
15636 to_intel_crtc(encoder->base.crtc)->active;
15637
15638 for_each_intel_connector(dev, connector) {
15639 if (connector->base.encoder != &encoder->base)
15640 continue;
15641
15642 active = true;
15643 break;
15644 }
15645
15646 if (active && !has_active_crtc) {
15647 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15648 encoder->base.base.id,
15649 encoder->base.name);
15650
15651 /* Connector is active, but has no active pipe. This is
15652 * fallout from our resume register restoring. Disable
15653 * the encoder manually again. */
15654 if (encoder->base.crtc) {
15655 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15656 encoder->base.base.id,
15657 encoder->base.name);
15658 encoder->disable(encoder);
15659 if (encoder->post_disable)
15660 encoder->post_disable(encoder);
15661 }
15662 encoder->base.crtc = NULL;
15663
15664 /* Inconsistent output/port/pipe state happens presumably due to
15665 * a bug in one of the get_hw_state functions. Or someplace else
15666 * in our code, like the register restore mess on resume. Clamp
15667 * things to off as a safer default. */
15668 for_each_intel_connector(dev, connector) {
15669 if (connector->encoder != encoder)
15670 continue;
15671 connector->base.dpms = DRM_MODE_DPMS_OFF;
15672 connector->base.encoder = NULL;
15673 }
15674 }
15675 /* Enabled encoders without active connectors will be fixed in
15676 * the crtc fixup. */
15677 }
15678
15679 void i915_redisable_vga_power_on(struct drm_device *dev)
15680 {
15681 struct drm_i915_private *dev_priv = dev->dev_private;
15682 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15683
15684 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15685 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15686 i915_disable_vga(dev);
15687 }
15688 }
15689
15690 void i915_redisable_vga(struct drm_device *dev)
15691 {
15692 struct drm_i915_private *dev_priv = dev->dev_private;
15693
15694 /* This function can be called both from intel_modeset_setup_hw_state or
15695 * at a very early point in our resume sequence, where the power well
15696 * structures are not yet restored. Since this function is at a very
15697 * paranoid "someone might have enabled VGA while we were not looking"
15698 * level, just check if the power well is enabled instead of trying to
15699 * follow the "don't touch the power well if we don't need it" policy
15700 * the rest of the driver uses. */
15701 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15702 return;
15703
15704 i915_redisable_vga_power_on(dev);
15705 }
15706
15707 static bool primary_get_hw_state(struct intel_plane *plane)
15708 {
15709 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15710
15711 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15712 }
15713
15714 /* FIXME read out full plane state for all planes */
15715 static void readout_plane_state(struct intel_crtc *crtc)
15716 {
15717 struct drm_plane *primary = crtc->base.primary;
15718 struct intel_plane_state *plane_state =
15719 to_intel_plane_state(primary->state);
15720
15721 plane_state->visible = crtc->active &&
15722 primary_get_hw_state(to_intel_plane(primary));
15723
15724 if (plane_state->visible)
15725 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15726 }
15727
15728 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15729 {
15730 struct drm_i915_private *dev_priv = dev->dev_private;
15731 enum pipe pipe;
15732 struct intel_crtc *crtc;
15733 struct intel_encoder *encoder;
15734 struct intel_connector *connector;
15735 int i;
15736
15737 dev_priv->active_crtcs = 0;
15738
15739 for_each_intel_crtc(dev, crtc) {
15740 struct intel_crtc_state *crtc_state = crtc->config;
15741 int pixclk = 0;
15742
15743 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15744 memset(crtc_state, 0, sizeof(*crtc_state));
15745 crtc_state->base.crtc = &crtc->base;
15746
15747 crtc_state->base.active = crtc_state->base.enable =
15748 dev_priv->display.get_pipe_config(crtc, crtc_state);
15749
15750 crtc->base.enabled = crtc_state->base.enable;
15751 crtc->active = crtc_state->base.active;
15752
15753 if (crtc_state->base.active) {
15754 dev_priv->active_crtcs |= 1 << crtc->pipe;
15755
15756 if (IS_BROADWELL(dev_priv)) {
15757 pixclk = ilk_pipe_pixel_rate(crtc_state);
15758
15759 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15760 if (crtc_state->ips_enabled)
15761 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15762 } else if (IS_VALLEYVIEW(dev_priv) ||
15763 IS_CHERRYVIEW(dev_priv) ||
15764 IS_BROXTON(dev_priv))
15765 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15766 else
15767 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15768 }
15769
15770 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15771
15772 readout_plane_state(crtc);
15773
15774 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15775 crtc->base.base.id,
15776 crtc->active ? "enabled" : "disabled");
15777 }
15778
15779 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15780 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15781
15782 pll->on = pll->get_hw_state(dev_priv, pll,
15783 &pll->config.hw_state);
15784 pll->active = 0;
15785 pll->config.crtc_mask = 0;
15786 for_each_intel_crtc(dev, crtc) {
15787 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15788 pll->active++;
15789 pll->config.crtc_mask |= 1 << crtc->pipe;
15790 }
15791 }
15792
15793 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15794 pll->name, pll->config.crtc_mask, pll->on);
15795
15796 if (pll->config.crtc_mask)
15797 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15798 }
15799
15800 for_each_intel_encoder(dev, encoder) {
15801 pipe = 0;
15802
15803 if (encoder->get_hw_state(encoder, &pipe)) {
15804 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15805 encoder->base.crtc = &crtc->base;
15806 encoder->get_config(encoder, crtc->config);
15807 } else {
15808 encoder->base.crtc = NULL;
15809 }
15810
15811 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15812 encoder->base.base.id,
15813 encoder->base.name,
15814 encoder->base.crtc ? "enabled" : "disabled",
15815 pipe_name(pipe));
15816 }
15817
15818 for_each_intel_connector(dev, connector) {
15819 if (connector->get_hw_state(connector)) {
15820 connector->base.dpms = DRM_MODE_DPMS_ON;
15821
15822 encoder = connector->encoder;
15823 connector->base.encoder = &encoder->base;
15824
15825 if (encoder->base.crtc &&
15826 encoder->base.crtc->state->active) {
15827 /*
15828 * This has to be done during hardware readout
15829 * because anything calling .crtc_disable may
15830 * rely on the connector_mask being accurate.
15831 */
15832 encoder->base.crtc->state->connector_mask |=
15833 1 << drm_connector_index(&connector->base);
15834 encoder->base.crtc->state->encoder_mask |=
15835 1 << drm_encoder_index(&encoder->base);
15836 }
15837
15838 } else {
15839 connector->base.dpms = DRM_MODE_DPMS_OFF;
15840 connector->base.encoder = NULL;
15841 }
15842 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15843 connector->base.base.id,
15844 connector->base.name,
15845 connector->base.encoder ? "enabled" : "disabled");
15846 }
15847
15848 for_each_intel_crtc(dev, crtc) {
15849 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15850
15851 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15852 if (crtc->base.state->active) {
15853 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15854 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15855 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15856
15857 /*
15858 * The initial mode needs to be set in order to keep
15859 * the atomic core happy. It wants a valid mode if the
15860 * crtc's enabled, so we do the above call.
15861 *
15862 * At this point some state updated by the connectors
15863 * in their ->detect() callback has not run yet, so
15864 * no recalculation can be done yet.
15865 *
15866 * Even if we could do a recalculation and modeset
15867 * right now it would cause a double modeset if
15868 * fbdev or userspace chooses a different initial mode.
15869 *
15870 * If that happens, someone indicated they wanted a
15871 * mode change, which means it's safe to do a full
15872 * recalculation.
15873 */
15874 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15875
15876 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15877 update_scanline_offset(crtc);
15878 }
15879 }
15880 }
15881
15882 /* Scan out the current hw modeset state,
15883 * and sanitizes it to the current state
15884 */
15885 static void
15886 intel_modeset_setup_hw_state(struct drm_device *dev)
15887 {
15888 struct drm_i915_private *dev_priv = dev->dev_private;
15889 enum pipe pipe;
15890 struct intel_crtc *crtc;
15891 struct intel_encoder *encoder;
15892 int i;
15893
15894 intel_modeset_readout_hw_state(dev);
15895
15896 /* HW state is read out, now we need to sanitize this mess. */
15897 for_each_intel_encoder(dev, encoder) {
15898 intel_sanitize_encoder(encoder);
15899 }
15900
15901 for_each_pipe(dev_priv, pipe) {
15902 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15903 intel_sanitize_crtc(crtc);
15904 intel_dump_pipe_config(crtc, crtc->config,
15905 "[setup_hw_state]");
15906 }
15907
15908 intel_modeset_update_connector_atomic_state(dev);
15909
15910 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15911 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15912
15913 if (!pll->on || pll->active)
15914 continue;
15915
15916 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15917
15918 pll->disable(dev_priv, pll);
15919 pll->on = false;
15920 }
15921
15922 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15923 vlv_wm_get_hw_state(dev);
15924 else if (IS_GEN9(dev))
15925 skl_wm_get_hw_state(dev);
15926 else if (HAS_PCH_SPLIT(dev))
15927 ilk_wm_get_hw_state(dev);
15928
15929 for_each_intel_crtc(dev, crtc) {
15930 unsigned long put_domains;
15931
15932 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15933 if (WARN_ON(put_domains))
15934 modeset_put_power_domains(dev_priv, put_domains);
15935 }
15936 intel_display_set_init_power(dev_priv, false);
15937 }
15938
15939 void intel_display_resume(struct drm_device *dev)
15940 {
15941 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15942 struct intel_connector *conn;
15943 struct intel_plane *plane;
15944 struct drm_crtc *crtc;
15945 int ret;
15946
15947 if (!state)
15948 return;
15949
15950 state->acquire_ctx = dev->mode_config.acquire_ctx;
15951
15952 /* preserve complete old state, including dpll */
15953 intel_atomic_get_shared_dpll_state(state);
15954
15955 for_each_crtc(dev, crtc) {
15956 struct drm_crtc_state *crtc_state =
15957 drm_atomic_get_crtc_state(state, crtc);
15958
15959 ret = PTR_ERR_OR_ZERO(crtc_state);
15960 if (ret)
15961 goto err;
15962
15963 /* force a restore */
15964 crtc_state->mode_changed = true;
15965 }
15966
15967 for_each_intel_plane(dev, plane) {
15968 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15969 if (ret)
15970 goto err;
15971 }
15972
15973 for_each_intel_connector(dev, conn) {
15974 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15975 if (ret)
15976 goto err;
15977 }
15978
15979 intel_modeset_setup_hw_state(dev);
15980
15981 i915_redisable_vga(dev);
15982 ret = drm_atomic_commit(state);
15983 if (!ret)
15984 return;
15985
15986 err:
15987 DRM_ERROR("Restoring old state failed with %i\n", ret);
15988 drm_atomic_state_free(state);
15989 }
15990
15991 void intel_modeset_gem_init(struct drm_device *dev)
15992 {
15993 struct drm_crtc *c;
15994 struct drm_i915_gem_object *obj;
15995 int ret;
15996
15997 mutex_lock(&dev->struct_mutex);
15998 intel_init_gt_powersave(dev);
15999 mutex_unlock(&dev->struct_mutex);
16000
16001 intel_modeset_init_hw(dev);
16002
16003 intel_setup_overlay(dev);
16004
16005 /*
16006 * Make sure any fbs we allocated at startup are properly
16007 * pinned & fenced. When we do the allocation it's too early
16008 * for this.
16009 */
16010 for_each_crtc(dev, c) {
16011 obj = intel_fb_obj(c->primary->fb);
16012 if (obj == NULL)
16013 continue;
16014
16015 mutex_lock(&dev->struct_mutex);
16016 ret = intel_pin_and_fence_fb_obj(c->primary,
16017 c->primary->fb,
16018 c->primary->state);
16019 mutex_unlock(&dev->struct_mutex);
16020 if (ret) {
16021 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16022 to_intel_crtc(c)->pipe);
16023 drm_framebuffer_unreference(c->primary->fb);
16024 c->primary->fb = NULL;
16025 c->primary->crtc = c->primary->state->crtc = NULL;
16026 update_state_fb(c->primary);
16027 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16028 }
16029 }
16030
16031 intel_backlight_register(dev);
16032 }
16033
16034 void intel_connector_unregister(struct intel_connector *intel_connector)
16035 {
16036 struct drm_connector *connector = &intel_connector->base;
16037
16038 intel_panel_destroy_backlight(connector);
16039 drm_connector_unregister(connector);
16040 }
16041
16042 void intel_modeset_cleanup(struct drm_device *dev)
16043 {
16044 struct drm_i915_private *dev_priv = dev->dev_private;
16045 struct intel_connector *connector;
16046
16047 intel_disable_gt_powersave(dev);
16048
16049 intel_backlight_unregister(dev);
16050
16051 /*
16052 * Interrupts and polling as the first thing to avoid creating havoc.
16053 * Too much stuff here (turning of connectors, ...) would
16054 * experience fancy races otherwise.
16055 */
16056 intel_irq_uninstall(dev_priv);
16057
16058 /*
16059 * Due to the hpd irq storm handling the hotplug work can re-arm the
16060 * poll handlers. Hence disable polling after hpd handling is shut down.
16061 */
16062 drm_kms_helper_poll_fini(dev);
16063
16064 intel_unregister_dsm_handler();
16065
16066 intel_fbc_disable(dev_priv);
16067
16068 /* flush any delayed tasks or pending work */
16069 flush_scheduled_work();
16070
16071 /* destroy the backlight and sysfs files before encoders/connectors */
16072 for_each_intel_connector(dev, connector)
16073 connector->unregister(connector);
16074
16075 drm_mode_config_cleanup(dev);
16076
16077 intel_cleanup_overlay(dev);
16078
16079 mutex_lock(&dev->struct_mutex);
16080 intel_cleanup_gt_powersave(dev);
16081 mutex_unlock(&dev->struct_mutex);
16082
16083 intel_teardown_gmbus(dev);
16084 }
16085
16086 /*
16087 * Return which encoder is currently attached for connector.
16088 */
16089 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16090 {
16091 return &intel_attached_encoder(connector)->base;
16092 }
16093
16094 void intel_connector_attach_encoder(struct intel_connector *connector,
16095 struct intel_encoder *encoder)
16096 {
16097 connector->encoder = encoder;
16098 drm_mode_connector_attach_encoder(&connector->base,
16099 &encoder->base);
16100 }
16101
16102 /*
16103 * set vga decode state - true == enable VGA decode
16104 */
16105 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16106 {
16107 struct drm_i915_private *dev_priv = dev->dev_private;
16108 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16109 u16 gmch_ctrl;
16110
16111 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16112 DRM_ERROR("failed to read control word\n");
16113 return -EIO;
16114 }
16115
16116 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16117 return 0;
16118
16119 if (state)
16120 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16121 else
16122 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16123
16124 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16125 DRM_ERROR("failed to write control word\n");
16126 return -EIO;
16127 }
16128
16129 return 0;
16130 }
16131
16132 struct intel_display_error_state {
16133
16134 u32 power_well_driver;
16135
16136 int num_transcoders;
16137
16138 struct intel_cursor_error_state {
16139 u32 control;
16140 u32 position;
16141 u32 base;
16142 u32 size;
16143 } cursor[I915_MAX_PIPES];
16144
16145 struct intel_pipe_error_state {
16146 bool power_domain_on;
16147 u32 source;
16148 u32 stat;
16149 } pipe[I915_MAX_PIPES];
16150
16151 struct intel_plane_error_state {
16152 u32 control;
16153 u32 stride;
16154 u32 size;
16155 u32 pos;
16156 u32 addr;
16157 u32 surface;
16158 u32 tile_offset;
16159 } plane[I915_MAX_PIPES];
16160
16161 struct intel_transcoder_error_state {
16162 bool power_domain_on;
16163 enum transcoder cpu_transcoder;
16164
16165 u32 conf;
16166
16167 u32 htotal;
16168 u32 hblank;
16169 u32 hsync;
16170 u32 vtotal;
16171 u32 vblank;
16172 u32 vsync;
16173 } transcoder[4];
16174 };
16175
16176 struct intel_display_error_state *
16177 intel_display_capture_error_state(struct drm_device *dev)
16178 {
16179 struct drm_i915_private *dev_priv = dev->dev_private;
16180 struct intel_display_error_state *error;
16181 int transcoders[] = {
16182 TRANSCODER_A,
16183 TRANSCODER_B,
16184 TRANSCODER_C,
16185 TRANSCODER_EDP,
16186 };
16187 int i;
16188
16189 if (INTEL_INFO(dev)->num_pipes == 0)
16190 return NULL;
16191
16192 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16193 if (error == NULL)
16194 return NULL;
16195
16196 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16197 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16198
16199 for_each_pipe(dev_priv, i) {
16200 error->pipe[i].power_domain_on =
16201 __intel_display_power_is_enabled(dev_priv,
16202 POWER_DOMAIN_PIPE(i));
16203 if (!error->pipe[i].power_domain_on)
16204 continue;
16205
16206 error->cursor[i].control = I915_READ(CURCNTR(i));
16207 error->cursor[i].position = I915_READ(CURPOS(i));
16208 error->cursor[i].base = I915_READ(CURBASE(i));
16209
16210 error->plane[i].control = I915_READ(DSPCNTR(i));
16211 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16212 if (INTEL_INFO(dev)->gen <= 3) {
16213 error->plane[i].size = I915_READ(DSPSIZE(i));
16214 error->plane[i].pos = I915_READ(DSPPOS(i));
16215 }
16216 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16217 error->plane[i].addr = I915_READ(DSPADDR(i));
16218 if (INTEL_INFO(dev)->gen >= 4) {
16219 error->plane[i].surface = I915_READ(DSPSURF(i));
16220 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16221 }
16222
16223 error->pipe[i].source = I915_READ(PIPESRC(i));
16224
16225 if (HAS_GMCH_DISPLAY(dev))
16226 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16227 }
16228
16229 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16230 if (HAS_DDI(dev_priv->dev))
16231 error->num_transcoders++; /* Account for eDP. */
16232
16233 for (i = 0; i < error->num_transcoders; i++) {
16234 enum transcoder cpu_transcoder = transcoders[i];
16235
16236 error->transcoder[i].power_domain_on =
16237 __intel_display_power_is_enabled(dev_priv,
16238 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16239 if (!error->transcoder[i].power_domain_on)
16240 continue;
16241
16242 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16243
16244 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16245 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16246 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16247 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16248 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16249 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16250 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16251 }
16252
16253 return error;
16254 }
16255
16256 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16257
16258 void
16259 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16260 struct drm_device *dev,
16261 struct intel_display_error_state *error)
16262 {
16263 struct drm_i915_private *dev_priv = dev->dev_private;
16264 int i;
16265
16266 if (!error)
16267 return;
16268
16269 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16270 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16271 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16272 error->power_well_driver);
16273 for_each_pipe(dev_priv, i) {
16274 err_printf(m, "Pipe [%d]:\n", i);
16275 err_printf(m, " Power: %s\n",
16276 onoff(error->pipe[i].power_domain_on));
16277 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16278 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16279
16280 err_printf(m, "Plane [%d]:\n", i);
16281 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16282 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16283 if (INTEL_INFO(dev)->gen <= 3) {
16284 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16285 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16286 }
16287 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16288 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16289 if (INTEL_INFO(dev)->gen >= 4) {
16290 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16291 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16292 }
16293
16294 err_printf(m, "Cursor [%d]:\n", i);
16295 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16296 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16297 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16298 }
16299
16300 for (i = 0; i < error->num_transcoders; i++) {
16301 err_printf(m, "CPU transcoder: %c\n",
16302 transcoder_name(error->transcoder[i].cpu_transcoder));
16303 err_printf(m, " Power: %s\n",
16304 onoff(error->transcoder[i].power_domain_on));
16305 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16306 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16307 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16308 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16309 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16310 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16311 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16312 }
16313 }
Linux kernel - Deliverables
This page took 0.379078 seconds and 5 git commands to generate.