drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181
 182         /* for each plane in the normal GTT view */
 183         struct {
 184                 unsigned int x, y;
 185         } normal[2];
 186         /* for each plane in the rotated GTT view */
 187         struct {
 188                 unsigned int x, y;
 189                 unsigned int pitch; /* pixels */
 190         } rotated[2];
 191 };
 192
 193 struct intel_fbdev {
 194         struct drm_fb_helper helper;
 195         struct intel_framebuffer *fb;
 196         struct i915_vma *vma;
 197         async_cookie_t cookie;
 198         int preferred_bpp;
 199 };
 200
 201 struct intel_encoder {
 202         struct drm_encoder base;
 203
 204         enum intel_output_type type;
 205         unsigned int cloneable;
 206         void (*hot_plug)(struct intel_encoder *);
 207         bool (*compute_config)(struct intel_encoder *,
 208                                struct intel_crtc_state *,
 209                                struct drm_connector_state *);
 210         void (*pre_pll_enable)(struct intel_encoder *,
 211                                struct intel_crtc_state *,
 212                                struct drm_connector_state *);
 213         void (*pre_enable)(struct intel_encoder *,
 214                            struct intel_crtc_state *,
 215                            struct drm_connector_state *);
 216         void (*enable)(struct intel_encoder *,
 217                        struct intel_crtc_state *,
 218                        struct drm_connector_state *);
 219         void (*disable)(struct intel_encoder *,
 220                         struct intel_crtc_state *,
 221                         struct drm_connector_state *);
 222         void (*post_disable)(struct intel_encoder *,
 223                              struct intel_crtc_state *,
 224                              struct drm_connector_state *);
 225         void (*post_pll_disable)(struct intel_encoder *,
 226                                  struct intel_crtc_state *,
 227                                  struct drm_connector_state *);
 228         /* Read out the current hw state of this connector, returning true if
 229          * the encoder is active. If the encoder is enabled it also set the pipe
 230          * it is connected to in the pipe parameter. */
 231         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 232         /* Reconstructs the equivalent mode flags for the current hardware
 233          * state. This must be called _after_ display->get_pipe_config has
 234          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 235          * be set correctly before calling this function. */
 236         void (*get_config)(struct intel_encoder *,
 237                            struct intel_crtc_state *pipe_config);
 238         /*
 239          * Called during system suspend after all pending requests for the
 240          * encoder are flushed (for example for DP AUX transactions) and
 241          * device interrupts are disabled.
 242          */
 243         void (*suspend)(struct intel_encoder *);
 244         int crtc_mask;
 245         enum hpd_pin hpd_pin;
 246 };
 247
 248 struct intel_panel {
 249         struct drm_display_mode *fixed_mode;
 250         struct drm_display_mode *downclock_mode;
 251         int fitting_mode;
 252
 253         /* backlight */
 254         struct {
 255                 bool present;
 256                 u32 level;
 257                 u32 min;
 258                 u32 max;
 259                 bool enabled;
 260                 bool combination_mode;  /* gen 2/4 only */
 261                 bool active_low_pwm;
 262
 263                 /* PWM chip */
 264                 bool util_pin_active_low;       /* bxt+ */
 265                 u8 controller;          /* bxt+ only */
 266                 struct pwm_device *pwm;
 267
 268                 struct backlight_device *device;
 269
 270                 /* Connector and platform specific backlight functions */
 271                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 272                 uint32_t (*get)(struct intel_connector *connector);
 273                 void (*set)(struct intel_connector *connector, uint32_t level);
 274                 void (*disable)(struct intel_connector *connector);
 275                 void (*enable)(struct intel_connector *connector);
 276                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 277                                       uint32_t hz);
 278                 void (*power)(struct intel_connector *, bool enable);
 279         } backlight;
 280 };
 281
 282 struct intel_connector {
 283         struct drm_connector base;
 284         /*
 285          * The fixed encoder this connector is connected to.
 286          */
 287         struct intel_encoder *encoder;
 288
 289         /* Reads out the current hw, returning true if the connector is enabled
 290          * and active (i.e. dpms ON state). */
 291         bool (*get_hw_state)(struct intel_connector *);
 292
 293         /* Panel info for eDP and LVDS */
 294         struct intel_panel panel;
 295
 296         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 297         struct edid *edid;
 298         struct edid *detect_edid;
 299
 300         /* since POLL and HPD connectors may use the same HPD line keep the native
 301            state of connector->polled in case hotplug storm detection changes it */
 302         u8 polled;
 303
 304         void *port; /* store this opaque as its illegal to dereference it */
 305
 306         struct intel_dp *mst_port;
 307 };
 308
 309 struct dpll {
 310         /* given values */
 311         int n;
 312         int m1, m2;
 313         int p1, p2;
 314         /* derived values */
 315         int     dot;
 316         int     vco;
 317         int     m;
 318         int     p;
 319 };
 320
 321 struct intel_atomic_state {
 322         struct drm_atomic_state base;
 323
 324         unsigned int cdclk;
 325
 326         /*
 327          * Calculated device cdclk, can be different from cdclk
 328          * only when all crtc's are DPMS off.
 329          */
 330         unsigned int dev_cdclk;
 331
 332         bool dpll_set, modeset;
 333
 334         /*
 335          * Does this transaction change the pipes that are active?  This mask
 336          * tracks which CRTC's have changed their active state at the end of
 337          * the transaction (not counting the temporary disable during modesets).
 338          * This mask should only be non-zero when intel_state->modeset is true,
 339          * but the converse is not necessarily true; simply changing a mode may
 340          * not flip the final active status of any CRTC's
 341          */
 342         unsigned int active_pipe_changes;
 343
 344         unsigned int active_crtcs;
 345         unsigned int min_pixclk[I915_MAX_PIPES];
 346
 347         /* SKL/KBL Only */
 348         unsigned int cdclk_pll_vco;
 349
 350         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 351
 352         /*
 353          * Current watermarks can't be trusted during hardware readout, so
 354          * don't bother calculating intermediate watermarks.
 355          */
 356         bool skip_intermediate_wm;
 357
 358         /* Gen9+ only */
 359         struct skl_wm_values wm_results;
 360 };
 361
 362 struct intel_plane_state {
 363         struct drm_plane_state base;
 364         struct drm_rect clip;
 365
 366         struct {
 367                 u32 offset;
 368                 int x, y;
 369         } main;
 370         struct {
 371                 u32 offset;
 372                 int x, y;
 373         } aux;
 374
 375         /*
 376          * scaler_id
 377          *    = -1 : not using a scaler
 378          *    >=  0 : using a scalers
 379          *
 380          * plane requiring a scaler:
 381          *   - During check_plane, its bit is set in
 382          *     crtc_state->scaler_state.scaler_users by calling helper function
 383          *     update_scaler_plane.
 384          *   - scaler_id indicates the scaler it got assigned.
 385          *
 386          * plane doesn't require a scaler:
 387          *   - this can happen when scaling is no more required or plane simply
 388          *     got disabled.
 389          *   - During check_plane, corresponding bit is reset in
 390          *     crtc_state->scaler_state.scaler_users by calling helper function
 391          *     update_scaler_plane.
 392          */
 393         int scaler_id;
 394
 395         struct drm_intel_sprite_colorkey ckey;
 396
 397         /* async flip related structures */
 398         struct drm_i915_gem_request *wait_req;
 399 };
 400
 401 struct intel_initial_plane_config {
 402         struct intel_framebuffer *fb;
 403         unsigned int tiling;
 404         int size;
 405         u32 base;
 406 };
 407
 408 #define SKL_MIN_SRC_W 8
 409 #define SKL_MAX_SRC_W 4096
 410 #define SKL_MIN_SRC_H 8
 411 #define SKL_MAX_SRC_H 4096
 412 #define SKL_MIN_DST_W 8
 413 #define SKL_MAX_DST_W 4096
 414 #define SKL_MIN_DST_H 8
 415 #define SKL_MAX_DST_H 4096
 416
 417 struct intel_scaler {
 418         int in_use;
 419         uint32_t mode;
 420 };
 421
 422 struct intel_crtc_scaler_state {
 423 #define SKL_NUM_SCALERS 2
 424         struct intel_scaler scalers[SKL_NUM_SCALERS];
 425
 426         /*
 427          * scaler_users: keeps track of users requesting scalers on this crtc.
 428          *
 429          *     If a bit is set, a user is using a scaler.
 430          *     Here user can be a plane or crtc as defined below:
 431          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 432          *       bit 31    - crtc
 433          *
 434          * Instead of creating a new index to cover planes and crtc, using
 435          * existing drm_plane_index for planes which is well less than 31
 436          * planes and bit 31 for crtc. This should be fine to cover all
 437          * our platforms.
 438          *
 439          * intel_atomic_setup_scalers will setup available scalers to users
 440          * requesting scalers. It will gracefully fail if request exceeds
 441          * avilability.
 442          */
 443 #define SKL_CRTC_INDEX 31
 444         unsigned scaler_users;
 445
 446         /* scaler used by crtc for panel fitting purpose */
 447         int scaler_id;
 448 };
 449
 450 /* drm_mode->private_flags */
 451 #define I915_MODE_FLAG_INHERITED 1
 452
 453 struct intel_pipe_wm {
 454         struct intel_wm_level wm[5];
 455         struct intel_wm_level raw_wm[5];
 456         uint32_t linetime;
 457         bool fbc_wm_enabled;
 458         bool pipe_enabled;
 459         bool sprites_enabled;
 460         bool sprites_scaled;
 461 };
 462
 463 struct skl_pipe_wm {
 464         struct skl_wm_level wm[8];
 465         struct skl_wm_level trans_wm;
 466         uint32_t linetime;
 467 };
 468
 469 struct intel_crtc_wm_state {
 470         union {
 471                 struct {
 472                         /*
 473                          * Intermediate watermarks; these can be
 474                          * programmed immediately since they satisfy
 475                          * both the current configuration we're
 476                          * switching away from and the new
 477                          * configuration we're switching to.
 478                          */
 479                         struct intel_pipe_wm intermediate;
 480
 481                         /*
 482                          * Optimal watermarks, programmed post-vblank
 483                          * when this state is committed.
 484                          */
 485                         struct intel_pipe_wm optimal;
 486                 } ilk;
 487
 488                 struct {
 489                         /* gen9+ only needs 1-step wm programming */
 490                         struct skl_pipe_wm optimal;
 491
 492                         /* cached plane data rate */
 493                         unsigned plane_data_rate[I915_MAX_PLANES];
 494                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 495
 496                         /* minimum block allocation */
 497                         uint16_t minimum_blocks[I915_MAX_PLANES];
 498                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 499                 } skl;
 500         };
 501
 502         /*
 503          * Platforms with two-step watermark programming will need to
 504          * update watermark programming post-vblank to switch from the
 505          * safe intermediate watermarks to the optimal final
 506          * watermarks.
 507          */
 508         bool need_postvbl_update;
 509 };
 510
 511 struct intel_crtc_state {
 512         struct drm_crtc_state base;
 513
 514         /**
 515          * quirks - bitfield with hw state readout quirks
 516          *
 517          * For various reasons the hw state readout code might not be able to
 518          * completely faithfully read out the current state. These cases are
 519          * tracked with quirk flags so that fastboot and state checker can act
 520          * accordingly.
 521          */
 522 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 523         unsigned long quirks;
 524
 525         unsigned fb_bits; /* framebuffers to flip */
 526         bool update_pipe; /* can a fast modeset be performed? */
 527         bool disable_cxsr;
 528         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 529         bool fb_changed; /* fb on any of the planes is changed */
 530
 531         /* Pipe source size (ie. panel fitter input size)
 532          * All planes will be positioned inside this space,
 533          * and get clipped at the edges. */
 534         int pipe_src_w, pipe_src_h;
 535
 536         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 537          * between pch encoders and cpu encoders. */
 538         bool has_pch_encoder;
 539
 540         /* Are we sending infoframes on the attached port */
 541         bool has_infoframe;
 542
 543         /* CPU Transcoder for the pipe. Currently this can only differ from the
 544          * pipe on Haswell and later (where we have a special eDP transcoder)
 545          * and Broxton (where we have special DSI transcoders). */
 546         enum transcoder cpu_transcoder;
 547
 548         /*
 549          * Use reduced/limited/broadcast rbg range, compressing from the full
 550          * range fed into the crtcs.
 551          */
 552         bool limited_color_range;
 553
 554         /* Bitmask of encoder types (enum intel_output_type)
 555          * driven by the pipe.
 556          */
 557         unsigned int output_types;
 558
 559         /* Whether we should send NULL infoframes. Required for audio. */
 560         bool has_hdmi_sink;
 561
 562         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 563          * has_dp_encoder is set. */
 564         bool has_audio;
 565
 566         /*
 567          * Enable dithering, used when the selected pipe bpp doesn't match the
 568          * plane bpp.
 569          */
 570         bool dither;
 571
 572         /* Controls for the clock computation, to override various stages. */
 573         bool clock_set;
 574
 575         /* SDVO TV has a bunch of special case. To make multifunction encoders
 576          * work correctly, we need to track this at runtime.*/
 577         bool sdvo_tv_clock;
 578
 579         /*
 580          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 581          * required. This is set in the 2nd loop of calling encoder's
 582          * ->compute_config if the first pick doesn't work out.
 583          */
 584         bool bw_constrained;
 585
 586         /* Settings for the intel dpll used on pretty much everything but
 587          * haswell. */
 588         struct dpll dpll;
 589
 590         /* Selected dpll when shared or NULL. */
 591         struct intel_shared_dpll *shared_dpll;
 592
 593         /* Actual register state of the dpll, for shared dpll cross-checking. */
 594         struct intel_dpll_hw_state dpll_hw_state;
 595
 596         /* DSI PLL registers */
 597         struct {
 598                 u32 ctrl, div;
 599         } dsi_pll;
 600
 601         int pipe_bpp;
 602         struct intel_link_m_n dp_m_n;
 603
 604         /* m2_n2 for eDP downclock */
 605         struct intel_link_m_n dp_m2_n2;
 606         bool has_drrs;
 607
 608         /*
 609          * Frequence the dpll for the port should run at. Differs from the
 610          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 611          * already multiplied by pixel_multiplier.
 612          */
 613         int port_clock;
 614
 615         /* Used by SDVO (and if we ever fix it, HDMI). */
 616         unsigned pixel_multiplier;
 617
 618         uint8_t lane_count;
 619
 620         /*
 621          * Used by platforms having DP/HDMI PHY with programmable lane
 622          * latency optimization.
 623          */
 624         uint8_t lane_lat_optim_mask;
 625
 626         /* Panel fitter controls for gen2-gen4 + VLV */
 627         struct {
 628                 u32 control;
 629                 u32 pgm_ratios;
 630                 u32 lvds_border_bits;
 631         } gmch_pfit;
 632
 633         /* Panel fitter placement and size for Ironlake+ */
 634         struct {
 635                 u32 pos;
 636                 u32 size;
 637                 bool enabled;
 638                 bool force_thru;
 639         } pch_pfit;
 640
 641         /* FDI configuration, only valid if has_pch_encoder is set. */
 642         int fdi_lanes;
 643         struct intel_link_m_n fdi_m_n;
 644
 645         bool ips_enabled;
 646
 647         bool enable_fbc;
 648
 649         bool double_wide;
 650
 651         bool dp_encoder_is_mst;
 652         int pbn;
 653
 654         struct intel_crtc_scaler_state scaler_state;
 655
 656         /* w/a for waiting 2 vblanks during crtc enable */
 657         enum pipe hsw_workaround_pipe;
 658
 659         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 660         bool disable_lp_wm;
 661
 662         struct intel_crtc_wm_state wm;
 663
 664         /* Gamma mode programmed on the pipe */
 665         uint32_t gamma_mode;
 666 };
 667
 668 struct vlv_wm_state {
 669         struct vlv_pipe_wm wm[3];
 670         struct vlv_sr_wm sr[3];
 671         uint8_t num_active_planes;
 672         uint8_t num_levels;
 673         uint8_t level;
 674         bool cxsr;
 675 };
 676
 677 struct intel_crtc {
 678         struct drm_crtc base;
 679         enum pipe pipe;
 680         enum plane plane;
 681         u8 lut_r[256], lut_g[256], lut_b[256];
 682         /*
 683          * Whether the crtc and the connected output pipeline is active. Implies
 684          * that crtc->enabled is set, i.e. the current mode configuration has
 685          * some outputs connected to this crtc.
 686          */
 687         bool active;
 688         unsigned long enabled_power_domains;
 689         bool lowfreq_avail;
 690         struct intel_overlay *overlay;
 691         struct intel_flip_work *flip_work;
 692
 693         atomic_t unpin_work_count;
 694
 695         /* Display surface base address adjustement for pageflips. Note that on
 696          * gen4+ this only adjusts up to a tile, offsets within a tile are
 697          * handled in the hw itself (with the TILEOFF register). */
 698         u32 dspaddr_offset;
 699         int adjusted_x;
 700         int adjusted_y;
 701
 702         uint32_t cursor_addr;
 703         uint32_t cursor_cntl;
 704         uint32_t cursor_size;
 705         uint32_t cursor_base;
 706
 707         struct intel_crtc_state *config;
 708
 709         /* global reset count when the last flip was submitted */
 710         unsigned int reset_count;
 711
 712         /* Access to these should be protected by dev_priv->irq_lock. */
 713         bool cpu_fifo_underrun_disabled;
 714         bool pch_fifo_underrun_disabled;
 715
 716         /* per-pipe watermark state */
 717         struct {
 718                 /* watermarks currently being used  */
 719                 union {
 720                         struct intel_pipe_wm ilk;
 721                         struct skl_pipe_wm skl;
 722                 } active;
 723
 724                 /* allow CxSR on this pipe */
 725                 bool cxsr_allowed;
 726         } wm;
 727
 728         int scanline_offset;
 729
 730         struct {
 731                 unsigned start_vbl_count;
 732                 ktime_t start_vbl_time;
 733                 int min_vbl, max_vbl;
 734                 int scanline_start;
 735         } debug;
 736
 737         /* scalers available on this crtc */
 738         int num_scalers;
 739
 740         struct vlv_wm_state wm_state;
 741 };
 742
 743 struct intel_plane_wm_parameters {
 744         uint32_t horiz_pixels;
 745         uint32_t vert_pixels;
 746         /*
 747          *   For packed pixel formats:
 748          *     bytes_per_pixel - holds bytes per pixel
 749          *   For planar pixel formats:
 750          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 751          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 752          */
 753         uint8_t bytes_per_pixel;
 754         uint8_t y_bytes_per_pixel;
 755         bool enabled;
 756         bool scaled;
 757         u64 tiling;
 758         unsigned int rotation;
 759         uint16_t fifo_size;
 760 };
 761
 762 struct intel_plane {
 763         struct drm_plane base;
 764         int plane;
 765         enum pipe pipe;
 766         bool can_scale;
 767         int max_downscale;
 768         uint32_t frontbuffer_bit;
 769
 770         /* Since we need to change the watermarks before/after
 771          * enabling/disabling the planes, we need to store the parameters here
 772          * as the other pieces of the struct may not reflect the values we want
 773          * for the watermark calculations. Currently only Haswell uses this.
 774          */
 775         struct intel_plane_wm_parameters wm;
 776
 777         /*
 778          * NOTE: Do not place new plane state fields here (e.g., when adding
 779          * new plane properties).  New runtime state should now be placed in
 780          * the intel_plane_state structure and accessed via plane_state.
 781          */
 782
 783         void (*update_plane)(struct drm_plane *plane,
 784                              const struct intel_crtc_state *crtc_state,
 785                              const struct intel_plane_state *plane_state);
 786         void (*disable_plane)(struct drm_plane *plane,
 787                               struct drm_crtc *crtc);
 788         int (*check_plane)(struct drm_plane *plane,
 789                            struct intel_crtc_state *crtc_state,
 790                            struct intel_plane_state *state);
 791 };
 792
 793 struct intel_watermark_params {
 794         unsigned long fifo_size;
 795         unsigned long max_wm;
 796         unsigned long default_wm;
 797         unsigned long guard_size;
 798         unsigned long cacheline_size;
 799 };
 800
 801 struct cxsr_latency {
 802         int is_desktop;
 803         int is_ddr3;
 804         unsigned long fsb_freq;
 805         unsigned long mem_freq;
 806         unsigned long display_sr;
 807         unsigned long display_hpll_disable;
 808         unsigned long cursor_sr;
 809         unsigned long cursor_hpll_disable;
 810 };
 811
 812 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 813 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 814 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 815 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 816 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 817 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 818 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 819 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 820 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 821
 822 struct intel_hdmi {
 823         i915_reg_t hdmi_reg;
 824         int ddc_bus;
 825         struct {
 826                 enum drm_dp_dual_mode_type type;
 827                 int max_tmds_clock;
 828         } dp_dual_mode;
 829         bool limited_color_range;
 830         bool color_range_auto;
 831         bool has_hdmi_sink;
 832         bool has_audio;
 833         enum hdmi_force_audio force_audio;
 834         bool rgb_quant_range_selectable;
 835         enum hdmi_picture_aspect aspect_ratio;
 836         struct intel_connector *attached_connector;
 837         void (*write_infoframe)(struct drm_encoder *encoder,
 838                                 enum hdmi_infoframe_type type,
 839                                 const void *frame, ssize_t len);
 840         void (*set_infoframes)(struct drm_encoder *encoder,
 841                                bool enable,
 842                                const struct drm_display_mode *adjusted_mode);
 843         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 844                                   const struct intel_crtc_state *pipe_config);
 845 };
 846
 847 struct intel_dp_mst_encoder;
 848 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 849
 850 /*
 851  * enum link_m_n_set:
 852  *      When platform provides two set of M_N registers for dp, we can
 853  *      program them and switch between them incase of DRRS.
 854  *      But When only one such register is provided, we have to program the
 855  *      required divider value on that registers itself based on the DRRS state.
 856  *
 857  * M1_N1        : Program dp_m_n on M1_N1 registers
 858  *                        dp_m2_n2 on M2_N2 registers (If supported)
 859  *
 860  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 861  *                        M2_N2 registers are not supported
 862  */
 863
 864 enum link_m_n_set {
 865         /* Sets the m1_n1 and m2_n2 */
 866         M1_N1 = 0,
 867         M2_N2
 868 };
 869
 870 struct intel_dp {
 871         i915_reg_t output_reg;
 872         i915_reg_t aux_ch_ctl_reg;
 873         i915_reg_t aux_ch_data_reg[5];
 874         uint32_t DP;
 875         int link_rate;
 876         uint8_t lane_count;
 877         uint8_t sink_count;
 878         bool link_mst;
 879         bool has_audio;
 880         bool detect_done;
 881         bool channel_eq_status;
 882         enum hdmi_force_audio force_audio;
 883         bool limited_color_range;
 884         bool color_range_auto;
 885         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 886         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 887         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 888         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 889         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 890         uint8_t num_sink_rates;
 891         int sink_rates[DP_MAX_SUPPORTED_RATES];
 892         struct drm_dp_aux aux;
 893         uint8_t train_set[4];
 894         int panel_power_up_delay;
 895         int panel_power_down_delay;
 896         int panel_power_cycle_delay;
 897         int backlight_on_delay;
 898         int backlight_off_delay;
 899         struct delayed_work panel_vdd_work;
 900         bool want_panel_vdd;
 901         unsigned long last_power_on;
 902         unsigned long last_backlight_off;
 903         ktime_t panel_power_off_time;
 904
 905         struct notifier_block edp_notifier;
 906
 907         /*
 908          * Pipe whose power sequencer is currently locked into
 909          * this port. Only relevant on VLV/CHV.
 910          */
 911         enum pipe pps_pipe;
 912         /*
 913          * Set if the sequencer may be reset due to a power transition,
 914          * requiring a reinitialization. Only relevant on BXT.
 915          */
 916         bool pps_reset;
 917         struct edp_power_seq pps_delays;
 918
 919         bool can_mst; /* this port supports mst */
 920         bool is_mst;
 921         int active_mst_links;
 922         /* connector directly attached - won't be use for modeset in mst world */
 923         struct intel_connector *attached_connector;
 924
 925         /* mst connector list */
 926         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 927         struct drm_dp_mst_topology_mgr mst_mgr;
 928
 929         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 930         /*
 931          * This function returns the value we have to program the AUX_CTL
 932          * register with to kick off an AUX transaction.
 933          */
 934         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 935                                      bool has_aux_irq,
 936                                      int send_bytes,
 937                                      uint32_t aux_clock_divider);
 938
 939         /* This is called before a link training is starterd */
 940         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 941
 942         /* Displayport compliance testing */
 943         unsigned long compliance_test_type;
 944         unsigned long compliance_test_data;
 945         bool compliance_test_active;
 946 };
 947
 948 struct intel_digital_port {
 949         struct intel_encoder base;
 950         enum port port;
 951         u32 saved_port_bits;
 952         struct intel_dp dp;
 953         struct intel_hdmi hdmi;
 954         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 955         bool release_cl2_override;
 956         uint8_t max_lanes;
 957         /* for communication with audio component; protected by av_mutex */
 958         const struct drm_connector *audio_connector;
 959 };
 960
 961 struct intel_dp_mst_encoder {
 962         struct intel_encoder base;
 963         enum pipe pipe;
 964         struct intel_digital_port *primary;
 965         struct intel_connector *connector;
 966 };
 967
 968 static inline enum dpio_channel
 969 vlv_dport_to_channel(struct intel_digital_port *dport)
 970 {
 971         switch (dport->port) {
 972         case PORT_B:
 973         case PORT_D:
 974                 return DPIO_CH0;
 975         case PORT_C:
 976                 return DPIO_CH1;
 977         default:
 978                 BUG();
 979         }
 980 }
 981
 982 static inline enum dpio_phy
 983 vlv_dport_to_phy(struct intel_digital_port *dport)
 984 {
 985         switch (dport->port) {
 986         case PORT_B:
 987         case PORT_C:
 988                 return DPIO_PHY0;
 989         case PORT_D:
 990                 return DPIO_PHY1;
 991         default:
 992                 BUG();
 993         }
 994 }
 995
 996 static inline enum dpio_channel
 997 vlv_pipe_to_channel(enum pipe pipe)
 998 {
 999         switch (pipe) {
1000         case PIPE_A:
1001         case PIPE_C:
1002                 return DPIO_CH0;
1003         case PIPE_B:
1004                 return DPIO_CH1;
1005         default:
1006                 BUG();
1007         }
1008 }
1009
1010 static inline struct drm_crtc *
1011 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(dev);
1014         return dev_priv->pipe_to_crtc_mapping[pipe];
1015 }
1016
1017 static inline struct drm_crtc *
1018 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(dev);
1021         return dev_priv->plane_to_crtc_mapping[plane];
1022 }
1023
1024 struct intel_flip_work {
1025         struct work_struct unpin_work;
1026         struct work_struct mmio_work;
1027
1028         struct drm_crtc *crtc;
1029         struct drm_framebuffer *old_fb;
1030         struct drm_i915_gem_object *pending_flip_obj;
1031         struct drm_pending_vblank_event *event;
1032         atomic_t pending;
1033         u32 flip_count;
1034         u32 gtt_offset;
1035         struct drm_i915_gem_request *flip_queued_req;
1036         u32 flip_queued_vblank;
1037         u32 flip_ready_vblank;
1038         unsigned int rotation;
1039 };
1040
1041 struct intel_load_detect_pipe {
1042         struct drm_atomic_state *restore_state;
1043 };
1044
1045 static inline struct intel_encoder *
1046 intel_attached_encoder(struct drm_connector *connector)
1047 {
1048         return to_intel_connector(connector)->encoder;
1049 }
1050
1051 static inline struct intel_digital_port *
1052 enc_to_dig_port(struct drm_encoder *encoder)
1053 {
1054         return container_of(encoder, struct intel_digital_port, base.base);
1055 }
1056
1057 static inline struct intel_dp_mst_encoder *
1058 enc_to_mst(struct drm_encoder *encoder)
1059 {
1060         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1061 }
1062
1063 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1064 {
1065         return &enc_to_dig_port(encoder)->dp;
1066 }
1067
1068 static inline struct intel_digital_port *
1069 dp_to_dig_port(struct intel_dp *intel_dp)
1070 {
1071         return container_of(intel_dp, struct intel_digital_port, dp);
1072 }
1073
1074 static inline struct intel_digital_port *
1075 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1076 {
1077         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1078 }
1079
1080 /*
1081  * Returns the number of planes for this pipe, ie the number of sprites + 1
1082  * (primary plane). This doesn't count the cursor plane then.
1083  */
1084 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1085 {
1086         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1087 }
1088
1089 /* intel_fifo_underrun.c */
1090 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1091                                            enum pipe pipe, bool enable);
1092 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1093                                            enum transcoder pch_transcoder,
1094                                            bool enable);
1095 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1096                                          enum pipe pipe);
1097 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1098                                          enum transcoder pch_transcoder);
1099 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1100 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1101
1102 /* i915_irq.c */
1103 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1104 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1105 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1106 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1107 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1108 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1109 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1110 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1111 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1112 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1113 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1114 {
1115         /*
1116          * We only use drm_irq_uninstall() at unload and VT switch, so
1117          * this is the only thing we need to check.
1118          */
1119         return dev_priv->pm.irqs_enabled;
1120 }
1121
1122 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1123 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1124                                      unsigned int pipe_mask);
1125 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1126                                      unsigned int pipe_mask);
1127
1128 /* intel_crt.c */
1129 void intel_crt_init(struct drm_device *dev);
1130 void intel_crt_reset(struct drm_encoder *encoder);
1131
1132 /* intel_ddi.c */
1133 void intel_ddi_clk_select(struct intel_encoder *encoder,
1134                           struct intel_shared_dpll *pll);
1135 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1136                                 struct intel_crtc_state *old_crtc_state,
1137                                 struct drm_connector_state *old_conn_state);
1138 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1139 void hsw_fdi_link_train(struct drm_crtc *crtc);
1140 void intel_ddi_init(struct drm_device *dev, enum port port);
1141 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1142 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1143 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1144 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1145                                        enum transcoder cpu_transcoder);
1146 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1147 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1148 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1149                           struct intel_crtc_state *crtc_state);
1150 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1151 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1152 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1153 void intel_ddi_get_config(struct intel_encoder *encoder,
1154                           struct intel_crtc_state *pipe_config);
1155 struct intel_encoder *
1156 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1157
1158 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1159 void intel_ddi_clock_get(struct intel_encoder *encoder,
1160                          struct intel_crtc_state *pipe_config);
1161 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1162 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1163 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1164                                                   int clock);
1165 unsigned int intel_fb_align_height(struct drm_device *dev,
1166                                    unsigned int height,
1167                                    uint32_t pixel_format,
1168                                    uint64_t fb_format_modifier);
1169 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1170                               uint64_t fb_modifier, uint32_t pixel_format);
1171
1172 /* intel_audio.c */
1173 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1174 void intel_audio_codec_enable(struct intel_encoder *encoder);
1175 void intel_audio_codec_disable(struct intel_encoder *encoder);
1176 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1177 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1178
1179 /* intel_display.c */
1180 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1181 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1182 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1183                       const char *name, u32 reg, int ref_freq);
1184 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1185 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1186 extern const struct drm_plane_funcs intel_plane_funcs;
1187 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1188 unsigned int intel_fb_xy_to_linear(int x, int y,
1189                                    const struct intel_plane_state *state,
1190                                    int plane);
1191 void intel_add_fb_offsets(int *x, int *y,
1192                           const struct intel_plane_state *state, int plane);
1193 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1194 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1195 void intel_mark_busy(struct drm_i915_private *dev_priv);
1196 void intel_mark_idle(struct drm_i915_private *dev_priv);
1197 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1198 int intel_display_suspend(struct drm_device *dev);
1199 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1200 void intel_encoder_destroy(struct drm_encoder *encoder);
1201 int intel_connector_init(struct intel_connector *);
1202 struct intel_connector *intel_connector_alloc(void);
1203 bool intel_connector_get_hw_state(struct intel_connector *connector);
1204 void intel_connector_attach_encoder(struct intel_connector *connector,
1205                                     struct intel_encoder *encoder);
1206 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1207                                              struct drm_crtc *crtc);
1208 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1209 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1210                                 struct drm_file *file_priv);
1211 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1212                                              enum pipe pipe);
1213 static inline bool
1214 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1215                     enum intel_output_type type)
1216 {
1217         return crtc_state->output_types & (1 << type);
1218 }
1219 static inline bool
1220 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1221 {
1222         return crtc_state->output_types &
1223                 ((1 << INTEL_OUTPUT_DP) |
1224                  (1 << INTEL_OUTPUT_DP_MST) |
1225                  (1 << INTEL_OUTPUT_EDP));
1226 }
1227 static inline void
1228 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1229 {
1230         drm_wait_one_vblank(dev, pipe);
1231 }
1232 static inline void
1233 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1234 {
1235         const struct intel_crtc *crtc =
1236                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1237
1238         if (crtc->active)
1239                 intel_wait_for_vblank(dev, pipe);
1240 }
1241
1242 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1243
1244 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1245 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1246                          struct intel_digital_port *dport,
1247                          unsigned int expected_mask);
1248 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1249                                 struct drm_display_mode *mode,
1250                                 struct intel_load_detect_pipe *old,
1251                                 struct drm_modeset_acquire_ctx *ctx);
1252 void intel_release_load_detect_pipe(struct drm_connector *connector,
1253                                     struct intel_load_detect_pipe *old,
1254                                     struct drm_modeset_acquire_ctx *ctx);
1255 struct i915_vma *
1256 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1257 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1258 struct drm_framebuffer *
1259 __intel_framebuffer_create(struct drm_device *dev,
1260                            struct drm_mode_fb_cmd2 *mode_cmd,
1261                            struct drm_i915_gem_object *obj);
1262 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1263 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1264 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1265 int intel_prepare_plane_fb(struct drm_plane *plane,
1266                            struct drm_plane_state *new_state);
1267 void intel_cleanup_plane_fb(struct drm_plane *plane,
1268                             struct drm_plane_state *old_state);
1269 int intel_plane_atomic_get_property(struct drm_plane *plane,
1270                                     const struct drm_plane_state *state,
1271                                     struct drm_property *property,
1272                                     uint64_t *val);
1273 int intel_plane_atomic_set_property(struct drm_plane *plane,
1274                                     struct drm_plane_state *state,
1275                                     struct drm_property *property,
1276                                     uint64_t val);
1277 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1278                                     struct drm_plane_state *plane_state);
1279
1280 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1281                                uint64_t fb_modifier, unsigned int cpp);
1282
1283 static inline bool
1284 intel_rotation_90_or_270(unsigned int rotation)
1285 {
1286         return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1287 }
1288
1289 void intel_create_rotation_property(struct drm_device *dev,
1290                                         struct intel_plane *plane);
1291
1292 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe);
1294
1295 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1296                      const struct dpll *dpll);
1297 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1298 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1299
1300 /* modesetting asserts */
1301 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1302                            enum pipe pipe);
1303 void assert_pll(struct drm_i915_private *dev_priv,
1304                 enum pipe pipe, bool state);
1305 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1306 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1307 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1308 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1309 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1310 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1311                        enum pipe pipe, bool state);
1312 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1313 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1314 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1315 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1316 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1317 u32 intel_compute_tile_offset(int *x, int *y,
1318                               const struct intel_plane_state *state, int plane);
1319 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1320 void intel_finish_reset(struct drm_i915_private *dev_priv);
1321 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1322 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1323 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1324 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1326 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1327 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1328                             enum dpio_phy phy);
1329 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1330                               enum dpio_phy phy);
1331 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1332 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1333 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1334 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1335 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1336 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1337 unsigned int skl_cdclk_get_vco(unsigned int freq);
1338 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1339 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1340 void intel_dp_get_m_n(struct intel_crtc *crtc,
1341                       struct intel_crtc_state *pipe_config);
1342 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1343 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1344 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1345                         struct dpll *best_clock);
1346 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1347
1348 bool intel_crtc_active(struct drm_crtc *crtc);
1349 void hsw_enable_ips(struct intel_crtc *crtc);
1350 void hsw_disable_ips(struct intel_crtc *crtc);
1351 enum intel_display_power_domain
1352 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1353 enum intel_display_power_domain
1354 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1355 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1356                                  struct intel_crtc_state *pipe_config);
1357
1358 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1359 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1360
1361 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1362
1363 u32 skl_plane_ctl_format(uint32_t pixel_format);
1364 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1365 u32 skl_plane_ctl_rotation(unsigned int rotation);
1366 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1367                      unsigned int rotation);
1368 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1369
1370 /* intel_csr.c */
1371 void intel_csr_ucode_init(struct drm_i915_private *);
1372 void intel_csr_load_program(struct drm_i915_private *);
1373 void intel_csr_ucode_fini(struct drm_i915_private *);
1374 void intel_csr_ucode_suspend(struct drm_i915_private *);
1375 void intel_csr_ucode_resume(struct drm_i915_private *);
1376
1377 /* intel_dp.c */
1378 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1379 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1380                              struct intel_connector *intel_connector);
1381 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1382                               int link_rate, uint8_t lane_count,
1383                               bool link_mst);
1384 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1385 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1386 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1387 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1388 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1389 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1390 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1391 bool intel_dp_compute_config(struct intel_encoder *encoder,
1392                              struct intel_crtc_state *pipe_config,
1393                              struct drm_connector_state *conn_state);
1394 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1395 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1396                                   bool long_hpd);
1397 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1398 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1399 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1400 void intel_edp_panel_on(struct intel_dp *intel_dp);
1401 void intel_edp_panel_off(struct intel_dp *intel_dp);
1402 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1403 void intel_dp_mst_suspend(struct drm_device *dev);
1404 void intel_dp_mst_resume(struct drm_device *dev);
1405 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1406 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1407 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1408 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1409 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1410 void intel_plane_destroy(struct drm_plane *plane);
1411 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1412                            struct intel_crtc_state *crtc_state);
1413 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1414                            struct intel_crtc_state *crtc_state);
1415 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1416                                unsigned int frontbuffer_bits);
1417 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1418                           unsigned int frontbuffer_bits);
1419
1420 void
1421 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1422                                        uint8_t dp_train_pat);
1423 void
1424 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1425 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1426 uint8_t
1427 intel_dp_voltage_max(struct intel_dp *intel_dp);
1428 uint8_t
1429 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1430 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1431                            uint8_t *link_bw, uint8_t *rate_select);
1432 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1433 bool
1434 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1435
1436 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1437 {
1438         return ~((1 << lane_count) - 1) & 0xf;
1439 }
1440
1441 /* intel_dp_aux_backlight.c */
1442 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1443
1444 /* intel_dp_mst.c */
1445 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1446 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1447 /* intel_dsi.c */
1448 void intel_dsi_init(struct drm_device *dev);
1449
1450 /* intel_dsi_dcs_backlight.c */
1451 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1452
1453 /* intel_dvo.c */
1454 void intel_dvo_init(struct drm_device *dev);
1455 /* intel_hotplug.c */
1456 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1457
1458
1459 /* legacy fbdev emulation in intel_fbdev.c */
1460 #ifdef CONFIG_DRM_FBDEV_EMULATION
1461 extern int intel_fbdev_init(struct drm_device *dev);
1462 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1463 extern void intel_fbdev_fini(struct drm_device *dev);
1464 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1465 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1466 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1467 #else
1468 static inline int intel_fbdev_init(struct drm_device *dev)
1469 {
1470         return 0;
1471 }
1472
1473 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1474 {
1475 }
1476
1477 static inline void intel_fbdev_fini(struct drm_device *dev)
1478 {
1479 }
1480
1481 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1482 {
1483 }
1484
1485 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1486 {
1487 }
1488 #endif
1489
1490 /* intel_fbc.c */
1491 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1492                            struct drm_atomic_state *state);
1493 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1494 void intel_fbc_pre_update(struct intel_crtc *crtc,
1495                           struct intel_crtc_state *crtc_state,
1496                           struct intel_plane_state *plane_state);
1497 void intel_fbc_post_update(struct intel_crtc *crtc);
1498 void intel_fbc_init(struct drm_i915_private *dev_priv);
1499 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1500 void intel_fbc_enable(struct intel_crtc *crtc,
1501                       struct intel_crtc_state *crtc_state,
1502                       struct intel_plane_state *plane_state);
1503 void intel_fbc_disable(struct intel_crtc *crtc);
1504 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1505 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1506                           unsigned int frontbuffer_bits,
1507                           enum fb_op_origin origin);
1508 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1509                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1510 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1511
1512 /* intel_hdmi.c */
1513 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1514 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1515                                struct intel_connector *intel_connector);
1516 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1517 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1518                                struct intel_crtc_state *pipe_config,
1519                                struct drm_connector_state *conn_state);
1520 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1521
1522
1523 /* intel_lvds.c */
1524 void intel_lvds_init(struct drm_device *dev);
1525 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1526 bool intel_is_dual_link_lvds(struct drm_device *dev);
1527
1528
1529 /* intel_modes.c */
1530 int intel_connector_update_modes(struct drm_connector *connector,
1531                                  struct edid *edid);
1532 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1533 void intel_attach_force_audio_property(struct drm_connector *connector);
1534 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1535 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1536
1537
1538 /* intel_overlay.c */
1539 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1540 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1541 int intel_overlay_switch_off(struct intel_overlay *overlay);
1542 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1543                                   struct drm_file *file_priv);
1544 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1545                               struct drm_file *file_priv);
1546 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1547
1548
1549 /* intel_panel.c */
1550 int intel_panel_init(struct intel_panel *panel,
1551                      struct drm_display_mode *fixed_mode,
1552                      struct drm_display_mode *downclock_mode);
1553 void intel_panel_fini(struct intel_panel *panel);
1554 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1555                             struct drm_display_mode *adjusted_mode);
1556 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1557                              struct intel_crtc_state *pipe_config,
1558                              int fitting_mode);
1559 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1560                               struct intel_crtc_state *pipe_config,
1561                               int fitting_mode);
1562 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1563                                     u32 level, u32 max);
1564 int intel_panel_setup_backlight(struct drm_connector *connector,
1565                                 enum pipe pipe);
1566 void intel_panel_enable_backlight(struct intel_connector *connector);
1567 void intel_panel_disable_backlight(struct intel_connector *connector);
1568 void intel_panel_destroy_backlight(struct drm_connector *connector);
1569 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1570 extern struct drm_display_mode *intel_find_panel_downclock(
1571                                 struct drm_device *dev,
1572                                 struct drm_display_mode *fixed_mode,
1573                                 struct drm_connector *connector);
1574
1575 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1576 int intel_backlight_device_register(struct intel_connector *connector);
1577 void intel_backlight_device_unregister(struct intel_connector *connector);
1578 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1579 static int intel_backlight_device_register(struct intel_connector *connector)
1580 {
1581         return 0;
1582 }
1583 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1584 {
1585 }
1586 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1587
1588
1589 /* intel_psr.c */
1590 void intel_psr_enable(struct intel_dp *intel_dp);
1591 void intel_psr_disable(struct intel_dp *intel_dp);
1592 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1593                           unsigned frontbuffer_bits);
1594 void intel_psr_flush(struct drm_i915_private *dev_priv,
1595                      unsigned frontbuffer_bits,
1596                      enum fb_op_origin origin);
1597 void intel_psr_init(struct drm_device *dev);
1598 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1599                                    unsigned frontbuffer_bits);
1600
1601 /* intel_runtime_pm.c */
1602 int intel_power_domains_init(struct drm_i915_private *);
1603 void intel_power_domains_fini(struct drm_i915_private *);
1604 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1605 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1606 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1607 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1608 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1609 const char *
1610 intel_display_power_domain_str(enum intel_display_power_domain domain);
1611
1612 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1613                                     enum intel_display_power_domain domain);
1614 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1615                                       enum intel_display_power_domain domain);
1616 void intel_display_power_get(struct drm_i915_private *dev_priv,
1617                              enum intel_display_power_domain domain);
1618 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1619                                         enum intel_display_power_domain domain);
1620 void intel_display_power_put(struct drm_i915_private *dev_priv,
1621                              enum intel_display_power_domain domain);
1622
1623 static inline void
1624 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1625 {
1626         WARN_ONCE(dev_priv->pm.suspended,
1627                   "Device suspended during HW access\n");
1628 }
1629
1630 static inline void
1631 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1632 {
1633         assert_rpm_device_not_suspended(dev_priv);
1634         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1635          * too much noise. */
1636         if (!atomic_read(&dev_priv->pm.wakeref_count))
1637                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1638 }
1639
1640 static inline int
1641 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1642 {
1643         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1644
1645         assert_rpm_wakelock_held(dev_priv);
1646
1647         return seq;
1648 }
1649
1650 static inline void
1651 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1652 {
1653         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1654                   "HW access outside of RPM atomic section\n");
1655 }
1656
1657 /**
1658  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1659  * @dev_priv: i915 device instance
1660  *
1661  * This function disable asserts that check if we hold an RPM wakelock
1662  * reference, while keeping the device-not-suspended checks still enabled.
1663  * It's meant to be used only in special circumstances where our rule about
1664  * the wakelock refcount wrt. the device power state doesn't hold. According
1665  * to this rule at any point where we access the HW or want to keep the HW in
1666  * an active state we must hold an RPM wakelock reference acquired via one of
1667  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1668  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1669  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1670  * users should avoid using this function.
1671  *
1672  * Any calls to this function must have a symmetric call to
1673  * enable_rpm_wakeref_asserts().
1674  */
1675 static inline void
1676 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1677 {
1678         atomic_inc(&dev_priv->pm.wakeref_count);
1679 }
1680
1681 /**
1682  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1683  * @dev_priv: i915 device instance
1684  *
1685  * This function re-enables the RPM assert checks after disabling them with
1686  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1687  * circumstances otherwise its use should be avoided.
1688  *
1689  * Any calls to this function must have a symmetric call to
1690  * disable_rpm_wakeref_asserts().
1691  */
1692 static inline void
1693 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1694 {
1695         atomic_dec(&dev_priv->pm.wakeref_count);
1696 }
1697
1698 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1699 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1700 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1701 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1702
1703 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1704
1705 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1706                              bool override, unsigned int mask);
1707 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1708                           enum dpio_channel ch, bool override);
1709
1710
1711 /* intel_pm.c */
1712 void intel_init_clock_gating(struct drm_device *dev);
1713 void intel_suspend_hw(struct drm_device *dev);
1714 int ilk_wm_max_level(const struct drm_device *dev);
1715 void intel_update_watermarks(struct drm_crtc *crtc);
1716 void intel_init_pm(struct drm_device *dev);
1717 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1718 void intel_pm_setup(struct drm_device *dev);
1719 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1720 void intel_gpu_ips_teardown(void);
1721 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1722 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1723 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1724 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1725 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1726 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1727 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1728 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1729 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1730 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1731 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1732                     struct intel_rps_client *rps,
1733                     unsigned long submitted);
1734 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1735 void vlv_wm_get_hw_state(struct drm_device *dev);
1736 void ilk_wm_get_hw_state(struct drm_device *dev);
1737 void skl_wm_get_hw_state(struct drm_device *dev);
1738 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1739                           struct skl_ddb_allocation *ddb /* out */);
1740 bool skl_can_enable_sagv(struct drm_atomic_state *state);
1741 int skl_enable_sagv(struct drm_i915_private *dev_priv);
1742 int skl_disable_sagv(struct drm_i915_private *dev_priv);
1743 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1744                                const struct skl_ddb_allocation *new,
1745                                enum pipe pipe);
1746 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1747                                  const struct skl_ddb_allocation *old,
1748                                  const struct skl_ddb_allocation *new,
1749                                  enum pipe pipe);
1750 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1751                          const struct skl_wm_values *wm);
1752 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1753                         const struct skl_wm_values *wm,
1754                         int plane);
1755 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1756 bool ilk_disable_lp_wm(struct drm_device *dev);
1757 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1758 static inline int intel_enable_rc6(void)
1759 {
1760         return i915.enable_rc6;
1761 }
1762
1763 /* intel_sdvo.c */
1764 bool intel_sdvo_init(struct drm_device *dev,
1765                      i915_reg_t reg, enum port port);
1766
1767
1768 /* intel_sprite.c */
1769 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1770                              int usecs);
1771 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1772 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1773                               struct drm_file *file_priv);
1774 void intel_pipe_update_start(struct intel_crtc *crtc);
1775 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1776
1777 /* intel_tv.c */
1778 void intel_tv_init(struct drm_device *dev);
1779
1780 /* intel_atomic.c */
1781 int intel_connector_atomic_get_property(struct drm_connector *connector,
1782                                         const struct drm_connector_state *state,
1783                                         struct drm_property *property,
1784                                         uint64_t *val);
1785 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1786 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1787                                struct drm_crtc_state *state);
1788 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1789 void intel_atomic_state_clear(struct drm_atomic_state *);
1790 struct intel_shared_dpll_config *
1791 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1792
1793 static inline struct intel_crtc_state *
1794 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1795                             struct intel_crtc *crtc)
1796 {
1797         struct drm_crtc_state *crtc_state;
1798         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1799         if (IS_ERR(crtc_state))
1800                 return ERR_CAST(crtc_state);
1801
1802         return to_intel_crtc_state(crtc_state);
1803 }
1804
1805 static inline struct intel_plane_state *
1806 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1807                                       struct intel_plane *plane)
1808 {
1809         struct drm_plane_state *plane_state;
1810
1811         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1812
1813         return to_intel_plane_state(plane_state);
1814 }
1815
1816 int intel_atomic_setup_scalers(struct drm_device *dev,
1817         struct intel_crtc *intel_crtc,
1818         struct intel_crtc_state *crtc_state);
1819
1820 /* intel_atomic_plane.c */
1821 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1822 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1823 void intel_plane_destroy_state(struct drm_plane *plane,
1824                                struct drm_plane_state *state);
1825 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1826
1827 /* intel_color.c */
1828 void intel_color_init(struct drm_crtc *crtc);
1829 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1830 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1831 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1832
1833 #endif /* __INTEL_DRV_H__ */