drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_state *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         void (*post_pll_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_state *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180
 181                 /* PWM chip */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185         } backlight;
 186
 187         void (*backlight_power)(struct intel_connector *, bool enable);
 188 };
 189
 190 struct intel_connector {
 191         struct drm_connector base;
 192         /*
 193          * The fixed encoder this connector is connected to.
 194          */
 195         struct intel_encoder *encoder;
 196
 197         /* Reads out the current hw, returning true if the connector is enabled
 198          * and active (i.e. dpms ON state). */
 199         bool (*get_hw_state)(struct intel_connector *);
 200
 201         /*
 202          * Removes all interfaces through which the connector is accessible
 203          * - like sysfs, debugfs entries -, so that no new operations can be
 204          * started on the connector. Also makes sure all currently pending
 205          * operations finish before returing.
 206          */
 207         void (*unregister)(struct intel_connector *);
 208
 209         /* Panel info for eDP and LVDS */
 210         struct intel_panel panel;
 211
 212         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 213         struct edid *edid;
 214         struct edid *detect_edid;
 215
 216         /* since POLL and HPD connectors may use the same HPD line keep the native
 217            state of connector->polled in case hotplug storm detection changes it */
 218         u8 polled;
 219
 220         void *port; /* store this opaque as its illegal to dereference it */
 221
 222         struct intel_dp *mst_port;
 223 };
 224
 225 typedef struct dpll {
 226         /* given values */
 227         int n;
 228         int m1, m2;
 229         int p1, p2;
 230         /* derived values */
 231         int     dot;
 232         int     vco;
 233         int     m;
 234         int     p;
 235 } intel_clock_t;
 236
 237 struct intel_atomic_state {
 238         struct drm_atomic_state base;
 239
 240         unsigned int cdclk;
 241         bool dpll_set;
 242         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 243 };
 244
 245 struct intel_plane_state {
 246         struct drm_plane_state base;
 247         struct drm_rect src;
 248         struct drm_rect dst;
 249         struct drm_rect clip;
 250         bool visible;
 251
 252         /*
 253          * scaler_id
 254          *    = -1 : not using a scaler
 255          *    >=  0 : using a scalers
 256          *
 257          * plane requiring a scaler:
 258          *   - During check_plane, its bit is set in
 259          *     crtc_state->scaler_state.scaler_users by calling helper function
 260          *     update_scaler_plane.
 261          *   - scaler_id indicates the scaler it got assigned.
 262          *
 263          * plane doesn't require a scaler:
 264          *   - this can happen when scaling is no more required or plane simply
 265          *     got disabled.
 266          *   - During check_plane, corresponding bit is reset in
 267          *     crtc_state->scaler_state.scaler_users by calling helper function
 268          *     update_scaler_plane.
 269          */
 270         int scaler_id;
 271
 272         struct drm_intel_sprite_colorkey ckey;
 273 };
 274
 275 struct intel_initial_plane_config {
 276         struct intel_framebuffer *fb;
 277         unsigned int tiling;
 278         int size;
 279         u32 base;
 280 };
 281
 282 #define SKL_MIN_SRC_W 8
 283 #define SKL_MAX_SRC_W 4096
 284 #define SKL_MIN_SRC_H 8
 285 #define SKL_MAX_SRC_H 4096
 286 #define SKL_MIN_DST_W 8
 287 #define SKL_MAX_DST_W 4096
 288 #define SKL_MIN_DST_H 8
 289 #define SKL_MAX_DST_H 4096
 290
 291 struct intel_scaler {
 292         int in_use;
 293         uint32_t mode;
 294 };
 295
 296 struct intel_crtc_scaler_state {
 297 #define SKL_NUM_SCALERS 2
 298         struct intel_scaler scalers[SKL_NUM_SCALERS];
 299
 300         /*
 301          * scaler_users: keeps track of users requesting scalers on this crtc.
 302          *
 303          *     If a bit is set, a user is using a scaler.
 304          *     Here user can be a plane or crtc as defined below:
 305          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 306          *       bit 31    - crtc
 307          *
 308          * Instead of creating a new index to cover planes and crtc, using
 309          * existing drm_plane_index for planes which is well less than 31
 310          * planes and bit 31 for crtc. This should be fine to cover all
 311          * our platforms.
 312          *
 313          * intel_atomic_setup_scalers will setup available scalers to users
 314          * requesting scalers. It will gracefully fail if request exceeds
 315          * avilability.
 316          */
 317 #define SKL_CRTC_INDEX 31
 318         unsigned scaler_users;
 319
 320         /* scaler used by crtc for panel fitting purpose */
 321         int scaler_id;
 322 };
 323
 324 /* drm_mode->private_flags */
 325 #define I915_MODE_FLAG_INHERITED 1
 326
 327 struct intel_crtc_state {
 328         struct drm_crtc_state base;
 329
 330         /**
 331          * quirks - bitfield with hw state readout quirks
 332          *
 333          * For various reasons the hw state readout code might not be able to
 334          * completely faithfully read out the current state. These cases are
 335          * tracked with quirk flags so that fastboot and state checker can act
 336          * accordingly.
 337          */
 338 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 339         unsigned long quirks;
 340
 341         bool update_pipe;
 342
 343         /* Pipe source size (ie. panel fitter input size)
 344          * All planes will be positioned inside this space,
 345          * and get clipped at the edges. */
 346         int pipe_src_w, pipe_src_h;
 347
 348         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 349          * between pch encoders and cpu encoders. */
 350         bool has_pch_encoder;
 351
 352         /* Are we sending infoframes on the attached port */
 353         bool has_infoframe;
 354
 355         /* CPU Transcoder for the pipe. Currently this can only differ from the
 356          * pipe on Haswell (where we have a special eDP transcoder). */
 357         enum transcoder cpu_transcoder;
 358
 359         /*
 360          * Use reduced/limited/broadcast rbg range, compressing from the full
 361          * range fed into the crtcs.
 362          */
 363         bool limited_color_range;
 364
 365         /* DP has a bunch of special case unfortunately, so mark the pipe
 366          * accordingly. */
 367         bool has_dp_encoder;
 368
 369         /* Whether we should send NULL infoframes. Required for audio. */
 370         bool has_hdmi_sink;
 371
 372         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 373          * has_dp_encoder is set. */
 374         bool has_audio;
 375
 376         /*
 377          * Enable dithering, used when the selected pipe bpp doesn't match the
 378          * plane bpp.
 379          */
 380         bool dither;
 381
 382         /* Controls for the clock computation, to override various stages. */
 383         bool clock_set;
 384
 385         /* SDVO TV has a bunch of special case. To make multifunction encoders
 386          * work correctly, we need to track this at runtime.*/
 387         bool sdvo_tv_clock;
 388
 389         /*
 390          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 391          * required. This is set in the 2nd loop of calling encoder's
 392          * ->compute_config if the first pick doesn't work out.
 393          */
 394         bool bw_constrained;
 395
 396         /* Settings for the intel dpll used on pretty much everything but
 397          * haswell. */
 398         struct dpll dpll;
 399
 400         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 401         enum intel_dpll_id shared_dpll;
 402
 403         /*
 404          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 405          * - enum skl_dpll on SKL
 406          */
 407         uint32_t ddi_pll_sel;
 408
 409         /* Actual register state of the dpll, for shared dpll cross-checking. */
 410         struct intel_dpll_hw_state dpll_hw_state;
 411
 412         int pipe_bpp;
 413         struct intel_link_m_n dp_m_n;
 414
 415         /* m2_n2 for eDP downclock */
 416         struct intel_link_m_n dp_m2_n2;
 417         bool has_drrs;
 418
 419         /*
 420          * Frequence the dpll for the port should run at. Differs from the
 421          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 422          * already multiplied by pixel_multiplier.
 423          */
 424         int port_clock;
 425
 426         /* Used by SDVO (and if we ever fix it, HDMI). */
 427         unsigned pixel_multiplier;
 428
 429         uint8_t lane_count;
 430
 431         /* Panel fitter controls for gen2-gen4 + VLV */
 432         struct {
 433                 u32 control;
 434                 u32 pgm_ratios;
 435                 u32 lvds_border_bits;
 436         } gmch_pfit;
 437
 438         /* Panel fitter placement and size for Ironlake+ */
 439         struct {
 440                 u32 pos;
 441                 u32 size;
 442                 bool enabled;
 443                 bool force_thru;
 444         } pch_pfit;
 445
 446         /* FDI configuration, only valid if has_pch_encoder is set. */
 447         int fdi_lanes;
 448         struct intel_link_m_n fdi_m_n;
 449
 450         bool ips_enabled;
 451
 452         bool double_wide;
 453
 454         bool dp_encoder_is_mst;
 455         int pbn;
 456
 457         struct intel_crtc_scaler_state scaler_state;
 458
 459         /* w/a for waiting 2 vblanks during crtc enable */
 460         enum pipe hsw_workaround_pipe;
 461 };
 462
 463 struct vlv_wm_state {
 464         struct vlv_pipe_wm wm[3];
 465         struct vlv_sr_wm sr[3];
 466         uint8_t num_active_planes;
 467         uint8_t num_levels;
 468         uint8_t level;
 469         bool cxsr;
 470 };
 471
 472 struct intel_pipe_wm {
 473         struct intel_wm_level wm[5];
 474         uint32_t linetime;
 475         bool fbc_wm_enabled;
 476         bool pipe_enabled;
 477         bool sprites_enabled;
 478         bool sprites_scaled;
 479 };
 480
 481 struct intel_mmio_flip {
 482         struct work_struct work;
 483         struct drm_i915_private *i915;
 484         struct drm_i915_gem_request *req;
 485         struct intel_crtc *crtc;
 486 };
 487
 488 struct skl_pipe_wm {
 489         struct skl_wm_level wm[8];
 490         struct skl_wm_level trans_wm;
 491         uint32_t linetime;
 492 };
 493
 494 /*
 495  * Tracking of operations that need to be performed at the beginning/end of an
 496  * atomic commit, outside the atomic section where interrupts are disabled.
 497  * These are generally operations that grab mutexes or might otherwise sleep
 498  * and thus can't be run with interrupts disabled.
 499  */
 500 struct intel_crtc_atomic_commit {
 501         /* Sleepable operations to perform before commit */
 502         bool wait_for_flips;
 503         bool disable_fbc;
 504         bool disable_ips;
 505         bool disable_cxsr;
 506         bool pre_disable_primary;
 507         bool update_wm_pre, update_wm_post;
 508         unsigned disabled_planes;
 509
 510         /* Sleepable operations to perform after commit */
 511         unsigned fb_bits;
 512         bool wait_vblank;
 513         bool update_fbc;
 514         bool post_enable_primary;
 515         unsigned update_sprite_watermarks;
 516 };
 517
 518 struct intel_crtc {
 519         struct drm_crtc base;
 520         enum pipe pipe;
 521         enum plane plane;
 522         u8 lut_r[256], lut_g[256], lut_b[256];
 523         /*
 524          * Whether the crtc and the connected output pipeline is active. Implies
 525          * that crtc->enabled is set, i.e. the current mode configuration has
 526          * some outputs connected to this crtc.
 527          */
 528         bool active;
 529         unsigned long enabled_power_domains;
 530         bool lowfreq_avail;
 531         struct intel_overlay *overlay;
 532         struct intel_unpin_work *unpin_work;
 533
 534         atomic_t unpin_work_count;
 535
 536         /* Display surface base address adjustement for pageflips. Note that on
 537          * gen4+ this only adjusts up to a tile, offsets within a tile are
 538          * handled in the hw itself (with the TILEOFF register). */
 539         unsigned long dspaddr_offset;
 540         int adjusted_x;
 541         int adjusted_y;
 542
 543         struct drm_i915_gem_object *cursor_bo;
 544         uint32_t cursor_addr;
 545         uint32_t cursor_cntl;
 546         uint32_t cursor_size;
 547         uint32_t cursor_base;
 548
 549         struct intel_crtc_state *config;
 550
 551         /* reset counter value when the last flip was submitted */
 552         unsigned int reset_counter;
 553
 554         /* Access to these should be protected by dev_priv->irq_lock. */
 555         bool cpu_fifo_underrun_disabled;
 556         bool pch_fifo_underrun_disabled;
 557
 558         /* per-pipe watermark state */
 559         struct {
 560                 /* watermarks currently being used  */
 561                 struct intel_pipe_wm active;
 562                 /* SKL wm values currently in use */
 563                 struct skl_pipe_wm skl_active;
 564                 /* allow CxSR on this pipe */
 565                 bool cxsr_allowed;
 566         } wm;
 567
 568         int scanline_offset;
 569
 570         struct {
 571                 unsigned start_vbl_count;
 572                 ktime_t start_vbl_time;
 573                 int min_vbl, max_vbl;
 574                 int scanline_start;
 575         } debug;
 576
 577         struct intel_crtc_atomic_commit atomic;
 578
 579         /* scalers available on this crtc */
 580         int num_scalers;
 581
 582         struct vlv_wm_state wm_state;
 583 };
 584
 585 struct intel_plane_wm_parameters {
 586         uint32_t horiz_pixels;
 587         uint32_t vert_pixels;
 588         /*
 589          *   For packed pixel formats:
 590          *     bytes_per_pixel - holds bytes per pixel
 591          *   For planar pixel formats:
 592          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 593          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 594          */
 595         uint8_t bytes_per_pixel;
 596         uint8_t y_bytes_per_pixel;
 597         bool enabled;
 598         bool scaled;
 599         u64 tiling;
 600         unsigned int rotation;
 601         uint16_t fifo_size;
 602 };
 603
 604 struct intel_plane {
 605         struct drm_plane base;
 606         int plane;
 607         enum pipe pipe;
 608         bool can_scale;
 609         int max_downscale;
 610         uint32_t frontbuffer_bit;
 611
 612         /* Since we need to change the watermarks before/after
 613          * enabling/disabling the planes, we need to store the parameters here
 614          * as the other pieces of the struct may not reflect the values we want
 615          * for the watermark calculations. Currently only Haswell uses this.
 616          */
 617         struct intel_plane_wm_parameters wm;
 618
 619         /*
 620          * NOTE: Do not place new plane state fields here (e.g., when adding
 621          * new plane properties).  New runtime state should now be placed in
 622          * the intel_plane_state structure and accessed via drm_plane->state.
 623          */
 624
 625         void (*update_plane)(struct drm_plane *plane,
 626                              struct drm_crtc *crtc,
 627                              struct drm_framebuffer *fb,
 628                              int crtc_x, int crtc_y,
 629                              unsigned int crtc_w, unsigned int crtc_h,
 630                              uint32_t x, uint32_t y,
 631                              uint32_t src_w, uint32_t src_h);
 632         void (*disable_plane)(struct drm_plane *plane,
 633                               struct drm_crtc *crtc);
 634         int (*check_plane)(struct drm_plane *plane,
 635                            struct intel_crtc_state *crtc_state,
 636                            struct intel_plane_state *state);
 637         void (*commit_plane)(struct drm_plane *plane,
 638                              struct intel_plane_state *state);
 639 };
 640
 641 struct intel_watermark_params {
 642         unsigned long fifo_size;
 643         unsigned long max_wm;
 644         unsigned long default_wm;
 645         unsigned long guard_size;
 646         unsigned long cacheline_size;
 647 };
 648
 649 struct cxsr_latency {
 650         int is_desktop;
 651         int is_ddr3;
 652         unsigned long fsb_freq;
 653         unsigned long mem_freq;
 654         unsigned long display_sr;
 655         unsigned long display_hpll_disable;
 656         unsigned long cursor_sr;
 657         unsigned long cursor_hpll_disable;
 658 };
 659
 660 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 661 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 662 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 663 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 664 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 665 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 666 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 667 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 668 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 669
 670 struct intel_hdmi {
 671         u32 hdmi_reg;
 672         int ddc_bus;
 673         bool limited_color_range;
 674         bool color_range_auto;
 675         bool has_hdmi_sink;
 676         bool has_audio;
 677         enum hdmi_force_audio force_audio;
 678         bool rgb_quant_range_selectable;
 679         enum hdmi_picture_aspect aspect_ratio;
 680         struct intel_connector *attached_connector;
 681         void (*write_infoframe)(struct drm_encoder *encoder,
 682                                 enum hdmi_infoframe_type type,
 683                                 const void *frame, ssize_t len);
 684         void (*set_infoframes)(struct drm_encoder *encoder,
 685                                bool enable,
 686                                struct drm_display_mode *adjusted_mode);
 687         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 688 };
 689
 690 struct intel_dp_mst_encoder;
 691 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 692
 693 /*
 694  * enum link_m_n_set:
 695  *      When platform provides two set of M_N registers for dp, we can
 696  *      program them and switch between them incase of DRRS.
 697  *      But When only one such register is provided, we have to program the
 698  *      required divider value on that registers itself based on the DRRS state.
 699  *
 700  * M1_N1        : Program dp_m_n on M1_N1 registers
 701  *                        dp_m2_n2 on M2_N2 registers (If supported)
 702  *
 703  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 704  *                        M2_N2 registers are not supported
 705  */
 706
 707 enum link_m_n_set {
 708         /* Sets the m1_n1 and m2_n2 */
 709         M1_N1 = 0,
 710         M2_N2
 711 };
 712
 713 struct sink_crc {
 714         bool started;
 715         u8 last_crc[6];
 716         int last_count;
 717 };
 718
 719 struct intel_dp {
 720         uint32_t output_reg;
 721         uint32_t aux_ch_ctl_reg;
 722         uint32_t DP;
 723         int link_rate;
 724         uint8_t lane_count;
 725         bool has_audio;
 726         enum hdmi_force_audio force_audio;
 727         bool limited_color_range;
 728         bool color_range_auto;
 729         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 730         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 731         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 732         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 733         uint8_t num_sink_rates;
 734         int sink_rates[DP_MAX_SUPPORTED_RATES];
 735         struct sink_crc sink_crc;
 736         struct drm_dp_aux aux;
 737         uint8_t train_set[4];
 738         int panel_power_up_delay;
 739         int panel_power_down_delay;
 740         int panel_power_cycle_delay;
 741         int backlight_on_delay;
 742         int backlight_off_delay;
 743         struct delayed_work panel_vdd_work;
 744         bool want_panel_vdd;
 745         unsigned long last_power_cycle;
 746         unsigned long last_power_on;
 747         unsigned long last_backlight_off;
 748
 749         struct notifier_block edp_notifier;
 750
 751         /*
 752          * Pipe whose power sequencer is currently locked into
 753          * this port. Only relevant on VLV/CHV.
 754          */
 755         enum pipe pps_pipe;
 756         struct edp_power_seq pps_delays;
 757
 758         bool can_mst; /* this port supports mst */
 759         bool is_mst;
 760         int active_mst_links;
 761         /* connector directly attached - won't be use for modeset in mst world */
 762         struct intel_connector *attached_connector;
 763
 764         /* mst connector list */
 765         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 766         struct drm_dp_mst_topology_mgr mst_mgr;
 767
 768         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 769         /*
 770          * This function returns the value we have to program the AUX_CTL
 771          * register with to kick off an AUX transaction.
 772          */
 773         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 774                                      bool has_aux_irq,
 775                                      int send_bytes,
 776                                      uint32_t aux_clock_divider);
 777         bool train_set_valid;
 778
 779         /* Displayport compliance testing */
 780         unsigned long compliance_test_type;
 781         unsigned long compliance_test_data;
 782         bool compliance_test_active;
 783 };
 784
 785 struct intel_digital_port {
 786         struct intel_encoder base;
 787         enum port port;
 788         u32 saved_port_bits;
 789         struct intel_dp dp;
 790         struct intel_hdmi hdmi;
 791         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 792         bool release_cl2_override;
 793 };
 794
 795 struct intel_dp_mst_encoder {
 796         struct intel_encoder base;
 797         enum pipe pipe;
 798         struct intel_digital_port *primary;
 799         void *port; /* store this opaque as its illegal to dereference it */
 800 };
 801
 802 static inline enum dpio_channel
 803 vlv_dport_to_channel(struct intel_digital_port *dport)
 804 {
 805         switch (dport->port) {
 806         case PORT_B:
 807         case PORT_D:
 808                 return DPIO_CH0;
 809         case PORT_C:
 810                 return DPIO_CH1;
 811         default:
 812                 BUG();
 813         }
 814 }
 815
 816 static inline enum dpio_phy
 817 vlv_dport_to_phy(struct intel_digital_port *dport)
 818 {
 819         switch (dport->port) {
 820         case PORT_B:
 821         case PORT_C:
 822                 return DPIO_PHY0;
 823         case PORT_D:
 824                 return DPIO_PHY1;
 825         default:
 826                 BUG();
 827         }
 828 }
 829
 830 static inline enum dpio_channel
 831 vlv_pipe_to_channel(enum pipe pipe)
 832 {
 833         switch (pipe) {
 834         case PIPE_A:
 835         case PIPE_C:
 836                 return DPIO_CH0;
 837         case PIPE_B:
 838                 return DPIO_CH1;
 839         default:
 840                 BUG();
 841         }
 842 }
 843
 844 static inline struct drm_crtc *
 845 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         return dev_priv->pipe_to_crtc_mapping[pipe];
 849 }
 850
 851 static inline struct drm_crtc *
 852 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 853 {
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         return dev_priv->plane_to_crtc_mapping[plane];
 856 }
 857
 858 struct intel_unpin_work {
 859         struct work_struct work;
 860         struct drm_crtc *crtc;
 861         struct drm_framebuffer *old_fb;
 862         struct drm_i915_gem_object *pending_flip_obj;
 863         struct drm_pending_vblank_event *event;
 864         atomic_t pending;
 865 #define INTEL_FLIP_INACTIVE     0
 866 #define INTEL_FLIP_PENDING      1
 867 #define INTEL_FLIP_COMPLETE     2
 868         u32 flip_count;
 869         u32 gtt_offset;
 870         struct drm_i915_gem_request *flip_queued_req;
 871         u32 flip_queued_vblank;
 872         u32 flip_ready_vblank;
 873         bool enable_stall_check;
 874 };
 875
 876 struct intel_load_detect_pipe {
 877         struct drm_framebuffer *release_fb;
 878         bool load_detect_temp;
 879         int dpms_mode;
 880 };
 881
 882 static inline struct intel_encoder *
 883 intel_attached_encoder(struct drm_connector *connector)
 884 {
 885         return to_intel_connector(connector)->encoder;
 886 }
 887
 888 static inline struct intel_digital_port *
 889 enc_to_dig_port(struct drm_encoder *encoder)
 890 {
 891         return container_of(encoder, struct intel_digital_port, base.base);
 892 }
 893
 894 static inline struct intel_dp_mst_encoder *
 895 enc_to_mst(struct drm_encoder *encoder)
 896 {
 897         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 898 }
 899
 900 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 901 {
 902         return &enc_to_dig_port(encoder)->dp;
 903 }
 904
 905 static inline struct intel_digital_port *
 906 dp_to_dig_port(struct intel_dp *intel_dp)
 907 {
 908         return container_of(intel_dp, struct intel_digital_port, dp);
 909 }
 910
 911 static inline struct intel_digital_port *
 912 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 913 {
 914         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 915 }
 916
 917 /*
 918  * Returns the number of planes for this pipe, ie the number of sprites + 1
 919  * (primary plane). This doesn't count the cursor plane then.
 920  */
 921 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 922 {
 923         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 924 }
 925
 926 /* intel_fifo_underrun.c */
 927 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 928                                            enum pipe pipe, bool enable);
 929 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 930                                            enum transcoder pch_transcoder,
 931                                            bool enable);
 932 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 933                                          enum pipe pipe);
 934 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 935                                          enum transcoder pch_transcoder);
 936 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 937
 938 /* i915_irq.c */
 939 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 940 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 941 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 942 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 943 void gen6_reset_rps_interrupts(struct drm_device *dev);
 944 void gen6_enable_rps_interrupts(struct drm_device *dev);
 945 void gen6_disable_rps_interrupts(struct drm_device *dev);
 946 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 947 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 948 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 949 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 950 {
 951         /*
 952          * We only use drm_irq_uninstall() at unload and VT switch, so
 953          * this is the only thing we need to check.
 954          */
 955         return dev_priv->pm.irqs_enabled;
 956 }
 957
 958 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 959 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 960                                      unsigned int pipe_mask);
 961
 962 /* intel_crt.c */
 963 void intel_crt_init(struct drm_device *dev);
 964
 965
 966 /* intel_ddi.c */
 967 void intel_prepare_ddi(struct drm_device *dev);
 968 void hsw_fdi_link_train(struct drm_crtc *crtc);
 969 void intel_ddi_init(struct drm_device *dev, enum port port);
 970 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 971 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 972 void intel_ddi_pll_init(struct drm_device *dev);
 973 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 974 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 975                                        enum transcoder cpu_transcoder);
 976 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 977 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 978 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 979                           struct intel_crtc_state *crtc_state);
 980 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 981 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 982 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 983 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 984 void intel_ddi_get_config(struct intel_encoder *encoder,
 985                           struct intel_crtc_state *pipe_config);
 986 struct intel_encoder *
 987 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 988
 989 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 990 void intel_ddi_clock_get(struct intel_encoder *encoder,
 991                          struct intel_crtc_state *pipe_config);
 992 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 993 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 994
 995 /* intel_frontbuffer.c */
 996 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 997                              enum fb_op_origin origin);
 998 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 999                                     unsigned frontbuffer_bits);
1000 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1001                                      unsigned frontbuffer_bits);
1002 void intel_frontbuffer_flip(struct drm_device *dev,
1003                             unsigned frontbuffer_bits);
1004 unsigned int intel_fb_align_height(struct drm_device *dev,
1005                                    unsigned int height,
1006                                    uint32_t pixel_format,
1007                                    uint64_t fb_format_modifier);
1008 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1009                         enum fb_op_origin origin);
1010 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1011                               uint32_t pixel_format);
1012
1013 /* intel_audio.c */
1014 void intel_init_audio(struct drm_device *dev);
1015 void intel_audio_codec_enable(struct intel_encoder *encoder);
1016 void intel_audio_codec_disable(struct intel_encoder *encoder);
1017 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1018 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1019
1020 /* intel_display.c */
1021 extern const struct drm_plane_funcs intel_plane_funcs;
1022 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1023 int intel_pch_rawclk(struct drm_device *dev);
1024 int intel_hrawclk(struct drm_device *dev);
1025 void intel_mark_busy(struct drm_device *dev);
1026 void intel_mark_idle(struct drm_device *dev);
1027 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1028 int intel_display_suspend(struct drm_device *dev);
1029 void intel_encoder_destroy(struct drm_encoder *encoder);
1030 int intel_connector_init(struct intel_connector *);
1031 struct intel_connector *intel_connector_alloc(void);
1032 bool intel_connector_get_hw_state(struct intel_connector *connector);
1033 void intel_connector_attach_encoder(struct intel_connector *connector,
1034                                     struct intel_encoder *encoder);
1035 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1036 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1037                                              struct drm_crtc *crtc);
1038 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1039 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1040                                 struct drm_file *file_priv);
1041 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1042                                              enum pipe pipe);
1043 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1044 static inline void
1045 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1046 {
1047         drm_wait_one_vblank(dev, pipe);
1048 }
1049 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1050 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1051                          struct intel_digital_port *dport,
1052                          unsigned int expected_mask);
1053 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1054                                 struct drm_display_mode *mode,
1055                                 struct intel_load_detect_pipe *old,
1056                                 struct drm_modeset_acquire_ctx *ctx);
1057 void intel_release_load_detect_pipe(struct drm_connector *connector,
1058                                     struct intel_load_detect_pipe *old,
1059                                     struct drm_modeset_acquire_ctx *ctx);
1060 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1061                                struct drm_framebuffer *fb,
1062                                const struct drm_plane_state *plane_state,
1063                                struct intel_engine_cs *pipelined,
1064                                struct drm_i915_gem_request **pipelined_request);
1065 struct drm_framebuffer *
1066 __intel_framebuffer_create(struct drm_device *dev,
1067                            struct drm_mode_fb_cmd2 *mode_cmd,
1068                            struct drm_i915_gem_object *obj);
1069 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1070 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1071 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1072 void intel_check_page_flip(struct drm_device *dev, int pipe);
1073 int intel_prepare_plane_fb(struct drm_plane *plane,
1074                            const struct drm_plane_state *new_state);
1075 void intel_cleanup_plane_fb(struct drm_plane *plane,
1076                             const struct drm_plane_state *old_state);
1077 int intel_plane_atomic_get_property(struct drm_plane *plane,
1078                                     const struct drm_plane_state *state,
1079                                     struct drm_property *property,
1080                                     uint64_t *val);
1081 int intel_plane_atomic_set_property(struct drm_plane *plane,
1082                                     struct drm_plane_state *state,
1083                                     struct drm_property *property,
1084                                     uint64_t val);
1085 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1086                                     struct drm_plane_state *plane_state);
1087
1088 unsigned int
1089 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1090                   uint64_t fb_format_modifier, unsigned int plane);
1091
1092 static inline bool
1093 intel_rotation_90_or_270(unsigned int rotation)
1094 {
1095         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1096 }
1097
1098 void intel_create_rotation_property(struct drm_device *dev,
1099                                         struct intel_plane *plane);
1100
1101 /* shared dpll functions */
1102 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1103 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1104                         struct intel_shared_dpll *pll,
1105                         bool state);
1106 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1107 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1108 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1109                                                 struct intel_crtc_state *state);
1110
1111 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1112                       const struct dpll *dpll);
1113 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1114
1115 /* modesetting asserts */
1116 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1117                            enum pipe pipe);
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119                 enum pipe pipe, bool state);
1120 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1121 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1122 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1123                        enum pipe pipe, bool state);
1124 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1125 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1126 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1127 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1128 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1129 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1130                                              int *x, int *y,
1131                                              unsigned int tiling_mode,
1132                                              unsigned int bpp,
1133                                              unsigned int pitch);
1134 void intel_prepare_reset(struct drm_device *dev);
1135 void intel_finish_reset(struct drm_device *dev);
1136 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1137 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1138 void broxton_init_cdclk(struct drm_device *dev);
1139 void broxton_uninit_cdclk(struct drm_device *dev);
1140 void broxton_ddi_phy_init(struct drm_device *dev);
1141 void broxton_ddi_phy_uninit(struct drm_device *dev);
1142 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1143 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1144 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1145 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1146 void intel_dp_get_m_n(struct intel_crtc *crtc,
1147                       struct intel_crtc_state *pipe_config);
1148 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1149 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1150 void
1151 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1152                                 int dotclock);
1153 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1154                         intel_clock_t *best_clock);
1155 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1156
1157 bool intel_crtc_active(struct drm_crtc *crtc);
1158 void hsw_enable_ips(struct intel_crtc *crtc);
1159 void hsw_disable_ips(struct intel_crtc *crtc);
1160 enum intel_display_power_domain
1161 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1162 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1163                                  struct intel_crtc_state *pipe_config);
1164 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1165 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1166
1167 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1168 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1169
1170 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1171                                      struct drm_i915_gem_object *obj,
1172                                      unsigned int plane);
1173
1174 u32 skl_plane_ctl_format(uint32_t pixel_format);
1175 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1176 u32 skl_plane_ctl_rotation(unsigned int rotation);
1177
1178 /* intel_csr.c */
1179 void intel_csr_ucode_init(struct drm_device *dev);
1180 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1181 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1182                                         enum csr_state state);
1183 void intel_csr_load_program(struct drm_device *dev);
1184 void intel_csr_ucode_fini(struct drm_device *dev);
1185 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1186
1187 /* intel_dp.c */
1188 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1189 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1190                              struct intel_connector *intel_connector);
1191 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1192                               const struct intel_crtc_state *pipe_config);
1193 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1194 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1195 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1196 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1197 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1198 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1199 bool intel_dp_compute_config(struct intel_encoder *encoder,
1200                              struct intel_crtc_state *pipe_config);
1201 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1202 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1203                                   bool long_hpd);
1204 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1205 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1206 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1207 void intel_edp_panel_on(struct intel_dp *intel_dp);
1208 void intel_edp_panel_off(struct intel_dp *intel_dp);
1209 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1210 void intel_dp_mst_suspend(struct drm_device *dev);
1211 void intel_dp_mst_resume(struct drm_device *dev);
1212 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1213 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1214 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1215 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1216 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1217 void intel_plane_destroy(struct drm_plane *plane);
1218 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1219 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1220 void intel_edp_drrs_invalidate(struct drm_device *dev,
1221                 unsigned frontbuffer_bits);
1222 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1223 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1224                                          struct intel_digital_port *port);
1225 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1226
1227 /* intel_dp_mst.c */
1228 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1229 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1230 /* intel_dsi.c */
1231 void intel_dsi_init(struct drm_device *dev);
1232
1233
1234 /* intel_dvo.c */
1235 void intel_dvo_init(struct drm_device *dev);
1236
1237
1238 /* legacy fbdev emulation in intel_fbdev.c */
1239 #ifdef CONFIG_DRM_FBDEV_EMULATION
1240 extern int intel_fbdev_init(struct drm_device *dev);
1241 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1242 extern void intel_fbdev_fini(struct drm_device *dev);
1243 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1244 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1245 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1246 #else
1247 static inline int intel_fbdev_init(struct drm_device *dev)
1248 {
1249         return 0;
1250 }
1251
1252 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1253 {
1254 }
1255
1256 static inline void intel_fbdev_fini(struct drm_device *dev)
1257 {
1258 }
1259
1260 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1261 {
1262 }
1263
1264 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1265 {
1266 }
1267 #endif
1268
1269 /* intel_fbc.c */
1270 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1271 void intel_fbc_update(struct drm_i915_private *dev_priv);
1272 void intel_fbc_init(struct drm_i915_private *dev_priv);
1273 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1274 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1275 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1276                           unsigned int frontbuffer_bits,
1277                           enum fb_op_origin origin);
1278 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1279                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1280 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1281 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1282
1283 /* intel_hdmi.c */
1284 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1285 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1286                                struct intel_connector *intel_connector);
1287 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1288 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1289                                struct intel_crtc_state *pipe_config);
1290
1291
1292 /* intel_lvds.c */
1293 void intel_lvds_init(struct drm_device *dev);
1294 bool intel_is_dual_link_lvds(struct drm_device *dev);
1295
1296
1297 /* intel_modes.c */
1298 int intel_connector_update_modes(struct drm_connector *connector,
1299                                  struct edid *edid);
1300 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1301 void intel_attach_force_audio_property(struct drm_connector *connector);
1302 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1303
1304
1305 /* intel_overlay.c */
1306 void intel_setup_overlay(struct drm_device *dev);
1307 void intel_cleanup_overlay(struct drm_device *dev);
1308 int intel_overlay_switch_off(struct intel_overlay *overlay);
1309 int intel_overlay_put_image(struct drm_device *dev, void *data,
1310                             struct drm_file *file_priv);
1311 int intel_overlay_attrs(struct drm_device *dev, void *data,
1312                         struct drm_file *file_priv);
1313 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1314
1315
1316 /* intel_panel.c */
1317 int intel_panel_init(struct intel_panel *panel,
1318                      struct drm_display_mode *fixed_mode,
1319                      struct drm_display_mode *downclock_mode);
1320 void intel_panel_fini(struct intel_panel *panel);
1321 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1322                             struct drm_display_mode *adjusted_mode);
1323 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1324                              struct intel_crtc_state *pipe_config,
1325                              int fitting_mode);
1326 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1327                               struct intel_crtc_state *pipe_config,
1328                               int fitting_mode);
1329 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1330                                     u32 level, u32 max);
1331 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1332 void intel_panel_enable_backlight(struct intel_connector *connector);
1333 void intel_panel_disable_backlight(struct intel_connector *connector);
1334 void intel_panel_destroy_backlight(struct drm_connector *connector);
1335 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1336 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1337 extern struct drm_display_mode *intel_find_panel_downclock(
1338                                 struct drm_device *dev,
1339                                 struct drm_display_mode *fixed_mode,
1340                                 struct drm_connector *connector);
1341 void intel_backlight_register(struct drm_device *dev);
1342 void intel_backlight_unregister(struct drm_device *dev);
1343
1344
1345 /* intel_psr.c */
1346 void intel_psr_enable(struct intel_dp *intel_dp);
1347 void intel_psr_disable(struct intel_dp *intel_dp);
1348 void intel_psr_invalidate(struct drm_device *dev,
1349                           unsigned frontbuffer_bits);
1350 void intel_psr_flush(struct drm_device *dev,
1351                      unsigned frontbuffer_bits,
1352                      enum fb_op_origin origin);
1353 void intel_psr_init(struct drm_device *dev);
1354 void intel_psr_single_frame_update(struct drm_device *dev,
1355                                    unsigned frontbuffer_bits);
1356
1357 /* intel_runtime_pm.c */
1358 int intel_power_domains_init(struct drm_i915_private *);
1359 void intel_power_domains_fini(struct drm_i915_private *);
1360 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1361 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1362
1363 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1364                                     enum intel_display_power_domain domain);
1365 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1366                                       enum intel_display_power_domain domain);
1367 void intel_display_power_get(struct drm_i915_private *dev_priv,
1368                              enum intel_display_power_domain domain);
1369 void intel_display_power_put(struct drm_i915_private *dev_priv,
1370                              enum intel_display_power_domain domain);
1371 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1372 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1373 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1374 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1375 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1376
1377 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1378
1379 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1380                              bool override, unsigned int mask);
1381 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1382                           enum dpio_channel ch, bool override);
1383
1384
1385 /* intel_pm.c */
1386 void intel_init_clock_gating(struct drm_device *dev);
1387 void intel_suspend_hw(struct drm_device *dev);
1388 int ilk_wm_max_level(const struct drm_device *dev);
1389 void intel_update_watermarks(struct drm_crtc *crtc);
1390 void intel_update_sprite_watermarks(struct drm_plane *plane,
1391                                     struct drm_crtc *crtc,
1392                                     uint32_t sprite_width,
1393                                     uint32_t sprite_height,
1394                                     int pixel_size,
1395                                     bool enabled, bool scaled);
1396 void intel_init_pm(struct drm_device *dev);
1397 void intel_pm_setup(struct drm_device *dev);
1398 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1399 void intel_gpu_ips_teardown(void);
1400 void intel_init_gt_powersave(struct drm_device *dev);
1401 void intel_cleanup_gt_powersave(struct drm_device *dev);
1402 void intel_enable_gt_powersave(struct drm_device *dev);
1403 void intel_disable_gt_powersave(struct drm_device *dev);
1404 void intel_suspend_gt_powersave(struct drm_device *dev);
1405 void intel_reset_gt_powersave(struct drm_device *dev);
1406 void gen6_update_ring_freq(struct drm_device *dev);
1407 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1408 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1409 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1410 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1411                     struct intel_rps_client *rps,
1412                     unsigned long submitted);
1413 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1414                                        struct drm_i915_gem_request *req);
1415 void vlv_wm_get_hw_state(struct drm_device *dev);
1416 void ilk_wm_get_hw_state(struct drm_device *dev);
1417 void skl_wm_get_hw_state(struct drm_device *dev);
1418 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1419                           struct skl_ddb_allocation *ddb /* out */);
1420 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1421
1422 /* intel_sdvo.c */
1423 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1424
1425
1426 /* intel_sprite.c */
1427 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1428 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1429                               struct drm_file *file_priv);
1430 void intel_pipe_update_start(struct intel_crtc *crtc);
1431 void intel_pipe_update_end(struct intel_crtc *crtc);
1432
1433 /* intel_tv.c */
1434 void intel_tv_init(struct drm_device *dev);
1435
1436 /* intel_atomic.c */
1437 int intel_connector_atomic_get_property(struct drm_connector *connector,
1438                                         const struct drm_connector_state *state,
1439                                         struct drm_property *property,
1440                                         uint64_t *val);
1441 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1442 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1443                                struct drm_crtc_state *state);
1444 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1445 void intel_atomic_state_clear(struct drm_atomic_state *);
1446 struct intel_shared_dpll_config *
1447 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1448
1449 static inline struct intel_crtc_state *
1450 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1451                             struct intel_crtc *crtc)
1452 {
1453         struct drm_crtc_state *crtc_state;
1454         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1455         if (IS_ERR(crtc_state))
1456                 return ERR_CAST(crtc_state);
1457
1458         return to_intel_crtc_state(crtc_state);
1459 }
1460 int intel_atomic_setup_scalers(struct drm_device *dev,
1461         struct intel_crtc *intel_crtc,
1462         struct intel_crtc_state *crtc_state);
1463
1464 /* intel_atomic_plane.c */
1465 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1466 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1467 void intel_plane_destroy_state(struct drm_plane *plane,
1468                                struct drm_plane_state *state);
1469 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1470
1471 #endif /* __INTEL_DRV_H__ */