drivers/gpu/drm/i915/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "i915_drv.h"
  26 #include "intel_ringbuffer.h"
  27 #include "intel_lrc.h"
  28
  29 static const struct engine_info {
  30         const char *name;
  31         unsigned exec_id;
  32         enum intel_engine_hw_id hw_id;
  33         u32 mmio_base;
  34         unsigned irq_shift;
  35         int (*init_legacy)(struct intel_engine_cs *engine);
  36         int (*init_execlists)(struct intel_engine_cs *engine);
  37 } intel_engines[] = {
  38         [RCS] = {
  39                 .name = "render ring",
  40                 .exec_id = I915_EXEC_RENDER,
  41                 .hw_id = RCS_HW,
  42                 .mmio_base = RENDER_RING_BASE,
  43                 .irq_shift = GEN8_RCS_IRQ_SHIFT,
  44                 .init_execlists = logical_render_ring_init,
  45                 .init_legacy = intel_init_render_ring_buffer,
  46         },
  47         [BCS] = {
  48                 .name = "blitter ring",
  49                 .exec_id = I915_EXEC_BLT,
  50                 .hw_id = BCS_HW,
  51                 .mmio_base = BLT_RING_BASE,
  52                 .irq_shift = GEN8_BCS_IRQ_SHIFT,
  53                 .init_execlists = logical_xcs_ring_init,
  54                 .init_legacy = intel_init_blt_ring_buffer,
  55         },
  56         [VCS] = {
  57                 .name = "bsd ring",
  58                 .exec_id = I915_EXEC_BSD,
  59                 .hw_id = VCS_HW,
  60                 .mmio_base = GEN6_BSD_RING_BASE,
  61                 .irq_shift = GEN8_VCS1_IRQ_SHIFT,
  62                 .init_execlists = logical_xcs_ring_init,
  63                 .init_legacy = intel_init_bsd_ring_buffer,
  64         },
  65         [VCS2] = {
  66                 .name = "bsd2 ring",
  67                 .exec_id = I915_EXEC_BSD,
  68                 .hw_id = VCS2_HW,
  69                 .mmio_base = GEN8_BSD2_RING_BASE,
  70                 .irq_shift = GEN8_VCS2_IRQ_SHIFT,
  71                 .init_execlists = logical_xcs_ring_init,
  72                 .init_legacy = intel_init_bsd2_ring_buffer,
  73         },
  74         [VECS] = {
  75                 .name = "video enhancement ring",
  76                 .exec_id = I915_EXEC_VEBOX,
  77                 .hw_id = VECS_HW,
  78                 .mmio_base = VEBOX_RING_BASE,
  79                 .irq_shift = GEN8_VECS_IRQ_SHIFT,
  80                 .init_execlists = logical_xcs_ring_init,
  81                 .init_legacy = intel_init_vebox_ring_buffer,
  82         },
  83 };
  84
  85 static struct intel_engine_cs *
  86 intel_engine_setup(struct drm_i915_private *dev_priv,
  87                    enum intel_engine_id id)
  88 {
  89         const struct engine_info *info = &intel_engines[id];
  90         struct intel_engine_cs *engine = &dev_priv->engine[id];
  91
  92         engine->id = id;
  93         engine->i915 = dev_priv;
  94         engine->name = info->name;
  95         engine->exec_id = info->exec_id;
  96         engine->hw_id = engine->guc_id = info->hw_id;
  97         engine->mmio_base = info->mmio_base;
  98         engine->irq_shift = info->irq_shift;
  99
 100         return engine;
 101 }
 102
 103 /**
 104  * intel_engines_init() - allocate, populate and init the Engine Command Streamers
 105  * @dev: DRM device.
 106  *
 107  * Return: non-zero if the initialization failed.
 108  */
 109 int intel_engines_init(struct drm_device *dev)
 110 {
 111         struct drm_i915_private *dev_priv = to_i915(dev);
 112         struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
 113         unsigned int mask = 0;
 114         int (*init)(struct intel_engine_cs *engine);
 115         unsigned int i;
 116         int ret;
 117
 118         WARN_ON(INTEL_INFO(dev_priv)->ring_mask == 0);
 119         WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
 120                 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
 121
 122         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 123                 if (!HAS_ENGINE(dev_priv, i))
 124                         continue;
 125
 126                 if (i915.enable_execlists)
 127                         init = intel_engines[i].init_execlists;
 128                 else
 129                         init = intel_engines[i].init_legacy;
 130
 131                 if (!init)
 132                         continue;
 133
 134                 ret = init(intel_engine_setup(dev_priv, i));
 135                 if (ret)
 136                         goto cleanup;
 137
 138                 mask |= ENGINE_MASK(i);
 139         }
 140
 141         /*
 142          * Catch failures to update intel_engines table when the new engines
 143          * are added to the driver by a warning and disabling the forgotten
 144          * engines.
 145          */
 146         if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
 147                 device_info->ring_mask = mask;
 148
 149         device_info->num_rings = hweight32(mask);
 150
 151         return 0;
 152
 153 cleanup:
 154         for (i = 0; i < I915_NUM_ENGINES; i++) {
 155                 if (i915.enable_execlists)
 156                         intel_logical_ring_cleanup(&dev_priv->engine[i]);
 157                 else
 158                         intel_engine_cleanup(&dev_priv->engine[i]);
 159         }
 160
 161         return ret;
 162 }
 163
 164 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
 165 {
 166         struct drm_i915_private *dev_priv = engine->i915;
 167
 168         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
 169          * so long as the semaphore value in the register/page is greater
 170          * than the sync value), so whenever we reset the seqno,
 171          * so long as we reset the tracking semaphore value to 0, it will
 172          * always be before the next request's seqno. If we don't reset
 173          * the semaphore value, then when the seqno moves backwards all
 174          * future waits will complete instantly (causing rendering corruption).
 175          */
 176         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 177                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
 178                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
 179                 if (HAS_VEBOX(dev_priv))
 180                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
 181         }
 182         if (dev_priv->semaphore) {
 183                 struct page *page = i915_vma_first_page(dev_priv->semaphore);
 184                 void *semaphores;
 185
 186                 /* Semaphores are in noncoherent memory, flush to be safe */
 187                 semaphores = kmap(page);
 188                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 189                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 190                 drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
 191                                        I915_NUM_ENGINES * gen8_semaphore_seqno_size);
 192                 kunmap(page);
 193         }
 194         memset(engine->semaphore.sync_seqno, 0,
 195                sizeof(engine->semaphore.sync_seqno));
 196
 197         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
 198         if (engine->irq_seqno_barrier)
 199                 engine->irq_seqno_barrier(engine);
 200         engine->last_submitted_seqno = seqno;
 201
 202         engine->hangcheck.seqno = seqno;
 203
 204         /* After manually advancing the seqno, fake the interrupt in case
 205          * there are any waiters for that seqno.
 206          */
 207         intel_engine_wakeup(engine);
 208 }
 209
 210 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 211 {
 212         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 213         clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
 214         if (intel_engine_has_waiter(engine))
 215                 i915_queue_hangcheck(engine->i915);
 216 }
 217
 218 static void intel_engine_init_requests(struct intel_engine_cs *engine)
 219 {
 220         init_request_active(&engine->last_request, NULL);
 221         INIT_LIST_HEAD(&engine->request_list);
 222 }
 223
 224 /**
 225  * intel_engines_setup_common - setup engine state not requiring hw access
 226  * @engine: Engine to setup.
 227  *
 228  * Initializes @engine@ structure members shared between legacy and execlists
 229  * submission modes which do not require hardware access.
 230  *
 231  * Typically done early in the submission mode specific engine setup stage.
 232  */
 233 void intel_engine_setup_common(struct intel_engine_cs *engine)
 234 {
 235         INIT_LIST_HEAD(&engine->execlist_queue);
 236         spin_lock_init(&engine->execlist_lock);
 237
 238         engine->fence_context = fence_context_alloc(1);
 239
 240         intel_engine_init_requests(engine);
 241         intel_engine_init_hangcheck(engine);
 242         i915_gem_batch_pool_init(engine, &engine->batch_pool);
 243
 244         intel_engine_init_cmd_parser(engine);
 245 }
 246
 247 int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
 248 {
 249         struct drm_i915_gem_object *obj;
 250         struct i915_vma *vma;
 251         int ret;
 252
 253         WARN_ON(engine->scratch);
 254
 255         obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
 256         if (!obj)
 257                 obj = i915_gem_object_create(&engine->i915->drm, size);
 258         if (IS_ERR(obj)) {
 259                 DRM_ERROR("Failed to allocate scratch page\n");
 260                 return PTR_ERR(obj);
 261         }
 262
 263         vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
 264         if (IS_ERR(vma)) {
 265                 ret = PTR_ERR(vma);
 266                 goto err_unref;
 267         }
 268
 269         ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
 270         if (ret)
 271                 goto err_unref;
 272
 273         engine->scratch = vma;
 274         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 275                          engine->name, i915_ggtt_offset(vma));
 276         return 0;
 277
 278 err_unref:
 279         i915_gem_object_put(obj);
 280         return ret;
 281 }
 282
 283 static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
 284 {
 285         i915_vma_unpin_and_release(&engine->scratch);
 286 }
 287
 288 /**
 289  * intel_engines_init_common - initialize cengine state which might require hw access
 290  * @engine: Engine to initialize.
 291  *
 292  * Initializes @engine@ structure members shared between legacy and execlists
 293  * submission modes which do require hardware access.
 294  *
 295  * Typcally done at later stages of submission mode specific engine setup.
 296  *
 297  * Returns zero on success or an error code on failure.
 298  */
 299 int intel_engine_init_common(struct intel_engine_cs *engine)
 300 {
 301         int ret;
 302
 303         ret = intel_engine_init_breadcrumbs(engine);
 304         if (ret)
 305                 return ret;
 306
 307         return 0;
 308 }
 309
 310 void intel_engine_reset_irq(struct intel_engine_cs *engine)
 311 {
 312         struct drm_i915_private *dev_priv = engine->i915;
 313
 314         spin_lock_irq(&dev_priv->irq_lock);
 315         if (intel_engine_has_waiter(engine))
 316                 engine->irq_enable(engine);
 317         else
 318                 engine->irq_disable(engine);
 319         spin_unlock_irq(&dev_priv->irq_lock);
 320 }
 321
 322 /**
 323  * intel_engines_cleanup_common - cleans up the engine state created by
 324  *                                the common initiailizers.
 325  * @engine: Engine to cleanup.
 326  *
 327  * This cleans up everything created by the common helpers.
 328  */
 329 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 330 {
 331         intel_engine_cleanup_scratch(engine);
 332
 333         intel_engine_fini_breadcrumbs(engine);
 334         intel_engine_cleanup_cmd_parser(engine);
 335         i915_gem_batch_pool_fini(&engine->batch_pool);
 336 }