2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define SKL_FW_MAJOR 6
63 #define SKL_FW_MINOR 1
65 #define BXT_FW_MAJOR 8
66 #define BXT_FW_MINOR 7
68 #define KBL_FW_MAJOR 9
69 #define KBL_FW_MINOR 14
71 #define GUC_FW_PATH(platform, major, minor) \
72 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
74 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
75 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
77 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
78 MODULE_FIRMWARE(I915_BXT_GUC_UCODE
);
80 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
81 MODULE_FIRMWARE(I915_KBL_GUC_UCODE
);
83 /* User-friendly representation of an enum */
84 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
)
87 case GUC_FIRMWARE_FAIL
:
89 case GUC_FIRMWARE_NONE
:
91 case GUC_FIRMWARE_PENDING
:
93 case GUC_FIRMWARE_SUCCESS
:
100 static void direct_interrupts_to_host(struct drm_i915_private
*dev_priv
)
102 struct intel_engine_cs
*engine
;
105 /* tell all command streamers NOT to forward interrupts or vblank to GuC */
106 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
107 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
108 for_each_engine(engine
, dev_priv
)
109 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
111 /* route all GT interrupts to the host */
112 I915_WRITE(GUC_BCS_RCS_IER
, 0);
113 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
114 I915_WRITE(GUC_WD_VECS_IER
, 0);
117 static void direct_interrupts_to_guc(struct drm_i915_private
*dev_priv
)
119 struct intel_engine_cs
*engine
;
123 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
124 irqs
= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
125 for_each_engine(engine
, dev_priv
)
126 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
128 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
129 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
130 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
131 /* These three registers have the same bit definitions */
132 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
133 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
134 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
137 * If GuC has routed PM interrupts to itself, don't keep it.
138 * and keep other interrupts those are unmasked by GuC.
140 tmp
= I915_READ(GEN6_PMINTRMSK
);
141 if (tmp
& GEN8_PMINTR_REDIRECT_TO_NON_DISP
) {
142 dev_priv
->rps
.pm_intr_keep
|= ~(tmp
& ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
143 dev_priv
->rps
.pm_intr_keep
&= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
147 static u32
get_gttype(struct drm_i915_private
*dev_priv
)
149 /* XXX: GT type based on PCI device ID? field seems unused by fw */
153 static u32
get_core_family(struct drm_i915_private
*dev_priv
)
155 u32 gen
= INTEL_GEN(dev_priv
);
159 return GFXCORE_FAMILY_GEN9
;
162 WARN(1, "GEN%d does not support GuC operation!\n", gen
);
163 return GFXCORE_FAMILY_UNKNOWN
;
167 static void set_guc_init_params(struct drm_i915_private
*dev_priv
)
169 struct intel_guc
*guc
= &dev_priv
->guc
;
170 u32 params
[GUC_CTL_MAX_DWORDS
];
173 memset(¶ms
, 0, sizeof(params
));
175 params
[GUC_CTL_DEVICE_INFO
] |=
176 (get_gttype(dev_priv
) << GUC_CTL_GTTYPE_SHIFT
) |
177 (get_core_family(dev_priv
) << GUC_CTL_COREFAMILY_SHIFT
);
180 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
181 * second. This ARAR is calculated by:
182 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
184 params
[GUC_CTL_ARAT_HIGH
] = 0;
185 params
[GUC_CTL_ARAT_LOW
] = 100000000;
187 params
[GUC_CTL_WA
] |= GUC_CTL_WA_UK_BY_DRIVER
;
189 params
[GUC_CTL_FEATURE
] |= GUC_CTL_DISABLE_SCHEDULER
|
190 GUC_CTL_VCS2_ENABLED
;
192 if (i915
.guc_log_level
>= 0) {
193 params
[GUC_CTL_LOG_PARAMS
] = guc
->log_flags
;
194 params
[GUC_CTL_DEBUG
] =
195 i915
.guc_log_level
<< GUC_LOG_VERBOSITY_SHIFT
;
199 u32 ads
= i915_ggtt_offset(guc
->ads_vma
) >> PAGE_SHIFT
;
200 params
[GUC_CTL_DEBUG
] |= ads
<< GUC_ADS_ADDR_SHIFT
;
201 params
[GUC_CTL_DEBUG
] |= GUC_ADS_ENABLED
;
204 /* If GuC submission is enabled, set up additional parameters here */
205 if (i915
.enable_guc_submission
) {
206 u32 pgs
= i915_ggtt_offset(dev_priv
->guc
.ctx_pool_vma
);
207 u32 ctx_in_16
= GUC_MAX_GPU_CONTEXTS
/ 16;
210 params
[GUC_CTL_CTXINFO
] = (pgs
<< GUC_CTL_BASE_ADDR_SHIFT
) |
211 (ctx_in_16
<< GUC_CTL_CTXNUM_IN16_SHIFT
);
213 params
[GUC_CTL_FEATURE
] |= GUC_CTL_KERNEL_SUBMISSIONS
;
215 /* Unmask this bit to enable the GuC's internal scheduler */
216 params
[GUC_CTL_FEATURE
] &= ~GUC_CTL_DISABLE_SCHEDULER
;
219 I915_WRITE(SOFT_SCRATCH(0), 0);
221 for (i
= 0; i
< GUC_CTL_MAX_DWORDS
; i
++)
222 I915_WRITE(SOFT_SCRATCH(1 + i
), params
[i
]);
226 * Read the GuC status register (GUC_STATUS) and store it in the
227 * specified location; then return a boolean indicating whether
228 * the value matches either of two values representing completion
229 * of the GuC boot process.
231 * This is used for polling the GuC status in a wait_for()
234 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
237 u32 val
= I915_READ(GUC_STATUS
);
238 u32 uk_val
= val
& GS_UKERNEL_MASK
;
240 return (uk_val
== GS_UKERNEL_READY
||
241 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
245 * Transfer the firmware image to RAM for execution by the microcontroller.
247 * Architecturally, the DMA engine is bidirectional, and can potentially even
248 * transfer between GTT locations. This functionality is left out of the API
249 * for now as there is no need for it.
251 * Note that GuC needs the CSS header plus uKernel code to be copied by the
252 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
254 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
,
255 struct i915_vma
*vma
)
257 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
258 unsigned long offset
;
259 struct sg_table
*sg
= vma
->pages
;
260 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
263 /* where RSA signature starts */
264 offset
= guc_fw
->rsa_offset
;
266 /* Copy RSA signature from the fw image to HW for verification */
267 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
268 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
269 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
271 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
272 * other components */
273 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
275 /* Set the source address for the new blob */
276 offset
= i915_ggtt_offset(vma
) + guc_fw
->header_offset
;
277 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
278 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
281 * Set the DMA destination. Current uCode expects the code to be
282 * loaded at 8k; locations below this are used for the stack.
284 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
285 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
287 /* Finally start the DMA */
288 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
291 * Wait for the DMA to complete & the GuC to start up.
292 * NB: Docs recommend not using the interrupt for completion.
293 * Measurements indicate this should take no more than 20ms, so a
294 * timeout here indicates that the GuC has failed and is unusable.
295 * (Higher levels of the driver will attempt to fall back to
296 * execlist mode if this happens.)
298 ret
= wait_for(guc_ucode_response(dev_priv
, &status
), 100);
300 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
301 I915_READ(DMA_CTRL
), status
);
303 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
304 DRM_ERROR("GuC firmware signature verification failed\n");
308 DRM_DEBUG_DRIVER("returning %d\n", ret
);
313 static u32
guc_wopcm_size(struct drm_i915_private
*dev_priv
)
315 u32 wopcm_size
= GUC_WOPCM_TOP
;
317 /* On BXT, the top of WOPCM is reserved for RC6 context */
318 if (IS_BROXTON(dev_priv
))
319 wopcm_size
-= BXT_GUC_WOPCM_RC6_RESERVED
;
325 * Load the GuC firmware blob into the MinuteIA.
327 static int guc_ucode_xfer(struct drm_i915_private
*dev_priv
)
329 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
330 struct drm_device
*dev
= &dev_priv
->drm
;
331 struct i915_vma
*vma
;
334 ret
= i915_gem_object_set_to_gtt_domain(guc_fw
->guc_fw_obj
, false);
336 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret
);
340 vma
= i915_gem_object_ggtt_pin(guc_fw
->guc_fw_obj
, NULL
, 0, 0, 0);
342 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma
));
346 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
347 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
349 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
352 I915_WRITE(GUC_WOPCM_SIZE
, guc_wopcm_size(dev_priv
));
353 I915_WRITE(DMA_GUC_WOPCM_OFFSET
, GUC_WOPCM_OFFSET_VALUE
);
355 /* Enable MIA caching. GuC clock gating is disabled. */
356 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
358 /* WaDisableMinuteIaClockGating:skl,bxt */
359 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
360 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
361 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
362 ~GUC_ENABLE_MIA_CLOCK_GATING
));
365 /* WaC6DisallowByGfxPause*/
366 if (IS_SKL_REVID(dev
, 0, SKL_REVID_C0
) ||
367 IS_BXT_REVID(dev
, 0, BXT_REVID_B0
))
368 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
371 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
373 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
376 /* DOP Clock Gating Enable for GuC clocks */
377 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
378 I915_READ(GEN7_MISCCPCTL
)));
380 /* allows for 5us before GT can go to RC6 */
381 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
384 set_guc_init_params(dev_priv
);
386 ret
= guc_ucode_xfer_dma(dev_priv
, vma
);
388 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
391 * We keep the object pages for reuse during resume. But we can unpin it
392 * now that DMA has completed, so it doesn't continue to take up space.
399 static int i915_reset_guc(struct drm_i915_private
*dev_priv
)
404 ret
= intel_guc_reset(dev_priv
);
406 DRM_ERROR("GuC reset failed, ret = %d\n", ret
);
410 guc_status
= I915_READ(GUC_STATUS
);
411 WARN(!(guc_status
& GS_MIA_IN_RESET
),
412 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status
);
418 * intel_guc_setup() - finish preparing the GuC for activity
421 * Called from gem_init_hw() during driver loading and also after a GPU reset.
423 * The main action required here it to load the GuC uCode into the device.
424 * The firmware image should have already been fetched into memory by the
425 * earlier call to intel_guc_init(), so here we need only check that worked,
426 * and then transfer the image to the h/w.
428 * Return: non-zero code on error
430 int intel_guc_setup(struct drm_device
*dev
)
432 struct drm_i915_private
*dev_priv
= to_i915(dev
);
433 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
434 const char *fw_path
= guc_fw
->guc_fw_path
;
435 int retries
, ret
, err
;
437 DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
439 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
440 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
442 /* Loading forbidden, or no firmware to load? */
443 if (!i915
.enable_guc_loading
) {
446 } else if (fw_path
== NULL
) {
447 /* Device is known to have no uCode (e.g. no GuC) */
450 } else if (*fw_path
== '\0') {
451 /* Device has a GuC but we don't know what f/w to load? */
452 WARN(1, "No GuC firmware known for this platform!\n");
457 /* Fetch failed, or already fetched but failed to load? */
458 if (guc_fw
->guc_fw_fetch_status
!= GUC_FIRMWARE_SUCCESS
) {
461 } else if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_FAIL
) {
466 direct_interrupts_to_host(dev_priv
);
468 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_PENDING
;
470 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
471 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
472 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
474 err
= i915_guc_submission_init(dev_priv
);
479 * WaEnableuKernelHeaderValidFix:skl,bxt
480 * For BXT, this is only upto B0 but below WA is required for later
481 * steppings also so this is extended as well.
483 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
484 for (retries
= 3; ; ) {
486 * Always reset the GuC just before (re)loading, so
487 * that the state and timing are fairly predictable
489 err
= i915_reset_guc(dev_priv
);
493 err
= guc_ucode_xfer(dev_priv
);
500 DRM_INFO("GuC fw load failed: %d; will reset and "
501 "retry %d more time(s)\n", err
, retries
);
504 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_SUCCESS
;
506 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
507 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
508 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
510 if (i915
.enable_guc_submission
) {
511 err
= i915_guc_submission_enable(dev_priv
);
514 direct_interrupts_to_guc(dev_priv
);
520 if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_PENDING
)
521 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_FAIL
;
523 direct_interrupts_to_host(dev_priv
);
524 i915_guc_submission_disable(dev_priv
);
525 i915_guc_submission_fini(dev_priv
);
528 * We've failed to load the firmware :(
530 * Decide whether to disable GuC submission and fall back to
531 * execlist mode, and whether to hide the error by returning
532 * zero or to return -EIO, which the caller will treat as a
533 * nonfatal error (i.e. it doesn't prevent driver load, but
534 * marks the GPU as wedged until reset).
536 if (i915
.enable_guc_loading
> 1) {
538 } else if (i915
.enable_guc_submission
> 1) {
544 if (err
== 0 && !HAS_GUC_UCODE(dev
))
545 ; /* Don't mention the GuC! */
547 DRM_INFO("GuC firmware load skipped\n");
548 else if (ret
!= -EIO
)
549 DRM_NOTE("GuC firmware load failed: %d\n", err
);
551 DRM_WARN("GuC firmware load failed: %d\n", err
);
553 if (i915
.enable_guc_submission
) {
555 DRM_INFO("GuC submission without firmware not supported\n");
557 DRM_NOTE("Falling back from GuC submission to execlist mode\n");
559 DRM_ERROR("GuC init failed: %d\n", ret
);
561 i915
.enable_guc_submission
= 0;
566 static void guc_fw_fetch(struct drm_device
*dev
, struct intel_guc_fw
*guc_fw
)
568 struct pci_dev
*pdev
= dev
->pdev
;
569 struct drm_i915_gem_object
*obj
;
570 const struct firmware
*fw
;
571 struct guc_css_header
*css
;
575 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
576 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
578 err
= request_firmware(&fw
, guc_fw
->guc_fw_path
, &pdev
->dev
);
584 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
585 guc_fw
->guc_fw_path
, fw
);
587 /* Check the size of the blob before examining buffer contents */
588 if (fw
->size
< sizeof(struct guc_css_header
)) {
589 DRM_NOTE("Firmware header is missing\n");
593 css
= (struct guc_css_header
*)fw
->data
;
595 /* Firmware bits always start from header */
596 guc_fw
->header_offset
= 0;
597 guc_fw
->header_size
= (css
->header_size_dw
- css
->modulus_size_dw
-
598 css
->key_size_dw
- css
->exponent_size_dw
) * sizeof(u32
);
600 if (guc_fw
->header_size
!= sizeof(struct guc_css_header
)) {
601 DRM_NOTE("CSS header definition mismatch\n");
606 guc_fw
->ucode_offset
= guc_fw
->header_offset
+ guc_fw
->header_size
;
607 guc_fw
->ucode_size
= (css
->size_dw
- css
->header_size_dw
) * sizeof(u32
);
610 if (css
->key_size_dw
!= UOS_RSA_SCRATCH_MAX_COUNT
) {
611 DRM_NOTE("RSA key size is bad\n");
614 guc_fw
->rsa_offset
= guc_fw
->ucode_offset
+ guc_fw
->ucode_size
;
615 guc_fw
->rsa_size
= css
->key_size_dw
* sizeof(u32
);
617 /* At least, it should have header, uCode and RSA. Size of all three. */
618 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
+ guc_fw
->rsa_size
;
619 if (fw
->size
< size
) {
620 DRM_NOTE("Missing firmware components\n");
624 /* Header and uCode will be loaded to WOPCM. Size of the two. */
625 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
;
626 if (size
> guc_wopcm_size(to_i915(dev
))) {
627 DRM_NOTE("Firmware is too large to fit in WOPCM\n");
632 * The GuC firmware image has the version number embedded at a well-known
633 * offset within the firmware blob; note that major / minor version are
634 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
635 * in terms of bytes (u8).
637 guc_fw
->guc_fw_major_found
= css
->guc_sw_version
>> 16;
638 guc_fw
->guc_fw_minor_found
= css
->guc_sw_version
& 0xFFFF;
640 if (guc_fw
->guc_fw_major_found
!= guc_fw
->guc_fw_major_wanted
||
641 guc_fw
->guc_fw_minor_found
< guc_fw
->guc_fw_minor_wanted
) {
642 DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
643 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
644 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
649 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
650 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
651 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
653 mutex_lock(&dev
->struct_mutex
);
654 obj
= i915_gem_object_create_from_data(dev
, fw
->data
, fw
->size
);
655 mutex_unlock(&dev
->struct_mutex
);
656 if (IS_ERR_OR_NULL(obj
)) {
657 err
= obj
? PTR_ERR(obj
) : -ENOMEM
;
661 guc_fw
->guc_fw_obj
= obj
;
662 guc_fw
->guc_fw_size
= fw
->size
;
664 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
667 release_firmware(fw
);
668 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_SUCCESS
;
672 DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
673 guc_fw
->guc_fw_path
, err
);
674 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
675 err
, fw
, guc_fw
->guc_fw_obj
);
677 mutex_lock(&dev
->struct_mutex
);
678 obj
= guc_fw
->guc_fw_obj
;
680 i915_gem_object_put(obj
);
681 guc_fw
->guc_fw_obj
= NULL
;
682 mutex_unlock(&dev
->struct_mutex
);
684 release_firmware(fw
); /* OK even if fw is NULL */
685 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
689 * intel_guc_init() - define parameters and fetch firmware
692 * Called early during driver load, but after GEM is initialised.
694 * The firmware will be transferred to the GuC's memory later,
695 * when intel_guc_setup() is called.
697 void intel_guc_init(struct drm_device
*dev
)
699 struct drm_i915_private
*dev_priv
= to_i915(dev
);
700 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
703 /* A negative value means "use platform default" */
704 if (i915
.enable_guc_loading
< 0)
705 i915
.enable_guc_loading
= HAS_GUC_UCODE(dev
);
706 if (i915
.enable_guc_submission
< 0)
707 i915
.enable_guc_submission
= HAS_GUC_SCHED(dev
);
709 if (!HAS_GUC_UCODE(dev
)) {
711 } else if (IS_SKYLAKE(dev
)) {
712 fw_path
= I915_SKL_GUC_UCODE
;
713 guc_fw
->guc_fw_major_wanted
= SKL_FW_MAJOR
;
714 guc_fw
->guc_fw_minor_wanted
= SKL_FW_MINOR
;
715 } else if (IS_BROXTON(dev
)) {
716 fw_path
= I915_BXT_GUC_UCODE
;
717 guc_fw
->guc_fw_major_wanted
= BXT_FW_MAJOR
;
718 guc_fw
->guc_fw_minor_wanted
= BXT_FW_MINOR
;
719 } else if (IS_KABYLAKE(dev
)) {
720 fw_path
= I915_KBL_GUC_UCODE
;
721 guc_fw
->guc_fw_major_wanted
= KBL_FW_MAJOR
;
722 guc_fw
->guc_fw_minor_wanted
= KBL_FW_MINOR
;
724 fw_path
= ""; /* unknown device */
727 guc_fw
->guc_dev
= dev
;
728 guc_fw
->guc_fw_path
= fw_path
;
729 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;
730 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_NONE
;
732 /* Early (and silent) return if GuC loading is disabled */
733 if (!i915
.enable_guc_loading
)
737 if (*fw_path
== '\0')
740 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_PENDING
;
741 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path
);
742 guc_fw_fetch(dev
, guc_fw
);
743 /* status must now be FAIL or SUCCESS */
747 * intel_guc_fini() - clean up all allocated resources
750 void intel_guc_fini(struct drm_device
*dev
)
752 struct drm_i915_private
*dev_priv
= to_i915(dev
);
753 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
755 mutex_lock(&dev
->struct_mutex
);
756 direct_interrupts_to_host(dev_priv
);
757 i915_guc_submission_disable(dev_priv
);
758 i915_guc_submission_fini(dev_priv
);
760 if (guc_fw
->guc_fw_obj
)
761 i915_gem_object_put(guc_fw
->guc_fw_obj
);
762 guc_fw
->guc_fw_obj
= NULL
;
763 mutex_unlock(&dev
->struct_mutex
);
765 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;