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d8060e6251f8c4b0bdced645919c215c05962f85
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 MISSING_CASE(type);
82 return 0;
83 }
84 }
85
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99 }
100
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 MISSING_CASE(type);
112 return 0;
113 }
114 }
115
116 static i915_reg_t
117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
121 {
122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
125 case HDMI_INFOFRAME_TYPE_SPD:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_VENDOR:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
129 default:
130 MISSING_CASE(type);
131 return INVALID_MMIO_REG;
132 }
133 }
134
135 static void g4x_write_infoframe(struct drm_encoder *encoder,
136 enum hdmi_infoframe_type type,
137 const void *frame, ssize_t len)
138 {
139 const uint32_t *data = frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 u32 val = I915_READ(VIDEO_DIP_CTL);
143 int i;
144
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(type);
149
150 val &= ~g4x_infoframe_enable(type);
151
152 I915_WRITE(VIDEO_DIP_CTL, val);
153
154 mmiowb();
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
162 mmiowb();
163
164 val |= g4x_infoframe_enable(type);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
167
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
170 }
171
172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
174 {
175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
181
182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
187 }
188
189 static void ibx_write_infoframe(struct drm_encoder *encoder,
190 enum hdmi_infoframe_type type,
191 const void *frame, ssize_t len)
192 {
193 const uint32_t *data = frame;
194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
198 u32 val = I915_READ(reg);
199 int i;
200
201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
204 val |= g4x_infoframe_index(type);
205
206 val &= ~g4x_infoframe_enable(type);
207
208 I915_WRITE(reg, val);
209
210 mmiowb();
211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
218 mmiowb();
219
220 val |= g4x_infoframe_enable(type);
221 val &= ~VIDEO_DIP_FREQ_MASK;
222 val |= VIDEO_DIP_FREQ_VSYNC;
223
224 I915_WRITE(reg, val);
225 POSTING_READ(reg);
226 }
227
228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
230 {
231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
235 u32 val = I915_READ(reg);
236
237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
239
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
242
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
246 }
247
248 static void cpt_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
251 {
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
258 int i;
259
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
264
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
269
270 I915_WRITE(reg, val);
271
272 mmiowb();
273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
280 mmiowb();
281
282 val |= g4x_infoframe_enable(type);
283 val &= ~VIDEO_DIP_FREQ_MASK;
284 val |= VIDEO_DIP_FREQ_VSYNC;
285
286 I915_WRITE(reg, val);
287 POSTING_READ(reg);
288 }
289
290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
292 {
293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
296
297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
303 }
304
305 static void vlv_write_infoframe(struct drm_encoder *encoder,
306 enum hdmi_infoframe_type type,
307 const void *frame, ssize_t len)
308 {
309 const uint32_t *data = frame;
310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
314 u32 val = I915_READ(reg);
315 int i;
316
317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
321
322 val &= ~g4x_infoframe_enable(type);
323
324 I915_WRITE(reg, val);
325
326 mmiowb();
327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
334 mmiowb();
335
336 val |= g4x_infoframe_enable(type);
337 val &= ~VIDEO_DIP_FREQ_MASK;
338 val |= VIDEO_DIP_FREQ_VSYNC;
339
340 I915_WRITE(reg, val);
341 POSTING_READ(reg);
342 }
343
344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
346 {
347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
351
352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
357
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
361 }
362
363 static void hsw_write_infoframe(struct drm_encoder *encoder,
364 enum hdmi_infoframe_type type,
365 const void *frame, ssize_t len)
366 {
367 const uint32_t *data = frame;
368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
374 int i;
375 u32 val = I915_READ(ctl_reg);
376
377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
378
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
381
382 mmiowb();
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
386 data++;
387 }
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
392 mmiowb();
393
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
397 }
398
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
401 {
402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
404
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
408 }
409
410 /*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
429 {
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
433
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
445
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
447 }
448
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 const struct drm_display_mode *adjusted_mode)
451 {
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
455 int ret;
456
457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
463
464 if (intel_hdmi->rgb_quant_range_selectable) {
465 if (intel_crtc->config->limited_color_range)
466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
468 else
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
471 }
472
473 intel_write_infoframe(encoder, &frame);
474 }
475
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
477 {
478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
486
487 frame.spd.sdi = HDMI_SPD_SDI_PC;
488
489 intel_write_infoframe(encoder, &frame);
490 }
491
492 static void
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
494 const struct drm_display_mode *adjusted_mode)
495 {
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505 }
506
507 static void g4x_set_infoframes(struct drm_encoder *encoder,
508 bool enable,
509 const struct drm_display_mode *adjusted_mode)
510 {
511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
514 i915_reg_t reg = VIDEO_DIP_CTL;
515 u32 val = I915_READ(reg);
516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
517
518 assert_hdmi_port_disabled(intel_hdmi);
519
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
531 if (!enable) {
532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
541 I915_WRITE(reg, val);
542 POSTING_READ(reg);
543 return;
544 }
545
546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
556 val |= VIDEO_DIP_ENABLE;
557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
559
560 I915_WRITE(reg, val);
561 POSTING_READ(reg);
562
563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
566 }
567
568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569 {
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585 }
586
587 /*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599 {
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628 }
629
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631 {
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
634 i915_reg_t reg;
635 u32 val = 0;
636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv->dev))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
655 I915_WRITE(reg, val);
656
657 return val != 0;
658 }
659
660 static void ibx_set_infoframes(struct drm_encoder *encoder,
661 bool enable,
662 const struct drm_display_mode *adjusted_mode)
663 {
664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
669 u32 val = I915_READ(reg);
670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
671
672 assert_hdmi_port_disabled(intel_hdmi);
673
674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
677 if (!enable) {
678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
683 I915_WRITE(reg, val);
684 POSTING_READ(reg);
685 return;
686 }
687
688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
696 val |= VIDEO_DIP_ENABLE;
697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
700
701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
704 I915_WRITE(reg, val);
705 POSTING_READ(reg);
706
707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
710 }
711
712 static void cpt_set_infoframes(struct drm_encoder *encoder,
713 bool enable,
714 const struct drm_display_mode *adjusted_mode)
715 {
716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
720 u32 val = I915_READ(reg);
721
722 assert_hdmi_port_disabled(intel_hdmi);
723
724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
727 if (!enable) {
728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733 I915_WRITE(reg, val);
734 POSTING_READ(reg);
735 return;
736 }
737
738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
742
743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
746 I915_WRITE(reg, val);
747 POSTING_READ(reg);
748
749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
752 }
753
754 static void vlv_set_infoframes(struct drm_encoder *encoder,
755 bool enable,
756 const struct drm_display_mode *adjusted_mode)
757 {
758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
763 u32 val = I915_READ(reg);
764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
765
766 assert_hdmi_port_disabled(intel_hdmi);
767
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
771 if (!enable) {
772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
778 POSTING_READ(reg);
779 return;
780 }
781
782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
790 val |= VIDEO_DIP_ENABLE;
791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
794
795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
798 I915_WRITE(reg, val);
799 POSTING_READ(reg);
800
801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
804 }
805
806 static void hsw_set_infoframes(struct drm_encoder *encoder,
807 bool enable,
808 const struct drm_display_mode *adjusted_mode)
809 {
810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
814 u32 val = I915_READ(reg);
815
816 assert_hdmi_port_disabled(intel_hdmi);
817
818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
822 if (!enable) {
823 I915_WRITE(reg, val);
824 POSTING_READ(reg);
825 return;
826 }
827
828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
831 I915_WRITE(reg, val);
832 POSTING_READ(reg);
833
834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
837 }
838
839 static void intel_hdmi_prepare(struct intel_encoder *encoder)
840 {
841 struct drm_device *dev = encoder->base.dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
844 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
846 u32 hdmi_val;
847
848 hdmi_val = SDVO_ENCODING_HDMI;
849 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
850 hdmi_val |= HDMI_COLOR_RANGE_16_235;
851 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
852 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
854 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
855
856 if (crtc->config->pipe_bpp > 24)
857 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
858 else
859 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
860
861 if (crtc->config->has_hdmi_sink)
862 hdmi_val |= HDMI_MODE_SELECT_HDMI;
863
864 if (HAS_PCH_CPT(dev))
865 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
866 else if (IS_CHERRYVIEW(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
868 else
869 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
870
871 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
872 POSTING_READ(intel_hdmi->hdmi_reg);
873 }
874
875 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
876 enum pipe *pipe)
877 {
878 struct drm_device *dev = encoder->base.dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
881 enum intel_display_power_domain power_domain;
882 u32 tmp;
883 bool ret;
884
885 power_domain = intel_display_port_power_domain(encoder);
886 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
887 return false;
888
889 ret = false;
890
891 tmp = I915_READ(intel_hdmi->hdmi_reg);
892
893 if (!(tmp & SDVO_ENABLE))
894 goto out;
895
896 if (HAS_PCH_CPT(dev))
897 *pipe = PORT_TO_PIPE_CPT(tmp);
898 else if (IS_CHERRYVIEW(dev))
899 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
900 else
901 *pipe = PORT_TO_PIPE(tmp);
902
903 ret = true;
904
905 out:
906 intel_display_power_put(dev_priv, power_domain);
907
908 return ret;
909 }
910
911 static void intel_hdmi_get_config(struct intel_encoder *encoder,
912 struct intel_crtc_state *pipe_config)
913 {
914 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
915 struct drm_device *dev = encoder->base.dev;
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 u32 tmp, flags = 0;
918 int dotclock;
919
920 tmp = I915_READ(intel_hdmi->hdmi_reg);
921
922 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
923 flags |= DRM_MODE_FLAG_PHSYNC;
924 else
925 flags |= DRM_MODE_FLAG_NHSYNC;
926
927 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
928 flags |= DRM_MODE_FLAG_PVSYNC;
929 else
930 flags |= DRM_MODE_FLAG_NVSYNC;
931
932 if (tmp & HDMI_MODE_SELECT_HDMI)
933 pipe_config->has_hdmi_sink = true;
934
935 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
936 pipe_config->has_infoframe = true;
937
938 if (tmp & SDVO_AUDIO_ENABLE)
939 pipe_config->has_audio = true;
940
941 if (!HAS_PCH_SPLIT(dev) &&
942 tmp & HDMI_COLOR_RANGE_16_235)
943 pipe_config->limited_color_range = true;
944
945 pipe_config->base.adjusted_mode.flags |= flags;
946
947 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
948 dotclock = pipe_config->port_clock * 2 / 3;
949 else
950 dotclock = pipe_config->port_clock;
951
952 if (pipe_config->pixel_multiplier)
953 dotclock /= pipe_config->pixel_multiplier;
954
955 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
956 }
957
958 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
959 {
960 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
961
962 WARN_ON(!crtc->config->has_hdmi_sink);
963 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
964 pipe_name(crtc->pipe));
965 intel_audio_codec_enable(encoder);
966 }
967
968 static void g4x_enable_hdmi(struct intel_encoder *encoder)
969 {
970 struct drm_device *dev = encoder->base.dev;
971 struct drm_i915_private *dev_priv = dev->dev_private;
972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
974 u32 temp;
975
976 temp = I915_READ(intel_hdmi->hdmi_reg);
977
978 temp |= SDVO_ENABLE;
979 if (crtc->config->has_audio)
980 temp |= SDVO_AUDIO_ENABLE;
981
982 I915_WRITE(intel_hdmi->hdmi_reg, temp);
983 POSTING_READ(intel_hdmi->hdmi_reg);
984
985 if (crtc->config->has_audio)
986 intel_enable_hdmi_audio(encoder);
987 }
988
989 static void ibx_enable_hdmi(struct intel_encoder *encoder)
990 {
991 struct drm_device *dev = encoder->base.dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
994 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
995 u32 temp;
996
997 temp = I915_READ(intel_hdmi->hdmi_reg);
998
999 temp |= SDVO_ENABLE;
1000 if (crtc->config->has_audio)
1001 temp |= SDVO_AUDIO_ENABLE;
1002
1003 /*
1004 * HW workaround, need to write this twice for issue
1005 * that may result in first write getting masked.
1006 */
1007 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1008 POSTING_READ(intel_hdmi->hdmi_reg);
1009 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1010 POSTING_READ(intel_hdmi->hdmi_reg);
1011
1012 /*
1013 * HW workaround, need to toggle enable bit off and on
1014 * for 12bpc with pixel repeat.
1015 *
1016 * FIXME: BSpec says this should be done at the end of
1017 * of the modeset sequence, so not sure if this isn't too soon.
1018 */
1019 if (crtc->config->pipe_bpp > 24 &&
1020 crtc->config->pixel_multiplier > 1) {
1021 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1022 POSTING_READ(intel_hdmi->hdmi_reg);
1023
1024 /*
1025 * HW workaround, need to write this twice for issue
1026 * that may result in first write getting masked.
1027 */
1028 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1029 POSTING_READ(intel_hdmi->hdmi_reg);
1030 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1031 POSTING_READ(intel_hdmi->hdmi_reg);
1032 }
1033
1034 if (crtc->config->has_audio)
1035 intel_enable_hdmi_audio(encoder);
1036 }
1037
1038 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1039 {
1040 struct drm_device *dev = encoder->base.dev;
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1043 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1044 enum pipe pipe = crtc->pipe;
1045 u32 temp;
1046
1047 temp = I915_READ(intel_hdmi->hdmi_reg);
1048
1049 temp |= SDVO_ENABLE;
1050 if (crtc->config->has_audio)
1051 temp |= SDVO_AUDIO_ENABLE;
1052
1053 /*
1054 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1055 *
1056 * The procedure for 12bpc is as follows:
1057 * 1. disable HDMI clock gating
1058 * 2. enable HDMI with 8bpc
1059 * 3. enable HDMI with 12bpc
1060 * 4. enable HDMI clock gating
1061 */
1062
1063 if (crtc->config->pipe_bpp > 24) {
1064 I915_WRITE(TRANS_CHICKEN1(pipe),
1065 I915_READ(TRANS_CHICKEN1(pipe)) |
1066 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1067
1068 temp &= ~SDVO_COLOR_FORMAT_MASK;
1069 temp |= SDVO_COLOR_FORMAT_8bpc;
1070 }
1071
1072 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1073 POSTING_READ(intel_hdmi->hdmi_reg);
1074
1075 if (crtc->config->pipe_bpp > 24) {
1076 temp &= ~SDVO_COLOR_FORMAT_MASK;
1077 temp |= HDMI_COLOR_FORMAT_12bpc;
1078
1079 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1080 POSTING_READ(intel_hdmi->hdmi_reg);
1081
1082 I915_WRITE(TRANS_CHICKEN1(pipe),
1083 I915_READ(TRANS_CHICKEN1(pipe)) &
1084 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1085 }
1086
1087 if (crtc->config->has_audio)
1088 intel_enable_hdmi_audio(encoder);
1089 }
1090
1091 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1092 {
1093 }
1094
1095 static void intel_disable_hdmi(struct intel_encoder *encoder)
1096 {
1097 struct drm_device *dev = encoder->base.dev;
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1100 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1101 u32 temp;
1102
1103 temp = I915_READ(intel_hdmi->hdmi_reg);
1104
1105 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1106 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1107 POSTING_READ(intel_hdmi->hdmi_reg);
1108
1109 /*
1110 * HW workaround for IBX, we need to move the port
1111 * to transcoder A after disabling it to allow the
1112 * matching DP port to be enabled on transcoder A.
1113 */
1114 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1115 /*
1116 * We get CPU/PCH FIFO underruns on the other pipe when
1117 * doing the workaround. Sweep them under the rug.
1118 */
1119 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1120 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1121
1122 temp &= ~SDVO_PIPE_B_SELECT;
1123 temp |= SDVO_ENABLE;
1124 /*
1125 * HW workaround, need to write this twice for issue
1126 * that may result in first write getting masked.
1127 */
1128 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1129 POSTING_READ(intel_hdmi->hdmi_reg);
1130 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1131 POSTING_READ(intel_hdmi->hdmi_reg);
1132
1133 temp &= ~SDVO_ENABLE;
1134 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1135 POSTING_READ(intel_hdmi->hdmi_reg);
1136
1137 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1138 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1139 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1140 }
1141
1142 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1143 }
1144
1145 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1146 {
1147 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1148
1149 if (crtc->config->has_audio)
1150 intel_audio_codec_disable(encoder);
1151
1152 intel_disable_hdmi(encoder);
1153 }
1154
1155 static void pch_disable_hdmi(struct intel_encoder *encoder)
1156 {
1157 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1158
1159 if (crtc->config->has_audio)
1160 intel_audio_codec_disable(encoder);
1161 }
1162
1163 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1164 {
1165 intel_disable_hdmi(encoder);
1166 }
1167
1168 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1169 {
1170 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1171
1172 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1173 return 165000;
1174 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1175 return 300000;
1176 else
1177 return 225000;
1178 }
1179
1180 static enum drm_mode_status
1181 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1182 int clock, bool respect_dvi_limit)
1183 {
1184 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1185
1186 if (clock < 25000)
1187 return MODE_CLOCK_LOW;
1188 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1189 return MODE_CLOCK_HIGH;
1190
1191 /* BXT DPLL can't generate 223-240 MHz */
1192 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1193 return MODE_CLOCK_RANGE;
1194
1195 /* CHV DPLL can't generate 216-240 MHz */
1196 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1197 return MODE_CLOCK_RANGE;
1198
1199 return MODE_OK;
1200 }
1201
1202 static enum drm_mode_status
1203 intel_hdmi_mode_valid(struct drm_connector *connector,
1204 struct drm_display_mode *mode)
1205 {
1206 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1207 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1208 enum drm_mode_status status;
1209 int clock;
1210 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1211
1212 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1213 return MODE_NO_DBLESCAN;
1214
1215 clock = mode->clock;
1216
1217 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1218 clock *= 2;
1219
1220 if (clock > max_dotclk)
1221 return MODE_CLOCK_HIGH;
1222
1223 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1224 clock *= 2;
1225
1226 /* check if we can do 8bpc */
1227 status = hdmi_port_clock_valid(hdmi, clock, true);
1228
1229 /* if we can't do 8bpc we may still be able to do 12bpc */
1230 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1231 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1232
1233 return status;
1234 }
1235
1236 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1237 {
1238 struct drm_device *dev = crtc_state->base.crtc->dev;
1239 struct drm_atomic_state *state;
1240 struct intel_encoder *encoder;
1241 struct drm_connector *connector;
1242 struct drm_connector_state *connector_state;
1243 int count = 0, count_hdmi = 0;
1244 int i;
1245
1246 if (HAS_GMCH_DISPLAY(dev))
1247 return false;
1248
1249 state = crtc_state->base.state;
1250
1251 for_each_connector_in_state(state, connector, connector_state, i) {
1252 if (connector_state->crtc != crtc_state->base.crtc)
1253 continue;
1254
1255 encoder = to_intel_encoder(connector_state->best_encoder);
1256
1257 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1258 count++;
1259 }
1260
1261 /*
1262 * HDMI 12bpc affects the clocks, so it's only possible
1263 * when not cloning with other encoder types.
1264 */
1265 return count_hdmi > 0 && count_hdmi == count;
1266 }
1267
1268 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1269 struct intel_crtc_state *pipe_config)
1270 {
1271 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1272 struct drm_device *dev = encoder->base.dev;
1273 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1274 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1275 int clock_12bpc = clock_8bpc * 3 / 2;
1276 int desired_bpp;
1277
1278 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1279
1280 if (pipe_config->has_hdmi_sink)
1281 pipe_config->has_infoframe = true;
1282
1283 if (intel_hdmi->color_range_auto) {
1284 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1285 pipe_config->limited_color_range =
1286 pipe_config->has_hdmi_sink &&
1287 drm_match_cea_mode(adjusted_mode) > 1;
1288 } else {
1289 pipe_config->limited_color_range =
1290 intel_hdmi->limited_color_range;
1291 }
1292
1293 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1294 pipe_config->pixel_multiplier = 2;
1295 clock_8bpc *= 2;
1296 clock_12bpc *= 2;
1297 }
1298
1299 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1300 pipe_config->has_pch_encoder = true;
1301
1302 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1303 pipe_config->has_audio = true;
1304
1305 /*
1306 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1307 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1308 * outputs. We also need to check that the higher clock still fits
1309 * within limits.
1310 */
1311 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1312 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1313 hdmi_12bpc_possible(pipe_config)) {
1314 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1315 desired_bpp = 12*3;
1316
1317 /* Need to adjust the port link by 1.5x for 12bpc. */
1318 pipe_config->port_clock = clock_12bpc;
1319 } else {
1320 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1321 desired_bpp = 8*3;
1322
1323 pipe_config->port_clock = clock_8bpc;
1324 }
1325
1326 if (!pipe_config->bw_constrained) {
1327 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1328 pipe_config->pipe_bpp = desired_bpp;
1329 }
1330
1331 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1332 false) != MODE_OK) {
1333 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1334 return false;
1335 }
1336
1337 /* Set user selected PAR to incoming mode's member */
1338 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1339
1340 return true;
1341 }
1342
1343 static void
1344 intel_hdmi_unset_edid(struct drm_connector *connector)
1345 {
1346 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1347
1348 intel_hdmi->has_hdmi_sink = false;
1349 intel_hdmi->has_audio = false;
1350 intel_hdmi->rgb_quant_range_selectable = false;
1351
1352 kfree(to_intel_connector(connector)->detect_edid);
1353 to_intel_connector(connector)->detect_edid = NULL;
1354 }
1355
1356 static bool
1357 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1358 {
1359 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1360 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1361 struct edid *edid = NULL;
1362 bool connected = false;
1363
1364 if (force) {
1365 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1366
1367 edid = drm_get_edid(connector,
1368 intel_gmbus_get_adapter(dev_priv,
1369 intel_hdmi->ddc_bus));
1370
1371 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1372 }
1373
1374 to_intel_connector(connector)->detect_edid = edid;
1375 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1376 intel_hdmi->rgb_quant_range_selectable =
1377 drm_rgb_quant_range_selectable(edid);
1378
1379 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1380 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1381 intel_hdmi->has_audio =
1382 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1383
1384 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1385 intel_hdmi->has_hdmi_sink =
1386 drm_detect_hdmi_monitor(edid);
1387
1388 connected = true;
1389 }
1390
1391 return connected;
1392 }
1393
1394 static enum drm_connector_status
1395 intel_hdmi_detect(struct drm_connector *connector, bool force)
1396 {
1397 enum drm_connector_status status;
1398 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1399 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1400 bool live_status = false;
1401 unsigned int try;
1402
1403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1404 connector->base.id, connector->name);
1405
1406 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1407
1408 for (try = 0; !live_status && try < 9; try++) {
1409 if (try)
1410 msleep(10);
1411 live_status = intel_digital_port_connected(dev_priv,
1412 hdmi_to_dig_port(intel_hdmi));
1413 }
1414
1415 if (!live_status)
1416 DRM_DEBUG_KMS("Live status not up!");
1417
1418 intel_hdmi_unset_edid(connector);
1419
1420 if (intel_hdmi_set_edid(connector, live_status)) {
1421 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1422
1423 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1424 status = connector_status_connected;
1425 } else
1426 status = connector_status_disconnected;
1427
1428 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1429
1430 return status;
1431 }
1432
1433 static void
1434 intel_hdmi_force(struct drm_connector *connector)
1435 {
1436 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1437
1438 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1439 connector->base.id, connector->name);
1440
1441 intel_hdmi_unset_edid(connector);
1442
1443 if (connector->status != connector_status_connected)
1444 return;
1445
1446 intel_hdmi_set_edid(connector, true);
1447 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1448 }
1449
1450 static int intel_hdmi_get_modes(struct drm_connector *connector)
1451 {
1452 struct edid *edid;
1453
1454 edid = to_intel_connector(connector)->detect_edid;
1455 if (edid == NULL)
1456 return 0;
1457
1458 return intel_connector_update_modes(connector, edid);
1459 }
1460
1461 static bool
1462 intel_hdmi_detect_audio(struct drm_connector *connector)
1463 {
1464 bool has_audio = false;
1465 struct edid *edid;
1466
1467 edid = to_intel_connector(connector)->detect_edid;
1468 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1469 has_audio = drm_detect_monitor_audio(edid);
1470
1471 return has_audio;
1472 }
1473
1474 static int
1475 intel_hdmi_set_property(struct drm_connector *connector,
1476 struct drm_property *property,
1477 uint64_t val)
1478 {
1479 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1480 struct intel_digital_port *intel_dig_port =
1481 hdmi_to_dig_port(intel_hdmi);
1482 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1483 int ret;
1484
1485 ret = drm_object_property_set_value(&connector->base, property, val);
1486 if (ret)
1487 return ret;
1488
1489 if (property == dev_priv->force_audio_property) {
1490 enum hdmi_force_audio i = val;
1491 bool has_audio;
1492
1493 if (i == intel_hdmi->force_audio)
1494 return 0;
1495
1496 intel_hdmi->force_audio = i;
1497
1498 if (i == HDMI_AUDIO_AUTO)
1499 has_audio = intel_hdmi_detect_audio(connector);
1500 else
1501 has_audio = (i == HDMI_AUDIO_ON);
1502
1503 if (i == HDMI_AUDIO_OFF_DVI)
1504 intel_hdmi->has_hdmi_sink = 0;
1505
1506 intel_hdmi->has_audio = has_audio;
1507 goto done;
1508 }
1509
1510 if (property == dev_priv->broadcast_rgb_property) {
1511 bool old_auto = intel_hdmi->color_range_auto;
1512 bool old_range = intel_hdmi->limited_color_range;
1513
1514 switch (val) {
1515 case INTEL_BROADCAST_RGB_AUTO:
1516 intel_hdmi->color_range_auto = true;
1517 break;
1518 case INTEL_BROADCAST_RGB_FULL:
1519 intel_hdmi->color_range_auto = false;
1520 intel_hdmi->limited_color_range = false;
1521 break;
1522 case INTEL_BROADCAST_RGB_LIMITED:
1523 intel_hdmi->color_range_auto = false;
1524 intel_hdmi->limited_color_range = true;
1525 break;
1526 default:
1527 return -EINVAL;
1528 }
1529
1530 if (old_auto == intel_hdmi->color_range_auto &&
1531 old_range == intel_hdmi->limited_color_range)
1532 return 0;
1533
1534 goto done;
1535 }
1536
1537 if (property == connector->dev->mode_config.aspect_ratio_property) {
1538 switch (val) {
1539 case DRM_MODE_PICTURE_ASPECT_NONE:
1540 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1541 break;
1542 case DRM_MODE_PICTURE_ASPECT_4_3:
1543 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1544 break;
1545 case DRM_MODE_PICTURE_ASPECT_16_9:
1546 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551 goto done;
1552 }
1553
1554 return -EINVAL;
1555
1556 done:
1557 if (intel_dig_port->base.base.crtc)
1558 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1559
1560 return 0;
1561 }
1562
1563 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1564 {
1565 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1566 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1567 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1568
1569 intel_hdmi_prepare(encoder);
1570
1571 intel_hdmi->set_infoframes(&encoder->base,
1572 intel_crtc->config->has_hdmi_sink,
1573 adjusted_mode);
1574 }
1575
1576 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1577 {
1578 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1579 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1580 struct drm_device *dev = encoder->base.dev;
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct intel_crtc *intel_crtc =
1583 to_intel_crtc(encoder->base.crtc);
1584 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1585 enum dpio_channel port = vlv_dport_to_channel(dport);
1586 int pipe = intel_crtc->pipe;
1587 u32 val;
1588
1589 /* Enable clock channels for this port */
1590 mutex_lock(&dev_priv->sb_lock);
1591 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1592 val = 0;
1593 if (pipe)
1594 val |= (1<<21);
1595 else
1596 val &= ~(1<<21);
1597 val |= 0x001000c4;
1598 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1599
1600 /* HDMI 1.0V-2dB */
1601 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1602 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1603 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1604 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1605 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1606 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1607 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1608 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1609
1610 /* Program lane clock */
1611 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1612 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1613 mutex_unlock(&dev_priv->sb_lock);
1614
1615 intel_hdmi->set_infoframes(&encoder->base,
1616 intel_crtc->config->has_hdmi_sink,
1617 adjusted_mode);
1618
1619 g4x_enable_hdmi(encoder);
1620
1621 vlv_wait_port_ready(dev_priv, dport, 0x0);
1622 }
1623
1624 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1625 {
1626 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1627 struct drm_device *dev = encoder->base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 struct intel_crtc *intel_crtc =
1630 to_intel_crtc(encoder->base.crtc);
1631 enum dpio_channel port = vlv_dport_to_channel(dport);
1632 int pipe = intel_crtc->pipe;
1633
1634 intel_hdmi_prepare(encoder);
1635
1636 /* Program Tx lane resets to default */
1637 mutex_lock(&dev_priv->sb_lock);
1638 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1639 DPIO_PCS_TX_LANE2_RESET |
1640 DPIO_PCS_TX_LANE1_RESET);
1641 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1642 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1643 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1644 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1645 DPIO_PCS_CLK_SOFT_RESET);
1646
1647 /* Fix up inter-pair skew failure */
1648 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1649 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1650 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1651
1652 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1653 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1654 mutex_unlock(&dev_priv->sb_lock);
1655 }
1656
1657 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1658 bool reset)
1659 {
1660 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1661 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1662 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1663 enum pipe pipe = crtc->pipe;
1664 uint32_t val;
1665
1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1667 if (reset)
1668 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1669 else
1670 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1671 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1672
1673 if (crtc->config->lane_count > 2) {
1674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1675 if (reset)
1676 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1677 else
1678 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1679 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1680 }
1681
1682 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1683 val |= CHV_PCS_REQ_SOFTRESET_EN;
1684 if (reset)
1685 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1686 else
1687 val |= DPIO_PCS_CLK_SOFT_RESET;
1688 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1689
1690 if (crtc->config->lane_count > 2) {
1691 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1692 val |= CHV_PCS_REQ_SOFTRESET_EN;
1693 if (reset)
1694 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1695 else
1696 val |= DPIO_PCS_CLK_SOFT_RESET;
1697 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1698 }
1699 }
1700
1701 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1702 {
1703 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1704 struct drm_device *dev = encoder->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 struct intel_crtc *intel_crtc =
1707 to_intel_crtc(encoder->base.crtc);
1708 enum dpio_channel ch = vlv_dport_to_channel(dport);
1709 enum pipe pipe = intel_crtc->pipe;
1710 u32 val;
1711
1712 intel_hdmi_prepare(encoder);
1713
1714 /*
1715 * Must trick the second common lane into life.
1716 * Otherwise we can't even access the PLL.
1717 */
1718 if (ch == DPIO_CH0 && pipe == PIPE_B)
1719 dport->release_cl2_override =
1720 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1721
1722 chv_phy_powergate_lanes(encoder, true, 0x0);
1723
1724 mutex_lock(&dev_priv->sb_lock);
1725
1726 /* Assert data lane reset */
1727 chv_data_lane_soft_reset(encoder, true);
1728
1729 /* program left/right clock distribution */
1730 if (pipe != PIPE_B) {
1731 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1732 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1733 if (ch == DPIO_CH0)
1734 val |= CHV_BUFLEFTENA1_FORCE;
1735 if (ch == DPIO_CH1)
1736 val |= CHV_BUFRIGHTENA1_FORCE;
1737 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1738 } else {
1739 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1740 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1741 if (ch == DPIO_CH0)
1742 val |= CHV_BUFLEFTENA2_FORCE;
1743 if (ch == DPIO_CH1)
1744 val |= CHV_BUFRIGHTENA2_FORCE;
1745 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1746 }
1747
1748 /* program clock channel usage */
1749 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1750 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1751 if (pipe != PIPE_B)
1752 val &= ~CHV_PCS_USEDCLKCHANNEL;
1753 else
1754 val |= CHV_PCS_USEDCLKCHANNEL;
1755 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1756
1757 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1758 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1759 if (pipe != PIPE_B)
1760 val &= ~CHV_PCS_USEDCLKCHANNEL;
1761 else
1762 val |= CHV_PCS_USEDCLKCHANNEL;
1763 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1764
1765 /*
1766 * This a a bit weird since generally CL
1767 * matches the pipe, but here we need to
1768 * pick the CL based on the port.
1769 */
1770 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1771 if (pipe != PIPE_B)
1772 val &= ~CHV_CMN_USEDCLKCHANNEL;
1773 else
1774 val |= CHV_CMN_USEDCLKCHANNEL;
1775 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1776
1777 mutex_unlock(&dev_priv->sb_lock);
1778 }
1779
1780 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1781 {
1782 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1783 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1784 u32 val;
1785
1786 mutex_lock(&dev_priv->sb_lock);
1787
1788 /* disable left/right clock distribution */
1789 if (pipe != PIPE_B) {
1790 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1791 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1792 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1793 } else {
1794 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1795 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1796 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1797 }
1798
1799 mutex_unlock(&dev_priv->sb_lock);
1800
1801 /*
1802 * Leave the power down bit cleared for at least one
1803 * lane so that chv_powergate_phy_ch() will power
1804 * on something when the channel is otherwise unused.
1805 * When the port is off and the override is removed
1806 * the lanes power down anyway, so otherwise it doesn't
1807 * really matter what the state of power down bits is
1808 * after this.
1809 */
1810 chv_phy_powergate_lanes(encoder, false, 0x0);
1811 }
1812
1813 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1814 {
1815 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1816 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1817 struct intel_crtc *intel_crtc =
1818 to_intel_crtc(encoder->base.crtc);
1819 enum dpio_channel port = vlv_dport_to_channel(dport);
1820 int pipe = intel_crtc->pipe;
1821
1822 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1823 mutex_lock(&dev_priv->sb_lock);
1824 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1825 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1826 mutex_unlock(&dev_priv->sb_lock);
1827 }
1828
1829 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1830 {
1831 struct drm_device *dev = encoder->base.dev;
1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Assert data lane reset */
1837 chv_data_lane_soft_reset(encoder, true);
1838
1839 mutex_unlock(&dev_priv->sb_lock);
1840 }
1841
1842 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1843 {
1844 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1845 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1846 struct drm_device *dev = encoder->base.dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct intel_crtc *intel_crtc =
1849 to_intel_crtc(encoder->base.crtc);
1850 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1851 enum dpio_channel ch = vlv_dport_to_channel(dport);
1852 int pipe = intel_crtc->pipe;
1853 int data, i, stagger;
1854 u32 val;
1855
1856 mutex_lock(&dev_priv->sb_lock);
1857
1858 /* allow hardware to manage TX FIFO reset source */
1859 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1860 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1861 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1862
1863 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1864 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1865 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1866
1867 /* Program Tx latency optimal setting */
1868 for (i = 0; i < 4; i++) {
1869 /* Set the upar bit */
1870 data = (i == 1) ? 0x0 : 0x1;
1871 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1872 data << DPIO_UPAR_SHIFT);
1873 }
1874
1875 /* Data lane stagger programming */
1876 if (intel_crtc->config->port_clock > 270000)
1877 stagger = 0x18;
1878 else if (intel_crtc->config->port_clock > 135000)
1879 stagger = 0xd;
1880 else if (intel_crtc->config->port_clock > 67500)
1881 stagger = 0x7;
1882 else if (intel_crtc->config->port_clock > 33750)
1883 stagger = 0x4;
1884 else
1885 stagger = 0x2;
1886
1887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1888 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1890
1891 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1892 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1893 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1894
1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1896 DPIO_LANESTAGGER_STRAP(stagger) |
1897 DPIO_LANESTAGGER_STRAP_OVRD |
1898 DPIO_TX1_STAGGER_MASK(0x1f) |
1899 DPIO_TX1_STAGGER_MULT(6) |
1900 DPIO_TX2_STAGGER_MULT(0));
1901
1902 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1903 DPIO_LANESTAGGER_STRAP(stagger) |
1904 DPIO_LANESTAGGER_STRAP_OVRD |
1905 DPIO_TX1_STAGGER_MASK(0x1f) |
1906 DPIO_TX1_STAGGER_MULT(7) |
1907 DPIO_TX2_STAGGER_MULT(5));
1908
1909 /* Deassert data lane reset */
1910 chv_data_lane_soft_reset(encoder, false);
1911
1912 /* Clear calc init */
1913 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1914 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1915 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1916 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1918
1919 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1920 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1921 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1922 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1923 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1924
1925 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1926 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1927 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1928 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1929
1930 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1931 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1932 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1933 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1934
1935 /* FIXME: Program the support xxx V-dB */
1936 /* Use 800mV-0dB */
1937 for (i = 0; i < 4; i++) {
1938 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1939 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1940 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1941 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1942 }
1943
1944 for (i = 0; i < 4; i++) {
1945 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1946
1947 val &= ~DPIO_SWING_MARGIN000_MASK;
1948 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1949
1950 /*
1951 * Supposedly this value shouldn't matter when unique transition
1952 * scale is disabled, but in fact it does matter. Let's just
1953 * always program the same value and hope it's OK.
1954 */
1955 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1956 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1957
1958 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1959 }
1960
1961 /*
1962 * The document said it needs to set bit 27 for ch0 and bit 26
1963 * for ch1. Might be a typo in the doc.
1964 * For now, for this unique transition scale selection, set bit
1965 * 27 for ch0 and ch1.
1966 */
1967 for (i = 0; i < 4; i++) {
1968 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1969 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1970 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1971 }
1972
1973 /* Start swing calculation */
1974 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1975 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1976 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1977
1978 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1979 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1980 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1981
1982 mutex_unlock(&dev_priv->sb_lock);
1983
1984 intel_hdmi->set_infoframes(&encoder->base,
1985 intel_crtc->config->has_hdmi_sink,
1986 adjusted_mode);
1987
1988 g4x_enable_hdmi(encoder);
1989
1990 vlv_wait_port_ready(dev_priv, dport, 0x0);
1991
1992 /* Second common lane will stay alive on its own now */
1993 if (dport->release_cl2_override) {
1994 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1995 dport->release_cl2_override = false;
1996 }
1997 }
1998
1999 static void intel_hdmi_destroy(struct drm_connector *connector)
2000 {
2001 kfree(to_intel_connector(connector)->detect_edid);
2002 drm_connector_cleanup(connector);
2003 kfree(connector);
2004 }
2005
2006 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2007 .dpms = drm_atomic_helper_connector_dpms,
2008 .detect = intel_hdmi_detect,
2009 .force = intel_hdmi_force,
2010 .fill_modes = drm_helper_probe_single_connector_modes,
2011 .set_property = intel_hdmi_set_property,
2012 .atomic_get_property = intel_connector_atomic_get_property,
2013 .destroy = intel_hdmi_destroy,
2014 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2015 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2016 };
2017
2018 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2019 .get_modes = intel_hdmi_get_modes,
2020 .mode_valid = intel_hdmi_mode_valid,
2021 .best_encoder = intel_best_encoder,
2022 };
2023
2024 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2025 .destroy = intel_encoder_destroy,
2026 };
2027
2028 static void
2029 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2030 {
2031 intel_attach_force_audio_property(connector);
2032 intel_attach_broadcast_rgb_property(connector);
2033 intel_hdmi->color_range_auto = true;
2034 intel_attach_aspect_ratio_property(connector);
2035 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2036 }
2037
2038 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2039 struct intel_connector *intel_connector)
2040 {
2041 struct drm_connector *connector = &intel_connector->base;
2042 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2043 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2044 struct drm_device *dev = intel_encoder->base.dev;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 enum port port = intel_dig_port->port;
2047 uint8_t alternate_ddc_pin;
2048
2049 if (WARN(intel_dig_port->max_lanes < 4,
2050 "Not enough lanes (%d) for HDMI on port %c\n",
2051 intel_dig_port->max_lanes, port_name(port)))
2052 return;
2053
2054 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2055 DRM_MODE_CONNECTOR_HDMIA);
2056 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2057
2058 connector->interlace_allowed = 1;
2059 connector->doublescan_allowed = 0;
2060 connector->stereo_allowed = 1;
2061
2062 switch (port) {
2063 case PORT_B:
2064 if (IS_BROXTON(dev_priv))
2065 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2066 else
2067 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2068 /*
2069 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2070 * interrupts to check the external panel connection.
2071 */
2072 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2073 intel_encoder->hpd_pin = HPD_PORT_A;
2074 else
2075 intel_encoder->hpd_pin = HPD_PORT_B;
2076 break;
2077 case PORT_C:
2078 if (IS_BROXTON(dev_priv))
2079 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2080 else
2081 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2082 intel_encoder->hpd_pin = HPD_PORT_C;
2083 break;
2084 case PORT_D:
2085 if (WARN_ON(IS_BROXTON(dev_priv)))
2086 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2087 else if (IS_CHERRYVIEW(dev_priv))
2088 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2089 else
2090 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2091 intel_encoder->hpd_pin = HPD_PORT_D;
2092 break;
2093 case PORT_E:
2094 /* On SKL PORT E doesn't have seperate GMBUS pin
2095 * We rely on VBT to set a proper alternate GMBUS pin. */
2096 alternate_ddc_pin =
2097 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2098 switch (alternate_ddc_pin) {
2099 case DDC_PIN_B:
2100 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2101 break;
2102 case DDC_PIN_C:
2103 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2104 break;
2105 case DDC_PIN_D:
2106 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2107 break;
2108 default:
2109 MISSING_CASE(alternate_ddc_pin);
2110 }
2111 intel_encoder->hpd_pin = HPD_PORT_E;
2112 break;
2113 case PORT_A:
2114 intel_encoder->hpd_pin = HPD_PORT_A;
2115 /* Internal port only for eDP. */
2116 default:
2117 BUG();
2118 }
2119
2120 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2121 intel_hdmi->write_infoframe = vlv_write_infoframe;
2122 intel_hdmi->set_infoframes = vlv_set_infoframes;
2123 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2124 } else if (IS_G4X(dev)) {
2125 intel_hdmi->write_infoframe = g4x_write_infoframe;
2126 intel_hdmi->set_infoframes = g4x_set_infoframes;
2127 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2128 } else if (HAS_DDI(dev)) {
2129 intel_hdmi->write_infoframe = hsw_write_infoframe;
2130 intel_hdmi->set_infoframes = hsw_set_infoframes;
2131 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2132 } else if (HAS_PCH_IBX(dev)) {
2133 intel_hdmi->write_infoframe = ibx_write_infoframe;
2134 intel_hdmi->set_infoframes = ibx_set_infoframes;
2135 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2136 } else {
2137 intel_hdmi->write_infoframe = cpt_write_infoframe;
2138 intel_hdmi->set_infoframes = cpt_set_infoframes;
2139 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2140 }
2141
2142 if (HAS_DDI(dev))
2143 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2144 else
2145 intel_connector->get_hw_state = intel_connector_get_hw_state;
2146 intel_connector->unregister = intel_connector_unregister;
2147
2148 intel_hdmi_add_properties(intel_hdmi, connector);
2149
2150 intel_connector_attach_encoder(intel_connector, intel_encoder);
2151 drm_connector_register(connector);
2152 intel_hdmi->attached_connector = intel_connector;
2153
2154 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2155 * 0xd. Failure to do so will result in spurious interrupts being
2156 * generated on the port when a cable is not attached.
2157 */
2158 if (IS_G4X(dev) && !IS_GM45(dev)) {
2159 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2160 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2161 }
2162 }
2163
2164 void intel_hdmi_init(struct drm_device *dev,
2165 i915_reg_t hdmi_reg, enum port port)
2166 {
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_digital_port *intel_dig_port;
2169 struct intel_encoder *intel_encoder;
2170 struct intel_connector *intel_connector;
2171
2172 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2173 if (!intel_dig_port)
2174 return;
2175
2176 intel_connector = intel_connector_alloc();
2177 if (!intel_connector) {
2178 kfree(intel_dig_port);
2179 return;
2180 }
2181
2182 intel_encoder = &intel_dig_port->base;
2183
2184 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2185 DRM_MODE_ENCODER_TMDS, NULL);
2186
2187 intel_encoder->compute_config = intel_hdmi_compute_config;
2188 if (HAS_PCH_SPLIT(dev)) {
2189 intel_encoder->disable = pch_disable_hdmi;
2190 intel_encoder->post_disable = pch_post_disable_hdmi;
2191 } else {
2192 intel_encoder->disable = g4x_disable_hdmi;
2193 }
2194 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2195 intel_encoder->get_config = intel_hdmi_get_config;
2196 if (IS_CHERRYVIEW(dev)) {
2197 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2198 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2199 intel_encoder->enable = vlv_enable_hdmi;
2200 intel_encoder->post_disable = chv_hdmi_post_disable;
2201 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2202 } else if (IS_VALLEYVIEW(dev)) {
2203 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2204 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2205 intel_encoder->enable = vlv_enable_hdmi;
2206 intel_encoder->post_disable = vlv_hdmi_post_disable;
2207 } else {
2208 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2209 if (HAS_PCH_CPT(dev))
2210 intel_encoder->enable = cpt_enable_hdmi;
2211 else if (HAS_PCH_IBX(dev))
2212 intel_encoder->enable = ibx_enable_hdmi;
2213 else
2214 intel_encoder->enable = g4x_enable_hdmi;
2215 }
2216
2217 intel_encoder->type = INTEL_OUTPUT_HDMI;
2218 if (IS_CHERRYVIEW(dev)) {
2219 if (port == PORT_D)
2220 intel_encoder->crtc_mask = 1 << 2;
2221 else
2222 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2223 } else {
2224 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2225 }
2226 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2227 /*
2228 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2229 * to work on real hardware. And since g4x can send infoframes to
2230 * only one port anyway, nothing is lost by allowing it.
2231 */
2232 if (IS_G4X(dev))
2233 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2234
2235 intel_dig_port->port = port;
2236 dev_priv->dig_port_map[port] = intel_encoder;
2237 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2238 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2239 intel_dig_port->max_lanes = 4;
2240
2241 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2242 }
Linux kernel - Deliverables
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