drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 struct gmbus_pin {
  38         const char *name;
  39         i915_reg_t reg;
  40 };
  41
  42 /* Map gmbus pin pairs to names and registers. */
  43 static const struct gmbus_pin gmbus_pins[] = {
  44         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  45         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  46         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  47         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  48         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  49         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  50 };
  51
  52 static const struct gmbus_pin gmbus_pins_bdw[] = {
  53         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  54         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  55         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  56         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  57 };
  58
  59 static const struct gmbus_pin gmbus_pins_skl[] = {
  60         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  61         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  62         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  63 };
  64
  65 static const struct gmbus_pin gmbus_pins_bxt[] = {
  66         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  67         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  68         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  69 };
  70
  71 /* pin is expected to be valid */
  72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
  73                                              unsigned int pin)
  74 {
  75         if (IS_BROXTON(dev_priv))
  76                 return &gmbus_pins_bxt[pin];
  77         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
  78                 return &gmbus_pins_skl[pin];
  79         else if (IS_BROADWELL(dev_priv))
  80                 return &gmbus_pins_bdw[pin];
  81         else
  82                 return &gmbus_pins[pin];
  83 }
  84
  85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  86                               unsigned int pin)
  87 {
  88         unsigned int size;
  89
  90         if (IS_BROXTON(dev_priv))
  91                 size = ARRAY_SIZE(gmbus_pins_bxt);
  92         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
  93                 size = ARRAY_SIZE(gmbus_pins_skl);
  94         else if (IS_BROADWELL(dev_priv))
  95                 size = ARRAY_SIZE(gmbus_pins_bdw);
  96         else
  97                 size = ARRAY_SIZE(gmbus_pins);
  98
  99         return pin < size &&
 100                 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
 101 }
 102
 103 /* Intel GPIO access functions */
 104
 105 #define I2C_RISEFALL_TIME 10
 106
 107 static inline struct intel_gmbus *
 108 to_intel_gmbus(struct i2c_adapter *i2c)
 109 {
 110         return container_of(i2c, struct intel_gmbus, adapter);
 111 }
 112
 113 void
 114 intel_i2c_reset(struct drm_device *dev)
 115 {
 116         struct drm_i915_private *dev_priv = to_i915(dev);
 117
 118         I915_WRITE(GMBUS0, 0);
 119         I915_WRITE(GMBUS4, 0);
 120 }
 121
 122 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
 123 {
 124         u32 val;
 125
 126         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 127         if (!IS_PINEVIEW(dev_priv))
 128                 return;
 129
 130         val = I915_READ(DSPCLK_GATE_D);
 131         if (enable)
 132                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
 133         else
 134                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 135         I915_WRITE(DSPCLK_GATE_D, val);
 136 }
 137
 138 static u32 get_reserved(struct intel_gmbus *bus)
 139 {
 140         struct drm_i915_private *dev_priv = bus->dev_priv;
 141         struct drm_device *dev = &dev_priv->drm;
 142         u32 reserved = 0;
 143
 144         /* On most chips, these bits must be preserved in software. */
 145         if (!IS_I830(dev) && !IS_845G(dev))
 146                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
 147                                              (GPIO_DATA_PULLUP_DISABLE |
 148                                               GPIO_CLOCK_PULLUP_DISABLE);
 149
 150         return reserved;
 151 }
 152
 153 static int get_clock(void *data)
 154 {
 155         struct intel_gmbus *bus = data;
 156         struct drm_i915_private *dev_priv = bus->dev_priv;
 157         u32 reserved = get_reserved(bus);
 158         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 159         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 160         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 161 }
 162
 163 static int get_data(void *data)
 164 {
 165         struct intel_gmbus *bus = data;
 166         struct drm_i915_private *dev_priv = bus->dev_priv;
 167         u32 reserved = get_reserved(bus);
 168         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 169         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 170         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 171 }
 172
 173 static void set_clock(void *data, int state_high)
 174 {
 175         struct intel_gmbus *bus = data;
 176         struct drm_i915_private *dev_priv = bus->dev_priv;
 177         u32 reserved = get_reserved(bus);
 178         u32 clock_bits;
 179
 180         if (state_high)
 181                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 182         else
 183                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 184                         GPIO_CLOCK_VAL_MASK;
 185
 186         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 187         POSTING_READ(bus->gpio_reg);
 188 }
 189
 190 static void set_data(void *data, int state_high)
 191 {
 192         struct intel_gmbus *bus = data;
 193         struct drm_i915_private *dev_priv = bus->dev_priv;
 194         u32 reserved = get_reserved(bus);
 195         u32 data_bits;
 196
 197         if (state_high)
 198                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 199         else
 200                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 201                         GPIO_DATA_VAL_MASK;
 202
 203         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 204         POSTING_READ(bus->gpio_reg);
 205 }
 206
 207 static int
 208 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 209 {
 210         struct intel_gmbus *bus = container_of(adapter,
 211                                                struct intel_gmbus,
 212                                                adapter);
 213         struct drm_i915_private *dev_priv = bus->dev_priv;
 214
 215         intel_i2c_reset(&dev_priv->drm);
 216         intel_i2c_quirk_set(dev_priv, true);
 217         set_data(bus, 1);
 218         set_clock(bus, 1);
 219         udelay(I2C_RISEFALL_TIME);
 220         return 0;
 221 }
 222
 223 static void
 224 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 225 {
 226         struct intel_gmbus *bus = container_of(adapter,
 227                                                struct intel_gmbus,
 228                                                adapter);
 229         struct drm_i915_private *dev_priv = bus->dev_priv;
 230
 231         set_data(bus, 1);
 232         set_clock(bus, 1);
 233         intel_i2c_quirk_set(dev_priv, false);
 234 }
 235
 236 static void
 237 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 238 {
 239         struct drm_i915_private *dev_priv = bus->dev_priv;
 240         struct i2c_algo_bit_data *algo;
 241
 242         algo = &bus->bit_algo;
 243
 244         bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
 245                               i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
 246         bus->adapter.algo_data = algo;
 247         algo->setsda = set_data;
 248         algo->setscl = set_clock;
 249         algo->getsda = get_data;
 250         algo->getscl = get_clock;
 251         algo->pre_xfer = intel_gpio_pre_xfer;
 252         algo->post_xfer = intel_gpio_post_xfer;
 253         algo->udelay = I2C_RISEFALL_TIME;
 254         algo->timeout = usecs_to_jiffies(2200);
 255         algo->data = bus;
 256 }
 257
 258 static int
 259 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 260                      u32 gmbus2_status,
 261                      u32 gmbus4_irq_en)
 262 {
 263         int i;
 264         u32 gmbus2 = 0;
 265         DEFINE_WAIT(wait);
 266
 267         if (!HAS_GMBUS_IRQ(dev_priv))
 268                 gmbus4_irq_en = 0;
 269
 270         /* Important: The hw handles only the first bit, so set only one! Since
 271          * we also need to check for NAKs besides the hw ready/idle signal, we
 272          * need to wake up periodically and check that ourselves. */
 273         I915_WRITE(GMBUS4, gmbus4_irq_en);
 274
 275         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 276                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 277                                 TASK_UNINTERRUPTIBLE);
 278
 279                 gmbus2 = I915_READ_NOTRACE(GMBUS2);
 280                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 281                         break;
 282
 283                 schedule_timeout(1);
 284         }
 285         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 286
 287         I915_WRITE(GMBUS4, 0);
 288
 289         if (gmbus2 & GMBUS_SATOER)
 290                 return -ENXIO;
 291         if (gmbus2 & gmbus2_status)
 292                 return 0;
 293         return -ETIMEDOUT;
 294 }
 295
 296 static int
 297 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 298 {
 299         int ret;
 300
 301         if (!HAS_GMBUS_IRQ(dev_priv))
 302                 return intel_wait_for_register(dev_priv,
 303                                                GMBUS2, GMBUS_ACTIVE, 0,
 304                                                10);
 305
 306         /* Important: The hw handles only the first bit, so set only one! */
 307         I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
 308
 309         ret = wait_event_timeout(dev_priv->gmbus_wait_queue,
 310                                  (I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0,
 311                                  msecs_to_jiffies_timeout(10));
 312
 313         I915_WRITE(GMBUS4, 0);
 314
 315         if (ret)
 316                 return 0;
 317         else
 318                 return -ETIMEDOUT;
 319 }
 320
 321 static int
 322 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 323                       unsigned short addr, u8 *buf, unsigned int len,
 324                       u32 gmbus1_index)
 325 {
 326         I915_WRITE(GMBUS1,
 327                    gmbus1_index |
 328                    GMBUS_CYCLE_WAIT |
 329                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 330                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 331                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 332         while (len) {
 333                 int ret;
 334                 u32 val, loop = 0;
 335
 336                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 337                                            GMBUS_HW_RDY_EN);
 338                 if (ret)
 339                         return ret;
 340
 341                 val = I915_READ(GMBUS3);
 342                 do {
 343                         *buf++ = val & 0xff;
 344                         val >>= 8;
 345                 } while (--len && ++loop < 4);
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 353                 u32 gmbus1_index)
 354 {
 355         u8 *buf = msg->buf;
 356         unsigned int rx_size = msg->len;
 357         unsigned int len;
 358         int ret;
 359
 360         do {
 361                 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
 362
 363                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 364                                             buf, len, gmbus1_index);
 365                 if (ret)
 366                         return ret;
 367
 368                 rx_size -= len;
 369                 buf += len;
 370         } while (rx_size != 0);
 371
 372         return 0;
 373 }
 374
 375 static int
 376 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 377                        unsigned short addr, u8 *buf, unsigned int len)
 378 {
 379         unsigned int chunk_size = len;
 380         u32 val, loop;
 381
 382         val = loop = 0;
 383         while (len && loop < 4) {
 384                 val |= *buf++ << (8 * loop++);
 385                 len -= 1;
 386         }
 387
 388         I915_WRITE(GMBUS3, val);
 389         I915_WRITE(GMBUS1,
 390                    GMBUS_CYCLE_WAIT |
 391                    (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
 392                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 393                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 394         while (len) {
 395                 int ret;
 396
 397                 val = loop = 0;
 398                 do {
 399                         val |= *buf++ << (8 * loop);
 400                 } while (--len && ++loop < 4);
 401
 402                 I915_WRITE(GMBUS3, val);
 403
 404                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 405                                            GMBUS_HW_RDY_EN);
 406                 if (ret)
 407                         return ret;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int
 414 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 415 {
 416         u8 *buf = msg->buf;
 417         unsigned int tx_size = msg->len;
 418         unsigned int len;
 419         int ret;
 420
 421         do {
 422                 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
 423
 424                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
 425                 if (ret)
 426                         return ret;
 427
 428                 buf += len;
 429                 tx_size -= len;
 430         } while (tx_size != 0);
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * The gmbus controller can combine a 1 or 2 byte write with a read that
 437  * immediately follows it by using an "INDEX" cycle.
 438  */
 439 static bool
 440 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 441 {
 442         return (i + 1 < num &&
 443                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 444                 (msgs[i + 1].flags & I2C_M_RD));
 445 }
 446
 447 static int
 448 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 449 {
 450         u32 gmbus1_index = 0;
 451         u32 gmbus5 = 0;
 452         int ret;
 453
 454         if (msgs[0].len == 2)
 455                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 456                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 457         if (msgs[0].len == 1)
 458                 gmbus1_index = GMBUS_CYCLE_INDEX |
 459                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 460
 461         /* GMBUS5 holds 16-bit index */
 462         if (gmbus5)
 463                 I915_WRITE(GMBUS5, gmbus5);
 464
 465         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 466
 467         /* Clear GMBUS5 after each index transfer */
 468         if (gmbus5)
 469                 I915_WRITE(GMBUS5, 0);
 470
 471         return ret;
 472 }
 473
 474 static int
 475 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 476 {
 477         struct intel_gmbus *bus = container_of(adapter,
 478                                                struct intel_gmbus,
 479                                                adapter);
 480         struct drm_i915_private *dev_priv = bus->dev_priv;
 481         int i = 0, inc, try = 0;
 482         int ret = 0;
 483
 484 retry:
 485         I915_WRITE(GMBUS0, bus->reg0);
 486
 487         for (; i < num; i += inc) {
 488                 inc = 1;
 489                 if (gmbus_is_index_read(msgs, i, num)) {
 490                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 491                         inc = 2; /* an index read is two msgs */
 492                 } else if (msgs[i].flags & I2C_M_RD) {
 493                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 494                 } else {
 495                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 496                 }
 497
 498                 if (!ret)
 499                         ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
 500                                                    GMBUS_HW_WAIT_EN);
 501                 if (ret == -ETIMEDOUT)
 502                         goto timeout;
 503                 else if (ret)
 504                         goto clear_err;
 505         }
 506
 507         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 508          * a STOP on the very first cycle. To simplify the code we
 509          * unconditionally generate the STOP condition with an additional gmbus
 510          * cycle. */
 511         I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 512
 513         /* Mark the GMBUS interface as disabled after waiting for idle.
 514          * We will re-enable it at the start of the next xfer,
 515          * till then let it sleep.
 516          */
 517         if (gmbus_wait_idle(dev_priv)) {
 518                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 519                          adapter->name);
 520                 ret = -ETIMEDOUT;
 521         }
 522         I915_WRITE(GMBUS0, 0);
 523         ret = ret ?: i;
 524         goto out;
 525
 526 clear_err:
 527         /*
 528          * Wait for bus to IDLE before clearing NAK.
 529          * If we clear the NAK while bus is still active, then it will stay
 530          * active and the next transaction may fail.
 531          *
 532          * If no ACK is received during the address phase of a transaction, the
 533          * adapter must report -ENXIO. It is not clear what to return if no ACK
 534          * is received at other times. But we have to be careful to not return
 535          * spurious -ENXIO because that will prevent i2c and drm edid functions
 536          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 537          * timing out seems to happen when there _is_ a ddc chip present, but
 538          * it's slow responding and only answers on the 2nd retry.
 539          */
 540         ret = -ENXIO;
 541         if (gmbus_wait_idle(dev_priv)) {
 542                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 543                               adapter->name);
 544                 ret = -ETIMEDOUT;
 545         }
 546
 547         /* Toggle the Software Clear Interrupt bit. This has the effect
 548          * of resetting the GMBUS controller and so clearing the
 549          * BUS_ERROR raised by the slave's NAK.
 550          */
 551         I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
 552         I915_WRITE(GMBUS1, 0);
 553         I915_WRITE(GMBUS0, 0);
 554
 555         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 556                          adapter->name, msgs[i].addr,
 557                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 558
 559         /*
 560          * Passive adapters sometimes NAK the first probe. Retry the first
 561          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 562          * has retries internally. See also the retry loop in
 563          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 564          */
 565         if (ret == -ENXIO && i == 0 && try++ == 0) {
 566                 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
 567                               adapter->name);
 568                 goto retry;
 569         }
 570
 571         goto out;
 572
 573 timeout:
 574         DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 575                       bus->adapter.name, bus->reg0 & 0xff);
 576         I915_WRITE(GMBUS0, 0);
 577
 578         /*
 579          * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
 580          * instead. Use EAGAIN to have i2c core retry.
 581          */
 582         ret = -EAGAIN;
 583
 584 out:
 585         return ret;
 586 }
 587
 588 static int
 589 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 590 {
 591         struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
 592                                                adapter);
 593         struct drm_i915_private *dev_priv = bus->dev_priv;
 594         int ret;
 595
 596         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 597         mutex_lock(&dev_priv->gmbus_mutex);
 598
 599         if (bus->force_bit) {
 600                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 601                 if (ret < 0)
 602                         bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
 603         } else {
 604                 ret = do_gmbus_xfer(adapter, msgs, num);
 605                 if (ret == -EAGAIN)
 606                         bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
 607         }
 608
 609         mutex_unlock(&dev_priv->gmbus_mutex);
 610         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
 611
 612         return ret;
 613 }
 614
 615 static u32 gmbus_func(struct i2c_adapter *adapter)
 616 {
 617         return i2c_bit_algo.functionality(adapter) &
 618                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 619                 /* I2C_FUNC_10BIT_ADDR | */
 620                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 621                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 622 }
 623
 624 static const struct i2c_algorithm gmbus_algorithm = {
 625         .master_xfer    = gmbus_xfer,
 626         .functionality  = gmbus_func
 627 };
 628
 629 /**
 630  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 631  * @dev: DRM device
 632  */
 633 int intel_setup_gmbus(struct drm_device *dev)
 634 {
 635         struct drm_i915_private *dev_priv = to_i915(dev);
 636         struct intel_gmbus *bus;
 637         unsigned int pin;
 638         int ret;
 639
 640         if (HAS_PCH_NOP(dev))
 641                 return 0;
 642
 643         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 644                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 645         else if (!HAS_GMCH_DISPLAY(dev_priv))
 646                 dev_priv->gpio_mmio_base =
 647                         i915_mmio_reg_offset(PCH_GPIOA) -
 648                         i915_mmio_reg_offset(GPIOA);
 649
 650         mutex_init(&dev_priv->gmbus_mutex);
 651         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 652
 653         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 654                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 655                         continue;
 656
 657                 bus = &dev_priv->gmbus[pin];
 658
 659                 bus->adapter.owner = THIS_MODULE;
 660                 bus->adapter.class = I2C_CLASS_DDC;
 661                 snprintf(bus->adapter.name,
 662                          sizeof(bus->adapter.name),
 663                          "i915 gmbus %s",
 664                          get_gmbus_pin(dev_priv, pin)->name);
 665
 666                 bus->adapter.dev.parent = &dev->pdev->dev;
 667                 bus->dev_priv = dev_priv;
 668
 669                 bus->adapter.algo = &gmbus_algorithm;
 670
 671                 /*
 672                  * We wish to retry with bit banging
 673                  * after a timed out GMBUS attempt.
 674                  */
 675                 bus->adapter.retries = 1;
 676
 677                 /* By default use a conservative clock rate */
 678                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
 679
 680                 /* gmbus seems to be broken on i830 */
 681                 if (IS_I830(dev))
 682                         bus->force_bit = 1;
 683
 684                 intel_gpio_setup(bus, pin);
 685
 686                 ret = i2c_add_adapter(&bus->adapter);
 687                 if (ret)
 688                         goto err;
 689         }
 690
 691         intel_i2c_reset(&dev_priv->drm);
 692
 693         return 0;
 694
 695 err:
 696         while (pin--) {
 697                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 698                         continue;
 699
 700                 bus = &dev_priv->gmbus[pin];
 701                 i2c_del_adapter(&bus->adapter);
 702         }
 703         return ret;
 704 }
 705
 706 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 707                                             unsigned int pin)
 708 {
 709         if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
 710                 return NULL;
 711
 712         return &dev_priv->gmbus[pin].adapter;
 713 }
 714
 715 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 716 {
 717         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 718
 719         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 720 }
 721
 722 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 723 {
 724         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 725         struct drm_i915_private *dev_priv = bus->dev_priv;
 726
 727         mutex_lock(&dev_priv->gmbus_mutex);
 728
 729         bus->force_bit += force_bit ? 1 : -1;
 730         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 731                       force_bit ? "en" : "dis", adapter->name,
 732                       bus->force_bit);
 733
 734         mutex_unlock(&dev_priv->gmbus_mutex);
 735 }
 736
 737 void intel_teardown_gmbus(struct drm_device *dev)
 738 {
 739         struct drm_i915_private *dev_priv = to_i915(dev);
 740         struct intel_gmbus *bus;
 741         unsigned int pin;
 742
 743         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 744                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 745                         continue;
 746
 747                 bus = &dev_priv->gmbus[pin];
 748                 i2c_del_adapter(&bus->adapter);
 749         }
 750 }