2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define GEN8_CTX_VALID (1<<0)
194 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
195 #define GEN8_CTX_FORCE_RESTORE (1<<2)
196 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
197 #define GEN8_CTX_PRIVILEGE (1<<8)
199 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
200 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
201 (reg_state)[(pos)+1] = (val); \
204 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
205 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
206 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
207 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
210 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
211 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
212 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
217 FAULT_AND_HALT
, /* Debug only */
219 FAULT_AND_CONTINUE
/* Unsupported */
221 #define GEN8_CTX_ID_SHIFT 32
222 #define GEN8_CTX_ID_WIDTH 21
223 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
224 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
226 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
227 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
229 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
230 struct intel_engine_cs
*engine
);
231 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
232 struct intel_engine_cs
*engine
);
235 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @dev_priv: i915 device private
237 * @enable_execlists: value of i915.enable_execlists module parameter.
239 * Only certain platforms support Execlists (the prerequisites being
240 * support for Logical Ring Contexts and Aliasing PPGTT or better).
242 * Return: 1 if Execlists is supported and has to be enabled.
244 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
246 /* On platforms with execlist available, vGPU will only
247 * support execlist mode, no ring buffer mode.
249 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
252 if (INTEL_GEN(dev_priv
) >= 9)
255 if (enable_execlists
== 0)
258 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
259 USES_PPGTT(dev_priv
) &&
260 i915
.use_mmio_flip
>= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
269 struct drm_i915_private
*dev_priv
= engine
->i915
;
271 engine
->disable_lite_restore_wa
=
272 (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
273 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
274 (engine
->id
== VCS
|| engine
->id
== VCS2
);
276 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
277 if (IS_GEN8(dev_priv
))
278 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
279 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
281 /* TODO: WaDisableLiteRestore when we start using semaphore
282 * signalling between Command Streamers */
283 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
285 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
286 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
287 if (engine
->disable_lite_restore_wa
)
288 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
292 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
293 * descriptor for a pinned context
294 * @ctx: Context to work on
295 * @engine: Engine the descriptor will be used with
297 * The context descriptor encodes various attributes of a context,
298 * including its GTT address and some flags. Because it's fairly
299 * expensive to calculate, we'll just do it once and cache the result,
300 * which remains valid until the context is unpinned.
302 * This is what a descriptor looks like, from LSB to MSB::
304 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
305 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
306 * bits 32-52: ctx ID, a globally unique tag
307 * bits 53-54: mbz, reserved for use by hardware
308 * bits 55-63: group ID, currently unused and set to 0
311 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
312 struct intel_engine_cs
*engine
)
314 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
317 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
319 desc
= ctx
->desc_template
; /* bits 3-4 */
320 desc
|= engine
->ctx_desc_template
; /* bits 0-11 */
321 desc
|= i915_ggtt_offset(ce
->state
) + LRC_PPHWSP_PN
* PAGE_SIZE
;
323 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
328 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
329 struct intel_engine_cs
*engine
)
331 return ctx
->engine
[engine
->id
].lrc_desc
;
335 execlists_context_status_change(struct drm_i915_gem_request
*rq
,
336 unsigned long status
)
339 * Only used when GVT-g is enabled now. When GVT-g is disabled,
340 * The compiler should eliminate this function as dead-code.
342 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
345 atomic_notifier_call_chain(&rq
->ctx
->status_notifier
, status
, rq
);
349 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
351 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
352 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
353 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
354 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
357 static u64
execlists_update_context(struct drm_i915_gem_request
*rq
)
359 struct intel_context
*ce
= &rq
->ctx
->engine
[rq
->engine
->id
];
360 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
361 u32
*reg_state
= ce
->lrc_reg_state
;
363 reg_state
[CTX_RING_TAIL
+1] = intel_ring_offset(rq
->ring
, rq
->tail
);
365 /* True 32b PPGTT with dynamic page allocation: update PDP
366 * registers and point the unallocated PDPs to scratch page.
367 * PML4 is allocated during ppgtt init, so this is not needed
370 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
371 execlists_update_context_pdps(ppgtt
, reg_state
);
376 static void execlists_submit_ports(struct intel_engine_cs
*engine
)
378 struct drm_i915_private
*dev_priv
= engine
->i915
;
379 struct execlist_port
*port
= engine
->execlist_port
;
381 dev_priv
->regs
+ i915_mmio_reg_offset(RING_ELSP(engine
));
385 execlists_context_status_change(port
[0].request
,
386 INTEL_CONTEXT_SCHEDULE_IN
);
387 desc
[0] = execlists_update_context(port
[0].request
);
388 engine
->preempt_wa
= port
[0].count
++; /* bdw only? fixed on skl? */
390 if (port
[1].request
) {
391 GEM_BUG_ON(port
[1].count
);
392 execlists_context_status_change(port
[1].request
,
393 INTEL_CONTEXT_SCHEDULE_IN
);
394 desc
[1] = execlists_update_context(port
[1].request
);
399 GEM_BUG_ON(desc
[0] == desc
[1]);
401 /* You must always write both descriptors in the order below. */
402 writel(upper_32_bits(desc
[1]), elsp
);
403 writel(lower_32_bits(desc
[1]), elsp
);
405 writel(upper_32_bits(desc
[0]), elsp
);
406 /* The context is automatically loaded after the following */
407 writel(lower_32_bits(desc
[0]), elsp
);
410 static bool ctx_single_port_submission(const struct i915_gem_context
*ctx
)
412 return (IS_ENABLED(CONFIG_DRM_I915_GVT
) &&
413 ctx
->execlists_force_single_submission
);
416 static bool can_merge_ctx(const struct i915_gem_context
*prev
,
417 const struct i915_gem_context
*next
)
422 if (ctx_single_port_submission(prev
))
428 static void execlists_dequeue(struct intel_engine_cs
*engine
)
430 struct drm_i915_gem_request
*cursor
, *last
;
431 struct execlist_port
*port
= engine
->execlist_port
;
434 last
= port
->request
;
436 /* WaIdleLiteRestore:bdw,skl
437 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
438 * as we resubmit the request. See gen8_emit_request()
439 * for where we prepare the padding after the end of the
442 last
->tail
= last
->wa_tail
;
444 GEM_BUG_ON(port
[1].request
);
446 /* Hardware submission is through 2 ports. Conceptually each port
447 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
448 * static for a context, and unique to each, so we only execute
449 * requests belonging to a single context from each ring. RING_HEAD
450 * is maintained by the CS in the context image, it marks the place
451 * where it got up to last time, and through RING_TAIL we tell the CS
452 * where we want to execute up to this time.
454 * In this list the requests are in order of execution. Consecutive
455 * requests from the same context are adjacent in the ringbuffer. We
456 * can combine these requests into a single RING_TAIL update:
458 * RING_HEAD...req1...req2
460 * since to execute req2 the CS must first execute req1.
462 * Our goal then is to point each port to the end of a consecutive
463 * sequence of requests as being the most optimal (fewest wake ups
464 * and context switches) submission.
467 spin_lock(&engine
->execlist_lock
);
468 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
) {
469 /* Can we combine this request with the current port? It has to
470 * be the same context/ringbuffer and not have any exceptions
471 * (e.g. GVT saying never to combine contexts).
473 * If we can combine the requests, we can execute both by
474 * updating the RING_TAIL to point to the end of the second
475 * request, and so we never need to tell the hardware about
478 if (last
&& !can_merge_ctx(cursor
->ctx
, last
->ctx
)) {
479 /* If we are on the second port and cannot combine
480 * this request with the last, then we are done.
482 if (port
!= engine
->execlist_port
)
485 /* If GVT overrides us we only ever submit port[0],
486 * leaving port[1] empty. Note that we also have
487 * to be careful that we don't queue the same
488 * context (even though a different request) to
491 if (ctx_single_port_submission(cursor
->ctx
))
494 GEM_BUG_ON(last
->ctx
== cursor
->ctx
);
496 i915_gem_request_assign(&port
->request
, last
);
503 /* Decouple all the requests submitted from the queue */
504 engine
->execlist_queue
.next
= &cursor
->execlist_link
;
505 cursor
->execlist_link
.prev
= &engine
->execlist_queue
;
507 i915_gem_request_assign(&port
->request
, last
);
509 spin_unlock(&engine
->execlist_lock
);
512 execlists_submit_ports(engine
);
515 static bool execlists_elsp_idle(struct intel_engine_cs
*engine
)
517 return !engine
->execlist_port
[0].request
;
520 static bool execlists_elsp_ready(struct intel_engine_cs
*engine
)
524 port
= 1; /* wait for a free slot */
525 if (engine
->disable_lite_restore_wa
|| engine
->preempt_wa
)
526 port
= 0; /* wait for GPU to be idle before continuing */
528 return !engine
->execlist_port
[port
].request
;
532 * Check the unread Context Status Buffers and manage the submission of new
533 * contexts to the ELSP accordingly.
535 static void intel_lrc_irq_handler(unsigned long data
)
537 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
538 struct execlist_port
*port
= engine
->execlist_port
;
539 struct drm_i915_private
*dev_priv
= engine
->i915
;
541 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
543 if (!execlists_elsp_idle(engine
)) {
544 u32 __iomem
*csb_mmio
=
545 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine
));
547 dev_priv
->regs
+ i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine
, 0));
548 unsigned int csb
, head
, tail
;
550 csb
= readl(csb_mmio
);
551 head
= GEN8_CSB_READ_PTR(csb
);
552 tail
= GEN8_CSB_WRITE_PTR(csb
);
554 tail
+= GEN8_CSB_ENTRIES
;
555 while (head
< tail
) {
556 unsigned int idx
= ++head
% GEN8_CSB_ENTRIES
;
557 unsigned int status
= readl(buf
+ 2 * idx
);
559 if (!(status
& GEN8_CTX_STATUS_COMPLETED_MASK
))
562 GEM_BUG_ON(port
[0].count
== 0);
563 if (--port
[0].count
== 0) {
564 GEM_BUG_ON(status
& GEN8_CTX_STATUS_PREEMPTED
);
565 execlists_context_status_change(port
[0].request
,
566 INTEL_CONTEXT_SCHEDULE_OUT
);
568 i915_gem_request_put(port
[0].request
);
570 memset(&port
[1], 0, sizeof(port
[1]));
572 engine
->preempt_wa
= false;
575 GEM_BUG_ON(port
[0].count
== 0 &&
576 !(status
& GEN8_CTX_STATUS_ACTIVE_IDLE
));
579 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
580 GEN8_CSB_WRITE_PTR(csb
) << 8),
584 if (execlists_elsp_ready(engine
))
585 execlists_dequeue(engine
);
587 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
590 static void execlists_submit_request(struct drm_i915_gem_request
*request
)
592 struct intel_engine_cs
*engine
= request
->engine
;
595 spin_lock_irqsave(&engine
->execlist_lock
, flags
);
597 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
598 if (execlists_elsp_idle(engine
))
599 tasklet_hi_schedule(&engine
->irq_tasklet
);
601 spin_unlock_irqrestore(&engine
->execlist_lock
, flags
);
604 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
606 struct intel_engine_cs
*engine
= request
->engine
;
607 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
610 /* Flush enough space to reduce the likelihood of waiting after
611 * we start building the request - in which case we will just
612 * have to repeat work.
614 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
617 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
622 request
->ring
= ce
->ring
;
624 if (i915
.enable_guc_submission
) {
626 * Check that the GuC has space for the request before
627 * going any further, as the i915_add_request() call
628 * later on mustn't fail ...
630 ret
= i915_guc_wq_check_space(request
);
635 ret
= intel_lr_context_pin(request
->ctx
, engine
);
639 ret
= intel_ring_begin(request
, 0);
643 if (!ce
->initialised
) {
644 ret
= engine
->init_context(request
);
648 ce
->initialised
= true;
651 /* Note that after this point, we have committed to using
652 * this request as it is being used to both track the
653 * state of engine initialisation and liveness of the
654 * golden renderstate above. Think twice before you try
655 * to cancel/unwind this request now.
658 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
662 intel_lr_context_unpin(request
->ctx
, engine
);
667 * intel_logical_ring_advance() - advance the tail and prepare for submission
668 * @request: Request to advance the logical ringbuffer of.
670 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
671 * really happens during submission is that the context and current tail will be placed
672 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
673 * point, the tail *inside* the context is updated and the ELSP written to.
676 intel_logical_ring_advance(struct drm_i915_gem_request
*request
)
678 struct intel_ring
*ring
= request
->ring
;
679 struct intel_engine_cs
*engine
= request
->engine
;
681 intel_ring_advance(ring
);
682 request
->tail
= ring
->tail
;
685 * Here we add two extra NOOPs as padding to avoid
686 * lite restore of a context with HEAD==TAIL.
688 * Caller must reserve WA_TAIL_DWORDS for us!
690 intel_ring_emit(ring
, MI_NOOP
);
691 intel_ring_emit(ring
, MI_NOOP
);
692 intel_ring_advance(ring
);
693 request
->wa_tail
= ring
->tail
;
695 /* We keep the previous context alive until we retire the following
696 * request. This ensures that any the context object is still pinned
697 * for any residual writes the HW makes into it on the context switch
698 * into the next object following the breadcrumb. Otherwise, we may
699 * retire the context too early.
701 request
->previous_context
= engine
->last_context
;
702 engine
->last_context
= request
->ctx
;
706 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
707 struct intel_engine_cs
*engine
)
709 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
714 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
719 ret
= i915_vma_pin(ce
->state
, 0, GEN8_LR_CONTEXT_ALIGN
,
720 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
| PIN_GLOBAL
);
724 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
726 ret
= PTR_ERR(vaddr
);
730 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
732 ret
= intel_ring_pin(ce
->ring
);
736 intel_lr_context_descriptor_update(ctx
, engine
);
738 lrc_reg_state
[CTX_RING_BUFFER_START
+1] =
739 i915_ggtt_offset(ce
->ring
->vma
);
740 ce
->lrc_reg_state
= lrc_reg_state
;
741 ce
->state
->obj
->dirty
= true;
743 /* Invalidate GuC TLB. */
744 if (i915
.enable_guc_submission
) {
745 struct drm_i915_private
*dev_priv
= ctx
->i915
;
746 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
749 i915_gem_context_get(ctx
);
753 i915_gem_object_unpin_map(ce
->state
->obj
);
755 __i915_vma_unpin(ce
->state
);
761 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
762 struct intel_engine_cs
*engine
)
764 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
766 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
767 GEM_BUG_ON(ce
->pin_count
== 0);
772 intel_ring_unpin(ce
->ring
);
774 i915_gem_object_unpin_map(ce
->state
->obj
);
775 i915_vma_unpin(ce
->state
);
777 i915_gem_context_put(ctx
);
780 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
783 struct intel_ring
*ring
= req
->ring
;
784 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
789 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
793 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
797 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
798 for (i
= 0; i
< w
->count
; i
++) {
799 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
800 intel_ring_emit(ring
, w
->reg
[i
].value
);
802 intel_ring_emit(ring
, MI_NOOP
);
804 intel_ring_advance(ring
);
806 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
813 #define wa_ctx_emit(batch, index, cmd) \
815 int __index = (index)++; \
816 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
819 batch[__index] = (cmd); \
822 #define wa_ctx_emit_reg(batch, index, reg) \
823 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
826 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
827 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
828 * but there is a slight complication as this is applied in WA batch where the
829 * values are only initialized once so we cannot take register value at the
830 * beginning and reuse it further; hence we save its value to memory, upload a
831 * constant value with bit21 set and then we restore it back with the saved value.
832 * To simplify the WA, a constant value is formed by using the default value
833 * of this register. This shouldn't be a problem because we are only modifying
834 * it for a short period and this batch in non-premptible. We can ofcourse
835 * use additional instructions that read the actual value of the register
836 * at that time and set our bit of interest but it makes the WA complicated.
838 * This WA is also required for Gen9 so extracting as a function avoids
841 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
845 struct drm_i915_private
*dev_priv
= engine
->i915
;
846 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
849 * WaDisableLSQCROPERFforOCL:skl,kbl
850 * This WA is implemented in skl_init_clock_gating() but since
851 * this batch updates GEN8_L3SQCREG4 with default value we need to
852 * set this bit here to retain the WA during flush.
854 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
) ||
855 IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
856 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
858 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
859 MI_SRM_LRM_GLOBAL_GTT
));
860 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
861 wa_ctx_emit(batch
, index
, i915_ggtt_offset(engine
->scratch
) + 256);
862 wa_ctx_emit(batch
, index
, 0);
864 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
865 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
866 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
868 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
869 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
870 PIPE_CONTROL_DC_FLUSH_ENABLE
));
871 wa_ctx_emit(batch
, index
, 0);
872 wa_ctx_emit(batch
, index
, 0);
873 wa_ctx_emit(batch
, index
, 0);
874 wa_ctx_emit(batch
, index
, 0);
876 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
877 MI_SRM_LRM_GLOBAL_GTT
));
878 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
879 wa_ctx_emit(batch
, index
, i915_ggtt_offset(engine
->scratch
) + 256);
880 wa_ctx_emit(batch
, index
, 0);
885 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
887 uint32_t start_alignment
)
889 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
892 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
894 uint32_t size_alignment
)
896 wa_ctx
->size
= offset
- wa_ctx
->offset
;
898 WARN(wa_ctx
->size
% size_alignment
,
899 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
900 wa_ctx
->size
, size_alignment
);
905 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
906 * initialized at the beginning and shared across all contexts but this field
907 * helps us to have multiple batches at different offsets and select them based
908 * on a criteria. At the moment this batch always start at the beginning of the page
909 * and at this point we don't have multiple wa_ctx batch buffers.
911 * The number of WA applied are not known at the beginning; we use this field
912 * to return the no of DWORDS written.
914 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
915 * so it adds NOOPs as padding to make it cacheline aligned.
916 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
917 * makes a complete batch buffer.
919 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
920 struct i915_wa_ctx_bb
*wa_ctx
,
924 uint32_t scratch_addr
;
925 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
927 /* WaDisableCtxRestoreArbitration:bdw,chv */
928 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
930 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
931 if (IS_BROADWELL(engine
->i915
)) {
932 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
938 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
939 /* Actual scratch location is at 128 bytes offset */
940 scratch_addr
= i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
942 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
943 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
944 PIPE_CONTROL_GLOBAL_GTT_IVB
|
945 PIPE_CONTROL_CS_STALL
|
946 PIPE_CONTROL_QW_WRITE
));
947 wa_ctx_emit(batch
, index
, scratch_addr
);
948 wa_ctx_emit(batch
, index
, 0);
949 wa_ctx_emit(batch
, index
, 0);
950 wa_ctx_emit(batch
, index
, 0);
952 /* Pad to end of cacheline */
953 while (index
% CACHELINE_DWORDS
)
954 wa_ctx_emit(batch
, index
, MI_NOOP
);
957 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
958 * execution depends on the length specified in terms of cache lines
959 * in the register CTX_RCS_INDIRECT_CTX
962 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
966 * This batch is started immediately after indirect_ctx batch. Since we ensure
967 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
969 * The number of DWORDS written are returned using this field.
971 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
972 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
974 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
975 struct i915_wa_ctx_bb
*wa_ctx
,
979 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
981 /* WaDisableCtxRestoreArbitration:bdw,chv */
982 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
984 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
986 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
989 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
990 struct i915_wa_ctx_bb
*wa_ctx
,
995 struct drm_i915_private
*dev_priv
= engine
->i915
;
996 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
998 /* WaDisableCtxRestoreArbitration:skl,bxt */
999 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
) ||
1000 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1001 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1003 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1004 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1009 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1010 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1011 wa_ctx_emit_reg(batch
, index
, COMMON_SLICE_CHICKEN2
);
1012 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(
1013 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
));
1014 wa_ctx_emit(batch
, index
, MI_NOOP
);
1016 /* WaClearSlmSpaceAtContextSwitch:kbl */
1017 /* Actual scratch location is at 128 bytes offset */
1018 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_A0
)) {
1020 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1022 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1023 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1024 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1025 PIPE_CONTROL_CS_STALL
|
1026 PIPE_CONTROL_QW_WRITE
));
1027 wa_ctx_emit(batch
, index
, scratch_addr
);
1028 wa_ctx_emit(batch
, index
, 0);
1029 wa_ctx_emit(batch
, index
, 0);
1030 wa_ctx_emit(batch
, index
, 0);
1033 /* WaMediaPoolStateCmdInWABB:bxt */
1034 if (HAS_POOLED_EU(engine
->i915
)) {
1036 * EU pool configuration is setup along with golden context
1037 * during context initialization. This value depends on
1038 * device type (2x6 or 3x6) and needs to be updated based
1039 * on which subslice is disabled especially for 2x6
1040 * devices, however it is safe to load default
1041 * configuration of 3x6 device instead of masking off
1042 * corresponding bits because HW ignores bits of a disabled
1043 * subslice and drops down to appropriate config. Please
1044 * see render_state_setup() in i915_gem_render_state.c for
1045 * possible configurations, to avoid duplication they are
1046 * not shown here again.
1048 u32 eu_pool_config
= 0x00777000;
1049 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_STATE
);
1050 wa_ctx_emit(batch
, index
, GEN9_MEDIA_POOL_ENABLE
);
1051 wa_ctx_emit(batch
, index
, eu_pool_config
);
1052 wa_ctx_emit(batch
, index
, 0);
1053 wa_ctx_emit(batch
, index
, 0);
1054 wa_ctx_emit(batch
, index
, 0);
1057 /* Pad to end of cacheline */
1058 while (index
% CACHELINE_DWORDS
)
1059 wa_ctx_emit(batch
, index
, MI_NOOP
);
1061 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1064 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1065 struct i915_wa_ctx_bb
*wa_ctx
,
1069 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1071 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1072 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1073 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1074 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1075 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1076 wa_ctx_emit(batch
, index
,
1077 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1078 wa_ctx_emit(batch
, index
, MI_NOOP
);
1081 /* WaClearTdlStateAckDirtyBits:bxt */
1082 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1083 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1085 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1086 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1088 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1089 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1091 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1092 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1094 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1095 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1096 wa_ctx_emit(batch
, index
, 0x0);
1097 wa_ctx_emit(batch
, index
, MI_NOOP
);
1100 /* WaDisableCtxRestoreArbitration:skl,bxt */
1101 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1102 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1103 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1105 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1107 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1110 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1112 struct drm_i915_gem_object
*obj
;
1113 struct i915_vma
*vma
;
1116 obj
= i915_gem_object_create(&engine
->i915
->drm
, PAGE_ALIGN(size
));
1118 return PTR_ERR(obj
);
1120 vma
= i915_vma_create(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1126 err
= i915_vma_pin(vma
, 0, PAGE_SIZE
, PIN_GLOBAL
| PIN_HIGH
);
1130 engine
->wa_ctx
.vma
= vma
;
1134 i915_gem_object_put(obj
);
1138 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1140 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
);
1143 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1145 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1151 WARN_ON(engine
->id
!= RCS
);
1153 /* update this when WA for higher Gen are added */
1154 if (INTEL_GEN(engine
->i915
) > 9) {
1155 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1156 INTEL_GEN(engine
->i915
));
1160 /* some WA perform writes to scratch page, ensure it is valid */
1161 if (!engine
->scratch
) {
1162 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1166 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1168 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1172 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
1173 batch
= kmap_atomic(page
);
1176 if (IS_GEN8(engine
->i915
)) {
1177 ret
= gen8_init_indirectctx_bb(engine
,
1178 &wa_ctx
->indirect_ctx
,
1184 ret
= gen8_init_perctx_bb(engine
,
1190 } else if (IS_GEN9(engine
->i915
)) {
1191 ret
= gen9_init_indirectctx_bb(engine
,
1192 &wa_ctx
->indirect_ctx
,
1198 ret
= gen9_init_perctx_bb(engine
,
1207 kunmap_atomic(batch
);
1209 lrc_destroy_wa_ctx_obj(engine
);
1214 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1216 struct drm_i915_private
*dev_priv
= engine
->i915
;
1218 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1219 engine
->status_page
.ggtt_offset
);
1220 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1223 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1225 struct drm_i915_private
*dev_priv
= engine
->i915
;
1228 ret
= intel_mocs_init_engine(engine
);
1232 lrc_init_hws(engine
);
1234 intel_engine_reset_irq(engine
);
1236 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1238 I915_WRITE(RING_MODE_GEN7(engine
),
1239 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1240 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1242 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1244 intel_engine_init_hangcheck(engine
);
1246 if (!execlists_elsp_idle(engine
))
1247 execlists_submit_ports(engine
);
1252 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1254 struct drm_i915_private
*dev_priv
= engine
->i915
;
1257 ret
= gen8_init_common_ring(engine
);
1261 /* We need to disable the AsyncFlip performance optimisations in order
1262 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1263 * programmed to '1' on all products.
1265 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1267 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1269 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1271 return init_workarounds_ring(engine
);
1274 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1278 ret
= gen8_init_common_ring(engine
);
1282 return init_workarounds_ring(engine
);
1285 static void reset_common_ring(struct intel_engine_cs
*engine
,
1286 struct drm_i915_gem_request
*request
)
1288 struct drm_i915_private
*dev_priv
= engine
->i915
;
1289 struct execlist_port
*port
= engine
->execlist_port
;
1290 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
1292 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1293 ce
->lrc_reg_state
[CTX_RING_HEAD
+1] = request
->postfix
;
1294 request
->ring
->head
= request
->postfix
;
1295 request
->ring
->last_retired_head
= -1;
1296 intel_ring_update_space(request
->ring
);
1298 if (i915
.enable_guc_submission
)
1301 /* Catch up with any missed context-switch interrupts */
1302 I915_WRITE(RING_CONTEXT_STATUS_PTR(engine
), _MASKED_FIELD(0xffff, 0));
1303 if (request
->ctx
!= port
[0].request
->ctx
) {
1304 i915_gem_request_put(port
[0].request
);
1306 memset(&port
[1], 0, sizeof(port
[1]));
1309 /* CS is stopped, and we will resubmit both ports on resume */
1310 GEM_BUG_ON(request
->ctx
!= port
[0].request
->ctx
);
1315 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1317 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1318 struct intel_ring
*ring
= req
->ring
;
1319 struct intel_engine_cs
*engine
= req
->engine
;
1320 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1323 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1327 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1328 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1329 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1331 intel_ring_emit_reg(ring
, GEN8_RING_PDP_UDW(engine
, i
));
1332 intel_ring_emit(ring
, upper_32_bits(pd_daddr
));
1333 intel_ring_emit_reg(ring
, GEN8_RING_PDP_LDW(engine
, i
));
1334 intel_ring_emit(ring
, lower_32_bits(pd_daddr
));
1337 intel_ring_emit(ring
, MI_NOOP
);
1338 intel_ring_advance(ring
);
1343 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1344 u64 offset
, u32 len
,
1345 unsigned int dispatch_flags
)
1347 struct intel_ring
*ring
= req
->ring
;
1348 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1351 /* Don't rely in hw updating PDPs, specially in lite-restore.
1352 * Ideally, we should set Force PD Restore in ctx descriptor,
1353 * but we can't. Force Restore would be a second option, but
1354 * it is unsafe in case of lite-restore (because the ctx is
1355 * not idle). PML4 is allocated during ppgtt init so this is
1356 * not needed in 48-bit.*/
1357 if (req
->ctx
->ppgtt
&&
1358 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1359 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1360 !intel_vgpu_active(req
->i915
)) {
1361 ret
= intel_logical_ring_emit_pdps(req
);
1366 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1369 ret
= intel_ring_begin(req
, 4);
1373 /* FIXME(BDW): Address space and security selectors. */
1374 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
|
1376 (dispatch_flags
& I915_DISPATCH_RS
?
1377 MI_BATCH_RESOURCE_STREAMER
: 0));
1378 intel_ring_emit(ring
, lower_32_bits(offset
));
1379 intel_ring_emit(ring
, upper_32_bits(offset
));
1380 intel_ring_emit(ring
, MI_NOOP
);
1381 intel_ring_advance(ring
);
1386 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
1388 struct drm_i915_private
*dev_priv
= engine
->i915
;
1389 I915_WRITE_IMR(engine
,
1390 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1391 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1394 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
1396 struct drm_i915_private
*dev_priv
= engine
->i915
;
1397 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1400 static int gen8_emit_flush(struct drm_i915_gem_request
*request
, u32 mode
)
1402 struct intel_ring
*ring
= request
->ring
;
1406 ret
= intel_ring_begin(request
, 4);
1410 cmd
= MI_FLUSH_DW
+ 1;
1412 /* We always require a command barrier so that subsequent
1413 * commands, such as breadcrumb interrupts, are strictly ordered
1414 * wrt the contents of the write cache being flushed to memory
1415 * (and thus being coherent from the CPU).
1417 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1419 if (mode
& EMIT_INVALIDATE
) {
1420 cmd
|= MI_INVALIDATE_TLB
;
1421 if (request
->engine
->id
== VCS
)
1422 cmd
|= MI_INVALIDATE_BSD
;
1425 intel_ring_emit(ring
, cmd
);
1426 intel_ring_emit(ring
,
1427 I915_GEM_HWS_SCRATCH_ADDR
|
1428 MI_FLUSH_DW_USE_GTT
);
1429 intel_ring_emit(ring
, 0); /* upper addr */
1430 intel_ring_emit(ring
, 0); /* value */
1431 intel_ring_advance(ring
);
1436 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1439 struct intel_ring
*ring
= request
->ring
;
1440 struct intel_engine_cs
*engine
= request
->engine
;
1442 i915_ggtt_offset(engine
->scratch
) + 2 * CACHELINE_BYTES
;
1443 bool vf_flush_wa
= false, dc_flush_wa
= false;
1448 flags
|= PIPE_CONTROL_CS_STALL
;
1450 if (mode
& EMIT_FLUSH
) {
1451 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1452 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1453 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1454 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1457 if (mode
& EMIT_INVALIDATE
) {
1458 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1459 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1460 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1461 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1462 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1463 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1464 flags
|= PIPE_CONTROL_QW_WRITE
;
1465 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1468 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1471 if (IS_GEN9(request
->i915
))
1474 /* WaForGAMHang:kbl */
1475 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1487 ret
= intel_ring_begin(request
, len
);
1492 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1493 intel_ring_emit(ring
, 0);
1494 intel_ring_emit(ring
, 0);
1495 intel_ring_emit(ring
, 0);
1496 intel_ring_emit(ring
, 0);
1497 intel_ring_emit(ring
, 0);
1501 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1502 intel_ring_emit(ring
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1503 intel_ring_emit(ring
, 0);
1504 intel_ring_emit(ring
, 0);
1505 intel_ring_emit(ring
, 0);
1506 intel_ring_emit(ring
, 0);
1509 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1510 intel_ring_emit(ring
, flags
);
1511 intel_ring_emit(ring
, scratch_addr
);
1512 intel_ring_emit(ring
, 0);
1513 intel_ring_emit(ring
, 0);
1514 intel_ring_emit(ring
, 0);
1517 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1518 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
);
1519 intel_ring_emit(ring
, 0);
1520 intel_ring_emit(ring
, 0);
1521 intel_ring_emit(ring
, 0);
1522 intel_ring_emit(ring
, 0);
1525 intel_ring_advance(ring
);
1530 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1533 * On BXT A steppings there is a HW coherency issue whereby the
1534 * MI_STORE_DATA_IMM storing the completed request's seqno
1535 * occasionally doesn't invalidate the CPU cache. Work around this by
1536 * clflushing the corresponding cacheline whenever the caller wants
1537 * the coherency to be guaranteed. Note that this cacheline is known
1538 * to be clean at this point, since we only write it in
1539 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1540 * this clflush in practice becomes an invalidate operation.
1542 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1546 * Reserve space for 2 NOOPs at the end of each request to be
1547 * used as a workaround for not being allowed to do lite
1548 * restore with HEAD==TAIL (WaIdleLiteRestore).
1550 #define WA_TAIL_DWORDS 2
1552 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1554 struct intel_ring
*ring
= request
->ring
;
1557 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1561 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1562 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1564 intel_ring_emit(ring
, (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1565 intel_ring_emit(ring
,
1566 intel_hws_seqno_address(request
->engine
) |
1567 MI_FLUSH_DW_USE_GTT
);
1568 intel_ring_emit(ring
, 0);
1569 intel_ring_emit(ring
, request
->fence
.seqno
);
1570 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1571 intel_ring_emit(ring
, MI_NOOP
);
1572 return intel_logical_ring_advance(request
);
1575 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1577 struct intel_ring
*ring
= request
->ring
;
1580 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1584 /* We're using qword write, seqno should be aligned to 8 bytes. */
1585 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1587 /* w/a for post sync ops following a GPGPU operation we
1588 * need a prior CS_STALL, which is emitted by the flush
1589 * following the batch.
1591 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1592 intel_ring_emit(ring
,
1593 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1594 PIPE_CONTROL_CS_STALL
|
1595 PIPE_CONTROL_QW_WRITE
));
1596 intel_ring_emit(ring
, intel_hws_seqno_address(request
->engine
));
1597 intel_ring_emit(ring
, 0);
1598 intel_ring_emit(ring
, i915_gem_request_get_seqno(request
));
1599 /* We're thrashing one dword of HWS. */
1600 intel_ring_emit(ring
, 0);
1601 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1602 intel_ring_emit(ring
, MI_NOOP
);
1603 return intel_logical_ring_advance(request
);
1606 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1610 ret
= intel_logical_ring_workarounds_emit(req
);
1614 ret
= intel_rcs_context_init_mocs(req
);
1616 * Failing to program the MOCS is non-fatal.The system will not
1617 * run at peak performance. So generate an error and carry on.
1620 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1622 return i915_gem_render_state_init(req
);
1626 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1627 * @engine: Engine Command Streamer.
1629 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1631 struct drm_i915_private
*dev_priv
;
1633 if (!intel_engine_initialized(engine
))
1637 * Tasklet cannot be active at this point due intel_mark_active/idle
1638 * so this is just for documentation.
1640 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1641 tasklet_kill(&engine
->irq_tasklet
);
1643 dev_priv
= engine
->i915
;
1645 if (engine
->buffer
) {
1646 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1649 if (engine
->cleanup
)
1650 engine
->cleanup(engine
);
1652 intel_engine_cleanup_common(engine
);
1654 if (engine
->status_page
.vma
) {
1655 i915_gem_object_unpin_map(engine
->status_page
.vma
->obj
);
1656 engine
->status_page
.vma
= NULL
;
1658 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1660 lrc_destroy_wa_ctx_obj(engine
);
1661 engine
->i915
= NULL
;
1664 void intel_execlists_enable_submission(struct drm_i915_private
*dev_priv
)
1666 struct intel_engine_cs
*engine
;
1668 for_each_engine(engine
, dev_priv
)
1669 engine
->submit_request
= execlists_submit_request
;
1673 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1675 /* Default vfuncs which can be overriden by each engine. */
1676 engine
->init_hw
= gen8_init_common_ring
;
1677 engine
->reset_hw
= reset_common_ring
;
1678 engine
->emit_flush
= gen8_emit_flush
;
1679 engine
->emit_request
= gen8_emit_request
;
1680 engine
->submit_request
= execlists_submit_request
;
1682 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
1683 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
1684 engine
->emit_bb_start
= gen8_emit_bb_start
;
1685 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1686 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1690 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
1692 unsigned shift
= engine
->irq_shift
;
1693 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
1694 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
1698 lrc_setup_hws(struct intel_engine_cs
*engine
, struct i915_vma
*vma
)
1700 const int hws_offset
= LRC_PPHWSP_PN
* PAGE_SIZE
;
1703 /* The HWSP is part of the default context object in LRC mode. */
1704 hws
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
1706 return PTR_ERR(hws
);
1708 engine
->status_page
.page_addr
= hws
+ hws_offset
;
1709 engine
->status_page
.ggtt_offset
= i915_ggtt_offset(vma
) + hws_offset
;
1710 engine
->status_page
.vma
= vma
;
1716 logical_ring_setup(struct intel_engine_cs
*engine
)
1718 struct drm_i915_private
*dev_priv
= engine
->i915
;
1719 enum forcewake_domains fw_domains
;
1721 intel_engine_setup_common(engine
);
1723 /* Intentionally left blank. */
1724 engine
->buffer
= NULL
;
1726 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
1730 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1731 RING_CONTEXT_STATUS_PTR(engine
),
1732 FW_REG_READ
| FW_REG_WRITE
);
1734 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
1735 RING_CONTEXT_STATUS_BUF_BASE(engine
),
1738 engine
->fw_domains
= fw_domains
;
1740 tasklet_init(&engine
->irq_tasklet
,
1741 intel_lrc_irq_handler
, (unsigned long)engine
);
1743 logical_ring_init_platform_invariants(engine
);
1744 logical_ring_default_vfuncs(engine
);
1745 logical_ring_default_irqs(engine
);
1749 logical_ring_init(struct intel_engine_cs
*engine
)
1751 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
1754 ret
= intel_engine_init_common(engine
);
1758 ret
= execlists_context_deferred_alloc(dctx
, engine
);
1762 /* As this is the default context, always pin it */
1763 ret
= intel_lr_context_pin(dctx
, engine
);
1765 DRM_ERROR("Failed to pin context for %s: %d\n",
1770 /* And setup the hardware status page. */
1771 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
1773 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
1780 intel_logical_ring_cleanup(engine
);
1784 int logical_render_ring_init(struct intel_engine_cs
*engine
)
1786 struct drm_i915_private
*dev_priv
= engine
->i915
;
1789 logical_ring_setup(engine
);
1791 if (HAS_L3_DPF(dev_priv
))
1792 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1794 /* Override some for render ring. */
1795 if (INTEL_GEN(dev_priv
) >= 9)
1796 engine
->init_hw
= gen9_init_render_ring
;
1798 engine
->init_hw
= gen8_init_render_ring
;
1799 engine
->init_context
= gen8_init_rcs_context
;
1800 engine
->emit_flush
= gen8_emit_flush_render
;
1801 engine
->emit_request
= gen8_emit_request_render
;
1803 ret
= intel_engine_create_scratch(engine
, 4096);
1807 ret
= intel_init_workaround_bb(engine
);
1810 * We continue even if we fail to initialize WA batch
1811 * because we only expect rare glitches but nothing
1812 * critical to prevent us from using GPU
1814 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1818 ret
= logical_ring_init(engine
);
1820 lrc_destroy_wa_ctx_obj(engine
);
1826 int logical_xcs_ring_init(struct intel_engine_cs
*engine
)
1828 logical_ring_setup(engine
);
1830 return logical_ring_init(engine
);
1834 make_rpcs(struct drm_i915_private
*dev_priv
)
1839 * No explicit RPCS request is needed to ensure full
1840 * slice/subslice/EU enablement prior to Gen9.
1842 if (INTEL_GEN(dev_priv
) < 9)
1846 * Starting in Gen9, render power gating can leave
1847 * slice/subslice/EU in a partially enabled state. We
1848 * must make an explicit request through RPCS for full
1851 if (INTEL_INFO(dev_priv
)->sseu
.has_slice_pg
) {
1852 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
1853 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.slice_mask
) <<
1854 GEN8_RPCS_S_CNT_SHIFT
;
1855 rpcs
|= GEN8_RPCS_ENABLE
;
1858 if (INTEL_INFO(dev_priv
)->sseu
.has_subslice_pg
) {
1859 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
1860 rpcs
|= hweight8(INTEL_INFO(dev_priv
)->sseu
.subslice_mask
) <<
1861 GEN8_RPCS_SS_CNT_SHIFT
;
1862 rpcs
|= GEN8_RPCS_ENABLE
;
1865 if (INTEL_INFO(dev_priv
)->sseu
.has_eu_pg
) {
1866 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1867 GEN8_RPCS_EU_MIN_SHIFT
;
1868 rpcs
|= INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
<<
1869 GEN8_RPCS_EU_MAX_SHIFT
;
1870 rpcs
|= GEN8_RPCS_ENABLE
;
1876 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
1878 u32 indirect_ctx_offset
;
1880 switch (INTEL_GEN(engine
->i915
)) {
1882 MISSING_CASE(INTEL_GEN(engine
->i915
));
1885 indirect_ctx_offset
=
1886 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1889 indirect_ctx_offset
=
1890 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
1894 return indirect_ctx_offset
;
1898 populate_lr_context(struct i915_gem_context
*ctx
,
1899 struct drm_i915_gem_object
*ctx_obj
,
1900 struct intel_engine_cs
*engine
,
1901 struct intel_ring
*ring
)
1903 struct drm_i915_private
*dev_priv
= ctx
->i915
;
1904 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1910 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1912 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1914 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1918 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
1919 if (IS_ERR(vaddr
)) {
1920 ret
= PTR_ERR(vaddr
);
1921 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
1924 ctx_obj
->dirty
= true;
1926 /* The second page of the context object contains some fields which must
1927 * be set up prior to the first execution. */
1928 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
1930 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1931 * commands followed by (reg, value) pairs. The values we are setting here are
1932 * only for the first context restore: on a subsequent save, the GPU will
1933 * recreate this batchbuffer with new values (including all the missing
1934 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1935 reg_state
[CTX_LRI_HEADER_0
] =
1936 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
1937 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
1938 RING_CONTEXT_CONTROL(engine
),
1939 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
1940 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
1941 (HAS_RESOURCE_STREAMER(dev_priv
) ?
1942 CTX_CTRL_RS_CTX_ENABLE
: 0)));
1943 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
1945 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
1947 /* Ring buffer start address is not known until the buffer is pinned.
1948 * It is written to the context image in execlists_update_context()
1950 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
1951 RING_START(engine
->mmio_base
), 0);
1952 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
1953 RING_CTL(engine
->mmio_base
),
1954 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
1955 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
1956 RING_BBADDR_UDW(engine
->mmio_base
), 0);
1957 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
1958 RING_BBADDR(engine
->mmio_base
), 0);
1959 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
1960 RING_BBSTATE(engine
->mmio_base
),
1962 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
1963 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
1964 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
1965 RING_SBBADDR(engine
->mmio_base
), 0);
1966 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
1967 RING_SBBSTATE(engine
->mmio_base
), 0);
1968 if (engine
->id
== RCS
) {
1969 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
1970 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
1971 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
1972 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
1973 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
1974 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
1975 if (engine
->wa_ctx
.vma
) {
1976 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1977 u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
1979 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
1980 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
1981 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
1983 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
1984 intel_lr_indirect_ctx_offset(engine
) << 6;
1986 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
1987 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
1991 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
1992 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
1993 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
1994 /* PDP values well be assigned later if needed */
1995 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
1997 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
1999 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2001 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2003 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2005 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2007 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2009 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2012 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2013 /* 64b PPGTT (48bit canonical)
2014 * PDP0_DESCRIPTOR contains the base address to PML4 and
2015 * other PDP Descriptors are ignored.
2017 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2020 * PDP*_DESCRIPTOR contains the base address of space supported.
2021 * With dynamic page allocation, PDPs may not be allocated at
2022 * this point. Point the unallocated PDPs to the scratch page
2024 execlists_update_context_pdps(ppgtt
, reg_state
);
2027 if (engine
->id
== RCS
) {
2028 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2029 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2030 make_rpcs(dev_priv
));
2033 i915_gem_object_unpin_map(ctx_obj
);
2039 * intel_lr_context_size() - return the size of the context for an engine
2040 * @engine: which engine to find the context size for
2042 * Each engine may require a different amount of space for a context image,
2043 * so when allocating (or copying) an image, this function can be used to
2044 * find the right size for the specific engine.
2046 * Return: size (in bytes) of an engine-specific context image
2048 * Note: this size includes the HWSP, which is part of the context image
2049 * in LRC mode, but does not include the "shared data page" used with
2050 * GuC submission. The caller should account for this if using the GuC.
2052 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2056 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2058 switch (engine
->id
) {
2060 if (INTEL_GEN(engine
->i915
) >= 9)
2061 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2063 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2069 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2076 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2077 struct intel_engine_cs
*engine
)
2079 struct drm_i915_gem_object
*ctx_obj
;
2080 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2081 struct i915_vma
*vma
;
2082 uint32_t context_size
;
2083 struct intel_ring
*ring
;
2088 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2090 /* One extra page as the sharing data between driver and GuC */
2091 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2093 ctx_obj
= i915_gem_object_create(&ctx
->i915
->drm
, context_size
);
2094 if (IS_ERR(ctx_obj
)) {
2095 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2096 return PTR_ERR(ctx_obj
);
2099 vma
= i915_vma_create(ctx_obj
, &ctx
->i915
->ggtt
.base
, NULL
);
2102 goto error_deref_obj
;
2105 ring
= intel_engine_create_ring(engine
, ctx
->ring_size
);
2107 ret
= PTR_ERR(ring
);
2108 goto error_deref_obj
;
2111 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ring
);
2113 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2114 goto error_ring_free
;
2119 ce
->initialised
= engine
->init_context
== NULL
;
2124 intel_ring_free(ring
);
2126 i915_gem_object_put(ctx_obj
);
2130 void intel_lr_context_resume(struct drm_i915_private
*dev_priv
)
2132 struct i915_gem_context
*ctx
= dev_priv
->kernel_context
;
2133 struct intel_engine_cs
*engine
;
2135 for_each_engine(engine
, dev_priv
) {
2136 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2138 uint32_t *reg_state
;
2143 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
, I915_MAP_WB
);
2144 if (WARN_ON(IS_ERR(vaddr
)))
2147 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2149 reg_state
[CTX_RING_HEAD
+1] = 0;
2150 reg_state
[CTX_RING_TAIL
+1] = 0;
2152 ce
->state
->obj
->dirty
= true;
2153 i915_gem_object_unpin_map(ce
->state
->obj
);