2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
212 FAULT_AND_HALT
, /* Debug only */
214 FAULT_AND_CONTINUE
/* Unsupported */
216 #define GEN8_CTX_ID_SHIFT 32
217 #define GEN8_CTX_ID_WIDTH 21
218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
224 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
225 struct intel_engine_cs
*engine
);
226 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
227 struct intel_engine_cs
*engine
);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @dev_priv: i915 device private
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_i915_private
*dev_priv
, int enable_execlists
)
241 /* On platforms with execlist available, vGPU will only
242 * support execlist mode, no ring buffer mode.
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) && intel_vgpu_active(dev_priv
))
247 if (INTEL_GEN(dev_priv
) >= 9)
250 if (enable_execlists
== 0)
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
) &&
254 USES_PPGTT(dev_priv
) &&
255 i915
.use_mmio_flip
>= 0)
262 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
264 struct drm_i915_private
*dev_priv
= engine
->i915
;
266 if (IS_GEN8(dev_priv
) || IS_GEN9(dev_priv
))
267 engine
->idle_lite_restore_wa
= ~0;
269 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
270 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) &&
271 (engine
->id
== VCS
|| engine
->id
== VCS2
);
273 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
274 if (IS_GEN8(dev_priv
))
275 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
276 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
278 /* TODO: WaDisableLiteRestore when we start using semaphore
279 * signalling between Command Streamers */
280 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
282 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
283 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
284 if (engine
->disable_lite_restore_wa
)
285 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
289 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
290 * descriptor for a pinned context
292 * @ctx: Context to work on
293 * @engine: Engine the descriptor will be used with
295 * The context descriptor encodes various attributes of a context,
296 * including its GTT address and some flags. Because it's fairly
297 * expensive to calculate, we'll just do it once and cache the result,
298 * which remains valid until the context is unpinned.
300 * This is what a descriptor looks like, from LSB to MSB:
301 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
302 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
303 * bits 32-52: ctx ID, a globally unique tag
304 * bits 53-54: mbz, reserved for use by hardware
305 * bits 55-63: group ID, currently unused and set to 0
308 intel_lr_context_descriptor_update(struct i915_gem_context
*ctx
,
309 struct intel_engine_cs
*engine
)
311 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
314 BUILD_BUG_ON(MAX_CONTEXT_HW_ID
> (1<<GEN8_CTX_ID_WIDTH
));
316 desc
= ctx
->desc_template
; /* bits 3-4 */
317 desc
|= engine
->ctx_desc_template
; /* bits 0-11 */
318 desc
|= ce
->lrc_vma
->node
.start
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
320 desc
|= (u64
)ctx
->hw_id
<< GEN8_CTX_ID_SHIFT
; /* bits 32-52 */
325 uint64_t intel_lr_context_descriptor(struct i915_gem_context
*ctx
,
326 struct intel_engine_cs
*engine
)
328 return ctx
->engine
[engine
->id
].lrc_desc
;
331 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
332 struct drm_i915_gem_request
*rq1
)
335 struct intel_engine_cs
*engine
= rq0
->engine
;
336 struct drm_i915_private
*dev_priv
= rq0
->i915
;
340 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
341 rq1
->elsp_submitted
++;
346 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
347 rq0
->elsp_submitted
++;
349 /* You must always write both descriptors in the order below. */
350 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
351 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
353 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
354 /* The context is automatically loaded after the following */
355 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
357 /* ELSP is a wo register, use another nearby reg for posting */
358 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
362 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
364 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
365 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
366 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
367 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
370 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
372 struct intel_engine_cs
*engine
= rq
->engine
;
373 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
374 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
376 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
384 execlists_update_context_pdps(ppgtt
, reg_state
);
387 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
388 struct drm_i915_gem_request
*rq1
)
390 struct drm_i915_private
*dev_priv
= rq0
->i915
;
391 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
393 execlists_update_context(rq0
);
396 execlists_update_context(rq1
);
398 spin_lock_irq(&dev_priv
->uncore
.lock
);
399 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
401 execlists_elsp_write(rq0
, rq1
);
403 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
404 spin_unlock_irq(&dev_priv
->uncore
.lock
);
407 static inline void execlists_context_status_change(
408 struct drm_i915_gem_request
*rq
,
409 unsigned long status
)
412 * Only used when GVT-g is enabled now. When GVT-g is disabled,
413 * The compiler should eliminate this function as dead-code.
415 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
418 atomic_notifier_call_chain(&rq
->ctx
->status_notifier
, status
, rq
);
421 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
423 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
424 struct drm_i915_gem_request
*cursor
, *tmp
;
426 assert_spin_locked(&engine
->execlist_lock
);
429 * If irqs are not active generate a warning as batches that finish
430 * without the irqs may get lost and a GPU Hang may occur.
432 WARN_ON(!intel_irqs_enabled(engine
->i915
));
434 /* Try to read in pairs */
435 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
439 } else if (req0
->ctx
== cursor
->ctx
) {
440 /* Same ctx: ignore first request, as second request
441 * will update tail past first request's workload */
442 cursor
->elsp_submitted
= req0
->elsp_submitted
;
443 list_del(&req0
->execlist_link
);
444 i915_gem_request_unreference(req0
);
447 if (IS_ENABLED(CONFIG_DRM_I915_GVT
)) {
449 * req0 (after merged) ctx requires single
450 * submission, stop picking
452 if (req0
->ctx
->execlists_force_single_submission
)
455 * req0 ctx doesn't require single submission,
456 * but next req ctx requires, stop picking
458 if (cursor
->ctx
->execlists_force_single_submission
)
462 WARN_ON(req1
->elsp_submitted
);
470 execlists_context_status_change(req0
, INTEL_CONTEXT_SCHEDULE_IN
);
473 execlists_context_status_change(req1
,
474 INTEL_CONTEXT_SCHEDULE_IN
);
476 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
478 * WaIdleLiteRestore: make sure we never cause a lite restore
481 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
482 * resubmit the request. See gen8_emit_request() for where we
483 * prepare the padding after the end of the request.
485 struct intel_ringbuffer
*ringbuf
;
487 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
489 req0
->tail
&= ringbuf
->size
- 1;
492 execlists_submit_requests(req0
, req1
);
496 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 ctx_id
)
498 struct drm_i915_gem_request
*head_req
;
500 assert_spin_locked(&engine
->execlist_lock
);
502 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
503 struct drm_i915_gem_request
,
506 if (WARN_ON(!head_req
|| (head_req
->ctx_hw_id
!= ctx_id
)))
509 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
511 if (--head_req
->elsp_submitted
> 0)
514 execlists_context_status_change(head_req
, INTEL_CONTEXT_SCHEDULE_OUT
);
516 list_del(&head_req
->execlist_link
);
517 i915_gem_request_unreference(head_req
);
523 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
526 struct drm_i915_private
*dev_priv
= engine
->i915
;
529 read_pointer
%= GEN8_CSB_ENTRIES
;
531 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
533 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
536 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
543 * intel_lrc_irq_handler() - handle Context Switch interrupts
544 * @data: tasklet handler passed in unsigned long
546 * Check the unread Context Status Buffers and manage the submission of new
547 * contexts to the ELSP accordingly.
549 static void intel_lrc_irq_handler(unsigned long data
)
551 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
552 struct drm_i915_private
*dev_priv
= engine
->i915
;
554 unsigned int read_pointer
, write_pointer
;
555 u32 csb
[GEN8_CSB_ENTRIES
][2];
556 unsigned int csb_read
= 0, i
;
557 unsigned int submit_contexts
= 0;
559 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
561 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
563 read_pointer
= engine
->next_context_status_buffer
;
564 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
565 if (read_pointer
> write_pointer
)
566 write_pointer
+= GEN8_CSB_ENTRIES
;
568 while (read_pointer
< write_pointer
) {
569 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
571 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
576 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
578 /* Update the read pointer to the old write pointer. Manual ringbuffer
579 * management ftw </sarcasm> */
580 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
581 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
582 engine
->next_context_status_buffer
<< 8));
584 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
586 spin_lock(&engine
->execlist_lock
);
588 for (i
= 0; i
< csb_read
; i
++) {
589 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
590 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
591 if (execlists_check_remove_request(engine
, csb
[i
][1]))
592 WARN(1, "Lite Restored request removed from queue\n");
594 WARN(1, "Preemption without Lite Restore\n");
597 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
598 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
600 execlists_check_remove_request(engine
, csb
[i
][1]);
603 if (submit_contexts
) {
604 if (!engine
->disable_lite_restore_wa
||
605 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
606 execlists_context_unqueue(engine
);
609 spin_unlock(&engine
->execlist_lock
);
611 if (unlikely(submit_contexts
> 2))
612 DRM_ERROR("More than two context complete events?\n");
615 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
617 struct intel_engine_cs
*engine
= request
->engine
;
618 struct drm_i915_gem_request
*cursor
;
619 int num_elements
= 0;
621 spin_lock_bh(&engine
->execlist_lock
);
623 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
624 if (++num_elements
> 2)
627 if (num_elements
> 2) {
628 struct drm_i915_gem_request
*tail_req
;
630 tail_req
= list_last_entry(&engine
->execlist_queue
,
631 struct drm_i915_gem_request
,
634 if (request
->ctx
== tail_req
->ctx
) {
635 WARN(tail_req
->elsp_submitted
!= 0,
636 "More than 2 already-submitted reqs queued\n");
637 list_del(&tail_req
->execlist_link
);
638 i915_gem_request_unreference(tail_req
);
642 i915_gem_request_reference(request
);
643 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
644 request
->ctx_hw_id
= request
->ctx
->hw_id
;
645 if (num_elements
== 0)
646 execlists_context_unqueue(engine
);
648 spin_unlock_bh(&engine
->execlist_lock
);
651 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
653 struct intel_engine_cs
*engine
= req
->engine
;
654 uint32_t flush_domains
;
658 if (engine
->gpu_caches_dirty
)
659 flush_domains
= I915_GEM_GPU_DOMAINS
;
661 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
665 engine
->gpu_caches_dirty
= false;
669 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
670 struct list_head
*vmas
)
672 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
673 struct i915_vma
*vma
;
674 uint32_t flush_domains
= 0;
675 bool flush_chipset
= false;
678 list_for_each_entry(vma
, vmas
, exec_list
) {
679 struct drm_i915_gem_object
*obj
= vma
->obj
;
681 if (obj
->active
& other_rings
) {
682 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
687 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
688 flush_chipset
|= i915_gem_clflush_object(obj
, false);
690 flush_domains
|= obj
->base
.write_domain
;
693 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
696 /* Unconditionally invalidate gpu caches and ensure that we do flush
697 * any residual writes from the previous batch.
699 return logical_ring_invalidate_all_caches(req
);
702 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
704 struct intel_engine_cs
*engine
= request
->engine
;
705 struct intel_context
*ce
= &request
->ctx
->engine
[engine
->id
];
708 /* Flush enough space to reduce the likelihood of waiting after
709 * we start building the request - in which case we will just
710 * have to repeat work.
712 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
715 ret
= execlists_context_deferred_alloc(request
->ctx
, engine
);
720 request
->ringbuf
= ce
->ringbuf
;
722 if (i915
.enable_guc_submission
) {
724 * Check that the GuC has space for the request before
725 * going any further, as the i915_add_request() call
726 * later on mustn't fail ...
728 ret
= i915_guc_wq_check_space(request
);
733 ret
= intel_lr_context_pin(request
->ctx
, engine
);
737 ret
= intel_ring_begin(request
, 0);
741 if (!ce
->initialised
) {
742 ret
= engine
->init_context(request
);
746 ce
->initialised
= true;
749 /* Note that after this point, we have committed to using
750 * this request as it is being used to both track the
751 * state of engine initialisation and liveness of the
752 * golden renderstate above. Think twice before you try
753 * to cancel/unwind this request now.
756 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
760 intel_lr_context_unpin(request
->ctx
, engine
);
765 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
766 * @request: Request to advance the logical ringbuffer of.
768 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
769 * really happens during submission is that the context and current tail will be placed
770 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
771 * point, the tail *inside* the context is updated and the ELSP written to.
774 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
776 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
777 struct intel_engine_cs
*engine
= request
->engine
;
779 intel_logical_ring_advance(ringbuf
);
780 request
->tail
= ringbuf
->tail
;
783 * Here we add two extra NOOPs as padding to avoid
784 * lite restore of a context with HEAD==TAIL.
786 * Caller must reserve WA_TAIL_DWORDS for us!
788 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
789 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
790 intel_logical_ring_advance(ringbuf
);
792 if (intel_engine_stopped(engine
))
795 /* We keep the previous context alive until we retire the following
796 * request. This ensures that any the context object is still pinned
797 * for any residual writes the HW makes into it on the context switch
798 * into the next object following the breadcrumb. Otherwise, we may
799 * retire the context too early.
801 request
->previous_context
= engine
->last_context
;
802 engine
->last_context
= request
->ctx
;
804 if (i915
.enable_guc_submission
)
805 i915_guc_submit(request
);
807 execlists_context_queue(request
);
813 * execlists_submission() - submit a batchbuffer for execution, Execlists style
814 * @params: execbuffer call parameters.
815 * @args: execbuffer call arguments.
816 * @vmas: list of vmas.
818 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
819 * away the submission details of the execbuffer ioctl call.
821 * Return: non-zero if the submission fails.
823 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
824 struct drm_i915_gem_execbuffer2
*args
,
825 struct list_head
*vmas
)
827 struct drm_device
*dev
= params
->dev
;
828 struct intel_engine_cs
*engine
= params
->engine
;
829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
830 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
836 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
837 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
838 switch (instp_mode
) {
839 case I915_EXEC_CONSTANTS_REL_GENERAL
:
840 case I915_EXEC_CONSTANTS_ABSOLUTE
:
841 case I915_EXEC_CONSTANTS_REL_SURFACE
:
842 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
843 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
847 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
848 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
849 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
853 /* The HW changed the meaning on this bit on gen6 */
854 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
858 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
862 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
863 DRM_DEBUG("sol reset is gen7 only\n");
867 ret
= execlists_move_to_gpu(params
->request
, vmas
);
871 if (engine
== &dev_priv
->engine
[RCS
] &&
872 instp_mode
!= dev_priv
->relative_constants_mode
) {
873 ret
= intel_ring_begin(params
->request
, 4);
877 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
878 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
879 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
880 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
881 intel_logical_ring_advance(ringbuf
);
883 dev_priv
->relative_constants_mode
= instp_mode
;
886 exec_start
= params
->batch_obj_vm_offset
+
887 args
->batch_start_offset
;
889 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
893 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
895 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
900 void intel_execlists_cancel_requests(struct intel_engine_cs
*engine
)
902 struct drm_i915_gem_request
*req
, *tmp
;
903 LIST_HEAD(cancel_list
);
905 WARN_ON(!mutex_is_locked(&engine
->i915
->dev
->struct_mutex
));
907 spin_lock_bh(&engine
->execlist_lock
);
908 list_replace_init(&engine
->execlist_queue
, &cancel_list
);
909 spin_unlock_bh(&engine
->execlist_lock
);
911 list_for_each_entry_safe(req
, tmp
, &cancel_list
, execlist_link
) {
912 list_del(&req
->execlist_link
);
913 i915_gem_request_unreference(req
);
917 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
919 struct drm_i915_private
*dev_priv
= engine
->i915
;
922 if (!intel_engine_initialized(engine
))
925 ret
= intel_engine_idle(engine
);
927 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
930 /* TODO: Is this correct with Execlists enabled? */
931 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
932 if (intel_wait_for_register(dev_priv
,
933 RING_MI_MODE(engine
->mmio_base
),
934 MODE_IDLE
, MODE_IDLE
,
936 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
939 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
942 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
944 struct intel_engine_cs
*engine
= req
->engine
;
947 if (!engine
->gpu_caches_dirty
)
950 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
954 engine
->gpu_caches_dirty
= false;
958 static int intel_lr_context_pin(struct i915_gem_context
*ctx
,
959 struct intel_engine_cs
*engine
)
961 struct drm_i915_private
*dev_priv
= ctx
->i915
;
962 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
967 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
972 ret
= i915_gem_obj_ggtt_pin(ce
->state
, GEN8_LR_CONTEXT_ALIGN
,
973 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
977 vaddr
= i915_gem_object_pin_map(ce
->state
);
979 ret
= PTR_ERR(vaddr
);
983 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
985 ret
= intel_pin_and_map_ringbuffer_obj(dev_priv
, ce
->ringbuf
);
989 i915_gem_context_reference(ctx
);
990 ce
->lrc_vma
= i915_gem_obj_to_ggtt(ce
->state
);
991 intel_lr_context_descriptor_update(ctx
, engine
);
993 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ce
->ringbuf
->vma
->node
.start
;
994 ce
->lrc_reg_state
= lrc_reg_state
;
995 ce
->state
->dirty
= true;
997 /* Invalidate GuC TLB. */
998 if (i915
.enable_guc_submission
)
999 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1004 i915_gem_object_unpin_map(ce
->state
);
1006 i915_gem_object_ggtt_unpin(ce
->state
);
1012 void intel_lr_context_unpin(struct i915_gem_context
*ctx
,
1013 struct intel_engine_cs
*engine
)
1015 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1017 lockdep_assert_held(&ctx
->i915
->dev
->struct_mutex
);
1018 GEM_BUG_ON(ce
->pin_count
== 0);
1020 if (--ce
->pin_count
)
1023 intel_unpin_ringbuffer_obj(ce
->ringbuf
);
1025 i915_gem_object_unpin_map(ce
->state
);
1026 i915_gem_object_ggtt_unpin(ce
->state
);
1030 ce
->lrc_reg_state
= NULL
;
1032 i915_gem_context_unreference(ctx
);
1035 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1038 struct intel_engine_cs
*engine
= req
->engine
;
1039 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1040 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
1045 engine
->gpu_caches_dirty
= true;
1046 ret
= logical_ring_flush_all_caches(req
);
1050 ret
= intel_ring_begin(req
, w
->count
* 2 + 2);
1054 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1055 for (i
= 0; i
< w
->count
; i
++) {
1056 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1057 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1059 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1061 intel_logical_ring_advance(ringbuf
);
1063 engine
->gpu_caches_dirty
= true;
1064 ret
= logical_ring_flush_all_caches(req
);
1071 #define wa_ctx_emit(batch, index, cmd) \
1073 int __index = (index)++; \
1074 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1077 batch[__index] = (cmd); \
1080 #define wa_ctx_emit_reg(batch, index, reg) \
1081 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1084 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1085 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1086 * but there is a slight complication as this is applied in WA batch where the
1087 * values are only initialized once so we cannot take register value at the
1088 * beginning and reuse it further; hence we save its value to memory, upload a
1089 * constant value with bit21 set and then we restore it back with the saved value.
1090 * To simplify the WA, a constant value is formed by using the default value
1091 * of this register. This shouldn't be a problem because we are only modifying
1092 * it for a short period and this batch in non-premptible. We can ofcourse
1093 * use additional instructions that read the actual value of the register
1094 * at that time and set our bit of interest but it makes the WA complicated.
1096 * This WA is also required for Gen9 so extracting as a function avoids
1099 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1100 uint32_t *const batch
,
1103 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1106 * WaDisableLSQCROPERFforOCL:skl,kbl
1107 * This WA is implemented in skl_init_clock_gating() but since
1108 * this batch updates GEN8_L3SQCREG4 with default value we need to
1109 * set this bit here to retain the WA during flush.
1111 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_E0
) ||
1112 IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_E0
))
1113 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1115 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1116 MI_SRM_LRM_GLOBAL_GTT
));
1117 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1118 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1119 wa_ctx_emit(batch
, index
, 0);
1121 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1122 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1123 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1125 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1126 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1127 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1128 wa_ctx_emit(batch
, index
, 0);
1129 wa_ctx_emit(batch
, index
, 0);
1130 wa_ctx_emit(batch
, index
, 0);
1131 wa_ctx_emit(batch
, index
, 0);
1133 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1134 MI_SRM_LRM_GLOBAL_GTT
));
1135 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1136 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1137 wa_ctx_emit(batch
, index
, 0);
1142 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1144 uint32_t start_alignment
)
1146 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1149 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1151 uint32_t size_alignment
)
1153 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1155 WARN(wa_ctx
->size
% size_alignment
,
1156 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1157 wa_ctx
->size
, size_alignment
);
1162 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1164 * @engine: only applicable for RCS
1165 * @wa_ctx: structure representing wa_ctx
1166 * offset: specifies start of the batch, should be cache-aligned. This is updated
1167 * with the offset value received as input.
1168 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1169 * @batch: page in which WA are loaded
1170 * @offset: This field specifies the start of the batch, it should be
1171 * cache-aligned otherwise it is adjusted accordingly.
1172 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1173 * initialized at the beginning and shared across all contexts but this field
1174 * helps us to have multiple batches at different offsets and select them based
1175 * on a criteria. At the moment this batch always start at the beginning of the page
1176 * and at this point we don't have multiple wa_ctx batch buffers.
1178 * The number of WA applied are not known at the beginning; we use this field
1179 * to return the no of DWORDS written.
1181 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1182 * so it adds NOOPs as padding to make it cacheline aligned.
1183 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1184 * makes a complete batch buffer.
1186 * Return: non-zero if we exceed the PAGE_SIZE limit.
1189 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1190 struct i915_wa_ctx_bb
*wa_ctx
,
1191 uint32_t *const batch
,
1194 uint32_t scratch_addr
;
1195 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1197 /* WaDisableCtxRestoreArbitration:bdw,chv */
1198 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1200 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1201 if (IS_BROADWELL(engine
->i915
)) {
1202 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1208 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1209 /* Actual scratch location is at 128 bytes offset */
1210 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1212 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1213 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1214 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1215 PIPE_CONTROL_CS_STALL
|
1216 PIPE_CONTROL_QW_WRITE
));
1217 wa_ctx_emit(batch
, index
, scratch_addr
);
1218 wa_ctx_emit(batch
, index
, 0);
1219 wa_ctx_emit(batch
, index
, 0);
1220 wa_ctx_emit(batch
, index
, 0);
1222 /* Pad to end of cacheline */
1223 while (index
% CACHELINE_DWORDS
)
1224 wa_ctx_emit(batch
, index
, MI_NOOP
);
1227 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1228 * execution depends on the length specified in terms of cache lines
1229 * in the register CTX_RCS_INDIRECT_CTX
1232 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1236 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1238 * @engine: only applicable for RCS
1239 * @wa_ctx: structure representing wa_ctx
1240 * offset: specifies start of the batch, should be cache-aligned.
1241 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1242 * @batch: page in which WA are loaded
1243 * @offset: This field specifies the start of this batch.
1244 * This batch is started immediately after indirect_ctx batch. Since we ensure
1245 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1247 * The number of DWORDS written are returned using this field.
1249 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1250 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1252 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1253 struct i915_wa_ctx_bb
*wa_ctx
,
1254 uint32_t *const batch
,
1257 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1259 /* WaDisableCtxRestoreArbitration:bdw,chv */
1260 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1262 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1264 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1267 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1268 struct i915_wa_ctx_bb
*wa_ctx
,
1269 uint32_t *const batch
,
1273 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1275 /* WaDisableCtxRestoreArbitration:skl,bxt */
1276 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1277 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1278 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1280 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1281 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1286 /* WaClearSlmSpaceAtContextSwitch:kbl */
1287 /* Actual scratch location is at 128 bytes offset */
1288 if (IS_KBL_REVID(engine
->i915
, 0, KBL_REVID_A0
)) {
1289 uint32_t scratch_addr
1290 = engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1292 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1293 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1294 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1295 PIPE_CONTROL_CS_STALL
|
1296 PIPE_CONTROL_QW_WRITE
));
1297 wa_ctx_emit(batch
, index
, scratch_addr
);
1298 wa_ctx_emit(batch
, index
, 0);
1299 wa_ctx_emit(batch
, index
, 0);
1300 wa_ctx_emit(batch
, index
, 0);
1302 /* Pad to end of cacheline */
1303 while (index
% CACHELINE_DWORDS
)
1304 wa_ctx_emit(batch
, index
, MI_NOOP
);
1306 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1309 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1310 struct i915_wa_ctx_bb
*wa_ctx
,
1311 uint32_t *const batch
,
1314 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1316 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1317 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_B0
) ||
1318 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1319 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1320 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1321 wa_ctx_emit(batch
, index
,
1322 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1323 wa_ctx_emit(batch
, index
, MI_NOOP
);
1326 /* WaClearTdlStateAckDirtyBits:bxt */
1327 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_B0
)) {
1328 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1330 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1331 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1333 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1334 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1336 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1337 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1339 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1340 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1341 wa_ctx_emit(batch
, index
, 0x0);
1342 wa_ctx_emit(batch
, index
, MI_NOOP
);
1345 /* WaDisableCtxRestoreArbitration:skl,bxt */
1346 if (IS_SKL_REVID(engine
->i915
, 0, SKL_REVID_D0
) ||
1347 IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
))
1348 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1350 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1352 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1355 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1359 engine
->wa_ctx
.obj
= i915_gem_object_create(engine
->i915
->dev
,
1361 if (IS_ERR(engine
->wa_ctx
.obj
)) {
1362 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1363 ret
= PTR_ERR(engine
->wa_ctx
.obj
);
1364 engine
->wa_ctx
.obj
= NULL
;
1368 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1370 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1372 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1379 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1381 if (engine
->wa_ctx
.obj
) {
1382 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1383 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1384 engine
->wa_ctx
.obj
= NULL
;
1388 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1394 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1396 WARN_ON(engine
->id
!= RCS
);
1398 /* update this when WA for higher Gen are added */
1399 if (INTEL_GEN(engine
->i915
) > 9) {
1400 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1401 INTEL_GEN(engine
->i915
));
1405 /* some WA perform writes to scratch page, ensure it is valid */
1406 if (engine
->scratch
.obj
== NULL
) {
1407 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1411 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1413 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1417 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1418 batch
= kmap_atomic(page
);
1421 if (IS_GEN8(engine
->i915
)) {
1422 ret
= gen8_init_indirectctx_bb(engine
,
1423 &wa_ctx
->indirect_ctx
,
1429 ret
= gen8_init_perctx_bb(engine
,
1435 } else if (IS_GEN9(engine
->i915
)) {
1436 ret
= gen9_init_indirectctx_bb(engine
,
1437 &wa_ctx
->indirect_ctx
,
1443 ret
= gen9_init_perctx_bb(engine
,
1452 kunmap_atomic(batch
);
1454 lrc_destroy_wa_ctx_obj(engine
);
1459 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1461 struct drm_i915_private
*dev_priv
= engine
->i915
;
1463 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1464 (u32
)engine
->status_page
.gfx_addr
);
1465 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1468 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1470 struct drm_i915_private
*dev_priv
= engine
->i915
;
1471 unsigned int next_context_status_buffer_hw
;
1473 lrc_init_hws(engine
);
1475 I915_WRITE_IMR(engine
,
1476 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1477 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1479 I915_WRITE(RING_MODE_GEN7(engine
),
1480 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1481 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1482 POSTING_READ(RING_MODE_GEN7(engine
));
1485 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1486 * zero, we need to read the write pointer from hardware and use its
1487 * value because "this register is power context save restored".
1488 * Effectively, these states have been observed:
1490 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1491 * BDW | CSB regs not reset | CSB regs reset |
1492 * CHT | CSB regs not reset | CSB regs not reset |
1496 next_context_status_buffer_hw
=
1497 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1500 * When the CSB registers are reset (also after power-up / gpu reset),
1501 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1502 * this special case, so the first element read is CSB[0].
1504 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1505 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1507 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1508 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1510 intel_engine_init_hangcheck(engine
);
1512 return intel_mocs_init_engine(engine
);
1515 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1517 struct drm_i915_private
*dev_priv
= engine
->i915
;
1520 ret
= gen8_init_common_ring(engine
);
1524 /* We need to disable the AsyncFlip performance optimisations in order
1525 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1526 * programmed to '1' on all products.
1528 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1530 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1532 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1534 return init_workarounds_ring(engine
);
1537 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1541 ret
= gen8_init_common_ring(engine
);
1545 return init_workarounds_ring(engine
);
1548 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1550 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1551 struct intel_engine_cs
*engine
= req
->engine
;
1552 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1553 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1556 ret
= intel_ring_begin(req
, num_lri_cmds
* 2 + 2);
1560 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1561 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1562 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1564 intel_logical_ring_emit_reg(ringbuf
,
1565 GEN8_RING_PDP_UDW(engine
, i
));
1566 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1567 intel_logical_ring_emit_reg(ringbuf
,
1568 GEN8_RING_PDP_LDW(engine
, i
));
1569 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1572 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1573 intel_logical_ring_advance(ringbuf
);
1578 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1579 u64 offset
, unsigned dispatch_flags
)
1581 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1582 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1585 /* Don't rely in hw updating PDPs, specially in lite-restore.
1586 * Ideally, we should set Force PD Restore in ctx descriptor,
1587 * but we can't. Force Restore would be a second option, but
1588 * it is unsafe in case of lite-restore (because the ctx is
1589 * not idle). PML4 is allocated during ppgtt init so this is
1590 * not needed in 48-bit.*/
1591 if (req
->ctx
->ppgtt
&&
1592 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1593 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1594 !intel_vgpu_active(req
->i915
)) {
1595 ret
= intel_logical_ring_emit_pdps(req
);
1600 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1603 ret
= intel_ring_begin(req
, 4);
1607 /* FIXME(BDW): Address space and security selectors. */
1608 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1610 (dispatch_flags
& I915_DISPATCH_RS
?
1611 MI_BATCH_RESOURCE_STREAMER
: 0));
1612 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1613 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1614 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1615 intel_logical_ring_advance(ringbuf
);
1620 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1622 struct drm_i915_private
*dev_priv
= engine
->i915
;
1623 unsigned long flags
;
1625 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1628 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1629 if (engine
->irq_refcount
++ == 0) {
1630 I915_WRITE_IMR(engine
,
1631 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1632 POSTING_READ(RING_IMR(engine
->mmio_base
));
1634 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1639 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1641 struct drm_i915_private
*dev_priv
= engine
->i915
;
1642 unsigned long flags
;
1644 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1645 if (--engine
->irq_refcount
== 0) {
1646 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1647 POSTING_READ(RING_IMR(engine
->mmio_base
));
1649 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1652 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1653 u32 invalidate_domains
,
1656 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1657 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1658 struct drm_i915_private
*dev_priv
= request
->i915
;
1662 ret
= intel_ring_begin(request
, 4);
1666 cmd
= MI_FLUSH_DW
+ 1;
1668 /* We always require a command barrier so that subsequent
1669 * commands, such as breadcrumb interrupts, are strictly ordered
1670 * wrt the contents of the write cache being flushed to memory
1671 * (and thus being coherent from the CPU).
1673 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1675 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1676 cmd
|= MI_INVALIDATE_TLB
;
1677 if (engine
== &dev_priv
->engine
[VCS
])
1678 cmd
|= MI_INVALIDATE_BSD
;
1681 intel_logical_ring_emit(ringbuf
, cmd
);
1682 intel_logical_ring_emit(ringbuf
,
1683 I915_GEM_HWS_SCRATCH_ADDR
|
1684 MI_FLUSH_DW_USE_GTT
);
1685 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1686 intel_logical_ring_emit(ringbuf
, 0); /* value */
1687 intel_logical_ring_advance(ringbuf
);
1692 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1693 u32 invalidate_domains
,
1696 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1697 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1698 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1699 bool vf_flush_wa
= false, dc_flush_wa
= false;
1704 flags
|= PIPE_CONTROL_CS_STALL
;
1706 if (flush_domains
) {
1707 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1708 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1709 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1710 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1713 if (invalidate_domains
) {
1714 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1715 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1716 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1717 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1718 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1719 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1720 flags
|= PIPE_CONTROL_QW_WRITE
;
1721 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1724 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1727 if (IS_GEN9(request
->i915
))
1730 /* WaForGAMHang:kbl */
1731 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
1743 ret
= intel_ring_begin(request
, len
);
1748 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1749 intel_logical_ring_emit(ringbuf
, 0);
1750 intel_logical_ring_emit(ringbuf
, 0);
1751 intel_logical_ring_emit(ringbuf
, 0);
1752 intel_logical_ring_emit(ringbuf
, 0);
1753 intel_logical_ring_emit(ringbuf
, 0);
1757 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1758 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_DC_FLUSH_ENABLE
);
1759 intel_logical_ring_emit(ringbuf
, 0);
1760 intel_logical_ring_emit(ringbuf
, 0);
1761 intel_logical_ring_emit(ringbuf
, 0);
1762 intel_logical_ring_emit(ringbuf
, 0);
1765 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1766 intel_logical_ring_emit(ringbuf
, flags
);
1767 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1768 intel_logical_ring_emit(ringbuf
, 0);
1769 intel_logical_ring_emit(ringbuf
, 0);
1770 intel_logical_ring_emit(ringbuf
, 0);
1773 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1774 intel_logical_ring_emit(ringbuf
, PIPE_CONTROL_CS_STALL
);
1775 intel_logical_ring_emit(ringbuf
, 0);
1776 intel_logical_ring_emit(ringbuf
, 0);
1777 intel_logical_ring_emit(ringbuf
, 0);
1778 intel_logical_ring_emit(ringbuf
, 0);
1781 intel_logical_ring_advance(ringbuf
);
1786 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1788 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1791 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1793 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1796 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1799 * On BXT A steppings there is a HW coherency issue whereby the
1800 * MI_STORE_DATA_IMM storing the completed request's seqno
1801 * occasionally doesn't invalidate the CPU cache. Work around this by
1802 * clflushing the corresponding cacheline whenever the caller wants
1803 * the coherency to be guaranteed. Note that this cacheline is known
1804 * to be clean at this point, since we only write it in
1805 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1806 * this clflush in practice becomes an invalidate operation.
1808 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1811 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1813 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1815 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1816 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1820 * Reserve space for 2 NOOPs at the end of each request to be
1821 * used as a workaround for not being allowed to do lite
1822 * restore with HEAD==TAIL (WaIdleLiteRestore).
1824 #define WA_TAIL_DWORDS 2
1826 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1828 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1831 ret
= intel_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1835 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1836 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1838 intel_logical_ring_emit(ringbuf
,
1839 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1840 intel_logical_ring_emit(ringbuf
,
1841 intel_hws_seqno_address(request
->engine
) |
1842 MI_FLUSH_DW_USE_GTT
);
1843 intel_logical_ring_emit(ringbuf
, 0);
1844 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1845 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1846 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1847 return intel_logical_ring_advance_and_submit(request
);
1850 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1852 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1855 ret
= intel_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1859 /* We're using qword write, seqno should be aligned to 8 bytes. */
1860 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1862 /* w/a for post sync ops following a GPGPU operation we
1863 * need a prior CS_STALL, which is emitted by the flush
1864 * following the batch.
1866 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1867 intel_logical_ring_emit(ringbuf
,
1868 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1869 PIPE_CONTROL_CS_STALL
|
1870 PIPE_CONTROL_QW_WRITE
));
1871 intel_logical_ring_emit(ringbuf
,
1872 intel_hws_seqno_address(request
->engine
));
1873 intel_logical_ring_emit(ringbuf
, 0);
1874 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1875 /* We're thrashing one dword of HWS. */
1876 intel_logical_ring_emit(ringbuf
, 0);
1877 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1878 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1879 return intel_logical_ring_advance_and_submit(request
);
1882 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1884 struct render_state so
;
1887 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1891 if (so
.rodata
== NULL
)
1894 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1895 I915_DISPATCH_SECURE
);
1899 ret
= req
->engine
->emit_bb_start(req
,
1900 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1901 I915_DISPATCH_SECURE
);
1905 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1908 i915_gem_render_state_fini(&so
);
1912 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1916 ret
= intel_logical_ring_workarounds_emit(req
);
1920 ret
= intel_rcs_context_init_mocs(req
);
1922 * Failing to program the MOCS is non-fatal.The system will not
1923 * run at peak performance. So generate an error and carry on.
1926 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1928 return intel_lr_context_render_state_init(req
);
1932 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1934 * @engine: Engine Command Streamer.
1937 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
1939 struct drm_i915_private
*dev_priv
;
1941 if (!intel_engine_initialized(engine
))
1945 * Tasklet cannot be active at this point due intel_mark_active/idle
1946 * so this is just for documentation.
1948 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
1949 tasklet_kill(&engine
->irq_tasklet
);
1951 dev_priv
= engine
->i915
;
1953 if (engine
->buffer
) {
1954 intel_logical_ring_stop(engine
);
1955 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
1958 if (engine
->cleanup
)
1959 engine
->cleanup(engine
);
1961 i915_cmd_parser_fini_ring(engine
);
1962 i915_gem_batch_pool_fini(&engine
->batch_pool
);
1964 intel_engine_fini_breadcrumbs(engine
);
1966 if (engine
->status_page
.obj
) {
1967 i915_gem_object_unpin_map(engine
->status_page
.obj
);
1968 engine
->status_page
.obj
= NULL
;
1970 intel_lr_context_unpin(dev_priv
->kernel_context
, engine
);
1972 engine
->idle_lite_restore_wa
= 0;
1973 engine
->disable_lite_restore_wa
= false;
1974 engine
->ctx_desc_template
= 0;
1976 lrc_destroy_wa_ctx_obj(engine
);
1977 engine
->i915
= NULL
;
1981 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
1983 /* Default vfuncs which can be overriden by each engine. */
1984 engine
->init_hw
= gen8_init_common_ring
;
1985 engine
->emit_request
= gen8_emit_request
;
1986 engine
->emit_flush
= gen8_emit_flush
;
1987 engine
->irq_get
= gen8_logical_ring_get_irq
;
1988 engine
->irq_put
= gen8_logical_ring_put_irq
;
1989 engine
->emit_bb_start
= gen8_emit_bb_start
;
1990 engine
->get_seqno
= gen8_get_seqno
;
1991 engine
->set_seqno
= gen8_set_seqno
;
1992 if (IS_BXT_REVID(engine
->i915
, 0, BXT_REVID_A1
)) {
1993 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
1994 engine
->set_seqno
= bxt_a_set_seqno
;
1999 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
2001 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
2002 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
2006 lrc_setup_hws(struct intel_engine_cs
*engine
,
2007 struct drm_i915_gem_object
*dctx_obj
)
2011 /* The HWSP is part of the default context object in LRC mode. */
2012 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
2013 LRC_PPHWSP_PN
* PAGE_SIZE
;
2014 hws
= i915_gem_object_pin_map(dctx_obj
);
2016 return PTR_ERR(hws
);
2017 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
2018 engine
->status_page
.obj
= dctx_obj
;
2024 logical_ring_init(struct intel_engine_cs
*engine
)
2026 struct i915_gem_context
*dctx
= engine
->i915
->kernel_context
;
2029 ret
= intel_engine_init_breadcrumbs(engine
);
2033 ret
= i915_cmd_parser_init_ring(engine
);
2037 ret
= execlists_context_deferred_alloc(dctx
, engine
);
2041 /* As this is the default context, always pin it */
2042 ret
= intel_lr_context_pin(dctx
, engine
);
2044 DRM_ERROR("Failed to pin context for %s: %d\n",
2049 /* And setup the hardware status page. */
2050 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2052 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2059 intel_logical_ring_cleanup(engine
);
2063 static int logical_render_ring_init(struct intel_engine_cs
*engine
)
2065 struct drm_i915_private
*dev_priv
= engine
->i915
;
2068 if (HAS_L3_DPF(dev_priv
))
2069 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2071 /* Override some for render ring. */
2072 if (INTEL_GEN(dev_priv
) >= 9)
2073 engine
->init_hw
= gen9_init_render_ring
;
2075 engine
->init_hw
= gen8_init_render_ring
;
2076 engine
->init_context
= gen8_init_rcs_context
;
2077 engine
->cleanup
= intel_fini_pipe_control
;
2078 engine
->emit_flush
= gen8_emit_flush_render
;
2079 engine
->emit_request
= gen8_emit_request_render
;
2081 ret
= intel_init_pipe_control(engine
);
2085 ret
= intel_init_workaround_bb(engine
);
2088 * We continue even if we fail to initialize WA batch
2089 * because we only expect rare glitches but nothing
2090 * critical to prevent us from using GPU
2092 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2096 ret
= logical_ring_init(engine
);
2098 lrc_destroy_wa_ctx_obj(engine
);
2104 static const struct logical_ring_info
{
2110 int (*init
)(struct intel_engine_cs
*engine
);
2111 } logical_rings
[] = {
2113 .name
= "render ring",
2114 .exec_id
= I915_EXEC_RENDER
,
2115 .guc_id
= GUC_RENDER_ENGINE
,
2116 .mmio_base
= RENDER_RING_BASE
,
2117 .irq_shift
= GEN8_RCS_IRQ_SHIFT
,
2118 .init
= logical_render_ring_init
,
2121 .name
= "blitter ring",
2122 .exec_id
= I915_EXEC_BLT
,
2123 .guc_id
= GUC_BLITTER_ENGINE
,
2124 .mmio_base
= BLT_RING_BASE
,
2125 .irq_shift
= GEN8_BCS_IRQ_SHIFT
,
2126 .init
= logical_ring_init
,
2130 .exec_id
= I915_EXEC_BSD
,
2131 .guc_id
= GUC_VIDEO_ENGINE
,
2132 .mmio_base
= GEN6_BSD_RING_BASE
,
2133 .irq_shift
= GEN8_VCS1_IRQ_SHIFT
,
2134 .init
= logical_ring_init
,
2137 .name
= "bsd2 ring",
2138 .exec_id
= I915_EXEC_BSD
,
2139 .guc_id
= GUC_VIDEO_ENGINE2
,
2140 .mmio_base
= GEN8_BSD2_RING_BASE
,
2141 .irq_shift
= GEN8_VCS2_IRQ_SHIFT
,
2142 .init
= logical_ring_init
,
2145 .name
= "video enhancement ring",
2146 .exec_id
= I915_EXEC_VEBOX
,
2147 .guc_id
= GUC_VIDEOENHANCE_ENGINE
,
2148 .mmio_base
= VEBOX_RING_BASE
,
2149 .irq_shift
= GEN8_VECS_IRQ_SHIFT
,
2150 .init
= logical_ring_init
,
2154 static struct intel_engine_cs
*
2155 logical_ring_setup(struct drm_i915_private
*dev_priv
, enum intel_engine_id id
)
2157 const struct logical_ring_info
*info
= &logical_rings
[id
];
2158 struct intel_engine_cs
*engine
= &dev_priv
->engine
[id
];
2159 enum forcewake_domains fw_domains
;
2162 engine
->name
= info
->name
;
2163 engine
->exec_id
= info
->exec_id
;
2164 engine
->guc_id
= info
->guc_id
;
2165 engine
->mmio_base
= info
->mmio_base
;
2167 engine
->i915
= dev_priv
;
2169 /* Intentionally left blank. */
2170 engine
->buffer
= NULL
;
2172 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2176 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2177 RING_CONTEXT_STATUS_PTR(engine
),
2178 FW_REG_READ
| FW_REG_WRITE
);
2180 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2181 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2184 engine
->fw_domains
= fw_domains
;
2186 INIT_LIST_HEAD(&engine
->active_list
);
2187 INIT_LIST_HEAD(&engine
->request_list
);
2188 INIT_LIST_HEAD(&engine
->buffers
);
2189 INIT_LIST_HEAD(&engine
->execlist_queue
);
2190 spin_lock_init(&engine
->execlist_lock
);
2192 tasklet_init(&engine
->irq_tasklet
,
2193 intel_lrc_irq_handler
, (unsigned long)engine
);
2195 logical_ring_init_platform_invariants(engine
);
2196 logical_ring_default_vfuncs(engine
);
2197 logical_ring_default_irqs(engine
, info
->irq_shift
);
2199 intel_engine_init_hangcheck(engine
);
2200 i915_gem_batch_pool_init(dev_priv
->dev
, &engine
->batch_pool
);
2206 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2209 * This function inits the engines for an Execlists submission style (the
2210 * equivalent in the legacy ringbuffer submission world would be
2211 * i915_gem_init_engines). It does it only for those engines that are present in
2214 * Return: non-zero if the initialization failed.
2216 int intel_logical_rings_init(struct drm_device
*dev
)
2218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2219 unsigned int mask
= 0;
2223 WARN_ON(INTEL_INFO(dev_priv
)->ring_mask
&
2224 GENMASK(sizeof(mask
) * BITS_PER_BYTE
- 1, I915_NUM_ENGINES
));
2226 for (i
= 0; i
< ARRAY_SIZE(logical_rings
); i
++) {
2227 if (!HAS_ENGINE(dev_priv
, i
))
2230 if (!logical_rings
[i
].init
)
2233 ret
= logical_rings
[i
].init(logical_ring_setup(dev_priv
, i
));
2237 mask
|= ENGINE_MASK(i
);
2241 * Catch failures to update logical_rings table when the new engines
2242 * are added to the driver by a warning and disabling the forgotten
2245 if (WARN_ON(mask
!= INTEL_INFO(dev_priv
)->ring_mask
)) {
2246 struct intel_device_info
*info
=
2247 (struct intel_device_info
*)&dev_priv
->info
;
2248 info
->ring_mask
= mask
;
2254 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
2255 intel_logical_ring_cleanup(&dev_priv
->engine
[i
]);
2261 make_rpcs(struct drm_i915_private
*dev_priv
)
2266 * No explicit RPCS request is needed to ensure full
2267 * slice/subslice/EU enablement prior to Gen9.
2269 if (INTEL_GEN(dev_priv
) < 9)
2273 * Starting in Gen9, render power gating can leave
2274 * slice/subslice/EU in a partially enabled state. We
2275 * must make an explicit request through RPCS for full
2278 if (INTEL_INFO(dev_priv
)->has_slice_pg
) {
2279 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2280 rpcs
|= INTEL_INFO(dev_priv
)->slice_total
<<
2281 GEN8_RPCS_S_CNT_SHIFT
;
2282 rpcs
|= GEN8_RPCS_ENABLE
;
2285 if (INTEL_INFO(dev_priv
)->has_subslice_pg
) {
2286 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2287 rpcs
|= INTEL_INFO(dev_priv
)->subslice_per_slice
<<
2288 GEN8_RPCS_SS_CNT_SHIFT
;
2289 rpcs
|= GEN8_RPCS_ENABLE
;
2292 if (INTEL_INFO(dev_priv
)->has_eu_pg
) {
2293 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2294 GEN8_RPCS_EU_MIN_SHIFT
;
2295 rpcs
|= INTEL_INFO(dev_priv
)->eu_per_subslice
<<
2296 GEN8_RPCS_EU_MAX_SHIFT
;
2297 rpcs
|= GEN8_RPCS_ENABLE
;
2303 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2305 u32 indirect_ctx_offset
;
2307 switch (INTEL_GEN(engine
->i915
)) {
2309 MISSING_CASE(INTEL_GEN(engine
->i915
));
2312 indirect_ctx_offset
=
2313 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2316 indirect_ctx_offset
=
2317 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2321 return indirect_ctx_offset
;
2325 populate_lr_context(struct i915_gem_context
*ctx
,
2326 struct drm_i915_gem_object
*ctx_obj
,
2327 struct intel_engine_cs
*engine
,
2328 struct intel_ringbuffer
*ringbuf
)
2330 struct drm_i915_private
*dev_priv
= ctx
->i915
;
2331 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2337 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2339 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2341 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2345 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2346 if (IS_ERR(vaddr
)) {
2347 ret
= PTR_ERR(vaddr
);
2348 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2351 ctx_obj
->dirty
= true;
2353 /* The second page of the context object contains some fields which must
2354 * be set up prior to the first execution. */
2355 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2357 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2358 * commands followed by (reg, value) pairs. The values we are setting here are
2359 * only for the first context restore: on a subsequent save, the GPU will
2360 * recreate this batchbuffer with new values (including all the missing
2361 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2362 reg_state
[CTX_LRI_HEADER_0
] =
2363 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2364 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2365 RING_CONTEXT_CONTROL(engine
),
2366 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2367 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2368 (HAS_RESOURCE_STREAMER(dev_priv
) ?
2369 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2370 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2372 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2374 /* Ring buffer start address is not known until the buffer is pinned.
2375 * It is written to the context image in execlists_update_context()
2377 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2378 RING_START(engine
->mmio_base
), 0);
2379 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2380 RING_CTL(engine
->mmio_base
),
2381 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2382 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2383 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2384 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2385 RING_BBADDR(engine
->mmio_base
), 0);
2386 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2387 RING_BBSTATE(engine
->mmio_base
),
2389 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2390 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2391 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2392 RING_SBBADDR(engine
->mmio_base
), 0);
2393 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2394 RING_SBBSTATE(engine
->mmio_base
), 0);
2395 if (engine
->id
== RCS
) {
2396 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2397 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2398 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2399 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2400 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2401 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2402 if (engine
->wa_ctx
.obj
) {
2403 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2404 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2406 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2407 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2408 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2410 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2411 intel_lr_indirect_ctx_offset(engine
) << 6;
2413 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2414 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2418 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2419 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2420 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2421 /* PDP values well be assigned later if needed */
2422 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2424 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2426 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2428 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2430 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2432 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2434 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2436 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2439 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2440 /* 64b PPGTT (48bit canonical)
2441 * PDP0_DESCRIPTOR contains the base address to PML4 and
2442 * other PDP Descriptors are ignored.
2444 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2447 * PDP*_DESCRIPTOR contains the base address of space supported.
2448 * With dynamic page allocation, PDPs may not be allocated at
2449 * this point. Point the unallocated PDPs to the scratch page
2451 execlists_update_context_pdps(ppgtt
, reg_state
);
2454 if (engine
->id
== RCS
) {
2455 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2456 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2457 make_rpcs(dev_priv
));
2460 i915_gem_object_unpin_map(ctx_obj
);
2466 * intel_lr_context_size() - return the size of the context for an engine
2467 * @engine: which engine to find the context size for
2469 * Each engine may require a different amount of space for a context image,
2470 * so when allocating (or copying) an image, this function can be used to
2471 * find the right size for the specific engine.
2473 * Return: size (in bytes) of an engine-specific context image
2475 * Note: this size includes the HWSP, which is part of the context image
2476 * in LRC mode, but does not include the "shared data page" used with
2477 * GuC submission. The caller should account for this if using the GuC.
2479 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2483 WARN_ON(INTEL_GEN(engine
->i915
) < 8);
2485 switch (engine
->id
) {
2487 if (INTEL_GEN(engine
->i915
) >= 9)
2488 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2490 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2496 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2504 * execlists_context_deferred_alloc() - create the LRC specific bits of a context
2505 * @ctx: LR context to create.
2506 * @engine: engine to be used with the context.
2508 * This function can be called more than once, with different engines, if we plan
2509 * to use the context with them. The context backing objects and the ringbuffers
2510 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2511 * the creation is a deferred call: it's better to make sure first that we need to use
2512 * a given ring with the context.
2514 * Return: non-zero on error.
2516 static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx
,
2517 struct intel_engine_cs
*engine
)
2519 struct drm_i915_gem_object
*ctx_obj
;
2520 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2521 uint32_t context_size
;
2522 struct intel_ringbuffer
*ringbuf
;
2527 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2529 /* One extra page as the sharing data between driver and GuC */
2530 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2532 ctx_obj
= i915_gem_object_create(ctx
->i915
->dev
, context_size
);
2533 if (IS_ERR(ctx_obj
)) {
2534 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2535 return PTR_ERR(ctx_obj
);
2538 ringbuf
= intel_engine_create_ringbuffer(engine
, ctx
->ring_size
);
2539 if (IS_ERR(ringbuf
)) {
2540 ret
= PTR_ERR(ringbuf
);
2541 goto error_deref_obj
;
2544 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2546 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2550 ce
->ringbuf
= ringbuf
;
2551 ce
->state
= ctx_obj
;
2552 ce
->initialised
= engine
->init_context
== NULL
;
2557 intel_ringbuffer_free(ringbuf
);
2559 drm_gem_object_unreference(&ctx_obj
->base
);
2565 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2566 struct i915_gem_context
*ctx
)
2568 struct intel_engine_cs
*engine
;
2570 for_each_engine(engine
, dev_priv
) {
2571 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2572 struct drm_i915_gem_object
*ctx_obj
= ce
->state
;
2574 uint32_t *reg_state
;
2579 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2580 if (WARN_ON(IS_ERR(vaddr
)))
2583 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2584 ctx_obj
->dirty
= true;
2586 reg_state
[CTX_RING_HEAD
+1] = 0;
2587 reg_state
[CTX_RING_TAIL
+1] = 0;
2589 i915_gem_object_unpin_map(ctx_obj
);
2591 ce
->ringbuf
->head
= 0;
2592 ce
->ringbuf
->tail
= 0;