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Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34
35 /**
36 * DOC: RC6
37 *
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
57
58 static void gen9_init_clock_gating(struct drm_device *dev)
59 {
60 struct drm_i915_private *dev_priv = dev->dev_private;
61
62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
82 }
83
84 static void bxt_init_clock_gating(struct drm_device *dev)
85 {
86 struct drm_i915_private *dev_priv = to_i915(dev);
87
88 gen9_init_clock_gating(dev);
89
90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
94 /*
95 * FIXME:
96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
97 */
98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
108 }
109
110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
111 {
112 struct drm_i915_private *dev_priv = to_i915(dev);
113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147 }
148
149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150 {
151 struct drm_i915_private *dev_priv = to_i915(dev);
152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
177 dev_priv->ips.r_t = dev_priv->mem_freq;
178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
209 dev_priv->ips.c_m = 0;
210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
211 dev_priv->ips.c_m = 1;
212 } else {
213 dev_priv->ips.c_m = 2;
214 }
215 }
216
217 static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253 };
254
255 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
256 int is_ddr3,
257 int fsb,
258 int mem)
259 {
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277 }
278
279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280 {
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299 }
300
301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302 {
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315 }
316
317 #define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
321 {
322 struct drm_device *dev = &dev_priv->drm;
323 u32 val;
324
325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
327 POSTING_READ(FW_BLC_SELF_VLV);
328 dev_priv->wm.vlv.cxsr = enable;
329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
331 POSTING_READ(FW_BLC_SELF);
332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
336 POSTING_READ(DSPFW3);
337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
341 POSTING_READ(FW_BLC_SELF);
342 } else if (IS_I915GM(dev)) {
343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
351 POSTING_READ(INSTPM);
352 } else {
353 return;
354 }
355
356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
358 }
359
360
361 /*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
375 static const int pessimal_latency_ns = 5000;
376
377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380 static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382 {
383 struct drm_i915_private *dev_priv = to_i915(dev);
384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430 }
431
432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
433 {
434 struct drm_i915_private *dev_priv = to_i915(dev);
435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446 }
447
448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
449 {
450 struct drm_i915_private *dev_priv = to_i915(dev);
451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463 }
464
465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
466 {
467 struct drm_i915_private *dev_priv = to_i915(dev);
468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479 }
480
481 /* Pineview has different values for various configs */
482 static const struct intel_watermark_params pineview_display_wm = {
483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
488 };
489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
495 };
496 static const struct intel_watermark_params pineview_cursor_wm = {
497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
502 };
503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
509 };
510 static const struct intel_watermark_params g4x_wm_info = {
511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
516 };
517 static const struct intel_watermark_params g4x_cursor_wm_info = {
518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
523 };
524 static const struct intel_watermark_params i965_cursor_wm_info = {
525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
530 };
531 static const struct intel_watermark_params i945_wm_info = {
532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
537 };
538 static const struct intel_watermark_params i915_wm_info = {
539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
544 };
545 static const struct intel_watermark_params i830_a_wm_info = {
546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
551 };
552 static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558 };
559 static const struct intel_watermark_params i845_wm_info = {
560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
565 };
566
567 /**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
571 * @cpp: bytes per pixel
572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
587 int fifo_size, int cpp,
588 unsigned long latency_ns)
589 {
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
624 return wm_size;
625 }
626
627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628 {
629 struct drm_crtc *crtc, *enabled = NULL;
630
631 for_each_crtc(dev, crtc) {
632 if (intel_crtc_active(crtc)) {
633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640 }
641
642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
643 {
644 struct drm_device *dev = unused_crtc->dev;
645 struct drm_i915_private *dev_priv = to_i915(dev);
646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
655 intel_set_memory_cxsr(dev_priv, false);
656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
663 int clock = adjusted_mode->crtc_clock;
664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
668 cpp, latency->display_sr);
669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
671 reg |= FW_WM(wm, SR);
672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
678 cpp, latency->cursor_sr);
679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
681 reg |= FW_WM(wm, CURSOR_SR);
682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
687 cpp, latency->display_hpll_disable);
688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
690 reg |= FW_WM(wm, HPLL_SR);
691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
696 cpp, latency->cursor_hpll_disable);
697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
699 reg |= FW_WM(wm, HPLL_CURSOR);
700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
703 intel_set_memory_cxsr(dev_priv, true);
704 } else {
705 intel_set_memory_cxsr(dev_priv, false);
706 }
707 }
708
709 static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717 {
718 struct drm_crtc *crtc;
719 const struct drm_display_mode *adjusted_mode;
720 int htotal, hdisplay, clock, cpp;
721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
725 if (!intel_crtc_active(crtc)) {
726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
732 clock = adjusted_mode->crtc_clock;
733 htotal = adjusted_mode->crtc_htotal;
734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
736
737 /* Use the small buffer method to calculate plane watermark */
738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
748 line_time_us = max(htotal * 1000 / clock, 1);
749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760 }
761
762 /*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769 static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773 {
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795 }
796
797 static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803 {
804 struct drm_crtc *crtc;
805 const struct drm_display_mode *adjusted_mode;
806 int hdisplay, htotal, cpp, clock;
807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
819 clock = adjusted_mode->crtc_clock;
820 htotal = adjusted_mode->crtc_htotal;
821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
823
824 line_time_us = max(htotal * 1000 / clock, 1);
825 line_count = (latency_ns / line_time_us + 1000) / 1000;
826 line_size = hdisplay * cpp;
827
828 /* Use the minimum of the small and large buffer method for primary */
829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843 }
844
845 #define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
848 static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850 {
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
860 I915_WRITE(DSPFW1,
861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
865 I915_WRITE(DSPFW2,
866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
869 I915_WRITE(DSPFW3,
870 FW_WM(wm->sr.cursor, CURSOR_SR));
871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
876 I915_WRITE(DSPFW8_CHV,
877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
879 I915_WRITE(DSPFW9_CHV,
880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
882 I915_WRITE(DSPHOWM,
883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
893 } else {
894 I915_WRITE(DSPFW7,
895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
897 I915_WRITE(DSPHOWM,
898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
905 }
906
907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
913 POSTING_READ(DSPFW1);
914 }
915
916 #undef FW_WM_VLV
917
918 enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
922 };
923
924 /* latency must be in 0.1us units. */
925 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
928 unsigned int cpp,
929 unsigned int latency)
930 {
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
934 ret = (ret + 1) * horiz_pixels * cpp;
935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938 }
939
940 static void vlv_setup_wm_latency(struct drm_device *dev)
941 {
942 struct drm_i915_private *dev_priv = to_i915(dev);
943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
954 }
955 }
956
957 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961 {
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
963 int clock, htotal, cpp, width, wm;
964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
968 if (!state->base.visible)
969 return 0;
970
971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
987 wm = vlv_wm_method2(clock, htotal, width, cpp,
988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992 }
993
994 static void vlv_compute_fifo(struct intel_crtc *crtc)
995 {
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
1010 if (state->base.visible) {
1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
1026 if (!state->base.visible) {
1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059 }
1060
1061 static void vlv_invert_wms(struct intel_crtc *crtc)
1062 {
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093 }
1094
1095 static void vlv_compute_wm(struct intel_crtc *crtc)
1096 {
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1107
1108 wm_state->num_active_planes = 0;
1109
1110 vlv_compute_fifo(crtc);
1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
1126 if (!state->base.visible)
1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
1167 wm_state->wm[level].cursor;
1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192 }
1193
1194 #define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198 {
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280 }
1281
1282 #undef VLV_FIFO
1283
1284 static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286 {
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
1290 wm->level = to_i915(dev)->wm.max_level;
1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328 }
1329
1330 static void vlv_update_wm(struct drm_crtc *crtc)
1331 {
1332 struct drm_device *dev = crtc->dev;
1333 struct drm_i915_private *dev_priv = to_i915(dev);
1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
1338 vlv_compute_wm(intel_crtc);
1339 vlv_merge_wm(dev, &wm);
1340
1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
1344 return;
1345 }
1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1356 intel_set_memory_cxsr(dev_priv, false);
1357
1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1370 intel_set_memory_cxsr(dev_priv, true);
1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
1381 }
1382
1383 #define single_plane_enabled(mask) is_power_of_2(mask)
1384
1385 static void g4x_update_wm(struct drm_crtc *crtc)
1386 {
1387 struct drm_device *dev = crtc->dev;
1388 static const int sr_latency_ns = 12000;
1389 struct drm_i915_private *dev_priv = to_i915(dev);
1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
1393 bool cxsr_enabled;
1394
1395 if (g4x_compute_wm0(dev, PIPE_A,
1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
1398 &planea_wm, &cursora_wm))
1399 enabled |= 1 << PIPE_A;
1400
1401 if (g4x_compute_wm0(dev, PIPE_B,
1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
1404 &planeb_wm, &cursorb_wm))
1405 enabled |= 1 << PIPE_B;
1406
1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
1412 &plane_sr, &cursor_sr)) {
1413 cxsr_enabled = true;
1414 } else {
1415 cxsr_enabled = false;
1416 intel_set_memory_cxsr(dev_priv, false);
1417 plane_sr = cursor_sr = 0;
1418 }
1419
1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
1431 I915_WRITE(DSPFW2,
1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433 FW_WM(cursora_wm, CURSORA));
1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1437 FW_WM(cursor_sr, CURSOR_SR));
1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
1441 }
1442
1443 static void i965_update_wm(struct drm_crtc *unused_crtc)
1444 {
1445 struct drm_device *dev = unused_crtc->dev;
1446 struct drm_i915_private *dev_priv = to_i915(dev);
1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
1450 bool cxsr_enabled;
1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1458 int clock = adjusted_mode->crtc_clock;
1459 int htotal = adjusted_mode->crtc_htotal;
1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1462 unsigned long line_time_us;
1463 int entries;
1464
1465 line_time_us = max(htotal * 1000 / clock, 1);
1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469 cpp * hdisplay;
1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479 cpp * crtc->cursor->state->crtc_w;
1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
1491 cxsr_enabled = true;
1492 } else {
1493 cxsr_enabled = false;
1494 /* Turn off self refresh if both pipes are enabled */
1495 intel_set_memory_cxsr(dev_priv, false);
1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
1508 /* update cursor SR watermark */
1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
1513 }
1514
1515 #undef FW_WM
1516
1517 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1518 {
1519 struct drm_device *dev = unused_crtc->dev;
1520 struct drm_i915_private *dev_priv = to_i915(dev);
1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
1534 wm_info = &i830_a_wm_info;
1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
1538 if (intel_crtc_active(crtc)) {
1539 const struct drm_display_mode *adjusted_mode;
1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546 wm_info, fifo_size, cpp,
1547 pessimal_latency_ns);
1548 enabled = crtc;
1549 } else {
1550 planea_wm = fifo_size - wm_info->guard_size;
1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
1560 if (intel_crtc_active(crtc)) {
1561 const struct drm_display_mode *adjusted_mode;
1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568 wm_info, fifo_size, cpp,
1569 pessimal_latency_ns);
1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
1574 } else {
1575 planeb_wm = fifo_size - wm_info->guard_size;
1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582 if (IS_I915GM(dev) && enabled) {
1583 struct drm_i915_gem_object *obj;
1584
1585 obj = intel_fb_obj(enabled->primary->state->fb);
1586
1587 /* self-refresh seems busted with untiled */
1588 if (!i915_gem_object_is_tiled(obj))
1589 enabled = NULL;
1590 }
1591
1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
1598 intel_set_memory_cxsr(dev_priv, false);
1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1605 int clock = adjusted_mode->crtc_clock;
1606 int htotal = adjusted_mode->crtc_htotal;
1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1609 unsigned long line_time_us;
1610 int entries;
1611
1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
1615 line_time_us = max(htotal * 1000 / clock, 1);
1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619 cpp * hdisplay;
1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1629 else
1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
1648 }
1649
1650 static void i845_update_wm(struct drm_crtc *unused_crtc)
1651 {
1652 struct drm_device *dev = unused_crtc->dev;
1653 struct drm_i915_private *dev_priv = to_i915(dev);
1654 struct drm_crtc *crtc;
1655 const struct drm_display_mode *adjusted_mode;
1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1665 &i845_wm_info,
1666 dev_priv->display.get_fifo_size(dev, 0),
1667 4, pessimal_latency_ns);
1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674 }
1675
1676 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1677 {
1678 uint32_t pixel_rate;
1679
1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
1685 if (pipe_config->pch_pfit.enabled) {
1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
1691
1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707 }
1708
1709 /* latency must be in 0.1us units. */
1710 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1711 {
1712 uint64_t ret;
1713
1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
1717 ret = (uint64_t) pixel_rate * cpp * latency;
1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721 }
1722
1723 /* latency must be in 0.1us units. */
1724 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1725 uint32_t horiz_pixels, uint8_t cpp,
1726 uint32_t latency)
1727 {
1728 uint32_t ret;
1729
1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
1734
1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1736 ret = (ret + 1) * horiz_pixels * cpp;
1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739 }
1740
1741 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1742 uint8_t cpp)
1743 {
1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
1750 if (WARN_ON(!cpp))
1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1756 }
1757
1758 struct ilk_wm_maximums {
1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763 };
1764
1765 /*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
1769 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1770 const struct intel_plane_state *pstate,
1771 uint32_t mem_value,
1772 bool is_lp)
1773 {
1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1776 uint32_t method1, method2;
1777
1778 if (!cstate->base.active || !pstate->base.visible)
1779 return 0;
1780
1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1782
1783 if (!is_lp)
1784 return method1;
1785
1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
1788 drm_rect_width(&pstate->base.dst),
1789 cpp, mem_value);
1790
1791 return min(method1, method2);
1792 }
1793
1794 /*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
1798 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1799 const struct intel_plane_state *pstate,
1800 uint32_t mem_value)
1801 {
1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804 uint32_t method1, method2;
1805
1806 if (!cstate->base.active || !pstate->base.visible)
1807 return 0;
1808
1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
1812 drm_rect_width(&pstate->base.dst),
1813 cpp, mem_value);
1814 return min(method1, method2);
1815 }
1816
1817 /*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
1821 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1822 const struct intel_plane_state *pstate,
1823 uint32_t mem_value)
1824 {
1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1832
1833 if (!cstate->base.active)
1834 return 0;
1835
1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
1838 width, cpp, mem_value);
1839 }
1840
1841 /* Only for WM_LP. */
1842 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1843 const struct intel_plane_state *pstate,
1844 uint32_t pri_val)
1845 {
1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1848
1849 if (!cstate->base.active || !pstate->base.visible)
1850 return 0;
1851
1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1853 }
1854
1855 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856 {
1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
1860 return 768;
1861 else
1862 return 512;
1863 }
1864
1865 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867 {
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880 }
1881
1882 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884 {
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889 }
1890
1891 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892 {
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897 }
1898
1899 /* Calculate the maximum primary/sprite plane watermark */
1900 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
1902 const struct intel_wm_config *config,
1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905 {
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
1907
1908 /* if sprites aren't enabled, sprites get nothing */
1909 if (is_sprite && !config->sprites_enabled)
1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
1913 if (level == 0 || config->num_pipes_active > 1) {
1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
1925 if (config->sprites_enabled) {
1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1938 }
1939
1940 /* Calculate the maximum cursor plane watermark */
1941 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1942 int level,
1943 const struct intel_wm_config *config)
1944 {
1945 /* HSW LP1+ watermarks w/ multiple pipes */
1946 if (level > 0 && config->num_pipes_active > 1)
1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
1950 return ilk_cursor_wm_reg_max(dev, level);
1951 }
1952
1953 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
1957 struct ilk_wm_maximums *max)
1958 {
1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
1962 max->fbc = ilk_fbc_wm_reg_max(dev);
1963 }
1964
1965 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968 {
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973 }
1974
1975 static bool ilk_validate_wm_level(int level,
1976 const struct ilk_wm_maximums *max,
1977 struct intel_wm_level *result)
1978 {
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
2013 return ret;
2014 }
2015
2016 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2017 const struct intel_crtc *intel_crtc,
2018 int level,
2019 struct intel_crtc_state *cstate,
2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
2023 struct intel_wm_level *result)
2024 {
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
2048 result->enable = true;
2049 }
2050
2051 static uint32_t
2052 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2053 {
2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
2058 u32 linetime, ips_linetime;
2059
2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
2064 if (WARN_ON(intel_state->cdclk == 0))
2065 return 0;
2066
2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073 intel_state->cdclk);
2074
2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
2077 }
2078
2079 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2080 {
2081 struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
2085 int ret, i;
2086 int level, max_level = ilk_wm_max_level(dev);
2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
2129 /*
2130 * WaWmMemoryReadLatency:skl
2131 *
2132 * punit doesn't take into account the read latency so we need
2133 * to add 2us to the various latency levels we retrieve from
2134 * the punit.
2135 * - W0 is a bit special in that it's the only level that
2136 * can't be disabled if we want to have display working, so
2137 * we always add 2us there.
2138 * - For levels >=1, punit returns 0us latency when they are
2139 * disabled, so we respect that and don't add 2us then
2140 *
2141 * Additionally, if a level n (n > 1) has a 0us latency, all
2142 * levels m (m >= n) need to be disabled. We make sure to
2143 * sanitize the values out of the punit to satisfy this
2144 * requirement.
2145 */
2146 wm[0] += 2;
2147 for (level = 1; level <= max_level; level++)
2148 if (wm[level] != 0)
2149 wm[level] += 2;
2150 else {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
2153
2154 break;
2155 }
2156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2157 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159 wm[0] = (sskpd >> 56) & 0xFF;
2160 if (wm[0] == 0)
2161 wm[0] = sskpd & 0xF;
2162 wm[1] = (sskpd >> 4) & 0xFF;
2163 wm[2] = (sskpd >> 12) & 0xFF;
2164 wm[3] = (sskpd >> 20) & 0x1FF;
2165 wm[4] = (sskpd >> 32) & 0x1FF;
2166 } else if (INTEL_INFO(dev)->gen >= 6) {
2167 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2173 } else if (INTEL_INFO(dev)->gen >= 5) {
2174 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176 /* ILK primary LP0 latency is 700 ns */
2177 wm[0] = 7;
2178 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2180 }
2181 }
2182
2183 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184 {
2185 /* ILK sprite LP0 latency is 1300 ns */
2186 if (IS_GEN5(dev))
2187 wm[0] = 13;
2188 }
2189
2190 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191 {
2192 /* ILK cursor LP0 latency is 1300 ns */
2193 if (IS_GEN5(dev))
2194 wm[0] = 13;
2195
2196 /* WaDoubleCursorLP3Latency:ivb */
2197 if (IS_IVYBRIDGE(dev))
2198 wm[3] *= 2;
2199 }
2200
2201 int ilk_wm_max_level(const struct drm_device *dev)
2202 {
2203 /* how many WM levels are we expecting */
2204 if (INTEL_INFO(dev)->gen >= 9)
2205 return 7;
2206 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2207 return 4;
2208 else if (INTEL_INFO(dev)->gen >= 6)
2209 return 3;
2210 else
2211 return 2;
2212 }
2213
2214 static void intel_print_wm_latency(struct drm_device *dev,
2215 const char *name,
2216 const uint16_t wm[8])
2217 {
2218 int level, max_level = ilk_wm_max_level(dev);
2219
2220 for (level = 0; level <= max_level; level++) {
2221 unsigned int latency = wm[level];
2222
2223 if (latency == 0) {
2224 DRM_ERROR("%s WM%d latency not provided\n",
2225 name, level);
2226 continue;
2227 }
2228
2229 /*
2230 * - latencies are in us on gen9.
2231 * - before then, WM1+ latency values are in 0.5us units
2232 */
2233 if (IS_GEN9(dev))
2234 latency *= 10;
2235 else if (level > 0)
2236 latency *= 5;
2237
2238 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239 name, level, wm[level],
2240 latency / 10, latency % 10);
2241 }
2242 }
2243
2244 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245 uint16_t wm[5], uint16_t min)
2246 {
2247 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2248
2249 if (wm[0] >= min)
2250 return false;
2251
2252 wm[0] = max(wm[0], min);
2253 for (level = 1; level <= max_level; level++)
2254 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256 return true;
2257 }
2258
2259 static void snb_wm_latency_quirk(struct drm_device *dev)
2260 {
2261 struct drm_i915_private *dev_priv = to_i915(dev);
2262 bool changed;
2263
2264 /*
2265 * The BIOS provided WM memory latency values are often
2266 * inadequate for high resolution displays. Adjust them.
2267 */
2268 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272 if (!changed)
2273 return;
2274
2275 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279 }
2280
2281 static void ilk_setup_wm_latency(struct drm_device *dev)
2282 {
2283 struct drm_i915_private *dev_priv = to_i915(dev);
2284
2285 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288 sizeof(dev_priv->wm.pri_latency));
2289 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291
2292 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2294
2295 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2298
2299 if (IS_GEN6(dev))
2300 snb_wm_latency_quirk(dev);
2301 }
2302
2303 static void skl_setup_wm_latency(struct drm_device *dev)
2304 {
2305 struct drm_i915_private *dev_priv = to_i915(dev);
2306
2307 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309 }
2310
2311 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312 struct intel_pipe_wm *pipe_wm)
2313 {
2314 /* LP0 watermark maximums depend on this pipe alone */
2315 const struct intel_wm_config config = {
2316 .num_pipes_active = 1,
2317 .sprites_enabled = pipe_wm->sprites_enabled,
2318 .sprites_scaled = pipe_wm->sprites_scaled,
2319 };
2320 struct ilk_wm_maximums max;
2321
2322 /* LP0 watermarks always use 1/2 DDB partitioning */
2323 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325 /* At least LP0 must be valid */
2326 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328 return false;
2329 }
2330
2331 return true;
2332 }
2333
2334 /* Compute new watermarks for the pipe */
2335 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2336 {
2337 struct drm_atomic_state *state = cstate->base.state;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2339 struct intel_pipe_wm *pipe_wm;
2340 struct drm_device *dev = state->dev;
2341 const struct drm_i915_private *dev_priv = to_i915(dev);
2342 struct intel_plane *intel_plane;
2343 struct intel_plane_state *pristate = NULL;
2344 struct intel_plane_state *sprstate = NULL;
2345 struct intel_plane_state *curstate = NULL;
2346 int level, max_level = ilk_wm_max_level(dev), usable_level;
2347 struct ilk_wm_maximums max;
2348
2349 pipe_wm = &cstate->wm.ilk.optimal;
2350
2351 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2352 struct intel_plane_state *ps;
2353
2354 ps = intel_atomic_get_existing_plane_state(state,
2355 intel_plane);
2356 if (!ps)
2357 continue;
2358
2359 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2360 pristate = ps;
2361 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2362 sprstate = ps;
2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2364 curstate = ps;
2365 }
2366
2367 pipe_wm->pipe_enabled = cstate->base.active;
2368 if (sprstate) {
2369 pipe_wm->sprites_enabled = sprstate->base.visible;
2370 pipe_wm->sprites_scaled = sprstate->base.visible &&
2371 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2372 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2373 }
2374
2375 usable_level = max_level;
2376
2377 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2378 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2379 usable_level = 1;
2380
2381 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2382 if (pipe_wm->sprites_scaled)
2383 usable_level = 0;
2384
2385 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2386 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2390
2391 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2392 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2393
2394 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2395 return -EINVAL;
2396
2397 ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399 for (level = 1; level <= max_level; level++) {
2400 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2401
2402 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2403 pristate, sprstate, curstate, wm);
2404
2405 /*
2406 * Disable any watermark level that exceeds the
2407 * register maximums since such watermarks are
2408 * always invalid.
2409 */
2410 if (level > usable_level)
2411 continue;
2412
2413 if (ilk_validate_wm_level(level, &max, wm))
2414 pipe_wm->wm[level] = *wm;
2415 else
2416 usable_level = level;
2417 }
2418
2419 return 0;
2420 }
2421
2422 /*
2423 * Build a set of 'intermediate' watermark values that satisfy both the old
2424 * state and the new state. These can be programmed to the hardware
2425 * immediately.
2426 */
2427 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428 struct intel_crtc *intel_crtc,
2429 struct intel_crtc_state *newstate)
2430 {
2431 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2432 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433 int level, max_level = ilk_wm_max_level(dev);
2434
2435 /*
2436 * Start with the final, target watermarks, then combine with the
2437 * currently active watermarks to get values that are safe both before
2438 * and after the vblank.
2439 */
2440 *a = newstate->wm.ilk.optimal;
2441 a->pipe_enabled |= b->pipe_enabled;
2442 a->sprites_enabled |= b->sprites_enabled;
2443 a->sprites_scaled |= b->sprites_scaled;
2444
2445 for (level = 0; level <= max_level; level++) {
2446 struct intel_wm_level *a_wm = &a->wm[level];
2447 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449 a_wm->enable &= b_wm->enable;
2450 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454 }
2455
2456 /*
2457 * We need to make sure that these merged watermark values are
2458 * actually a valid configuration themselves. If they're not,
2459 * there's no safe way to transition from the old state to
2460 * the new state, so we need to fail the atomic transaction.
2461 */
2462 if (!ilk_validate_pipe_wm(dev, a))
2463 return -EINVAL;
2464
2465 /*
2466 * If our intermediate WM are identical to the final WM, then we can
2467 * omit the post-vblank programming; only update if it's different.
2468 */
2469 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2470 newstate->wm.need_postvbl_update = false;
2471
2472 return 0;
2473 }
2474
2475 /*
2476 * Merge the watermarks from all active pipes for a specific level.
2477 */
2478 static void ilk_merge_wm_level(struct drm_device *dev,
2479 int level,
2480 struct intel_wm_level *ret_wm)
2481 {
2482 const struct intel_crtc *intel_crtc;
2483
2484 ret_wm->enable = true;
2485
2486 for_each_intel_crtc(dev, intel_crtc) {
2487 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2488 const struct intel_wm_level *wm = &active->wm[level];
2489
2490 if (!active->pipe_enabled)
2491 continue;
2492
2493 /*
2494 * The watermark values may have been used in the past,
2495 * so we must maintain them in the registers for some
2496 * time even if the level is now disabled.
2497 */
2498 if (!wm->enable)
2499 ret_wm->enable = false;
2500
2501 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505 }
2506 }
2507
2508 /*
2509 * Merge all low power watermarks for all active pipes.
2510 */
2511 static void ilk_wm_merge(struct drm_device *dev,
2512 const struct intel_wm_config *config,
2513 const struct ilk_wm_maximums *max,
2514 struct intel_pipe_wm *merged)
2515 {
2516 struct drm_i915_private *dev_priv = to_i915(dev);
2517 int level, max_level = ilk_wm_max_level(dev);
2518 int last_enabled_level = max_level;
2519
2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522 config->num_pipes_active > 1)
2523 last_enabled_level = 0;
2524
2525 /* ILK: FBC WM must be disabled always */
2526 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2527
2528 /* merge each WM1+ level */
2529 for (level = 1; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 ilk_merge_wm_level(dev, level, wm);
2533
2534 if (level > last_enabled_level)
2535 wm->enable = false;
2536 else if (!ilk_validate_wm_level(level, max, wm))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level = level - 1;
2539
2540 /*
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2543 */
2544 if (wm->fbc_val > max->fbc) {
2545 if (wm->enable)
2546 merged->fbc_wm_enabled = false;
2547 wm->fbc_val = 0;
2548 }
2549 }
2550
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552 /*
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2556 */
2557 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2558 intel_fbc_is_active(dev_priv)) {
2559 for (level = 2; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 wm->enable = false;
2563 }
2564 }
2565 }
2566
2567 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568 {
2569 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571 }
2572
2573 /* The value we need to program into the WM_LPx latency field */
2574 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575 {
2576 struct drm_i915_private *dev_priv = to_i915(dev);
2577
2578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2579 return 2 * level;
2580 else
2581 return dev_priv->wm.pri_latency[level];
2582 }
2583
2584 static void ilk_compute_wm_results(struct drm_device *dev,
2585 const struct intel_pipe_wm *merged,
2586 enum intel_ddb_partitioning partitioning,
2587 struct ilk_wm_values *results)
2588 {
2589 struct intel_crtc *intel_crtc;
2590 int level, wm_lp;
2591
2592 results->enable_fbc_wm = merged->fbc_wm_enabled;
2593 results->partitioning = partitioning;
2594
2595 /* LP1+ register values */
2596 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2597 const struct intel_wm_level *r;
2598
2599 level = ilk_wm_lp_to_level(wm_lp, merged);
2600
2601 r = &merged->wm[level];
2602
2603 /*
2604 * Maintain the watermark values even if the level is
2605 * disabled. Doing otherwise could cause underruns.
2606 */
2607 results->wm_lp[wm_lp - 1] =
2608 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2609 (r->pri_val << WM1_LP_SR_SHIFT) |
2610 r->cur_val;
2611
2612 if (r->enable)
2613 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
2615 if (INTEL_INFO(dev)->gen >= 8)
2616 results->wm_lp[wm_lp - 1] |=
2617 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618 else
2619 results->wm_lp[wm_lp - 1] |=
2620 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
2622 /*
2623 * Always set WM1S_LP_EN when spr_val != 0, even if the
2624 * level is disabled. Doing otherwise could cause underruns.
2625 */
2626 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627 WARN_ON(wm_lp != 1);
2628 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629 } else
2630 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2631 }
2632
2633 /* LP0 register values */
2634 for_each_intel_crtc(dev, intel_crtc) {
2635 enum pipe pipe = intel_crtc->pipe;
2636 const struct intel_wm_level *r =
2637 &intel_crtc->wm.active.ilk.wm[0];
2638
2639 if (WARN_ON(!r->enable))
2640 continue;
2641
2642 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2643
2644 results->wm_pipe[pipe] =
2645 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647 r->cur_val;
2648 }
2649 }
2650
2651 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652 * case both are at the same level. Prefer r1 in case they're the same. */
2653 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2654 struct intel_pipe_wm *r1,
2655 struct intel_pipe_wm *r2)
2656 {
2657 int level, max_level = ilk_wm_max_level(dev);
2658 int level1 = 0, level2 = 0;
2659
2660 for (level = 1; level <= max_level; level++) {
2661 if (r1->wm[level].enable)
2662 level1 = level;
2663 if (r2->wm[level].enable)
2664 level2 = level;
2665 }
2666
2667 if (level1 == level2) {
2668 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2669 return r2;
2670 else
2671 return r1;
2672 } else if (level1 > level2) {
2673 return r1;
2674 } else {
2675 return r2;
2676 }
2677 }
2678
2679 /* dirty bits used to track which watermarks need changes */
2680 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684 #define WM_DIRTY_FBC (1 << 24)
2685 #define WM_DIRTY_DDB (1 << 25)
2686
2687 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2688 const struct ilk_wm_values *old,
2689 const struct ilk_wm_values *new)
2690 {
2691 unsigned int dirty = 0;
2692 enum pipe pipe;
2693 int wm_lp;
2694
2695 for_each_pipe(dev_priv, pipe) {
2696 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697 dirty |= WM_DIRTY_LINETIME(pipe);
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2700 }
2701
2702 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703 dirty |= WM_DIRTY_PIPE(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707 }
2708
2709 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710 dirty |= WM_DIRTY_FBC;
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714
2715 if (old->partitioning != new->partitioning) {
2716 dirty |= WM_DIRTY_DDB;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 /* LP1+ watermarks already deemed dirty, no need to continue */
2722 if (dirty & WM_DIRTY_LP_ALL)
2723 return dirty;
2724
2725 /* Find the lowest numbered LP1+ watermark in need of an update... */
2726 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729 break;
2730 }
2731
2732 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733 for (; wm_lp <= 3; wm_lp++)
2734 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736 return dirty;
2737 }
2738
2739 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740 unsigned int dirty)
2741 {
2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2743 bool changed = false;
2744
2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2748 changed = true;
2749 }
2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2753 changed = true;
2754 }
2755 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2758 changed = true;
2759 }
2760
2761 /*
2762 * Don't touch WM1S_LP_EN here.
2763 * Doing so could cause underruns.
2764 */
2765
2766 return changed;
2767 }
2768
2769 /*
2770 * The spec says we shouldn't write when we don't need, because every write
2771 * causes WMs to be re-evaluated, expending some power.
2772 */
2773 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774 struct ilk_wm_values *results)
2775 {
2776 struct drm_device *dev = &dev_priv->drm;
2777 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2778 unsigned int dirty;
2779 uint32_t val;
2780
2781 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2782 if (!dirty)
2783 return;
2784
2785 _ilk_disable_lp_wm(dev_priv, dirty);
2786
2787 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2788 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2789 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2790 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2791 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2792 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
2794 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2795 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2796 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2798 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
2801 if (dirty & WM_DIRTY_DDB) {
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2803 val = I915_READ(WM_MISC);
2804 if (results->partitioning == INTEL_DDB_PART_1_2)
2805 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806 else
2807 val |= WM_MISC_DATA_PARTITION_5_6;
2808 I915_WRITE(WM_MISC, val);
2809 } else {
2810 val = I915_READ(DISP_ARB_CTL2);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~DISP_DATA_PARTITION_5_6;
2813 else
2814 val |= DISP_DATA_PARTITION_5_6;
2815 I915_WRITE(DISP_ARB_CTL2, val);
2816 }
2817 }
2818
2819 if (dirty & WM_DIRTY_FBC) {
2820 val = I915_READ(DISP_ARB_CTL);
2821 if (results->enable_fbc_wm)
2822 val &= ~DISP_FBC_WM_DIS;
2823 else
2824 val |= DISP_FBC_WM_DIS;
2825 I915_WRITE(DISP_ARB_CTL, val);
2826 }
2827
2828 if (dirty & WM_DIRTY_LP(1) &&
2829 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832 if (INTEL_INFO(dev)->gen >= 7) {
2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837 }
2838
2839 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2840 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2841 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2842 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2843 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2844 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2845
2846 dev_priv->wm.hw = *results;
2847 }
2848
2849 bool ilk_disable_lp_wm(struct drm_device *dev)
2850 {
2851 struct drm_i915_private *dev_priv = to_i915(dev);
2852
2853 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854 }
2855
2856 /*
2857 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2858 * different active planes.
2859 */
2860
2861 #define SKL_DDB_SIZE 896 /* in blocks */
2862 #define BXT_DDB_SIZE 512
2863 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2864
2865 /*
2866 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2867 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868 * other universal planes are in indices 1..n. Note that this may leave unused
2869 * indices between the top "sprite" plane and the cursor.
2870 */
2871 static int
2872 skl_wm_plane_id(const struct intel_plane *plane)
2873 {
2874 switch (plane->base.type) {
2875 case DRM_PLANE_TYPE_PRIMARY:
2876 return 0;
2877 case DRM_PLANE_TYPE_CURSOR:
2878 return PLANE_CURSOR;
2879 case DRM_PLANE_TYPE_OVERLAY:
2880 return plane->plane + 1;
2881 default:
2882 MISSING_CASE(plane->base.type);
2883 return plane->plane;
2884 }
2885 }
2886
2887 /*
2888 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2889 * depending on power and performance requirements. The display engine access
2890 * to system memory is blocked during the adjustment time. Because of the
2891 * blocking time, having this enabled can cause full system hangs and/or pipe
2892 * underruns if we don't meet all of the following requirements:
2893 *
2894 * - <= 1 pipe enabled
2895 * - All planes can enable watermarks for latencies >= SAGV engine block time
2896 * - We're not using an interlaced display configuration
2897 */
2898 int
2899 skl_enable_sagv(struct drm_i915_private *dev_priv)
2900 {
2901 int ret;
2902
2903 if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2904 dev_priv->skl_sagv_status == I915_SKL_SAGV_ENABLED)
2905 return 0;
2906
2907 DRM_DEBUG_KMS("Enabling the SAGV\n");
2908 mutex_lock(&dev_priv->rps.hw_lock);
2909
2910 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2911 GEN9_SAGV_ENABLE);
2912
2913 /* We don't need to wait for the SAGV when enabling */
2914 mutex_unlock(&dev_priv->rps.hw_lock);
2915
2916 /*
2917 * Some skl systems, pre-release machines in particular,
2918 * don't actually have an SAGV.
2919 */
2920 if (ret == -ENXIO) {
2921 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2922 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2923 return 0;
2924 } else if (ret < 0) {
2925 DRM_ERROR("Failed to enable the SAGV\n");
2926 return ret;
2927 }
2928
2929 dev_priv->skl_sagv_status = I915_SKL_SAGV_ENABLED;
2930 return 0;
2931 }
2932
2933 static int
2934 skl_do_sagv_disable(struct drm_i915_private *dev_priv)
2935 {
2936 int ret;
2937 uint32_t temp = GEN9_SAGV_DISABLE;
2938
2939 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2940 &temp);
2941 if (ret)
2942 return ret;
2943 else
2944 return temp & GEN9_SAGV_IS_DISABLED;
2945 }
2946
2947 int
2948 skl_disable_sagv(struct drm_i915_private *dev_priv)
2949 {
2950 int ret, result;
2951
2952 if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2953 dev_priv->skl_sagv_status == I915_SKL_SAGV_DISABLED)
2954 return 0;
2955
2956 DRM_DEBUG_KMS("Disabling the SAGV\n");
2957 mutex_lock(&dev_priv->rps.hw_lock);
2958
2959 /* bspec says to keep retrying for at least 1 ms */
2960 ret = wait_for(result = skl_do_sagv_disable(dev_priv), 1);
2961 mutex_unlock(&dev_priv->rps.hw_lock);
2962
2963 if (ret == -ETIMEDOUT) {
2964 DRM_ERROR("Request to disable SAGV timed out\n");
2965 return -ETIMEDOUT;
2966 }
2967
2968 /*
2969 * Some skl systems, pre-release machines in particular,
2970 * don't actually have an SAGV.
2971 */
2972 if (result == -ENXIO) {
2973 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2974 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2975 return 0;
2976 } else if (result < 0) {
2977 DRM_ERROR("Failed to disable the SAGV\n");
2978 return result;
2979 }
2980
2981 dev_priv->skl_sagv_status = I915_SKL_SAGV_DISABLED;
2982 return 0;
2983 }
2984
2985 bool skl_can_enable_sagv(struct drm_atomic_state *state)
2986 {
2987 struct drm_device *dev = state->dev;
2988 struct drm_i915_private *dev_priv = to_i915(dev);
2989 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2990 struct drm_crtc *crtc;
2991 enum pipe pipe;
2992 int level, plane;
2993
2994 /*
2995 * SKL workaround: bspec recommends we disable the SAGV when we have
2996 * more then one pipe enabled
2997 *
2998 * If there are no active CRTCs, no additional checks need be performed
2999 */
3000 if (hweight32(intel_state->active_crtcs) == 0)
3001 return true;
3002 else if (hweight32(intel_state->active_crtcs) > 1)
3003 return false;
3004
3005 /* Since we're now guaranteed to only have one active CRTC... */
3006 pipe = ffs(intel_state->active_crtcs) - 1;
3007 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3008
3009 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3010 return false;
3011
3012 for_each_plane(dev_priv, pipe, plane) {
3013 /* Skip this plane if it's not enabled */
3014 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3015 continue;
3016
3017 /* Find the highest enabled wm level for this plane */
3018 for (level = ilk_wm_max_level(dev);
3019 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3020 { }
3021
3022 /*
3023 * If any of the planes on this pipe don't enable wm levels
3024 * that incur memory latencies higher then 30µs we can't enable
3025 * the SAGV
3026 */
3027 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3028 return false;
3029 }
3030
3031 return true;
3032 }
3033
3034 static void
3035 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3036 const struct intel_crtc_state *cstate,
3037 struct skl_ddb_entry *alloc, /* out */
3038 int *num_active /* out */)
3039 {
3040 struct drm_atomic_state *state = cstate->base.state;
3041 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3042 struct drm_i915_private *dev_priv = to_i915(dev);
3043 struct drm_crtc *for_crtc = cstate->base.crtc;
3044 unsigned int pipe_size, ddb_size;
3045 int nth_active_pipe;
3046 int pipe = to_intel_crtc(for_crtc)->pipe;
3047
3048 if (WARN_ON(!state) || !cstate->base.active) {
3049 alloc->start = 0;
3050 alloc->end = 0;
3051 *num_active = hweight32(dev_priv->active_crtcs);
3052 return;
3053 }
3054
3055 if (intel_state->active_pipe_changes)
3056 *num_active = hweight32(intel_state->active_crtcs);
3057 else
3058 *num_active = hweight32(dev_priv->active_crtcs);
3059
3060 if (IS_BROXTON(dev))
3061 ddb_size = BXT_DDB_SIZE;
3062 else
3063 ddb_size = SKL_DDB_SIZE;
3064
3065 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3066
3067 /*
3068 * If the state doesn't change the active CRTC's, then there's
3069 * no need to recalculate; the existing pipe allocation limits
3070 * should remain unchanged. Note that we're safe from racing
3071 * commits since any racing commit that changes the active CRTC
3072 * list would need to grab _all_ crtc locks, including the one
3073 * we currently hold.
3074 */
3075 if (!intel_state->active_pipe_changes) {
3076 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3077 return;
3078 }
3079
3080 nth_active_pipe = hweight32(intel_state->active_crtcs &
3081 (drm_crtc_mask(for_crtc) - 1));
3082 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3083 alloc->start = nth_active_pipe * ddb_size / *num_active;
3084 alloc->end = alloc->start + pipe_size;
3085 }
3086
3087 static unsigned int skl_cursor_allocation(int num_active)
3088 {
3089 if (num_active == 1)
3090 return 32;
3091
3092 return 8;
3093 }
3094
3095 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3096 {
3097 entry->start = reg & 0x3ff;
3098 entry->end = (reg >> 16) & 0x3ff;
3099 if (entry->end)
3100 entry->end += 1;
3101 }
3102
3103 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3104 struct skl_ddb_allocation *ddb /* out */)
3105 {
3106 enum pipe pipe;
3107 int plane;
3108 u32 val;
3109
3110 memset(ddb, 0, sizeof(*ddb));
3111
3112 for_each_pipe(dev_priv, pipe) {
3113 enum intel_display_power_domain power_domain;
3114
3115 power_domain = POWER_DOMAIN_PIPE(pipe);
3116 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3117 continue;
3118
3119 for_each_plane(dev_priv, pipe, plane) {
3120 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3121 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3122 val);
3123 }
3124
3125 val = I915_READ(CUR_BUF_CFG(pipe));
3126 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3127 val);
3128
3129 intel_display_power_put(dev_priv, power_domain);
3130 }
3131 }
3132
3133 /*
3134 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3135 * The bspec defines downscale amount as:
3136 *
3137 * """
3138 * Horizontal down scale amount = maximum[1, Horizontal source size /
3139 * Horizontal destination size]
3140 * Vertical down scale amount = maximum[1, Vertical source size /
3141 * Vertical destination size]
3142 * Total down scale amount = Horizontal down scale amount *
3143 * Vertical down scale amount
3144 * """
3145 *
3146 * Return value is provided in 16.16 fixed point form to retain fractional part.
3147 * Caller should take care of dividing & rounding off the value.
3148 */
3149 static uint32_t
3150 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3151 {
3152 uint32_t downscale_h, downscale_w;
3153 uint32_t src_w, src_h, dst_w, dst_h;
3154
3155 if (WARN_ON(!pstate->base.visible))
3156 return DRM_PLANE_HELPER_NO_SCALING;
3157
3158 /* n.b., src is 16.16 fixed point, dst is whole integer */
3159 src_w = drm_rect_width(&pstate->base.src);
3160 src_h = drm_rect_height(&pstate->base.src);
3161 dst_w = drm_rect_width(&pstate->base.dst);
3162 dst_h = drm_rect_height(&pstate->base.dst);
3163 if (intel_rotation_90_or_270(pstate->base.rotation))
3164 swap(dst_w, dst_h);
3165
3166 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3167 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3168
3169 /* Provide result in 16.16 fixed point */
3170 return (uint64_t)downscale_w * downscale_h >> 16;
3171 }
3172
3173 static unsigned int
3174 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3175 const struct drm_plane_state *pstate,
3176 int y)
3177 {
3178 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3179 struct drm_framebuffer *fb = pstate->fb;
3180 uint32_t down_scale_amount, data_rate;
3181 uint32_t width = 0, height = 0;
3182 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3183
3184 if (!intel_pstate->base.visible)
3185 return 0;
3186 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3187 return 0;
3188 if (y && format != DRM_FORMAT_NV12)
3189 return 0;
3190
3191 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3192 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3193
3194 if (intel_rotation_90_or_270(pstate->rotation))
3195 swap(width, height);
3196
3197 /* for planar format */
3198 if (format == DRM_FORMAT_NV12) {
3199 if (y) /* y-plane data rate */
3200 data_rate = width * height *
3201 drm_format_plane_cpp(format, 0);
3202 else /* uv-plane data rate */
3203 data_rate = (width / 2) * (height / 2) *
3204 drm_format_plane_cpp(format, 1);
3205 } else {
3206 /* for packed formats */
3207 data_rate = width * height * drm_format_plane_cpp(format, 0);
3208 }
3209
3210 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3211
3212 return (uint64_t)data_rate * down_scale_amount >> 16;
3213 }
3214
3215 /*
3216 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3217 * a 8192x4096@32bpp framebuffer:
3218 * 3 * 4096 * 8192 * 4 < 2^32
3219 */
3220 static unsigned int
3221 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3222 {
3223 struct drm_crtc_state *cstate = &intel_cstate->base;
3224 struct drm_atomic_state *state = cstate->state;
3225 struct drm_crtc *crtc = cstate->crtc;
3226 struct drm_device *dev = crtc->dev;
3227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228 const struct drm_plane *plane;
3229 const struct intel_plane *intel_plane;
3230 struct drm_plane_state *pstate;
3231 unsigned int rate, total_data_rate = 0;
3232 int id;
3233 int i;
3234
3235 if (WARN_ON(!state))
3236 return 0;
3237
3238 /* Calculate and cache data rate for each plane */
3239 for_each_plane_in_state(state, plane, pstate, i) {
3240 id = skl_wm_plane_id(to_intel_plane(plane));
3241 intel_plane = to_intel_plane(plane);
3242
3243 if (intel_plane->pipe != intel_crtc->pipe)
3244 continue;
3245
3246 /* packed/uv */
3247 rate = skl_plane_relative_data_rate(intel_cstate,
3248 pstate, 0);
3249 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3250
3251 /* y-plane */
3252 rate = skl_plane_relative_data_rate(intel_cstate,
3253 pstate, 1);
3254 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3255 }
3256
3257 /* Calculate CRTC's total data rate from cached values */
3258 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3259 int id = skl_wm_plane_id(intel_plane);
3260
3261 /* packed/uv */
3262 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3263 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3264 }
3265
3266 return total_data_rate;
3267 }
3268
3269 static uint16_t
3270 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3271 const int y)
3272 {
3273 struct drm_framebuffer *fb = pstate->fb;
3274 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3275 uint32_t src_w, src_h;
3276 uint32_t min_scanlines = 8;
3277 uint8_t plane_bpp;
3278
3279 if (WARN_ON(!fb))
3280 return 0;
3281
3282 /* For packed formats, no y-plane, return 0 */
3283 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3284 return 0;
3285
3286 /* For Non Y-tile return 8-blocks */
3287 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3288 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3289 return 8;
3290
3291 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3292 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3293
3294 if (intel_rotation_90_or_270(pstate->rotation))
3295 swap(src_w, src_h);
3296
3297 /* Halve UV plane width and height for NV12 */
3298 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3299 src_w /= 2;
3300 src_h /= 2;
3301 }
3302
3303 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3304 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3305 else
3306 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3307
3308 if (intel_rotation_90_or_270(pstate->rotation)) {
3309 switch (plane_bpp) {
3310 case 1:
3311 min_scanlines = 32;
3312 break;
3313 case 2:
3314 min_scanlines = 16;
3315 break;
3316 case 4:
3317 min_scanlines = 8;
3318 break;
3319 case 8:
3320 min_scanlines = 4;
3321 break;
3322 default:
3323 WARN(1, "Unsupported pixel depth %u for rotation",
3324 plane_bpp);
3325 min_scanlines = 32;
3326 }
3327 }
3328
3329 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3330 }
3331
3332 static int
3333 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3334 struct skl_ddb_allocation *ddb /* out */)
3335 {
3336 struct drm_atomic_state *state = cstate->base.state;
3337 struct drm_crtc *crtc = cstate->base.crtc;
3338 struct drm_device *dev = crtc->dev;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 struct intel_plane *intel_plane;
3341 struct drm_plane *plane;
3342 struct drm_plane_state *pstate;
3343 enum pipe pipe = intel_crtc->pipe;
3344 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3345 uint16_t alloc_size, start, cursor_blocks;
3346 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3347 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3348 unsigned int total_data_rate;
3349 int num_active;
3350 int id, i;
3351
3352 if (WARN_ON(!state))
3353 return 0;
3354
3355 if (!cstate->base.active) {
3356 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3357 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3358 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3359 return 0;
3360 }
3361
3362 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3363 alloc_size = skl_ddb_entry_size(alloc);
3364 if (alloc_size == 0) {
3365 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3366 return 0;
3367 }
3368
3369 cursor_blocks = skl_cursor_allocation(num_active);
3370 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3371 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3372
3373 alloc_size -= cursor_blocks;
3374
3375 /* 1. Allocate the mininum required blocks for each active plane */
3376 for_each_plane_in_state(state, plane, pstate, i) {
3377 intel_plane = to_intel_plane(plane);
3378 id = skl_wm_plane_id(intel_plane);
3379
3380 if (intel_plane->pipe != pipe)
3381 continue;
3382
3383 if (!to_intel_plane_state(pstate)->base.visible) {
3384 minimum[id] = 0;
3385 y_minimum[id] = 0;
3386 continue;
3387 }
3388 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3389 minimum[id] = 0;
3390 y_minimum[id] = 0;
3391 continue;
3392 }
3393
3394 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3395 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3396 }
3397
3398 for (i = 0; i < PLANE_CURSOR; i++) {
3399 alloc_size -= minimum[i];
3400 alloc_size -= y_minimum[i];
3401 }
3402
3403 /*
3404 * 2. Distribute the remaining space in proportion to the amount of
3405 * data each plane needs to fetch from memory.
3406 *
3407 * FIXME: we may not allocate every single block here.
3408 */
3409 total_data_rate = skl_get_total_relative_data_rate(cstate);
3410 if (total_data_rate == 0)
3411 return 0;
3412
3413 start = alloc->start;
3414 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3415 unsigned int data_rate, y_data_rate;
3416 uint16_t plane_blocks, y_plane_blocks = 0;
3417 int id = skl_wm_plane_id(intel_plane);
3418
3419 data_rate = cstate->wm.skl.plane_data_rate[id];
3420
3421 /*
3422 * allocation for (packed formats) or (uv-plane part of planar format):
3423 * promote the expression to 64 bits to avoid overflowing, the
3424 * result is < available as data_rate / total_data_rate < 1
3425 */
3426 plane_blocks = minimum[id];
3427 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3428 total_data_rate);
3429
3430 /* Leave disabled planes at (0,0) */
3431 if (data_rate) {
3432 ddb->plane[pipe][id].start = start;
3433 ddb->plane[pipe][id].end = start + plane_blocks;
3434 }
3435
3436 start += plane_blocks;
3437
3438 /*
3439 * allocation for y_plane part of planar format:
3440 */
3441 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3442
3443 y_plane_blocks = y_minimum[id];
3444 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3445 total_data_rate);
3446
3447 if (y_data_rate) {
3448 ddb->y_plane[pipe][id].start = start;
3449 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3450 }
3451
3452 start += y_plane_blocks;
3453 }
3454
3455 return 0;
3456 }
3457
3458 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3459 {
3460 /* TODO: Take into account the scalers once we support them */
3461 return config->base.adjusted_mode.crtc_clock;
3462 }
3463
3464 /*
3465 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3466 * for the read latency) and cpp should always be <= 8, so that
3467 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3468 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3469 */
3470 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3471 {
3472 uint32_t wm_intermediate_val, ret;
3473
3474 if (latency == 0)
3475 return UINT_MAX;
3476
3477 wm_intermediate_val = latency * pixel_rate * cpp / 512;
3478 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3479
3480 return ret;
3481 }
3482
3483 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3484 uint32_t horiz_pixels, uint8_t cpp,
3485 uint64_t tiling, uint32_t latency)
3486 {
3487 uint32_t ret;
3488 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3489 uint32_t wm_intermediate_val;
3490
3491 if (latency == 0)
3492 return UINT_MAX;
3493
3494 plane_bytes_per_line = horiz_pixels * cpp;
3495
3496 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3497 tiling == I915_FORMAT_MOD_Yf_TILED) {
3498 plane_bytes_per_line *= 4;
3499 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3500 plane_blocks_per_line /= 4;
3501 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3502 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3503 } else {
3504 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3505 }
3506
3507 wm_intermediate_val = latency * pixel_rate;
3508 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3509 plane_blocks_per_line;
3510
3511 return ret;
3512 }
3513
3514 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3515 struct intel_plane_state *pstate)
3516 {
3517 uint64_t adjusted_pixel_rate;
3518 uint64_t downscale_amount;
3519 uint64_t pixel_rate;
3520
3521 /* Shouldn't reach here on disabled planes... */
3522 if (WARN_ON(!pstate->base.visible))
3523 return 0;
3524
3525 /*
3526 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3527 * with additional adjustments for plane-specific scaling.
3528 */
3529 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3530 downscale_amount = skl_plane_downscale_amount(pstate);
3531
3532 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3533 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3534
3535 return pixel_rate;
3536 }
3537
3538 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3539 struct intel_crtc_state *cstate,
3540 struct intel_plane_state *intel_pstate,
3541 uint16_t ddb_allocation,
3542 int level,
3543 uint16_t *out_blocks, /* out */
3544 uint8_t *out_lines, /* out */
3545 bool *enabled /* out */)
3546 {
3547 struct drm_plane_state *pstate = &intel_pstate->base;
3548 struct drm_framebuffer *fb = pstate->fb;
3549 uint32_t latency = dev_priv->wm.skl_latency[level];
3550 uint32_t method1, method2;
3551 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3552 uint32_t res_blocks, res_lines;
3553 uint32_t selected_result;
3554 uint8_t cpp;
3555 uint32_t width = 0, height = 0;
3556 uint32_t plane_pixel_rate;
3557
3558 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3559 *enabled = false;
3560 return 0;
3561 }
3562
3563 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3564 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3565
3566 if (intel_rotation_90_or_270(pstate->rotation))
3567 swap(width, height);
3568
3569 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3570 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3571
3572 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3573 method2 = skl_wm_method2(plane_pixel_rate,
3574 cstate->base.adjusted_mode.crtc_htotal,
3575 width,
3576 cpp,
3577 fb->modifier[0],
3578 latency);
3579
3580 plane_bytes_per_line = width * cpp;
3581 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3582
3583 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3584 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3585 uint32_t min_scanlines = 4;
3586 uint32_t y_tile_minimum;
3587 if (intel_rotation_90_or_270(pstate->rotation)) {
3588 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3589 drm_format_plane_cpp(fb->pixel_format, 1) :
3590 drm_format_plane_cpp(fb->pixel_format, 0);
3591
3592 switch (cpp) {
3593 case 1:
3594 min_scanlines = 16;
3595 break;
3596 case 2:
3597 min_scanlines = 8;
3598 break;
3599 case 8:
3600 WARN(1, "Unsupported pixel depth for rotation");
3601 }
3602 }
3603 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3604 selected_result = max(method2, y_tile_minimum);
3605 } else {
3606 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3607 selected_result = min(method1, method2);
3608 else
3609 selected_result = method1;
3610 }
3611
3612 res_blocks = selected_result + 1;
3613 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3614
3615 if (level >= 1 && level <= 7) {
3616 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3617 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3618 res_lines += 4;
3619 else
3620 res_blocks++;
3621 }
3622
3623 if (res_blocks >= ddb_allocation || res_lines > 31) {
3624 *enabled = false;
3625
3626 /*
3627 * If there are no valid level 0 watermarks, then we can't
3628 * support this display configuration.
3629 */
3630 if (level) {
3631 return 0;
3632 } else {
3633 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3634 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3635 to_intel_crtc(cstate->base.crtc)->pipe,
3636 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3637 res_blocks, ddb_allocation, res_lines);
3638
3639 return -EINVAL;
3640 }
3641 }
3642
3643 *out_blocks = res_blocks;
3644 *out_lines = res_lines;
3645 *enabled = true;
3646
3647 return 0;
3648 }
3649
3650 static int
3651 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3652 struct skl_ddb_allocation *ddb,
3653 struct intel_crtc_state *cstate,
3654 int level,
3655 struct skl_wm_level *result)
3656 {
3657 struct drm_atomic_state *state = cstate->base.state;
3658 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3659 struct drm_plane *plane;
3660 struct intel_plane *intel_plane;
3661 struct intel_plane_state *intel_pstate;
3662 uint16_t ddb_blocks;
3663 enum pipe pipe = intel_crtc->pipe;
3664 int ret;
3665
3666 /*
3667 * We'll only calculate watermarks for planes that are actually
3668 * enabled, so make sure all other planes are set as disabled.
3669 */
3670 memset(result, 0, sizeof(*result));
3671
3672 for_each_intel_plane_mask(&dev_priv->drm,
3673 intel_plane,
3674 cstate->base.plane_mask) {
3675 int i = skl_wm_plane_id(intel_plane);
3676
3677 plane = &intel_plane->base;
3678 intel_pstate = NULL;
3679 if (state)
3680 intel_pstate =
3681 intel_atomic_get_existing_plane_state(state,
3682 intel_plane);
3683
3684 /*
3685 * Note: If we start supporting multiple pending atomic commits
3686 * against the same planes/CRTC's in the future, plane->state
3687 * will no longer be the correct pre-state to use for the
3688 * calculations here and we'll need to change where we get the
3689 * 'unchanged' plane data from.
3690 *
3691 * For now this is fine because we only allow one queued commit
3692 * against a CRTC. Even if the plane isn't modified by this
3693 * transaction and we don't have a plane lock, we still have
3694 * the CRTC's lock, so we know that no other transactions are
3695 * racing with us to update it.
3696 */
3697 if (!intel_pstate)
3698 intel_pstate = to_intel_plane_state(plane->state);
3699
3700 WARN_ON(!intel_pstate->base.fb);
3701
3702 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3703
3704 ret = skl_compute_plane_wm(dev_priv,
3705 cstate,
3706 intel_pstate,
3707 ddb_blocks,
3708 level,
3709 &result->plane_res_b[i],
3710 &result->plane_res_l[i],
3711 &result->plane_en[i]);
3712 if (ret)
3713 return ret;
3714 }
3715
3716 return 0;
3717 }
3718
3719 static uint32_t
3720 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3721 {
3722 if (!cstate->base.active)
3723 return 0;
3724
3725 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3726 return 0;
3727
3728 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3729 skl_pipe_pixel_rate(cstate));
3730 }
3731
3732 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3733 struct skl_wm_level *trans_wm /* out */)
3734 {
3735 struct drm_crtc *crtc = cstate->base.crtc;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 struct intel_plane *intel_plane;
3738
3739 if (!cstate->base.active)
3740 return;
3741
3742 /* Until we know more, just disable transition WMs */
3743 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3744 int i = skl_wm_plane_id(intel_plane);
3745
3746 trans_wm->plane_en[i] = false;
3747 }
3748 }
3749
3750 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3751 struct skl_ddb_allocation *ddb,
3752 struct skl_pipe_wm *pipe_wm)
3753 {
3754 struct drm_device *dev = cstate->base.crtc->dev;
3755 const struct drm_i915_private *dev_priv = to_i915(dev);
3756 int level, max_level = ilk_wm_max_level(dev);
3757 int ret;
3758
3759 for (level = 0; level <= max_level; level++) {
3760 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3761 level, &pipe_wm->wm[level]);
3762 if (ret)
3763 return ret;
3764 }
3765 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3766
3767 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3768
3769 return 0;
3770 }
3771
3772 static void skl_compute_wm_results(struct drm_device *dev,
3773 struct skl_pipe_wm *p_wm,
3774 struct skl_wm_values *r,
3775 struct intel_crtc *intel_crtc)
3776 {
3777 int level, max_level = ilk_wm_max_level(dev);
3778 enum pipe pipe = intel_crtc->pipe;
3779 uint32_t temp;
3780 int i;
3781
3782 for (level = 0; level <= max_level; level++) {
3783 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3784 temp = 0;
3785
3786 temp |= p_wm->wm[level].plane_res_l[i] <<
3787 PLANE_WM_LINES_SHIFT;
3788 temp |= p_wm->wm[level].plane_res_b[i];
3789 if (p_wm->wm[level].plane_en[i])
3790 temp |= PLANE_WM_EN;
3791
3792 r->plane[pipe][i][level] = temp;
3793 }
3794
3795 temp = 0;
3796
3797 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3798 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3799
3800 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3801 temp |= PLANE_WM_EN;
3802
3803 r->plane[pipe][PLANE_CURSOR][level] = temp;
3804
3805 }
3806
3807 /* transition WMs */
3808 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3809 temp = 0;
3810 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3811 temp |= p_wm->trans_wm.plane_res_b[i];
3812 if (p_wm->trans_wm.plane_en[i])
3813 temp |= PLANE_WM_EN;
3814
3815 r->plane_trans[pipe][i] = temp;
3816 }
3817
3818 temp = 0;
3819 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3820 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3821 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3822 temp |= PLANE_WM_EN;
3823
3824 r->plane_trans[pipe][PLANE_CURSOR] = temp;
3825
3826 r->wm_linetime[pipe] = p_wm->linetime;
3827 }
3828
3829 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3830 i915_reg_t reg,
3831 const struct skl_ddb_entry *entry)
3832 {
3833 if (entry->end)
3834 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3835 else
3836 I915_WRITE(reg, 0);
3837 }
3838
3839 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3840 const struct skl_wm_values *wm,
3841 int plane)
3842 {
3843 struct drm_crtc *crtc = &intel_crtc->base;
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = to_i915(dev);
3846 int level, max_level = ilk_wm_max_level(dev);
3847 enum pipe pipe = intel_crtc->pipe;
3848
3849 for (level = 0; level <= max_level; level++) {
3850 I915_WRITE(PLANE_WM(pipe, plane, level),
3851 wm->plane[pipe][plane][level]);
3852 }
3853 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3854
3855 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3856 &wm->ddb.plane[pipe][plane]);
3857 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3858 &wm->ddb.y_plane[pipe][plane]);
3859 }
3860
3861 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3862 const struct skl_wm_values *wm)
3863 {
3864 struct drm_crtc *crtc = &intel_crtc->base;
3865 struct drm_device *dev = crtc->dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
3867 int level, max_level = ilk_wm_max_level(dev);
3868 enum pipe pipe = intel_crtc->pipe;
3869
3870 for (level = 0; level <= max_level; level++) {
3871 I915_WRITE(CUR_WM(pipe, level),
3872 wm->plane[pipe][PLANE_CURSOR][level]);
3873 }
3874 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3875
3876 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3877 &wm->ddb.plane[pipe][PLANE_CURSOR]);
3878 }
3879
3880 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3881 const struct skl_ddb_allocation *new,
3882 enum pipe pipe)
3883 {
3884 return new->pipe[pipe].start == old->pipe[pipe].start &&
3885 new->pipe[pipe].end == old->pipe[pipe].end;
3886 }
3887
3888 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3889 const struct skl_ddb_entry *b)
3890 {
3891 return a->start < b->end && b->start < a->end;
3892 }
3893
3894 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3895 const struct skl_ddb_allocation *old,
3896 const struct skl_ddb_allocation *new,
3897 enum pipe pipe)
3898 {
3899 struct drm_device *dev = state->dev;
3900 struct intel_crtc *intel_crtc;
3901 enum pipe otherp;
3902
3903 for_each_intel_crtc(dev, intel_crtc) {
3904 otherp = intel_crtc->pipe;
3905
3906 if (otherp == pipe)
3907 continue;
3908
3909 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3910 &old->pipe[otherp]))
3911 return true;
3912 }
3913
3914 return false;
3915 }
3916
3917 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3918 struct skl_ddb_allocation *ddb, /* out */
3919 struct skl_pipe_wm *pipe_wm, /* out */
3920 bool *changed /* out */)
3921 {
3922 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3923 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3924 int ret;
3925
3926 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3927 if (ret)
3928 return ret;
3929
3930 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3931 *changed = false;
3932 else
3933 *changed = true;
3934
3935 return 0;
3936 }
3937
3938 static uint32_t
3939 pipes_modified(struct drm_atomic_state *state)
3940 {
3941 struct drm_crtc *crtc;
3942 struct drm_crtc_state *cstate;
3943 uint32_t i, ret = 0;
3944
3945 for_each_crtc_in_state(state, crtc, cstate, i)
3946 ret |= drm_crtc_mask(crtc);
3947
3948 return ret;
3949 }
3950
3951 static int
3952 skl_compute_ddb(struct drm_atomic_state *state)
3953 {
3954 struct drm_device *dev = state->dev;
3955 struct drm_i915_private *dev_priv = to_i915(dev);
3956 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3957 struct intel_crtc *intel_crtc;
3958 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3959 uint32_t realloc_pipes = pipes_modified(state);
3960 int ret;
3961
3962 /*
3963 * If this is our first atomic update following hardware readout,
3964 * we can't trust the DDB that the BIOS programmed for us. Let's
3965 * pretend that all pipes switched active status so that we'll
3966 * ensure a full DDB recompute.
3967 */
3968 if (dev_priv->wm.distrust_bios_wm) {
3969 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3970 state->acquire_ctx);
3971 if (ret)
3972 return ret;
3973
3974 intel_state->active_pipe_changes = ~0;
3975
3976 /*
3977 * We usually only initialize intel_state->active_crtcs if we
3978 * we're doing a modeset; make sure this field is always
3979 * initialized during the sanitization process that happens
3980 * on the first commit too.
3981 */
3982 if (!intel_state->modeset)
3983 intel_state->active_crtcs = dev_priv->active_crtcs;
3984 }
3985
3986 /*
3987 * If the modeset changes which CRTC's are active, we need to
3988 * recompute the DDB allocation for *all* active pipes, even
3989 * those that weren't otherwise being modified in any way by this
3990 * atomic commit. Due to the shrinking of the per-pipe allocations
3991 * when new active CRTC's are added, it's possible for a pipe that
3992 * we were already using and aren't changing at all here to suddenly
3993 * become invalid if its DDB needs exceeds its new allocation.
3994 *
3995 * Note that if we wind up doing a full DDB recompute, we can't let
3996 * any other display updates race with this transaction, so we need
3997 * to grab the lock on *all* CRTC's.
3998 */
3999 if (intel_state->active_pipe_changes) {
4000 realloc_pipes = ~0;
4001 intel_state->wm_results.dirty_pipes = ~0;
4002 }
4003
4004 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4005 struct intel_crtc_state *cstate;
4006
4007 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4008 if (IS_ERR(cstate))
4009 return PTR_ERR(cstate);
4010
4011 ret = skl_allocate_pipe_ddb(cstate, ddb);
4012 if (ret)
4013 return ret;
4014
4015 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4016 if (ret)
4017 return ret;
4018 }
4019
4020 return 0;
4021 }
4022
4023 static void
4024 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4025 struct skl_wm_values *src,
4026 enum pipe pipe)
4027 {
4028 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4029 memcpy(dst->plane[pipe], src->plane[pipe],
4030 sizeof(dst->plane[pipe]));
4031 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4032 sizeof(dst->plane_trans[pipe]));
4033
4034 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4035 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4036 sizeof(dst->ddb.y_plane[pipe]));
4037 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4038 sizeof(dst->ddb.plane[pipe]));
4039 }
4040
4041 static int
4042 skl_compute_wm(struct drm_atomic_state *state)
4043 {
4044 struct drm_crtc *crtc;
4045 struct drm_crtc_state *cstate;
4046 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4047 struct skl_wm_values *results = &intel_state->wm_results;
4048 struct skl_pipe_wm *pipe_wm;
4049 bool changed = false;
4050 int ret, i;
4051
4052 /*
4053 * If this transaction isn't actually touching any CRTC's, don't
4054 * bother with watermark calculation. Note that if we pass this
4055 * test, we're guaranteed to hold at least one CRTC state mutex,
4056 * which means we can safely use values like dev_priv->active_crtcs
4057 * since any racing commits that want to update them would need to
4058 * hold _all_ CRTC state mutexes.
4059 */
4060 for_each_crtc_in_state(state, crtc, cstate, i)
4061 changed = true;
4062 if (!changed)
4063 return 0;
4064
4065 /* Clear all dirty flags */
4066 results->dirty_pipes = 0;
4067
4068 ret = skl_compute_ddb(state);
4069 if (ret)
4070 return ret;
4071
4072 /*
4073 * Calculate WM's for all pipes that are part of this transaction.
4074 * Note that the DDB allocation above may have added more CRTC's that
4075 * weren't otherwise being modified (and set bits in dirty_pipes) if
4076 * pipe allocations had to change.
4077 *
4078 * FIXME: Now that we're doing this in the atomic check phase, we
4079 * should allow skl_update_pipe_wm() to return failure in cases where
4080 * no suitable watermark values can be found.
4081 */
4082 for_each_crtc_in_state(state, crtc, cstate, i) {
4083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4084 struct intel_crtc_state *intel_cstate =
4085 to_intel_crtc_state(cstate);
4086
4087 pipe_wm = &intel_cstate->wm.skl.optimal;
4088 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4089 &changed);
4090 if (ret)
4091 return ret;
4092
4093 if (changed)
4094 results->dirty_pipes |= drm_crtc_mask(crtc);
4095
4096 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4097 /* This pipe's WM's did not change */
4098 continue;
4099
4100 intel_cstate->update_wm_pre = true;
4101 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4102 }
4103
4104 return 0;
4105 }
4106
4107 static void skl_update_wm(struct drm_crtc *crtc)
4108 {
4109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4110 struct drm_device *dev = crtc->dev;
4111 struct drm_i915_private *dev_priv = to_i915(dev);
4112 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4113 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4114 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4115 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4116 enum pipe pipe = intel_crtc->pipe;
4117
4118 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4119 return;
4120
4121 intel_crtc->wm.active.skl = *pipe_wm;
4122
4123 mutex_lock(&dev_priv->wm.wm_mutex);
4124
4125 /*
4126 * If this pipe isn't active already, we're going to be enabling it
4127 * very soon. Since it's safe to update a pipe's ddb allocation while
4128 * the pipe's shut off, just do so here. Already active pipes will have
4129 * their watermarks updated once we update their planes.
4130 */
4131 if (crtc->state->active_changed) {
4132 int plane;
4133
4134 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4135 skl_write_plane_wm(intel_crtc, results, plane);
4136
4137 skl_write_cursor_wm(intel_crtc, results);
4138 }
4139
4140 skl_copy_wm_for_pipe(hw_vals, results, pipe);
4141
4142 mutex_unlock(&dev_priv->wm.wm_mutex);
4143 }
4144
4145 static void ilk_compute_wm_config(struct drm_device *dev,
4146 struct intel_wm_config *config)
4147 {
4148 struct intel_crtc *crtc;
4149
4150 /* Compute the currently _active_ config */
4151 for_each_intel_crtc(dev, crtc) {
4152 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4153
4154 if (!wm->pipe_enabled)
4155 continue;
4156
4157 config->sprites_enabled |= wm->sprites_enabled;
4158 config->sprites_scaled |= wm->sprites_scaled;
4159 config->num_pipes_active++;
4160 }
4161 }
4162
4163 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4164 {
4165 struct drm_device *dev = &dev_priv->drm;
4166 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4167 struct ilk_wm_maximums max;
4168 struct intel_wm_config config = {};
4169 struct ilk_wm_values results = {};
4170 enum intel_ddb_partitioning partitioning;
4171
4172 ilk_compute_wm_config(dev, &config);
4173
4174 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4175 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4176
4177 /* 5/6 split only in single pipe config on IVB+ */
4178 if (INTEL_INFO(dev)->gen >= 7 &&
4179 config.num_pipes_active == 1 && config.sprites_enabled) {
4180 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4181 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4182
4183 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4184 } else {
4185 best_lp_wm = &lp_wm_1_2;
4186 }
4187
4188 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4189 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4190
4191 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4192
4193 ilk_write_wm_values(dev_priv, &results);
4194 }
4195
4196 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4197 {
4198 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4199 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4200
4201 mutex_lock(&dev_priv->wm.wm_mutex);
4202 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4203 ilk_program_watermarks(dev_priv);
4204 mutex_unlock(&dev_priv->wm.wm_mutex);
4205 }
4206
4207 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4208 {
4209 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4210 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4211
4212 mutex_lock(&dev_priv->wm.wm_mutex);
4213 if (cstate->wm.need_postvbl_update) {
4214 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4215 ilk_program_watermarks(dev_priv);
4216 }
4217 mutex_unlock(&dev_priv->wm.wm_mutex);
4218 }
4219
4220 static void skl_pipe_wm_active_state(uint32_t val,
4221 struct skl_pipe_wm *active,
4222 bool is_transwm,
4223 bool is_cursor,
4224 int i,
4225 int level)
4226 {
4227 bool is_enabled = (val & PLANE_WM_EN) != 0;
4228
4229 if (!is_transwm) {
4230 if (!is_cursor) {
4231 active->wm[level].plane_en[i] = is_enabled;
4232 active->wm[level].plane_res_b[i] =
4233 val & PLANE_WM_BLOCKS_MASK;
4234 active->wm[level].plane_res_l[i] =
4235 (val >> PLANE_WM_LINES_SHIFT) &
4236 PLANE_WM_LINES_MASK;
4237 } else {
4238 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4239 active->wm[level].plane_res_b[PLANE_CURSOR] =
4240 val & PLANE_WM_BLOCKS_MASK;
4241 active->wm[level].plane_res_l[PLANE_CURSOR] =
4242 (val >> PLANE_WM_LINES_SHIFT) &
4243 PLANE_WM_LINES_MASK;
4244 }
4245 } else {
4246 if (!is_cursor) {
4247 active->trans_wm.plane_en[i] = is_enabled;
4248 active->trans_wm.plane_res_b[i] =
4249 val & PLANE_WM_BLOCKS_MASK;
4250 active->trans_wm.plane_res_l[i] =
4251 (val >> PLANE_WM_LINES_SHIFT) &
4252 PLANE_WM_LINES_MASK;
4253 } else {
4254 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4255 active->trans_wm.plane_res_b[PLANE_CURSOR] =
4256 val & PLANE_WM_BLOCKS_MASK;
4257 active->trans_wm.plane_res_l[PLANE_CURSOR] =
4258 (val >> PLANE_WM_LINES_SHIFT) &
4259 PLANE_WM_LINES_MASK;
4260 }
4261 }
4262 }
4263
4264 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4265 {
4266 struct drm_device *dev = crtc->dev;
4267 struct drm_i915_private *dev_priv = to_i915(dev);
4268 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4270 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4271 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4272 enum pipe pipe = intel_crtc->pipe;
4273 int level, i, max_level;
4274 uint32_t temp;
4275
4276 max_level = ilk_wm_max_level(dev);
4277
4278 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4279
4280 for (level = 0; level <= max_level; level++) {
4281 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4282 hw->plane[pipe][i][level] =
4283 I915_READ(PLANE_WM(pipe, i, level));
4284 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4285 }
4286
4287 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4288 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4289 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4290
4291 if (!intel_crtc->active)
4292 return;
4293
4294 hw->dirty_pipes |= drm_crtc_mask(crtc);
4295
4296 active->linetime = hw->wm_linetime[pipe];
4297
4298 for (level = 0; level <= max_level; level++) {
4299 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4300 temp = hw->plane[pipe][i][level];
4301 skl_pipe_wm_active_state(temp, active, false,
4302 false, i, level);
4303 }
4304 temp = hw->plane[pipe][PLANE_CURSOR][level];
4305 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4306 }
4307
4308 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4309 temp = hw->plane_trans[pipe][i];
4310 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4311 }
4312
4313 temp = hw->plane_trans[pipe][PLANE_CURSOR];
4314 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4315
4316 intel_crtc->wm.active.skl = *active;
4317 }
4318
4319 void skl_wm_get_hw_state(struct drm_device *dev)
4320 {
4321 struct drm_i915_private *dev_priv = to_i915(dev);
4322 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4323 struct drm_crtc *crtc;
4324
4325 skl_ddb_get_hw_state(dev_priv, ddb);
4326 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4327 skl_pipe_wm_get_hw_state(crtc);
4328
4329 if (dev_priv->active_crtcs) {
4330 /* Fully recompute DDB on first atomic commit */
4331 dev_priv->wm.distrust_bios_wm = true;
4332 } else {
4333 /* Easy/common case; just sanitize DDB now if everything off */
4334 memset(ddb, 0, sizeof(*ddb));
4335 }
4336 }
4337
4338 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4339 {
4340 struct drm_device *dev = crtc->dev;
4341 struct drm_i915_private *dev_priv = to_i915(dev);
4342 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4345 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4346 enum pipe pipe = intel_crtc->pipe;
4347 static const i915_reg_t wm0_pipe_reg[] = {
4348 [PIPE_A] = WM0_PIPEA_ILK,
4349 [PIPE_B] = WM0_PIPEB_ILK,
4350 [PIPE_C] = WM0_PIPEC_IVB,
4351 };
4352
4353 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4355 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4356
4357 memset(active, 0, sizeof(*active));
4358
4359 active->pipe_enabled = intel_crtc->active;
4360
4361 if (active->pipe_enabled) {
4362 u32 tmp = hw->wm_pipe[pipe];
4363
4364 /*
4365 * For active pipes LP0 watermark is marked as
4366 * enabled, and LP1+ watermaks as disabled since
4367 * we can't really reverse compute them in case
4368 * multiple pipes are active.
4369 */
4370 active->wm[0].enable = true;
4371 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4372 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4373 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4374 active->linetime = hw->wm_linetime[pipe];
4375 } else {
4376 int level, max_level = ilk_wm_max_level(dev);
4377
4378 /*
4379 * For inactive pipes, all watermark levels
4380 * should be marked as enabled but zeroed,
4381 * which is what we'd compute them to.
4382 */
4383 for (level = 0; level <= max_level; level++)
4384 active->wm[level].enable = true;
4385 }
4386
4387 intel_crtc->wm.active.ilk = *active;
4388 }
4389
4390 #define _FW_WM(value, plane) \
4391 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4392 #define _FW_WM_VLV(value, plane) \
4393 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4394
4395 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4396 struct vlv_wm_values *wm)
4397 {
4398 enum pipe pipe;
4399 uint32_t tmp;
4400
4401 for_each_pipe(dev_priv, pipe) {
4402 tmp = I915_READ(VLV_DDL(pipe));
4403
4404 wm->ddl[pipe].primary =
4405 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4406 wm->ddl[pipe].cursor =
4407 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4408 wm->ddl[pipe].sprite[0] =
4409 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4410 wm->ddl[pipe].sprite[1] =
4411 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4412 }
4413
4414 tmp = I915_READ(DSPFW1);
4415 wm->sr.plane = _FW_WM(tmp, SR);
4416 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4417 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4418 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4419
4420 tmp = I915_READ(DSPFW2);
4421 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4422 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4423 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4424
4425 tmp = I915_READ(DSPFW3);
4426 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4427
4428 if (IS_CHERRYVIEW(dev_priv)) {
4429 tmp = I915_READ(DSPFW7_CHV);
4430 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4431 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4432
4433 tmp = I915_READ(DSPFW8_CHV);
4434 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4435 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4436
4437 tmp = I915_READ(DSPFW9_CHV);
4438 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4439 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4440
4441 tmp = I915_READ(DSPHOWM);
4442 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4443 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4444 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4445 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4446 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4447 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4448 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4449 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4450 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4451 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4452 } else {
4453 tmp = I915_READ(DSPFW7);
4454 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4455 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4456
4457 tmp = I915_READ(DSPHOWM);
4458 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4459 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4460 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4461 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4462 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4463 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4464 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4465 }
4466 }
4467
4468 #undef _FW_WM
4469 #undef _FW_WM_VLV
4470
4471 void vlv_wm_get_hw_state(struct drm_device *dev)
4472 {
4473 struct drm_i915_private *dev_priv = to_i915(dev);
4474 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4475 struct intel_plane *plane;
4476 enum pipe pipe;
4477 u32 val;
4478
4479 vlv_read_wm_values(dev_priv, wm);
4480
4481 for_each_intel_plane(dev, plane) {
4482 switch (plane->base.type) {
4483 int sprite;
4484 case DRM_PLANE_TYPE_CURSOR:
4485 plane->wm.fifo_size = 63;
4486 break;
4487 case DRM_PLANE_TYPE_PRIMARY:
4488 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4489 break;
4490 case DRM_PLANE_TYPE_OVERLAY:
4491 sprite = plane->plane;
4492 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4493 break;
4494 }
4495 }
4496
4497 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4498 wm->level = VLV_WM_LEVEL_PM2;
4499
4500 if (IS_CHERRYVIEW(dev_priv)) {
4501 mutex_lock(&dev_priv->rps.hw_lock);
4502
4503 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4504 if (val & DSP_MAXFIFO_PM5_ENABLE)
4505 wm->level = VLV_WM_LEVEL_PM5;
4506
4507 /*
4508 * If DDR DVFS is disabled in the BIOS, Punit
4509 * will never ack the request. So if that happens
4510 * assume we don't have to enable/disable DDR DVFS
4511 * dynamically. To test that just set the REQ_ACK
4512 * bit to poke the Punit, but don't change the
4513 * HIGH/LOW bits so that we don't actually change
4514 * the current state.
4515 */
4516 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4517 val |= FORCE_DDR_FREQ_REQ_ACK;
4518 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4519
4520 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4521 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4522 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4523 "assuming DDR DVFS is disabled\n");
4524 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4525 } else {
4526 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4527 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4528 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4529 }
4530
4531 mutex_unlock(&dev_priv->rps.hw_lock);
4532 }
4533
4534 for_each_pipe(dev_priv, pipe)
4535 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4536 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4537 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4538
4539 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4540 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4541 }
4542
4543 void ilk_wm_get_hw_state(struct drm_device *dev)
4544 {
4545 struct drm_i915_private *dev_priv = to_i915(dev);
4546 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4547 struct drm_crtc *crtc;
4548
4549 for_each_crtc(dev, crtc)
4550 ilk_pipe_wm_get_hw_state(crtc);
4551
4552 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4553 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4554 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4555
4556 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4557 if (INTEL_INFO(dev)->gen >= 7) {
4558 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4559 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4560 }
4561
4562 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4563 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4564 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4565 else if (IS_IVYBRIDGE(dev))
4566 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4567 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4568
4569 hw->enable_fbc_wm =
4570 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4571 }
4572
4573 /**
4574 * intel_update_watermarks - update FIFO watermark values based on current modes
4575 *
4576 * Calculate watermark values for the various WM regs based on current mode
4577 * and plane configuration.
4578 *
4579 * There are several cases to deal with here:
4580 * - normal (i.e. non-self-refresh)
4581 * - self-refresh (SR) mode
4582 * - lines are large relative to FIFO size (buffer can hold up to 2)
4583 * - lines are small relative to FIFO size (buffer can hold more than 2
4584 * lines), so need to account for TLB latency
4585 *
4586 * The normal calculation is:
4587 * watermark = dotclock * bytes per pixel * latency
4588 * where latency is platform & configuration dependent (we assume pessimal
4589 * values here).
4590 *
4591 * The SR calculation is:
4592 * watermark = (trunc(latency/line time)+1) * surface width *
4593 * bytes per pixel
4594 * where
4595 * line time = htotal / dotclock
4596 * surface width = hdisplay for normal plane and 64 for cursor
4597 * and latency is assumed to be high, as above.
4598 *
4599 * The final value programmed to the register should always be rounded up,
4600 * and include an extra 2 entries to account for clock crossings.
4601 *
4602 * We don't use the sprite, so we can ignore that. And on Crestline we have
4603 * to set the non-SR watermarks to 8.
4604 */
4605 void intel_update_watermarks(struct drm_crtc *crtc)
4606 {
4607 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4608
4609 if (dev_priv->display.update_wm)
4610 dev_priv->display.update_wm(crtc);
4611 }
4612
4613 /*
4614 * Lock protecting IPS related data structures
4615 */
4616 DEFINE_SPINLOCK(mchdev_lock);
4617
4618 /* Global for IPS driver to get at the current i915 device. Protected by
4619 * mchdev_lock. */
4620 static struct drm_i915_private *i915_mch_dev;
4621
4622 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4623 {
4624 u16 rgvswctl;
4625
4626 assert_spin_locked(&mchdev_lock);
4627
4628 rgvswctl = I915_READ16(MEMSWCTL);
4629 if (rgvswctl & MEMCTL_CMD_STS) {
4630 DRM_DEBUG("gpu busy, RCS change rejected\n");
4631 return false; /* still busy with another command */
4632 }
4633
4634 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4635 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4636 I915_WRITE16(MEMSWCTL, rgvswctl);
4637 POSTING_READ16(MEMSWCTL);
4638
4639 rgvswctl |= MEMCTL_CMD_STS;
4640 I915_WRITE16(MEMSWCTL, rgvswctl);
4641
4642 return true;
4643 }
4644
4645 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4646 {
4647 u32 rgvmodectl;
4648 u8 fmax, fmin, fstart, vstart;
4649
4650 spin_lock_irq(&mchdev_lock);
4651
4652 rgvmodectl = I915_READ(MEMMODECTL);
4653
4654 /* Enable temp reporting */
4655 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4656 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4657
4658 /* 100ms RC evaluation intervals */
4659 I915_WRITE(RCUPEI, 100000);
4660 I915_WRITE(RCDNEI, 100000);
4661
4662 /* Set max/min thresholds to 90ms and 80ms respectively */
4663 I915_WRITE(RCBMAXAVG, 90000);
4664 I915_WRITE(RCBMINAVG, 80000);
4665
4666 I915_WRITE(MEMIHYST, 1);
4667
4668 /* Set up min, max, and cur for interrupt handling */
4669 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4670 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4671 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4672 MEMMODE_FSTART_SHIFT;
4673
4674 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4675 PXVFREQ_PX_SHIFT;
4676
4677 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4678 dev_priv->ips.fstart = fstart;
4679
4680 dev_priv->ips.max_delay = fstart;
4681 dev_priv->ips.min_delay = fmin;
4682 dev_priv->ips.cur_delay = fstart;
4683
4684 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4685 fmax, fmin, fstart);
4686
4687 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4688
4689 /*
4690 * Interrupts will be enabled in ironlake_irq_postinstall
4691 */
4692
4693 I915_WRITE(VIDSTART, vstart);
4694 POSTING_READ(VIDSTART);
4695
4696 rgvmodectl |= MEMMODE_SWMODE_EN;
4697 I915_WRITE(MEMMODECTL, rgvmodectl);
4698
4699 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4700 DRM_ERROR("stuck trying to change perf mode\n");
4701 mdelay(1);
4702
4703 ironlake_set_drps(dev_priv, fstart);
4704
4705 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4706 I915_READ(DDREC) + I915_READ(CSIEC);
4707 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4708 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4709 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4710
4711 spin_unlock_irq(&mchdev_lock);
4712 }
4713
4714 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4715 {
4716 u16 rgvswctl;
4717
4718 spin_lock_irq(&mchdev_lock);
4719
4720 rgvswctl = I915_READ16(MEMSWCTL);
4721
4722 /* Ack interrupts, disable EFC interrupt */
4723 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4724 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4725 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4726 I915_WRITE(DEIIR, DE_PCU_EVENT);
4727 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4728
4729 /* Go back to the starting frequency */
4730 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4731 mdelay(1);
4732 rgvswctl |= MEMCTL_CMD_STS;
4733 I915_WRITE(MEMSWCTL, rgvswctl);
4734 mdelay(1);
4735
4736 spin_unlock_irq(&mchdev_lock);
4737 }
4738
4739 /* There's a funny hw issue where the hw returns all 0 when reading from
4740 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4741 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4742 * all limits and the gpu stuck at whatever frequency it is at atm).
4743 */
4744 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4745 {
4746 u32 limits;
4747
4748 /* Only set the down limit when we've reached the lowest level to avoid
4749 * getting more interrupts, otherwise leave this clear. This prevents a
4750 * race in the hw when coming out of rc6: There's a tiny window where
4751 * the hw runs at the minimal clock before selecting the desired
4752 * frequency, if the down threshold expires in that window we will not
4753 * receive a down interrupt. */
4754 if (IS_GEN9(dev_priv)) {
4755 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4756 if (val <= dev_priv->rps.min_freq_softlimit)
4757 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4758 } else {
4759 limits = dev_priv->rps.max_freq_softlimit << 24;
4760 if (val <= dev_priv->rps.min_freq_softlimit)
4761 limits |= dev_priv->rps.min_freq_softlimit << 16;
4762 }
4763
4764 return limits;
4765 }
4766
4767 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4768 {
4769 int new_power;
4770 u32 threshold_up = 0, threshold_down = 0; /* in % */
4771 u32 ei_up = 0, ei_down = 0;
4772
4773 new_power = dev_priv->rps.power;
4774 switch (dev_priv->rps.power) {
4775 case LOW_POWER:
4776 if (val > dev_priv->rps.efficient_freq + 1 &&
4777 val > dev_priv->rps.cur_freq)
4778 new_power = BETWEEN;
4779 break;
4780
4781 case BETWEEN:
4782 if (val <= dev_priv->rps.efficient_freq &&
4783 val < dev_priv->rps.cur_freq)
4784 new_power = LOW_POWER;
4785 else if (val >= dev_priv->rps.rp0_freq &&
4786 val > dev_priv->rps.cur_freq)
4787 new_power = HIGH_POWER;
4788 break;
4789
4790 case HIGH_POWER:
4791 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4792 val < dev_priv->rps.cur_freq)
4793 new_power = BETWEEN;
4794 break;
4795 }
4796 /* Max/min bins are special */
4797 if (val <= dev_priv->rps.min_freq_softlimit)
4798 new_power = LOW_POWER;
4799 if (val >= dev_priv->rps.max_freq_softlimit)
4800 new_power = HIGH_POWER;
4801 if (new_power == dev_priv->rps.power)
4802 return;
4803
4804 /* Note the units here are not exactly 1us, but 1280ns. */
4805 switch (new_power) {
4806 case LOW_POWER:
4807 /* Upclock if more than 95% busy over 16ms */
4808 ei_up = 16000;
4809 threshold_up = 95;
4810
4811 /* Downclock if less than 85% busy over 32ms */
4812 ei_down = 32000;
4813 threshold_down = 85;
4814 break;
4815
4816 case BETWEEN:
4817 /* Upclock if more than 90% busy over 13ms */
4818 ei_up = 13000;
4819 threshold_up = 90;
4820
4821 /* Downclock if less than 75% busy over 32ms */
4822 ei_down = 32000;
4823 threshold_down = 75;
4824 break;
4825
4826 case HIGH_POWER:
4827 /* Upclock if more than 85% busy over 10ms */
4828 ei_up = 10000;
4829 threshold_up = 85;
4830
4831 /* Downclock if less than 60% busy over 32ms */
4832 ei_down = 32000;
4833 threshold_down = 60;
4834 break;
4835 }
4836
4837 I915_WRITE(GEN6_RP_UP_EI,
4838 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4839 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4840 GT_INTERVAL_FROM_US(dev_priv,
4841 ei_up * threshold_up / 100));
4842
4843 I915_WRITE(GEN6_RP_DOWN_EI,
4844 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4845 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4846 GT_INTERVAL_FROM_US(dev_priv,
4847 ei_down * threshold_down / 100));
4848
4849 I915_WRITE(GEN6_RP_CONTROL,
4850 GEN6_RP_MEDIA_TURBO |
4851 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4852 GEN6_RP_MEDIA_IS_GFX |
4853 GEN6_RP_ENABLE |
4854 GEN6_RP_UP_BUSY_AVG |
4855 GEN6_RP_DOWN_IDLE_AVG);
4856
4857 dev_priv->rps.power = new_power;
4858 dev_priv->rps.up_threshold = threshold_up;
4859 dev_priv->rps.down_threshold = threshold_down;
4860 dev_priv->rps.last_adj = 0;
4861 }
4862
4863 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4864 {
4865 u32 mask = 0;
4866
4867 if (val > dev_priv->rps.min_freq_softlimit)
4868 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4869 if (val < dev_priv->rps.max_freq_softlimit)
4870 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4871
4872 mask &= dev_priv->pm_rps_events;
4873
4874 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4875 }
4876
4877 /* gen6_set_rps is called to update the frequency request, but should also be
4878 * called when the range (min_delay and max_delay) is modified so that we can
4879 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4880 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4881 {
4882 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4883 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4884 return;
4885
4886 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4887 WARN_ON(val > dev_priv->rps.max_freq);
4888 WARN_ON(val < dev_priv->rps.min_freq);
4889
4890 /* min/max delay may still have been modified so be sure to
4891 * write the limits value.
4892 */
4893 if (val != dev_priv->rps.cur_freq) {
4894 gen6_set_rps_thresholds(dev_priv, val);
4895
4896 if (IS_GEN9(dev_priv))
4897 I915_WRITE(GEN6_RPNSWREQ,
4898 GEN9_FREQUENCY(val));
4899 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4900 I915_WRITE(GEN6_RPNSWREQ,
4901 HSW_FREQUENCY(val));
4902 else
4903 I915_WRITE(GEN6_RPNSWREQ,
4904 GEN6_FREQUENCY(val) |
4905 GEN6_OFFSET(0) |
4906 GEN6_AGGRESSIVE_TURBO);
4907 }
4908
4909 /* Make sure we continue to get interrupts
4910 * until we hit the minimum or maximum frequencies.
4911 */
4912 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4913 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4914
4915 POSTING_READ(GEN6_RPNSWREQ);
4916
4917 dev_priv->rps.cur_freq = val;
4918 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4919 }
4920
4921 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4922 {
4923 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4924 WARN_ON(val > dev_priv->rps.max_freq);
4925 WARN_ON(val < dev_priv->rps.min_freq);
4926
4927 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4928 "Odd GPU freq value\n"))
4929 val &= ~1;
4930
4931 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4932
4933 if (val != dev_priv->rps.cur_freq) {
4934 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4935 if (!IS_CHERRYVIEW(dev_priv))
4936 gen6_set_rps_thresholds(dev_priv, val);
4937 }
4938
4939 dev_priv->rps.cur_freq = val;
4940 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4941 }
4942
4943 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4944 *
4945 * * If Gfx is Idle, then
4946 * 1. Forcewake Media well.
4947 * 2. Request idle freq.
4948 * 3. Release Forcewake of Media well.
4949 */
4950 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4951 {
4952 u32 val = dev_priv->rps.idle_freq;
4953
4954 if (dev_priv->rps.cur_freq <= val)
4955 return;
4956
4957 /* Wake up the media well, as that takes a lot less
4958 * power than the Render well. */
4959 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4960 valleyview_set_rps(dev_priv, val);
4961 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4962 }
4963
4964 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4965 {
4966 mutex_lock(&dev_priv->rps.hw_lock);
4967 if (dev_priv->rps.enabled) {
4968 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4969 gen6_rps_reset_ei(dev_priv);
4970 I915_WRITE(GEN6_PMINTRMSK,
4971 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4972
4973 gen6_enable_rps_interrupts(dev_priv);
4974
4975 /* Ensure we start at the user's desired frequency */
4976 intel_set_rps(dev_priv,
4977 clamp(dev_priv->rps.cur_freq,
4978 dev_priv->rps.min_freq_softlimit,
4979 dev_priv->rps.max_freq_softlimit));
4980 }
4981 mutex_unlock(&dev_priv->rps.hw_lock);
4982 }
4983
4984 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4985 {
4986 /* Flush our bottom-half so that it does not race with us
4987 * setting the idle frequency and so that it is bounded by
4988 * our rpm wakeref. And then disable the interrupts to stop any
4989 * futher RPS reclocking whilst we are asleep.
4990 */
4991 gen6_disable_rps_interrupts(dev_priv);
4992
4993 mutex_lock(&dev_priv->rps.hw_lock);
4994 if (dev_priv->rps.enabled) {
4995 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4996 vlv_set_rps_idle(dev_priv);
4997 else
4998 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4999 dev_priv->rps.last_adj = 0;
5000 I915_WRITE(GEN6_PMINTRMSK,
5001 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5002 }
5003 mutex_unlock(&dev_priv->rps.hw_lock);
5004
5005 spin_lock(&dev_priv->rps.client_lock);
5006 while (!list_empty(&dev_priv->rps.clients))
5007 list_del_init(dev_priv->rps.clients.next);
5008 spin_unlock(&dev_priv->rps.client_lock);
5009 }
5010
5011 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5012 struct intel_rps_client *rps,
5013 unsigned long submitted)
5014 {
5015 /* This is intentionally racy! We peek at the state here, then
5016 * validate inside the RPS worker.
5017 */
5018 if (!(dev_priv->gt.awake &&
5019 dev_priv->rps.enabled &&
5020 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5021 return;
5022
5023 /* Force a RPS boost (and don't count it against the client) if
5024 * the GPU is severely congested.
5025 */
5026 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5027 rps = NULL;
5028
5029 spin_lock(&dev_priv->rps.client_lock);
5030 if (rps == NULL || list_empty(&rps->link)) {
5031 spin_lock_irq(&dev_priv->irq_lock);
5032 if (dev_priv->rps.interrupts_enabled) {
5033 dev_priv->rps.client_boost = true;
5034 schedule_work(&dev_priv->rps.work);
5035 }
5036 spin_unlock_irq(&dev_priv->irq_lock);
5037
5038 if (rps != NULL) {
5039 list_add(&rps->link, &dev_priv->rps.clients);
5040 rps->boosts++;
5041 } else
5042 dev_priv->rps.boosts++;
5043 }
5044 spin_unlock(&dev_priv->rps.client_lock);
5045 }
5046
5047 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5048 {
5049 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5050 valleyview_set_rps(dev_priv, val);
5051 else
5052 gen6_set_rps(dev_priv, val);
5053 }
5054
5055 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5056 {
5057 I915_WRITE(GEN6_RC_CONTROL, 0);
5058 I915_WRITE(GEN9_PG_ENABLE, 0);
5059 }
5060
5061 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5062 {
5063 I915_WRITE(GEN6_RP_CONTROL, 0);
5064 }
5065
5066 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5067 {
5068 I915_WRITE(GEN6_RC_CONTROL, 0);
5069 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5070 I915_WRITE(GEN6_RP_CONTROL, 0);
5071 }
5072
5073 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5074 {
5075 I915_WRITE(GEN6_RC_CONTROL, 0);
5076 }
5077
5078 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5079 {
5080 /* we're doing forcewake before Disabling RC6,
5081 * This what the BIOS expects when going into suspend */
5082 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5083
5084 I915_WRITE(GEN6_RC_CONTROL, 0);
5085
5086 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5087 }
5088
5089 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5090 {
5091 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5092 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5093 mode = GEN6_RC_CTL_RC6_ENABLE;
5094 else
5095 mode = 0;
5096 }
5097 if (HAS_RC6p(dev_priv))
5098 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5099 "RC6 %s RC6p %s RC6pp %s\n",
5100 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5101 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5102 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5103
5104 else
5105 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5106 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5107 }
5108
5109 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5110 {
5111 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5112 bool enable_rc6 = true;
5113 unsigned long rc6_ctx_base;
5114 u32 rc_ctl;
5115 int rc_sw_target;
5116
5117 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5118 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5119 RC_SW_TARGET_STATE_SHIFT;
5120 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5121 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5122 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5123 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5124 rc_sw_target);
5125
5126 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5127 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5128 enable_rc6 = false;
5129 }
5130
5131 /*
5132 * The exact context size is not known for BXT, so assume a page size
5133 * for this check.
5134 */
5135 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5136 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5137 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5138 ggtt->stolen_reserved_size))) {
5139 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5140 enable_rc6 = false;
5141 }
5142
5143 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5144 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5145 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5146 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5147 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5148 enable_rc6 = false;
5149 }
5150
5151 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5152 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5153 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5154 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5155 enable_rc6 = false;
5156 }
5157
5158 if (!I915_READ(GEN6_GFXPAUSE)) {
5159 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5160 enable_rc6 = false;
5161 }
5162
5163 if (!I915_READ(GEN8_MISC_CTRL0)) {
5164 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5165 enable_rc6 = false;
5166 }
5167
5168 return enable_rc6;
5169 }
5170
5171 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5172 {
5173 /* No RC6 before Ironlake and code is gone for ilk. */
5174 if (INTEL_INFO(dev_priv)->gen < 6)
5175 return 0;
5176
5177 if (!enable_rc6)
5178 return 0;
5179
5180 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5181 DRM_INFO("RC6 disabled by BIOS\n");
5182 return 0;
5183 }
5184
5185 /* Respect the kernel parameter if it is set */
5186 if (enable_rc6 >= 0) {
5187 int mask;
5188
5189 if (HAS_RC6p(dev_priv))
5190 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5191 INTEL_RC6pp_ENABLE;
5192 else
5193 mask = INTEL_RC6_ENABLE;
5194
5195 if ((enable_rc6 & mask) != enable_rc6)
5196 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5197 "(requested %d, valid %d)\n",
5198 enable_rc6 & mask, enable_rc6, mask);
5199
5200 return enable_rc6 & mask;
5201 }
5202
5203 if (IS_IVYBRIDGE(dev_priv))
5204 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5205
5206 return INTEL_RC6_ENABLE;
5207 }
5208
5209 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5210 {
5211 /* All of these values are in units of 50MHz */
5212
5213 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5214 if (IS_BROXTON(dev_priv)) {
5215 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5216 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5217 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5218 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5219 } else {
5220 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5221 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5222 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5223 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5224 }
5225 /* hw_max = RP0 until we check for overclocking */
5226 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5227
5228 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5229 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5230 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5231 u32 ddcc_status = 0;
5232
5233 if (sandybridge_pcode_read(dev_priv,
5234 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5235 &ddcc_status) == 0)
5236 dev_priv->rps.efficient_freq =
5237 clamp_t(u8,
5238 ((ddcc_status >> 8) & 0xff),
5239 dev_priv->rps.min_freq,
5240 dev_priv->rps.max_freq);
5241 }
5242
5243 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5244 /* Store the frequency values in 16.66 MHZ units, which is
5245 * the natural hardware unit for SKL
5246 */
5247 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5248 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5249 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5250 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5251 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5252 }
5253 }
5254
5255 static void reset_rps(struct drm_i915_private *dev_priv,
5256 void (*set)(struct drm_i915_private *, u8))
5257 {
5258 u8 freq = dev_priv->rps.cur_freq;
5259
5260 /* force a reset */
5261 dev_priv->rps.power = -1;
5262 dev_priv->rps.cur_freq = -1;
5263
5264 set(dev_priv, freq);
5265 }
5266
5267 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5268 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5269 {
5270 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5271
5272 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5273 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5274 /*
5275 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5276 * clear out the Control register just to avoid inconsitency
5277 * with debugfs interface, which will show Turbo as enabled
5278 * only and that is not expected by the User after adding the
5279 * WaGsvDisableTurbo. Apart from this there is no problem even
5280 * if the Turbo is left enabled in the Control register, as the
5281 * Up/Down interrupts would remain masked.
5282 */
5283 gen9_disable_rps(dev_priv);
5284 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5285 return;
5286 }
5287
5288 /* Program defaults and thresholds for RPS*/
5289 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5290 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5291
5292 /* 1 second timeout*/
5293 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5294 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5295
5296 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5297
5298 /* Leaning on the below call to gen6_set_rps to program/setup the
5299 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5300 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5301 reset_rps(dev_priv, gen6_set_rps);
5302
5303 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5304 }
5305
5306 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5307 {
5308 struct intel_engine_cs *engine;
5309 uint32_t rc6_mask = 0;
5310
5311 /* 1a: Software RC state - RC0 */
5312 I915_WRITE(GEN6_RC_STATE, 0);
5313
5314 /* 1b: Get forcewake during program sequence. Although the driver
5315 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5316 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5317
5318 /* 2a: Disable RC states. */
5319 I915_WRITE(GEN6_RC_CONTROL, 0);
5320
5321 /* 2b: Program RC6 thresholds.*/
5322
5323 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5324 if (IS_SKYLAKE(dev_priv))
5325 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5326 else
5327 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5328 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5329 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5330 for_each_engine(engine, dev_priv)
5331 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5332
5333 if (HAS_GUC(dev_priv))
5334 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5335
5336 I915_WRITE(GEN6_RC_SLEEP, 0);
5337
5338 /* 2c: Program Coarse Power Gating Policies. */
5339 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5340 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5341
5342 /* 3a: Enable RC6 */
5343 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5344 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5345 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5346 /* WaRsUseTimeoutMode */
5347 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5348 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5349 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5350 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5351 GEN7_RC_CTL_TO_MODE |
5352 rc6_mask);
5353 } else {
5354 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5355 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5356 GEN6_RC_CTL_EI_MODE(1) |
5357 rc6_mask);
5358 }
5359
5360 /*
5361 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5362 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5363 */
5364 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5365 I915_WRITE(GEN9_PG_ENABLE, 0);
5366 else
5367 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5368 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5369
5370 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5371 }
5372
5373 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5374 {
5375 struct intel_engine_cs *engine;
5376 uint32_t rc6_mask = 0;
5377
5378 /* 1a: Software RC state - RC0 */
5379 I915_WRITE(GEN6_RC_STATE, 0);
5380
5381 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5382 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5383 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5384
5385 /* 2a: Disable RC states. */
5386 I915_WRITE(GEN6_RC_CONTROL, 0);
5387
5388 /* 2b: Program RC6 thresholds.*/
5389 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5390 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5391 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5392 for_each_engine(engine, dev_priv)
5393 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5394 I915_WRITE(GEN6_RC_SLEEP, 0);
5395 if (IS_BROADWELL(dev_priv))
5396 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5397 else
5398 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5399
5400 /* 3: Enable RC6 */
5401 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5402 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5403 intel_print_rc6_info(dev_priv, rc6_mask);
5404 if (IS_BROADWELL(dev_priv))
5405 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5406 GEN7_RC_CTL_TO_MODE |
5407 rc6_mask);
5408 else
5409 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5410 GEN6_RC_CTL_EI_MODE(1) |
5411 rc6_mask);
5412
5413 /* 4 Program defaults and thresholds for RPS*/
5414 I915_WRITE(GEN6_RPNSWREQ,
5415 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5416 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5417 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5418 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5419 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5420
5421 /* Docs recommend 900MHz, and 300 MHz respectively */
5422 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5423 dev_priv->rps.max_freq_softlimit << 24 |
5424 dev_priv->rps.min_freq_softlimit << 16);
5425
5426 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5427 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5428 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5429 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5430
5431 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5432
5433 /* 5: Enable RPS */
5434 I915_WRITE(GEN6_RP_CONTROL,
5435 GEN6_RP_MEDIA_TURBO |
5436 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5437 GEN6_RP_MEDIA_IS_GFX |
5438 GEN6_RP_ENABLE |
5439 GEN6_RP_UP_BUSY_AVG |
5440 GEN6_RP_DOWN_IDLE_AVG);
5441
5442 /* 6: Ring frequency + overclocking (our driver does this later */
5443
5444 reset_rps(dev_priv, gen6_set_rps);
5445
5446 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5447 }
5448
5449 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5450 {
5451 struct intel_engine_cs *engine;
5452 u32 rc6vids, rc6_mask = 0;
5453 u32 gtfifodbg;
5454 int rc6_mode;
5455 int ret;
5456
5457 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5458
5459 /* Here begins a magic sequence of register writes to enable
5460 * auto-downclocking.
5461 *
5462 * Perhaps there might be some value in exposing these to
5463 * userspace...
5464 */
5465 I915_WRITE(GEN6_RC_STATE, 0);
5466
5467 /* Clear the DBG now so we don't confuse earlier errors */
5468 gtfifodbg = I915_READ(GTFIFODBG);
5469 if (gtfifodbg) {
5470 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5471 I915_WRITE(GTFIFODBG, gtfifodbg);
5472 }
5473
5474 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5475
5476 /* disable the counters and set deterministic thresholds */
5477 I915_WRITE(GEN6_RC_CONTROL, 0);
5478
5479 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5480 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5481 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5482 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5483 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5484
5485 for_each_engine(engine, dev_priv)
5486 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5487
5488 I915_WRITE(GEN6_RC_SLEEP, 0);
5489 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5490 if (IS_IVYBRIDGE(dev_priv))
5491 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5492 else
5493 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5494 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5495 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5496
5497 /* Check if we are enabling RC6 */
5498 rc6_mode = intel_enable_rc6();
5499 if (rc6_mode & INTEL_RC6_ENABLE)
5500 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5501
5502 /* We don't use those on Haswell */
5503 if (!IS_HASWELL(dev_priv)) {
5504 if (rc6_mode & INTEL_RC6p_ENABLE)
5505 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5506
5507 if (rc6_mode & INTEL_RC6pp_ENABLE)
5508 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5509 }
5510
5511 intel_print_rc6_info(dev_priv, rc6_mask);
5512
5513 I915_WRITE(GEN6_RC_CONTROL,
5514 rc6_mask |
5515 GEN6_RC_CTL_EI_MODE(1) |
5516 GEN6_RC_CTL_HW_ENABLE);
5517
5518 /* Power down if completely idle for over 50ms */
5519 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5520 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5521
5522 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5523 if (ret)
5524 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5525
5526 reset_rps(dev_priv, gen6_set_rps);
5527
5528 rc6vids = 0;
5529 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5530 if (IS_GEN6(dev_priv) && ret) {
5531 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5532 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5533 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5534 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5535 rc6vids &= 0xffff00;
5536 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5537 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5538 if (ret)
5539 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5540 }
5541
5542 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5543 }
5544
5545 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5546 {
5547 int min_freq = 15;
5548 unsigned int gpu_freq;
5549 unsigned int max_ia_freq, min_ring_freq;
5550 unsigned int max_gpu_freq, min_gpu_freq;
5551 int scaling_factor = 180;
5552 struct cpufreq_policy *policy;
5553
5554 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5555
5556 policy = cpufreq_cpu_get(0);
5557 if (policy) {
5558 max_ia_freq = policy->cpuinfo.max_freq;
5559 cpufreq_cpu_put(policy);
5560 } else {
5561 /*
5562 * Default to measured freq if none found, PCU will ensure we
5563 * don't go over
5564 */
5565 max_ia_freq = tsc_khz;
5566 }
5567
5568 /* Convert from kHz to MHz */
5569 max_ia_freq /= 1000;
5570
5571 min_ring_freq = I915_READ(DCLK) & 0xf;
5572 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5573 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5574
5575 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5576 /* Convert GT frequency to 50 HZ units */
5577 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5578 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5579 } else {
5580 min_gpu_freq = dev_priv->rps.min_freq;
5581 max_gpu_freq = dev_priv->rps.max_freq;
5582 }
5583
5584 /*
5585 * For each potential GPU frequency, load a ring frequency we'd like
5586 * to use for memory access. We do this by specifying the IA frequency
5587 * the PCU should use as a reference to determine the ring frequency.
5588 */
5589 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5590 int diff = max_gpu_freq - gpu_freq;
5591 unsigned int ia_freq = 0, ring_freq = 0;
5592
5593 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5594 /*
5595 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5596 * No floor required for ring frequency on SKL.
5597 */
5598 ring_freq = gpu_freq;
5599 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5600 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5601 ring_freq = max(min_ring_freq, gpu_freq);
5602 } else if (IS_HASWELL(dev_priv)) {
5603 ring_freq = mult_frac(gpu_freq, 5, 4);
5604 ring_freq = max(min_ring_freq, ring_freq);
5605 /* leave ia_freq as the default, chosen by cpufreq */
5606 } else {
5607 /* On older processors, there is no separate ring
5608 * clock domain, so in order to boost the bandwidth
5609 * of the ring, we need to upclock the CPU (ia_freq).
5610 *
5611 * For GPU frequencies less than 750MHz,
5612 * just use the lowest ring freq.
5613 */
5614 if (gpu_freq < min_freq)
5615 ia_freq = 800;
5616 else
5617 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5618 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5619 }
5620
5621 sandybridge_pcode_write(dev_priv,
5622 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5623 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5624 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5625 gpu_freq);
5626 }
5627 }
5628
5629 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5630 {
5631 u32 val, rp0;
5632
5633 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5634
5635 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5636 case 8:
5637 /* (2 * 4) config */
5638 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5639 break;
5640 case 12:
5641 /* (2 * 6) config */
5642 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5643 break;
5644 case 16:
5645 /* (2 * 8) config */
5646 default:
5647 /* Setting (2 * 8) Min RP0 for any other combination */
5648 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5649 break;
5650 }
5651
5652 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5653
5654 return rp0;
5655 }
5656
5657 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5658 {
5659 u32 val, rpe;
5660
5661 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5662 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5663
5664 return rpe;
5665 }
5666
5667 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5668 {
5669 u32 val, rp1;
5670
5671 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5672 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5673
5674 return rp1;
5675 }
5676
5677 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5678 {
5679 u32 val, rp1;
5680
5681 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5682
5683 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5684
5685 return rp1;
5686 }
5687
5688 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5689 {
5690 u32 val, rp0;
5691
5692 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5693
5694 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5695 /* Clamp to max */
5696 rp0 = min_t(u32, rp0, 0xea);
5697
5698 return rp0;
5699 }
5700
5701 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5702 {
5703 u32 val, rpe;
5704
5705 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5706 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5707 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5708 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5709
5710 return rpe;
5711 }
5712
5713 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5714 {
5715 u32 val;
5716
5717 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5718 /*
5719 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5720 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5721 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5722 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5723 * to make sure it matches what Punit accepts.
5724 */
5725 return max_t(u32, val, 0xc0);
5726 }
5727
5728 /* Check that the pctx buffer wasn't move under us. */
5729 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5730 {
5731 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5732
5733 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5734 dev_priv->vlv_pctx->stolen->start);
5735 }
5736
5737
5738 /* Check that the pcbr address is not empty. */
5739 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5740 {
5741 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5742
5743 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5744 }
5745
5746 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5747 {
5748 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5749 unsigned long pctx_paddr, paddr;
5750 u32 pcbr;
5751 int pctx_size = 32*1024;
5752
5753 pcbr = I915_READ(VLV_PCBR);
5754 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5755 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5756 paddr = (dev_priv->mm.stolen_base +
5757 (ggtt->stolen_size - pctx_size));
5758
5759 pctx_paddr = (paddr & (~4095));
5760 I915_WRITE(VLV_PCBR, pctx_paddr);
5761 }
5762
5763 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5764 }
5765
5766 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5767 {
5768 struct drm_i915_gem_object *pctx;
5769 unsigned long pctx_paddr;
5770 u32 pcbr;
5771 int pctx_size = 24*1024;
5772
5773 pcbr = I915_READ(VLV_PCBR);
5774 if (pcbr) {
5775 /* BIOS set it up already, grab the pre-alloc'd space */
5776 int pcbr_offset;
5777
5778 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5779 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5780 pcbr_offset,
5781 I915_GTT_OFFSET_NONE,
5782 pctx_size);
5783 goto out;
5784 }
5785
5786 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5787
5788 /*
5789 * From the Gunit register HAS:
5790 * The Gfx driver is expected to program this register and ensure
5791 * proper allocation within Gfx stolen memory. For example, this
5792 * register should be programmed such than the PCBR range does not
5793 * overlap with other ranges, such as the frame buffer, protected
5794 * memory, or any other relevant ranges.
5795 */
5796 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5797 if (!pctx) {
5798 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5799 goto out;
5800 }
5801
5802 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5803 I915_WRITE(VLV_PCBR, pctx_paddr);
5804
5805 out:
5806 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5807 dev_priv->vlv_pctx = pctx;
5808 }
5809
5810 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5811 {
5812 if (WARN_ON(!dev_priv->vlv_pctx))
5813 return;
5814
5815 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5816 dev_priv->vlv_pctx = NULL;
5817 }
5818
5819 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5820 {
5821 dev_priv->rps.gpll_ref_freq =
5822 vlv_get_cck_clock(dev_priv, "GPLL ref",
5823 CCK_GPLL_CLOCK_CONTROL,
5824 dev_priv->czclk_freq);
5825
5826 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5827 dev_priv->rps.gpll_ref_freq);
5828 }
5829
5830 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5831 {
5832 u32 val;
5833
5834 valleyview_setup_pctx(dev_priv);
5835
5836 vlv_init_gpll_ref_freq(dev_priv);
5837
5838 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5839 switch ((val >> 6) & 3) {
5840 case 0:
5841 case 1:
5842 dev_priv->mem_freq = 800;
5843 break;
5844 case 2:
5845 dev_priv->mem_freq = 1066;
5846 break;
5847 case 3:
5848 dev_priv->mem_freq = 1333;
5849 break;
5850 }
5851 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5852
5853 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5854 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5855 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5856 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5857 dev_priv->rps.max_freq);
5858
5859 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5860 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5861 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5862 dev_priv->rps.efficient_freq);
5863
5864 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5865 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5866 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5867 dev_priv->rps.rp1_freq);
5868
5869 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5870 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5871 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5872 dev_priv->rps.min_freq);
5873 }
5874
5875 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5876 {
5877 u32 val;
5878
5879 cherryview_setup_pctx(dev_priv);
5880
5881 vlv_init_gpll_ref_freq(dev_priv);
5882
5883 mutex_lock(&dev_priv->sb_lock);
5884 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5885 mutex_unlock(&dev_priv->sb_lock);
5886
5887 switch ((val >> 2) & 0x7) {
5888 case 3:
5889 dev_priv->mem_freq = 2000;
5890 break;
5891 default:
5892 dev_priv->mem_freq = 1600;
5893 break;
5894 }
5895 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5896
5897 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5898 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5899 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5900 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5901 dev_priv->rps.max_freq);
5902
5903 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5904 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5905 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5906 dev_priv->rps.efficient_freq);
5907
5908 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5909 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5910 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5911 dev_priv->rps.rp1_freq);
5912
5913 /* PUnit validated range is only [RPe, RP0] */
5914 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5915 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5916 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5917 dev_priv->rps.min_freq);
5918
5919 WARN_ONCE((dev_priv->rps.max_freq |
5920 dev_priv->rps.efficient_freq |
5921 dev_priv->rps.rp1_freq |
5922 dev_priv->rps.min_freq) & 1,
5923 "Odd GPU freq values\n");
5924 }
5925
5926 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5927 {
5928 valleyview_cleanup_pctx(dev_priv);
5929 }
5930
5931 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5932 {
5933 struct intel_engine_cs *engine;
5934 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5935
5936 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5937
5938 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5939 GT_FIFO_FREE_ENTRIES_CHV);
5940 if (gtfifodbg) {
5941 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5942 gtfifodbg);
5943 I915_WRITE(GTFIFODBG, gtfifodbg);
5944 }
5945
5946 cherryview_check_pctx(dev_priv);
5947
5948 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5949 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5950 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5951
5952 /* Disable RC states. */
5953 I915_WRITE(GEN6_RC_CONTROL, 0);
5954
5955 /* 2a: Program RC6 thresholds.*/
5956 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5957 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5958 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5959
5960 for_each_engine(engine, dev_priv)
5961 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5962 I915_WRITE(GEN6_RC_SLEEP, 0);
5963
5964 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5965 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5966
5967 /* allows RC6 residency counter to work */
5968 I915_WRITE(VLV_COUNTER_CONTROL,
5969 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5970 VLV_MEDIA_RC6_COUNT_EN |
5971 VLV_RENDER_RC6_COUNT_EN));
5972
5973 /* For now we assume BIOS is allocating and populating the PCBR */
5974 pcbr = I915_READ(VLV_PCBR);
5975
5976 /* 3: Enable RC6 */
5977 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5978 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5979 rc6_mode = GEN7_RC_CTL_TO_MODE;
5980
5981 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5982
5983 /* 4 Program defaults and thresholds for RPS*/
5984 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5985 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5986 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5987 I915_WRITE(GEN6_RP_UP_EI, 66000);
5988 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5989
5990 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5991
5992 /* 5: Enable RPS */
5993 I915_WRITE(GEN6_RP_CONTROL,
5994 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5995 GEN6_RP_MEDIA_IS_GFX |
5996 GEN6_RP_ENABLE |
5997 GEN6_RP_UP_BUSY_AVG |
5998 GEN6_RP_DOWN_IDLE_AVG);
5999
6000 /* Setting Fixed Bias */
6001 val = VLV_OVERRIDE_EN |
6002 VLV_SOC_TDP_EN |
6003 CHV_BIAS_CPU_50_SOC_50;
6004 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6005
6006 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6007
6008 /* RPS code assumes GPLL is used */
6009 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6010
6011 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6012 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6013
6014 reset_rps(dev_priv, valleyview_set_rps);
6015
6016 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6017 }
6018
6019 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6020 {
6021 struct intel_engine_cs *engine;
6022 u32 gtfifodbg, val, rc6_mode = 0;
6023
6024 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6025
6026 valleyview_check_pctx(dev_priv);
6027
6028 gtfifodbg = I915_READ(GTFIFODBG);
6029 if (gtfifodbg) {
6030 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6031 gtfifodbg);
6032 I915_WRITE(GTFIFODBG, gtfifodbg);
6033 }
6034
6035 /* If VLV, Forcewake all wells, else re-direct to regular path */
6036 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6037
6038 /* Disable RC states. */
6039 I915_WRITE(GEN6_RC_CONTROL, 0);
6040
6041 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6042 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6043 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6044 I915_WRITE(GEN6_RP_UP_EI, 66000);
6045 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6046
6047 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6048
6049 I915_WRITE(GEN6_RP_CONTROL,
6050 GEN6_RP_MEDIA_TURBO |
6051 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6052 GEN6_RP_MEDIA_IS_GFX |
6053 GEN6_RP_ENABLE |
6054 GEN6_RP_UP_BUSY_AVG |
6055 GEN6_RP_DOWN_IDLE_CONT);
6056
6057 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6058 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6059 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6060
6061 for_each_engine(engine, dev_priv)
6062 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6063
6064 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6065
6066 /* allows RC6 residency counter to work */
6067 I915_WRITE(VLV_COUNTER_CONTROL,
6068 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6069 VLV_RENDER_RC0_COUNT_EN |
6070 VLV_MEDIA_RC6_COUNT_EN |
6071 VLV_RENDER_RC6_COUNT_EN));
6072
6073 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6074 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6075
6076 intel_print_rc6_info(dev_priv, rc6_mode);
6077
6078 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6079
6080 /* Setting Fixed Bias */
6081 val = VLV_OVERRIDE_EN |
6082 VLV_SOC_TDP_EN |
6083 VLV_BIAS_CPU_125_SOC_875;
6084 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6085
6086 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6087
6088 /* RPS code assumes GPLL is used */
6089 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6090
6091 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6092 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6093
6094 reset_rps(dev_priv, valleyview_set_rps);
6095
6096 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6097 }
6098
6099 static unsigned long intel_pxfreq(u32 vidfreq)
6100 {
6101 unsigned long freq;
6102 int div = (vidfreq & 0x3f0000) >> 16;
6103 int post = (vidfreq & 0x3000) >> 12;
6104 int pre = (vidfreq & 0x7);
6105
6106 if (!pre)
6107 return 0;
6108
6109 freq = ((div * 133333) / ((1<<post) * pre));
6110
6111 return freq;
6112 }
6113
6114 static const struct cparams {
6115 u16 i;
6116 u16 t;
6117 u16 m;
6118 u16 c;
6119 } cparams[] = {
6120 { 1, 1333, 301, 28664 },
6121 { 1, 1066, 294, 24460 },
6122 { 1, 800, 294, 25192 },
6123 { 0, 1333, 276, 27605 },
6124 { 0, 1066, 276, 27605 },
6125 { 0, 800, 231, 23784 },
6126 };
6127
6128 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6129 {
6130 u64 total_count, diff, ret;
6131 u32 count1, count2, count3, m = 0, c = 0;
6132 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6133 int i;
6134
6135 assert_spin_locked(&mchdev_lock);
6136
6137 diff1 = now - dev_priv->ips.last_time1;
6138
6139 /* Prevent division-by-zero if we are asking too fast.
6140 * Also, we don't get interesting results if we are polling
6141 * faster than once in 10ms, so just return the saved value
6142 * in such cases.
6143 */
6144 if (diff1 <= 10)
6145 return dev_priv->ips.chipset_power;
6146
6147 count1 = I915_READ(DMIEC);
6148 count2 = I915_READ(DDREC);
6149 count3 = I915_READ(CSIEC);
6150
6151 total_count = count1 + count2 + count3;
6152
6153 /* FIXME: handle per-counter overflow */
6154 if (total_count < dev_priv->ips.last_count1) {
6155 diff = ~0UL - dev_priv->ips.last_count1;
6156 diff += total_count;
6157 } else {
6158 diff = total_count - dev_priv->ips.last_count1;
6159 }
6160
6161 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6162 if (cparams[i].i == dev_priv->ips.c_m &&
6163 cparams[i].t == dev_priv->ips.r_t) {
6164 m = cparams[i].m;
6165 c = cparams[i].c;
6166 break;
6167 }
6168 }
6169
6170 diff = div_u64(diff, diff1);
6171 ret = ((m * diff) + c);
6172 ret = div_u64(ret, 10);
6173
6174 dev_priv->ips.last_count1 = total_count;
6175 dev_priv->ips.last_time1 = now;
6176
6177 dev_priv->ips.chipset_power = ret;
6178
6179 return ret;
6180 }
6181
6182 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6183 {
6184 unsigned long val;
6185
6186 if (INTEL_INFO(dev_priv)->gen != 5)
6187 return 0;
6188
6189 spin_lock_irq(&mchdev_lock);
6190
6191 val = __i915_chipset_val(dev_priv);
6192
6193 spin_unlock_irq(&mchdev_lock);
6194
6195 return val;
6196 }
6197
6198 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6199 {
6200 unsigned long m, x, b;
6201 u32 tsfs;
6202
6203 tsfs = I915_READ(TSFS);
6204
6205 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6206 x = I915_READ8(TR1);
6207
6208 b = tsfs & TSFS_INTR_MASK;
6209
6210 return ((m * x) / 127) - b;
6211 }
6212
6213 static int _pxvid_to_vd(u8 pxvid)
6214 {
6215 if (pxvid == 0)
6216 return 0;
6217
6218 if (pxvid >= 8 && pxvid < 31)
6219 pxvid = 31;
6220
6221 return (pxvid + 2) * 125;
6222 }
6223
6224 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6225 {
6226 const int vd = _pxvid_to_vd(pxvid);
6227 const int vm = vd - 1125;
6228
6229 if (INTEL_INFO(dev_priv)->is_mobile)
6230 return vm > 0 ? vm : 0;
6231
6232 return vd;
6233 }
6234
6235 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6236 {
6237 u64 now, diff, diffms;
6238 u32 count;
6239
6240 assert_spin_locked(&mchdev_lock);
6241
6242 now = ktime_get_raw_ns();
6243 diffms = now - dev_priv->ips.last_time2;
6244 do_div(diffms, NSEC_PER_MSEC);
6245
6246 /* Don't divide by 0 */
6247 if (!diffms)
6248 return;
6249
6250 count = I915_READ(GFXEC);
6251
6252 if (count < dev_priv->ips.last_count2) {
6253 diff = ~0UL - dev_priv->ips.last_count2;
6254 diff += count;
6255 } else {
6256 diff = count - dev_priv->ips.last_count2;
6257 }
6258
6259 dev_priv->ips.last_count2 = count;
6260 dev_priv->ips.last_time2 = now;
6261
6262 /* More magic constants... */
6263 diff = diff * 1181;
6264 diff = div_u64(diff, diffms * 10);
6265 dev_priv->ips.gfx_power = diff;
6266 }
6267
6268 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6269 {
6270 if (INTEL_INFO(dev_priv)->gen != 5)
6271 return;
6272
6273 spin_lock_irq(&mchdev_lock);
6274
6275 __i915_update_gfx_val(dev_priv);
6276
6277 spin_unlock_irq(&mchdev_lock);
6278 }
6279
6280 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6281 {
6282 unsigned long t, corr, state1, corr2, state2;
6283 u32 pxvid, ext_v;
6284
6285 assert_spin_locked(&mchdev_lock);
6286
6287 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6288 pxvid = (pxvid >> 24) & 0x7f;
6289 ext_v = pvid_to_extvid(dev_priv, pxvid);
6290
6291 state1 = ext_v;
6292
6293 t = i915_mch_val(dev_priv);
6294
6295 /* Revel in the empirically derived constants */
6296
6297 /* Correction factor in 1/100000 units */
6298 if (t > 80)
6299 corr = ((t * 2349) + 135940);
6300 else if (t >= 50)
6301 corr = ((t * 964) + 29317);
6302 else /* < 50 */
6303 corr = ((t * 301) + 1004);
6304
6305 corr = corr * ((150142 * state1) / 10000 - 78642);
6306 corr /= 100000;
6307 corr2 = (corr * dev_priv->ips.corr);
6308
6309 state2 = (corr2 * state1) / 10000;
6310 state2 /= 100; /* convert to mW */
6311
6312 __i915_update_gfx_val(dev_priv);
6313
6314 return dev_priv->ips.gfx_power + state2;
6315 }
6316
6317 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6318 {
6319 unsigned long val;
6320
6321 if (INTEL_INFO(dev_priv)->gen != 5)
6322 return 0;
6323
6324 spin_lock_irq(&mchdev_lock);
6325
6326 val = __i915_gfx_val(dev_priv);
6327
6328 spin_unlock_irq(&mchdev_lock);
6329
6330 return val;
6331 }
6332
6333 /**
6334 * i915_read_mch_val - return value for IPS use
6335 *
6336 * Calculate and return a value for the IPS driver to use when deciding whether
6337 * we have thermal and power headroom to increase CPU or GPU power budget.
6338 */
6339 unsigned long i915_read_mch_val(void)
6340 {
6341 struct drm_i915_private *dev_priv;
6342 unsigned long chipset_val, graphics_val, ret = 0;
6343
6344 spin_lock_irq(&mchdev_lock);
6345 if (!i915_mch_dev)
6346 goto out_unlock;
6347 dev_priv = i915_mch_dev;
6348
6349 chipset_val = __i915_chipset_val(dev_priv);
6350 graphics_val = __i915_gfx_val(dev_priv);
6351
6352 ret = chipset_val + graphics_val;
6353
6354 out_unlock:
6355 spin_unlock_irq(&mchdev_lock);
6356
6357 return ret;
6358 }
6359 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6360
6361 /**
6362 * i915_gpu_raise - raise GPU frequency limit
6363 *
6364 * Raise the limit; IPS indicates we have thermal headroom.
6365 */
6366 bool i915_gpu_raise(void)
6367 {
6368 struct drm_i915_private *dev_priv;
6369 bool ret = true;
6370
6371 spin_lock_irq(&mchdev_lock);
6372 if (!i915_mch_dev) {
6373 ret = false;
6374 goto out_unlock;
6375 }
6376 dev_priv = i915_mch_dev;
6377
6378 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6379 dev_priv->ips.max_delay--;
6380
6381 out_unlock:
6382 spin_unlock_irq(&mchdev_lock);
6383
6384 return ret;
6385 }
6386 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6387
6388 /**
6389 * i915_gpu_lower - lower GPU frequency limit
6390 *
6391 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6392 * frequency maximum.
6393 */
6394 bool i915_gpu_lower(void)
6395 {
6396 struct drm_i915_private *dev_priv;
6397 bool ret = true;
6398
6399 spin_lock_irq(&mchdev_lock);
6400 if (!i915_mch_dev) {
6401 ret = false;
6402 goto out_unlock;
6403 }
6404 dev_priv = i915_mch_dev;
6405
6406 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6407 dev_priv->ips.max_delay++;
6408
6409 out_unlock:
6410 spin_unlock_irq(&mchdev_lock);
6411
6412 return ret;
6413 }
6414 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6415
6416 /**
6417 * i915_gpu_busy - indicate GPU business to IPS
6418 *
6419 * Tell the IPS driver whether or not the GPU is busy.
6420 */
6421 bool i915_gpu_busy(void)
6422 {
6423 bool ret = false;
6424
6425 spin_lock_irq(&mchdev_lock);
6426 if (i915_mch_dev)
6427 ret = i915_mch_dev->gt.awake;
6428 spin_unlock_irq(&mchdev_lock);
6429
6430 return ret;
6431 }
6432 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6433
6434 /**
6435 * i915_gpu_turbo_disable - disable graphics turbo
6436 *
6437 * Disable graphics turbo by resetting the max frequency and setting the
6438 * current frequency to the default.
6439 */
6440 bool i915_gpu_turbo_disable(void)
6441 {
6442 struct drm_i915_private *dev_priv;
6443 bool ret = true;
6444
6445 spin_lock_irq(&mchdev_lock);
6446 if (!i915_mch_dev) {
6447 ret = false;
6448 goto out_unlock;
6449 }
6450 dev_priv = i915_mch_dev;
6451
6452 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6453
6454 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6455 ret = false;
6456
6457 out_unlock:
6458 spin_unlock_irq(&mchdev_lock);
6459
6460 return ret;
6461 }
6462 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6463
6464 /**
6465 * Tells the intel_ips driver that the i915 driver is now loaded, if
6466 * IPS got loaded first.
6467 *
6468 * This awkward dance is so that neither module has to depend on the
6469 * other in order for IPS to do the appropriate communication of
6470 * GPU turbo limits to i915.
6471 */
6472 static void
6473 ips_ping_for_i915_load(void)
6474 {
6475 void (*link)(void);
6476
6477 link = symbol_get(ips_link_to_i915_driver);
6478 if (link) {
6479 link();
6480 symbol_put(ips_link_to_i915_driver);
6481 }
6482 }
6483
6484 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6485 {
6486 /* We only register the i915 ips part with intel-ips once everything is
6487 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6488 spin_lock_irq(&mchdev_lock);
6489 i915_mch_dev = dev_priv;
6490 spin_unlock_irq(&mchdev_lock);
6491
6492 ips_ping_for_i915_load();
6493 }
6494
6495 void intel_gpu_ips_teardown(void)
6496 {
6497 spin_lock_irq(&mchdev_lock);
6498 i915_mch_dev = NULL;
6499 spin_unlock_irq(&mchdev_lock);
6500 }
6501
6502 static void intel_init_emon(struct drm_i915_private *dev_priv)
6503 {
6504 u32 lcfuse;
6505 u8 pxw[16];
6506 int i;
6507
6508 /* Disable to program */
6509 I915_WRITE(ECR, 0);
6510 POSTING_READ(ECR);
6511
6512 /* Program energy weights for various events */
6513 I915_WRITE(SDEW, 0x15040d00);
6514 I915_WRITE(CSIEW0, 0x007f0000);
6515 I915_WRITE(CSIEW1, 0x1e220004);
6516 I915_WRITE(CSIEW2, 0x04000004);
6517
6518 for (i = 0; i < 5; i++)
6519 I915_WRITE(PEW(i), 0);
6520 for (i = 0; i < 3; i++)
6521 I915_WRITE(DEW(i), 0);
6522
6523 /* Program P-state weights to account for frequency power adjustment */
6524 for (i = 0; i < 16; i++) {
6525 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6526 unsigned long freq = intel_pxfreq(pxvidfreq);
6527 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6528 PXVFREQ_PX_SHIFT;
6529 unsigned long val;
6530
6531 val = vid * vid;
6532 val *= (freq / 1000);
6533 val *= 255;
6534 val /= (127*127*900);
6535 if (val > 0xff)
6536 DRM_ERROR("bad pxval: %ld\n", val);
6537 pxw[i] = val;
6538 }
6539 /* Render standby states get 0 weight */
6540 pxw[14] = 0;
6541 pxw[15] = 0;
6542
6543 for (i = 0; i < 4; i++) {
6544 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6545 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6546 I915_WRITE(PXW(i), val);
6547 }
6548
6549 /* Adjust magic regs to magic values (more experimental results) */
6550 I915_WRITE(OGW0, 0);
6551 I915_WRITE(OGW1, 0);
6552 I915_WRITE(EG0, 0x00007f00);
6553 I915_WRITE(EG1, 0x0000000e);
6554 I915_WRITE(EG2, 0x000e0000);
6555 I915_WRITE(EG3, 0x68000300);
6556 I915_WRITE(EG4, 0x42000000);
6557 I915_WRITE(EG5, 0x00140031);
6558 I915_WRITE(EG6, 0);
6559 I915_WRITE(EG7, 0);
6560
6561 for (i = 0; i < 8; i++)
6562 I915_WRITE(PXWL(i), 0);
6563
6564 /* Enable PMON + select events */
6565 I915_WRITE(ECR, 0x80000019);
6566
6567 lcfuse = I915_READ(LCFUSE02);
6568
6569 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6570 }
6571
6572 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6573 {
6574 /*
6575 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6576 * requirement.
6577 */
6578 if (!i915.enable_rc6) {
6579 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6580 intel_runtime_pm_get(dev_priv);
6581 }
6582
6583 mutex_lock(&dev_priv->drm.struct_mutex);
6584 mutex_lock(&dev_priv->rps.hw_lock);
6585
6586 /* Initialize RPS limits (for userspace) */
6587 if (IS_CHERRYVIEW(dev_priv))
6588 cherryview_init_gt_powersave(dev_priv);
6589 else if (IS_VALLEYVIEW(dev_priv))
6590 valleyview_init_gt_powersave(dev_priv);
6591 else if (INTEL_GEN(dev_priv) >= 6)
6592 gen6_init_rps_frequencies(dev_priv);
6593
6594 /* Derive initial user preferences/limits from the hardware limits */
6595 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6596 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6597
6598 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6599 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6600
6601 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6602 dev_priv->rps.min_freq_softlimit =
6603 max_t(int,
6604 dev_priv->rps.efficient_freq,
6605 intel_freq_opcode(dev_priv, 450));
6606
6607 /* After setting max-softlimit, find the overclock max freq */
6608 if (IS_GEN6(dev_priv) ||
6609 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6610 u32 params = 0;
6611
6612 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6613 if (params & BIT(31)) { /* OC supported */
6614 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6615 (dev_priv->rps.max_freq & 0xff) * 50,
6616 (params & 0xff) * 50);
6617 dev_priv->rps.max_freq = params & 0xff;
6618 }
6619 }
6620
6621 /* Finally allow us to boost to max by default */
6622 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6623
6624 mutex_unlock(&dev_priv->rps.hw_lock);
6625 mutex_unlock(&dev_priv->drm.struct_mutex);
6626
6627 intel_autoenable_gt_powersave(dev_priv);
6628 }
6629
6630 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6631 {
6632 if (IS_VALLEYVIEW(dev_priv))
6633 valleyview_cleanup_gt_powersave(dev_priv);
6634
6635 if (!i915.enable_rc6)
6636 intel_runtime_pm_put(dev_priv);
6637 }
6638
6639 /**
6640 * intel_suspend_gt_powersave - suspend PM work and helper threads
6641 * @dev_priv: i915 device
6642 *
6643 * We don't want to disable RC6 or other features here, we just want
6644 * to make sure any work we've queued has finished and won't bother
6645 * us while we're suspended.
6646 */
6647 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6648 {
6649 if (INTEL_GEN(dev_priv) < 6)
6650 return;
6651
6652 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6653 intel_runtime_pm_put(dev_priv);
6654
6655 /* gen6_rps_idle() will be called later to disable interrupts */
6656 }
6657
6658 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6659 {
6660 dev_priv->rps.enabled = true; /* force disabling */
6661 intel_disable_gt_powersave(dev_priv);
6662
6663 gen6_reset_rps_interrupts(dev_priv);
6664 }
6665
6666 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6667 {
6668 if (!READ_ONCE(dev_priv->rps.enabled))
6669 return;
6670
6671 mutex_lock(&dev_priv->rps.hw_lock);
6672
6673 if (INTEL_GEN(dev_priv) >= 9) {
6674 gen9_disable_rc6(dev_priv);
6675 gen9_disable_rps(dev_priv);
6676 } else if (IS_CHERRYVIEW(dev_priv)) {
6677 cherryview_disable_rps(dev_priv);
6678 } else if (IS_VALLEYVIEW(dev_priv)) {
6679 valleyview_disable_rps(dev_priv);
6680 } else if (INTEL_GEN(dev_priv) >= 6) {
6681 gen6_disable_rps(dev_priv);
6682 } else if (IS_IRONLAKE_M(dev_priv)) {
6683 ironlake_disable_drps(dev_priv);
6684 }
6685
6686 dev_priv->rps.enabled = false;
6687 mutex_unlock(&dev_priv->rps.hw_lock);
6688 }
6689
6690 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6691 {
6692 /* We shouldn't be disabling as we submit, so this should be less
6693 * racy than it appears!
6694 */
6695 if (READ_ONCE(dev_priv->rps.enabled))
6696 return;
6697
6698 /* Powersaving is controlled by the host when inside a VM */
6699 if (intel_vgpu_active(dev_priv))
6700 return;
6701
6702 mutex_lock(&dev_priv->rps.hw_lock);
6703
6704 if (IS_CHERRYVIEW(dev_priv)) {
6705 cherryview_enable_rps(dev_priv);
6706 } else if (IS_VALLEYVIEW(dev_priv)) {
6707 valleyview_enable_rps(dev_priv);
6708 } else if (INTEL_GEN(dev_priv) >= 9) {
6709 gen9_enable_rc6(dev_priv);
6710 gen9_enable_rps(dev_priv);
6711 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6712 gen6_update_ring_freq(dev_priv);
6713 } else if (IS_BROADWELL(dev_priv)) {
6714 gen8_enable_rps(dev_priv);
6715 gen6_update_ring_freq(dev_priv);
6716 } else if (INTEL_GEN(dev_priv) >= 6) {
6717 gen6_enable_rps(dev_priv);
6718 gen6_update_ring_freq(dev_priv);
6719 } else if (IS_IRONLAKE_M(dev_priv)) {
6720 ironlake_enable_drps(dev_priv);
6721 intel_init_emon(dev_priv);
6722 }
6723
6724 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6725 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6726
6727 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6728 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6729
6730 dev_priv->rps.enabled = true;
6731 mutex_unlock(&dev_priv->rps.hw_lock);
6732 }
6733
6734 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6735 {
6736 struct drm_i915_private *dev_priv =
6737 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6738 struct intel_engine_cs *rcs;
6739 struct drm_i915_gem_request *req;
6740
6741 if (READ_ONCE(dev_priv->rps.enabled))
6742 goto out;
6743
6744 rcs = &dev_priv->engine[RCS];
6745 if (rcs->last_context)
6746 goto out;
6747
6748 if (!rcs->init_context)
6749 goto out;
6750
6751 mutex_lock(&dev_priv->drm.struct_mutex);
6752
6753 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6754 if (IS_ERR(req))
6755 goto unlock;
6756
6757 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6758 rcs->init_context(req);
6759
6760 /* Mark the device busy, calling intel_enable_gt_powersave() */
6761 i915_add_request_no_flush(req);
6762
6763 unlock:
6764 mutex_unlock(&dev_priv->drm.struct_mutex);
6765 out:
6766 intel_runtime_pm_put(dev_priv);
6767 }
6768
6769 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6770 {
6771 if (READ_ONCE(dev_priv->rps.enabled))
6772 return;
6773
6774 if (IS_IRONLAKE_M(dev_priv)) {
6775 ironlake_enable_drps(dev_priv);
6776 intel_init_emon(dev_priv);
6777 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6778 /*
6779 * PCU communication is slow and this doesn't need to be
6780 * done at any specific time, so do this out of our fast path
6781 * to make resume and init faster.
6782 *
6783 * We depend on the HW RC6 power context save/restore
6784 * mechanism when entering D3 through runtime PM suspend. So
6785 * disable RPM until RPS/RC6 is properly setup. We can only
6786 * get here via the driver load/system resume/runtime resume
6787 * paths, so the _noresume version is enough (and in case of
6788 * runtime resume it's necessary).
6789 */
6790 if (queue_delayed_work(dev_priv->wq,
6791 &dev_priv->rps.autoenable_work,
6792 round_jiffies_up_relative(HZ)))
6793 intel_runtime_pm_get_noresume(dev_priv);
6794 }
6795 }
6796
6797 static void ibx_init_clock_gating(struct drm_device *dev)
6798 {
6799 struct drm_i915_private *dev_priv = to_i915(dev);
6800
6801 /*
6802 * On Ibex Peak and Cougar Point, we need to disable clock
6803 * gating for the panel power sequencer or it will fail to
6804 * start up when no ports are active.
6805 */
6806 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6807 }
6808
6809 static void g4x_disable_trickle_feed(struct drm_device *dev)
6810 {
6811 struct drm_i915_private *dev_priv = to_i915(dev);
6812 enum pipe pipe;
6813
6814 for_each_pipe(dev_priv, pipe) {
6815 I915_WRITE(DSPCNTR(pipe),
6816 I915_READ(DSPCNTR(pipe)) |
6817 DISPPLANE_TRICKLE_FEED_DISABLE);
6818
6819 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6820 POSTING_READ(DSPSURF(pipe));
6821 }
6822 }
6823
6824 static void ilk_init_lp_watermarks(struct drm_device *dev)
6825 {
6826 struct drm_i915_private *dev_priv = to_i915(dev);
6827
6828 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6829 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6830 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6831
6832 /*
6833 * Don't touch WM1S_LP_EN here.
6834 * Doing so could cause underruns.
6835 */
6836 }
6837
6838 static void ironlake_init_clock_gating(struct drm_device *dev)
6839 {
6840 struct drm_i915_private *dev_priv = to_i915(dev);
6841 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6842
6843 /*
6844 * Required for FBC
6845 * WaFbcDisableDpfcClockGating:ilk
6846 */
6847 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6848 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6849 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6850
6851 I915_WRITE(PCH_3DCGDIS0,
6852 MARIUNIT_CLOCK_GATE_DISABLE |
6853 SVSMUNIT_CLOCK_GATE_DISABLE);
6854 I915_WRITE(PCH_3DCGDIS1,
6855 VFMUNIT_CLOCK_GATE_DISABLE);
6856
6857 /*
6858 * According to the spec the following bits should be set in
6859 * order to enable memory self-refresh
6860 * The bit 22/21 of 0x42004
6861 * The bit 5 of 0x42020
6862 * The bit 15 of 0x45000
6863 */
6864 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6865 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6866 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6867 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6868 I915_WRITE(DISP_ARB_CTL,
6869 (I915_READ(DISP_ARB_CTL) |
6870 DISP_FBC_WM_DIS));
6871
6872 ilk_init_lp_watermarks(dev);
6873
6874 /*
6875 * Based on the document from hardware guys the following bits
6876 * should be set unconditionally in order to enable FBC.
6877 * The bit 22 of 0x42000
6878 * The bit 22 of 0x42004
6879 * The bit 7,8,9 of 0x42020.
6880 */
6881 if (IS_IRONLAKE_M(dev)) {
6882 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6883 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6884 I915_READ(ILK_DISPLAY_CHICKEN1) |
6885 ILK_FBCQ_DIS);
6886 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6887 I915_READ(ILK_DISPLAY_CHICKEN2) |
6888 ILK_DPARB_GATE);
6889 }
6890
6891 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6892
6893 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6894 I915_READ(ILK_DISPLAY_CHICKEN2) |
6895 ILK_ELPIN_409_SELECT);
6896 I915_WRITE(_3D_CHICKEN2,
6897 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6898 _3D_CHICKEN2_WM_READ_PIPELINED);
6899
6900 /* WaDisableRenderCachePipelinedFlush:ilk */
6901 I915_WRITE(CACHE_MODE_0,
6902 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6903
6904 /* WaDisable_RenderCache_OperationalFlush:ilk */
6905 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6906
6907 g4x_disable_trickle_feed(dev);
6908
6909 ibx_init_clock_gating(dev);
6910 }
6911
6912 static void cpt_init_clock_gating(struct drm_device *dev)
6913 {
6914 struct drm_i915_private *dev_priv = to_i915(dev);
6915 int pipe;
6916 uint32_t val;
6917
6918 /*
6919 * On Ibex Peak and Cougar Point, we need to disable clock
6920 * gating for the panel power sequencer or it will fail to
6921 * start up when no ports are active.
6922 */
6923 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6924 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6925 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6926 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6927 DPLS_EDP_PPS_FIX_DIS);
6928 /* The below fixes the weird display corruption, a few pixels shifted
6929 * downward, on (only) LVDS of some HP laptops with IVY.
6930 */
6931 for_each_pipe(dev_priv, pipe) {
6932 val = I915_READ(TRANS_CHICKEN2(pipe));
6933 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6934 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6935 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6936 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6937 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6938 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6939 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6940 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6941 }
6942 /* WADP0ClockGatingDisable */
6943 for_each_pipe(dev_priv, pipe) {
6944 I915_WRITE(TRANS_CHICKEN1(pipe),
6945 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6946 }
6947 }
6948
6949 static void gen6_check_mch_setup(struct drm_device *dev)
6950 {
6951 struct drm_i915_private *dev_priv = to_i915(dev);
6952 uint32_t tmp;
6953
6954 tmp = I915_READ(MCH_SSKPD);
6955 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6956 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6957 tmp);
6958 }
6959
6960 static void gen6_init_clock_gating(struct drm_device *dev)
6961 {
6962 struct drm_i915_private *dev_priv = to_i915(dev);
6963 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6964
6965 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6966
6967 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6968 I915_READ(ILK_DISPLAY_CHICKEN2) |
6969 ILK_ELPIN_409_SELECT);
6970
6971 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6972 I915_WRITE(_3D_CHICKEN,
6973 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6974
6975 /* WaDisable_RenderCache_OperationalFlush:snb */
6976 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6977
6978 /*
6979 * BSpec recoomends 8x4 when MSAA is used,
6980 * however in practice 16x4 seems fastest.
6981 *
6982 * Note that PS/WM thread counts depend on the WIZ hashing
6983 * disable bit, which we don't touch here, but it's good
6984 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6985 */
6986 I915_WRITE(GEN6_GT_MODE,
6987 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6988
6989 ilk_init_lp_watermarks(dev);
6990
6991 I915_WRITE(CACHE_MODE_0,
6992 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6993
6994 I915_WRITE(GEN6_UCGCTL1,
6995 I915_READ(GEN6_UCGCTL1) |
6996 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6997 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6998
6999 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7000 * gating disable must be set. Failure to set it results in
7001 * flickering pixels due to Z write ordering failures after
7002 * some amount of runtime in the Mesa "fire" demo, and Unigine
7003 * Sanctuary and Tropics, and apparently anything else with
7004 * alpha test or pixel discard.
7005 *
7006 * According to the spec, bit 11 (RCCUNIT) must also be set,
7007 * but we didn't debug actual testcases to find it out.
7008 *
7009 * WaDisableRCCUnitClockGating:snb
7010 * WaDisableRCPBUnitClockGating:snb
7011 */
7012 I915_WRITE(GEN6_UCGCTL2,
7013 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7014 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7015
7016 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7017 I915_WRITE(_3D_CHICKEN3,
7018 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7019
7020 /*
7021 * Bspec says:
7022 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7023 * 3DSTATE_SF number of SF output attributes is more than 16."
7024 */
7025 I915_WRITE(_3D_CHICKEN3,
7026 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7027
7028 /*
7029 * According to the spec the following bits should be
7030 * set in order to enable memory self-refresh and fbc:
7031 * The bit21 and bit22 of 0x42000
7032 * The bit21 and bit22 of 0x42004
7033 * The bit5 and bit7 of 0x42020
7034 * The bit14 of 0x70180
7035 * The bit14 of 0x71180
7036 *
7037 * WaFbcAsynchFlipDisableFbcQueue:snb
7038 */
7039 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7040 I915_READ(ILK_DISPLAY_CHICKEN1) |
7041 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7042 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7043 I915_READ(ILK_DISPLAY_CHICKEN2) |
7044 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7045 I915_WRITE(ILK_DSPCLK_GATE_D,
7046 I915_READ(ILK_DSPCLK_GATE_D) |
7047 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7048 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7049
7050 g4x_disable_trickle_feed(dev);
7051
7052 cpt_init_clock_gating(dev);
7053
7054 gen6_check_mch_setup(dev);
7055 }
7056
7057 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7058 {
7059 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7060
7061 /*
7062 * WaVSThreadDispatchOverride:ivb,vlv
7063 *
7064 * This actually overrides the dispatch
7065 * mode for all thread types.
7066 */
7067 reg &= ~GEN7_FF_SCHED_MASK;
7068 reg |= GEN7_FF_TS_SCHED_HW;
7069 reg |= GEN7_FF_VS_SCHED_HW;
7070 reg |= GEN7_FF_DS_SCHED_HW;
7071
7072 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7073 }
7074
7075 static void lpt_init_clock_gating(struct drm_device *dev)
7076 {
7077 struct drm_i915_private *dev_priv = to_i915(dev);
7078
7079 /*
7080 * TODO: this bit should only be enabled when really needed, then
7081 * disabled when not needed anymore in order to save power.
7082 */
7083 if (HAS_PCH_LPT_LP(dev))
7084 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7085 I915_READ(SOUTH_DSPCLK_GATE_D) |
7086 PCH_LP_PARTITION_LEVEL_DISABLE);
7087
7088 /* WADPOClockGatingDisable:hsw */
7089 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7090 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7091 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7092 }
7093
7094 static void lpt_suspend_hw(struct drm_device *dev)
7095 {
7096 struct drm_i915_private *dev_priv = to_i915(dev);
7097
7098 if (HAS_PCH_LPT_LP(dev)) {
7099 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7100
7101 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7102 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7103 }
7104 }
7105
7106 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7107 int general_prio_credits,
7108 int high_prio_credits)
7109 {
7110 u32 misccpctl;
7111
7112 /* WaTempDisableDOPClkGating:bdw */
7113 misccpctl = I915_READ(GEN7_MISCCPCTL);
7114 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7115
7116 I915_WRITE(GEN8_L3SQCREG1,
7117 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7118 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7119
7120 /*
7121 * Wait at least 100 clocks before re-enabling clock gating.
7122 * See the definition of L3SQCREG1 in BSpec.
7123 */
7124 POSTING_READ(GEN8_L3SQCREG1);
7125 udelay(1);
7126 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7127 }
7128
7129 static void kabylake_init_clock_gating(struct drm_device *dev)
7130 {
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132
7133 gen9_init_clock_gating(dev);
7134
7135 /* WaDisableSDEUnitClockGating:kbl */
7136 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7137 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7138 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7139
7140 /* WaDisableGamClockGating:kbl */
7141 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7142 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7143 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7144
7145 /* WaFbcNukeOnHostModify:kbl */
7146 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7147 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7148 }
7149
7150 static void skylake_init_clock_gating(struct drm_device *dev)
7151 {
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153
7154 gen9_init_clock_gating(dev);
7155
7156 /* WAC6entrylatency:skl */
7157 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7158 FBC_LLC_FULLY_OPEN);
7159
7160 /* WaFbcNukeOnHostModify:skl */
7161 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7162 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7163 }
7164
7165 static void broadwell_init_clock_gating(struct drm_device *dev)
7166 {
7167 struct drm_i915_private *dev_priv = to_i915(dev);
7168 enum pipe pipe;
7169
7170 ilk_init_lp_watermarks(dev);
7171
7172 /* WaSwitchSolVfFArbitrationPriority:bdw */
7173 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7174
7175 /* WaPsrDPAMaskVBlankInSRD:bdw */
7176 I915_WRITE(CHICKEN_PAR1_1,
7177 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7178
7179 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7180 for_each_pipe(dev_priv, pipe) {
7181 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7182 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7183 BDW_DPRS_MASK_VBLANK_SRD);
7184 }
7185
7186 /* WaVSRefCountFullforceMissDisable:bdw */
7187 /* WaDSRefCountFullforceMissDisable:bdw */
7188 I915_WRITE(GEN7_FF_THREAD_MODE,
7189 I915_READ(GEN7_FF_THREAD_MODE) &
7190 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7191
7192 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7193 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7194
7195 /* WaDisableSDEUnitClockGating:bdw */
7196 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7197 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7198
7199 /* WaProgramL3SqcReg1Default:bdw */
7200 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7201
7202 /*
7203 * WaGttCachingOffByDefault:bdw
7204 * GTT cache may not work with big pages, so if those
7205 * are ever enabled GTT cache may need to be disabled.
7206 */
7207 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7208
7209 /* WaKVMNotificationOnConfigChange:bdw */
7210 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7211 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7212
7213 lpt_init_clock_gating(dev);
7214 }
7215
7216 static void haswell_init_clock_gating(struct drm_device *dev)
7217 {
7218 struct drm_i915_private *dev_priv = to_i915(dev);
7219
7220 ilk_init_lp_watermarks(dev);
7221
7222 /* L3 caching of data atomics doesn't work -- disable it. */
7223 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7224 I915_WRITE(HSW_ROW_CHICKEN3,
7225 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7226
7227 /* This is required by WaCatErrorRejectionIssue:hsw */
7228 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7229 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7230 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7231
7232 /* WaVSRefCountFullforceMissDisable:hsw */
7233 I915_WRITE(GEN7_FF_THREAD_MODE,
7234 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7235
7236 /* WaDisable_RenderCache_OperationalFlush:hsw */
7237 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7238
7239 /* enable HiZ Raw Stall Optimization */
7240 I915_WRITE(CACHE_MODE_0_GEN7,
7241 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7242
7243 /* WaDisable4x2SubspanOptimization:hsw */
7244 I915_WRITE(CACHE_MODE_1,
7245 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7246
7247 /*
7248 * BSpec recommends 8x4 when MSAA is used,
7249 * however in practice 16x4 seems fastest.
7250 *
7251 * Note that PS/WM thread counts depend on the WIZ hashing
7252 * disable bit, which we don't touch here, but it's good
7253 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7254 */
7255 I915_WRITE(GEN7_GT_MODE,
7256 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7257
7258 /* WaSampleCChickenBitEnable:hsw */
7259 I915_WRITE(HALF_SLICE_CHICKEN3,
7260 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7261
7262 /* WaSwitchSolVfFArbitrationPriority:hsw */
7263 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7264
7265 /* WaRsPkgCStateDisplayPMReq:hsw */
7266 I915_WRITE(CHICKEN_PAR1_1,
7267 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7268
7269 lpt_init_clock_gating(dev);
7270 }
7271
7272 static void ivybridge_init_clock_gating(struct drm_device *dev)
7273 {
7274 struct drm_i915_private *dev_priv = to_i915(dev);
7275 uint32_t snpcr;
7276
7277 ilk_init_lp_watermarks(dev);
7278
7279 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7280
7281 /* WaDisableEarlyCull:ivb */
7282 I915_WRITE(_3D_CHICKEN3,
7283 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7284
7285 /* WaDisableBackToBackFlipFix:ivb */
7286 I915_WRITE(IVB_CHICKEN3,
7287 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7288 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7289
7290 /* WaDisablePSDDualDispatchEnable:ivb */
7291 if (IS_IVB_GT1(dev))
7292 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7293 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7294
7295 /* WaDisable_RenderCache_OperationalFlush:ivb */
7296 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7297
7298 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7299 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7300 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7301
7302 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7303 I915_WRITE(GEN7_L3CNTLREG1,
7304 GEN7_WA_FOR_GEN7_L3_CONTROL);
7305 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7306 GEN7_WA_L3_CHICKEN_MODE);
7307 if (IS_IVB_GT1(dev))
7308 I915_WRITE(GEN7_ROW_CHICKEN2,
7309 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7310 else {
7311 /* must write both registers */
7312 I915_WRITE(GEN7_ROW_CHICKEN2,
7313 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7314 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7315 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7316 }
7317
7318 /* WaForceL3Serialization:ivb */
7319 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7320 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7321
7322 /*
7323 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7324 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7325 */
7326 I915_WRITE(GEN6_UCGCTL2,
7327 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7328
7329 /* This is required by WaCatErrorRejectionIssue:ivb */
7330 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7331 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7332 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7333
7334 g4x_disable_trickle_feed(dev);
7335
7336 gen7_setup_fixed_func_scheduler(dev_priv);
7337
7338 if (0) { /* causes HiZ corruption on ivb:gt1 */
7339 /* enable HiZ Raw Stall Optimization */
7340 I915_WRITE(CACHE_MODE_0_GEN7,
7341 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7342 }
7343
7344 /* WaDisable4x2SubspanOptimization:ivb */
7345 I915_WRITE(CACHE_MODE_1,
7346 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7347
7348 /*
7349 * BSpec recommends 8x4 when MSAA is used,
7350 * however in practice 16x4 seems fastest.
7351 *
7352 * Note that PS/WM thread counts depend on the WIZ hashing
7353 * disable bit, which we don't touch here, but it's good
7354 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7355 */
7356 I915_WRITE(GEN7_GT_MODE,
7357 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7358
7359 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7360 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7361 snpcr |= GEN6_MBC_SNPCR_MED;
7362 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7363
7364 if (!HAS_PCH_NOP(dev))
7365 cpt_init_clock_gating(dev);
7366
7367 gen6_check_mch_setup(dev);
7368 }
7369
7370 static void valleyview_init_clock_gating(struct drm_device *dev)
7371 {
7372 struct drm_i915_private *dev_priv = to_i915(dev);
7373
7374 /* WaDisableEarlyCull:vlv */
7375 I915_WRITE(_3D_CHICKEN3,
7376 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7377
7378 /* WaDisableBackToBackFlipFix:vlv */
7379 I915_WRITE(IVB_CHICKEN3,
7380 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7381 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7382
7383 /* WaPsdDispatchEnable:vlv */
7384 /* WaDisablePSDDualDispatchEnable:vlv */
7385 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7386 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7387 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7388
7389 /* WaDisable_RenderCache_OperationalFlush:vlv */
7390 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7391
7392 /* WaForceL3Serialization:vlv */
7393 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7394 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7395
7396 /* WaDisableDopClockGating:vlv */
7397 I915_WRITE(GEN7_ROW_CHICKEN2,
7398 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7399
7400 /* This is required by WaCatErrorRejectionIssue:vlv */
7401 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7402 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7403 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7404
7405 gen7_setup_fixed_func_scheduler(dev_priv);
7406
7407 /*
7408 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7409 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7410 */
7411 I915_WRITE(GEN6_UCGCTL2,
7412 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7413
7414 /* WaDisableL3Bank2xClockGate:vlv
7415 * Disabling L3 clock gating- MMIO 940c[25] = 1
7416 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7417 I915_WRITE(GEN7_UCGCTL4,
7418 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7419
7420 /*
7421 * BSpec says this must be set, even though
7422 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7423 */
7424 I915_WRITE(CACHE_MODE_1,
7425 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7426
7427 /*
7428 * BSpec recommends 8x4 when MSAA is used,
7429 * however in practice 16x4 seems fastest.
7430 *
7431 * Note that PS/WM thread counts depend on the WIZ hashing
7432 * disable bit, which we don't touch here, but it's good
7433 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7434 */
7435 I915_WRITE(GEN7_GT_MODE,
7436 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7437
7438 /*
7439 * WaIncreaseL3CreditsForVLVB0:vlv
7440 * This is the hardware default actually.
7441 */
7442 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7443
7444 /*
7445 * WaDisableVLVClockGating_VBIIssue:vlv
7446 * Disable clock gating on th GCFG unit to prevent a delay
7447 * in the reporting of vblank events.
7448 */
7449 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7450 }
7451
7452 static void cherryview_init_clock_gating(struct drm_device *dev)
7453 {
7454 struct drm_i915_private *dev_priv = to_i915(dev);
7455
7456 /* WaVSRefCountFullforceMissDisable:chv */
7457 /* WaDSRefCountFullforceMissDisable:chv */
7458 I915_WRITE(GEN7_FF_THREAD_MODE,
7459 I915_READ(GEN7_FF_THREAD_MODE) &
7460 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7461
7462 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7463 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7464 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7465
7466 /* WaDisableCSUnitClockGating:chv */
7467 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7468 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7469
7470 /* WaDisableSDEUnitClockGating:chv */
7471 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7472 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7473
7474 /*
7475 * WaProgramL3SqcReg1Default:chv
7476 * See gfxspecs/Related Documents/Performance Guide/
7477 * LSQC Setting Recommendations.
7478 */
7479 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7480
7481 /*
7482 * GTT cache may not work with big pages, so if those
7483 * are ever enabled GTT cache may need to be disabled.
7484 */
7485 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7486 }
7487
7488 static void g4x_init_clock_gating(struct drm_device *dev)
7489 {
7490 struct drm_i915_private *dev_priv = to_i915(dev);
7491 uint32_t dspclk_gate;
7492
7493 I915_WRITE(RENCLK_GATE_D1, 0);
7494 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7495 GS_UNIT_CLOCK_GATE_DISABLE |
7496 CL_UNIT_CLOCK_GATE_DISABLE);
7497 I915_WRITE(RAMCLK_GATE_D, 0);
7498 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7499 OVRUNIT_CLOCK_GATE_DISABLE |
7500 OVCUNIT_CLOCK_GATE_DISABLE;
7501 if (IS_GM45(dev))
7502 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7503 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7504
7505 /* WaDisableRenderCachePipelinedFlush */
7506 I915_WRITE(CACHE_MODE_0,
7507 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7508
7509 /* WaDisable_RenderCache_OperationalFlush:g4x */
7510 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7511
7512 g4x_disable_trickle_feed(dev);
7513 }
7514
7515 static void crestline_init_clock_gating(struct drm_device *dev)
7516 {
7517 struct drm_i915_private *dev_priv = to_i915(dev);
7518
7519 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7520 I915_WRITE(RENCLK_GATE_D2, 0);
7521 I915_WRITE(DSPCLK_GATE_D, 0);
7522 I915_WRITE(RAMCLK_GATE_D, 0);
7523 I915_WRITE16(DEUC, 0);
7524 I915_WRITE(MI_ARB_STATE,
7525 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7526
7527 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7528 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7529 }
7530
7531 static void broadwater_init_clock_gating(struct drm_device *dev)
7532 {
7533 struct drm_i915_private *dev_priv = to_i915(dev);
7534
7535 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7536 I965_RCC_CLOCK_GATE_DISABLE |
7537 I965_RCPB_CLOCK_GATE_DISABLE |
7538 I965_ISC_CLOCK_GATE_DISABLE |
7539 I965_FBC_CLOCK_GATE_DISABLE);
7540 I915_WRITE(RENCLK_GATE_D2, 0);
7541 I915_WRITE(MI_ARB_STATE,
7542 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7543
7544 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7545 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7546 }
7547
7548 static void gen3_init_clock_gating(struct drm_device *dev)
7549 {
7550 struct drm_i915_private *dev_priv = to_i915(dev);
7551 u32 dstate = I915_READ(D_STATE);
7552
7553 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7554 DSTATE_DOT_CLOCK_GATING;
7555 I915_WRITE(D_STATE, dstate);
7556
7557 if (IS_PINEVIEW(dev))
7558 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7559
7560 /* IIR "flip pending" means done if this bit is set */
7561 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7562
7563 /* interrupts should cause a wake up from C3 */
7564 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7565
7566 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7567 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7568
7569 I915_WRITE(MI_ARB_STATE,
7570 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7571 }
7572
7573 static void i85x_init_clock_gating(struct drm_device *dev)
7574 {
7575 struct drm_i915_private *dev_priv = to_i915(dev);
7576
7577 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7578
7579 /* interrupts should cause a wake up from C3 */
7580 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7581 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7582
7583 I915_WRITE(MEM_MODE,
7584 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7585 }
7586
7587 static void i830_init_clock_gating(struct drm_device *dev)
7588 {
7589 struct drm_i915_private *dev_priv = to_i915(dev);
7590
7591 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7592
7593 I915_WRITE(MEM_MODE,
7594 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7595 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7596 }
7597
7598 void intel_init_clock_gating(struct drm_device *dev)
7599 {
7600 struct drm_i915_private *dev_priv = to_i915(dev);
7601
7602 dev_priv->display.init_clock_gating(dev);
7603 }
7604
7605 void intel_suspend_hw(struct drm_device *dev)
7606 {
7607 if (HAS_PCH_LPT(dev))
7608 lpt_suspend_hw(dev);
7609 }
7610
7611 static void nop_init_clock_gating(struct drm_device *dev)
7612 {
7613 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7614 }
7615
7616 /**
7617 * intel_init_clock_gating_hooks - setup the clock gating hooks
7618 * @dev_priv: device private
7619 *
7620 * Setup the hooks that configure which clocks of a given platform can be
7621 * gated and also apply various GT and display specific workarounds for these
7622 * platforms. Note that some GT specific workarounds are applied separately
7623 * when GPU contexts or batchbuffers start their execution.
7624 */
7625 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7626 {
7627 if (IS_SKYLAKE(dev_priv))
7628 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7629 else if (IS_KABYLAKE(dev_priv))
7630 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7631 else if (IS_BROXTON(dev_priv))
7632 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7633 else if (IS_BROADWELL(dev_priv))
7634 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7635 else if (IS_CHERRYVIEW(dev_priv))
7636 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7637 else if (IS_HASWELL(dev_priv))
7638 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7639 else if (IS_IVYBRIDGE(dev_priv))
7640 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7641 else if (IS_VALLEYVIEW(dev_priv))
7642 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7643 else if (IS_GEN6(dev_priv))
7644 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7645 else if (IS_GEN5(dev_priv))
7646 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7647 else if (IS_G4X(dev_priv))
7648 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7649 else if (IS_CRESTLINE(dev_priv))
7650 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7651 else if (IS_BROADWATER(dev_priv))
7652 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7653 else if (IS_GEN3(dev_priv))
7654 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7655 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7656 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7657 else if (IS_GEN2(dev_priv))
7658 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7659 else {
7660 MISSING_CASE(INTEL_DEVID(dev_priv));
7661 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7662 }
7663 }
7664
7665 /* Set up chip specific power management-related functions */
7666 void intel_init_pm(struct drm_device *dev)
7667 {
7668 struct drm_i915_private *dev_priv = to_i915(dev);
7669
7670 intel_fbc_init(dev_priv);
7671
7672 /* For cxsr */
7673 if (IS_PINEVIEW(dev))
7674 i915_pineview_get_mem_freq(dev);
7675 else if (IS_GEN5(dev))
7676 i915_ironlake_get_mem_freq(dev);
7677
7678 /* For FIFO watermark updates */
7679 if (INTEL_INFO(dev)->gen >= 9) {
7680 skl_setup_wm_latency(dev);
7681 dev_priv->display.update_wm = skl_update_wm;
7682 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7683 } else if (HAS_PCH_SPLIT(dev)) {
7684 ilk_setup_wm_latency(dev);
7685
7686 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7687 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7688 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7689 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7690 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7691 dev_priv->display.compute_intermediate_wm =
7692 ilk_compute_intermediate_wm;
7693 dev_priv->display.initial_watermarks =
7694 ilk_initial_watermarks;
7695 dev_priv->display.optimize_watermarks =
7696 ilk_optimize_watermarks;
7697 } else {
7698 DRM_DEBUG_KMS("Failed to read display plane latency. "
7699 "Disable CxSR\n");
7700 }
7701 } else if (IS_CHERRYVIEW(dev)) {
7702 vlv_setup_wm_latency(dev);
7703 dev_priv->display.update_wm = vlv_update_wm;
7704 } else if (IS_VALLEYVIEW(dev)) {
7705 vlv_setup_wm_latency(dev);
7706 dev_priv->display.update_wm = vlv_update_wm;
7707 } else if (IS_PINEVIEW(dev)) {
7708 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7709 dev_priv->is_ddr3,
7710 dev_priv->fsb_freq,
7711 dev_priv->mem_freq)) {
7712 DRM_INFO("failed to find known CxSR latency "
7713 "(found ddr%s fsb freq %d, mem freq %d), "
7714 "disabling CxSR\n",
7715 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7716 dev_priv->fsb_freq, dev_priv->mem_freq);
7717 /* Disable CxSR and never update its watermark again */
7718 intel_set_memory_cxsr(dev_priv, false);
7719 dev_priv->display.update_wm = NULL;
7720 } else
7721 dev_priv->display.update_wm = pineview_update_wm;
7722 } else if (IS_G4X(dev)) {
7723 dev_priv->display.update_wm = g4x_update_wm;
7724 } else if (IS_GEN4(dev)) {
7725 dev_priv->display.update_wm = i965_update_wm;
7726 } else if (IS_GEN3(dev)) {
7727 dev_priv->display.update_wm = i9xx_update_wm;
7728 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7729 } else if (IS_GEN2(dev)) {
7730 if (INTEL_INFO(dev)->num_pipes == 1) {
7731 dev_priv->display.update_wm = i845_update_wm;
7732 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7733 } else {
7734 dev_priv->display.update_wm = i9xx_update_wm;
7735 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7736 }
7737 } else {
7738 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7739 }
7740 }
7741
7742 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7743 {
7744 uint32_t flags =
7745 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7746
7747 switch (flags) {
7748 case GEN6_PCODE_SUCCESS:
7749 return 0;
7750 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7751 case GEN6_PCODE_ILLEGAL_CMD:
7752 return -ENXIO;
7753 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7754 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7755 return -EOVERFLOW;
7756 case GEN6_PCODE_TIMEOUT:
7757 return -ETIMEDOUT;
7758 default:
7759 MISSING_CASE(flags)
7760 return 0;
7761 }
7762 }
7763
7764 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7765 {
7766 uint32_t flags =
7767 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7768
7769 switch (flags) {
7770 case GEN6_PCODE_SUCCESS:
7771 return 0;
7772 case GEN6_PCODE_ILLEGAL_CMD:
7773 return -ENXIO;
7774 case GEN7_PCODE_TIMEOUT:
7775 return -ETIMEDOUT;
7776 case GEN7_PCODE_ILLEGAL_DATA:
7777 return -EINVAL;
7778 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7779 return -EOVERFLOW;
7780 default:
7781 MISSING_CASE(flags);
7782 return 0;
7783 }
7784 }
7785
7786 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7787 {
7788 int status;
7789
7790 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7791
7792 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7793 * use te fw I915_READ variants to reduce the amount of work
7794 * required when reading/writing.
7795 */
7796
7797 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7798 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7799 return -EAGAIN;
7800 }
7801
7802 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7803 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7804 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7805
7806 if (intel_wait_for_register_fw(dev_priv,
7807 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7808 500)) {
7809 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7810 return -ETIMEDOUT;
7811 }
7812
7813 *val = I915_READ_FW(GEN6_PCODE_DATA);
7814 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7815
7816 if (INTEL_GEN(dev_priv) > 6)
7817 status = gen7_check_mailbox_status(dev_priv);
7818 else
7819 status = gen6_check_mailbox_status(dev_priv);
7820
7821 if (status) {
7822 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7823 status);
7824 return status;
7825 }
7826
7827 return 0;
7828 }
7829
7830 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7831 u32 mbox, u32 val)
7832 {
7833 int status;
7834
7835 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7836
7837 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7838 * use te fw I915_READ variants to reduce the amount of work
7839 * required when reading/writing.
7840 */
7841
7842 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7843 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7844 return -EAGAIN;
7845 }
7846
7847 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7848 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7849
7850 if (intel_wait_for_register_fw(dev_priv,
7851 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7852 500)) {
7853 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7854 return -ETIMEDOUT;
7855 }
7856
7857 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7858
7859 if (INTEL_GEN(dev_priv) > 6)
7860 status = gen7_check_mailbox_status(dev_priv);
7861 else
7862 status = gen6_check_mailbox_status(dev_priv);
7863
7864 if (status) {
7865 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7866 status);
7867 return status;
7868 }
7869
7870 return 0;
7871 }
7872
7873 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7874 {
7875 /*
7876 * N = val - 0xb7
7877 * Slow = Fast = GPLL ref * N
7878 */
7879 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7880 }
7881
7882 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7883 {
7884 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7885 }
7886
7887 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7888 {
7889 /*
7890 * N = val / 2
7891 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7892 */
7893 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7894 }
7895
7896 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7897 {
7898 /* CHV needs even values */
7899 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7900 }
7901
7902 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7903 {
7904 if (IS_GEN9(dev_priv))
7905 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7906 GEN9_FREQ_SCALER);
7907 else if (IS_CHERRYVIEW(dev_priv))
7908 return chv_gpu_freq(dev_priv, val);
7909 else if (IS_VALLEYVIEW(dev_priv))
7910 return byt_gpu_freq(dev_priv, val);
7911 else
7912 return val * GT_FREQUENCY_MULTIPLIER;
7913 }
7914
7915 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7916 {
7917 if (IS_GEN9(dev_priv))
7918 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7919 GT_FREQUENCY_MULTIPLIER);
7920 else if (IS_CHERRYVIEW(dev_priv))
7921 return chv_freq_opcode(dev_priv, val);
7922 else if (IS_VALLEYVIEW(dev_priv))
7923 return byt_freq_opcode(dev_priv, val);
7924 else
7925 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7926 }
7927
7928 struct request_boost {
7929 struct work_struct work;
7930 struct drm_i915_gem_request *req;
7931 };
7932
7933 static void __intel_rps_boost_work(struct work_struct *work)
7934 {
7935 struct request_boost *boost = container_of(work, struct request_boost, work);
7936 struct drm_i915_gem_request *req = boost->req;
7937
7938 if (!i915_gem_request_completed(req))
7939 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7940
7941 i915_gem_request_put(req);
7942 kfree(boost);
7943 }
7944
7945 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7946 {
7947 struct request_boost *boost;
7948
7949 if (req == NULL || INTEL_GEN(req->i915) < 6)
7950 return;
7951
7952 if (i915_gem_request_completed(req))
7953 return;
7954
7955 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7956 if (boost == NULL)
7957 return;
7958
7959 boost->req = i915_gem_request_get(req);
7960
7961 INIT_WORK(&boost->work, __intel_rps_boost_work);
7962 queue_work(req->i915->wq, &boost->work);
7963 }
7964
7965 void intel_pm_setup(struct drm_device *dev)
7966 {
7967 struct drm_i915_private *dev_priv = to_i915(dev);
7968
7969 mutex_init(&dev_priv->rps.hw_lock);
7970 spin_lock_init(&dev_priv->rps.client_lock);
7971
7972 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7973 __intel_autoenable_gt_powersave);
7974 INIT_LIST_HEAD(&dev_priv->rps.clients);
7975
7976 dev_priv->pm.suspended = false;
7977 atomic_set(&dev_priv->pm.wakeref_count, 0);
7978 atomic_set(&dev_priv->pm.atomic_seq, 0);
7979 }
Linux kernel - Deliverables
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