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drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40 #define LEGACY_REQUEST_SIZE 200
41
42 int __intel_ring_space(int head, int tail, int size)
43 {
44 int space = head - tail;
45 if (space <= 0)
46 space += size;
47 return space - I915_RING_FREE_SPACE;
48 }
49
50 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
51 {
52 if (ringbuf->last_retired_head != -1) {
53 ringbuf->head = ringbuf->last_retired_head;
54 ringbuf->last_retired_head = -1;
55 }
56
57 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
58 ringbuf->tail, ringbuf->size);
59 }
60
61 bool intel_engine_stopped(struct intel_engine_cs *engine)
62 {
63 struct drm_i915_private *dev_priv = engine->i915;
64 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
65 }
66
67 static void __intel_ring_advance(struct intel_engine_cs *engine)
68 {
69 struct intel_ringbuffer *ringbuf = engine->buffer;
70 ringbuf->tail &= ringbuf->size - 1;
71 if (intel_engine_stopped(engine))
72 return;
73 engine->write_tail(engine, ringbuf->tail);
74 }
75
76 static int
77 gen2_render_ring_flush(struct drm_i915_gem_request *req,
78 u32 invalidate_domains,
79 u32 flush_domains)
80 {
81 struct intel_engine_cs *engine = req->engine;
82 u32 cmd;
83 int ret;
84
85 cmd = MI_FLUSH;
86 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
87 cmd |= MI_NO_WRITE_FLUSH;
88
89 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
90 cmd |= MI_READ_FLUSH;
91
92 ret = intel_ring_begin(req, 2);
93 if (ret)
94 return ret;
95
96 intel_ring_emit(engine, cmd);
97 intel_ring_emit(engine, MI_NOOP);
98 intel_ring_advance(engine);
99
100 return 0;
101 }
102
103 static int
104 gen4_render_ring_flush(struct drm_i915_gem_request *req,
105 u32 invalidate_domains,
106 u32 flush_domains)
107 {
108 struct intel_engine_cs *engine = req->engine;
109 u32 cmd;
110 int ret;
111
112 /*
113 * read/write caches:
114 *
115 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
116 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
117 * also flushed at 2d versus 3d pipeline switches.
118 *
119 * read-only caches:
120 *
121 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
122 * MI_READ_FLUSH is set, and is always flushed on 965.
123 *
124 * I915_GEM_DOMAIN_COMMAND may not exist?
125 *
126 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
127 * invalidated when MI_EXE_FLUSH is set.
128 *
129 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
130 * invalidated with every MI_FLUSH.
131 *
132 * TLBs:
133 *
134 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
135 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
136 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
137 * are flushed at any MI_FLUSH.
138 */
139
140 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
141 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
142 cmd &= ~MI_NO_WRITE_FLUSH;
143 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
144 cmd |= MI_EXE_FLUSH;
145
146 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
147 (IS_G4X(req->i915) || IS_GEN5(req->i915)))
148 cmd |= MI_INVALIDATE_ISP;
149
150 ret = intel_ring_begin(req, 2);
151 if (ret)
152 return ret;
153
154 intel_ring_emit(engine, cmd);
155 intel_ring_emit(engine, MI_NOOP);
156 intel_ring_advance(engine);
157
158 return 0;
159 }
160
161 /**
162 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
163 * implementing two workarounds on gen6. From section 1.4.7.1
164 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
165 *
166 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
167 * produced by non-pipelined state commands), software needs to first
168 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
169 * 0.
170 *
171 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
172 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
173 *
174 * And the workaround for these two requires this workaround first:
175 *
176 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
177 * BEFORE the pipe-control with a post-sync op and no write-cache
178 * flushes.
179 *
180 * And this last workaround is tricky because of the requirements on
181 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
182 * volume 2 part 1:
183 *
184 * "1 of the following must also be set:
185 * - Render Target Cache Flush Enable ([12] of DW1)
186 * - Depth Cache Flush Enable ([0] of DW1)
187 * - Stall at Pixel Scoreboard ([1] of DW1)
188 * - Depth Stall ([13] of DW1)
189 * - Post-Sync Operation ([13] of DW1)
190 * - Notify Enable ([8] of DW1)"
191 *
192 * The cache flushes require the workaround flush that triggered this
193 * one, so we can't use it. Depth stall would trigger the same.
194 * Post-sync nonzero is what triggered this second workaround, so we
195 * can't use that one either. Notify enable is IRQs, which aren't
196 * really our business. That leaves only stall at scoreboard.
197 */
198 static int
199 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
200 {
201 struct intel_engine_cs *engine = req->engine;
202 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
203 int ret;
204
205 ret = intel_ring_begin(req, 6);
206 if (ret)
207 return ret;
208
209 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
210 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
211 PIPE_CONTROL_STALL_AT_SCOREBOARD);
212 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(engine, 0); /* low dword */
214 intel_ring_emit(engine, 0); /* high dword */
215 intel_ring_emit(engine, MI_NOOP);
216 intel_ring_advance(engine);
217
218 ret = intel_ring_begin(req, 6);
219 if (ret)
220 return ret;
221
222 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
223 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
224 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
225 intel_ring_emit(engine, 0);
226 intel_ring_emit(engine, 0);
227 intel_ring_emit(engine, MI_NOOP);
228 intel_ring_advance(engine);
229
230 return 0;
231 }
232
233 static int
234 gen6_render_ring_flush(struct drm_i915_gem_request *req,
235 u32 invalidate_domains, u32 flush_domains)
236 {
237 struct intel_engine_cs *engine = req->engine;
238 u32 flags = 0;
239 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
240 int ret;
241
242 /* Force SNB workarounds for PIPE_CONTROL flushes */
243 ret = intel_emit_post_sync_nonzero_flush(req);
244 if (ret)
245 return ret;
246
247 /* Just flush everything. Experiments have shown that reducing the
248 * number of bits based on the write domains has little performance
249 * impact.
250 */
251 if (flush_domains) {
252 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
253 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
254 /*
255 * Ensure that any following seqno writes only happen
256 * when the render cache is indeed flushed.
257 */
258 flags |= PIPE_CONTROL_CS_STALL;
259 }
260 if (invalidate_domains) {
261 flags |= PIPE_CONTROL_TLB_INVALIDATE;
262 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
263 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
264 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
267 /*
268 * TLB invalidate requires a post-sync write.
269 */
270 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
271 }
272
273 ret = intel_ring_begin(req, 4);
274 if (ret)
275 return ret;
276
277 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
278 intel_ring_emit(engine, flags);
279 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
280 intel_ring_emit(engine, 0);
281 intel_ring_advance(engine);
282
283 return 0;
284 }
285
286 static int
287 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
288 {
289 struct intel_engine_cs *engine = req->engine;
290 int ret;
291
292 ret = intel_ring_begin(req, 4);
293 if (ret)
294 return ret;
295
296 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
297 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
298 PIPE_CONTROL_STALL_AT_SCOREBOARD);
299 intel_ring_emit(engine, 0);
300 intel_ring_emit(engine, 0);
301 intel_ring_advance(engine);
302
303 return 0;
304 }
305
306 static int
307 gen7_render_ring_flush(struct drm_i915_gem_request *req,
308 u32 invalidate_domains, u32 flush_domains)
309 {
310 struct intel_engine_cs *engine = req->engine;
311 u32 flags = 0;
312 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
313 int ret;
314
315 /*
316 * Ensure that any following seqno writes only happen when the render
317 * cache is indeed flushed.
318 *
319 * Workaround: 4th PIPE_CONTROL command (except the ones with only
320 * read-cache invalidate bits set) must have the CS_STALL bit set. We
321 * don't try to be clever and just set it unconditionally.
322 */
323 flags |= PIPE_CONTROL_CS_STALL;
324
325 /* Just flush everything. Experiments have shown that reducing the
326 * number of bits based on the write domains has little performance
327 * impact.
328 */
329 if (flush_domains) {
330 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
331 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
332 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
333 flags |= PIPE_CONTROL_FLUSH_ENABLE;
334 }
335 if (invalidate_domains) {
336 flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
343 /*
344 * TLB invalidate requires a post-sync write.
345 */
346 flags |= PIPE_CONTROL_QW_WRITE;
347 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
348
349 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
350
351 /* Workaround: we must issue a pipe_control with CS-stall bit
352 * set before a pipe_control command that has the state cache
353 * invalidate bit set. */
354 gen7_render_ring_cs_stall_wa(req);
355 }
356
357 ret = intel_ring_begin(req, 4);
358 if (ret)
359 return ret;
360
361 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
362 intel_ring_emit(engine, flags);
363 intel_ring_emit(engine, scratch_addr);
364 intel_ring_emit(engine, 0);
365 intel_ring_advance(engine);
366
367 return 0;
368 }
369
370 static int
371 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
372 u32 flags, u32 scratch_addr)
373 {
374 struct intel_engine_cs *engine = req->engine;
375 int ret;
376
377 ret = intel_ring_begin(req, 6);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
382 intel_ring_emit(engine, flags);
383 intel_ring_emit(engine, scratch_addr);
384 intel_ring_emit(engine, 0);
385 intel_ring_emit(engine, 0);
386 intel_ring_emit(engine, 0);
387 intel_ring_advance(engine);
388
389 return 0;
390 }
391
392 static int
393 gen8_render_ring_flush(struct drm_i915_gem_request *req,
394 u32 invalidate_domains, u32 flush_domains)
395 {
396 u32 flags = 0;
397 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
398 int ret;
399
400 flags |= PIPE_CONTROL_CS_STALL;
401
402 if (flush_domains) {
403 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
404 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
405 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
406 flags |= PIPE_CONTROL_FLUSH_ENABLE;
407 }
408 if (invalidate_domains) {
409 flags |= PIPE_CONTROL_TLB_INVALIDATE;
410 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
412 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_QW_WRITE;
416 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
417
418 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
419 ret = gen8_emit_pipe_control(req,
420 PIPE_CONTROL_CS_STALL |
421 PIPE_CONTROL_STALL_AT_SCOREBOARD,
422 0);
423 if (ret)
424 return ret;
425 }
426
427 return gen8_emit_pipe_control(req, flags, scratch_addr);
428 }
429
430 static void ring_write_tail(struct intel_engine_cs *engine,
431 u32 value)
432 {
433 struct drm_i915_private *dev_priv = engine->i915;
434 I915_WRITE_TAIL(engine, value);
435 }
436
437 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
438 {
439 struct drm_i915_private *dev_priv = engine->i915;
440 u64 acthd;
441
442 if (INTEL_GEN(dev_priv) >= 8)
443 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
444 RING_ACTHD_UDW(engine->mmio_base));
445 else if (INTEL_GEN(dev_priv) >= 4)
446 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
447 else
448 acthd = I915_READ(ACTHD);
449
450 return acthd;
451 }
452
453 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
454 {
455 struct drm_i915_private *dev_priv = engine->i915;
456 u32 addr;
457
458 addr = dev_priv->status_page_dmah->busaddr;
459 if (INTEL_GEN(dev_priv) >= 4)
460 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
461 I915_WRITE(HWS_PGA, addr);
462 }
463
464 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
465 {
466 struct drm_i915_private *dev_priv = engine->i915;
467 i915_reg_t mmio;
468
469 /* The ring status page addresses are no longer next to the rest of
470 * the ring registers as of gen7.
471 */
472 if (IS_GEN7(dev_priv)) {
473 switch (engine->id) {
474 case RCS:
475 mmio = RENDER_HWS_PGA_GEN7;
476 break;
477 case BCS:
478 mmio = BLT_HWS_PGA_GEN7;
479 break;
480 /*
481 * VCS2 actually doesn't exist on Gen7. Only shut up
482 * gcc switch check warning
483 */
484 case VCS2:
485 case VCS:
486 mmio = BSD_HWS_PGA_GEN7;
487 break;
488 case VECS:
489 mmio = VEBOX_HWS_PGA_GEN7;
490 break;
491 }
492 } else if (IS_GEN6(dev_priv)) {
493 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
494 } else {
495 /* XXX: gen8 returns to sanity */
496 mmio = RING_HWS_PGA(engine->mmio_base);
497 }
498
499 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
500 POSTING_READ(mmio);
501
502 /*
503 * Flush the TLB for this page
504 *
505 * FIXME: These two bits have disappeared on gen8, so a question
506 * arises: do we still need this and if so how should we go about
507 * invalidating the TLB?
508 */
509 if (IS_GEN(dev_priv, 6, 7)) {
510 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
511
512 /* ring should be idle before issuing a sync flush*/
513 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
514
515 I915_WRITE(reg,
516 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
517 INSTPM_SYNC_FLUSH));
518 if (intel_wait_for_register(dev_priv,
519 reg, INSTPM_SYNC_FLUSH, 0,
520 1000))
521 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
522 engine->name);
523 }
524 }
525
526 static bool stop_ring(struct intel_engine_cs *engine)
527 {
528 struct drm_i915_private *dev_priv = engine->i915;
529
530 if (!IS_GEN2(dev_priv)) {
531 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
532 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
533 DRM_ERROR("%s : timed out trying to stop ring\n",
534 engine->name);
535 /* Sometimes we observe that the idle flag is not
536 * set even though the ring is empty. So double
537 * check before giving up.
538 */
539 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
540 return false;
541 }
542 }
543
544 I915_WRITE_CTL(engine, 0);
545 I915_WRITE_HEAD(engine, 0);
546 engine->write_tail(engine, 0);
547
548 if (!IS_GEN2(dev_priv)) {
549 (void)I915_READ_CTL(engine);
550 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
551 }
552
553 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
554 }
555
556 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
557 {
558 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
559 }
560
561 static int init_ring_common(struct intel_engine_cs *engine)
562 {
563 struct drm_i915_private *dev_priv = engine->i915;
564 struct intel_ringbuffer *ringbuf = engine->buffer;
565 struct drm_i915_gem_object *obj = ringbuf->obj;
566 int ret = 0;
567
568 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
569
570 if (!stop_ring(engine)) {
571 /* G45 ring initialization often fails to reset head to zero */
572 DRM_DEBUG_KMS("%s head not reset to zero "
573 "ctl %08x head %08x tail %08x start %08x\n",
574 engine->name,
575 I915_READ_CTL(engine),
576 I915_READ_HEAD(engine),
577 I915_READ_TAIL(engine),
578 I915_READ_START(engine));
579
580 if (!stop_ring(engine)) {
581 DRM_ERROR("failed to set %s head to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 engine->name,
584 I915_READ_CTL(engine),
585 I915_READ_HEAD(engine),
586 I915_READ_TAIL(engine),
587 I915_READ_START(engine));
588 ret = -EIO;
589 goto out;
590 }
591 }
592
593 if (I915_NEED_GFX_HWS(dev_priv))
594 intel_ring_setup_status_page(engine);
595 else
596 ring_setup_phys_status_page(engine);
597
598 /* Enforce ordering by reading HEAD register back */
599 I915_READ_HEAD(engine);
600
601 /* Initialize the ring. This must happen _after_ we've cleared the ring
602 * registers with the above sequence (the readback of the HEAD registers
603 * also enforces ordering), otherwise the hw might lose the new ring
604 * register values. */
605 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
606
607 /* WaClearRingBufHeadRegAtInit:ctg,elk */
608 if (I915_READ_HEAD(engine))
609 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
610 engine->name, I915_READ_HEAD(engine));
611 I915_WRITE_HEAD(engine, 0);
612 (void)I915_READ_HEAD(engine);
613
614 I915_WRITE_CTL(engine,
615 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
616 | RING_VALID);
617
618 /* If the head is still not zero, the ring is dead */
619 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
620 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
621 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
622 DRM_ERROR("%s initialization failed "
623 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
624 engine->name,
625 I915_READ_CTL(engine),
626 I915_READ_CTL(engine) & RING_VALID,
627 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
628 I915_READ_START(engine),
629 (unsigned long)i915_gem_obj_ggtt_offset(obj));
630 ret = -EIO;
631 goto out;
632 }
633
634 ringbuf->last_retired_head = -1;
635 ringbuf->head = I915_READ_HEAD(engine);
636 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
637 intel_ring_update_space(ringbuf);
638
639 intel_engine_init_hangcheck(engine);
640
641 out:
642 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
643
644 return ret;
645 }
646
647 void
648 intel_fini_pipe_control(struct intel_engine_cs *engine)
649 {
650 if (engine->scratch.obj == NULL)
651 return;
652
653 if (INTEL_GEN(engine->i915) >= 5) {
654 kunmap(sg_page(engine->scratch.obj->pages->sgl));
655 i915_gem_object_ggtt_unpin(engine->scratch.obj);
656 }
657
658 drm_gem_object_unreference(&engine->scratch.obj->base);
659 engine->scratch.obj = NULL;
660 }
661
662 int
663 intel_init_pipe_control(struct intel_engine_cs *engine)
664 {
665 int ret;
666
667 WARN_ON(engine->scratch.obj);
668
669 engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
670 if (IS_ERR(engine->scratch.obj)) {
671 DRM_ERROR("Failed to allocate seqno page\n");
672 ret = PTR_ERR(engine->scratch.obj);
673 engine->scratch.obj = NULL;
674 goto err;
675 }
676
677 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
678 I915_CACHE_LLC);
679 if (ret)
680 goto err_unref;
681
682 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
683 if (ret)
684 goto err_unref;
685
686 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
687 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
688 if (engine->scratch.cpu_page == NULL) {
689 ret = -ENOMEM;
690 goto err_unpin;
691 }
692
693 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
694 engine->name, engine->scratch.gtt_offset);
695 return 0;
696
697 err_unpin:
698 i915_gem_object_ggtt_unpin(engine->scratch.obj);
699 err_unref:
700 drm_gem_object_unreference(&engine->scratch.obj->base);
701 err:
702 return ret;
703 }
704
705 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
706 {
707 struct intel_engine_cs *engine = req->engine;
708 struct i915_workarounds *w = &req->i915->workarounds;
709 int ret, i;
710
711 if (w->count == 0)
712 return 0;
713
714 engine->gpu_caches_dirty = true;
715 ret = intel_ring_flush_all_caches(req);
716 if (ret)
717 return ret;
718
719 ret = intel_ring_begin(req, (w->count * 2 + 2));
720 if (ret)
721 return ret;
722
723 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
724 for (i = 0; i < w->count; i++) {
725 intel_ring_emit_reg(engine, w->reg[i].addr);
726 intel_ring_emit(engine, w->reg[i].value);
727 }
728 intel_ring_emit(engine, MI_NOOP);
729
730 intel_ring_advance(engine);
731
732 engine->gpu_caches_dirty = true;
733 ret = intel_ring_flush_all_caches(req);
734 if (ret)
735 return ret;
736
737 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
738
739 return 0;
740 }
741
742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
743 {
744 int ret;
745
746 ret = intel_ring_workarounds_emit(req);
747 if (ret != 0)
748 return ret;
749
750 ret = i915_gem_render_state_init(req);
751 if (ret)
752 return ret;
753
754 return 0;
755 }
756
757 static int wa_add(struct drm_i915_private *dev_priv,
758 i915_reg_t addr,
759 const u32 mask, const u32 val)
760 {
761 const u32 idx = dev_priv->workarounds.count;
762
763 if (WARN_ON(idx >= I915_MAX_WA_REGS))
764 return -ENOSPC;
765
766 dev_priv->workarounds.reg[idx].addr = addr;
767 dev_priv->workarounds.reg[idx].value = val;
768 dev_priv->workarounds.reg[idx].mask = mask;
769
770 dev_priv->workarounds.count++;
771
772 return 0;
773 }
774
775 #define WA_REG(addr, mask, val) do { \
776 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
777 if (r) \
778 return r; \
779 } while (0)
780
781 #define WA_SET_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
783
784 #define WA_CLR_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
786
787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
788 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
789
790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
792
793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
794
795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
796 i915_reg_t reg)
797 {
798 struct drm_i915_private *dev_priv = engine->i915;
799 struct i915_workarounds *wa = &dev_priv->workarounds;
800 const uint32_t index = wa->hw_whitelist_count[engine->id];
801
802 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
803 return -EINVAL;
804
805 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
806 i915_mmio_reg_offset(reg));
807 wa->hw_whitelist_count[engine->id]++;
808
809 return 0;
810 }
811
812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
813 {
814 struct drm_i915_private *dev_priv = engine->i915;
815
816 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
817
818 /* WaDisableAsyncFlipPerfMode:bdw,chv */
819 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
820
821 /* WaDisablePartialInstShootdown:bdw,chv */
822 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
823 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
824
825 /* Use Force Non-Coherent whenever executing a 3D context. This is a
826 * workaround for for a possible hang in the unlikely event a TLB
827 * invalidation occurs during a PSD flush.
828 */
829 /* WaForceEnableNonCoherent:bdw,chv */
830 /* WaHdcDisableFetchWhenMasked:bdw,chv */
831 WA_SET_BIT_MASKED(HDC_CHICKEN0,
832 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
833 HDC_FORCE_NON_COHERENT);
834
835 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
836 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
837 * polygons in the same 8x4 pixel/sample area to be processed without
838 * stalling waiting for the earlier ones to write to Hierarchical Z
839 * buffer."
840 *
841 * This optimization is off by default for BDW and CHV; turn it on.
842 */
843 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
844
845 /* Wa4x4STCOptimizationDisable:bdw,chv */
846 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
847
848 /*
849 * BSpec recommends 8x4 when MSAA is used,
850 * however in practice 16x4 seems fastest.
851 *
852 * Note that PS/WM thread counts depend on the WIZ hashing
853 * disable bit, which we don't touch here, but it's good
854 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
855 */
856 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
857 GEN6_WIZ_HASHING_MASK,
858 GEN6_WIZ_HASHING_16x4);
859
860 return 0;
861 }
862
863 static int bdw_init_workarounds(struct intel_engine_cs *engine)
864 {
865 struct drm_i915_private *dev_priv = engine->i915;
866 int ret;
867
868 ret = gen8_init_workarounds(engine);
869 if (ret)
870 return ret;
871
872 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
873 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
874
875 /* WaDisableDopClockGating:bdw */
876 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
877 DOP_CLOCK_GATING_DISABLE);
878
879 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
880 GEN8_SAMPLER_POWER_BYPASS_DIS);
881
882 WA_SET_BIT_MASKED(HDC_CHICKEN0,
883 /* WaForceContextSaveRestoreNonCoherent:bdw */
884 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
885 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
886 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
887
888 return 0;
889 }
890
891 static int chv_init_workarounds(struct intel_engine_cs *engine)
892 {
893 struct drm_i915_private *dev_priv = engine->i915;
894 int ret;
895
896 ret = gen8_init_workarounds(engine);
897 if (ret)
898 return ret;
899
900 /* WaDisableThreadStallDopClockGating:chv */
901 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
902
903 /* Improve HiZ throughput on CHV. */
904 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
905
906 return 0;
907 }
908
909 static int gen9_init_workarounds(struct intel_engine_cs *engine)
910 {
911 struct drm_i915_private *dev_priv = engine->i915;
912 int ret;
913
914 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
915 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
916
917 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
918 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
919 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
920
921 /* WaDisableKillLogic:bxt,skl,kbl */
922 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
923 ECOCHK_DIS_TLB);
924
925 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
926 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
927 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
928 FLOW_CONTROL_ENABLE |
929 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
930
931 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
932 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
933 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
934
935 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
936 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
937 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
938 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
939 GEN9_DG_MIRROR_FIX_ENABLE);
940
941 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
942 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
943 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
944 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
945 GEN9_RHWO_OPTIMIZATION_DISABLE);
946 /*
947 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
948 * but we do that in per ctx batchbuffer as there is an issue
949 * with this register not getting restored on ctx restore
950 */
951 }
952
953 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
954 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
955 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
956 GEN9_ENABLE_YV12_BUGFIX |
957 GEN9_ENABLE_GPGPU_PREEMPTION);
958
959 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
960 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
961 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
962 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
963
964 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
965 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
966 GEN9_CCS_TLB_PREFETCH_ENABLE);
967
968 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
969 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
970 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
971 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
972 PIXEL_MASK_CAMMING_DISABLE);
973
974 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
975 WA_SET_BIT_MASKED(HDC_CHICKEN0,
976 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
977 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
978
979 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
980 * both tied to WaForceContextSaveRestoreNonCoherent
981 * in some hsds for skl. We keep the tie for all gen9. The
982 * documentation is a bit hazy and so we want to get common behaviour,
983 * even though there is no clear evidence we would need both on kbl/bxt.
984 * This area has been source of system hangs so we play it safe
985 * and mimic the skl regardless of what bspec says.
986 *
987 * Use Force Non-Coherent whenever executing a 3D context. This
988 * is a workaround for a possible hang in the unlikely event
989 * a TLB invalidation occurs during a PSD flush.
990 */
991
992 /* WaForceEnableNonCoherent:skl,bxt,kbl */
993 WA_SET_BIT_MASKED(HDC_CHICKEN0,
994 HDC_FORCE_NON_COHERENT);
995
996 /* WaDisableHDCInvalidation:skl,bxt,kbl */
997 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
998 BDW_DISABLE_HDC_INVALIDATION);
999
1000 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1001 if (IS_SKYLAKE(dev_priv) ||
1002 IS_KABYLAKE(dev_priv) ||
1003 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1004 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1005 GEN8_SAMPLER_POWER_BYPASS_DIS);
1006
1007 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1008 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1009
1010 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1011 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1012 GEN8_LQSC_FLUSH_COHERENT_LINES));
1013
1014 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1015 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1016 if (ret)
1017 return ret;
1018
1019 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1020 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1021 if (ret)
1022 return ret;
1023
1024 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1025 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1026 if (ret)
1027 return ret;
1028
1029 return 0;
1030 }
1031
1032 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1033 {
1034 struct drm_i915_private *dev_priv = engine->i915;
1035 u8 vals[3] = { 0, 0, 0 };
1036 unsigned int i;
1037
1038 for (i = 0; i < 3; i++) {
1039 u8 ss;
1040
1041 /*
1042 * Only consider slices where one, and only one, subslice has 7
1043 * EUs
1044 */
1045 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1046 continue;
1047
1048 /*
1049 * subslice_7eu[i] != 0 (because of the check above) and
1050 * ss_max == 4 (maximum number of subslices possible per slice)
1051 *
1052 * -> 0 <= ss <= 3;
1053 */
1054 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1055 vals[i] = 3 - ss;
1056 }
1057
1058 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1059 return 0;
1060
1061 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1062 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1063 GEN9_IZ_HASHING_MASK(2) |
1064 GEN9_IZ_HASHING_MASK(1) |
1065 GEN9_IZ_HASHING_MASK(0),
1066 GEN9_IZ_HASHING(2, vals[2]) |
1067 GEN9_IZ_HASHING(1, vals[1]) |
1068 GEN9_IZ_HASHING(0, vals[0]));
1069
1070 return 0;
1071 }
1072
1073 static int skl_init_workarounds(struct intel_engine_cs *engine)
1074 {
1075 struct drm_i915_private *dev_priv = engine->i915;
1076 int ret;
1077
1078 ret = gen9_init_workarounds(engine);
1079 if (ret)
1080 return ret;
1081
1082 /*
1083 * Actual WA is to disable percontext preemption granularity control
1084 * until D0 which is the default case so this is equivalent to
1085 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1086 */
1087 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1088 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1089 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1090 }
1091
1092 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
1093 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1094 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1095 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1096 }
1097
1098 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1099 * involving this register should also be added to WA batch as required.
1100 */
1101 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1102 /* WaDisableLSQCROPERFforOCL:skl */
1103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1104 GEN8_LQSC_RO_PERF_DIS);
1105
1106 /* WaEnableGapsTsvCreditFix:skl */
1107 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1108 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1109 GEN9_GAPS_TSV_CREDIT_DISABLE));
1110 }
1111
1112 /* WaDisablePowerCompilerClockGating:skl */
1113 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1114 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1115 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1116
1117 /* WaBarrierPerformanceFixDisable:skl */
1118 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1119 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1120 HDC_FENCE_DEST_SLM_DISABLE |
1121 HDC_BARRIER_PERFORMANCE_DISABLE);
1122
1123 /* WaDisableSbeCacheDispatchPortSharing:skl */
1124 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1125 WA_SET_BIT_MASKED(
1126 GEN7_HALF_SLICE_CHICKEN1,
1127 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1128
1129 /* WaDisableGafsUnitClkGating:skl */
1130 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1131
1132 /* WaDisableLSQCROPERFforOCL:skl */
1133 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1134 if (ret)
1135 return ret;
1136
1137 return skl_tune_iz_hashing(engine);
1138 }
1139
1140 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1141 {
1142 struct drm_i915_private *dev_priv = engine->i915;
1143 int ret;
1144
1145 ret = gen9_init_workarounds(engine);
1146 if (ret)
1147 return ret;
1148
1149 /* WaStoreMultiplePTEenable:bxt */
1150 /* This is a requirement according to Hardware specification */
1151 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1152 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1153
1154 /* WaSetClckGatingDisableMedia:bxt */
1155 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1156 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1157 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1158 }
1159
1160 /* WaDisableThreadStallDopClockGating:bxt */
1161 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1162 STALL_DOP_GATING_DISABLE);
1163
1164 /* WaDisablePooledEuLoadBalancingFix:bxt */
1165 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1166 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1167 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1168 }
1169
1170 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1171 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1172 WA_SET_BIT_MASKED(
1173 GEN7_HALF_SLICE_CHICKEN1,
1174 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1175 }
1176
1177 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1178 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1179 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1180 /* WaDisableLSQCROPERFforOCL:bxt */
1181 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1182 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1183 if (ret)
1184 return ret;
1185
1186 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1187 if (ret)
1188 return ret;
1189 }
1190
1191 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1192 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1193 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1194 L3_HIGH_PRIO_CREDITS(2));
1195
1196 /* WaInsertDummyPushConstPs:bxt */
1197 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1198 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1199 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1200
1201 return 0;
1202 }
1203
1204 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1205 {
1206 struct drm_i915_private *dev_priv = engine->i915;
1207 int ret;
1208
1209 ret = gen9_init_workarounds(engine);
1210 if (ret)
1211 return ret;
1212
1213 /* WaEnableGapsTsvCreditFix:kbl */
1214 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1215 GEN9_GAPS_TSV_CREDIT_DISABLE));
1216
1217 /* WaDisableDynamicCreditSharing:kbl */
1218 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1219 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1220 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1221
1222 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1223 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1224 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1225 HDC_FENCE_DEST_SLM_DISABLE);
1226
1227 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1228 * involving this register should also be added to WA batch as required.
1229 */
1230 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1231 /* WaDisableLSQCROPERFforOCL:kbl */
1232 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1233 GEN8_LQSC_RO_PERF_DIS);
1234
1235 /* WaInsertDummyPushConstPs:kbl */
1236 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1237 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1238 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1239
1240 /* WaDisableGafsUnitClkGating:kbl */
1241 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1242
1243 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1244 WA_SET_BIT_MASKED(
1245 GEN7_HALF_SLICE_CHICKEN1,
1246 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1247
1248 /* WaDisableLSQCROPERFforOCL:kbl */
1249 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1250 if (ret)
1251 return ret;
1252
1253 return 0;
1254 }
1255
1256 int init_workarounds_ring(struct intel_engine_cs *engine)
1257 {
1258 struct drm_i915_private *dev_priv = engine->i915;
1259
1260 WARN_ON(engine->id != RCS);
1261
1262 dev_priv->workarounds.count = 0;
1263 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1264
1265 if (IS_BROADWELL(dev_priv))
1266 return bdw_init_workarounds(engine);
1267
1268 if (IS_CHERRYVIEW(dev_priv))
1269 return chv_init_workarounds(engine);
1270
1271 if (IS_SKYLAKE(dev_priv))
1272 return skl_init_workarounds(engine);
1273
1274 if (IS_BROXTON(dev_priv))
1275 return bxt_init_workarounds(engine);
1276
1277 if (IS_KABYLAKE(dev_priv))
1278 return kbl_init_workarounds(engine);
1279
1280 return 0;
1281 }
1282
1283 static int init_render_ring(struct intel_engine_cs *engine)
1284 {
1285 struct drm_i915_private *dev_priv = engine->i915;
1286 int ret = init_ring_common(engine);
1287 if (ret)
1288 return ret;
1289
1290 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1291 if (IS_GEN(dev_priv, 4, 6))
1292 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1293
1294 /* We need to disable the AsyncFlip performance optimisations in order
1295 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1296 * programmed to '1' on all products.
1297 *
1298 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1299 */
1300 if (IS_GEN(dev_priv, 6, 7))
1301 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1302
1303 /* Required for the hardware to program scanline values for waiting */
1304 /* WaEnableFlushTlbInvalidationMode:snb */
1305 if (IS_GEN6(dev_priv))
1306 I915_WRITE(GFX_MODE,
1307 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1308
1309 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1310 if (IS_GEN7(dev_priv))
1311 I915_WRITE(GFX_MODE_GEN7,
1312 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1313 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1314
1315 if (IS_GEN6(dev_priv)) {
1316 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1317 * "If this bit is set, STCunit will have LRA as replacement
1318 * policy. [...] This bit must be reset. LRA replacement
1319 * policy is not supported."
1320 */
1321 I915_WRITE(CACHE_MODE_0,
1322 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1323 }
1324
1325 if (IS_GEN(dev_priv, 6, 7))
1326 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1327
1328 if (HAS_L3_DPF(dev_priv))
1329 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1330
1331 return init_workarounds_ring(engine);
1332 }
1333
1334 static void render_ring_cleanup(struct intel_engine_cs *engine)
1335 {
1336 struct drm_i915_private *dev_priv = engine->i915;
1337
1338 if (dev_priv->semaphore_obj) {
1339 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1340 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1341 dev_priv->semaphore_obj = NULL;
1342 }
1343
1344 intel_fini_pipe_control(engine);
1345 }
1346
1347 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1348 unsigned int num_dwords)
1349 {
1350 #define MBOX_UPDATE_DWORDS 8
1351 struct intel_engine_cs *signaller = signaller_req->engine;
1352 struct drm_i915_private *dev_priv = signaller_req->i915;
1353 struct intel_engine_cs *waiter;
1354 enum intel_engine_id id;
1355 int ret, num_rings;
1356
1357 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1358 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1359 #undef MBOX_UPDATE_DWORDS
1360
1361 ret = intel_ring_begin(signaller_req, num_dwords);
1362 if (ret)
1363 return ret;
1364
1365 for_each_engine_id(waiter, dev_priv, id) {
1366 u32 seqno;
1367 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1368 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1369 continue;
1370
1371 seqno = i915_gem_request_get_seqno(signaller_req);
1372 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1373 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1374 PIPE_CONTROL_QW_WRITE |
1375 PIPE_CONTROL_CS_STALL);
1376 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1377 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1378 intel_ring_emit(signaller, seqno);
1379 intel_ring_emit(signaller, 0);
1380 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1381 MI_SEMAPHORE_TARGET(waiter->hw_id));
1382 intel_ring_emit(signaller, 0);
1383 }
1384
1385 return 0;
1386 }
1387
1388 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1389 unsigned int num_dwords)
1390 {
1391 #define MBOX_UPDATE_DWORDS 6
1392 struct intel_engine_cs *signaller = signaller_req->engine;
1393 struct drm_i915_private *dev_priv = signaller_req->i915;
1394 struct intel_engine_cs *waiter;
1395 enum intel_engine_id id;
1396 int ret, num_rings;
1397
1398 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1399 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1400 #undef MBOX_UPDATE_DWORDS
1401
1402 ret = intel_ring_begin(signaller_req, num_dwords);
1403 if (ret)
1404 return ret;
1405
1406 for_each_engine_id(waiter, dev_priv, id) {
1407 u32 seqno;
1408 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1409 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1410 continue;
1411
1412 seqno = i915_gem_request_get_seqno(signaller_req);
1413 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1414 MI_FLUSH_DW_OP_STOREDW);
1415 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1416 MI_FLUSH_DW_USE_GTT);
1417 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1418 intel_ring_emit(signaller, seqno);
1419 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1420 MI_SEMAPHORE_TARGET(waiter->hw_id));
1421 intel_ring_emit(signaller, 0);
1422 }
1423
1424 return 0;
1425 }
1426
1427 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1428 unsigned int num_dwords)
1429 {
1430 struct intel_engine_cs *signaller = signaller_req->engine;
1431 struct drm_i915_private *dev_priv = signaller_req->i915;
1432 struct intel_engine_cs *useless;
1433 enum intel_engine_id id;
1434 int ret, num_rings;
1435
1436 #define MBOX_UPDATE_DWORDS 3
1437 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1438 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1439 #undef MBOX_UPDATE_DWORDS
1440
1441 ret = intel_ring_begin(signaller_req, num_dwords);
1442 if (ret)
1443 return ret;
1444
1445 for_each_engine_id(useless, dev_priv, id) {
1446 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1447
1448 if (i915_mmio_reg_valid(mbox_reg)) {
1449 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1450
1451 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1452 intel_ring_emit_reg(signaller, mbox_reg);
1453 intel_ring_emit(signaller, seqno);
1454 }
1455 }
1456
1457 /* If num_dwords was rounded, make sure the tail pointer is correct */
1458 if (num_rings % 2 == 0)
1459 intel_ring_emit(signaller, MI_NOOP);
1460
1461 return 0;
1462 }
1463
1464 /**
1465 * gen6_add_request - Update the semaphore mailbox registers
1466 *
1467 * @request - request to write to the ring
1468 *
1469 * Update the mailbox registers in the *other* rings with the current seqno.
1470 * This acts like a signal in the canonical semaphore.
1471 */
1472 static int
1473 gen6_add_request(struct drm_i915_gem_request *req)
1474 {
1475 struct intel_engine_cs *engine = req->engine;
1476 int ret;
1477
1478 if (engine->semaphore.signal)
1479 ret = engine->semaphore.signal(req, 4);
1480 else
1481 ret = intel_ring_begin(req, 4);
1482
1483 if (ret)
1484 return ret;
1485
1486 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1487 intel_ring_emit(engine,
1488 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1489 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1490 intel_ring_emit(engine, MI_USER_INTERRUPT);
1491 __intel_ring_advance(engine);
1492
1493 return 0;
1494 }
1495
1496 static int
1497 gen8_render_add_request(struct drm_i915_gem_request *req)
1498 {
1499 struct intel_engine_cs *engine = req->engine;
1500 int ret;
1501
1502 if (engine->semaphore.signal)
1503 ret = engine->semaphore.signal(req, 8);
1504 else
1505 ret = intel_ring_begin(req, 8);
1506 if (ret)
1507 return ret;
1508
1509 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1510 intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1511 PIPE_CONTROL_CS_STALL |
1512 PIPE_CONTROL_QW_WRITE));
1513 intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1514 intel_ring_emit(engine, 0);
1515 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1516 /* We're thrashing one dword of HWS. */
1517 intel_ring_emit(engine, 0);
1518 intel_ring_emit(engine, MI_USER_INTERRUPT);
1519 intel_ring_emit(engine, MI_NOOP);
1520 __intel_ring_advance(engine);
1521
1522 return 0;
1523 }
1524
1525 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
1526 u32 seqno)
1527 {
1528 return dev_priv->last_seqno < seqno;
1529 }
1530
1531 /**
1532 * intel_ring_sync - sync the waiter to the signaller on seqno
1533 *
1534 * @waiter - ring that is waiting
1535 * @signaller - ring which has, or will signal
1536 * @seqno - seqno which the waiter will block on
1537 */
1538
1539 static int
1540 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1541 struct intel_engine_cs *signaller,
1542 u32 seqno)
1543 {
1544 struct intel_engine_cs *waiter = waiter_req->engine;
1545 struct drm_i915_private *dev_priv = waiter_req->i915;
1546 struct i915_hw_ppgtt *ppgtt;
1547 int ret;
1548
1549 ret = intel_ring_begin(waiter_req, 4);
1550 if (ret)
1551 return ret;
1552
1553 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1554 MI_SEMAPHORE_GLOBAL_GTT |
1555 MI_SEMAPHORE_SAD_GTE_SDD);
1556 intel_ring_emit(waiter, seqno);
1557 intel_ring_emit(waiter,
1558 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1559 intel_ring_emit(waiter,
1560 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1561 intel_ring_advance(waiter);
1562
1563 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1564 * pagetables and we must reload them before executing the batch.
1565 * We do this on the i915_switch_context() following the wait and
1566 * before the dispatch.
1567 */
1568 ppgtt = waiter_req->ctx->ppgtt;
1569 if (ppgtt && waiter_req->engine->id != RCS)
1570 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
1571 return 0;
1572 }
1573
1574 static int
1575 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1576 struct intel_engine_cs *signaller,
1577 u32 seqno)
1578 {
1579 struct intel_engine_cs *waiter = waiter_req->engine;
1580 u32 dw1 = MI_SEMAPHORE_MBOX |
1581 MI_SEMAPHORE_COMPARE |
1582 MI_SEMAPHORE_REGISTER;
1583 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1584 int ret;
1585
1586 /* Throughout all of the GEM code, seqno passed implies our current
1587 * seqno is >= the last seqno executed. However for hardware the
1588 * comparison is strictly greater than.
1589 */
1590 seqno -= 1;
1591
1592 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1593
1594 ret = intel_ring_begin(waiter_req, 4);
1595 if (ret)
1596 return ret;
1597
1598 /* If seqno wrap happened, omit the wait with no-ops */
1599 if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
1600 intel_ring_emit(waiter, dw1 | wait_mbox);
1601 intel_ring_emit(waiter, seqno);
1602 intel_ring_emit(waiter, 0);
1603 intel_ring_emit(waiter, MI_NOOP);
1604 } else {
1605 intel_ring_emit(waiter, MI_NOOP);
1606 intel_ring_emit(waiter, MI_NOOP);
1607 intel_ring_emit(waiter, MI_NOOP);
1608 intel_ring_emit(waiter, MI_NOOP);
1609 }
1610 intel_ring_advance(waiter);
1611
1612 return 0;
1613 }
1614
1615 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1616 do { \
1617 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1618 PIPE_CONTROL_DEPTH_STALL); \
1619 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1620 intel_ring_emit(ring__, 0); \
1621 intel_ring_emit(ring__, 0); \
1622 } while (0)
1623
1624 static int
1625 pc_render_add_request(struct drm_i915_gem_request *req)
1626 {
1627 struct intel_engine_cs *engine = req->engine;
1628 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1629 int ret;
1630
1631 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1632 * incoherent with writes to memory, i.e. completely fubar,
1633 * so we need to use PIPE_NOTIFY instead.
1634 *
1635 * However, we also need to workaround the qword write
1636 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1637 * memory before requesting an interrupt.
1638 */
1639 ret = intel_ring_begin(req, 32);
1640 if (ret)
1641 return ret;
1642
1643 intel_ring_emit(engine,
1644 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1645 PIPE_CONTROL_WRITE_FLUSH |
1646 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1647 intel_ring_emit(engine,
1648 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1649 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1650 intel_ring_emit(engine, 0);
1651 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1652 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1653 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1654 scratch_addr += 2 * CACHELINE_BYTES;
1655 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1656 scratch_addr += 2 * CACHELINE_BYTES;
1657 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1658 scratch_addr += 2 * CACHELINE_BYTES;
1659 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1660 scratch_addr += 2 * CACHELINE_BYTES;
1661 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1662
1663 intel_ring_emit(engine,
1664 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1665 PIPE_CONTROL_WRITE_FLUSH |
1666 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1667 PIPE_CONTROL_NOTIFY);
1668 intel_ring_emit(engine,
1669 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1670 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1671 intel_ring_emit(engine, 0);
1672 __intel_ring_advance(engine);
1673
1674 return 0;
1675 }
1676
1677 static void
1678 gen6_seqno_barrier(struct intel_engine_cs *engine)
1679 {
1680 struct drm_i915_private *dev_priv = engine->i915;
1681
1682 /* Workaround to force correct ordering between irq and seqno writes on
1683 * ivb (and maybe also on snb) by reading from a CS register (like
1684 * ACTHD) before reading the status page.
1685 *
1686 * Note that this effectively stalls the read by the time it takes to
1687 * do a memory transaction, which more or less ensures that the write
1688 * from the GPU has sufficient time to invalidate the CPU cacheline.
1689 * Alternatively we could delay the interrupt from the CS ring to give
1690 * the write time to land, but that would incur a delay after every
1691 * batch i.e. much more frequent than a delay when waiting for the
1692 * interrupt (with the same net latency).
1693 *
1694 * Also note that to prevent whole machine hangs on gen7, we have to
1695 * take the spinlock to guard against concurrent cacheline access.
1696 */
1697 spin_lock_irq(&dev_priv->uncore.lock);
1698 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1699 spin_unlock_irq(&dev_priv->uncore.lock);
1700 }
1701
1702 static u32
1703 ring_get_seqno(struct intel_engine_cs *engine)
1704 {
1705 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1706 }
1707
1708 static void
1709 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1710 {
1711 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1712 }
1713
1714 static u32
1715 pc_render_get_seqno(struct intel_engine_cs *engine)
1716 {
1717 return engine->scratch.cpu_page[0];
1718 }
1719
1720 static void
1721 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1722 {
1723 engine->scratch.cpu_page[0] = seqno;
1724 }
1725
1726 static bool
1727 gen5_ring_get_irq(struct intel_engine_cs *engine)
1728 {
1729 struct drm_i915_private *dev_priv = engine->i915;
1730 unsigned long flags;
1731
1732 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1733 return false;
1734
1735 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1736 if (engine->irq_refcount++ == 0)
1737 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739
1740 return true;
1741 }
1742
1743 static void
1744 gen5_ring_put_irq(struct intel_engine_cs *engine)
1745 {
1746 struct drm_i915_private *dev_priv = engine->i915;
1747 unsigned long flags;
1748
1749 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1750 if (--engine->irq_refcount == 0)
1751 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1752 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1753 }
1754
1755 static bool
1756 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1757 {
1758 struct drm_i915_private *dev_priv = engine->i915;
1759 unsigned long flags;
1760
1761 if (!intel_irqs_enabled(dev_priv))
1762 return false;
1763
1764 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1765 if (engine->irq_refcount++ == 0) {
1766 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1767 I915_WRITE(IMR, dev_priv->irq_mask);
1768 POSTING_READ(IMR);
1769 }
1770 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1771
1772 return true;
1773 }
1774
1775 static void
1776 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1777 {
1778 struct drm_i915_private *dev_priv = engine->i915;
1779 unsigned long flags;
1780
1781 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1782 if (--engine->irq_refcount == 0) {
1783 dev_priv->irq_mask |= engine->irq_enable_mask;
1784 I915_WRITE(IMR, dev_priv->irq_mask);
1785 POSTING_READ(IMR);
1786 }
1787 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1788 }
1789
1790 static bool
1791 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1792 {
1793 struct drm_i915_private *dev_priv = engine->i915;
1794 unsigned long flags;
1795
1796 if (!intel_irqs_enabled(dev_priv))
1797 return false;
1798
1799 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1800 if (engine->irq_refcount++ == 0) {
1801 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1802 I915_WRITE16(IMR, dev_priv->irq_mask);
1803 POSTING_READ16(IMR);
1804 }
1805 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1806
1807 return true;
1808 }
1809
1810 static void
1811 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1812 {
1813 struct drm_i915_private *dev_priv = engine->i915;
1814 unsigned long flags;
1815
1816 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1817 if (--engine->irq_refcount == 0) {
1818 dev_priv->irq_mask |= engine->irq_enable_mask;
1819 I915_WRITE16(IMR, dev_priv->irq_mask);
1820 POSTING_READ16(IMR);
1821 }
1822 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1823 }
1824
1825 static int
1826 bsd_ring_flush(struct drm_i915_gem_request *req,
1827 u32 invalidate_domains,
1828 u32 flush_domains)
1829 {
1830 struct intel_engine_cs *engine = req->engine;
1831 int ret;
1832
1833 ret = intel_ring_begin(req, 2);
1834 if (ret)
1835 return ret;
1836
1837 intel_ring_emit(engine, MI_FLUSH);
1838 intel_ring_emit(engine, MI_NOOP);
1839 intel_ring_advance(engine);
1840 return 0;
1841 }
1842
1843 static int
1844 i9xx_add_request(struct drm_i915_gem_request *req)
1845 {
1846 struct intel_engine_cs *engine = req->engine;
1847 int ret;
1848
1849 ret = intel_ring_begin(req, 4);
1850 if (ret)
1851 return ret;
1852
1853 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1854 intel_ring_emit(engine,
1855 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1856 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1857 intel_ring_emit(engine, MI_USER_INTERRUPT);
1858 __intel_ring_advance(engine);
1859
1860 return 0;
1861 }
1862
1863 static bool
1864 gen6_ring_get_irq(struct intel_engine_cs *engine)
1865 {
1866 struct drm_i915_private *dev_priv = engine->i915;
1867 unsigned long flags;
1868
1869 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1870 return false;
1871
1872 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1873 if (engine->irq_refcount++ == 0) {
1874 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1875 I915_WRITE_IMR(engine,
1876 ~(engine->irq_enable_mask |
1877 GT_PARITY_ERROR(dev_priv)));
1878 else
1879 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1880 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1881 }
1882 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1883
1884 return true;
1885 }
1886
1887 static void
1888 gen6_ring_put_irq(struct intel_engine_cs *engine)
1889 {
1890 struct drm_i915_private *dev_priv = engine->i915;
1891 unsigned long flags;
1892
1893 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1894 if (--engine->irq_refcount == 0) {
1895 if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
1896 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
1897 else
1898 I915_WRITE_IMR(engine, ~0);
1899 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1900 }
1901 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1902 }
1903
1904 static bool
1905 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1906 {
1907 struct drm_i915_private *dev_priv = engine->i915;
1908 unsigned long flags;
1909
1910 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1911 return false;
1912
1913 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1914 if (engine->irq_refcount++ == 0) {
1915 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1916 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1917 }
1918 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1919
1920 return true;
1921 }
1922
1923 static void
1924 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1925 {
1926 struct drm_i915_private *dev_priv = engine->i915;
1927 unsigned long flags;
1928
1929 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1930 if (--engine->irq_refcount == 0) {
1931 I915_WRITE_IMR(engine, ~0);
1932 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1933 }
1934 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1935 }
1936
1937 static bool
1938 gen8_ring_get_irq(struct intel_engine_cs *engine)
1939 {
1940 struct drm_i915_private *dev_priv = engine->i915;
1941 unsigned long flags;
1942
1943 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1944 return false;
1945
1946 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1947 if (engine->irq_refcount++ == 0) {
1948 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1949 I915_WRITE_IMR(engine,
1950 ~(engine->irq_enable_mask |
1951 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1952 } else {
1953 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1954 }
1955 POSTING_READ(RING_IMR(engine->mmio_base));
1956 }
1957 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1958
1959 return true;
1960 }
1961
1962 static void
1963 gen8_ring_put_irq(struct intel_engine_cs *engine)
1964 {
1965 struct drm_i915_private *dev_priv = engine->i915;
1966 unsigned long flags;
1967
1968 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1969 if (--engine->irq_refcount == 0) {
1970 if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
1971 I915_WRITE_IMR(engine,
1972 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1973 } else {
1974 I915_WRITE_IMR(engine, ~0);
1975 }
1976 POSTING_READ(RING_IMR(engine->mmio_base));
1977 }
1978 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1979 }
1980
1981 static int
1982 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1983 u64 offset, u32 length,
1984 unsigned dispatch_flags)
1985 {
1986 struct intel_engine_cs *engine = req->engine;
1987 int ret;
1988
1989 ret = intel_ring_begin(req, 2);
1990 if (ret)
1991 return ret;
1992
1993 intel_ring_emit(engine,
1994 MI_BATCH_BUFFER_START |
1995 MI_BATCH_GTT |
1996 (dispatch_flags & I915_DISPATCH_SECURE ?
1997 0 : MI_BATCH_NON_SECURE_I965));
1998 intel_ring_emit(engine, offset);
1999 intel_ring_advance(engine);
2000
2001 return 0;
2002 }
2003
2004 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
2005 #define I830_BATCH_LIMIT (256*1024)
2006 #define I830_TLB_ENTRIES (2)
2007 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
2008 static int
2009 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
2010 u64 offset, u32 len,
2011 unsigned dispatch_flags)
2012 {
2013 struct intel_engine_cs *engine = req->engine;
2014 u32 cs_offset = engine->scratch.gtt_offset;
2015 int ret;
2016
2017 ret = intel_ring_begin(req, 6);
2018 if (ret)
2019 return ret;
2020
2021 /* Evict the invalid PTE TLBs */
2022 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
2023 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
2024 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
2025 intel_ring_emit(engine, cs_offset);
2026 intel_ring_emit(engine, 0xdeadbeef);
2027 intel_ring_emit(engine, MI_NOOP);
2028 intel_ring_advance(engine);
2029
2030 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
2031 if (len > I830_BATCH_LIMIT)
2032 return -ENOSPC;
2033
2034 ret = intel_ring_begin(req, 6 + 2);
2035 if (ret)
2036 return ret;
2037
2038 /* Blit the batch (which has now all relocs applied) to the
2039 * stable batch scratch bo area (so that the CS never
2040 * stumbles over its tlb invalidation bug) ...
2041 */
2042 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
2043 intel_ring_emit(engine,
2044 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
2045 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
2046 intel_ring_emit(engine, cs_offset);
2047 intel_ring_emit(engine, 4096);
2048 intel_ring_emit(engine, offset);
2049
2050 intel_ring_emit(engine, MI_FLUSH);
2051 intel_ring_emit(engine, MI_NOOP);
2052 intel_ring_advance(engine);
2053
2054 /* ... and execute it. */
2055 offset = cs_offset;
2056 }
2057
2058 ret = intel_ring_begin(req, 2);
2059 if (ret)
2060 return ret;
2061
2062 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2063 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2064 0 : MI_BATCH_NON_SECURE));
2065 intel_ring_advance(engine);
2066
2067 return 0;
2068 }
2069
2070 static int
2071 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2072 u64 offset, u32 len,
2073 unsigned dispatch_flags)
2074 {
2075 struct intel_engine_cs *engine = req->engine;
2076 int ret;
2077
2078 ret = intel_ring_begin(req, 2);
2079 if (ret)
2080 return ret;
2081
2082 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2083 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2084 0 : MI_BATCH_NON_SECURE));
2085 intel_ring_advance(engine);
2086
2087 return 0;
2088 }
2089
2090 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2091 {
2092 struct drm_i915_private *dev_priv = engine->i915;
2093
2094 if (!dev_priv->status_page_dmah)
2095 return;
2096
2097 drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
2098 engine->status_page.page_addr = NULL;
2099 }
2100
2101 static void cleanup_status_page(struct intel_engine_cs *engine)
2102 {
2103 struct drm_i915_gem_object *obj;
2104
2105 obj = engine->status_page.obj;
2106 if (obj == NULL)
2107 return;
2108
2109 kunmap(sg_page(obj->pages->sgl));
2110 i915_gem_object_ggtt_unpin(obj);
2111 drm_gem_object_unreference(&obj->base);
2112 engine->status_page.obj = NULL;
2113 }
2114
2115 static int init_status_page(struct intel_engine_cs *engine)
2116 {
2117 struct drm_i915_gem_object *obj = engine->status_page.obj;
2118
2119 if (obj == NULL) {
2120 unsigned flags;
2121 int ret;
2122
2123 obj = i915_gem_object_create(engine->i915->dev, 4096);
2124 if (IS_ERR(obj)) {
2125 DRM_ERROR("Failed to allocate status page\n");
2126 return PTR_ERR(obj);
2127 }
2128
2129 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2130 if (ret)
2131 goto err_unref;
2132
2133 flags = 0;
2134 if (!HAS_LLC(engine->i915))
2135 /* On g33, we cannot place HWS above 256MiB, so
2136 * restrict its pinning to the low mappable arena.
2137 * Though this restriction is not documented for
2138 * gen4, gen5, or byt, they also behave similarly
2139 * and hang if the HWS is placed at the top of the
2140 * GTT. To generalise, it appears that all !llc
2141 * platforms have issues with us placing the HWS
2142 * above the mappable region (even though we never
2143 * actualy map it).
2144 */
2145 flags |= PIN_MAPPABLE;
2146 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2147 if (ret) {
2148 err_unref:
2149 drm_gem_object_unreference(&obj->base);
2150 return ret;
2151 }
2152
2153 engine->status_page.obj = obj;
2154 }
2155
2156 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2157 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2158 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2159
2160 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2161 engine->name, engine->status_page.gfx_addr);
2162
2163 return 0;
2164 }
2165
2166 static int init_phys_status_page(struct intel_engine_cs *engine)
2167 {
2168 struct drm_i915_private *dev_priv = engine->i915;
2169
2170 if (!dev_priv->status_page_dmah) {
2171 dev_priv->status_page_dmah =
2172 drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
2173 if (!dev_priv->status_page_dmah)
2174 return -ENOMEM;
2175 }
2176
2177 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2178 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2179
2180 return 0;
2181 }
2182
2183 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2184 {
2185 GEM_BUG_ON(ringbuf->vma == NULL);
2186 GEM_BUG_ON(ringbuf->virtual_start == NULL);
2187
2188 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2189 i915_gem_object_unpin_map(ringbuf->obj);
2190 else
2191 i915_vma_unpin_iomap(ringbuf->vma);
2192 ringbuf->virtual_start = NULL;
2193
2194 i915_gem_object_ggtt_unpin(ringbuf->obj);
2195 ringbuf->vma = NULL;
2196 }
2197
2198 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
2199 struct intel_ringbuffer *ringbuf)
2200 {
2201 struct drm_i915_gem_object *obj = ringbuf->obj;
2202 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2203 unsigned flags = PIN_OFFSET_BIAS | 4096;
2204 void *addr;
2205 int ret;
2206
2207 if (HAS_LLC(dev_priv) && !obj->stolen) {
2208 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2209 if (ret)
2210 return ret;
2211
2212 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2213 if (ret)
2214 goto err_unpin;
2215
2216 addr = i915_gem_object_pin_map(obj);
2217 if (IS_ERR(addr)) {
2218 ret = PTR_ERR(addr);
2219 goto err_unpin;
2220 }
2221 } else {
2222 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2223 flags | PIN_MAPPABLE);
2224 if (ret)
2225 return ret;
2226
2227 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2228 if (ret)
2229 goto err_unpin;
2230
2231 /* Access through the GTT requires the device to be awake. */
2232 assert_rpm_wakelock_held(dev_priv);
2233
2234 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2235 if (IS_ERR(addr)) {
2236 ret = PTR_ERR(addr);
2237 goto err_unpin;
2238 }
2239 }
2240
2241 ringbuf->virtual_start = addr;
2242 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2243 return 0;
2244
2245 err_unpin:
2246 i915_gem_object_ggtt_unpin(obj);
2247 return ret;
2248 }
2249
2250 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2251 {
2252 drm_gem_object_unreference(&ringbuf->obj->base);
2253 ringbuf->obj = NULL;
2254 }
2255
2256 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2257 struct intel_ringbuffer *ringbuf)
2258 {
2259 struct drm_i915_gem_object *obj;
2260
2261 obj = NULL;
2262 if (!HAS_LLC(dev))
2263 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2264 if (obj == NULL)
2265 obj = i915_gem_object_create(dev, ringbuf->size);
2266 if (IS_ERR(obj))
2267 return PTR_ERR(obj);
2268
2269 /* mark ring buffers as read-only from GPU side by default */
2270 obj->gt_ro = 1;
2271
2272 ringbuf->obj = obj;
2273
2274 return 0;
2275 }
2276
2277 struct intel_ringbuffer *
2278 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2279 {
2280 struct intel_ringbuffer *ring;
2281 int ret;
2282
2283 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2284 if (ring == NULL) {
2285 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2286 engine->name);
2287 return ERR_PTR(-ENOMEM);
2288 }
2289
2290 ring->engine = engine;
2291 list_add(&ring->link, &engine->buffers);
2292
2293 ring->size = size;
2294 /* Workaround an erratum on the i830 which causes a hang if
2295 * the TAIL pointer points to within the last 2 cachelines
2296 * of the buffer.
2297 */
2298 ring->effective_size = size;
2299 if (IS_I830(engine->i915) || IS_845G(engine->i915))
2300 ring->effective_size -= 2 * CACHELINE_BYTES;
2301
2302 ring->last_retired_head = -1;
2303 intel_ring_update_space(ring);
2304
2305 ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
2306 if (ret) {
2307 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2308 engine->name, ret);
2309 list_del(&ring->link);
2310 kfree(ring);
2311 return ERR_PTR(ret);
2312 }
2313
2314 return ring;
2315 }
2316
2317 void
2318 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2319 {
2320 intel_destroy_ringbuffer_obj(ring);
2321 list_del(&ring->link);
2322 kfree(ring);
2323 }
2324
2325 static int intel_ring_context_pin(struct i915_gem_context *ctx,
2326 struct intel_engine_cs *engine)
2327 {
2328 struct intel_context *ce = &ctx->engine[engine->id];
2329 int ret;
2330
2331 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
2332
2333 if (ce->pin_count++)
2334 return 0;
2335
2336 if (ce->state) {
2337 ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
2338 if (ret)
2339 goto error;
2340 }
2341
2342 /* The kernel context is only used as a placeholder for flushing the
2343 * active context. It is never used for submitting user rendering and
2344 * as such never requires the golden render context, and so we can skip
2345 * emitting it when we switch to the kernel context. This is required
2346 * as during eviction we cannot allocate and pin the renderstate in
2347 * order to initialise the context.
2348 */
2349 if (ctx == ctx->i915->kernel_context)
2350 ce->initialised = true;
2351
2352 i915_gem_context_reference(ctx);
2353 return 0;
2354
2355 error:
2356 ce->pin_count = 0;
2357 return ret;
2358 }
2359
2360 static void intel_ring_context_unpin(struct i915_gem_context *ctx,
2361 struct intel_engine_cs *engine)
2362 {
2363 struct intel_context *ce = &ctx->engine[engine->id];
2364
2365 lockdep_assert_held(&ctx->i915->dev->struct_mutex);
2366
2367 if (--ce->pin_count)
2368 return;
2369
2370 if (ce->state)
2371 i915_gem_object_ggtt_unpin(ce->state);
2372
2373 i915_gem_context_unreference(ctx);
2374 }
2375
2376 static int intel_init_ring_buffer(struct drm_device *dev,
2377 struct intel_engine_cs *engine)
2378 {
2379 struct drm_i915_private *dev_priv = to_i915(dev);
2380 struct intel_ringbuffer *ringbuf;
2381 int ret;
2382
2383 WARN_ON(engine->buffer);
2384
2385 engine->i915 = dev_priv;
2386 INIT_LIST_HEAD(&engine->active_list);
2387 INIT_LIST_HEAD(&engine->request_list);
2388 INIT_LIST_HEAD(&engine->execlist_queue);
2389 INIT_LIST_HEAD(&engine->buffers);
2390 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2391 memset(engine->semaphore.sync_seqno, 0,
2392 sizeof(engine->semaphore.sync_seqno));
2393
2394 init_waitqueue_head(&engine->irq_queue);
2395
2396 /* We may need to do things with the shrinker which
2397 * require us to immediately switch back to the default
2398 * context. This can cause a problem as pinning the
2399 * default context also requires GTT space which may not
2400 * be available. To avoid this we always pin the default
2401 * context.
2402 */
2403 ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2404 if (ret)
2405 goto error;
2406
2407 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2408 if (IS_ERR(ringbuf)) {
2409 ret = PTR_ERR(ringbuf);
2410 goto error;
2411 }
2412 engine->buffer = ringbuf;
2413
2414 if (I915_NEED_GFX_HWS(dev_priv)) {
2415 ret = init_status_page(engine);
2416 if (ret)
2417 goto error;
2418 } else {
2419 WARN_ON(engine->id != RCS);
2420 ret = init_phys_status_page(engine);
2421 if (ret)
2422 goto error;
2423 }
2424
2425 ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
2426 if (ret) {
2427 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2428 engine->name, ret);
2429 intel_destroy_ringbuffer_obj(ringbuf);
2430 goto error;
2431 }
2432
2433 ret = i915_cmd_parser_init_ring(engine);
2434 if (ret)
2435 goto error;
2436
2437 return 0;
2438
2439 error:
2440 intel_cleanup_engine(engine);
2441 return ret;
2442 }
2443
2444 void intel_cleanup_engine(struct intel_engine_cs *engine)
2445 {
2446 struct drm_i915_private *dev_priv;
2447
2448 if (!intel_engine_initialized(engine))
2449 return;
2450
2451 dev_priv = engine->i915;
2452
2453 if (engine->buffer) {
2454 intel_stop_engine(engine);
2455 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2456
2457 intel_unpin_ringbuffer_obj(engine->buffer);
2458 intel_ringbuffer_free(engine->buffer);
2459 engine->buffer = NULL;
2460 }
2461
2462 if (engine->cleanup)
2463 engine->cleanup(engine);
2464
2465 if (I915_NEED_GFX_HWS(dev_priv)) {
2466 cleanup_status_page(engine);
2467 } else {
2468 WARN_ON(engine->id != RCS);
2469 cleanup_phys_status_page(engine);
2470 }
2471
2472 i915_cmd_parser_fini_ring(engine);
2473 i915_gem_batch_pool_fini(&engine->batch_pool);
2474
2475 intel_ring_context_unpin(dev_priv->kernel_context, engine);
2476
2477 engine->i915 = NULL;
2478 }
2479
2480 int intel_engine_idle(struct intel_engine_cs *engine)
2481 {
2482 struct drm_i915_gem_request *req;
2483
2484 /* Wait upon the last request to be completed */
2485 if (list_empty(&engine->request_list))
2486 return 0;
2487
2488 req = list_entry(engine->request_list.prev,
2489 struct drm_i915_gem_request,
2490 list);
2491
2492 /* Make sure we do not trigger any retires */
2493 return __i915_wait_request(req,
2494 req->i915->mm.interruptible,
2495 NULL, NULL);
2496 }
2497
2498 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2499 {
2500 int ret;
2501
2502 /* Flush enough space to reduce the likelihood of waiting after
2503 * we start building the request - in which case we will just
2504 * have to repeat work.
2505 */
2506 request->reserved_space += LEGACY_REQUEST_SIZE;
2507
2508 request->ringbuf = request->engine->buffer;
2509
2510 ret = intel_ring_begin(request, 0);
2511 if (ret)
2512 return ret;
2513
2514 request->reserved_space -= LEGACY_REQUEST_SIZE;
2515 return 0;
2516 }
2517
2518 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2519 {
2520 struct intel_ringbuffer *ringbuf = req->ringbuf;
2521 struct intel_engine_cs *engine = req->engine;
2522 struct drm_i915_gem_request *target;
2523
2524 intel_ring_update_space(ringbuf);
2525 if (ringbuf->space >= bytes)
2526 return 0;
2527
2528 /*
2529 * Space is reserved in the ringbuffer for finalising the request,
2530 * as that cannot be allowed to fail. During request finalisation,
2531 * reserved_space is set to 0 to stop the overallocation and the
2532 * assumption is that then we never need to wait (which has the
2533 * risk of failing with EINTR).
2534 *
2535 * See also i915_gem_request_alloc() and i915_add_request().
2536 */
2537 GEM_BUG_ON(!req->reserved_space);
2538
2539 list_for_each_entry(target, &engine->request_list, list) {
2540 unsigned space;
2541
2542 /*
2543 * The request queue is per-engine, so can contain requests
2544 * from multiple ringbuffers. Here, we must ignore any that
2545 * aren't from the ringbuffer we're considering.
2546 */
2547 if (target->ringbuf != ringbuf)
2548 continue;
2549
2550 /* Would completion of this request free enough space? */
2551 space = __intel_ring_space(target->postfix, ringbuf->tail,
2552 ringbuf->size);
2553 if (space >= bytes)
2554 break;
2555 }
2556
2557 if (WARN_ON(&target->list == &engine->request_list))
2558 return -ENOSPC;
2559
2560 return i915_wait_request(target);
2561 }
2562
2563 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2564 {
2565 struct intel_ringbuffer *ringbuf = req->ringbuf;
2566 int remain_actual = ringbuf->size - ringbuf->tail;
2567 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2568 int bytes = num_dwords * sizeof(u32);
2569 int total_bytes, wait_bytes;
2570 bool need_wrap = false;
2571
2572 total_bytes = bytes + req->reserved_space;
2573
2574 if (unlikely(bytes > remain_usable)) {
2575 /*
2576 * Not enough space for the basic request. So need to flush
2577 * out the remainder and then wait for base + reserved.
2578 */
2579 wait_bytes = remain_actual + total_bytes;
2580 need_wrap = true;
2581 } else if (unlikely(total_bytes > remain_usable)) {
2582 /*
2583 * The base request will fit but the reserved space
2584 * falls off the end. So we don't need an immediate wrap
2585 * and only need to effectively wait for the reserved
2586 * size space from the start of ringbuffer.
2587 */
2588 wait_bytes = remain_actual + req->reserved_space;
2589 } else {
2590 /* No wrapping required, just waiting. */
2591 wait_bytes = total_bytes;
2592 }
2593
2594 if (wait_bytes > ringbuf->space) {
2595 int ret = wait_for_space(req, wait_bytes);
2596 if (unlikely(ret))
2597 return ret;
2598
2599 intel_ring_update_space(ringbuf);
2600 if (unlikely(ringbuf->space < wait_bytes))
2601 return -EAGAIN;
2602 }
2603
2604 if (unlikely(need_wrap)) {
2605 GEM_BUG_ON(remain_actual > ringbuf->space);
2606 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2607
2608 /* Fill the tail with MI_NOOP */
2609 memset(ringbuf->virtual_start + ringbuf->tail,
2610 0, remain_actual);
2611 ringbuf->tail = 0;
2612 ringbuf->space -= remain_actual;
2613 }
2614
2615 ringbuf->space -= bytes;
2616 GEM_BUG_ON(ringbuf->space < 0);
2617 return 0;
2618 }
2619
2620 /* Align the ring tail to a cacheline boundary */
2621 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2622 {
2623 struct intel_engine_cs *engine = req->engine;
2624 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2625 int ret;
2626
2627 if (num_dwords == 0)
2628 return 0;
2629
2630 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2631 ret = intel_ring_begin(req, num_dwords);
2632 if (ret)
2633 return ret;
2634
2635 while (num_dwords--)
2636 intel_ring_emit(engine, MI_NOOP);
2637
2638 intel_ring_advance(engine);
2639
2640 return 0;
2641 }
2642
2643 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2644 {
2645 struct drm_i915_private *dev_priv = engine->i915;
2646
2647 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2648 * so long as the semaphore value in the register/page is greater
2649 * than the sync value), so whenever we reset the seqno,
2650 * so long as we reset the tracking semaphore value to 0, it will
2651 * always be before the next request's seqno. If we don't reset
2652 * the semaphore value, then when the seqno moves backwards all
2653 * future waits will complete instantly (causing rendering corruption).
2654 */
2655 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2656 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2657 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2658 if (HAS_VEBOX(dev_priv))
2659 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2660 }
2661 if (dev_priv->semaphore_obj) {
2662 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2663 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2664 void *semaphores = kmap(page);
2665 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2666 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2667 kunmap(page);
2668 }
2669 memset(engine->semaphore.sync_seqno, 0,
2670 sizeof(engine->semaphore.sync_seqno));
2671
2672 engine->set_seqno(engine, seqno);
2673 engine->last_submitted_seqno = seqno;
2674
2675 engine->hangcheck.seqno = seqno;
2676 }
2677
2678 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2679 u32 value)
2680 {
2681 struct drm_i915_private *dev_priv = engine->i915;
2682
2683 /* Every tail move must follow the sequence below */
2684
2685 /* Disable notification that the ring is IDLE. The GT
2686 * will then assume that it is busy and bring it out of rc6.
2687 */
2688 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2689 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2690
2691 /* Clear the context id. Here be magic! */
2692 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2693
2694 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2695 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2696 GEN6_BSD_SLEEP_INDICATOR) == 0,
2697 50))
2698 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2699
2700 /* Now that the ring is fully powered up, update the tail */
2701 I915_WRITE_TAIL(engine, value);
2702 POSTING_READ(RING_TAIL(engine->mmio_base));
2703
2704 /* Let the ring send IDLE messages to the GT again,
2705 * and so let it sleep to conserve power when idle.
2706 */
2707 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2708 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2709 }
2710
2711 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2712 u32 invalidate, u32 flush)
2713 {
2714 struct intel_engine_cs *engine = req->engine;
2715 uint32_t cmd;
2716 int ret;
2717
2718 ret = intel_ring_begin(req, 4);
2719 if (ret)
2720 return ret;
2721
2722 cmd = MI_FLUSH_DW;
2723 if (INTEL_GEN(req->i915) >= 8)
2724 cmd += 1;
2725
2726 /* We always require a command barrier so that subsequent
2727 * commands, such as breadcrumb interrupts, are strictly ordered
2728 * wrt the contents of the write cache being flushed to memory
2729 * (and thus being coherent from the CPU).
2730 */
2731 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2732
2733 /*
2734 * Bspec vol 1c.5 - video engine command streamer:
2735 * "If ENABLED, all TLBs will be invalidated once the flush
2736 * operation is complete. This bit is only valid when the
2737 * Post-Sync Operation field is a value of 1h or 3h."
2738 */
2739 if (invalidate & I915_GEM_GPU_DOMAINS)
2740 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2741
2742 intel_ring_emit(engine, cmd);
2743 intel_ring_emit(engine,
2744 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2745 if (INTEL_GEN(req->i915) >= 8) {
2746 intel_ring_emit(engine, 0); /* upper addr */
2747 intel_ring_emit(engine, 0); /* value */
2748 } else {
2749 intel_ring_emit(engine, 0);
2750 intel_ring_emit(engine, MI_NOOP);
2751 }
2752 intel_ring_advance(engine);
2753 return 0;
2754 }
2755
2756 static int
2757 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2758 u64 offset, u32 len,
2759 unsigned dispatch_flags)
2760 {
2761 struct intel_engine_cs *engine = req->engine;
2762 bool ppgtt = USES_PPGTT(engine->dev) &&
2763 !(dispatch_flags & I915_DISPATCH_SECURE);
2764 int ret;
2765
2766 ret = intel_ring_begin(req, 4);
2767 if (ret)
2768 return ret;
2769
2770 /* FIXME(BDW): Address space and security selectors. */
2771 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2772 (dispatch_flags & I915_DISPATCH_RS ?
2773 MI_BATCH_RESOURCE_STREAMER : 0));
2774 intel_ring_emit(engine, lower_32_bits(offset));
2775 intel_ring_emit(engine, upper_32_bits(offset));
2776 intel_ring_emit(engine, MI_NOOP);
2777 intel_ring_advance(engine);
2778
2779 return 0;
2780 }
2781
2782 static int
2783 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2784 u64 offset, u32 len,
2785 unsigned dispatch_flags)
2786 {
2787 struct intel_engine_cs *engine = req->engine;
2788 int ret;
2789
2790 ret = intel_ring_begin(req, 2);
2791 if (ret)
2792 return ret;
2793
2794 intel_ring_emit(engine,
2795 MI_BATCH_BUFFER_START |
2796 (dispatch_flags & I915_DISPATCH_SECURE ?
2797 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2798 (dispatch_flags & I915_DISPATCH_RS ?
2799 MI_BATCH_RESOURCE_STREAMER : 0));
2800 /* bit0-7 is the length on GEN6+ */
2801 intel_ring_emit(engine, offset);
2802 intel_ring_advance(engine);
2803
2804 return 0;
2805 }
2806
2807 static int
2808 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2809 u64 offset, u32 len,
2810 unsigned dispatch_flags)
2811 {
2812 struct intel_engine_cs *engine = req->engine;
2813 int ret;
2814
2815 ret = intel_ring_begin(req, 2);
2816 if (ret)
2817 return ret;
2818
2819 intel_ring_emit(engine,
2820 MI_BATCH_BUFFER_START |
2821 (dispatch_flags & I915_DISPATCH_SECURE ?
2822 0 : MI_BATCH_NON_SECURE_I965));
2823 /* bit0-7 is the length on GEN6+ */
2824 intel_ring_emit(engine, offset);
2825 intel_ring_advance(engine);
2826
2827 return 0;
2828 }
2829
2830 /* Blitter support (SandyBridge+) */
2831
2832 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2833 u32 invalidate, u32 flush)
2834 {
2835 struct intel_engine_cs *engine = req->engine;
2836 uint32_t cmd;
2837 int ret;
2838
2839 ret = intel_ring_begin(req, 4);
2840 if (ret)
2841 return ret;
2842
2843 cmd = MI_FLUSH_DW;
2844 if (INTEL_GEN(req->i915) >= 8)
2845 cmd += 1;
2846
2847 /* We always require a command barrier so that subsequent
2848 * commands, such as breadcrumb interrupts, are strictly ordered
2849 * wrt the contents of the write cache being flushed to memory
2850 * (and thus being coherent from the CPU).
2851 */
2852 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2853
2854 /*
2855 * Bspec vol 1c.3 - blitter engine command streamer:
2856 * "If ENABLED, all TLBs will be invalidated once the flush
2857 * operation is complete. This bit is only valid when the
2858 * Post-Sync Operation field is a value of 1h or 3h."
2859 */
2860 if (invalidate & I915_GEM_DOMAIN_RENDER)
2861 cmd |= MI_INVALIDATE_TLB;
2862 intel_ring_emit(engine, cmd);
2863 intel_ring_emit(engine,
2864 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2865 if (INTEL_GEN(req->i915) >= 8) {
2866 intel_ring_emit(engine, 0); /* upper addr */
2867 intel_ring_emit(engine, 0); /* value */
2868 } else {
2869 intel_ring_emit(engine, 0);
2870 intel_ring_emit(engine, MI_NOOP);
2871 }
2872 intel_ring_advance(engine);
2873
2874 return 0;
2875 }
2876
2877 int intel_init_render_ring_buffer(struct drm_device *dev)
2878 {
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2880 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2881 struct drm_i915_gem_object *obj;
2882 int ret;
2883
2884 engine->name = "render ring";
2885 engine->id = RCS;
2886 engine->exec_id = I915_EXEC_RENDER;
2887 engine->hw_id = 0;
2888 engine->mmio_base = RENDER_RING_BASE;
2889
2890 if (INTEL_GEN(dev_priv) >= 8) {
2891 if (i915_semaphore_is_enabled(dev_priv)) {
2892 obj = i915_gem_object_create(dev, 4096);
2893 if (IS_ERR(obj)) {
2894 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2895 i915.semaphores = 0;
2896 } else {
2897 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2898 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2899 if (ret != 0) {
2900 drm_gem_object_unreference(&obj->base);
2901 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2902 i915.semaphores = 0;
2903 } else
2904 dev_priv->semaphore_obj = obj;
2905 }
2906 }
2907
2908 engine->init_context = intel_rcs_ctx_init;
2909 engine->add_request = gen8_render_add_request;
2910 engine->flush = gen8_render_ring_flush;
2911 engine->irq_get = gen8_ring_get_irq;
2912 engine->irq_put = gen8_ring_put_irq;
2913 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2914 engine->get_seqno = ring_get_seqno;
2915 engine->set_seqno = ring_set_seqno;
2916 if (i915_semaphore_is_enabled(dev_priv)) {
2917 WARN_ON(!dev_priv->semaphore_obj);
2918 engine->semaphore.sync_to = gen8_ring_sync;
2919 engine->semaphore.signal = gen8_rcs_signal;
2920 GEN8_RING_SEMAPHORE_INIT(engine);
2921 }
2922 } else if (INTEL_GEN(dev_priv) >= 6) {
2923 engine->init_context = intel_rcs_ctx_init;
2924 engine->add_request = gen6_add_request;
2925 engine->flush = gen7_render_ring_flush;
2926 if (IS_GEN6(dev_priv))
2927 engine->flush = gen6_render_ring_flush;
2928 engine->irq_get = gen6_ring_get_irq;
2929 engine->irq_put = gen6_ring_put_irq;
2930 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2931 engine->irq_seqno_barrier = gen6_seqno_barrier;
2932 engine->get_seqno = ring_get_seqno;
2933 engine->set_seqno = ring_set_seqno;
2934 if (i915_semaphore_is_enabled(dev_priv)) {
2935 engine->semaphore.sync_to = gen6_ring_sync;
2936 engine->semaphore.signal = gen6_signal;
2937 /*
2938 * The current semaphore is only applied on pre-gen8
2939 * platform. And there is no VCS2 ring on the pre-gen8
2940 * platform. So the semaphore between RCS and VCS2 is
2941 * initialized as INVALID. Gen8 will initialize the
2942 * sema between VCS2 and RCS later.
2943 */
2944 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2945 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2946 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2947 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2948 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2949 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2950 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2951 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2952 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2953 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2954 }
2955 } else if (IS_GEN5(dev_priv)) {
2956 engine->add_request = pc_render_add_request;
2957 engine->flush = gen4_render_ring_flush;
2958 engine->get_seqno = pc_render_get_seqno;
2959 engine->set_seqno = pc_render_set_seqno;
2960 engine->irq_get = gen5_ring_get_irq;
2961 engine->irq_put = gen5_ring_put_irq;
2962 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2963 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2964 } else {
2965 engine->add_request = i9xx_add_request;
2966 if (INTEL_GEN(dev_priv) < 4)
2967 engine->flush = gen2_render_ring_flush;
2968 else
2969 engine->flush = gen4_render_ring_flush;
2970 engine->get_seqno = ring_get_seqno;
2971 engine->set_seqno = ring_set_seqno;
2972 if (IS_GEN2(dev_priv)) {
2973 engine->irq_get = i8xx_ring_get_irq;
2974 engine->irq_put = i8xx_ring_put_irq;
2975 } else {
2976 engine->irq_get = i9xx_ring_get_irq;
2977 engine->irq_put = i9xx_ring_put_irq;
2978 }
2979 engine->irq_enable_mask = I915_USER_INTERRUPT;
2980 }
2981 engine->write_tail = ring_write_tail;
2982
2983 if (IS_HASWELL(dev_priv))
2984 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2985 else if (IS_GEN8(dev_priv))
2986 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2987 else if (INTEL_GEN(dev_priv) >= 6)
2988 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2989 else if (INTEL_GEN(dev_priv) >= 4)
2990 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2991 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2992 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2993 else
2994 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2995 engine->init_hw = init_render_ring;
2996 engine->cleanup = render_ring_cleanup;
2997
2998 /* Workaround batchbuffer to combat CS tlb bug. */
2999 if (HAS_BROKEN_CS_TLB(dev_priv)) {
3000 obj = i915_gem_object_create(dev, I830_WA_SIZE);
3001 if (IS_ERR(obj)) {
3002 DRM_ERROR("Failed to allocate batch bo\n");
3003 return PTR_ERR(obj);
3004 }
3005
3006 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
3007 if (ret != 0) {
3008 drm_gem_object_unreference(&obj->base);
3009 DRM_ERROR("Failed to ping batch bo\n");
3010 return ret;
3011 }
3012
3013 engine->scratch.obj = obj;
3014 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
3015 }
3016
3017 ret = intel_init_ring_buffer(dev, engine);
3018 if (ret)
3019 return ret;
3020
3021 if (INTEL_GEN(dev_priv) >= 5) {
3022 ret = intel_init_pipe_control(engine);
3023 if (ret)
3024 return ret;
3025 }
3026
3027 return 0;
3028 }
3029
3030 int intel_init_bsd_ring_buffer(struct drm_device *dev)
3031 {
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
3034
3035 engine->name = "bsd ring";
3036 engine->id = VCS;
3037 engine->exec_id = I915_EXEC_BSD;
3038 engine->hw_id = 1;
3039
3040 engine->write_tail = ring_write_tail;
3041 if (INTEL_GEN(dev_priv) >= 6) {
3042 engine->mmio_base = GEN6_BSD_RING_BASE;
3043 /* gen6 bsd needs a special wa for tail updates */
3044 if (IS_GEN6(dev_priv))
3045 engine->write_tail = gen6_bsd_ring_write_tail;
3046 engine->flush = gen6_bsd_ring_flush;
3047 engine->add_request = gen6_add_request;
3048 engine->irq_seqno_barrier = gen6_seqno_barrier;
3049 engine->get_seqno = ring_get_seqno;
3050 engine->set_seqno = ring_set_seqno;
3051 if (INTEL_GEN(dev_priv) >= 8) {
3052 engine->irq_enable_mask =
3053 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
3054 engine->irq_get = gen8_ring_get_irq;
3055 engine->irq_put = gen8_ring_put_irq;
3056 engine->dispatch_execbuffer =
3057 gen8_ring_dispatch_execbuffer;
3058 if (i915_semaphore_is_enabled(dev_priv)) {
3059 engine->semaphore.sync_to = gen8_ring_sync;
3060 engine->semaphore.signal = gen8_xcs_signal;
3061 GEN8_RING_SEMAPHORE_INIT(engine);
3062 }
3063 } else {
3064 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
3065 engine->irq_get = gen6_ring_get_irq;
3066 engine->irq_put = gen6_ring_put_irq;
3067 engine->dispatch_execbuffer =
3068 gen6_ring_dispatch_execbuffer;
3069 if (i915_semaphore_is_enabled(dev_priv)) {
3070 engine->semaphore.sync_to = gen6_ring_sync;
3071 engine->semaphore.signal = gen6_signal;
3072 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
3073 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
3074 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
3075 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
3076 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3077 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
3078 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
3079 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
3080 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
3081 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3082 }
3083 }
3084 } else {
3085 engine->mmio_base = BSD_RING_BASE;
3086 engine->flush = bsd_ring_flush;
3087 engine->add_request = i9xx_add_request;
3088 engine->get_seqno = ring_get_seqno;
3089 engine->set_seqno = ring_set_seqno;
3090 if (IS_GEN5(dev_priv)) {
3091 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
3092 engine->irq_get = gen5_ring_get_irq;
3093 engine->irq_put = gen5_ring_put_irq;
3094 } else {
3095 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
3096 engine->irq_get = i9xx_ring_get_irq;
3097 engine->irq_put = i9xx_ring_put_irq;
3098 }
3099 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
3100 }
3101 engine->init_hw = init_ring_common;
3102
3103 return intel_init_ring_buffer(dev, engine);
3104 }
3105
3106 /**
3107 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3108 */
3109 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3110 {
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3113
3114 engine->name = "bsd2 ring";
3115 engine->id = VCS2;
3116 engine->exec_id = I915_EXEC_BSD;
3117 engine->hw_id = 4;
3118
3119 engine->write_tail = ring_write_tail;
3120 engine->mmio_base = GEN8_BSD2_RING_BASE;
3121 engine->flush = gen6_bsd_ring_flush;
3122 engine->add_request = gen6_add_request;
3123 engine->irq_seqno_barrier = gen6_seqno_barrier;
3124 engine->get_seqno = ring_get_seqno;
3125 engine->set_seqno = ring_set_seqno;
3126 engine->irq_enable_mask =
3127 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3128 engine->irq_get = gen8_ring_get_irq;
3129 engine->irq_put = gen8_ring_put_irq;
3130 engine->dispatch_execbuffer =
3131 gen8_ring_dispatch_execbuffer;
3132 if (i915_semaphore_is_enabled(dev_priv)) {
3133 engine->semaphore.sync_to = gen8_ring_sync;
3134 engine->semaphore.signal = gen8_xcs_signal;
3135 GEN8_RING_SEMAPHORE_INIT(engine);
3136 }
3137 engine->init_hw = init_ring_common;
3138
3139 return intel_init_ring_buffer(dev, engine);
3140 }
3141
3142 int intel_init_blt_ring_buffer(struct drm_device *dev)
3143 {
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3146
3147 engine->name = "blitter ring";
3148 engine->id = BCS;
3149 engine->exec_id = I915_EXEC_BLT;
3150 engine->hw_id = 2;
3151
3152 engine->mmio_base = BLT_RING_BASE;
3153 engine->write_tail = ring_write_tail;
3154 engine->flush = gen6_ring_flush;
3155 engine->add_request = gen6_add_request;
3156 engine->irq_seqno_barrier = gen6_seqno_barrier;
3157 engine->get_seqno = ring_get_seqno;
3158 engine->set_seqno = ring_set_seqno;
3159 if (INTEL_GEN(dev_priv) >= 8) {
3160 engine->irq_enable_mask =
3161 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3162 engine->irq_get = gen8_ring_get_irq;
3163 engine->irq_put = gen8_ring_put_irq;
3164 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3165 if (i915_semaphore_is_enabled(dev_priv)) {
3166 engine->semaphore.sync_to = gen8_ring_sync;
3167 engine->semaphore.signal = gen8_xcs_signal;
3168 GEN8_RING_SEMAPHORE_INIT(engine);
3169 }
3170 } else {
3171 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3172 engine->irq_get = gen6_ring_get_irq;
3173 engine->irq_put = gen6_ring_put_irq;
3174 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3175 if (i915_semaphore_is_enabled(dev_priv)) {
3176 engine->semaphore.signal = gen6_signal;
3177 engine->semaphore.sync_to = gen6_ring_sync;
3178 /*
3179 * The current semaphore is only applied on pre-gen8
3180 * platform. And there is no VCS2 ring on the pre-gen8
3181 * platform. So the semaphore between BCS and VCS2 is
3182 * initialized as INVALID. Gen8 will initialize the
3183 * sema between BCS and VCS2 later.
3184 */
3185 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3186 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3187 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3188 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3189 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3190 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3191 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3192 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3193 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3194 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3195 }
3196 }
3197 engine->init_hw = init_ring_common;
3198
3199 return intel_init_ring_buffer(dev, engine);
3200 }
3201
3202 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3203 {
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3206
3207 engine->name = "video enhancement ring";
3208 engine->id = VECS;
3209 engine->exec_id = I915_EXEC_VEBOX;
3210 engine->hw_id = 3;
3211
3212 engine->mmio_base = VEBOX_RING_BASE;
3213 engine->write_tail = ring_write_tail;
3214 engine->flush = gen6_ring_flush;
3215 engine->add_request = gen6_add_request;
3216 engine->irq_seqno_barrier = gen6_seqno_barrier;
3217 engine->get_seqno = ring_get_seqno;
3218 engine->set_seqno = ring_set_seqno;
3219
3220 if (INTEL_GEN(dev_priv) >= 8) {
3221 engine->irq_enable_mask =
3222 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3223 engine->irq_get = gen8_ring_get_irq;
3224 engine->irq_put = gen8_ring_put_irq;
3225 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3226 if (i915_semaphore_is_enabled(dev_priv)) {
3227 engine->semaphore.sync_to = gen8_ring_sync;
3228 engine->semaphore.signal = gen8_xcs_signal;
3229 GEN8_RING_SEMAPHORE_INIT(engine);
3230 }
3231 } else {
3232 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3233 engine->irq_get = hsw_vebox_get_irq;
3234 engine->irq_put = hsw_vebox_put_irq;
3235 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3236 if (i915_semaphore_is_enabled(dev_priv)) {
3237 engine->semaphore.sync_to = gen6_ring_sync;
3238 engine->semaphore.signal = gen6_signal;
3239 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3240 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3241 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3242 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3243 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3244 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3245 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3246 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3247 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3248 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3249 }
3250 }
3251 engine->init_hw = init_ring_common;
3252
3253 return intel_init_ring_buffer(dev, engine);
3254 }
3255
3256 int
3257 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3258 {
3259 struct intel_engine_cs *engine = req->engine;
3260 int ret;
3261
3262 if (!engine->gpu_caches_dirty)
3263 return 0;
3264
3265 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3266 if (ret)
3267 return ret;
3268
3269 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3270
3271 engine->gpu_caches_dirty = false;
3272 return 0;
3273 }
3274
3275 int
3276 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3277 {
3278 struct intel_engine_cs *engine = req->engine;
3279 uint32_t flush_domains;
3280 int ret;
3281
3282 flush_domains = 0;
3283 if (engine->gpu_caches_dirty)
3284 flush_domains = I915_GEM_GPU_DOMAINS;
3285
3286 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3287 if (ret)
3288 return ret;
3289
3290 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3291
3292 engine->gpu_caches_dirty = false;
3293 return 0;
3294 }
3295
3296 void
3297 intel_stop_engine(struct intel_engine_cs *engine)
3298 {
3299 int ret;
3300
3301 if (!intel_engine_initialized(engine))
3302 return;
3303
3304 ret = intel_engine_idle(engine);
3305 if (ret)
3306 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3307 engine->name, ret);
3308
3309 stop_ring(engine);
3310 }
Linux kernel - Deliverables
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