2 * i.MX drm driver - LVDS display bridge
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/module.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
20 #include <drm/drm_fb_helper.h>
21 #include <drm/drm_crtc_helper.h>
22 #include <drm/drm_panel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
25 #include <linux/of_device.h>
26 #include <linux/of_graph.h>
27 #include <video/of_videomode.h>
28 #include <linux/regmap.h>
29 #include <linux/videodev2.h>
33 #define DRIVER_NAME "imx-ldb"
35 #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
36 #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
37 #define LDB_CH0_MODE_EN_MASK (3 << 0)
38 #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
39 #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
40 #define LDB_CH1_MODE_EN_MASK (3 << 2)
41 #define LDB_SPLIT_MODE_EN (1 << 4)
42 #define LDB_DATA_WIDTH_CH0_24 (1 << 5)
43 #define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
44 #define LDB_DATA_WIDTH_CH1_24 (1 << 7)
45 #define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
46 #define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
47 #define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
48 #define LDB_BGREF_RMODE_INT (1 << 15)
50 #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
51 #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
55 struct imx_ldb_channel
{
57 struct drm_connector connector
;
58 struct drm_encoder encoder
;
59 struct drm_panel
*panel
;
60 struct device_node
*child
;
64 struct drm_display_mode mode
;
76 struct regmap
*regmap
;
78 struct imx_ldb_channel channel
[2];
79 struct clk
*clk
[2]; /* our own clock */
80 struct clk
*clk_sel
[4]; /* parent of display clock */
81 struct clk
*clk_parent
[4]; /* original parent of clk_sel */
82 struct clk
*clk_pll
[2]; /* upstream clock we can adjust */
84 const struct bus_mux
*lvds_mux
;
87 static enum drm_connector_status
imx_ldb_connector_detect(
88 struct drm_connector
*connector
, bool force
)
90 return connector_status_connected
;
93 static int imx_ldb_connector_get_modes(struct drm_connector
*connector
)
95 struct imx_ldb_channel
*imx_ldb_ch
= con_to_imx_ldb_ch(connector
);
98 if (imx_ldb_ch
->panel
&& imx_ldb_ch
->panel
->funcs
&&
99 imx_ldb_ch
->panel
->funcs
->get_modes
) {
100 struct drm_display_info
*di
= &connector
->display_info
;
102 num_modes
= imx_ldb_ch
->panel
->funcs
->get_modes(imx_ldb_ch
->panel
);
103 if (!imx_ldb_ch
->bus_format
&& di
->num_bus_formats
)
104 imx_ldb_ch
->bus_format
= di
->bus_formats
[0];
109 if (imx_ldb_ch
->edid
) {
110 drm_mode_connector_update_edid_property(connector
,
112 num_modes
= drm_add_edid_modes(connector
, imx_ldb_ch
->edid
);
115 if (imx_ldb_ch
->mode_valid
) {
116 struct drm_display_mode
*mode
;
118 mode
= drm_mode_create(connector
->dev
);
121 drm_mode_copy(mode
, &imx_ldb_ch
->mode
);
122 mode
->type
|= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
123 drm_mode_probed_add(connector
, mode
);
130 static struct drm_encoder
*imx_ldb_connector_best_encoder(
131 struct drm_connector
*connector
)
133 struct imx_ldb_channel
*imx_ldb_ch
= con_to_imx_ldb_ch(connector
);
135 return &imx_ldb_ch
->encoder
;
138 static void imx_ldb_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
142 static void imx_ldb_set_clock(struct imx_ldb
*ldb
, int mux
, int chno
,
143 unsigned long serial_clk
, unsigned long di_clk
)
147 dev_dbg(ldb
->dev
, "%s: now: %ld want: %ld\n", __func__
,
148 clk_get_rate(ldb
->clk_pll
[chno
]), serial_clk
);
149 clk_set_rate(ldb
->clk_pll
[chno
], serial_clk
);
151 dev_dbg(ldb
->dev
, "%s after: %ld\n", __func__
,
152 clk_get_rate(ldb
->clk_pll
[chno
]));
154 dev_dbg(ldb
->dev
, "%s: now: %ld want: %ld\n", __func__
,
155 clk_get_rate(ldb
->clk
[chno
]),
157 clk_set_rate(ldb
->clk
[chno
], di_clk
);
159 dev_dbg(ldb
->dev
, "%s after: %ld\n", __func__
,
160 clk_get_rate(ldb
->clk
[chno
]));
162 /* set display clock mux to LDB input clock */
163 ret
= clk_set_parent(ldb
->clk_sel
[mux
], ldb
->clk
[chno
]);
166 "unable to set di%d parent clock to ldb_di%d\n", mux
,
170 static void imx_ldb_encoder_prepare(struct drm_encoder
*encoder
)
172 struct imx_ldb_channel
*imx_ldb_ch
= enc_to_imx_ldb_ch(encoder
);
173 struct imx_ldb
*ldb
= imx_ldb_ch
->ldb
;
174 int dual
= ldb
->ldb_ctrl
& LDB_SPLIT_MODE_EN
;
177 switch (imx_ldb_ch
->bus_format
) {
180 "could not determine data mapping, default to 18-bit \"spwg\"\n");
182 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
:
183 bus_format
= MEDIA_BUS_FMT_RGB666_1X18
;
185 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
:
186 bus_format
= MEDIA_BUS_FMT_RGB888_1X24
;
187 if (imx_ldb_ch
->chno
== 0 || dual
)
188 ldb
->ldb_ctrl
|= LDB_DATA_WIDTH_CH0_24
;
189 if (imx_ldb_ch
->chno
== 1 || dual
)
190 ldb
->ldb_ctrl
|= LDB_DATA_WIDTH_CH1_24
;
192 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
:
193 bus_format
= MEDIA_BUS_FMT_RGB888_1X24
;
194 if (imx_ldb_ch
->chno
== 0 || dual
)
195 ldb
->ldb_ctrl
|= LDB_DATA_WIDTH_CH0_24
|
196 LDB_BIT_MAP_CH0_JEIDA
;
197 if (imx_ldb_ch
->chno
== 1 || dual
)
198 ldb
->ldb_ctrl
|= LDB_DATA_WIDTH_CH1_24
|
199 LDB_BIT_MAP_CH1_JEIDA
;
203 imx_drm_set_bus_format(encoder
, bus_format
);
206 static void imx_ldb_encoder_commit(struct drm_encoder
*encoder
)
208 struct imx_ldb_channel
*imx_ldb_ch
= enc_to_imx_ldb_ch(encoder
);
209 struct imx_ldb
*ldb
= imx_ldb_ch
->ldb
;
210 int dual
= ldb
->ldb_ctrl
& LDB_SPLIT_MODE_EN
;
211 int mux
= imx_drm_encoder_get_mux_id(imx_ldb_ch
->child
, encoder
);
213 drm_panel_prepare(imx_ldb_ch
->panel
);
216 clk_prepare_enable(ldb
->clk
[0]);
217 clk_prepare_enable(ldb
->clk
[1]);
220 if (imx_ldb_ch
== &ldb
->channel
[0] || dual
) {
221 ldb
->ldb_ctrl
&= ~LDB_CH0_MODE_EN_MASK
;
222 if (mux
== 0 || ldb
->lvds_mux
)
223 ldb
->ldb_ctrl
|= LDB_CH0_MODE_EN_TO_DI0
;
225 ldb
->ldb_ctrl
|= LDB_CH0_MODE_EN_TO_DI1
;
227 if (imx_ldb_ch
== &ldb
->channel
[1] || dual
) {
228 ldb
->ldb_ctrl
&= ~LDB_CH1_MODE_EN_MASK
;
229 if (mux
== 1 || ldb
->lvds_mux
)
230 ldb
->ldb_ctrl
|= LDB_CH1_MODE_EN_TO_DI1
;
232 ldb
->ldb_ctrl
|= LDB_CH1_MODE_EN_TO_DI0
;
236 const struct bus_mux
*lvds_mux
= NULL
;
238 if (imx_ldb_ch
== &ldb
->channel
[0])
239 lvds_mux
= &ldb
->lvds_mux
[0];
240 else if (imx_ldb_ch
== &ldb
->channel
[1])
241 lvds_mux
= &ldb
->lvds_mux
[1];
243 regmap_update_bits(ldb
->regmap
, lvds_mux
->reg
, lvds_mux
->mask
,
244 mux
<< lvds_mux
->shift
);
247 regmap_write(ldb
->regmap
, IOMUXC_GPR2
, ldb
->ldb_ctrl
);
249 drm_panel_enable(imx_ldb_ch
->panel
);
252 static void imx_ldb_encoder_mode_set(struct drm_encoder
*encoder
,
253 struct drm_display_mode
*orig_mode
,
254 struct drm_display_mode
*mode
)
256 struct imx_ldb_channel
*imx_ldb_ch
= enc_to_imx_ldb_ch(encoder
);
257 struct imx_ldb
*ldb
= imx_ldb_ch
->ldb
;
258 int dual
= ldb
->ldb_ctrl
& LDB_SPLIT_MODE_EN
;
259 unsigned long serial_clk
;
260 unsigned long di_clk
= mode
->clock
* 1000;
261 int mux
= imx_drm_encoder_get_mux_id(imx_ldb_ch
->child
, encoder
);
263 if (mode
->clock
> 170000) {
265 "%s: mode exceeds 170 MHz pixel clock\n", __func__
);
267 if (mode
->clock
> 85000 && !dual
) {
269 "%s: mode exceeds 85 MHz pixel clock\n", __func__
);
273 serial_clk
= 3500UL * mode
->clock
;
274 imx_ldb_set_clock(ldb
, mux
, 0, serial_clk
, di_clk
);
275 imx_ldb_set_clock(ldb
, mux
, 1, serial_clk
, di_clk
);
277 serial_clk
= 7000UL * mode
->clock
;
278 imx_ldb_set_clock(ldb
, mux
, imx_ldb_ch
->chno
, serial_clk
,
282 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
283 if (imx_ldb_ch
== &ldb
->channel
[0]) {
284 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
285 ldb
->ldb_ctrl
|= LDB_DI0_VS_POL_ACT_LOW
;
286 else if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
287 ldb
->ldb_ctrl
&= ~LDB_DI0_VS_POL_ACT_LOW
;
289 if (imx_ldb_ch
== &ldb
->channel
[1]) {
290 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
291 ldb
->ldb_ctrl
|= LDB_DI1_VS_POL_ACT_LOW
;
292 else if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
293 ldb
->ldb_ctrl
&= ~LDB_DI1_VS_POL_ACT_LOW
;
297 static void imx_ldb_encoder_disable(struct drm_encoder
*encoder
)
299 struct imx_ldb_channel
*imx_ldb_ch
= enc_to_imx_ldb_ch(encoder
);
300 struct imx_ldb
*ldb
= imx_ldb_ch
->ldb
;
304 * imx_ldb_encoder_disable is called by
305 * drm_helper_disable_unused_functions without
306 * the encoder being enabled before.
308 if (imx_ldb_ch
== &ldb
->channel
[0] &&
309 (ldb
->ldb_ctrl
& LDB_CH0_MODE_EN_MASK
) == 0)
311 else if (imx_ldb_ch
== &ldb
->channel
[1] &&
312 (ldb
->ldb_ctrl
& LDB_CH1_MODE_EN_MASK
) == 0)
315 drm_panel_disable(imx_ldb_ch
->panel
);
317 if (imx_ldb_ch
== &ldb
->channel
[0])
318 ldb
->ldb_ctrl
&= ~LDB_CH0_MODE_EN_MASK
;
319 else if (imx_ldb_ch
== &ldb
->channel
[1])
320 ldb
->ldb_ctrl
&= ~LDB_CH1_MODE_EN_MASK
;
322 regmap_write(ldb
->regmap
, IOMUXC_GPR2
, ldb
->ldb_ctrl
);
324 if (ldb
->ldb_ctrl
& LDB_SPLIT_MODE_EN
) {
325 clk_disable_unprepare(ldb
->clk
[0]);
326 clk_disable_unprepare(ldb
->clk
[1]);
330 const struct bus_mux
*lvds_mux
= NULL
;
332 if (imx_ldb_ch
== &ldb
->channel
[0])
333 lvds_mux
= &ldb
->lvds_mux
[0];
334 else if (imx_ldb_ch
== &ldb
->channel
[1])
335 lvds_mux
= &ldb
->lvds_mux
[1];
337 regmap_read(ldb
->regmap
, lvds_mux
->reg
, &mux
);
338 mux
&= lvds_mux
->mask
;
339 mux
>>= lvds_mux
->shift
;
341 mux
= (imx_ldb_ch
== &ldb
->channel
[0]) ? 0 : 1;
344 /* set display clock mux back to original input clock */
345 ret
= clk_set_parent(ldb
->clk_sel
[mux
], ldb
->clk_parent
[mux
]);
348 "unable to set di%d parent clock to original parent\n",
351 drm_panel_unprepare(imx_ldb_ch
->panel
);
354 static const struct drm_connector_funcs imx_ldb_connector_funcs
= {
355 .dpms
= drm_helper_connector_dpms
,
356 .fill_modes
= drm_helper_probe_single_connector_modes
,
357 .detect
= imx_ldb_connector_detect
,
358 .destroy
= imx_drm_connector_destroy
,
361 static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs
= {
362 .get_modes
= imx_ldb_connector_get_modes
,
363 .best_encoder
= imx_ldb_connector_best_encoder
,
366 static const struct drm_encoder_funcs imx_ldb_encoder_funcs
= {
367 .destroy
= imx_drm_encoder_destroy
,
370 static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs
= {
371 .dpms
= imx_ldb_encoder_dpms
,
372 .prepare
= imx_ldb_encoder_prepare
,
373 .commit
= imx_ldb_encoder_commit
,
374 .mode_set
= imx_ldb_encoder_mode_set
,
375 .disable
= imx_ldb_encoder_disable
,
378 static int imx_ldb_get_clk(struct imx_ldb
*ldb
, int chno
)
382 snprintf(clkname
, sizeof(clkname
), "di%d", chno
);
383 ldb
->clk
[chno
] = devm_clk_get(ldb
->dev
, clkname
);
384 if (IS_ERR(ldb
->clk
[chno
]))
385 return PTR_ERR(ldb
->clk
[chno
]);
387 snprintf(clkname
, sizeof(clkname
), "di%d_pll", chno
);
388 ldb
->clk_pll
[chno
] = devm_clk_get(ldb
->dev
, clkname
);
390 return PTR_ERR_OR_ZERO(ldb
->clk_pll
[chno
]);
393 static int imx_ldb_register(struct drm_device
*drm
,
394 struct imx_ldb_channel
*imx_ldb_ch
)
396 struct imx_ldb
*ldb
= imx_ldb_ch
->ldb
;
399 ret
= imx_drm_encoder_parse_of(drm
, &imx_ldb_ch
->encoder
,
404 ret
= imx_ldb_get_clk(ldb
, imx_ldb_ch
->chno
);
408 if (ldb
->ldb_ctrl
& LDB_SPLIT_MODE_EN
) {
409 ret
= imx_ldb_get_clk(ldb
, 1);
414 drm_encoder_helper_add(&imx_ldb_ch
->encoder
,
415 &imx_ldb_encoder_helper_funcs
);
416 drm_encoder_init(drm
, &imx_ldb_ch
->encoder
, &imx_ldb_encoder_funcs
,
417 DRM_MODE_ENCODER_LVDS
, NULL
);
419 drm_connector_helper_add(&imx_ldb_ch
->connector
,
420 &imx_ldb_connector_helper_funcs
);
421 drm_connector_init(drm
, &imx_ldb_ch
->connector
,
422 &imx_ldb_connector_funcs
, DRM_MODE_CONNECTOR_LVDS
);
424 if (imx_ldb_ch
->panel
)
425 drm_panel_attach(imx_ldb_ch
->panel
, &imx_ldb_ch
->connector
);
427 drm_mode_connector_attach_encoder(&imx_ldb_ch
->connector
,
428 &imx_ldb_ch
->encoder
);
438 struct imx_ldb_bit_mapping
{
441 const char * const mapping
;
444 static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings
[] = {
445 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
, 18, "spwg" },
446 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
, 24, "spwg" },
447 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
, 24, "jeida" },
450 static u32
of_get_bus_format(struct device
*dev
, struct device_node
*np
)
456 ret
= of_property_read_string(np
, "fsl,data-mapping", &bm
);
460 of_property_read_u32(np
, "fsl,data-width", &datawidth
);
462 for (i
= 0; i
< ARRAY_SIZE(imx_ldb_bit_mappings
); i
++) {
463 if (!strcasecmp(bm
, imx_ldb_bit_mappings
[i
].mapping
) &&
464 datawidth
== imx_ldb_bit_mappings
[i
].datawidth
)
465 return imx_ldb_bit_mappings
[i
].bus_format
;
468 dev_err(dev
, "invalid data mapping: %d-bit \"%s\"\n", datawidth
, bm
);
473 static struct bus_mux imx6q_lvds_mux
[2] = {
477 .mask
= IMX6Q_GPR3_LVDS0_MUX_CTL_MASK
,
481 .mask
= IMX6Q_GPR3_LVDS1_MUX_CTL_MASK
,
486 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
487 * of_match_device will walk through this list and take the first entry
488 * matching any of its compatible values. Therefore, the more generic
489 * entries (in this case fsl,imx53-ldb) need to be ordered last.
491 static const struct of_device_id imx_ldb_dt_ids
[] = {
492 { .compatible
= "fsl,imx6q-ldb", .data
= imx6q_lvds_mux
, },
493 { .compatible
= "fsl,imx53-ldb", .data
= NULL
, },
496 MODULE_DEVICE_TABLE(of
, imx_ldb_dt_ids
);
498 static int imx_ldb_bind(struct device
*dev
, struct device
*master
, void *data
)
500 struct drm_device
*drm
= data
;
501 struct device_node
*np
= dev
->of_node
;
502 const struct of_device_id
*of_id
=
503 of_match_device(imx_ldb_dt_ids
, dev
);
504 struct device_node
*child
;
506 struct imx_ldb
*imx_ldb
;
511 imx_ldb
= devm_kzalloc(dev
, sizeof(*imx_ldb
), GFP_KERNEL
);
515 imx_ldb
->regmap
= syscon_regmap_lookup_by_phandle(np
, "gpr");
516 if (IS_ERR(imx_ldb
->regmap
)) {
517 dev_err(dev
, "failed to get parent regmap\n");
518 return PTR_ERR(imx_ldb
->regmap
);
524 imx_ldb
->lvds_mux
= of_id
->data
;
526 dual
= of_property_read_bool(np
, "fsl,dual-channel");
528 imx_ldb
->ldb_ctrl
|= LDB_SPLIT_MODE_EN
;
531 * There are three different possible clock mux configurations:
532 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
533 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
534 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
535 * Map them all to di0_sel...di3_sel.
537 for (i
= 0; i
< 4; i
++) {
540 sprintf(clkname
, "di%d_sel", i
);
541 imx_ldb
->clk_sel
[i
] = devm_clk_get(imx_ldb
->dev
, clkname
);
542 if (IS_ERR(imx_ldb
->clk_sel
[i
])) {
543 ret
= PTR_ERR(imx_ldb
->clk_sel
[i
]);
544 imx_ldb
->clk_sel
[i
] = NULL
;
548 imx_ldb
->clk_parent
[i
] = clk_get_parent(imx_ldb
->clk_sel
[i
]);
553 for_each_child_of_node(np
, child
) {
554 struct imx_ldb_channel
*channel
;
555 struct device_node
*port
;
557 ret
= of_property_read_u32(child
, "reg", &i
);
558 if (ret
|| i
< 0 || i
> 1)
562 dev_warn(dev
, "dual-channel mode, ignoring second output\n");
566 if (!of_device_is_available(child
))
569 channel
= &imx_ldb
->channel
[i
];
570 channel
->ldb
= imx_ldb
;
572 channel
->child
= child
;
575 * The output port is port@4 with an external 4-port mux or
576 * port@2 with the internal 2-port mux.
578 port
= of_graph_get_port_by_id(child
, imx_ldb
->lvds_mux
? 4 : 2);
580 struct device_node
*endpoint
, *remote
;
582 endpoint
= of_get_child_by_name(port
, "endpoint");
584 remote
= of_graph_get_remote_port_parent(endpoint
);
586 channel
->panel
= of_drm_find_panel(remote
);
588 return -EPROBE_DEFER
;
589 if (!channel
->panel
) {
590 dev_err(dev
, "panel not found: %s\n",
592 return -EPROBE_DEFER
;
597 edidp
= of_get_property(child
, "edid", &channel
->edid_len
);
599 channel
->edid
= kmemdup(edidp
, channel
->edid_len
,
601 } else if (!channel
->panel
) {
602 ret
= of_get_drm_display_mode(child
, &channel
->mode
, 0);
604 channel
->mode_valid
= 1;
607 channel
->bus_format
= of_get_bus_format(dev
, child
);
608 if (channel
->bus_format
== -EINVAL
) {
610 * If no bus format was specified in the device tree,
611 * we can still get it from the connected panel later.
613 if (channel
->panel
&& channel
->panel
->funcs
&&
614 channel
->panel
->funcs
->get_modes
)
615 channel
->bus_format
= 0;
617 if (channel
->bus_format
< 0) {
618 dev_err(dev
, "could not determine data mapping: %d\n",
619 channel
->bus_format
);
620 return channel
->bus_format
;
623 ret
= imx_ldb_register(drm
, channel
);
628 dev_set_drvdata(dev
, imx_ldb
);
633 static void imx_ldb_unbind(struct device
*dev
, struct device
*master
,
636 struct imx_ldb
*imx_ldb
= dev_get_drvdata(dev
);
639 for (i
= 0; i
< 2; i
++) {
640 struct imx_ldb_channel
*channel
= &imx_ldb
->channel
[i
];
642 if (!channel
->connector
.funcs
)
645 channel
->connector
.funcs
->destroy(&channel
->connector
);
646 channel
->encoder
.funcs
->destroy(&channel
->encoder
);
648 kfree(channel
->edid
);
652 static const struct component_ops imx_ldb_ops
= {
653 .bind
= imx_ldb_bind
,
654 .unbind
= imx_ldb_unbind
,
657 static int imx_ldb_probe(struct platform_device
*pdev
)
659 return component_add(&pdev
->dev
, &imx_ldb_ops
);
662 static int imx_ldb_remove(struct platform_device
*pdev
)
664 component_del(&pdev
->dev
, &imx_ldb_ops
);
668 static struct platform_driver imx_ldb_driver
= {
669 .probe
= imx_ldb_probe
,
670 .remove
= imx_ldb_remove
,
672 .of_match_table
= imx_ldb_dt_ids
,
677 module_platform_driver(imx_ldb_driver
);
679 MODULE_DESCRIPTION("i.MX LVDS driver");
680 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
681 MODULE_LICENSE("GPL");
682 MODULE_ALIAS("platform:" DRIVER_NAME
);