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Merge tag 'drm-intel-fixes-2016-03-11' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5.xml.h
1 #ifndef MDP5_XML
2 #define MDP5_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
22
23 Copyright (C) 2013-2015 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25
26 Permission is hereby granted, free of charge, to any person obtaining
27 a copy of this software and associated documentation files (the
28 "Software"), to deal in the Software without restriction, including
29 without limitation the rights to use, copy, modify, merge, publish,
30 distribute, sublicense, and/or sell copies of the Software, and to
31 permit persons to whom the Software is furnished to do so, subject to
32 the following conditions:
33
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial
36 portions of the Software.
37
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47
48 enum mdp5_intf_type {
49 INTF_DISABLED = 0,
50 INTF_DSI = 1,
51 INTF_HDMI = 3,
52 INTF_LCDC = 5,
53 INTF_eDP = 9,
54 INTF_VIRTUAL = 100,
55 INTF_WB = 101,
56 };
57
58 enum mdp5_intfnum {
59 NO_INTF = 0,
60 INTF0 = 1,
61 INTF1 = 2,
62 INTF2 = 3,
63 INTF3 = 4,
64 };
65
66 enum mdp5_pipe {
67 SSPP_VIG0 = 0,
68 SSPP_VIG1 = 1,
69 SSPP_VIG2 = 2,
70 SSPP_RGB0 = 3,
71 SSPP_RGB1 = 4,
72 SSPP_RGB2 = 5,
73 SSPP_DMA0 = 6,
74 SSPP_DMA1 = 7,
75 SSPP_VIG3 = 8,
76 SSPP_RGB3 = 9,
77 };
78
79 enum mdp5_ctl_mode {
80 MODE_NONE = 0,
81 MODE_WB_0_BLOCK = 1,
82 MODE_WB_1_BLOCK = 2,
83 MODE_WB_0_LINE = 3,
84 MODE_WB_1_LINE = 4,
85 MODE_WB_2_LINE = 5,
86 };
87
88 enum mdp5_pack_3d {
89 PACK_3D_FRAME_INT = 0,
90 PACK_3D_H_ROW_INT = 1,
91 PACK_3D_V_ROW_INT = 2,
92 PACK_3D_COL_INT = 3,
93 };
94
95 enum mdp5_scale_filter {
96 SCALE_FILTER_NEAREST = 0,
97 SCALE_FILTER_BIL = 1,
98 SCALE_FILTER_PCMN = 2,
99 SCALE_FILTER_CA = 3,
100 };
101
102 enum mdp5_pipe_bwc {
103 BWC_LOSSLESS = 0,
104 BWC_Q_HIGH = 1,
105 BWC_Q_MED = 2,
106 };
107
108 enum mdp5_cursor_format {
109 CURSOR_FMT_ARGB8888 = 0,
110 CURSOR_FMT_ARGB1555 = 2,
111 CURSOR_FMT_ARGB4444 = 4,
112 };
113
114 enum mdp5_cursor_alpha {
115 CURSOR_ALPHA_CONST = 0,
116 CURSOR_ALPHA_PER_PIXEL = 2,
117 };
118
119 enum mdp5_igc_type {
120 IGC_VIG = 0,
121 IGC_RGB = 1,
122 IGC_DMA = 2,
123 IGC_DSPP = 3,
124 };
125
126 enum mdp5_data_format {
127 DATA_FORMAT_RGB = 0,
128 DATA_FORMAT_YUV = 1,
129 };
130
131 enum mdp5_block_size {
132 BLOCK_SIZE_64 = 0,
133 BLOCK_SIZE_128 = 1,
134 };
135
136 enum mdp5_rotate_mode {
137 ROTATE_0 = 0,
138 ROTATE_90 = 1,
139 };
140
141 enum mdp5_chroma_downsample_method {
142 DS_MTHD_NO_PIXEL_DROP = 0,
143 DS_MTHD_PIXEL_DROP = 1,
144 };
145
146 #define MDP5_IRQ_WB_0_DONE 0x00000001
147 #define MDP5_IRQ_WB_1_DONE 0x00000002
148 #define MDP5_IRQ_WB_2_DONE 0x00000010
149 #define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
150 #define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
151 #define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
152 #define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
153 #define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
154 #define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
155 #define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
156 #define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
157 #define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
158 #define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
159 #define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
160 #define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
161 #define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
162 #define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
163 #define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
164 #define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
165 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
166 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
167 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
168 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
169 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
170 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
171 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
172 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
173 #define REG_MDSS_HW_VERSION 0x00000000
174 #define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
175 #define MDSS_HW_VERSION_STEP__SHIFT 0
176 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
177 {
178 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
179 }
180 #define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
181 #define MDSS_HW_VERSION_MINOR__SHIFT 16
182 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
183 {
184 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
185 }
186 #define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
187 #define MDSS_HW_VERSION_MAJOR__SHIFT 28
188 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
189 {
190 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
191 }
192
193 #define REG_MDSS_HW_INTR_STATUS 0x00000010
194 #define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
195 #define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
196 #define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
197 #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
198 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
199
200 static inline uint32_t __offset_MDP(uint32_t idx)
201 {
202 switch (idx) {
203 case 0: return (mdp5_cfg->mdp.base[0]);
204 default: return INVALID_IDX(idx);
205 }
206 }
207 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
208
209 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
210 #define MDP5_MDP_HW_VERSION_STEP__MASK 0x0000ffff
211 #define MDP5_MDP_HW_VERSION_STEP__SHIFT 0
212 static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
213 {
214 return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK;
215 }
216 #define MDP5_MDP_HW_VERSION_MINOR__MASK 0x0fff0000
217 #define MDP5_MDP_HW_VERSION_MINOR__SHIFT 16
218 static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)
219 {
220 return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK;
221 }
222 #define MDP5_MDP_HW_VERSION_MAJOR__MASK 0xf0000000
223 #define MDP5_MDP_HW_VERSION_MAJOR__SHIFT 28
224 static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val)
225 {
226 return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK;
227 }
228
229 static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); }
230 #define MDP5_MDP_DISP_INTF_SEL_INTF0__MASK 0x000000ff
231 #define MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT 0
232 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
233 {
234 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
235 }
236 #define MDP5_MDP_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
237 #define MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT 8
238 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
239 {
240 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
241 }
242 #define MDP5_MDP_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
243 #define MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT 16
244 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
245 {
246 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
247 }
248 #define MDP5_MDP_DISP_INTF_SEL_INTF3__MASK 0xff000000
249 #define MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT 24
250 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
251 {
252 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
253 }
254
255 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); }
256
257 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); }
258
259 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); }
260
261 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); }
262
263 static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); }
264
265 static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); }
266
267 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); }
268 #define MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
269
270 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
271
272 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
273 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
274 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
275 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
276 {
277 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
278 }
279 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
280 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
281 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
282 {
283 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
284 }
285 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
286 #define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
287 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
288 {
289 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
290 }
291
292 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
293
294 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
295 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
296 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
297 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
298 {
299 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
300 }
301 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
302 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
303 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
304 {
305 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
306 }
307 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
308 #define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
309 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
310 {
311 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
312 }
313
314 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
315 {
316 switch (idx) {
317 case IGC_VIG: return 0x00000200;
318 case IGC_RGB: return 0x00000210;
319 case IGC_DMA: return 0x00000220;
320 case IGC_DSPP: return 0x00000300;
321 default: return INVALID_IDX(idx);
322 }
323 }
324 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); }
325
326 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
327
328 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
329 #define MDP5_MDP_IGC_LUT_REG_VAL__MASK 0x00000fff
330 #define MDP5_MDP_IGC_LUT_REG_VAL__SHIFT 0
331 static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)
332 {
333 return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK;
334 }
335 #define MDP5_MDP_IGC_LUT_REG_INDEX_UPDATE 0x02000000
336 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
337 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
338 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
339
340 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); }
341
342 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); }
343 #define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
344 #define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
345 #define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
346 #define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
347
348 static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); }
349 #define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
350 #define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
351 #define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
352 #define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
353
354 static inline uint32_t __offset_CTL(uint32_t idx)
355 {
356 switch (idx) {
357 case 0: return (mdp5_cfg->ctl.base[0]);
358 case 1: return (mdp5_cfg->ctl.base[1]);
359 case 2: return (mdp5_cfg->ctl.base[2]);
360 case 3: return (mdp5_cfg->ctl.base[3]);
361 case 4: return (mdp5_cfg->ctl.base[4]);
362 default: return INVALID_IDX(idx);
363 }
364 }
365 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
366
367 static inline uint32_t __offset_LAYER(uint32_t idx)
368 {
369 switch (idx) {
370 case 0: return 0x00000000;
371 case 1: return 0x00000004;
372 case 2: return 0x00000008;
373 case 3: return 0x0000000c;
374 case 4: return 0x00000010;
375 case 5: return 0x00000024;
376 default: return INVALID_IDX(idx);
377 }
378 }
379 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
380
381 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
382 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
383 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
384 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
385 {
386 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
387 }
388 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
389 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
390 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
391 {
392 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
393 }
394 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
395 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
396 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
397 {
398 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
399 }
400 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
401 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
402 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
403 {
404 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
405 }
406 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
407 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
408 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
409 {
410 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
411 }
412 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
413 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
414 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
415 {
416 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
417 }
418 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
419 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
420 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
421 {
422 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
423 }
424 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
425 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
426 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
427 {
428 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
429 }
430 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
431 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
432 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
433 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
434 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
435 {
436 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
437 }
438 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
439 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
440 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
441 {
442 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
443 }
444
445 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
446 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
447 #define MDP5_CTL_OP_MODE__SHIFT 0
448 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
449 {
450 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
451 }
452 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
453 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
454 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
455 {
456 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
457 }
458 #define MDP5_CTL_OP_CMD_MODE 0x00020000
459 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
460 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
461 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
462 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
463 {
464 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
465 }
466
467 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
468 #define MDP5_CTL_FLUSH_VIG0 0x00000001
469 #define MDP5_CTL_FLUSH_VIG1 0x00000002
470 #define MDP5_CTL_FLUSH_VIG2 0x00000004
471 #define MDP5_CTL_FLUSH_RGB0 0x00000008
472 #define MDP5_CTL_FLUSH_RGB1 0x00000010
473 #define MDP5_CTL_FLUSH_RGB2 0x00000020
474 #define MDP5_CTL_FLUSH_LM0 0x00000040
475 #define MDP5_CTL_FLUSH_LM1 0x00000080
476 #define MDP5_CTL_FLUSH_LM2 0x00000100
477 #define MDP5_CTL_FLUSH_LM3 0x00000200
478 #define MDP5_CTL_FLUSH_LM4 0x00000400
479 #define MDP5_CTL_FLUSH_DMA0 0x00000800
480 #define MDP5_CTL_FLUSH_DMA1 0x00001000
481 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
482 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
483 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
484 #define MDP5_CTL_FLUSH_WB 0x00010000
485 #define MDP5_CTL_FLUSH_CTL 0x00020000
486 #define MDP5_CTL_FLUSH_VIG3 0x00040000
487 #define MDP5_CTL_FLUSH_RGB3 0x00080000
488 #define MDP5_CTL_FLUSH_LM5 0x00100000
489 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
490 #define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
491 #define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
492 #define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
493 #define MDP5_CTL_FLUSH_TIMING_3 0x10000000
494 #define MDP5_CTL_FLUSH_TIMING_2 0x20000000
495 #define MDP5_CTL_FLUSH_TIMING_1 0x40000000
496 #define MDP5_CTL_FLUSH_TIMING_0 0x80000000
497
498 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
499
500 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
501
502 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
503 {
504 switch (idx) {
505 case 0: return 0x00000040;
506 case 1: return 0x00000044;
507 case 2: return 0x00000048;
508 case 3: return 0x0000004c;
509 case 4: return 0x00000050;
510 case 5: return 0x00000054;
511 default: return INVALID_IDX(idx);
512 }
513 }
514 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
515
516 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
517 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
518 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
519 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
520 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
521 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
522 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
523 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
524 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
525 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
526 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
527 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
528 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
529 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
530 {
531 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
532 }
533 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
534 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
535 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
536 {
537 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
538 }
539
540 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
541 {
542 switch (idx) {
543 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
544 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
545 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
546 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
547 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
548 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
549 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
550 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
551 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
552 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
553 default: return INVALID_IDX(idx);
554 }
555 }
556 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
557
558 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
559 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
560 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
561 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
562 {
563 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
564 }
565 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
566 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
567 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
568 {
569 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
570 }
571 #define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
572
573 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
574
575 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
576
577 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
578
579 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
580 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
581 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
582 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
583 {
584 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
585 }
586 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
587 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
588 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
589 {
590 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
591 }
592
593 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
594 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
595 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
596 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
597 {
598 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
599 }
600 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
601 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
602 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
603 {
604 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
605 }
606
607 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
608 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
609 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
610 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
611 {
612 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
613 }
614 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
615 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
616 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
617 {
618 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
619 }
620
621 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
622 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
623 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
624 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
625 {
626 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
627 }
628 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
629 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
630 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
631 {
632 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
633 }
634
635 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
636 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
637 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
638 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
639 {
640 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
641 }
642
643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
644
645 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
646 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
647 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
648 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
649 {
650 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
651 }
652 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
653 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
654 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
655 {
656 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
657 }
658
659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
660
661 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
662 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
663 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
664 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
665 {
666 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
667 }
668 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
669 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
670 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
671 {
672 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
673 }
674
675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
676
677 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
678 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
679 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
680 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
681 {
682 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
683 }
684
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
686
687 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
688 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
689 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
690 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
691 {
692 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
693 }
694
695 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
696 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
697 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
698 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
699 {
700 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
701 }
702 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
703 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
704 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
705 {
706 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
707 }
708
709 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
710 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
711 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
712 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
713 {
714 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
715 }
716 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
717 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
718 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
719 {
720 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
721 }
722
723 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
724 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
725 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
726 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
727 {
728 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
729 }
730 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
731 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
732 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
733 {
734 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
735 }
736
737 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
738 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
739 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
740 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
741 {
742 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
743 }
744 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
745 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
746 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
747 {
748 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
749 }
750
751 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
752 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
753 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
754 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
755 {
756 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
757 }
758 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
759 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
760 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
761 {
762 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
763 }
764
765 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
766
767 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
768
769 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
770
771 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
772
773 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
774 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
775 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
776 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
777 {
778 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
779 }
780 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
781 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
782 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
783 {
784 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
785 }
786
787 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
788 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
789 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
790 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
791 {
792 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
793 }
794 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
795 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
796 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
797 {
798 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
799 }
800
801 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
802
803 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
804 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
805 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
806 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
807 {
808 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
809 }
810 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
811 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
812 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
813 {
814 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
815 }
816 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
817 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
818 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
819 {
820 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
821 }
822 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
823 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
824 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
825 {
826 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
827 }
828 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
829 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
830 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
831 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
832 {
833 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
834 }
835 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
836 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
837 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
838 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
839 {
840 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
841 }
842 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
843 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
844 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
845 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
846 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
847 {
848 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
849 }
850 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
851 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
852 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
853 {
854 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
855 }
856
857 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
858 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
859 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
860 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
861 {
862 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
863 }
864 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
865 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
866 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
867 {
868 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
869 }
870 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
871 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
872 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
873 {
874 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
875 }
876 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
877 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
878 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
879 {
880 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
881 }
882
883 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
884 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
885 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
886 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
887 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
888 {
889 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
890 }
891 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
892 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
893 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
894 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
895 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
896 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
897 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
898 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
899
900 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
901
902 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
903
904 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
905
906 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
907
908 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
909
910 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
911
912 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
913
914 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
915
916 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
917
918 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
919
920 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
921
922 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
923 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
924 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
925 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
926 {
927 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
928 }
929 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
930 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
931 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
932 {
933 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
934 }
935
936 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
937 {
938 switch (idx) {
939 case COMP_0: return 0x00000100;
940 case COMP_1_2: return 0x00000110;
941 case COMP_3: return 0x00000120;
942 default: return INVALID_IDX(idx);
943 }
944 }
945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
946
947 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
948 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
949 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
950 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
951 {
952 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
953 }
954 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
955 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
956 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
957 {
958 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
959 }
960 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
961 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
962 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
963 {
964 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
965 }
966 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
967 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
968 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
969 {
970 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
971 }
972
973 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
974 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
975 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
976 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
977 {
978 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
979 }
980 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
981 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
982 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
983 {
984 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
985 }
986 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
987 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
988 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
989 {
990 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
991 }
992 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
993 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
994 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
995 {
996 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
997 }
998
999 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1000 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
1001 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
1002 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1003 {
1004 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1005 }
1006 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1007 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
1008 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1009 {
1010 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1011 }
1012
1013 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1014 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
1015 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
1016 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1017 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
1018 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1019 {
1020 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1021 }
1022 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1023 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
1024 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1025 {
1026 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1027 }
1028 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1029 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
1030 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1031 {
1032 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1033 }
1034 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1035 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
1036 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1037 {
1038 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1039 }
1040 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1041 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
1042 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1043 {
1044 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1045 }
1046 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1047 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
1048 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1049 {
1050 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1051 }
1052
1053 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1054
1055 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1056
1057 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1058
1059 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1060
1061 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1062
1063 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1064
1065 static inline uint32_t __offset_LM(uint32_t idx)
1066 {
1067 switch (idx) {
1068 case 0: return (mdp5_cfg->lm.base[0]);
1069 case 1: return (mdp5_cfg->lm.base[1]);
1070 case 2: return (mdp5_cfg->lm.base[2]);
1071 case 3: return (mdp5_cfg->lm.base[3]);
1072 case 4: return (mdp5_cfg->lm.base[4]);
1073 case 5: return (mdp5_cfg->lm.base[5]);
1074 default: return INVALID_IDX(idx);
1075 }
1076 }
1077 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1078
1079 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1080 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1081 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1082 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1083 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
1084
1085 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1086 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1087 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
1088 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1089 {
1090 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1091 }
1092 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1093 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
1094 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1095 {
1096 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1097 }
1098
1099 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1100
1101 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1102
1103 static inline uint32_t __offset_BLEND(uint32_t idx)
1104 {
1105 switch (idx) {
1106 case 0: return 0x00000020;
1107 case 1: return 0x00000050;
1108 case 2: return 0x00000080;
1109 case 3: return 0x000000b0;
1110 case 4: return 0x00000230;
1111 case 5: return 0x00000260;
1112 case 6: return 0x00000290;
1113 default: return INVALID_IDX(idx);
1114 }
1115 }
1116 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1117
1118 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1119 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1120 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
1121 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1122 {
1123 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1124 }
1125 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1126 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1127 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1128 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1129 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1130 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
1131 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1132 {
1133 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1134 }
1135 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1136 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1137 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1138 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1139
1140 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1141
1142 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1143
1144 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1145
1146 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1147
1148 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1149
1150 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1151
1152 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1153
1154 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1155
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1157
1158 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1159
1160 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1161 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1162 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
1163 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1164 {
1165 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1166 }
1167 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1168 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
1169 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1170 {
1171 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1172 }
1173
1174 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1175 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1176 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1177 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1178 {
1179 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1180 }
1181 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1182 #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1183 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1184 {
1185 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1186 }
1187
1188 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1189 #define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1190 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1191 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1192 {
1193 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1194 }
1195 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1196 #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1197 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1198 {
1199 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1200 }
1201
1202 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1203 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1204 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1205 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1206 {
1207 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1208 }
1209
1210 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1211 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1212 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1213 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1214 {
1215 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1216 }
1217
1218 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1219
1220 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1221 #define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1222 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1223 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1224 {
1225 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1226 }
1227 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1228 #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1229 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1230 {
1231 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1232 }
1233
1234 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1235 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1236 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1237 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1238 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1239 {
1240 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1241 }
1242 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1243
1244 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1245
1246 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1247
1248 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1249
1250 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1251
1252 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1253
1254 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1255
1256 static inline uint32_t __offset_DSPP(uint32_t idx)
1257 {
1258 switch (idx) {
1259 case 0: return (mdp5_cfg->dspp.base[0]);
1260 case 1: return (mdp5_cfg->dspp.base[1]);
1261 case 2: return (mdp5_cfg->dspp.base[2]);
1262 case 3: return (mdp5_cfg->dspp.base[3]);
1263 default: return INVALID_IDX(idx);
1264 }
1265 }
1266 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1267
1268 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1269 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1270 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1271 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1272 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1273 {
1274 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1275 }
1276 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1277 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1278 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1279 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1280 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1281 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1282 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1283 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1284
1285 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1286
1287 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1288
1289 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1290
1291 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1292
1293 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1294
1295 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1296
1297 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1298
1299 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1300
1301 static inline uint32_t __offset_PP(uint32_t idx)
1302 {
1303 switch (idx) {
1304 case 0: return (mdp5_cfg->pp.base[0]);
1305 case 1: return (mdp5_cfg->pp.base[1]);
1306 case 2: return (mdp5_cfg->pp.base[2]);
1307 case 3: return (mdp5_cfg->pp.base[3]);
1308 default: return INVALID_IDX(idx);
1309 }
1310 }
1311 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1312
1313 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1314
1315 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1316 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1317 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
1318 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1319 {
1320 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1321 }
1322 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1323 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1324
1325 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1326
1327 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1328 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1329 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
1330 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1331 {
1332 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1333 }
1334 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1335 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
1336 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1337 {
1338 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1339 }
1340
1341 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1342
1343 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1344 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1345 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
1346 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1347 {
1348 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1349 }
1350 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1351 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
1352 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1353 {
1354 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1355 }
1356
1357 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1358 #define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1359 #define MDP5_PP_SYNC_THRESH_START__SHIFT 0
1360 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1361 {
1362 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1363 }
1364 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1365 #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
1366 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1367 {
1368 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1369 }
1370
1371 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1372
1373 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1374
1375 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1376
1377 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1378
1379 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1380
1381 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1382
1383 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1384
1385 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1386
1387 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1388
1389 static inline uint32_t __offset_WB(uint32_t idx)
1390 {
1391 switch (idx) {
1392 #if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1393 case 0: return (mdp5_cfg->wb.base[0]);
1394 case 1: return (mdp5_cfg->wb.base[1]);
1395 case 2: return (mdp5_cfg->wb.base[2]);
1396 case 3: return (mdp5_cfg->wb.base[3]);
1397 case 4: return (mdp5_cfg->wb.base[4]);
1398 #endif
1399 default: return INVALID_IDX(idx);
1400 }
1401 }
1402 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1403
1404 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1405 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1406 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
1407 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1408 {
1409 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1410 }
1411 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1412 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
1413 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1414 {
1415 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1416 }
1417 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1418 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
1419 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1420 {
1421 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1422 }
1423 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1424 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
1425 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1426 {
1427 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1428 }
1429 #define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1430 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1431 #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
1432 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1433 {
1434 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1435 }
1436 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1437 #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
1438 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1439 {
1440 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1441 }
1442 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1443 #define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1444 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1445 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1446 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
1447 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1448 {
1449 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1450 }
1451 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1452 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1453 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
1454 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1455 {
1456 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1457 }
1458 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1459 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
1460 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1461 {
1462 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1463 }
1464 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1465 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
1466 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1467 {
1468 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1469 }
1470
1471 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1472 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1473 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1474 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
1475 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1476 {
1477 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1478 }
1479 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1480 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
1481 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1482 {
1483 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1484 }
1485 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1486 #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
1487 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1488 {
1489 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1490 }
1491 #define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1492 #define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1493 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1494 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
1495 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1496 {
1497 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1498 }
1499 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1500 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
1501 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1502 {
1503 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1504 }
1505 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1506 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1507 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
1508 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1509 {
1510 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1511 }
1512 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1513 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
1514 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1515 {
1516 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1517 }
1518 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1519 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
1520 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1521 {
1522 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1523 }
1524
1525 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1526 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1527 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
1528 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1529 {
1530 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1531 }
1532 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1533 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
1534 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1535 {
1536 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1537 }
1538 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1539 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
1540 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1541 {
1542 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1543 }
1544 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1545 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
1546 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1547 {
1548 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1549 }
1550
1551 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1552
1553 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1554
1555 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1556
1557 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1558
1559 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1560 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1561 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
1562 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1563 {
1564 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1565 }
1566 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1567 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
1568 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1569 {
1570 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1571 }
1572
1573 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1574 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1575 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
1576 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1577 {
1578 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1579 }
1580 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1581 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
1582 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1583 {
1584 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1585 }
1586
1587 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1588
1589 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1590
1591 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1592
1593 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1594
1595 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1596
1597 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1598
1599 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1600
1601 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1602
1603 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1604
1605 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1606
1607 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1608
1609 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1610 #define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1611 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
1612 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1613 {
1614 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1615 }
1616 #define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1617 #define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
1618 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1619 {
1620 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1621 }
1622
1623 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1624
1625 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1626 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1627 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
1628 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1629 {
1630 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1631 }
1632 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1633 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
1634 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1635 {
1636 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1637 }
1638
1639 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1640 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1641 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
1642 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1643 {
1644 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1645 }
1646 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1647 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
1648 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1649 {
1650 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1651 }
1652
1653 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1654 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1655 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
1656 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1657 {
1658 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1659 }
1660 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1661 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
1662 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1663 {
1664 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1665 }
1666
1667 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1668 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1669 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
1670 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1671 {
1672 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1673 }
1674 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1675 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
1676 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1677 {
1678 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1679 }
1680
1681 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1682 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1683 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
1684 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1685 {
1686 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1687 }
1688
1689 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1690
1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1692 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1693 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
1694 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1695 {
1696 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1697 }
1698 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1699 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
1700 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1701 {
1702 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1703 }
1704
1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1706
1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1708 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1709 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
1710 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1711 {
1712 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1713 }
1714 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1715 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
1716 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1717 {
1718 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1719 }
1720
1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1722
1723 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1724 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1725 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
1726 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1727 {
1728 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1729 }
1730
1731 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1732
1733 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1734 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1735 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
1736 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1737 {
1738 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1739 }
1740
1741 static inline uint32_t __offset_INTF(uint32_t idx)
1742 {
1743 switch (idx) {
1744 case 0: return (mdp5_cfg->intf.base[0]);
1745 case 1: return (mdp5_cfg->intf.base[1]);
1746 case 2: return (mdp5_cfg->intf.base[2]);
1747 case 3: return (mdp5_cfg->intf.base[3]);
1748 case 4: return (mdp5_cfg->intf.base[4]);
1749 default: return INVALID_IDX(idx);
1750 }
1751 }
1752 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1753
1754 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1755
1756 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1757
1758 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1759 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1760 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1761 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1762 {
1763 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1764 }
1765 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1766 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1767 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1768 {
1769 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1770 }
1771
1772 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1773
1774 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1775
1776 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1777
1778 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1779
1780 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1781
1782 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1783
1784 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1785
1786 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1787
1788 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1789 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1790 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1791 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1792 {
1793 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1794 }
1795 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1796
1797 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1798 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1799 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1800 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1801 {
1802 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1803 }
1804
1805 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1806
1807 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1808
1809 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1810 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1811 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1812 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1813 {
1814 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1815 }
1816 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1817 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1818 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1819 {
1820 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1821 }
1822
1823 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1824 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1825 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1826 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1827 {
1828 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1829 }
1830 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1831 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1832 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1833 {
1834 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1835 }
1836 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1837
1838 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1839
1840 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1841
1842 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1843
1844 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1845 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1846 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1847 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1848
1849 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1850
1851 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1852
1853 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1854
1855 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1856
1857 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1858
1859 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1860
1861 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1862
1863 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1864
1865 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1866
1867 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1868
1869 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1870
1871 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1872
1873 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1874
1875 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1876
1877 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1878
1879 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1880
1881 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1882
1883 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1884
1885 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1886
1887 static inline uint32_t __offset_AD(uint32_t idx)
1888 {
1889 switch (idx) {
1890 case 0: return (mdp5_cfg->ad.base[0]);
1891 case 1: return (mdp5_cfg->ad.base[1]);
1892 default: return INVALID_IDX(idx);
1893 }
1894 }
1895 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1896
1897 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1898
1899 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1900
1901 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1902
1903 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1904
1905 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1906
1907 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1908
1909 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1910
1911 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1912
1913 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1914
1915 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1916
1917 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1918
1919 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1920
1921 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1922
1923 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1924
1925 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1926
1927 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1928
1929 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1930
1931 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1932
1933 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1934
1935 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1936
1937 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1938
1939 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1940
1941 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1942
1943 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1944
1945 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1946
1947 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1948
1949 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1950
1951 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1952
1953 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1954
1955 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1956
1957 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1958
1959 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1960
1961 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1962
1963 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1964
1965
1966 #endif /* MDP5_XML */
Linux kernel - Deliverables
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