drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/videomode.h>
  38
  39 struct panel_desc {
  40         const struct drm_display_mode *modes;
  41         unsigned int num_modes;
  42         const struct display_timing *timings;
  43         unsigned int num_timings;
  44
  45         unsigned int bpc;
  46
  47         /**
  48          * @width: width (in millimeters) of the panel's active display area
  49          * @height: height (in millimeters) of the panel's active display area
  50          */
  51         struct {
  52                 unsigned int width;
  53                 unsigned int height;
  54         } size;
  55
  56         /**
  57          * @prepare: the time (in milliseconds) that it takes for the panel to
  58          *           become ready and start receiving video data
  59          * @enable: the time (in milliseconds) that it takes for the panel to
  60          *          display the first valid frame after starting to receive
  61          *          video data
  62          * @disable: the time (in milliseconds) that it takes for the panel to
  63          *           turn the display off (no content is visible)
  64          * @unprepare: the time (in milliseconds) that it takes for the panel
  65          *             to power itself down completely
  66          */
  67         struct {
  68                 unsigned int prepare;
  69                 unsigned int enable;
  70                 unsigned int disable;
  71                 unsigned int unprepare;
  72         } delay;
  73
  74         u32 bus_format;
  75         u32 bus_flags;
  76 };
  77
  78 struct panel_simple {
  79         struct drm_panel base;
  80         bool prepared;
  81         bool enabled;
  82
  83         const struct panel_desc *desc;
  84
  85         struct backlight_device *backlight;
  86         struct regulator *supply;
  87         struct i2c_adapter *ddc;
  88
  89         struct gpio_desc *enable_gpio;
  90 };
  91
  92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
  93 {
  94         return container_of(panel, struct panel_simple, base);
  95 }
  96
  97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
  98 {
  99         struct drm_connector *connector = panel->base.connector;
 100         struct drm_device *drm = panel->base.drm;
 101         struct drm_display_mode *mode;
 102         unsigned int i, num = 0;
 103
 104         if (!panel->desc)
 105                 return 0;
 106
 107         for (i = 0; i < panel->desc->num_timings; i++) {
 108                 const struct display_timing *dt = &panel->desc->timings[i];
 109                 struct videomode vm;
 110
 111                 videomode_from_timing(dt, &vm);
 112                 mode = drm_mode_create(drm);
 113                 if (!mode) {
 114                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 115                                 dt->hactive.typ, dt->vactive.typ);
 116                         continue;
 117                 }
 118
 119                 drm_display_mode_from_videomode(&vm, mode);
 120
 121                 mode->type |= DRM_MODE_TYPE_DRIVER;
 122
 123                 if (panel->desc->num_modes == 1)
 124                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 125
 126                 drm_mode_probed_add(connector, mode);
 127                 num++;
 128         }
 129
 130         for (i = 0; i < panel->desc->num_modes; i++) {
 131                 const struct drm_display_mode *m = &panel->desc->modes[i];
 132
 133                 mode = drm_mode_duplicate(drm, m);
 134                 if (!mode) {
 135                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 136                                 m->hdisplay, m->vdisplay, m->vrefresh);
 137                         continue;
 138                 }
 139
 140                 mode->type |= DRM_MODE_TYPE_DRIVER;
 141
 142                 if (panel->desc->num_modes == 1)
 143                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 144
 145                 drm_mode_set_name(mode);
 146
 147                 drm_mode_probed_add(connector, mode);
 148                 num++;
 149         }
 150
 151         connector->display_info.bpc = panel->desc->bpc;
 152         connector->display_info.width_mm = panel->desc->size.width;
 153         connector->display_info.height_mm = panel->desc->size.height;
 154         if (panel->desc->bus_format)
 155                 drm_display_info_set_bus_formats(&connector->display_info,
 156                                                  &panel->desc->bus_format, 1);
 157         connector->display_info.bus_flags = panel->desc->bus_flags;
 158
 159         return num;
 160 }
 161
 162 static int panel_simple_disable(struct drm_panel *panel)
 163 {
 164         struct panel_simple *p = to_panel_simple(panel);
 165
 166         if (!p->enabled)
 167                 return 0;
 168
 169         if (p->backlight) {
 170                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 171                 p->backlight->props.state |= BL_CORE_FBBLANK;
 172                 backlight_update_status(p->backlight);
 173         }
 174
 175         if (p->desc->delay.disable)
 176                 msleep(p->desc->delay.disable);
 177
 178         p->enabled = false;
 179
 180         return 0;
 181 }
 182
 183 static int panel_simple_unprepare(struct drm_panel *panel)
 184 {
 185         struct panel_simple *p = to_panel_simple(panel);
 186
 187         if (!p->prepared)
 188                 return 0;
 189
 190         if (p->enable_gpio)
 191                 gpiod_set_value_cansleep(p->enable_gpio, 0);
 192
 193         regulator_disable(p->supply);
 194
 195         if (p->desc->delay.unprepare)
 196                 msleep(p->desc->delay.unprepare);
 197
 198         p->prepared = false;
 199
 200         return 0;
 201 }
 202
 203 static int panel_simple_prepare(struct drm_panel *panel)
 204 {
 205         struct panel_simple *p = to_panel_simple(panel);
 206         int err;
 207
 208         if (p->prepared)
 209                 return 0;
 210
 211         err = regulator_enable(p->supply);
 212         if (err < 0) {
 213                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 214                 return err;
 215         }
 216
 217         if (p->enable_gpio)
 218                 gpiod_set_value_cansleep(p->enable_gpio, 1);
 219
 220         if (p->desc->delay.prepare)
 221                 msleep(p->desc->delay.prepare);
 222
 223         p->prepared = true;
 224
 225         return 0;
 226 }
 227
 228 static int panel_simple_enable(struct drm_panel *panel)
 229 {
 230         struct panel_simple *p = to_panel_simple(panel);
 231
 232         if (p->enabled)
 233                 return 0;
 234
 235         if (p->desc->delay.enable)
 236                 msleep(p->desc->delay.enable);
 237
 238         if (p->backlight) {
 239                 p->backlight->props.state &= ~BL_CORE_FBBLANK;
 240                 p->backlight->props.power = FB_BLANK_UNBLANK;
 241                 backlight_update_status(p->backlight);
 242         }
 243
 244         p->enabled = true;
 245
 246         return 0;
 247 }
 248
 249 static int panel_simple_get_modes(struct drm_panel *panel)
 250 {
 251         struct panel_simple *p = to_panel_simple(panel);
 252         int num = 0;
 253
 254         /* probe EDID if a DDC bus is available */
 255         if (p->ddc) {
 256                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 257                 drm_mode_connector_update_edid_property(panel->connector, edid);
 258                 if (edid) {
 259                         num += drm_add_edid_modes(panel->connector, edid);
 260                         kfree(edid);
 261                 }
 262         }
 263
 264         /* add hard-coded panel modes */
 265         num += panel_simple_get_fixed_modes(p);
 266
 267         return num;
 268 }
 269
 270 static int panel_simple_get_timings(struct drm_panel *panel,
 271                                     unsigned int num_timings,
 272                                     struct display_timing *timings)
 273 {
 274         struct panel_simple *p = to_panel_simple(panel);
 275         unsigned int i;
 276
 277         if (p->desc->num_timings < num_timings)
 278                 num_timings = p->desc->num_timings;
 279
 280         if (timings)
 281                 for (i = 0; i < num_timings; i++)
 282                         timings[i] = p->desc->timings[i];
 283
 284         return p->desc->num_timings;
 285 }
 286
 287 static const struct drm_panel_funcs panel_simple_funcs = {
 288         .disable = panel_simple_disable,
 289         .unprepare = panel_simple_unprepare,
 290         .prepare = panel_simple_prepare,
 291         .enable = panel_simple_enable,
 292         .get_modes = panel_simple_get_modes,
 293         .get_timings = panel_simple_get_timings,
 294 };
 295
 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 297 {
 298         struct device_node *backlight, *ddc;
 299         struct panel_simple *panel;
 300         int err;
 301
 302         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 303         if (!panel)
 304                 return -ENOMEM;
 305
 306         panel->enabled = false;
 307         panel->prepared = false;
 308         panel->desc = desc;
 309
 310         panel->supply = devm_regulator_get(dev, "power");
 311         if (IS_ERR(panel->supply))
 312                 return PTR_ERR(panel->supply);
 313
 314         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 315                                                      GPIOD_OUT_LOW);
 316         if (IS_ERR(panel->enable_gpio)) {
 317                 err = PTR_ERR(panel->enable_gpio);
 318                 dev_err(dev, "failed to request GPIO: %d\n", err);
 319                 return err;
 320         }
 321
 322         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 323         if (backlight) {
 324                 panel->backlight = of_find_backlight_by_node(backlight);
 325                 of_node_put(backlight);
 326
 327                 if (!panel->backlight)
 328                         return -EPROBE_DEFER;
 329         }
 330
 331         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 332         if (ddc) {
 333                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 334                 of_node_put(ddc);
 335
 336                 if (!panel->ddc) {
 337                         err = -EPROBE_DEFER;
 338                         goto free_backlight;
 339                 }
 340         }
 341
 342         drm_panel_init(&panel->base);
 343         panel->base.dev = dev;
 344         panel->base.funcs = &panel_simple_funcs;
 345
 346         err = drm_panel_add(&panel->base);
 347         if (err < 0)
 348                 goto free_ddc;
 349
 350         dev_set_drvdata(dev, panel);
 351
 352         return 0;
 353
 354 free_ddc:
 355         if (panel->ddc)
 356                 put_device(&panel->ddc->dev);
 357 free_backlight:
 358         if (panel->backlight)
 359                 put_device(&panel->backlight->dev);
 360
 361         return err;
 362 }
 363
 364 static int panel_simple_remove(struct device *dev)
 365 {
 366         struct panel_simple *panel = dev_get_drvdata(dev);
 367
 368         drm_panel_detach(&panel->base);
 369         drm_panel_remove(&panel->base);
 370
 371         panel_simple_disable(&panel->base);
 372
 373         if (panel->ddc)
 374                 put_device(&panel->ddc->dev);
 375
 376         if (panel->backlight)
 377                 put_device(&panel->backlight->dev);
 378
 379         return 0;
 380 }
 381
 382 static void panel_simple_shutdown(struct device *dev)
 383 {
 384         struct panel_simple *panel = dev_get_drvdata(dev);
 385
 386         panel_simple_disable(&panel->base);
 387 }
 388
 389 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 390         .clock = 33333,
 391         .hdisplay = 800,
 392         .hsync_start = 800 + 0,
 393         .hsync_end = 800 + 0 + 255,
 394         .htotal = 800 + 0 + 255 + 0,
 395         .vdisplay = 480,
 396         .vsync_start = 480 + 2,
 397         .vsync_end = 480 + 2 + 45,
 398         .vtotal = 480 + 2 + 45 + 0,
 399         .vrefresh = 60,
 400         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 401 };
 402
 403 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 404         .modes = &ampire_am800480r3tmqwa1h_mode,
 405         .num_modes = 1,
 406         .bpc = 6,
 407         .size = {
 408                 .width = 152,
 409                 .height = 91,
 410         },
 411         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 412 };
 413
 414 static const struct drm_display_mode auo_b101aw03_mode = {
 415         .clock = 51450,
 416         .hdisplay = 1024,
 417         .hsync_start = 1024 + 156,
 418         .hsync_end = 1024 + 156 + 8,
 419         .htotal = 1024 + 156 + 8 + 156,
 420         .vdisplay = 600,
 421         .vsync_start = 600 + 16,
 422         .vsync_end = 600 + 16 + 6,
 423         .vtotal = 600 + 16 + 6 + 16,
 424         .vrefresh = 60,
 425 };
 426
 427 static const struct panel_desc auo_b101aw03 = {
 428         .modes = &auo_b101aw03_mode,
 429         .num_modes = 1,
 430         .bpc = 6,
 431         .size = {
 432                 .width = 223,
 433                 .height = 125,
 434         },
 435 };
 436
 437 static const struct drm_display_mode auo_b101ean01_mode = {
 438         .clock = 72500,
 439         .hdisplay = 1280,
 440         .hsync_start = 1280 + 119,
 441         .hsync_end = 1280 + 119 + 32,
 442         .htotal = 1280 + 119 + 32 + 21,
 443         .vdisplay = 800,
 444         .vsync_start = 800 + 4,
 445         .vsync_end = 800 + 4 + 20,
 446         .vtotal = 800 + 4 + 20 + 8,
 447         .vrefresh = 60,
 448 };
 449
 450 static const struct panel_desc auo_b101ean01 = {
 451         .modes = &auo_b101ean01_mode,
 452         .num_modes = 1,
 453         .bpc = 6,
 454         .size = {
 455                 .width = 217,
 456                 .height = 136,
 457         },
 458 };
 459
 460 static const struct drm_display_mode auo_b101xtn01_mode = {
 461         .clock = 72000,
 462         .hdisplay = 1366,
 463         .hsync_start = 1366 + 20,
 464         .hsync_end = 1366 + 20 + 70,
 465         .htotal = 1366 + 20 + 70,
 466         .vdisplay = 768,
 467         .vsync_start = 768 + 14,
 468         .vsync_end = 768 + 14 + 42,
 469         .vtotal = 768 + 14 + 42,
 470         .vrefresh = 60,
 471         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 472 };
 473
 474 static const struct panel_desc auo_b101xtn01 = {
 475         .modes = &auo_b101xtn01_mode,
 476         .num_modes = 1,
 477         .bpc = 6,
 478         .size = {
 479                 .width = 223,
 480                 .height = 125,
 481         },
 482 };
 483
 484 static const struct drm_display_mode auo_b116xw03_mode = {
 485         .clock = 70589,
 486         .hdisplay = 1366,
 487         .hsync_start = 1366 + 40,
 488         .hsync_end = 1366 + 40 + 40,
 489         .htotal = 1366 + 40 + 40 + 32,
 490         .vdisplay = 768,
 491         .vsync_start = 768 + 10,
 492         .vsync_end = 768 + 10 + 12,
 493         .vtotal = 768 + 10 + 12 + 6,
 494         .vrefresh = 60,
 495 };
 496
 497 static const struct panel_desc auo_b116xw03 = {
 498         .modes = &auo_b116xw03_mode,
 499         .num_modes = 1,
 500         .bpc = 6,
 501         .size = {
 502                 .width = 256,
 503                 .height = 144,
 504         },
 505 };
 506
 507 static const struct drm_display_mode auo_b133xtn01_mode = {
 508         .clock = 69500,
 509         .hdisplay = 1366,
 510         .hsync_start = 1366 + 48,
 511         .hsync_end = 1366 + 48 + 32,
 512         .htotal = 1366 + 48 + 32 + 20,
 513         .vdisplay = 768,
 514         .vsync_start = 768 + 3,
 515         .vsync_end = 768 + 3 + 6,
 516         .vtotal = 768 + 3 + 6 + 13,
 517         .vrefresh = 60,
 518 };
 519
 520 static const struct panel_desc auo_b133xtn01 = {
 521         .modes = &auo_b133xtn01_mode,
 522         .num_modes = 1,
 523         .bpc = 6,
 524         .size = {
 525                 .width = 293,
 526                 .height = 165,
 527         },
 528 };
 529
 530 static const struct drm_display_mode auo_b133htn01_mode = {
 531         .clock = 150660,
 532         .hdisplay = 1920,
 533         .hsync_start = 1920 + 172,
 534         .hsync_end = 1920 + 172 + 80,
 535         .htotal = 1920 + 172 + 80 + 60,
 536         .vdisplay = 1080,
 537         .vsync_start = 1080 + 25,
 538         .vsync_end = 1080 + 25 + 10,
 539         .vtotal = 1080 + 25 + 10 + 10,
 540         .vrefresh = 60,
 541 };
 542
 543 static const struct panel_desc auo_b133htn01 = {
 544         .modes = &auo_b133htn01_mode,
 545         .num_modes = 1,
 546         .bpc = 6,
 547         .size = {
 548                 .width = 293,
 549                 .height = 165,
 550         },
 551         .delay = {
 552                 .prepare = 105,
 553                 .enable = 20,
 554                 .unprepare = 50,
 555         },
 556 };
 557
 558 static const struct drm_display_mode avic_tm070ddh03_mode = {
 559         .clock = 51200,
 560         .hdisplay = 1024,
 561         .hsync_start = 1024 + 160,
 562         .hsync_end = 1024 + 160 + 4,
 563         .htotal = 1024 + 160 + 4 + 156,
 564         .vdisplay = 600,
 565         .vsync_start = 600 + 17,
 566         .vsync_end = 600 + 17 + 1,
 567         .vtotal = 600 + 17 + 1 + 17,
 568         .vrefresh = 60,
 569 };
 570
 571 static const struct panel_desc avic_tm070ddh03 = {
 572         .modes = &avic_tm070ddh03_mode,
 573         .num_modes = 1,
 574         .bpc = 8,
 575         .size = {
 576                 .width = 154,
 577                 .height = 90,
 578         },
 579         .delay = {
 580                 .prepare = 20,
 581                 .enable = 200,
 582                 .disable = 200,
 583         },
 584 };
 585
 586 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 587         .clock = 72070,
 588         .hdisplay = 1366,
 589         .hsync_start = 1366 + 58,
 590         .hsync_end = 1366 + 58 + 58,
 591         .htotal = 1366 + 58 + 58 + 58,
 592         .vdisplay = 768,
 593         .vsync_start = 768 + 4,
 594         .vsync_end = 768 + 4 + 4,
 595         .vtotal = 768 + 4 + 4 + 4,
 596         .vrefresh = 60,
 597 };
 598
 599 static const struct panel_desc chunghwa_claa101wa01a = {
 600         .modes = &chunghwa_claa101wa01a_mode,
 601         .num_modes = 1,
 602         .bpc = 6,
 603         .size = {
 604                 .width = 220,
 605                 .height = 120,
 606         },
 607 };
 608
 609 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 610         .clock = 69300,
 611         .hdisplay = 1366,
 612         .hsync_start = 1366 + 48,
 613         .hsync_end = 1366 + 48 + 32,
 614         .htotal = 1366 + 48 + 32 + 20,
 615         .vdisplay = 768,
 616         .vsync_start = 768 + 16,
 617         .vsync_end = 768 + 16 + 8,
 618         .vtotal = 768 + 16 + 8 + 16,
 619         .vrefresh = 60,
 620 };
 621
 622 static const struct panel_desc chunghwa_claa101wb01 = {
 623         .modes = &chunghwa_claa101wb01_mode,
 624         .num_modes = 1,
 625         .bpc = 6,
 626         .size = {
 627                 .width = 223,
 628                 .height = 125,
 629         },
 630 };
 631
 632 static const struct drm_display_mode edt_et057090dhu_mode = {
 633         .clock = 25175,
 634         .hdisplay = 640,
 635         .hsync_start = 640 + 16,
 636         .hsync_end = 640 + 16 + 30,
 637         .htotal = 640 + 16 + 30 + 114,
 638         .vdisplay = 480,
 639         .vsync_start = 480 + 10,
 640         .vsync_end = 480 + 10 + 3,
 641         .vtotal = 480 + 10 + 3 + 32,
 642         .vrefresh = 60,
 643         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 644 };
 645
 646 static const struct panel_desc edt_et057090dhu = {
 647         .modes = &edt_et057090dhu_mode,
 648         .num_modes = 1,
 649         .bpc = 6,
 650         .size = {
 651                 .width = 115,
 652                 .height = 86,
 653         },
 654 };
 655
 656 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
 657         .clock = 33260,
 658         .hdisplay = 800,
 659         .hsync_start = 800 + 40,
 660         .hsync_end = 800 + 40 + 128,
 661         .htotal = 800 + 40 + 128 + 88,
 662         .vdisplay = 480,
 663         .vsync_start = 480 + 10,
 664         .vsync_end = 480 + 10 + 2,
 665         .vtotal = 480 + 10 + 2 + 33,
 666         .vrefresh = 60,
 667         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 668 };
 669
 670 static const struct panel_desc edt_etm0700g0dh6 = {
 671         .modes = &edt_etm0700g0dh6_mode,
 672         .num_modes = 1,
 673         .bpc = 6,
 674         .size = {
 675                 .width = 152,
 676                 .height = 91,
 677         },
 678 };
 679
 680 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
 681         .clock = 32260,
 682         .hdisplay = 800,
 683         .hsync_start = 800 + 168,
 684         .hsync_end = 800 + 168 + 64,
 685         .htotal = 800 + 168 + 64 + 88,
 686         .vdisplay = 480,
 687         .vsync_start = 480 + 37,
 688         .vsync_end = 480 + 37 + 2,
 689         .vtotal = 480 + 37 + 2 + 8,
 690         .vrefresh = 60,
 691 };
 692
 693 static const struct panel_desc foxlink_fl500wvr00_a0t = {
 694         .modes = &foxlink_fl500wvr00_a0t_mode,
 695         .num_modes = 1,
 696         .bpc = 8,
 697         .size = {
 698                 .width = 108,
 699                 .height = 65,
 700         },
 701         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 702 };
 703
 704 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
 705         .clock = 9000,
 706         .hdisplay = 480,
 707         .hsync_start = 480 + 5,
 708         .hsync_end = 480 + 5 + 1,
 709         .htotal = 480 + 5 + 1 + 40,
 710         .vdisplay = 272,
 711         .vsync_start = 272 + 8,
 712         .vsync_end = 272 + 8 + 1,
 713         .vtotal = 272 + 8 + 1 + 8,
 714         .vrefresh = 60,
 715 };
 716
 717 static const struct panel_desc giantplus_gpg482739qs5 = {
 718         .modes = &giantplus_gpg482739qs5_mode,
 719         .num_modes = 1,
 720         .bpc = 8,
 721         .size = {
 722                 .width = 95,
 723                 .height = 54,
 724         },
 725         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 726 };
 727
 728 static const struct display_timing hannstar_hsd070pww1_timing = {
 729         .pixelclock = { 64300000, 71100000, 82000000 },
 730         .hactive = { 1280, 1280, 1280 },
 731         .hfront_porch = { 1, 1, 10 },
 732         .hback_porch = { 1, 1, 10 },
 733         /*
 734          * According to the data sheet, the minimum horizontal blanking interval
 735          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
 736          * minimum working horizontal blanking interval to be 60 clocks.
 737          */
 738         .hsync_len = { 58, 158, 661 },
 739         .vactive = { 800, 800, 800 },
 740         .vfront_porch = { 1, 1, 10 },
 741         .vback_porch = { 1, 1, 10 },
 742         .vsync_len = { 1, 21, 203 },
 743         .flags = DISPLAY_FLAGS_DE_HIGH,
 744 };
 745
 746 static const struct panel_desc hannstar_hsd070pww1 = {
 747         .timings = &hannstar_hsd070pww1_timing,
 748         .num_timings = 1,
 749         .bpc = 6,
 750         .size = {
 751                 .width = 151,
 752                 .height = 94,
 753         },
 754         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 755 };
 756
 757 static const struct display_timing hannstar_hsd100pxn1_timing = {
 758         .pixelclock = { 55000000, 65000000, 75000000 },
 759         .hactive = { 1024, 1024, 1024 },
 760         .hfront_porch = { 40, 40, 40 },
 761         .hback_porch = { 220, 220, 220 },
 762         .hsync_len = { 20, 60, 100 },
 763         .vactive = { 768, 768, 768 },
 764         .vfront_porch = { 7, 7, 7 },
 765         .vback_porch = { 21, 21, 21 },
 766         .vsync_len = { 10, 10, 10 },
 767         .flags = DISPLAY_FLAGS_DE_HIGH,
 768 };
 769
 770 static const struct panel_desc hannstar_hsd100pxn1 = {
 771         .timings = &hannstar_hsd100pxn1_timing,
 772         .num_timings = 1,
 773         .bpc = 6,
 774         .size = {
 775                 .width = 203,
 776                 .height = 152,
 777         },
 778         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 779 };
 780
 781 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
 782         .clock = 33333,
 783         .hdisplay = 800,
 784         .hsync_start = 800 + 85,
 785         .hsync_end = 800 + 85 + 86,
 786         .htotal = 800 + 85 + 86 + 85,
 787         .vdisplay = 480,
 788         .vsync_start = 480 + 16,
 789         .vsync_end = 480 + 16 + 13,
 790         .vtotal = 480 + 16 + 13 + 16,
 791         .vrefresh = 60,
 792 };
 793
 794 static const struct panel_desc hitachi_tx23d38vm0caa = {
 795         .modes = &hitachi_tx23d38vm0caa_mode,
 796         .num_modes = 1,
 797         .bpc = 6,
 798         .size = {
 799                 .width = 195,
 800                 .height = 117,
 801         },
 802 };
 803
 804 static const struct drm_display_mode innolux_at043tn24_mode = {
 805         .clock = 9000,
 806         .hdisplay = 480,
 807         .hsync_start = 480 + 2,
 808         .hsync_end = 480 + 2 + 41,
 809         .htotal = 480 + 2 + 41 + 2,
 810         .vdisplay = 272,
 811         .vsync_start = 272 + 2,
 812         .vsync_end = 272 + 2 + 11,
 813         .vtotal = 272 + 2 + 11 + 2,
 814         .vrefresh = 60,
 815         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 816 };
 817
 818 static const struct panel_desc innolux_at043tn24 = {
 819         .modes = &innolux_at043tn24_mode,
 820         .num_modes = 1,
 821         .bpc = 8,
 822         .size = {
 823                 .width = 95,
 824                 .height = 54,
 825         },
 826         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 827 };
 828
 829 static const struct drm_display_mode innolux_at070tn92_mode = {
 830         .clock = 33333,
 831         .hdisplay = 800,
 832         .hsync_start = 800 + 210,
 833         .hsync_end = 800 + 210 + 20,
 834         .htotal = 800 + 210 + 20 + 46,
 835         .vdisplay = 480,
 836         .vsync_start = 480 + 22,
 837         .vsync_end = 480 + 22 + 10,
 838         .vtotal = 480 + 22 + 23 + 10,
 839         .vrefresh = 60,
 840 };
 841
 842 static const struct panel_desc innolux_at070tn92 = {
 843         .modes = &innolux_at070tn92_mode,
 844         .num_modes = 1,
 845         .size = {
 846                 .width = 154,
 847                 .height = 86,
 848         },
 849         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 850 };
 851
 852 static const struct drm_display_mode innolux_g121i1_l01_mode = {
 853         .clock = 71000,
 854         .hdisplay = 1280,
 855         .hsync_start = 1280 + 64,
 856         .hsync_end = 1280 + 64 + 32,
 857         .htotal = 1280 + 64 + 32 + 64,
 858         .vdisplay = 800,
 859         .vsync_start = 800 + 9,
 860         .vsync_end = 800 + 9 + 6,
 861         .vtotal = 800 + 9 + 6 + 9,
 862         .vrefresh = 60,
 863 };
 864
 865 static const struct panel_desc innolux_g121i1_l01 = {
 866         .modes = &innolux_g121i1_l01_mode,
 867         .num_modes = 1,
 868         .bpc = 6,
 869         .size = {
 870                 .width = 261,
 871                 .height = 163,
 872         },
 873 };
 874
 875 static const struct drm_display_mode innolux_g121x1_l03_mode = {
 876         .clock = 65000,
 877         .hdisplay = 1024,
 878         .hsync_start = 1024 + 0,
 879         .hsync_end = 1024 + 1,
 880         .htotal = 1024 + 0 + 1 + 320,
 881         .vdisplay = 768,
 882         .vsync_start = 768 + 38,
 883         .vsync_end = 768 + 38 + 1,
 884         .vtotal = 768 + 38 + 1 + 0,
 885         .vrefresh = 60,
 886         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 887 };
 888
 889 static const struct panel_desc innolux_g121x1_l03 = {
 890         .modes = &innolux_g121x1_l03_mode,
 891         .num_modes = 1,
 892         .bpc = 6,
 893         .size = {
 894                 .width = 246,
 895                 .height = 185,
 896         },
 897         .delay = {
 898                 .enable = 200,
 899                 .unprepare = 200,
 900                 .disable = 400,
 901         },
 902 };
 903
 904 static const struct drm_display_mode innolux_n116bge_mode = {
 905         .clock = 76420,
 906         .hdisplay = 1366,
 907         .hsync_start = 1366 + 136,
 908         .hsync_end = 1366 + 136 + 30,
 909         .htotal = 1366 + 136 + 30 + 60,
 910         .vdisplay = 768,
 911         .vsync_start = 768 + 8,
 912         .vsync_end = 768 + 8 + 12,
 913         .vtotal = 768 + 8 + 12 + 12,
 914         .vrefresh = 60,
 915         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 916 };
 917
 918 static const struct panel_desc innolux_n116bge = {
 919         .modes = &innolux_n116bge_mode,
 920         .num_modes = 1,
 921         .bpc = 6,
 922         .size = {
 923                 .width = 256,
 924                 .height = 144,
 925         },
 926 };
 927
 928 static const struct drm_display_mode innolux_n156bge_l21_mode = {
 929         .clock = 69300,
 930         .hdisplay = 1366,
 931         .hsync_start = 1366 + 16,
 932         .hsync_end = 1366 + 16 + 34,
 933         .htotal = 1366 + 16 + 34 + 50,
 934         .vdisplay = 768,
 935         .vsync_start = 768 + 2,
 936         .vsync_end = 768 + 2 + 6,
 937         .vtotal = 768 + 2 + 6 + 12,
 938         .vrefresh = 60,
 939 };
 940
 941 static const struct panel_desc innolux_n156bge_l21 = {
 942         .modes = &innolux_n156bge_l21_mode,
 943         .num_modes = 1,
 944         .bpc = 6,
 945         .size = {
 946                 .width = 344,
 947                 .height = 193,
 948         },
 949 };
 950
 951 static const struct drm_display_mode innolux_zj070na_01p_mode = {
 952         .clock = 51501,
 953         .hdisplay = 1024,
 954         .hsync_start = 1024 + 128,
 955         .hsync_end = 1024 + 128 + 64,
 956         .htotal = 1024 + 128 + 64 + 128,
 957         .vdisplay = 600,
 958         .vsync_start = 600 + 16,
 959         .vsync_end = 600 + 16 + 4,
 960         .vtotal = 600 + 16 + 4 + 16,
 961         .vrefresh = 60,
 962 };
 963
 964 static const struct panel_desc innolux_zj070na_01p = {
 965         .modes = &innolux_zj070na_01p_mode,
 966         .num_modes = 1,
 967         .bpc = 6,
 968         .size = {
 969                 .width = 154,
 970                 .height = 90,
 971         },
 972 };
 973
 974 static const struct display_timing kyo_tcg121xglp_timing = {
 975         .pixelclock = { 52000000, 65000000, 71000000 },
 976         .hactive = { 1024, 1024, 1024 },
 977         .hfront_porch = { 2, 2, 2 },
 978         .hback_porch = { 2, 2, 2 },
 979         .hsync_len = { 86, 124, 244 },
 980         .vactive = { 768, 768, 768 },
 981         .vfront_porch = { 2, 2, 2 },
 982         .vback_porch = { 2, 2, 2 },
 983         .vsync_len = { 6, 34, 73 },
 984         .flags = DISPLAY_FLAGS_DE_HIGH,
 985 };
 986
 987 static const struct panel_desc kyo_tcg121xglp = {
 988         .timings = &kyo_tcg121xglp_timing,
 989         .num_timings = 1,
 990         .bpc = 8,
 991         .size = {
 992                 .width = 246,
 993                 .height = 184,
 994         },
 995         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 996 };
 997
 998 static const struct drm_display_mode lg_lb070wv8_mode = {
 999         .clock = 33246,
1000         .hdisplay = 800,
1001         .hsync_start = 800 + 88,
1002         .hsync_end = 800 + 88 + 80,
1003         .htotal = 800 + 88 + 80 + 88,
1004         .vdisplay = 480,
1005         .vsync_start = 480 + 10,
1006         .vsync_end = 480 + 10 + 25,
1007         .vtotal = 480 + 10 + 25 + 10,
1008         .vrefresh = 60,
1009 };
1010
1011 static const struct panel_desc lg_lb070wv8 = {
1012         .modes = &lg_lb070wv8_mode,
1013         .num_modes = 1,
1014         .bpc = 16,
1015         .size = {
1016                 .width = 151,
1017                 .height = 91,
1018         },
1019         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1020 };
1021
1022 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1023         .clock = 200000,
1024         .hdisplay = 1536,
1025         .hsync_start = 1536 + 12,
1026         .hsync_end = 1536 + 12 + 16,
1027         .htotal = 1536 + 12 + 16 + 48,
1028         .vdisplay = 2048,
1029         .vsync_start = 2048 + 8,
1030         .vsync_end = 2048 + 8 + 4,
1031         .vtotal = 2048 + 8 + 4 + 8,
1032         .vrefresh = 60,
1033         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1034 };
1035
1036 static const struct panel_desc lg_lp079qx1_sp0v = {
1037         .modes = &lg_lp079qx1_sp0v_mode,
1038         .num_modes = 1,
1039         .size = {
1040                 .width = 129,
1041                 .height = 171,
1042         },
1043 };
1044
1045 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1046         .clock = 205210,
1047         .hdisplay = 2048,
1048         .hsync_start = 2048 + 150,
1049         .hsync_end = 2048 + 150 + 5,
1050         .htotal = 2048 + 150 + 5 + 5,
1051         .vdisplay = 1536,
1052         .vsync_start = 1536 + 3,
1053         .vsync_end = 1536 + 3 + 1,
1054         .vtotal = 1536 + 3 + 1 + 9,
1055         .vrefresh = 60,
1056 };
1057
1058 static const struct panel_desc lg_lp097qx1_spa1 = {
1059         .modes = &lg_lp097qx1_spa1_mode,
1060         .num_modes = 1,
1061         .size = {
1062                 .width = 208,
1063                 .height = 147,
1064         },
1065 };
1066
1067 static const struct drm_display_mode lg_lp120up1_mode = {
1068         .clock = 162300,
1069         .hdisplay = 1920,
1070         .hsync_start = 1920 + 40,
1071         .hsync_end = 1920 + 40 + 40,
1072         .htotal = 1920 + 40 + 40+ 80,
1073         .vdisplay = 1280,
1074         .vsync_start = 1280 + 4,
1075         .vsync_end = 1280 + 4 + 4,
1076         .vtotal = 1280 + 4 + 4 + 12,
1077         .vrefresh = 60,
1078 };
1079
1080 static const struct panel_desc lg_lp120up1 = {
1081         .modes = &lg_lp120up1_mode,
1082         .num_modes = 1,
1083         .bpc = 8,
1084         .size = {
1085                 .width = 267,
1086                 .height = 183,
1087         },
1088 };
1089
1090 static const struct drm_display_mode lg_lp129qe_mode = {
1091         .clock = 285250,
1092         .hdisplay = 2560,
1093         .hsync_start = 2560 + 48,
1094         .hsync_end = 2560 + 48 + 32,
1095         .htotal = 2560 + 48 + 32 + 80,
1096         .vdisplay = 1700,
1097         .vsync_start = 1700 + 3,
1098         .vsync_end = 1700 + 3 + 10,
1099         .vtotal = 1700 + 3 + 10 + 36,
1100         .vrefresh = 60,
1101 };
1102
1103 static const struct panel_desc lg_lp129qe = {
1104         .modes = &lg_lp129qe_mode,
1105         .num_modes = 1,
1106         .bpc = 8,
1107         .size = {
1108                 .width = 272,
1109                 .height = 181,
1110         },
1111 };
1112
1113 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1114         .clock = 10870,
1115         .hdisplay = 480,
1116         .hsync_start = 480 + 2,
1117         .hsync_end = 480 + 2 + 41,
1118         .htotal = 480 + 2 + 41 + 2,
1119         .vdisplay = 272,
1120         .vsync_start = 272 + 2,
1121         .vsync_end = 272 + 2 + 4,
1122         .vtotal = 272 + 2 + 4 + 2,
1123         .vrefresh = 74,
1124         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1125 };
1126
1127 static const struct panel_desc nec_nl4827hc19_05b = {
1128         .modes = &nec_nl4827hc19_05b_mode,
1129         .num_modes = 1,
1130         .bpc = 8,
1131         .size = {
1132                 .width = 95,
1133                 .height = 54,
1134         },
1135         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1136         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1137 };
1138
1139 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1140         .pixelclock = { 30000000, 30000000, 40000000 },
1141         .hactive = { 800, 800, 800 },
1142         .hfront_porch = { 40, 40, 40 },
1143         .hback_porch = { 40, 40, 40 },
1144         .hsync_len = { 1, 48, 48 },
1145         .vactive = { 480, 480, 480 },
1146         .vfront_porch = { 13, 13, 13 },
1147         .vback_porch = { 29, 29, 29 },
1148         .vsync_len = { 3, 3, 3 },
1149         .flags = DISPLAY_FLAGS_DE_HIGH,
1150 };
1151
1152 static const struct panel_desc okaya_rs800480t_7x0gp = {
1153         .timings = &okaya_rs800480t_7x0gp_timing,
1154         .num_timings = 1,
1155         .bpc = 6,
1156         .size = {
1157                 .width = 154,
1158                 .height = 87,
1159         },
1160         .delay = {
1161                 .prepare = 41,
1162                 .enable = 50,
1163                 .unprepare = 41,
1164                 .disable = 50,
1165         },
1166         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1167 };
1168
1169 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1170         .clock = 9000,
1171         .hdisplay = 480,
1172         .hsync_start = 480 + 5,
1173         .hsync_end = 480 + 5 + 30,
1174         .htotal = 480 + 5 + 30 + 10,
1175         .vdisplay = 272,
1176         .vsync_start = 272 + 8,
1177         .vsync_end = 272 + 8 + 5,
1178         .vtotal = 272 + 8 + 5 + 3,
1179         .vrefresh = 60,
1180 };
1181
1182 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1183         .modes = &olimex_lcd_olinuxino_43ts_mode,
1184         .num_modes = 1,
1185         .size = {
1186                 .width = 105,
1187                 .height = 67,
1188         },
1189         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1190 };
1191
1192 /*
1193  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1194  * pixel clocks, but this is the timing that was being used in the Adafruit
1195  * installation instructions.
1196  */
1197 static const struct drm_display_mode ontat_yx700wv03_mode = {
1198         .clock = 29500,
1199         .hdisplay = 800,
1200         .hsync_start = 824,
1201         .hsync_end = 896,
1202         .htotal = 992,
1203         .vdisplay = 480,
1204         .vsync_start = 483,
1205         .vsync_end = 493,
1206         .vtotal = 500,
1207         .vrefresh = 60,
1208         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1209 };
1210
1211 /*
1212  * Specification at:
1213  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1214  */
1215 static const struct panel_desc ontat_yx700wv03 = {
1216         .modes = &ontat_yx700wv03_mode,
1217         .num_modes = 1,
1218         .bpc = 8,
1219         .size = {
1220                 .width = 154,
1221                 .height = 83,
1222         },
1223         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1224 };
1225
1226 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1227         .clock = 25000,
1228         .hdisplay = 480,
1229         .hsync_start = 480 + 10,
1230         .hsync_end = 480 + 10 + 10,
1231         .htotal = 480 + 10 + 10 + 15,
1232         .vdisplay = 800,
1233         .vsync_start = 800 + 3,
1234         .vsync_end = 800 + 3 + 3,
1235         .vtotal = 800 + 3 + 3 + 3,
1236         .vrefresh = 60,
1237 };
1238
1239 static const struct panel_desc ortustech_com43h4m85ulc = {
1240         .modes = &ortustech_com43h4m85ulc_mode,
1241         .num_modes = 1,
1242         .bpc = 8,
1243         .size = {
1244                 .width = 56,
1245                 .height = 93,
1246         },
1247         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1248 };
1249
1250 static const struct drm_display_mode qd43003c0_40_mode = {
1251         .clock = 9000,
1252         .hdisplay = 480,
1253         .hsync_start = 480 + 8,
1254         .hsync_end = 480 + 8 + 4,
1255         .htotal = 480 + 8 + 4 + 39,
1256         .vdisplay = 272,
1257         .vsync_start = 272 + 4,
1258         .vsync_end = 272 + 4 + 10,
1259         .vtotal = 272 + 4 + 10 + 2,
1260         .vrefresh = 60,
1261 };
1262
1263 static const struct panel_desc qd43003c0_40 = {
1264         .modes = &qd43003c0_40_mode,
1265         .num_modes = 1,
1266         .bpc = 8,
1267         .size = {
1268                 .width = 95,
1269                 .height = 53,
1270         },
1271         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1272 };
1273
1274 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1275         .clock = 271560,
1276         .hdisplay = 2560,
1277         .hsync_start = 2560 + 48,
1278         .hsync_end = 2560 + 48 + 32,
1279         .htotal = 2560 + 48 + 32 + 80,
1280         .vdisplay = 1600,
1281         .vsync_start = 1600 + 2,
1282         .vsync_end = 1600 + 2 + 5,
1283         .vtotal = 1600 + 2 + 5 + 57,
1284         .vrefresh = 60,
1285 };
1286
1287 static const struct panel_desc samsung_lsn122dl01_c01 = {
1288         .modes = &samsung_lsn122dl01_c01_mode,
1289         .num_modes = 1,
1290         .size = {
1291                 .width = 263,
1292                 .height = 164,
1293         },
1294 };
1295
1296 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1297         .clock = 54030,
1298         .hdisplay = 1024,
1299         .hsync_start = 1024 + 24,
1300         .hsync_end = 1024 + 24 + 136,
1301         .htotal = 1024 + 24 + 136 + 160,
1302         .vdisplay = 600,
1303         .vsync_start = 600 + 3,
1304         .vsync_end = 600 + 3 + 6,
1305         .vtotal = 600 + 3 + 6 + 61,
1306         .vrefresh = 60,
1307 };
1308
1309 static const struct panel_desc samsung_ltn101nt05 = {
1310         .modes = &samsung_ltn101nt05_mode,
1311         .num_modes = 1,
1312         .bpc = 6,
1313         .size = {
1314                 .width = 223,
1315                 .height = 125,
1316         },
1317 };
1318
1319 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1320         .clock = 76300,
1321         .hdisplay = 1366,
1322         .hsync_start = 1366 + 64,
1323         .hsync_end = 1366 + 64 + 48,
1324         .htotal = 1366 + 64 + 48 + 128,
1325         .vdisplay = 768,
1326         .vsync_start = 768 + 2,
1327         .vsync_end = 768 + 2 + 5,
1328         .vtotal = 768 + 2 + 5 + 17,
1329         .vrefresh = 60,
1330 };
1331
1332 static const struct panel_desc samsung_ltn140at29_301 = {
1333         .modes = &samsung_ltn140at29_301_mode,
1334         .num_modes = 1,
1335         .bpc = 6,
1336         .size = {
1337                 .width = 320,
1338                 .height = 187,
1339         },
1340 };
1341
1342 static const struct display_timing sharp_lq101k1ly04_timing = {
1343         .pixelclock = { 60000000, 65000000, 80000000 },
1344         .hactive = { 1280, 1280, 1280 },
1345         .hfront_porch = { 20, 20, 20 },
1346         .hback_porch = { 20, 20, 20 },
1347         .hsync_len = { 10, 10, 10 },
1348         .vactive = { 800, 800, 800 },
1349         .vfront_porch = { 4, 4, 4 },
1350         .vback_porch = { 4, 4, 4 },
1351         .vsync_len = { 4, 4, 4 },
1352         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1353 };
1354
1355 static const struct panel_desc sharp_lq101k1ly04 = {
1356         .timings = &sharp_lq101k1ly04_timing,
1357         .num_timings = 1,
1358         .bpc = 8,
1359         .size = {
1360                 .width = 217,
1361                 .height = 136,
1362         },
1363         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1364 };
1365
1366 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1367         .clock = 252750,
1368         .hdisplay = 2400,
1369         .hsync_start = 2400 + 48,
1370         .hsync_end = 2400 + 48 + 32,
1371         .htotal = 2400 + 48 + 32 + 80,
1372         .vdisplay = 1600,
1373         .vsync_start = 1600 + 3,
1374         .vsync_end = 1600 + 3 + 10,
1375         .vtotal = 1600 + 3 + 10 + 33,
1376         .vrefresh = 60,
1377         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1378 };
1379
1380 static const struct panel_desc sharp_lq123p1jx31 = {
1381         .modes = &sharp_lq123p1jx31_mode,
1382         .num_modes = 1,
1383         .size = {
1384                 .width = 259,
1385                 .height = 173,
1386         },
1387         .delay = {
1388                 .prepare = 110,
1389                 .enable = 50,
1390                 .unprepare = 550,
1391         },
1392 };
1393
1394 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1395         .clock = 33300,
1396         .hdisplay = 800,
1397         .hsync_start = 800 + 1,
1398         .hsync_end = 800 + 1 + 64,
1399         .htotal = 800 + 1 + 64 + 64,
1400         .vdisplay = 480,
1401         .vsync_start = 480 + 1,
1402         .vsync_end = 480 + 1 + 23,
1403         .vtotal = 480 + 1 + 23 + 22,
1404         .vrefresh = 60,
1405 };
1406
1407 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1408         .modes = &shelly_sca07010_bfn_lnn_mode,
1409         .num_modes = 1,
1410         .size = {
1411                 .width = 152,
1412                 .height = 91,
1413         },
1414         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1415 };
1416
1417 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1418         .clock = 147000,
1419         .hdisplay = 1920,
1420         .hsync_start = 1920 + 16,
1421         .hsync_end = 1920 + 16 + 16,
1422         .htotal = 1920 + 16 + 16 + 32,
1423         .vdisplay = 1200,
1424         .vsync_start = 1200 + 15,
1425         .vsync_end = 1200 + 15 + 2,
1426         .vtotal = 1200 + 15 + 2 + 18,
1427         .vrefresh = 60,
1428         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1429 };
1430
1431 static const struct panel_desc starry_kr122ea0sra = {
1432         .modes = &starry_kr122ea0sra_mode,
1433         .num_modes = 1,
1434         .size = {
1435                 .width = 263,
1436                 .height = 164,
1437         },
1438 };
1439
1440 static const struct drm_display_mode tpk_f07a_0102_mode = {
1441         .clock = 33260,
1442         .hdisplay = 800,
1443         .hsync_start = 800 + 40,
1444         .hsync_end = 800 + 40 + 128,
1445         .htotal = 800 + 40 + 128 + 88,
1446         .vdisplay = 480,
1447         .vsync_start = 480 + 10,
1448         .vsync_end = 480 + 10 + 2,
1449         .vtotal = 480 + 10 + 2 + 33,
1450         .vrefresh = 60,
1451 };
1452
1453 static const struct panel_desc tpk_f07a_0102 = {
1454         .modes = &tpk_f07a_0102_mode,
1455         .num_modes = 1,
1456         .size = {
1457                 .width = 152,
1458                 .height = 91,
1459         },
1460         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1461 };
1462
1463 static const struct drm_display_mode tpk_f10a_0102_mode = {
1464         .clock = 45000,
1465         .hdisplay = 1024,
1466         .hsync_start = 1024 + 176,
1467         .hsync_end = 1024 + 176 + 5,
1468         .htotal = 1024 + 176 + 5 + 88,
1469         .vdisplay = 600,
1470         .vsync_start = 600 + 20,
1471         .vsync_end = 600 + 20 + 5,
1472         .vtotal = 600 + 20 + 5 + 25,
1473         .vrefresh = 60,
1474 };
1475
1476 static const struct panel_desc tpk_f10a_0102 = {
1477         .modes = &tpk_f10a_0102_mode,
1478         .num_modes = 1,
1479         .size = {
1480                 .width = 223,
1481                 .height = 125,
1482         },
1483 };
1484
1485 static const struct display_timing urt_umsh_8596md_timing = {
1486         .pixelclock = { 33260000, 33260000, 33260000 },
1487         .hactive = { 800, 800, 800 },
1488         .hfront_porch = { 41, 41, 41 },
1489         .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1490         .hsync_len = { 71, 128, 128 },
1491         .vactive = { 480, 480, 480 },
1492         .vfront_porch = { 10, 10, 10 },
1493         .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1494         .vsync_len = { 2, 2, 2 },
1495         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1496                 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1497 };
1498
1499 static const struct panel_desc urt_umsh_8596md_lvds = {
1500         .timings = &urt_umsh_8596md_timing,
1501         .num_timings = 1,
1502         .bpc = 6,
1503         .size = {
1504                 .width = 152,
1505                 .height = 91,
1506         },
1507         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1508 };
1509
1510 static const struct panel_desc urt_umsh_8596md_parallel = {
1511         .timings = &urt_umsh_8596md_timing,
1512         .num_timings = 1,
1513         .bpc = 6,
1514         .size = {
1515                 .width = 152,
1516                 .height = 91,
1517         },
1518         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1519 };
1520
1521 static const struct of_device_id platform_of_match[] = {
1522         {
1523                 .compatible = "ampire,am800480r3tmqwa1h",
1524                 .data = &ampire_am800480r3tmqwa1h,
1525         }, {
1526                 .compatible = "auo,b101aw03",
1527                 .data = &auo_b101aw03,
1528         }, {
1529                 .compatible = "auo,b101ean01",
1530                 .data = &auo_b101ean01,
1531         }, {
1532                 .compatible = "auo,b101xtn01",
1533                 .data = &auo_b101xtn01,
1534         }, {
1535                 .compatible = "auo,b116xw03",
1536                 .data = &auo_b116xw03,
1537         }, {
1538                 .compatible = "auo,b133htn01",
1539                 .data = &auo_b133htn01,
1540         }, {
1541                 .compatible = "auo,b133xtn01",
1542                 .data = &auo_b133xtn01,
1543         }, {
1544                 .compatible = "avic,tm070ddh03",
1545                 .data = &avic_tm070ddh03,
1546         }, {
1547                 .compatible = "chunghwa,claa101wa01a",
1548                 .data = &chunghwa_claa101wa01a
1549         }, {
1550                 .compatible = "chunghwa,claa101wb01",
1551                 .data = &chunghwa_claa101wb01
1552         }, {
1553                 .compatible = "edt,et057090dhu",
1554                 .data = &edt_et057090dhu,
1555         }, {
1556                 .compatible = "edt,et070080dh6",
1557                 .data = &edt_etm0700g0dh6,
1558         }, {
1559                 .compatible = "edt,etm0700g0dh6",
1560                 .data = &edt_etm0700g0dh6,
1561         }, {
1562                 .compatible = "foxlink,fl500wvr00-a0t",
1563                 .data = &foxlink_fl500wvr00_a0t,
1564         }, {
1565                 .compatible = "giantplus,gpg482739qs5",
1566                 .data = &giantplus_gpg482739qs5
1567         }, {
1568                 .compatible = "hannstar,hsd070pww1",
1569                 .data = &hannstar_hsd070pww1,
1570         }, {
1571                 .compatible = "hannstar,hsd100pxn1",
1572                 .data = &hannstar_hsd100pxn1,
1573         }, {
1574                 .compatible = "hit,tx23d38vm0caa",
1575                 .data = &hitachi_tx23d38vm0caa
1576         }, {
1577                 .compatible = "innolux,at043tn24",
1578                 .data = &innolux_at043tn24,
1579         }, {
1580                 .compatible = "innolux,at070tn92",
1581                 .data = &innolux_at070tn92,
1582         }, {
1583                 .compatible ="innolux,g121i1-l01",
1584                 .data = &innolux_g121i1_l01
1585         }, {
1586                 .compatible = "innolux,g121x1-l03",
1587                 .data = &innolux_g121x1_l03,
1588         }, {
1589                 .compatible = "innolux,n116bge",
1590                 .data = &innolux_n116bge,
1591         }, {
1592                 .compatible = "innolux,n156bge-l21",
1593                 .data = &innolux_n156bge_l21,
1594         }, {
1595                 .compatible = "innolux,zj070na-01p",
1596                 .data = &innolux_zj070na_01p,
1597         }, {
1598                 .compatible = "kyo,tcg121xglp",
1599                 .data = &kyo_tcg121xglp,
1600         }, {
1601                 .compatible = "lg,lb070wv8",
1602                 .data = &lg_lb070wv8,
1603         }, {
1604                 .compatible = "lg,lp079qx1-sp0v",
1605                 .data = &lg_lp079qx1_sp0v,
1606         }, {
1607                 .compatible = "lg,lp097qx1-spa1",
1608                 .data = &lg_lp097qx1_spa1,
1609         }, {
1610                 .compatible = "lg,lp120up1",
1611                 .data = &lg_lp120up1,
1612         }, {
1613                 .compatible = "lg,lp129qe",
1614                 .data = &lg_lp129qe,
1615         }, {
1616                 .compatible = "nec,nl4827hc19-05b",
1617                 .data = &nec_nl4827hc19_05b,
1618         }, {
1619                 .compatible = "okaya,rs800480t-7x0gp",
1620                 .data = &okaya_rs800480t_7x0gp,
1621         }, {
1622                 .compatible = "olimex,lcd-olinuxino-43-ts",
1623                 .data = &olimex_lcd_olinuxino_43ts,
1624         }, {
1625                 .compatible = "ontat,yx700wv03",
1626                 .data = &ontat_yx700wv03,
1627         }, {
1628                 .compatible = "ortustech,com43h4m85ulc",
1629                 .data = &ortustech_com43h4m85ulc,
1630         }, {
1631                 .compatible = "qiaodian,qd43003c0-40",
1632                 .data = &qd43003c0_40,
1633         }, {
1634                 .compatible = "samsung,lsn122dl01-c01",
1635                 .data = &samsung_lsn122dl01_c01,
1636         }, {
1637                 .compatible = "samsung,ltn101nt05",
1638                 .data = &samsung_ltn101nt05,
1639         }, {
1640                 .compatible = "samsung,ltn140at29-301",
1641                 .data = &samsung_ltn140at29_301,
1642         }, {
1643                 .compatible = "sharp,lq101k1ly04",
1644                 .data = &sharp_lq101k1ly04,
1645         }, {
1646                 .compatible = "sharp,lq123p1jx31",
1647                 .data = &sharp_lq123p1jx31,
1648         }, {
1649                 .compatible = "shelly,sca07010-bfn-lnn",
1650                 .data = &shelly_sca07010_bfn_lnn,
1651         }, {
1652                 .compatible = "starry,kr122ea0sra",
1653                 .data = &starry_kr122ea0sra,
1654         }, {
1655                 .compatible = "tpk,f07a-0102",
1656                 .data = &tpk_f07a_0102,
1657         }, {
1658                 .compatible = "tpk,f10a-0102",
1659                 .data = &tpk_f10a_0102,
1660         }, {
1661                 .compatible = "urt,umsh-8596md-t",
1662                 .data = &urt_umsh_8596md_parallel,
1663         }, {
1664                 .compatible = "urt,umsh-8596md-1t",
1665                 .data = &urt_umsh_8596md_parallel,
1666         }, {
1667                 .compatible = "urt,umsh-8596md-7t",
1668                 .data = &urt_umsh_8596md_parallel,
1669         }, {
1670                 .compatible = "urt,umsh-8596md-11t",
1671                 .data = &urt_umsh_8596md_lvds,
1672         }, {
1673                 .compatible = "urt,umsh-8596md-19t",
1674                 .data = &urt_umsh_8596md_lvds,
1675         }, {
1676                 .compatible = "urt,umsh-8596md-20t",
1677                 .data = &urt_umsh_8596md_parallel,
1678         }, {
1679                 /* sentinel */
1680         }
1681 };
1682 MODULE_DEVICE_TABLE(of, platform_of_match);
1683
1684 static int panel_simple_platform_probe(struct platform_device *pdev)
1685 {
1686         const struct of_device_id *id;
1687
1688         id = of_match_node(platform_of_match, pdev->dev.of_node);
1689         if (!id)
1690                 return -ENODEV;
1691
1692         return panel_simple_probe(&pdev->dev, id->data);
1693 }
1694
1695 static int panel_simple_platform_remove(struct platform_device *pdev)
1696 {
1697         return panel_simple_remove(&pdev->dev);
1698 }
1699
1700 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1701 {
1702         panel_simple_shutdown(&pdev->dev);
1703 }
1704
1705 static struct platform_driver panel_simple_platform_driver = {
1706         .driver = {
1707                 .name = "panel-simple",
1708                 .of_match_table = platform_of_match,
1709         },
1710         .probe = panel_simple_platform_probe,
1711         .remove = panel_simple_platform_remove,
1712         .shutdown = panel_simple_platform_shutdown,
1713 };
1714
1715 struct panel_desc_dsi {
1716         struct panel_desc desc;
1717
1718         unsigned long flags;
1719         enum mipi_dsi_pixel_format format;
1720         unsigned int lanes;
1721 };
1722
1723 static const struct drm_display_mode auo_b080uan01_mode = {
1724         .clock = 154500,
1725         .hdisplay = 1200,
1726         .hsync_start = 1200 + 62,
1727         .hsync_end = 1200 + 62 + 4,
1728         .htotal = 1200 + 62 + 4 + 62,
1729         .vdisplay = 1920,
1730         .vsync_start = 1920 + 9,
1731         .vsync_end = 1920 + 9 + 2,
1732         .vtotal = 1920 + 9 + 2 + 8,
1733         .vrefresh = 60,
1734 };
1735
1736 static const struct panel_desc_dsi auo_b080uan01 = {
1737         .desc = {
1738                 .modes = &auo_b080uan01_mode,
1739                 .num_modes = 1,
1740                 .bpc = 8,
1741                 .size = {
1742                         .width = 108,
1743                         .height = 272,
1744                 },
1745         },
1746         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1747         .format = MIPI_DSI_FMT_RGB888,
1748         .lanes = 4,
1749 };
1750
1751 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1752         .clock = 160000,
1753         .hdisplay = 1200,
1754         .hsync_start = 1200 + 120,
1755         .hsync_end = 1200 + 120 + 20,
1756         .htotal = 1200 + 120 + 20 + 21,
1757         .vdisplay = 1920,
1758         .vsync_start = 1920 + 21,
1759         .vsync_end = 1920 + 21 + 3,
1760         .vtotal = 1920 + 21 + 3 + 18,
1761         .vrefresh = 60,
1762         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1763 };
1764
1765 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1766         .desc = {
1767                 .modes = &boe_tv080wum_nl0_mode,
1768                 .num_modes = 1,
1769                 .size = {
1770                         .width = 107,
1771                         .height = 172,
1772                 },
1773         },
1774         .flags = MIPI_DSI_MODE_VIDEO |
1775                  MIPI_DSI_MODE_VIDEO_BURST |
1776                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1777         .format = MIPI_DSI_FMT_RGB888,
1778         .lanes = 4,
1779 };
1780
1781 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1782         .clock = 71000,
1783         .hdisplay = 800,
1784         .hsync_start = 800 + 32,
1785         .hsync_end = 800 + 32 + 1,
1786         .htotal = 800 + 32 + 1 + 57,
1787         .vdisplay = 1280,
1788         .vsync_start = 1280 + 28,
1789         .vsync_end = 1280 + 28 + 1,
1790         .vtotal = 1280 + 28 + 1 + 14,
1791         .vrefresh = 60,
1792 };
1793
1794 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1795         .desc = {
1796                 .modes = &lg_ld070wx3_sl01_mode,
1797                 .num_modes = 1,
1798                 .bpc = 8,
1799                 .size = {
1800                         .width = 94,
1801                         .height = 151,
1802                 },
1803         },
1804         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1805         .format = MIPI_DSI_FMT_RGB888,
1806         .lanes = 4,
1807 };
1808
1809 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1810         .clock = 67000,
1811         .hdisplay = 720,
1812         .hsync_start = 720 + 12,
1813         .hsync_end = 720 + 12 + 4,
1814         .htotal = 720 + 12 + 4 + 112,
1815         .vdisplay = 1280,
1816         .vsync_start = 1280 + 8,
1817         .vsync_end = 1280 + 8 + 4,
1818         .vtotal = 1280 + 8 + 4 + 12,
1819         .vrefresh = 60,
1820 };
1821
1822 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1823         .desc = {
1824                 .modes = &lg_lh500wx1_sd03_mode,
1825                 .num_modes = 1,
1826                 .bpc = 8,
1827                 .size = {
1828                         .width = 62,
1829                         .height = 110,
1830                 },
1831         },
1832         .flags = MIPI_DSI_MODE_VIDEO,
1833         .format = MIPI_DSI_FMT_RGB888,
1834         .lanes = 4,
1835 };
1836
1837 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1838         .clock = 157200,
1839         .hdisplay = 1920,
1840         .hsync_start = 1920 + 154,
1841         .hsync_end = 1920 + 154 + 16,
1842         .htotal = 1920 + 154 + 16 + 32,
1843         .vdisplay = 1200,
1844         .vsync_start = 1200 + 17,
1845         .vsync_end = 1200 + 17 + 2,
1846         .vtotal = 1200 + 17 + 2 + 16,
1847         .vrefresh = 60,
1848 };
1849
1850 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1851         .desc = {
1852                 .modes = &panasonic_vvx10f004b00_mode,
1853                 .num_modes = 1,
1854                 .bpc = 8,
1855                 .size = {
1856                         .width = 217,
1857                         .height = 136,
1858                 },
1859         },
1860         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1861                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1862         .format = MIPI_DSI_FMT_RGB888,
1863         .lanes = 4,
1864 };
1865
1866 static const struct of_device_id dsi_of_match[] = {
1867         {
1868                 .compatible = "auo,b080uan01",
1869                 .data = &auo_b080uan01
1870         }, {
1871                 .compatible = "boe,tv080wum-nl0",
1872                 .data = &boe_tv080wum_nl0
1873         }, {
1874                 .compatible = "lg,ld070wx3-sl01",
1875                 .data = &lg_ld070wx3_sl01
1876         }, {
1877                 .compatible = "lg,lh500wx1-sd03",
1878                 .data = &lg_lh500wx1_sd03
1879         }, {
1880                 .compatible = "panasonic,vvx10f004b00",
1881                 .data = &panasonic_vvx10f004b00
1882         }, {
1883                 /* sentinel */
1884         }
1885 };
1886 MODULE_DEVICE_TABLE(of, dsi_of_match);
1887
1888 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1889 {
1890         const struct panel_desc_dsi *desc;
1891         const struct of_device_id *id;
1892         int err;
1893
1894         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1895         if (!id)
1896                 return -ENODEV;
1897
1898         desc = id->data;
1899
1900         err = panel_simple_probe(&dsi->dev, &desc->desc);
1901         if (err < 0)
1902                 return err;
1903
1904         dsi->mode_flags = desc->flags;
1905         dsi->format = desc->format;
1906         dsi->lanes = desc->lanes;
1907
1908         return mipi_dsi_attach(dsi);
1909 }
1910
1911 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1912 {
1913         int err;
1914
1915         err = mipi_dsi_detach(dsi);
1916         if (err < 0)
1917                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1918
1919         return panel_simple_remove(&dsi->dev);
1920 }
1921
1922 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1923 {
1924         panel_simple_shutdown(&dsi->dev);
1925 }
1926
1927 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1928         .driver = {
1929                 .name = "panel-simple-dsi",
1930                 .of_match_table = dsi_of_match,
1931         },
1932         .probe = panel_simple_dsi_probe,
1933         .remove = panel_simple_dsi_remove,
1934         .shutdown = panel_simple_dsi_shutdown,
1935 };
1936
1937 static int __init panel_simple_init(void)
1938 {
1939         int err;
1940
1941         err = platform_driver_register(&panel_simple_platform_driver);
1942         if (err < 0)
1943                 return err;
1944
1945         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1946                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1947                 if (err < 0)
1948                         return err;
1949         }
1950
1951         return 0;
1952 }
1953 module_init(panel_simple_init);
1954
1955 static void __exit panel_simple_exit(void)
1956 {
1957         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1958                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1959
1960         platform_driver_unregister(&panel_simple_platform_driver);
1961 }
1962 module_exit(panel_simple_exit);
1963
1964 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1965 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1966 MODULE_LICENSE("GPL and additional rights");