drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/videomode.h>
  38
  39 struct panel_desc {
  40         const struct drm_display_mode *modes;
  41         unsigned int num_modes;
  42         const struct display_timing *timings;
  43         unsigned int num_timings;
  44
  45         unsigned int bpc;
  46
  47         /**
  48          * @width: width (in millimeters) of the panel's active display area
  49          * @height: height (in millimeters) of the panel's active display area
  50          */
  51         struct {
  52                 unsigned int width;
  53                 unsigned int height;
  54         } size;
  55
  56         /**
  57          * @prepare: the time (in milliseconds) that it takes for the panel to
  58          *           become ready and start receiving video data
  59          * @enable: the time (in milliseconds) that it takes for the panel to
  60          *          display the first valid frame after starting to receive
  61          *          video data
  62          * @disable: the time (in milliseconds) that it takes for the panel to
  63          *           turn the display off (no content is visible)
  64          * @unprepare: the time (in milliseconds) that it takes for the panel
  65          *             to power itself down completely
  66          */
  67         struct {
  68                 unsigned int prepare;
  69                 unsigned int enable;
  70                 unsigned int disable;
  71                 unsigned int unprepare;
  72         } delay;
  73
  74         u32 bus_format;
  75 };
  76
  77 struct panel_simple {
  78         struct drm_panel base;
  79         bool prepared;
  80         bool enabled;
  81
  82         const struct panel_desc *desc;
  83
  84         struct backlight_device *backlight;
  85         struct regulator *supply;
  86         struct i2c_adapter *ddc;
  87
  88         struct gpio_desc *enable_gpio;
  89 };
  90
  91 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
  92 {
  93         return container_of(panel, struct panel_simple, base);
  94 }
  95
  96 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
  97 {
  98         struct drm_connector *connector = panel->base.connector;
  99         struct drm_device *drm = panel->base.drm;
 100         struct drm_display_mode *mode;
 101         unsigned int i, num = 0;
 102
 103         if (!panel->desc)
 104                 return 0;
 105
 106         for (i = 0; i < panel->desc->num_timings; i++) {
 107                 const struct display_timing *dt = &panel->desc->timings[i];
 108                 struct videomode vm;
 109
 110                 videomode_from_timing(dt, &vm);
 111                 mode = drm_mode_create(drm);
 112                 if (!mode) {
 113                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 114                                 dt->hactive.typ, dt->vactive.typ);
 115                         continue;
 116                 }
 117
 118                 drm_display_mode_from_videomode(&vm, mode);
 119                 drm_mode_set_name(mode);
 120
 121                 drm_mode_probed_add(connector, mode);
 122                 num++;
 123         }
 124
 125         for (i = 0; i < panel->desc->num_modes; i++) {
 126                 const struct drm_display_mode *m = &panel->desc->modes[i];
 127
 128                 mode = drm_mode_duplicate(drm, m);
 129                 if (!mode) {
 130                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 131                                 m->hdisplay, m->vdisplay, m->vrefresh);
 132                         continue;
 133                 }
 134
 135                 drm_mode_set_name(mode);
 136
 137                 drm_mode_probed_add(connector, mode);
 138                 num++;
 139         }
 140
 141         connector->display_info.bpc = panel->desc->bpc;
 142         connector->display_info.width_mm = panel->desc->size.width;
 143         connector->display_info.height_mm = panel->desc->size.height;
 144         if (panel->desc->bus_format)
 145                 drm_display_info_set_bus_formats(&connector->display_info,
 146                                                  &panel->desc->bus_format, 1);
 147
 148         return num;
 149 }
 150
 151 static int panel_simple_disable(struct drm_panel *panel)
 152 {
 153         struct panel_simple *p = to_panel_simple(panel);
 154
 155         if (!p->enabled)
 156                 return 0;
 157
 158         if (p->backlight) {
 159                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 160                 backlight_update_status(p->backlight);
 161         }
 162
 163         if (p->desc->delay.disable)
 164                 msleep(p->desc->delay.disable);
 165
 166         p->enabled = false;
 167
 168         return 0;
 169 }
 170
 171 static int panel_simple_unprepare(struct drm_panel *panel)
 172 {
 173         struct panel_simple *p = to_panel_simple(panel);
 174
 175         if (!p->prepared)
 176                 return 0;
 177
 178         if (p->enable_gpio)
 179                 gpiod_set_value_cansleep(p->enable_gpio, 0);
 180
 181         regulator_disable(p->supply);
 182
 183         if (p->desc->delay.unprepare)
 184                 msleep(p->desc->delay.unprepare);
 185
 186         p->prepared = false;
 187
 188         return 0;
 189 }
 190
 191 static int panel_simple_prepare(struct drm_panel *panel)
 192 {
 193         struct panel_simple *p = to_panel_simple(panel);
 194         int err;
 195
 196         if (p->prepared)
 197                 return 0;
 198
 199         err = regulator_enable(p->supply);
 200         if (err < 0) {
 201                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 202                 return err;
 203         }
 204
 205         if (p->enable_gpio)
 206                 gpiod_set_value_cansleep(p->enable_gpio, 1);
 207
 208         if (p->desc->delay.prepare)
 209                 msleep(p->desc->delay.prepare);
 210
 211         p->prepared = true;
 212
 213         return 0;
 214 }
 215
 216 static int panel_simple_enable(struct drm_panel *panel)
 217 {
 218         struct panel_simple *p = to_panel_simple(panel);
 219
 220         if (p->enabled)
 221                 return 0;
 222
 223         if (p->desc->delay.enable)
 224                 msleep(p->desc->delay.enable);
 225
 226         if (p->backlight) {
 227                 p->backlight->props.power = FB_BLANK_UNBLANK;
 228                 backlight_update_status(p->backlight);
 229         }
 230
 231         p->enabled = true;
 232
 233         return 0;
 234 }
 235
 236 static int panel_simple_get_modes(struct drm_panel *panel)
 237 {
 238         struct panel_simple *p = to_panel_simple(panel);
 239         int num = 0;
 240
 241         /* probe EDID if a DDC bus is available */
 242         if (p->ddc) {
 243                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 244                 drm_mode_connector_update_edid_property(panel->connector, edid);
 245                 if (edid) {
 246                         num += drm_add_edid_modes(panel->connector, edid);
 247                         kfree(edid);
 248                 }
 249         }
 250
 251         /* add hard-coded panel modes */
 252         num += panel_simple_get_fixed_modes(p);
 253
 254         return num;
 255 }
 256
 257 static int panel_simple_get_timings(struct drm_panel *panel,
 258                                     unsigned int num_timings,
 259                                     struct display_timing *timings)
 260 {
 261         struct panel_simple *p = to_panel_simple(panel);
 262         unsigned int i;
 263
 264         if (p->desc->num_timings < num_timings)
 265                 num_timings = p->desc->num_timings;
 266
 267         if (timings)
 268                 for (i = 0; i < num_timings; i++)
 269                         timings[i] = p->desc->timings[i];
 270
 271         return p->desc->num_timings;
 272 }
 273
 274 static const struct drm_panel_funcs panel_simple_funcs = {
 275         .disable = panel_simple_disable,
 276         .unprepare = panel_simple_unprepare,
 277         .prepare = panel_simple_prepare,
 278         .enable = panel_simple_enable,
 279         .get_modes = panel_simple_get_modes,
 280         .get_timings = panel_simple_get_timings,
 281 };
 282
 283 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 284 {
 285         struct device_node *backlight, *ddc;
 286         struct panel_simple *panel;
 287         int err;
 288
 289         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 290         if (!panel)
 291                 return -ENOMEM;
 292
 293         panel->enabled = false;
 294         panel->prepared = false;
 295         panel->desc = desc;
 296
 297         panel->supply = devm_regulator_get(dev, "power");
 298         if (IS_ERR(panel->supply))
 299                 return PTR_ERR(panel->supply);
 300
 301         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 302                                                      GPIOD_OUT_LOW);
 303         if (IS_ERR(panel->enable_gpio)) {
 304                 err = PTR_ERR(panel->enable_gpio);
 305                 dev_err(dev, "failed to request GPIO: %d\n", err);
 306                 return err;
 307         }
 308
 309         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 310         if (backlight) {
 311                 panel->backlight = of_find_backlight_by_node(backlight);
 312                 of_node_put(backlight);
 313
 314                 if (!panel->backlight)
 315                         return -EPROBE_DEFER;
 316         }
 317
 318         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 319         if (ddc) {
 320                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 321                 of_node_put(ddc);
 322
 323                 if (!panel->ddc) {
 324                         err = -EPROBE_DEFER;
 325                         goto free_backlight;
 326                 }
 327         }
 328
 329         drm_panel_init(&panel->base);
 330         panel->base.dev = dev;
 331         panel->base.funcs = &panel_simple_funcs;
 332
 333         err = drm_panel_add(&panel->base);
 334         if (err < 0)
 335                 goto free_ddc;
 336
 337         dev_set_drvdata(dev, panel);
 338
 339         return 0;
 340
 341 free_ddc:
 342         if (panel->ddc)
 343                 put_device(&panel->ddc->dev);
 344 free_backlight:
 345         if (panel->backlight)
 346                 put_device(&panel->backlight->dev);
 347
 348         return err;
 349 }
 350
 351 static int panel_simple_remove(struct device *dev)
 352 {
 353         struct panel_simple *panel = dev_get_drvdata(dev);
 354
 355         drm_panel_detach(&panel->base);
 356         drm_panel_remove(&panel->base);
 357
 358         panel_simple_disable(&panel->base);
 359
 360         if (panel->ddc)
 361                 put_device(&panel->ddc->dev);
 362
 363         if (panel->backlight)
 364                 put_device(&panel->backlight->dev);
 365
 366         return 0;
 367 }
 368
 369 static void panel_simple_shutdown(struct device *dev)
 370 {
 371         struct panel_simple *panel = dev_get_drvdata(dev);
 372
 373         panel_simple_disable(&panel->base);
 374 }
 375
 376 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 377         .clock = 33333,
 378         .hdisplay = 800,
 379         .hsync_start = 800 + 0,
 380         .hsync_end = 800 + 0 + 255,
 381         .htotal = 800 + 0 + 255 + 0,
 382         .vdisplay = 480,
 383         .vsync_start = 480 + 2,
 384         .vsync_end = 480 + 2 + 45,
 385         .vtotal = 480 + 2 + 45 + 0,
 386         .vrefresh = 60,
 387         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 388 };
 389
 390 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 391         .modes = &ampire_am800480r3tmqwa1h_mode,
 392         .num_modes = 1,
 393         .bpc = 6,
 394         .size = {
 395                 .width = 152,
 396                 .height = 91,
 397         },
 398         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 399 };
 400
 401 static const struct drm_display_mode auo_b101aw03_mode = {
 402         .clock = 51450,
 403         .hdisplay = 1024,
 404         .hsync_start = 1024 + 156,
 405         .hsync_end = 1024 + 156 + 8,
 406         .htotal = 1024 + 156 + 8 + 156,
 407         .vdisplay = 600,
 408         .vsync_start = 600 + 16,
 409         .vsync_end = 600 + 16 + 6,
 410         .vtotal = 600 + 16 + 6 + 16,
 411         .vrefresh = 60,
 412 };
 413
 414 static const struct panel_desc auo_b101aw03 = {
 415         .modes = &auo_b101aw03_mode,
 416         .num_modes = 1,
 417         .bpc = 6,
 418         .size = {
 419                 .width = 223,
 420                 .height = 125,
 421         },
 422 };
 423
 424 static const struct drm_display_mode auo_b101ean01_mode = {
 425         .clock = 72500,
 426         .hdisplay = 1280,
 427         .hsync_start = 1280 + 119,
 428         .hsync_end = 1280 + 119 + 32,
 429         .htotal = 1280 + 119 + 32 + 21,
 430         .vdisplay = 800,
 431         .vsync_start = 800 + 4,
 432         .vsync_end = 800 + 4 + 20,
 433         .vtotal = 800 + 4 + 20 + 8,
 434         .vrefresh = 60,
 435 };
 436
 437 static const struct panel_desc auo_b101ean01 = {
 438         .modes = &auo_b101ean01_mode,
 439         .num_modes = 1,
 440         .bpc = 6,
 441         .size = {
 442                 .width = 217,
 443                 .height = 136,
 444         },
 445 };
 446
 447 static const struct drm_display_mode auo_b101xtn01_mode = {
 448         .clock = 72000,
 449         .hdisplay = 1366,
 450         .hsync_start = 1366 + 20,
 451         .hsync_end = 1366 + 20 + 70,
 452         .htotal = 1366 + 20 + 70,
 453         .vdisplay = 768,
 454         .vsync_start = 768 + 14,
 455         .vsync_end = 768 + 14 + 42,
 456         .vtotal = 768 + 14 + 42,
 457         .vrefresh = 60,
 458         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 459 };
 460
 461 static const struct panel_desc auo_b101xtn01 = {
 462         .modes = &auo_b101xtn01_mode,
 463         .num_modes = 1,
 464         .bpc = 6,
 465         .size = {
 466                 .width = 223,
 467                 .height = 125,
 468         },
 469 };
 470
 471 static const struct drm_display_mode auo_b116xw03_mode = {
 472         .clock = 70589,
 473         .hdisplay = 1366,
 474         .hsync_start = 1366 + 40,
 475         .hsync_end = 1366 + 40 + 40,
 476         .htotal = 1366 + 40 + 40 + 32,
 477         .vdisplay = 768,
 478         .vsync_start = 768 + 10,
 479         .vsync_end = 768 + 10 + 12,
 480         .vtotal = 768 + 10 + 12 + 6,
 481         .vrefresh = 60,
 482 };
 483
 484 static const struct panel_desc auo_b116xw03 = {
 485         .modes = &auo_b116xw03_mode,
 486         .num_modes = 1,
 487         .bpc = 6,
 488         .size = {
 489                 .width = 256,
 490                 .height = 144,
 491         },
 492 };
 493
 494 static const struct drm_display_mode auo_b133xtn01_mode = {
 495         .clock = 69500,
 496         .hdisplay = 1366,
 497         .hsync_start = 1366 + 48,
 498         .hsync_end = 1366 + 48 + 32,
 499         .htotal = 1366 + 48 + 32 + 20,
 500         .vdisplay = 768,
 501         .vsync_start = 768 + 3,
 502         .vsync_end = 768 + 3 + 6,
 503         .vtotal = 768 + 3 + 6 + 13,
 504         .vrefresh = 60,
 505 };
 506
 507 static const struct panel_desc auo_b133xtn01 = {
 508         .modes = &auo_b133xtn01_mode,
 509         .num_modes = 1,
 510         .bpc = 6,
 511         .size = {
 512                 .width = 293,
 513                 .height = 165,
 514         },
 515 };
 516
 517 static const struct drm_display_mode auo_b133htn01_mode = {
 518         .clock = 150660,
 519         .hdisplay = 1920,
 520         .hsync_start = 1920 + 172,
 521         .hsync_end = 1920 + 172 + 80,
 522         .htotal = 1920 + 172 + 80 + 60,
 523         .vdisplay = 1080,
 524         .vsync_start = 1080 + 25,
 525         .vsync_end = 1080 + 25 + 10,
 526         .vtotal = 1080 + 25 + 10 + 10,
 527         .vrefresh = 60,
 528 };
 529
 530 static const struct panel_desc auo_b133htn01 = {
 531         .modes = &auo_b133htn01_mode,
 532         .num_modes = 1,
 533         .bpc = 6,
 534         .size = {
 535                 .width = 293,
 536                 .height = 165,
 537         },
 538         .delay = {
 539                 .prepare = 105,
 540                 .enable = 20,
 541                 .unprepare = 50,
 542         },
 543 };
 544
 545 static const struct drm_display_mode avic_tm070ddh03_mode = {
 546         .clock = 51200,
 547         .hdisplay = 1024,
 548         .hsync_start = 1024 + 160,
 549         .hsync_end = 1024 + 160 + 4,
 550         .htotal = 1024 + 160 + 4 + 156,
 551         .vdisplay = 600,
 552         .vsync_start = 600 + 17,
 553         .vsync_end = 600 + 17 + 1,
 554         .vtotal = 600 + 17 + 1 + 17,
 555         .vrefresh = 60,
 556 };
 557
 558 static const struct panel_desc avic_tm070ddh03 = {
 559         .modes = &avic_tm070ddh03_mode,
 560         .num_modes = 1,
 561         .bpc = 8,
 562         .size = {
 563                 .width = 154,
 564                 .height = 90,
 565         },
 566         .delay = {
 567                 .prepare = 20,
 568                 .enable = 200,
 569                 .disable = 200,
 570         },
 571 };
 572
 573 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 574         .clock = 72070,
 575         .hdisplay = 1366,
 576         .hsync_start = 1366 + 58,
 577         .hsync_end = 1366 + 58 + 58,
 578         .htotal = 1366 + 58 + 58 + 58,
 579         .vdisplay = 768,
 580         .vsync_start = 768 + 4,
 581         .vsync_end = 768 + 4 + 4,
 582         .vtotal = 768 + 4 + 4 + 4,
 583         .vrefresh = 60,
 584 };
 585
 586 static const struct panel_desc chunghwa_claa101wa01a = {
 587         .modes = &chunghwa_claa101wa01a_mode,
 588         .num_modes = 1,
 589         .bpc = 6,
 590         .size = {
 591                 .width = 220,
 592                 .height = 120,
 593         },
 594 };
 595
 596 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 597         .clock = 69300,
 598         .hdisplay = 1366,
 599         .hsync_start = 1366 + 48,
 600         .hsync_end = 1366 + 48 + 32,
 601         .htotal = 1366 + 48 + 32 + 20,
 602         .vdisplay = 768,
 603         .vsync_start = 768 + 16,
 604         .vsync_end = 768 + 16 + 8,
 605         .vtotal = 768 + 16 + 8 + 16,
 606         .vrefresh = 60,
 607 };
 608
 609 static const struct panel_desc chunghwa_claa101wb01 = {
 610         .modes = &chunghwa_claa101wb01_mode,
 611         .num_modes = 1,
 612         .bpc = 6,
 613         .size = {
 614                 .width = 223,
 615                 .height = 125,
 616         },
 617 };
 618
 619 static const struct drm_display_mode edt_et057090dhu_mode = {
 620         .clock = 25175,
 621         .hdisplay = 640,
 622         .hsync_start = 640 + 16,
 623         .hsync_end = 640 + 16 + 30,
 624         .htotal = 640 + 16 + 30 + 114,
 625         .vdisplay = 480,
 626         .vsync_start = 480 + 10,
 627         .vsync_end = 480 + 10 + 3,
 628         .vtotal = 480 + 10 + 3 + 32,
 629         .vrefresh = 60,
 630         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 631 };
 632
 633 static const struct panel_desc edt_et057090dhu = {
 634         .modes = &edt_et057090dhu_mode,
 635         .num_modes = 1,
 636         .bpc = 6,
 637         .size = {
 638                 .width = 115,
 639                 .height = 86,
 640         },
 641 };
 642
 643 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
 644         .clock = 33260,
 645         .hdisplay = 800,
 646         .hsync_start = 800 + 40,
 647         .hsync_end = 800 + 40 + 128,
 648         .htotal = 800 + 40 + 128 + 88,
 649         .vdisplay = 480,
 650         .vsync_start = 480 + 10,
 651         .vsync_end = 480 + 10 + 2,
 652         .vtotal = 480 + 10 + 2 + 33,
 653         .vrefresh = 60,
 654         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 655 };
 656
 657 static const struct panel_desc edt_etm0700g0dh6 = {
 658         .modes = &edt_etm0700g0dh6_mode,
 659         .num_modes = 1,
 660         .bpc = 6,
 661         .size = {
 662                 .width = 152,
 663                 .height = 91,
 664         },
 665 };
 666
 667 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
 668         .clock = 32260,
 669         .hdisplay = 800,
 670         .hsync_start = 800 + 168,
 671         .hsync_end = 800 + 168 + 64,
 672         .htotal = 800 + 168 + 64 + 88,
 673         .vdisplay = 480,
 674         .vsync_start = 480 + 37,
 675         .vsync_end = 480 + 37 + 2,
 676         .vtotal = 480 + 37 + 2 + 8,
 677         .vrefresh = 60,
 678 };
 679
 680 static const struct panel_desc foxlink_fl500wvr00_a0t = {
 681         .modes = &foxlink_fl500wvr00_a0t_mode,
 682         .num_modes = 1,
 683         .bpc = 8,
 684         .size = {
 685                 .width = 108,
 686                 .height = 65,
 687         },
 688         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 689 };
 690
 691 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
 692         .clock = 9000,
 693         .hdisplay = 480,
 694         .hsync_start = 480 + 5,
 695         .hsync_end = 480 + 5 + 1,
 696         .htotal = 480 + 5 + 1 + 40,
 697         .vdisplay = 272,
 698         .vsync_start = 272 + 8,
 699         .vsync_end = 272 + 8 + 1,
 700         .vtotal = 272 + 8 + 1 + 8,
 701         .vrefresh = 60,
 702 };
 703
 704 static const struct panel_desc giantplus_gpg482739qs5 = {
 705         .modes = &giantplus_gpg482739qs5_mode,
 706         .num_modes = 1,
 707         .bpc = 8,
 708         .size = {
 709                 .width = 95,
 710                 .height = 54,
 711         },
 712         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 713 };
 714
 715 static const struct display_timing hannstar_hsd070pww1_timing = {
 716         .pixelclock = { 64300000, 71100000, 82000000 },
 717         .hactive = { 1280, 1280, 1280 },
 718         .hfront_porch = { 1, 1, 10 },
 719         .hback_porch = { 1, 1, 10 },
 720         /*
 721          * According to the data sheet, the minimum horizontal blanking interval
 722          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
 723          * minimum working horizontal blanking interval to be 60 clocks.
 724          */
 725         .hsync_len = { 58, 158, 661 },
 726         .vactive = { 800, 800, 800 },
 727         .vfront_porch = { 1, 1, 10 },
 728         .vback_porch = { 1, 1, 10 },
 729         .vsync_len = { 1, 21, 203 },
 730         .flags = DISPLAY_FLAGS_DE_HIGH,
 731 };
 732
 733 static const struct panel_desc hannstar_hsd070pww1 = {
 734         .timings = &hannstar_hsd070pww1_timing,
 735         .num_timings = 1,
 736         .bpc = 6,
 737         .size = {
 738                 .width = 151,
 739                 .height = 94,
 740         },
 741         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 742 };
 743
 744 static const struct display_timing hannstar_hsd100pxn1_timing = {
 745         .pixelclock = { 55000000, 65000000, 75000000 },
 746         .hactive = { 1024, 1024, 1024 },
 747         .hfront_porch = { 40, 40, 40 },
 748         .hback_porch = { 220, 220, 220 },
 749         .hsync_len = { 20, 60, 100 },
 750         .vactive = { 768, 768, 768 },
 751         .vfront_porch = { 7, 7, 7 },
 752         .vback_porch = { 21, 21, 21 },
 753         .vsync_len = { 10, 10, 10 },
 754         .flags = DISPLAY_FLAGS_DE_HIGH,
 755 };
 756
 757 static const struct panel_desc hannstar_hsd100pxn1 = {
 758         .timings = &hannstar_hsd100pxn1_timing,
 759         .num_timings = 1,
 760         .bpc = 6,
 761         .size = {
 762                 .width = 203,
 763                 .height = 152,
 764         },
 765         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
 766 };
 767
 768 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
 769         .clock = 33333,
 770         .hdisplay = 800,
 771         .hsync_start = 800 + 85,
 772         .hsync_end = 800 + 85 + 86,
 773         .htotal = 800 + 85 + 86 + 85,
 774         .vdisplay = 480,
 775         .vsync_start = 480 + 16,
 776         .vsync_end = 480 + 16 + 13,
 777         .vtotal = 480 + 16 + 13 + 16,
 778         .vrefresh = 60,
 779 };
 780
 781 static const struct panel_desc hitachi_tx23d38vm0caa = {
 782         .modes = &hitachi_tx23d38vm0caa_mode,
 783         .num_modes = 1,
 784         .bpc = 6,
 785         .size = {
 786                 .width = 195,
 787                 .height = 117,
 788         },
 789 };
 790
 791 static const struct drm_display_mode innolux_at043tn24_mode = {
 792         .clock = 9000,
 793         .hdisplay = 480,
 794         .hsync_start = 480 + 2,
 795         .hsync_end = 480 + 2 + 41,
 796         .htotal = 480 + 2 + 41 + 2,
 797         .vdisplay = 272,
 798         .vsync_start = 272 + 2,
 799         .vsync_end = 272 + 2 + 11,
 800         .vtotal = 272 + 2 + 11 + 2,
 801         .vrefresh = 60,
 802         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 803 };
 804
 805 static const struct panel_desc innolux_at043tn24 = {
 806         .modes = &innolux_at043tn24_mode,
 807         .num_modes = 1,
 808         .bpc = 8,
 809         .size = {
 810                 .width = 95,
 811                 .height = 54,
 812         },
 813         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 814 };
 815
 816 static const struct drm_display_mode innolux_g121i1_l01_mode = {
 817         .clock = 71000,
 818         .hdisplay = 1280,
 819         .hsync_start = 1280 + 64,
 820         .hsync_end = 1280 + 64 + 32,
 821         .htotal = 1280 + 64 + 32 + 64,
 822         .vdisplay = 800,
 823         .vsync_start = 800 + 9,
 824         .vsync_end = 800 + 9 + 6,
 825         .vtotal = 800 + 9 + 6 + 9,
 826         .vrefresh = 60,
 827 };
 828
 829 static const struct panel_desc innolux_g121i1_l01 = {
 830         .modes = &innolux_g121i1_l01_mode,
 831         .num_modes = 1,
 832         .bpc = 6,
 833         .size = {
 834                 .width = 261,
 835                 .height = 163,
 836         },
 837 };
 838
 839 static const struct drm_display_mode innolux_g121x1_l03_mode = {
 840         .clock = 65000,
 841         .hdisplay = 1024,
 842         .hsync_start = 1024 + 0,
 843         .hsync_end = 1024 + 1,
 844         .htotal = 1024 + 0 + 1 + 320,
 845         .vdisplay = 768,
 846         .vsync_start = 768 + 38,
 847         .vsync_end = 768 + 38 + 1,
 848         .vtotal = 768 + 38 + 1 + 0,
 849         .vrefresh = 60,
 850 };
 851
 852 static const struct panel_desc innolux_g121x1_l03 = {
 853         .modes = &innolux_g121x1_l03_mode,
 854         .num_modes = 1,
 855         .bpc = 6,
 856         .size = {
 857                 .width = 246,
 858                 .height = 185,
 859         },
 860         .delay = {
 861                 .enable = 200,
 862                 .unprepare = 200,
 863                 .disable = 400,
 864         },
 865 };
 866
 867 static const struct drm_display_mode innolux_n116bge_mode = {
 868         .clock = 76420,
 869         .hdisplay = 1366,
 870         .hsync_start = 1366 + 136,
 871         .hsync_end = 1366 + 136 + 30,
 872         .htotal = 1366 + 136 + 30 + 60,
 873         .vdisplay = 768,
 874         .vsync_start = 768 + 8,
 875         .vsync_end = 768 + 8 + 12,
 876         .vtotal = 768 + 8 + 12 + 12,
 877         .vrefresh = 60,
 878         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 879 };
 880
 881 static const struct panel_desc innolux_n116bge = {
 882         .modes = &innolux_n116bge_mode,
 883         .num_modes = 1,
 884         .bpc = 6,
 885         .size = {
 886                 .width = 256,
 887                 .height = 144,
 888         },
 889 };
 890
 891 static const struct drm_display_mode innolux_n156bge_l21_mode = {
 892         .clock = 69300,
 893         .hdisplay = 1366,
 894         .hsync_start = 1366 + 16,
 895         .hsync_end = 1366 + 16 + 34,
 896         .htotal = 1366 + 16 + 34 + 50,
 897         .vdisplay = 768,
 898         .vsync_start = 768 + 2,
 899         .vsync_end = 768 + 2 + 6,
 900         .vtotal = 768 + 2 + 6 + 12,
 901         .vrefresh = 60,
 902 };
 903
 904 static const struct panel_desc innolux_n156bge_l21 = {
 905         .modes = &innolux_n156bge_l21_mode,
 906         .num_modes = 1,
 907         .bpc = 6,
 908         .size = {
 909                 .width = 344,
 910                 .height = 193,
 911         },
 912 };
 913
 914 static const struct drm_display_mode innolux_zj070na_01p_mode = {
 915         .clock = 51501,
 916         .hdisplay = 1024,
 917         .hsync_start = 1024 + 128,
 918         .hsync_end = 1024 + 128 + 64,
 919         .htotal = 1024 + 128 + 64 + 128,
 920         .vdisplay = 600,
 921         .vsync_start = 600 + 16,
 922         .vsync_end = 600 + 16 + 4,
 923         .vtotal = 600 + 16 + 4 + 16,
 924         .vrefresh = 60,
 925 };
 926
 927 static const struct panel_desc innolux_zj070na_01p = {
 928         .modes = &innolux_zj070na_01p_mode,
 929         .num_modes = 1,
 930         .bpc = 6,
 931         .size = {
 932                 .width = 1024,
 933                 .height = 600,
 934         },
 935 };
 936
 937 static const struct display_timing kyo_tcg121xglp_timing = {
 938         .pixelclock = { 52000000, 65000000, 71000000 },
 939         .hactive = { 1024, 1024, 1024 },
 940         .hfront_porch = { 2, 2, 2 },
 941         .hback_porch = { 2, 2, 2 },
 942         .hsync_len = { 86, 124, 244 },
 943         .vactive = { 768, 768, 768 },
 944         .vfront_porch = { 2, 2, 2 },
 945         .vback_porch = { 2, 2, 2 },
 946         .vsync_len = { 6, 34, 73 },
 947         .flags = DISPLAY_FLAGS_DE_HIGH,
 948 };
 949
 950 static const struct panel_desc kyo_tcg121xglp = {
 951         .timings = &kyo_tcg121xglp_timing,
 952         .num_timings = 1,
 953         .bpc = 8,
 954         .size = {
 955                 .width = 246,
 956                 .height = 184,
 957         },
 958         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 959 };
 960
 961 static const struct drm_display_mode lg_lb070wv8_mode = {
 962         .clock = 33246,
 963         .hdisplay = 800,
 964         .hsync_start = 800 + 88,
 965         .hsync_end = 800 + 88 + 80,
 966         .htotal = 800 + 88 + 80 + 88,
 967         .vdisplay = 480,
 968         .vsync_start = 480 + 10,
 969         .vsync_end = 480 + 10 + 25,
 970         .vtotal = 480 + 10 + 25 + 10,
 971         .vrefresh = 60,
 972 };
 973
 974 static const struct panel_desc lg_lb070wv8 = {
 975         .modes = &lg_lb070wv8_mode,
 976         .num_modes = 1,
 977         .bpc = 16,
 978         .size = {
 979                 .width = 151,
 980                 .height = 91,
 981         },
 982         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 983 };
 984
 985 static const struct drm_display_mode lg_lp129qe_mode = {
 986         .clock = 285250,
 987         .hdisplay = 2560,
 988         .hsync_start = 2560 + 48,
 989         .hsync_end = 2560 + 48 + 32,
 990         .htotal = 2560 + 48 + 32 + 80,
 991         .vdisplay = 1700,
 992         .vsync_start = 1700 + 3,
 993         .vsync_end = 1700 + 3 + 10,
 994         .vtotal = 1700 + 3 + 10 + 36,
 995         .vrefresh = 60,
 996 };
 997
 998 static const struct panel_desc lg_lp129qe = {
 999         .modes = &lg_lp129qe_mode,
1000         .num_modes = 1,
1001         .bpc = 8,
1002         .size = {
1003                 .width = 272,
1004                 .height = 181,
1005         },
1006 };
1007
1008 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1009         .clock = 10870,
1010         .hdisplay = 480,
1011         .hsync_start = 480 + 2,
1012         .hsync_end = 480 + 2 + 41,
1013         .htotal = 480 + 2 + 41 + 2,
1014         .vdisplay = 272,
1015         .vsync_start = 272 + 2,
1016         .vsync_end = 272 + 2 + 4,
1017         .vtotal = 272 + 2 + 4 + 2,
1018         .vrefresh = 74,
1019 };
1020
1021 static const struct panel_desc nec_nl4827hc19_05b = {
1022         .modes = &nec_nl4827hc19_05b_mode,
1023         .num_modes = 1,
1024         .bpc = 8,
1025         .size = {
1026                 .width = 95,
1027                 .height = 54,
1028         },
1029         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1030 };
1031
1032 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1033         .pixelclock = { 30000000, 30000000, 40000000 },
1034         .hactive = { 800, 800, 800 },
1035         .hfront_porch = { 40, 40, 40 },
1036         .hback_porch = { 40, 40, 40 },
1037         .hsync_len = { 1, 48, 48 },
1038         .vactive = { 480, 480, 480 },
1039         .vfront_porch = { 13, 13, 13 },
1040         .vback_porch = { 29, 29, 29 },
1041         .vsync_len = { 3, 3, 3 },
1042         .flags = DISPLAY_FLAGS_DE_HIGH,
1043 };
1044
1045 static const struct panel_desc okaya_rs800480t_7x0gp = {
1046         .timings = &okaya_rs800480t_7x0gp_timing,
1047         .num_timings = 1,
1048         .bpc = 6,
1049         .size = {
1050                 .width = 154,
1051                 .height = 87,
1052         },
1053         .delay = {
1054                 .prepare = 41,
1055                 .enable = 50,
1056                 .unprepare = 41,
1057                 .disable = 50,
1058         },
1059         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1060 };
1061
1062 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1063         .clock = 25000,
1064         .hdisplay = 480,
1065         .hsync_start = 480 + 10,
1066         .hsync_end = 480 + 10 + 10,
1067         .htotal = 480 + 10 + 10 + 15,
1068         .vdisplay = 800,
1069         .vsync_start = 800 + 3,
1070         .vsync_end = 800 + 3 + 3,
1071         .vtotal = 800 + 3 + 3 + 3,
1072         .vrefresh = 60,
1073 };
1074
1075 static const struct panel_desc ortustech_com43h4m85ulc = {
1076         .modes = &ortustech_com43h4m85ulc_mode,
1077         .num_modes = 1,
1078         .bpc = 8,
1079         .size = {
1080                 .width = 56,
1081                 .height = 93,
1082         },
1083         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1084 };
1085
1086 static const struct drm_display_mode qd43003c0_40_mode = {
1087         .clock = 9000,
1088         .hdisplay = 480,
1089         .hsync_start = 480 + 8,
1090         .hsync_end = 480 + 8 + 4,
1091         .htotal = 480 + 8 + 4 + 39,
1092         .vdisplay = 272,
1093         .vsync_start = 272 + 4,
1094         .vsync_end = 272 + 4 + 10,
1095         .vtotal = 272 + 4 + 10 + 2,
1096         .vrefresh = 60,
1097 };
1098
1099 static const struct panel_desc qd43003c0_40 = {
1100         .modes = &qd43003c0_40_mode,
1101         .num_modes = 1,
1102         .bpc = 8,
1103         .size = {
1104                 .width = 95,
1105                 .height = 53,
1106         },
1107         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1108 };
1109
1110 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1111         .clock = 54030,
1112         .hdisplay = 1024,
1113         .hsync_start = 1024 + 24,
1114         .hsync_end = 1024 + 24 + 136,
1115         .htotal = 1024 + 24 + 136 + 160,
1116         .vdisplay = 600,
1117         .vsync_start = 600 + 3,
1118         .vsync_end = 600 + 3 + 6,
1119         .vtotal = 600 + 3 + 6 + 61,
1120         .vrefresh = 60,
1121 };
1122
1123 static const struct panel_desc samsung_ltn101nt05 = {
1124         .modes = &samsung_ltn101nt05_mode,
1125         .num_modes = 1,
1126         .bpc = 6,
1127         .size = {
1128                 .width = 1024,
1129                 .height = 600,
1130         },
1131 };
1132
1133 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1134         .clock = 76300,
1135         .hdisplay = 1366,
1136         .hsync_start = 1366 + 64,
1137         .hsync_end = 1366 + 64 + 48,
1138         .htotal = 1366 + 64 + 48 + 128,
1139         .vdisplay = 768,
1140         .vsync_start = 768 + 2,
1141         .vsync_end = 768 + 2 + 5,
1142         .vtotal = 768 + 2 + 5 + 17,
1143         .vrefresh = 60,
1144 };
1145
1146 static const struct panel_desc samsung_ltn140at29_301 = {
1147         .modes = &samsung_ltn140at29_301_mode,
1148         .num_modes = 1,
1149         .bpc = 6,
1150         .size = {
1151                 .width = 320,
1152                 .height = 187,
1153         },
1154 };
1155
1156 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1157         .clock = 33300,
1158         .hdisplay = 800,
1159         .hsync_start = 800 + 1,
1160         .hsync_end = 800 + 1 + 64,
1161         .htotal = 800 + 1 + 64 + 64,
1162         .vdisplay = 480,
1163         .vsync_start = 480 + 1,
1164         .vsync_end = 480 + 1 + 23,
1165         .vtotal = 480 + 1 + 23 + 22,
1166         .vrefresh = 60,
1167 };
1168
1169 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1170         .modes = &shelly_sca07010_bfn_lnn_mode,
1171         .num_modes = 1,
1172         .size = {
1173                 .width = 152,
1174                 .height = 91,
1175         },
1176         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1177 };
1178
1179 static const struct of_device_id platform_of_match[] = {
1180         {
1181                 .compatible = "ampire,am800480r3tmqwa1h",
1182                 .data = &ampire_am800480r3tmqwa1h,
1183         }, {
1184                 .compatible = "auo,b101aw03",
1185                 .data = &auo_b101aw03,
1186         }, {
1187                 .compatible = "auo,b101ean01",
1188                 .data = &auo_b101ean01,
1189         }, {
1190                 .compatible = "auo,b101xtn01",
1191                 .data = &auo_b101xtn01,
1192         }, {
1193                 .compatible = "auo,b116xw03",
1194                 .data = &auo_b116xw03,
1195         }, {
1196                 .compatible = "auo,b133htn01",
1197                 .data = &auo_b133htn01,
1198         }, {
1199                 .compatible = "auo,b133xtn01",
1200                 .data = &auo_b133xtn01,
1201         }, {
1202                 .compatible = "avic,tm070ddh03",
1203                 .data = &avic_tm070ddh03,
1204         }, {
1205                 .compatible = "chunghwa,claa101wa01a",
1206                 .data = &chunghwa_claa101wa01a
1207         }, {
1208                 .compatible = "chunghwa,claa101wb01",
1209                 .data = &chunghwa_claa101wb01
1210         }, {
1211                 .compatible = "edt,et057090dhu",
1212                 .data = &edt_et057090dhu,
1213         }, {
1214                 .compatible = "edt,et070080dh6",
1215                 .data = &edt_etm0700g0dh6,
1216         }, {
1217                 .compatible = "edt,etm0700g0dh6",
1218                 .data = &edt_etm0700g0dh6,
1219         }, {
1220                 .compatible = "foxlink,fl500wvr00-a0t",
1221                 .data = &foxlink_fl500wvr00_a0t,
1222         }, {
1223                 .compatible = "giantplus,gpg482739qs5",
1224                 .data = &giantplus_gpg482739qs5
1225         }, {
1226                 .compatible = "hannstar,hsd070pww1",
1227                 .data = &hannstar_hsd070pww1,
1228         }, {
1229                 .compatible = "hannstar,hsd100pxn1",
1230                 .data = &hannstar_hsd100pxn1,
1231         }, {
1232                 .compatible = "hit,tx23d38vm0caa",
1233                 .data = &hitachi_tx23d38vm0caa
1234         }, {
1235                 .compatible = "innolux,at043tn24",
1236                 .data = &innolux_at043tn24,
1237         }, {
1238                 .compatible ="innolux,g121i1-l01",
1239                 .data = &innolux_g121i1_l01
1240         }, {
1241                 .compatible = "innolux,g121x1-l03",
1242                 .data = &innolux_g121x1_l03,
1243         }, {
1244                 .compatible = "innolux,n116bge",
1245                 .data = &innolux_n116bge,
1246         }, {
1247                 .compatible = "innolux,n156bge-l21",
1248                 .data = &innolux_n156bge_l21,
1249         }, {
1250                 .compatible = "innolux,zj070na-01p",
1251                 .data = &innolux_zj070na_01p,
1252         }, {
1253                 .compatible = "kyo,tcg121xglp",
1254                 .data = &kyo_tcg121xglp,
1255         }, {
1256                 .compatible = "lg,lb070wv8",
1257                 .data = &lg_lb070wv8,
1258         }, {
1259                 .compatible = "lg,lp129qe",
1260                 .data = &lg_lp129qe,
1261         }, {
1262                 .compatible = "nec,nl4827hc19-05b",
1263                 .data = &nec_nl4827hc19_05b,
1264         }, {
1265                 .compatible = "okaya,rs800480t-7x0gp",
1266                 .data = &okaya_rs800480t_7x0gp,
1267         }, {
1268                 .compatible = "ortustech,com43h4m85ulc",
1269                 .data = &ortustech_com43h4m85ulc,
1270         }, {
1271                 .compatible = "qiaodian,qd43003c0-40",
1272                 .data = &qd43003c0_40,
1273         }, {
1274                 .compatible = "samsung,ltn101nt05",
1275                 .data = &samsung_ltn101nt05,
1276         }, {
1277                 .compatible = "samsung,ltn140at29-301",
1278                 .data = &samsung_ltn140at29_301,
1279         }, {
1280                 .compatible = "shelly,sca07010-bfn-lnn",
1281                 .data = &shelly_sca07010_bfn_lnn,
1282         }, {
1283                 /* sentinel */
1284         }
1285 };
1286 MODULE_DEVICE_TABLE(of, platform_of_match);
1287
1288 static int panel_simple_platform_probe(struct platform_device *pdev)
1289 {
1290         const struct of_device_id *id;
1291
1292         id = of_match_node(platform_of_match, pdev->dev.of_node);
1293         if (!id)
1294                 return -ENODEV;
1295
1296         return panel_simple_probe(&pdev->dev, id->data);
1297 }
1298
1299 static int panel_simple_platform_remove(struct platform_device *pdev)
1300 {
1301         return panel_simple_remove(&pdev->dev);
1302 }
1303
1304 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1305 {
1306         panel_simple_shutdown(&pdev->dev);
1307 }
1308
1309 static struct platform_driver panel_simple_platform_driver = {
1310         .driver = {
1311                 .name = "panel-simple",
1312                 .of_match_table = platform_of_match,
1313         },
1314         .probe = panel_simple_platform_probe,
1315         .remove = panel_simple_platform_remove,
1316         .shutdown = panel_simple_platform_shutdown,
1317 };
1318
1319 struct panel_desc_dsi {
1320         struct panel_desc desc;
1321
1322         unsigned long flags;
1323         enum mipi_dsi_pixel_format format;
1324         unsigned int lanes;
1325 };
1326
1327 static const struct drm_display_mode auo_b080uan01_mode = {
1328         .clock = 154500,
1329         .hdisplay = 1200,
1330         .hsync_start = 1200 + 62,
1331         .hsync_end = 1200 + 62 + 4,
1332         .htotal = 1200 + 62 + 4 + 62,
1333         .vdisplay = 1920,
1334         .vsync_start = 1920 + 9,
1335         .vsync_end = 1920 + 9 + 2,
1336         .vtotal = 1920 + 9 + 2 + 8,
1337         .vrefresh = 60,
1338 };
1339
1340 static const struct panel_desc_dsi auo_b080uan01 = {
1341         .desc = {
1342                 .modes = &auo_b080uan01_mode,
1343                 .num_modes = 1,
1344                 .bpc = 8,
1345                 .size = {
1346                         .width = 108,
1347                         .height = 272,
1348                 },
1349         },
1350         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1351         .format = MIPI_DSI_FMT_RGB888,
1352         .lanes = 4,
1353 };
1354
1355 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1356         .clock = 160000,
1357         .hdisplay = 1200,
1358         .hsync_start = 1200 + 120,
1359         .hsync_end = 1200 + 120 + 20,
1360         .htotal = 1200 + 120 + 20 + 21,
1361         .vdisplay = 1920,
1362         .vsync_start = 1920 + 21,
1363         .vsync_end = 1920 + 21 + 3,
1364         .vtotal = 1920 + 21 + 3 + 18,
1365         .vrefresh = 60,
1366         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1367 };
1368
1369 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1370         .desc = {
1371                 .modes = &boe_tv080wum_nl0_mode,
1372                 .num_modes = 1,
1373                 .size = {
1374                         .width = 107,
1375                         .height = 172,
1376                 },
1377         },
1378         .flags = MIPI_DSI_MODE_VIDEO |
1379                  MIPI_DSI_MODE_VIDEO_BURST |
1380                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1381         .format = MIPI_DSI_FMT_RGB888,
1382         .lanes = 4,
1383 };
1384
1385 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1386         .clock = 71000,
1387         .hdisplay = 800,
1388         .hsync_start = 800 + 32,
1389         .hsync_end = 800 + 32 + 1,
1390         .htotal = 800 + 32 + 1 + 57,
1391         .vdisplay = 1280,
1392         .vsync_start = 1280 + 28,
1393         .vsync_end = 1280 + 28 + 1,
1394         .vtotal = 1280 + 28 + 1 + 14,
1395         .vrefresh = 60,
1396 };
1397
1398 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1399         .desc = {
1400                 .modes = &lg_ld070wx3_sl01_mode,
1401                 .num_modes = 1,
1402                 .bpc = 8,
1403                 .size = {
1404                         .width = 94,
1405                         .height = 151,
1406                 },
1407         },
1408         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1409         .format = MIPI_DSI_FMT_RGB888,
1410         .lanes = 4,
1411 };
1412
1413 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1414         .clock = 67000,
1415         .hdisplay = 720,
1416         .hsync_start = 720 + 12,
1417         .hsync_end = 720 + 12 + 4,
1418         .htotal = 720 + 12 + 4 + 112,
1419         .vdisplay = 1280,
1420         .vsync_start = 1280 + 8,
1421         .vsync_end = 1280 + 8 + 4,
1422         .vtotal = 1280 + 8 + 4 + 12,
1423         .vrefresh = 60,
1424 };
1425
1426 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1427         .desc = {
1428                 .modes = &lg_lh500wx1_sd03_mode,
1429                 .num_modes = 1,
1430                 .bpc = 8,
1431                 .size = {
1432                         .width = 62,
1433                         .height = 110,
1434                 },
1435         },
1436         .flags = MIPI_DSI_MODE_VIDEO,
1437         .format = MIPI_DSI_FMT_RGB888,
1438         .lanes = 4,
1439 };
1440
1441 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1442         .clock = 157200,
1443         .hdisplay = 1920,
1444         .hsync_start = 1920 + 154,
1445         .hsync_end = 1920 + 154 + 16,
1446         .htotal = 1920 + 154 + 16 + 32,
1447         .vdisplay = 1200,
1448         .vsync_start = 1200 + 17,
1449         .vsync_end = 1200 + 17 + 2,
1450         .vtotal = 1200 + 17 + 2 + 16,
1451         .vrefresh = 60,
1452 };
1453
1454 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1455         .desc = {
1456                 .modes = &panasonic_vvx10f004b00_mode,
1457                 .num_modes = 1,
1458                 .bpc = 8,
1459                 .size = {
1460                         .width = 217,
1461                         .height = 136,
1462                 },
1463         },
1464         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1465                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1466         .format = MIPI_DSI_FMT_RGB888,
1467         .lanes = 4,
1468 };
1469
1470
1471 static const struct of_device_id dsi_of_match[] = {
1472         {
1473                 .compatible = "auo,b080uan01",
1474                 .data = &auo_b080uan01
1475         }, {
1476                 .compatible = "boe,tv080wum-nl0",
1477                 .data = &boe_tv080wum_nl0
1478         }, {
1479                 .compatible = "lg,ld070wx3-sl01",
1480                 .data = &lg_ld070wx3_sl01
1481         }, {
1482                 .compatible = "lg,lh500wx1-sd03",
1483                 .data = &lg_lh500wx1_sd03
1484         }, {
1485                 .compatible = "panasonic,vvx10f004b00",
1486                 .data = &panasonic_vvx10f004b00
1487         }, {
1488                 /* sentinel */
1489         }
1490 };
1491 MODULE_DEVICE_TABLE(of, dsi_of_match);
1492
1493 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1494 {
1495         const struct panel_desc_dsi *desc;
1496         const struct of_device_id *id;
1497         int err;
1498
1499         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1500         if (!id)
1501                 return -ENODEV;
1502
1503         desc = id->data;
1504
1505         err = panel_simple_probe(&dsi->dev, &desc->desc);
1506         if (err < 0)
1507                 return err;
1508
1509         dsi->mode_flags = desc->flags;
1510         dsi->format = desc->format;
1511         dsi->lanes = desc->lanes;
1512
1513         return mipi_dsi_attach(dsi);
1514 }
1515
1516 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1517 {
1518         int err;
1519
1520         err = mipi_dsi_detach(dsi);
1521         if (err < 0)
1522                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1523
1524         return panel_simple_remove(&dsi->dev);
1525 }
1526
1527 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1528 {
1529         panel_simple_shutdown(&dsi->dev);
1530 }
1531
1532 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1533         .driver = {
1534                 .name = "panel-simple-dsi",
1535                 .of_match_table = dsi_of_match,
1536         },
1537         .probe = panel_simple_dsi_probe,
1538         .remove = panel_simple_dsi_remove,
1539         .shutdown = panel_simple_dsi_shutdown,
1540 };
1541
1542 static int __init panel_simple_init(void)
1543 {
1544         int err;
1545
1546         err = platform_driver_register(&panel_simple_platform_driver);
1547         if (err < 0)
1548                 return err;
1549
1550         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1551                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1552                 if (err < 0)
1553                         return err;
1554         }
1555
1556         return 0;
1557 }
1558 module_init(panel_simple_init);
1559
1560 static void __exit panel_simple_exit(void)
1561 {
1562         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1563                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1564
1565         platform_driver_unregister(&panel_simple_platform_driver);
1566 }
1567 module_exit(panel_simple_exit);
1568
1569 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1570 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1571 MODULE_LICENSE("GPL and additional rights");