drivers/gpu/drm/radeon/radeon_drv.c

   1 /**
   2  * \file radeon_drv.c
   3  * ATI Radeon driver
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the next
  20  * paragraph) shall be included in all copies or substantial portions of the
  21  * Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  26  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  29  * OTHER DEALINGS IN THE SOFTWARE.
  30  */
  31
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon_drv.h"
  35
  36 #include <drm/drm_pciids.h>
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <drm/drm_gem.h>
  42
  43 #include "drm_crtc_helper.h"
  44 #include "radeon_kfd.h"
  45
  46 /*
  47  * KMS wrapper.
  48  * - 2.0.0 - initial interface
  49  * - 2.1.0 - add square tiling interface
  50  * - 2.2.0 - add r6xx/r7xx const buffer support
  51  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  52  * - 2.4.0 - add crtc id query
  53  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
  54  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
  55  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
  56  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
  57  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  58  *   2.10.0 - fusion 2D tiling
  59  *   2.11.0 - backend map, initial compute support for the CS checker
  60  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  61  *   2.13.0 - virtual memory support, streamout
  62  *   2.14.0 - add evergreen tiling informations
  63  *   2.15.0 - add max_pipes query
  64  *   2.16.0 - fix evergreen 2D tiled surface calculation
  65  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  66  *   2.18.0 - r600-eg: allow "invalid" DB formats
  67  *   2.19.0 - r600-eg: MSAA textures
  68  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  69  *   2.21.0 - r600-r700: FMASK and CMASK
  70  *   2.22.0 - r600 only: RESOLVE_BOX allowed
  71  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
  72  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
  73  *   2.25.0 - eg+: new info request for num SE and num SH
  74  *   2.26.0 - r600-eg: fix htile size computation
  75  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
  76  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
  77  *   2.29.0 - R500 FP16 color clear registers
  78  *   2.30.0 - fix for FMASK texturing
  79  *   2.31.0 - Add fastfb support for rs690
  80  *   2.32.0 - new info request for rings working
  81  *   2.33.0 - Add SI tiling mode array query
  82  *   2.34.0 - Add CIK tiling mode array query
  83  *   2.35.0 - Add CIK macrotile mode array query
  84  *   2.36.0 - Fix CIK DCE tiling setup
  85  *   2.37.0 - allow GS ring setup on r6xx/r7xx
  86  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
  87  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  88  *   2.39.0 - Add INFO query for number of active CUs
  89  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
  90  *            CS to GPU on >= r600
  91  *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
  92  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
  93  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
  94  *   2.44.0 - SET_APPEND_CNT packet3 support
  95  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
  96  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
  97  */
  98 #define KMS_DRIVER_MAJOR        2
  99 #define KMS_DRIVER_MINOR        46
 100 #define KMS_DRIVER_PATCHLEVEL   0
 101 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 102 int radeon_driver_unload_kms(struct drm_device *dev);
 103 void radeon_driver_lastclose_kms(struct drm_device *dev);
 104 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
 105 void radeon_driver_postclose_kms(struct drm_device *dev,
 106                                  struct drm_file *file_priv);
 107 void radeon_driver_preclose_kms(struct drm_device *dev,
 108                                 struct drm_file *file_priv);
 109 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
 110                        bool fbcon, bool freeze);
 111 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
 112 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
 113 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
 114 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
 115 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
 116                                     int *max_error,
 117                                     struct timeval *vblank_time,
 118                                     unsigned flags);
 119 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
 120 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
 121 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
 122 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
 123 void radeon_gem_object_free(struct drm_gem_object *obj);
 124 int radeon_gem_object_open(struct drm_gem_object *obj,
 125                                 struct drm_file *file_priv);
 126 void radeon_gem_object_close(struct drm_gem_object *obj,
 127                                 struct drm_file *file_priv);
 128 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
 129                                         struct drm_gem_object *gobj,
 130                                         int flags);
 131 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
 132                                       unsigned int flags, int *vpos, int *hpos,
 133                                       ktime_t *stime, ktime_t *etime,
 134                                       const struct drm_display_mode *mode);
 135 extern bool radeon_is_px(struct drm_device *dev);
 136 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
 137 extern int radeon_max_kms_ioctl;
 138 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
 139 int radeon_mode_dumb_mmap(struct drm_file *filp,
 140                           struct drm_device *dev,
 141                           uint32_t handle, uint64_t *offset_p);
 142 int radeon_mode_dumb_create(struct drm_file *file_priv,
 143                             struct drm_device *dev,
 144                             struct drm_mode_create_dumb *args);
 145 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
 146 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
 147                                                         struct dma_buf_attachment *,
 148                                                         struct sg_table *sg);
 149 int radeon_gem_prime_pin(struct drm_gem_object *obj);
 150 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
 151 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
 152 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
 153 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
 154 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
 155                                     unsigned long arg);
 156
 157 #if defined(CONFIG_DEBUG_FS)
 158 int radeon_debugfs_init(struct drm_minor *minor);
 159 void radeon_debugfs_cleanup(struct drm_minor *minor);
 160 #endif
 161
 162 /* atpx handler */
 163 #if defined(CONFIG_VGA_SWITCHEROO)
 164 void radeon_register_atpx_handler(void);
 165 void radeon_unregister_atpx_handler(void);
 166 bool radeon_has_atpx_dgpu_power_cntl(void);
 167 bool radeon_is_atpx_hybrid(void);
 168 #else
 169 static inline void radeon_register_atpx_handler(void) {}
 170 static inline void radeon_unregister_atpx_handler(void) {}
 171 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
 172 static inline bool radeon_is_atpx_hybrid(void) { return false; }
 173 #endif
 174
 175 int radeon_no_wb;
 176 int radeon_modeset = -1;
 177 int radeon_dynclks = -1;
 178 int radeon_r4xx_atom = 0;
 179 int radeon_agpmode = 0;
 180 int radeon_vram_limit = 0;
 181 int radeon_gart_size = -1; /* auto */
 182 int radeon_benchmarking = 0;
 183 int radeon_testing = 0;
 184 int radeon_connector_table = 0;
 185 int radeon_tv = 1;
 186 int radeon_audio = -1;
 187 int radeon_disp_priority = 0;
 188 int radeon_hw_i2c = 0;
 189 int radeon_pcie_gen2 = -1;
 190 int radeon_msi = -1;
 191 int radeon_lockup_timeout = 10000;
 192 int radeon_fastfb = 0;
 193 int radeon_dpm = -1;
 194 int radeon_aspm = -1;
 195 int radeon_runtime_pm = -1;
 196 int radeon_hard_reset = 0;
 197 int radeon_vm_size = 8;
 198 int radeon_vm_block_size = -1;
 199 int radeon_deep_color = 0;
 200 int radeon_use_pflipirq = 2;
 201 int radeon_bapm = -1;
 202 int radeon_backlight = -1;
 203 int radeon_auxch = -1;
 204 int radeon_mst = 0;
 205 int radeon_uvd = 1;
 206 int radeon_vce = 1;
 207
 208 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 209 module_param_named(no_wb, radeon_no_wb, int, 0444);
 210
 211 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
 212 module_param_named(modeset, radeon_modeset, int, 0400);
 213
 214 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
 215 module_param_named(dynclks, radeon_dynclks, int, 0444);
 216
 217 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
 218 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
 219
 220 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 221 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
 222
 223 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
 224 module_param_named(agpmode, radeon_agpmode, int, 0444);
 225
 226 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
 227 module_param_named(gartsize, radeon_gart_size, int, 0600);
 228
 229 MODULE_PARM_DESC(benchmark, "Run benchmark");
 230 module_param_named(benchmark, radeon_benchmarking, int, 0444);
 231
 232 MODULE_PARM_DESC(test, "Run tests");
 233 module_param_named(test, radeon_testing, int, 0444);
 234
 235 MODULE_PARM_DESC(connector_table, "Force connector table");
 236 module_param_named(connector_table, radeon_connector_table, int, 0444);
 237
 238 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
 239 module_param_named(tv, radeon_tv, int, 0444);
 240
 241 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 242 module_param_named(audio, radeon_audio, int, 0444);
 243
 244 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 245 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
 246
 247 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 248 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
 249
 250 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 251 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
 252
 253 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 254 module_param_named(msi, radeon_msi, int, 0444);
 255
 256 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
 257 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
 258
 259 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
 260 module_param_named(fastfb, radeon_fastfb, int, 0444);
 261
 262 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 263 module_param_named(dpm, radeon_dpm, int, 0444);
 264
 265 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 266 module_param_named(aspm, radeon_aspm, int, 0444);
 267
 268 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 269 module_param_named(runpm, radeon_runtime_pm, int, 0444);
 270
 271 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
 272 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
 273
 274 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
 275 module_param_named(vm_size, radeon_vm_size, int, 0444);
 276
 277 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 278 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
 279
 280 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 281 module_param_named(deep_color, radeon_deep_color, int, 0444);
 282
 283 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
 284 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
 285
 286 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
 287 module_param_named(bapm, radeon_bapm, int, 0444);
 288
 289 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
 290 module_param_named(backlight, radeon_backlight, int, 0444);
 291
 292 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
 293 module_param_named(auxch, radeon_auxch, int, 0444);
 294
 295 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
 296 module_param_named(mst, radeon_mst, int, 0444);
 297
 298 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
 299 module_param_named(uvd, radeon_uvd, int, 0444);
 300
 301 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
 302 module_param_named(vce, radeon_vce, int, 0444);
 303
 304 static struct pci_device_id pciidlist[] = {
 305         radeon_PCI_IDS
 306 };
 307
 308 MODULE_DEVICE_TABLE(pci, pciidlist);
 309
 310 static struct drm_driver kms_driver;
 311
 312 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
 313 {
 314         struct apertures_struct *ap;
 315         bool primary = false;
 316
 317         ap = alloc_apertures(1);
 318         if (!ap)
 319                 return -ENOMEM;
 320
 321         ap->ranges[0].base = pci_resource_start(pdev, 0);
 322         ap->ranges[0].size = pci_resource_len(pdev, 0);
 323
 324 #ifdef CONFIG_X86
 325         primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 326 #endif
 327         remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
 328         kfree(ap);
 329
 330         return 0;
 331 }
 332
 333 static int radeon_pci_probe(struct pci_dev *pdev,
 334                             const struct pci_device_id *ent)
 335 {
 336         int ret;
 337
 338         /*
 339          * Initialize amdkfd before starting radeon. If it was not loaded yet,
 340          * defer radeon probing
 341          */
 342         ret = radeon_kfd_init();
 343         if (ret == -EPROBE_DEFER)
 344                 return ret;
 345
 346         if (vga_switcheroo_client_probe_defer(pdev))
 347                 return -EPROBE_DEFER;
 348
 349         /* Get rid of things like offb */
 350         ret = radeon_kick_out_firmware_fb(pdev);
 351         if (ret)
 352                 return ret;
 353
 354         return drm_get_pci_dev(pdev, ent, &kms_driver);
 355 }
 356
 357 static void
 358 radeon_pci_remove(struct pci_dev *pdev)
 359 {
 360         struct drm_device *dev = pci_get_drvdata(pdev);
 361
 362         drm_put_dev(dev);
 363 }
 364
 365 static int radeon_pmops_suspend(struct device *dev)
 366 {
 367         struct pci_dev *pdev = to_pci_dev(dev);
 368         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 369         return radeon_suspend_kms(drm_dev, true, true, false);
 370 }
 371
 372 static int radeon_pmops_resume(struct device *dev)
 373 {
 374         struct pci_dev *pdev = to_pci_dev(dev);
 375         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 376         return radeon_resume_kms(drm_dev, true, true);
 377 }
 378
 379 static int radeon_pmops_freeze(struct device *dev)
 380 {
 381         struct pci_dev *pdev = to_pci_dev(dev);
 382         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 383         return radeon_suspend_kms(drm_dev, false, true, true);
 384 }
 385
 386 static int radeon_pmops_thaw(struct device *dev)
 387 {
 388         struct pci_dev *pdev = to_pci_dev(dev);
 389         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 390         return radeon_resume_kms(drm_dev, false, true);
 391 }
 392
 393 static int radeon_pmops_runtime_suspend(struct device *dev)
 394 {
 395         struct pci_dev *pdev = to_pci_dev(dev);
 396         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 397         int ret;
 398
 399         if (!radeon_is_px(drm_dev)) {
 400                 pm_runtime_forbid(dev);
 401                 return -EBUSY;
 402         }
 403
 404         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 405         drm_kms_helper_poll_disable(drm_dev);
 406         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
 407
 408         ret = radeon_suspend_kms(drm_dev, false, false, false);
 409         pci_save_state(pdev);
 410         pci_disable_device(pdev);
 411         pci_ignore_hotplug(pdev);
 412         if (radeon_is_atpx_hybrid())
 413                 pci_set_power_state(pdev, PCI_D3cold);
 414         else if (!radeon_has_atpx_dgpu_power_cntl())
 415                 pci_set_power_state(pdev, PCI_D3hot);
 416         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
 417
 418         return 0;
 419 }
 420
 421 static int radeon_pmops_runtime_resume(struct device *dev)
 422 {
 423         struct pci_dev *pdev = to_pci_dev(dev);
 424         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 425         int ret;
 426
 427         if (!radeon_is_px(drm_dev))
 428                 return -EINVAL;
 429
 430         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 431
 432         if (radeon_is_atpx_hybrid() ||
 433             !radeon_has_atpx_dgpu_power_cntl())
 434                 pci_set_power_state(pdev, PCI_D0);
 435         pci_restore_state(pdev);
 436         ret = pci_enable_device(pdev);
 437         if (ret)
 438                 return ret;
 439         pci_set_master(pdev);
 440
 441         ret = radeon_resume_kms(drm_dev, false, false);
 442         drm_kms_helper_poll_enable(drm_dev);
 443         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
 444         drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
 445         return 0;
 446 }
 447
 448 static int radeon_pmops_runtime_idle(struct device *dev)
 449 {
 450         struct pci_dev *pdev = to_pci_dev(dev);
 451         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 452         struct drm_crtc *crtc;
 453
 454         if (!radeon_is_px(drm_dev)) {
 455                 pm_runtime_forbid(dev);
 456                 return -EBUSY;
 457         }
 458
 459         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
 460                 if (crtc->enabled) {
 461                         DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
 462                         return -EBUSY;
 463                 }
 464         }
 465
 466         pm_runtime_mark_last_busy(dev);
 467         pm_runtime_autosuspend(dev);
 468         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
 469         return 1;
 470 }
 471
 472 long radeon_drm_ioctl(struct file *filp,
 473                       unsigned int cmd, unsigned long arg)
 474 {
 475         struct drm_file *file_priv = filp->private_data;
 476         struct drm_device *dev;
 477         long ret;
 478         dev = file_priv->minor->dev;
 479         ret = pm_runtime_get_sync(dev->dev);
 480         if (ret < 0)
 481                 return ret;
 482
 483         ret = drm_ioctl(filp, cmd, arg);
 484
 485         pm_runtime_mark_last_busy(dev->dev);
 486         pm_runtime_put_autosuspend(dev->dev);
 487         return ret;
 488 }
 489
 490 static const struct dev_pm_ops radeon_pm_ops = {
 491         .suspend = radeon_pmops_suspend,
 492         .resume = radeon_pmops_resume,
 493         .freeze = radeon_pmops_freeze,
 494         .thaw = radeon_pmops_thaw,
 495         .poweroff = radeon_pmops_freeze,
 496         .restore = radeon_pmops_resume,
 497         .runtime_suspend = radeon_pmops_runtime_suspend,
 498         .runtime_resume = radeon_pmops_runtime_resume,
 499         .runtime_idle = radeon_pmops_runtime_idle,
 500 };
 501
 502 static const struct file_operations radeon_driver_kms_fops = {
 503         .owner = THIS_MODULE,
 504         .open = drm_open,
 505         .release = drm_release,
 506         .unlocked_ioctl = radeon_drm_ioctl,
 507         .mmap = radeon_mmap,
 508         .poll = drm_poll,
 509         .read = drm_read,
 510 #ifdef CONFIG_COMPAT
 511         .compat_ioctl = radeon_kms_compat_ioctl,
 512 #endif
 513 };
 514
 515 static struct drm_driver kms_driver = {
 516         .driver_features =
 517             DRIVER_USE_AGP |
 518             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
 519             DRIVER_PRIME | DRIVER_RENDER,
 520         .load = radeon_driver_load_kms,
 521         .open = radeon_driver_open_kms,
 522         .preclose = radeon_driver_preclose_kms,
 523         .postclose = radeon_driver_postclose_kms,
 524         .lastclose = radeon_driver_lastclose_kms,
 525         .set_busid = drm_pci_set_busid,
 526         .unload = radeon_driver_unload_kms,
 527         .get_vblank_counter = radeon_get_vblank_counter_kms,
 528         .enable_vblank = radeon_enable_vblank_kms,
 529         .disable_vblank = radeon_disable_vblank_kms,
 530         .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
 531         .get_scanout_position = radeon_get_crtc_scanoutpos,
 532 #if defined(CONFIG_DEBUG_FS)
 533         .debugfs_init = radeon_debugfs_init,
 534         .debugfs_cleanup = radeon_debugfs_cleanup,
 535 #endif
 536         .irq_preinstall = radeon_driver_irq_preinstall_kms,
 537         .irq_postinstall = radeon_driver_irq_postinstall_kms,
 538         .irq_uninstall = radeon_driver_irq_uninstall_kms,
 539         .irq_handler = radeon_driver_irq_handler_kms,
 540         .ioctls = radeon_ioctls_kms,
 541         .gem_free_object_unlocked = radeon_gem_object_free,
 542         .gem_open_object = radeon_gem_object_open,
 543         .gem_close_object = radeon_gem_object_close,
 544         .dumb_create = radeon_mode_dumb_create,
 545         .dumb_map_offset = radeon_mode_dumb_mmap,
 546         .dumb_destroy = drm_gem_dumb_destroy,
 547         .fops = &radeon_driver_kms_fops,
 548
 549         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 550         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 551         .gem_prime_export = radeon_gem_prime_export,
 552         .gem_prime_import = drm_gem_prime_import,
 553         .gem_prime_pin = radeon_gem_prime_pin,
 554         .gem_prime_unpin = radeon_gem_prime_unpin,
 555         .gem_prime_res_obj = radeon_gem_prime_res_obj,
 556         .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
 557         .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
 558         .gem_prime_vmap = radeon_gem_prime_vmap,
 559         .gem_prime_vunmap = radeon_gem_prime_vunmap,
 560
 561         .name = DRIVER_NAME,
 562         .desc = DRIVER_DESC,
 563         .date = DRIVER_DATE,
 564         .major = KMS_DRIVER_MAJOR,
 565         .minor = KMS_DRIVER_MINOR,
 566         .patchlevel = KMS_DRIVER_PATCHLEVEL,
 567 };
 568
 569 static struct drm_driver *driver;
 570 static struct pci_driver *pdriver;
 571
 572 static struct pci_driver radeon_kms_pci_driver = {
 573         .name = DRIVER_NAME,
 574         .id_table = pciidlist,
 575         .probe = radeon_pci_probe,
 576         .remove = radeon_pci_remove,
 577         .driver.pm = &radeon_pm_ops,
 578 };
 579
 580 static int __init radeon_init(void)
 581 {
 582         if (vgacon_text_force() && radeon_modeset == -1) {
 583                 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
 584                 radeon_modeset = 0;
 585         }
 586         /* set to modesetting by default if not nomodeset */
 587         if (radeon_modeset == -1)
 588                 radeon_modeset = 1;
 589
 590         if (radeon_modeset == 1) {
 591                 DRM_INFO("radeon kernel modesetting enabled.\n");
 592                 driver = &kms_driver;
 593                 pdriver = &radeon_kms_pci_driver;
 594                 driver->driver_features |= DRIVER_MODESET;
 595                 driver->num_ioctls = radeon_max_kms_ioctl;
 596                 radeon_register_atpx_handler();
 597
 598         } else {
 599                 DRM_ERROR("No UMS support in radeon module!\n");
 600                 return -EINVAL;
 601         }
 602
 603         /* let modprobe override vga console setting */
 604         return drm_pci_init(driver, pdriver);
 605 }
 606
 607 static void __exit radeon_exit(void)
 608 {
 609         radeon_kfd_fini();
 610         drm_pci_exit(driver, pdriver);
 611         radeon_unregister_atpx_handler();
 612 }
 613
 614 module_init(radeon_init);
 615 module_exit(radeon_exit);
 616
 617 MODULE_AUTHOR(DRIVER_AUTHOR);
 618 MODULE_DESCRIPTION(DRIVER_DESC);
 619 MODULE_LICENSE("GPL and additional rights");