2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
33 #include "radeon_asic.h"
35 #include "rv515_reg_safe.h"
37 /* This files gather functions specifics to: rv515 */
38 static int rv515_debugfs_pipes_info_init(struct radeon_device
*rdev
);
39 static int rv515_debugfs_ga_info_init(struct radeon_device
*rdev
);
40 static void rv515_gpu_init(struct radeon_device
*rdev
);
41 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
);
43 static const u32 crtc_offsets
[2] =
46 AVIVO_D2CRTC_H_TOTAL
- AVIVO_D1CRTC_H_TOTAL
49 void rv515_debugfs(struct radeon_device
*rdev
)
51 if (r100_debugfs_rbbm_init(rdev
)) {
52 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
54 if (rv515_debugfs_pipes_info_init(rdev
)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
57 if (rv515_debugfs_ga_info_init(rdev
)) {
58 DRM_ERROR("Failed to register debugfs file for pipes !\n");
62 void rv515_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
66 r
= radeon_ring_lock(rdev
, ring
, 64);
70 radeon_ring_write(ring
, PACKET0(ISYNC_CNTL
, 0));
71 radeon_ring_write(ring
,
75 ISYNC_CPSCRATCH_IDLEGUI
);
76 radeon_ring_write(ring
, PACKET0(WAIT_UNTIL
, 0));
77 radeon_ring_write(ring
, WAIT_2D_IDLECLEAN
| WAIT_3D_IDLECLEAN
);
78 radeon_ring_write(ring
, PACKET0(R300_DST_PIPE_CONFIG
, 0));
79 radeon_ring_write(ring
, R300_PIPE_AUTO_CONFIG
);
80 radeon_ring_write(ring
, PACKET0(GB_SELECT
, 0));
81 radeon_ring_write(ring
, 0);
82 radeon_ring_write(ring
, PACKET0(GB_ENABLE
, 0));
83 radeon_ring_write(ring
, 0);
84 radeon_ring_write(ring
, PACKET0(R500_SU_REG_DEST
, 0));
85 radeon_ring_write(ring
, (1 << rdev
->num_gb_pipes
) - 1);
86 radeon_ring_write(ring
, PACKET0(VAP_INDEX_OFFSET
, 0));
87 radeon_ring_write(ring
, 0);
88 radeon_ring_write(ring
, PACKET0(RB3D_DSTCACHE_CTLSTAT
, 0));
89 radeon_ring_write(ring
, RB3D_DC_FLUSH
| RB3D_DC_FREE
);
90 radeon_ring_write(ring
, PACKET0(ZB_ZCACHE_CTLSTAT
, 0));
91 radeon_ring_write(ring
, ZC_FLUSH
| ZC_FREE
);
92 radeon_ring_write(ring
, PACKET0(WAIT_UNTIL
, 0));
93 radeon_ring_write(ring
, WAIT_2D_IDLECLEAN
| WAIT_3D_IDLECLEAN
);
94 radeon_ring_write(ring
, PACKET0(GB_AA_CONFIG
, 0));
95 radeon_ring_write(ring
, 0);
96 radeon_ring_write(ring
, PACKET0(RB3D_DSTCACHE_CTLSTAT
, 0));
97 radeon_ring_write(ring
, RB3D_DC_FLUSH
| RB3D_DC_FREE
);
98 radeon_ring_write(ring
, PACKET0(ZB_ZCACHE_CTLSTAT
, 0));
99 radeon_ring_write(ring
, ZC_FLUSH
| ZC_FREE
);
100 radeon_ring_write(ring
, PACKET0(GB_MSPOS0
, 0));
101 radeon_ring_write(ring
,
102 ((6 << MS_X0_SHIFT
) |
108 (6 << MSBD0_Y_SHIFT
) |
109 (6 << MSBD0_X_SHIFT
)));
110 radeon_ring_write(ring
, PACKET0(GB_MSPOS1
, 0));
111 radeon_ring_write(ring
,
112 ((6 << MS_X3_SHIFT
) |
118 (6 << MSBD1_SHIFT
)));
119 radeon_ring_write(ring
, PACKET0(GA_ENHANCE
, 0));
120 radeon_ring_write(ring
, GA_DEADLOCK_CNTL
| GA_FASTSYNC_CNTL
);
121 radeon_ring_write(ring
, PACKET0(GA_POLY_MODE
, 0));
122 radeon_ring_write(ring
, FRONT_PTYPE_TRIANGE
| BACK_PTYPE_TRIANGE
);
123 radeon_ring_write(ring
, PACKET0(GA_ROUND_MODE
, 0));
124 radeon_ring_write(ring
, GEOMETRY_ROUND_NEAREST
| COLOR_ROUND_NEAREST
);
125 radeon_ring_write(ring
, PACKET0(0x20C8, 0));
126 radeon_ring_write(ring
, 0);
127 radeon_ring_unlock_commit(rdev
, ring
, false);
130 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
)
135 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
137 tmp
= RREG32_MC(MC_STATUS
);
138 if (tmp
& MC_STATUS_IDLE
) {
146 void rv515_vga_render_disable(struct radeon_device
*rdev
)
148 WREG32(R_000300_VGA_RENDER_CONTROL
,
149 RREG32(R_000300_VGA_RENDER_CONTROL
) & C_000300_VGA_VSTATUS_CNTL
);
152 static void rv515_gpu_init(struct radeon_device
*rdev
)
154 unsigned pipe_select_current
, gb_pipe_select
, tmp
;
156 if (r100_gui_wait_for_idle(rdev
)) {
157 printk(KERN_WARNING
"Failed to wait GUI idle while "
158 "resetting GPU. Bad things might happen.\n");
160 rv515_vga_render_disable(rdev
);
161 r420_pipes_init(rdev
);
162 gb_pipe_select
= RREG32(R400_GB_PIPE_SELECT
);
163 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
164 pipe_select_current
= (tmp
>> 2) & 3;
165 tmp
= (1 << pipe_select_current
) |
166 (((gb_pipe_select
>> 8) & 0xF) << 4);
167 WREG32_PLL(0x000D, tmp
);
168 if (r100_gui_wait_for_idle(rdev
)) {
169 printk(KERN_WARNING
"Failed to wait GUI idle while "
170 "resetting GPU. Bad things might happen.\n");
172 if (rv515_mc_wait_for_idle(rdev
)) {
173 printk(KERN_WARNING
"Failed to wait MC idle while "
174 "programming pipes. Bad things might happen.\n");
178 static void rv515_vram_get_type(struct radeon_device
*rdev
)
182 rdev
->mc
.vram_width
= 128;
183 rdev
->mc
.vram_is_ddr
= true;
184 tmp
= RREG32_MC(RV515_MC_CNTL
) & MEM_NUM_CHANNELS_MASK
;
187 rdev
->mc
.vram_width
= 64;
190 rdev
->mc
.vram_width
= 128;
193 rdev
->mc
.vram_width
= 128;
198 static void rv515_mc_init(struct radeon_device
*rdev
)
201 rv515_vram_get_type(rdev
);
202 r100_vram_init_sizes(rdev
);
203 radeon_vram_location(rdev
, &rdev
->mc
, 0);
204 rdev
->mc
.gtt_base_align
= 0;
205 if (!(rdev
->flags
& RADEON_IS_AGP
))
206 radeon_gtt_location(rdev
, &rdev
->mc
);
207 radeon_update_bandwidth_info(rdev
);
210 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
215 spin_lock_irqsave(&rdev
->mc_idx_lock
, flags
);
216 WREG32(MC_IND_INDEX
, 0x7f0000 | (reg
& 0xffff));
217 r
= RREG32(MC_IND_DATA
);
218 WREG32(MC_IND_INDEX
, 0);
219 spin_unlock_irqrestore(&rdev
->mc_idx_lock
, flags
);
224 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
228 spin_lock_irqsave(&rdev
->mc_idx_lock
, flags
);
229 WREG32(MC_IND_INDEX
, 0xff0000 | ((reg
) & 0xffff));
230 WREG32(MC_IND_DATA
, (v
));
231 WREG32(MC_IND_INDEX
, 0);
232 spin_unlock_irqrestore(&rdev
->mc_idx_lock
, flags
);
235 #if defined(CONFIG_DEBUG_FS)
236 static int rv515_debugfs_pipes_info(struct seq_file
*m
, void *data
)
238 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
239 struct drm_device
*dev
= node
->minor
->dev
;
240 struct radeon_device
*rdev
= dev
->dev_private
;
243 tmp
= RREG32(GB_PIPE_SELECT
);
244 seq_printf(m
, "GB_PIPE_SELECT 0x%08x\n", tmp
);
245 tmp
= RREG32(SU_REG_DEST
);
246 seq_printf(m
, "SU_REG_DEST 0x%08x\n", tmp
);
247 tmp
= RREG32(GB_TILE_CONFIG
);
248 seq_printf(m
, "GB_TILE_CONFIG 0x%08x\n", tmp
);
249 tmp
= RREG32(DST_PIPE_CONFIG
);
250 seq_printf(m
, "DST_PIPE_CONFIG 0x%08x\n", tmp
);
254 static int rv515_debugfs_ga_info(struct seq_file
*m
, void *data
)
256 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
257 struct drm_device
*dev
= node
->minor
->dev
;
258 struct radeon_device
*rdev
= dev
->dev_private
;
261 tmp
= RREG32(0x2140);
262 seq_printf(m
, "VAP_CNTL_STATUS 0x%08x\n", tmp
);
263 radeon_asic_reset(rdev
);
264 tmp
= RREG32(0x425C);
265 seq_printf(m
, "GA_IDLE 0x%08x\n", tmp
);
269 static struct drm_info_list rv515_pipes_info_list
[] = {
270 {"rv515_pipes_info", rv515_debugfs_pipes_info
, 0, NULL
},
273 static struct drm_info_list rv515_ga_info_list
[] = {
274 {"rv515_ga_info", rv515_debugfs_ga_info
, 0, NULL
},
278 static int rv515_debugfs_pipes_info_init(struct radeon_device
*rdev
)
280 #if defined(CONFIG_DEBUG_FS)
281 return radeon_debugfs_add_files(rdev
, rv515_pipes_info_list
, 1);
287 static int rv515_debugfs_ga_info_init(struct radeon_device
*rdev
)
289 #if defined(CONFIG_DEBUG_FS)
290 return radeon_debugfs_add_files(rdev
, rv515_ga_info_list
, 1);
296 void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
)
298 u32 crtc_enabled
, tmp
, frame_count
, blackout
;
301 save
->vga_render_control
= RREG32(R_000300_VGA_RENDER_CONTROL
);
302 save
->vga_hdp_control
= RREG32(R_000328_VGA_HDP_CONTROL
);
304 /* disable VGA render */
305 WREG32(R_000300_VGA_RENDER_CONTROL
, 0);
306 /* blank the display controllers */
307 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
308 crtc_enabled
= RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]) & AVIVO_CRTC_EN
;
310 save
->crtc_enabled
[i
] = true;
311 tmp
= RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]);
312 if (!(tmp
& AVIVO_CRTC_DISP_READ_REQUEST_DISABLE
)) {
313 radeon_wait_for_vblank(rdev
, i
);
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
315 tmp
|= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE
;
316 WREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
317 WREG32(AVIVO_D1CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
319 /* wait for the next frame */
320 frame_count
= radeon_get_vblank_counter(rdev
, i
);
321 for (j
= 0; j
< rdev
->usec_timeout
; j
++) {
322 if (radeon_get_vblank_counter(rdev
, i
) != frame_count
)
327 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
328 WREG32(AVIVO_D1CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
329 tmp
= RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]);
330 tmp
&= ~AVIVO_CRTC_EN
;
331 WREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
332 WREG32(AVIVO_D1CRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
333 save
->crtc_enabled
[i
] = false;
336 save
->crtc_enabled
[i
] = false;
340 radeon_mc_wait_for_idle(rdev
);
342 if (rdev
->family
>= CHIP_R600
) {
343 if (rdev
->family
>= CHIP_RV770
)
344 blackout
= RREG32(R700_MC_CITF_CNTL
);
346 blackout
= RREG32(R600_CITF_CNTL
);
347 if ((blackout
& R600_BLACKOUT_MASK
) != R600_BLACKOUT_MASK
) {
348 /* Block CPU access */
349 WREG32(R600_BIF_FB_EN
, 0);
350 /* blackout the MC */
351 blackout
|= R600_BLACKOUT_MASK
;
352 if (rdev
->family
>= CHIP_RV770
)
353 WREG32(R700_MC_CITF_CNTL
, blackout
);
355 WREG32(R600_CITF_CNTL
, blackout
);
358 /* wait for the MC to settle */
361 /* lock double buffered regs */
362 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
363 if (save
->crtc_enabled
[i
]) {
364 tmp
= RREG32(AVIVO_D1GRPH_UPDATE
+ crtc_offsets
[i
]);
365 if (!(tmp
& AVIVO_D1GRPH_UPDATE_LOCK
)) {
366 tmp
|= AVIVO_D1GRPH_UPDATE_LOCK
;
367 WREG32(AVIVO_D1GRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
369 tmp
= RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
372 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
378 void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
)
380 u32 tmp
, frame_count
;
383 /* update crtc base addresses */
384 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
385 if (rdev
->family
>= CHIP_RV770
) {
387 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
,
388 upper_32_bits(rdev
->mc
.vram_start
));
389 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
,
390 upper_32_bits(rdev
->mc
.vram_start
));
392 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
,
393 upper_32_bits(rdev
->mc
.vram_start
));
394 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
,
395 upper_32_bits(rdev
->mc
.vram_start
));
398 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
399 (u32
)rdev
->mc
.vram_start
);
400 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
401 (u32
)rdev
->mc
.vram_start
);
403 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS
, (u32
)rdev
->mc
.vram_start
);
405 /* unlock regs and wait for update */
406 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
407 if (save
->crtc_enabled
[i
]) {
408 tmp
= RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
409 if ((tmp
& 0x7) != 0) {
411 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
413 tmp
= RREG32(AVIVO_D1GRPH_UPDATE
+ crtc_offsets
[i
]);
414 if (tmp
& AVIVO_D1GRPH_UPDATE_LOCK
) {
415 tmp
&= ~AVIVO_D1GRPH_UPDATE_LOCK
;
416 WREG32(AVIVO_D1GRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
418 tmp
= RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
421 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
423 for (j
= 0; j
< rdev
->usec_timeout
; j
++) {
424 tmp
= RREG32(AVIVO_D1GRPH_UPDATE
+ crtc_offsets
[i
]);
425 if ((tmp
& AVIVO_D1GRPH_SURFACE_UPDATE_PENDING
) == 0)
432 if (rdev
->family
>= CHIP_R600
) {
433 /* unblackout the MC */
434 if (rdev
->family
>= CHIP_RV770
)
435 tmp
= RREG32(R700_MC_CITF_CNTL
);
437 tmp
= RREG32(R600_CITF_CNTL
);
438 tmp
&= ~R600_BLACKOUT_MASK
;
439 if (rdev
->family
>= CHIP_RV770
)
440 WREG32(R700_MC_CITF_CNTL
, tmp
);
442 WREG32(R600_CITF_CNTL
, tmp
);
443 /* allow CPU access */
444 WREG32(R600_BIF_FB_EN
, R600_FB_READ_EN
| R600_FB_WRITE_EN
);
447 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
448 if (save
->crtc_enabled
[i
]) {
449 tmp
= RREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
]);
450 tmp
&= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE
;
451 WREG32(AVIVO_D1CRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
452 /* wait for the next frame */
453 frame_count
= radeon_get_vblank_counter(rdev
, i
);
454 for (j
= 0; j
< rdev
->usec_timeout
; j
++) {
455 if (radeon_get_vblank_counter(rdev
, i
) != frame_count
)
461 /* Unlock vga access */
462 WREG32(R_000328_VGA_HDP_CONTROL
, save
->vga_hdp_control
);
464 WREG32(R_000300_VGA_RENDER_CONTROL
, save
->vga_render_control
);
467 static void rv515_mc_program(struct radeon_device
*rdev
)
469 struct rv515_mc_save save
;
471 /* Stops all mc clients */
472 rv515_mc_stop(rdev
, &save
);
474 /* Wait for mc idle */
475 if (rv515_mc_wait_for_idle(rdev
))
476 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
477 /* Write VRAM size in case we are limiting it */
478 WREG32(R_0000F8_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
479 /* Program MC, should be a 32bits limited address space */
480 WREG32_MC(R_000001_MC_FB_LOCATION
,
481 S_000001_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
482 S_000001_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
483 WREG32(R_000134_HDP_FB_LOCATION
,
484 S_000134_HDP_FB_START(rdev
->mc
.vram_start
>> 16));
485 if (rdev
->flags
& RADEON_IS_AGP
) {
486 WREG32_MC(R_000002_MC_AGP_LOCATION
,
487 S_000002_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
488 S_000002_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
489 WREG32_MC(R_000003_MC_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
490 WREG32_MC(R_000004_MC_AGP_BASE_2
,
491 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev
->mc
.agp_base
)));
493 WREG32_MC(R_000002_MC_AGP_LOCATION
, 0xFFFFFFFF);
494 WREG32_MC(R_000003_MC_AGP_BASE
, 0);
495 WREG32_MC(R_000004_MC_AGP_BASE_2
, 0);
498 rv515_mc_resume(rdev
, &save
);
501 void rv515_clock_startup(struct radeon_device
*rdev
)
503 if (radeon_dynclks
!= -1 && radeon_dynclks
)
504 radeon_atom_set_clock_gating(rdev
, 1);
505 /* We need to force on some of the block */
506 WREG32_PLL(R_00000F_CP_DYN_CNTL
,
507 RREG32_PLL(R_00000F_CP_DYN_CNTL
) | S_00000F_CP_FORCEON(1));
508 WREG32_PLL(R_000011_E2_DYN_CNTL
,
509 RREG32_PLL(R_000011_E2_DYN_CNTL
) | S_000011_E2_FORCEON(1));
510 WREG32_PLL(R_000013_IDCT_DYN_CNTL
,
511 RREG32_PLL(R_000013_IDCT_DYN_CNTL
) | S_000013_IDCT_FORCEON(1));
514 static int rv515_startup(struct radeon_device
*rdev
)
518 rv515_mc_program(rdev
);
520 rv515_clock_startup(rdev
);
521 /* Initialize GPU configuration (# pipes, ...) */
522 rv515_gpu_init(rdev
);
523 /* Initialize GART (initialize after TTM so we can allocate
524 * memory through TTM but finalize after TTM) */
525 if (rdev
->flags
& RADEON_IS_PCIE
) {
526 r
= rv370_pcie_gart_enable(rdev
);
531 /* allocate wb buffer */
532 r
= radeon_wb_init(rdev
);
536 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
538 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
543 if (!rdev
->irq
.installed
) {
544 r
= radeon_irq_kms_init(rdev
);
550 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
552 r
= r100_cp_init(rdev
, 1024 * 1024);
554 dev_err(rdev
->dev
, "failed initializing CP (%d).\n", r
);
558 r
= radeon_ib_pool_init(rdev
);
560 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
567 int rv515_resume(struct radeon_device
*rdev
)
571 /* Make sur GART are not working */
572 if (rdev
->flags
& RADEON_IS_PCIE
)
573 rv370_pcie_gart_disable(rdev
);
574 /* Resume clock before doing reset */
575 rv515_clock_startup(rdev
);
576 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
577 if (radeon_asic_reset(rdev
)) {
578 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
579 RREG32(R_000E40_RBBM_STATUS
),
580 RREG32(R_0007C0_CP_STAT
));
583 atom_asic_init(rdev
->mode_info
.atom_context
);
584 /* Resume clock after posting */
585 rv515_clock_startup(rdev
);
586 /* Initialize surface registers */
587 radeon_surface_init(rdev
);
589 rdev
->accel_working
= true;
590 r
= rv515_startup(rdev
);
592 rdev
->accel_working
= false;
597 int rv515_suspend(struct radeon_device
*rdev
)
599 radeon_pm_suspend(rdev
);
600 r100_cp_disable(rdev
);
601 radeon_wb_disable(rdev
);
602 rs600_irq_disable(rdev
);
603 if (rdev
->flags
& RADEON_IS_PCIE
)
604 rv370_pcie_gart_disable(rdev
);
608 void rv515_set_safe_registers(struct radeon_device
*rdev
)
610 rdev
->config
.r300
.reg_safe_bm
= rv515_reg_safe_bm
;
611 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(rv515_reg_safe_bm
);
614 void rv515_fini(struct radeon_device
*rdev
)
616 radeon_pm_fini(rdev
);
618 radeon_wb_fini(rdev
);
619 radeon_ib_pool_fini(rdev
);
620 radeon_gem_fini(rdev
);
621 rv370_pcie_gart_fini(rdev
);
622 radeon_agp_fini(rdev
);
623 radeon_irq_kms_fini(rdev
);
624 radeon_fence_driver_fini(rdev
);
625 radeon_bo_fini(rdev
);
626 radeon_atombios_fini(rdev
);
631 int rv515_init(struct radeon_device
*rdev
)
635 /* Initialize scratch registers */
636 radeon_scratch_init(rdev
);
637 /* Initialize surface registers */
638 radeon_surface_init(rdev
);
639 /* TODO: disable VGA need to use VGA request */
640 /* restore some register to sane defaults */
641 r100_restore_sanity(rdev
);
643 if (!radeon_get_bios(rdev
)) {
644 if (ASIC_IS_AVIVO(rdev
))
647 if (rdev
->is_atom_bios
) {
648 r
= radeon_atombios_init(rdev
);
652 dev_err(rdev
->dev
, "Expecting atombios for RV515 GPU\n");
655 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
656 if (radeon_asic_reset(rdev
)) {
658 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
659 RREG32(R_000E40_RBBM_STATUS
),
660 RREG32(R_0007C0_CP_STAT
));
662 /* check if cards are posted or not */
663 if (radeon_boot_test_post_card(rdev
) == false)
665 /* Initialize clocks */
666 radeon_get_clock_info(rdev
->ddev
);
668 if (rdev
->flags
& RADEON_IS_AGP
) {
669 r
= radeon_agp_init(rdev
);
671 radeon_agp_disable(rdev
);
674 /* initialize memory controller */
678 r
= radeon_fence_driver_init(rdev
);
682 r
= radeon_bo_init(rdev
);
685 r
= rv370_pcie_gart_init(rdev
);
688 rv515_set_safe_registers(rdev
);
690 /* Initialize power management */
691 radeon_pm_init(rdev
);
693 rdev
->accel_working
= true;
694 r
= rv515_startup(rdev
);
696 /* Somethings want wront with the accel init stop accel */
697 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
699 radeon_wb_fini(rdev
);
700 radeon_ib_pool_fini(rdev
);
701 radeon_irq_kms_fini(rdev
);
702 rv370_pcie_gart_fini(rdev
);
703 radeon_agp_fini(rdev
);
704 rdev
->accel_working
= false;
709 void atom_rv515_force_tv_scaler(struct radeon_device
*rdev
, struct radeon_crtc
*crtc
)
711 int index_reg
= 0x6578 + crtc
->crtc_offset
;
712 int data_reg
= 0x657c + crtc
->crtc_offset
;
714 WREG32(0x659C + crtc
->crtc_offset
, 0x0);
715 WREG32(0x6594 + crtc
->crtc_offset
, 0x705);
716 WREG32(0x65A4 + crtc
->crtc_offset
, 0x10001);
717 WREG32(0x65D8 + crtc
->crtc_offset
, 0x0);
718 WREG32(0x65B0 + crtc
->crtc_offset
, 0x0);
719 WREG32(0x65C0 + crtc
->crtc_offset
, 0x0);
720 WREG32(0x65D4 + crtc
->crtc_offset
, 0x0);
721 WREG32(index_reg
, 0x0);
722 WREG32(data_reg
, 0x841880A8);
723 WREG32(index_reg
, 0x1);
724 WREG32(data_reg
, 0x84208680);
725 WREG32(index_reg
, 0x2);
726 WREG32(data_reg
, 0xBFF880B0);
727 WREG32(index_reg
, 0x100);
728 WREG32(data_reg
, 0x83D88088);
729 WREG32(index_reg
, 0x101);
730 WREG32(data_reg
, 0x84608680);
731 WREG32(index_reg
, 0x102);
732 WREG32(data_reg
, 0xBFF080D0);
733 WREG32(index_reg
, 0x200);
734 WREG32(data_reg
, 0x83988068);
735 WREG32(index_reg
, 0x201);
736 WREG32(data_reg
, 0x84A08680);
737 WREG32(index_reg
, 0x202);
738 WREG32(data_reg
, 0xBFF080F8);
739 WREG32(index_reg
, 0x300);
740 WREG32(data_reg
, 0x83588058);
741 WREG32(index_reg
, 0x301);
742 WREG32(data_reg
, 0x84E08660);
743 WREG32(index_reg
, 0x302);
744 WREG32(data_reg
, 0xBFF88120);
745 WREG32(index_reg
, 0x400);
746 WREG32(data_reg
, 0x83188040);
747 WREG32(index_reg
, 0x401);
748 WREG32(data_reg
, 0x85008660);
749 WREG32(index_reg
, 0x402);
750 WREG32(data_reg
, 0xBFF88150);
751 WREG32(index_reg
, 0x500);
752 WREG32(data_reg
, 0x82D88030);
753 WREG32(index_reg
, 0x501);
754 WREG32(data_reg
, 0x85408640);
755 WREG32(index_reg
, 0x502);
756 WREG32(data_reg
, 0xBFF88180);
757 WREG32(index_reg
, 0x600);
758 WREG32(data_reg
, 0x82A08018);
759 WREG32(index_reg
, 0x601);
760 WREG32(data_reg
, 0x85808620);
761 WREG32(index_reg
, 0x602);
762 WREG32(data_reg
, 0xBFF081B8);
763 WREG32(index_reg
, 0x700);
764 WREG32(data_reg
, 0x82608010);
765 WREG32(index_reg
, 0x701);
766 WREG32(data_reg
, 0x85A08600);
767 WREG32(index_reg
, 0x702);
768 WREG32(data_reg
, 0x800081F0);
769 WREG32(index_reg
, 0x800);
770 WREG32(data_reg
, 0x8228BFF8);
771 WREG32(index_reg
, 0x801);
772 WREG32(data_reg
, 0x85E085E0);
773 WREG32(index_reg
, 0x802);
774 WREG32(data_reg
, 0xBFF88228);
775 WREG32(index_reg
, 0x10000);
776 WREG32(data_reg
, 0x82A8BF00);
777 WREG32(index_reg
, 0x10001);
778 WREG32(data_reg
, 0x82A08CC0);
779 WREG32(index_reg
, 0x10002);
780 WREG32(data_reg
, 0x8008BEF8);
781 WREG32(index_reg
, 0x10100);
782 WREG32(data_reg
, 0x81F0BF28);
783 WREG32(index_reg
, 0x10101);
784 WREG32(data_reg
, 0x83608CA0);
785 WREG32(index_reg
, 0x10102);
786 WREG32(data_reg
, 0x8018BED0);
787 WREG32(index_reg
, 0x10200);
788 WREG32(data_reg
, 0x8148BF38);
789 WREG32(index_reg
, 0x10201);
790 WREG32(data_reg
, 0x84408C80);
791 WREG32(index_reg
, 0x10202);
792 WREG32(data_reg
, 0x8008BEB8);
793 WREG32(index_reg
, 0x10300);
794 WREG32(data_reg
, 0x80B0BF78);
795 WREG32(index_reg
, 0x10301);
796 WREG32(data_reg
, 0x85008C20);
797 WREG32(index_reg
, 0x10302);
798 WREG32(data_reg
, 0x8020BEA0);
799 WREG32(index_reg
, 0x10400);
800 WREG32(data_reg
, 0x8028BF90);
801 WREG32(index_reg
, 0x10401);
802 WREG32(data_reg
, 0x85E08BC0);
803 WREG32(index_reg
, 0x10402);
804 WREG32(data_reg
, 0x8018BE90);
805 WREG32(index_reg
, 0x10500);
806 WREG32(data_reg
, 0xBFB8BFB0);
807 WREG32(index_reg
, 0x10501);
808 WREG32(data_reg
, 0x86C08B40);
809 WREG32(index_reg
, 0x10502);
810 WREG32(data_reg
, 0x8010BE90);
811 WREG32(index_reg
, 0x10600);
812 WREG32(data_reg
, 0xBF58BFC8);
813 WREG32(index_reg
, 0x10601);
814 WREG32(data_reg
, 0x87A08AA0);
815 WREG32(index_reg
, 0x10602);
816 WREG32(data_reg
, 0x8010BE98);
817 WREG32(index_reg
, 0x10700);
818 WREG32(data_reg
, 0xBF10BFF0);
819 WREG32(index_reg
, 0x10701);
820 WREG32(data_reg
, 0x886089E0);
821 WREG32(index_reg
, 0x10702);
822 WREG32(data_reg
, 0x8018BEB0);
823 WREG32(index_reg
, 0x10800);
824 WREG32(data_reg
, 0xBED8BFE8);
825 WREG32(index_reg
, 0x10801);
826 WREG32(data_reg
, 0x89408940);
827 WREG32(index_reg
, 0x10802);
828 WREG32(data_reg
, 0xBFE8BED8);
829 WREG32(index_reg
, 0x20000);
830 WREG32(data_reg
, 0x80008000);
831 WREG32(index_reg
, 0x20001);
832 WREG32(data_reg
, 0x90008000);
833 WREG32(index_reg
, 0x20002);
834 WREG32(data_reg
, 0x80008000);
835 WREG32(index_reg
, 0x20003);
836 WREG32(data_reg
, 0x80008000);
837 WREG32(index_reg
, 0x20100);
838 WREG32(data_reg
, 0x80108000);
839 WREG32(index_reg
, 0x20101);
840 WREG32(data_reg
, 0x8FE0BF70);
841 WREG32(index_reg
, 0x20102);
842 WREG32(data_reg
, 0xBFE880C0);
843 WREG32(index_reg
, 0x20103);
844 WREG32(data_reg
, 0x80008000);
845 WREG32(index_reg
, 0x20200);
846 WREG32(data_reg
, 0x8018BFF8);
847 WREG32(index_reg
, 0x20201);
848 WREG32(data_reg
, 0x8F80BF08);
849 WREG32(index_reg
, 0x20202);
850 WREG32(data_reg
, 0xBFD081A0);
851 WREG32(index_reg
, 0x20203);
852 WREG32(data_reg
, 0xBFF88000);
853 WREG32(index_reg
, 0x20300);
854 WREG32(data_reg
, 0x80188000);
855 WREG32(index_reg
, 0x20301);
856 WREG32(data_reg
, 0x8EE0BEC0);
857 WREG32(index_reg
, 0x20302);
858 WREG32(data_reg
, 0xBFB082A0);
859 WREG32(index_reg
, 0x20303);
860 WREG32(data_reg
, 0x80008000);
861 WREG32(index_reg
, 0x20400);
862 WREG32(data_reg
, 0x80188000);
863 WREG32(index_reg
, 0x20401);
864 WREG32(data_reg
, 0x8E00BEA0);
865 WREG32(index_reg
, 0x20402);
866 WREG32(data_reg
, 0xBF8883C0);
867 WREG32(index_reg
, 0x20403);
868 WREG32(data_reg
, 0x80008000);
869 WREG32(index_reg
, 0x20500);
870 WREG32(data_reg
, 0x80188000);
871 WREG32(index_reg
, 0x20501);
872 WREG32(data_reg
, 0x8D00BE90);
873 WREG32(index_reg
, 0x20502);
874 WREG32(data_reg
, 0xBF588500);
875 WREG32(index_reg
, 0x20503);
876 WREG32(data_reg
, 0x80008008);
877 WREG32(index_reg
, 0x20600);
878 WREG32(data_reg
, 0x80188000);
879 WREG32(index_reg
, 0x20601);
880 WREG32(data_reg
, 0x8BC0BE98);
881 WREG32(index_reg
, 0x20602);
882 WREG32(data_reg
, 0xBF308660);
883 WREG32(index_reg
, 0x20603);
884 WREG32(data_reg
, 0x80008008);
885 WREG32(index_reg
, 0x20700);
886 WREG32(data_reg
, 0x80108000);
887 WREG32(index_reg
, 0x20701);
888 WREG32(data_reg
, 0x8A80BEB0);
889 WREG32(index_reg
, 0x20702);
890 WREG32(data_reg
, 0xBF0087C0);
891 WREG32(index_reg
, 0x20703);
892 WREG32(data_reg
, 0x80008008);
893 WREG32(index_reg
, 0x20800);
894 WREG32(data_reg
, 0x80108000);
895 WREG32(index_reg
, 0x20801);
896 WREG32(data_reg
, 0x8920BED0);
897 WREG32(index_reg
, 0x20802);
898 WREG32(data_reg
, 0xBED08920);
899 WREG32(index_reg
, 0x20803);
900 WREG32(data_reg
, 0x80008010);
901 WREG32(index_reg
, 0x30000);
902 WREG32(data_reg
, 0x90008000);
903 WREG32(index_reg
, 0x30001);
904 WREG32(data_reg
, 0x80008000);
905 WREG32(index_reg
, 0x30100);
906 WREG32(data_reg
, 0x8FE0BF90);
907 WREG32(index_reg
, 0x30101);
908 WREG32(data_reg
, 0xBFF880A0);
909 WREG32(index_reg
, 0x30200);
910 WREG32(data_reg
, 0x8F60BF40);
911 WREG32(index_reg
, 0x30201);
912 WREG32(data_reg
, 0xBFE88180);
913 WREG32(index_reg
, 0x30300);
914 WREG32(data_reg
, 0x8EC0BF00);
915 WREG32(index_reg
, 0x30301);
916 WREG32(data_reg
, 0xBFC88280);
917 WREG32(index_reg
, 0x30400);
918 WREG32(data_reg
, 0x8DE0BEE0);
919 WREG32(index_reg
, 0x30401);
920 WREG32(data_reg
, 0xBFA083A0);
921 WREG32(index_reg
, 0x30500);
922 WREG32(data_reg
, 0x8CE0BED0);
923 WREG32(index_reg
, 0x30501);
924 WREG32(data_reg
, 0xBF7884E0);
925 WREG32(index_reg
, 0x30600);
926 WREG32(data_reg
, 0x8BA0BED8);
927 WREG32(index_reg
, 0x30601);
928 WREG32(data_reg
, 0xBF508640);
929 WREG32(index_reg
, 0x30700);
930 WREG32(data_reg
, 0x8A60BEE8);
931 WREG32(index_reg
, 0x30701);
932 WREG32(data_reg
, 0xBF2087A0);
933 WREG32(index_reg
, 0x30800);
934 WREG32(data_reg
, 0x8900BF00);
935 WREG32(index_reg
, 0x30801);
936 WREG32(data_reg
, 0xBF008900);
939 struct rv515_watermark
{
940 u32 lb_request_fifo_depth
;
941 fixed20_12 num_line_pair
;
942 fixed20_12 estimated_width
;
943 fixed20_12 worst_case_latency
;
944 fixed20_12 consumption_rate
;
945 fixed20_12 active_time
;
947 fixed20_12 priority_mark_max
;
948 fixed20_12 priority_mark
;
952 static void rv515_crtc_bandwidth_compute(struct radeon_device
*rdev
,
953 struct radeon_crtc
*crtc
,
954 struct rv515_watermark
*wm
,
957 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
959 fixed20_12 pclk
, request_fifo_depth
, tolerable_latency
, estimated_width
;
960 fixed20_12 consumption_time
, line_time
, chunk_time
, read_delay_latency
;
964 if (!crtc
->base
.enabled
) {
965 /* FIXME: wouldn't it better to set priority mark to maximum */
966 wm
->lb_request_fifo_depth
= 4;
971 if ((rdev
->family
>= CHIP_RV610
) &&
972 (rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
973 selected_sclk
= radeon_dpm_get_sclk(rdev
, low
);
975 selected_sclk
= rdev
->pm
.current_sclk
;
978 a
.full
= dfixed_const(100);
979 sclk
.full
= dfixed_const(selected_sclk
);
980 sclk
.full
= dfixed_div(sclk
, a
);
982 if (crtc
->vsc
.full
> dfixed_const(2))
983 wm
->num_line_pair
.full
= dfixed_const(2);
985 wm
->num_line_pair
.full
= dfixed_const(1);
987 b
.full
= dfixed_const(mode
->crtc_hdisplay
);
988 c
.full
= dfixed_const(256);
989 a
.full
= dfixed_div(b
, c
);
990 request_fifo_depth
.full
= dfixed_mul(a
, wm
->num_line_pair
);
991 request_fifo_depth
.full
= dfixed_ceil(request_fifo_depth
);
992 if (a
.full
< dfixed_const(4)) {
993 wm
->lb_request_fifo_depth
= 4;
995 wm
->lb_request_fifo_depth
= dfixed_trunc(request_fifo_depth
);
998 /* Determine consumption rate
999 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
1000 * vtaps = number of vertical taps,
1001 * vsc = vertical scaling ratio, defined as source/destination
1002 * hsc = horizontal scaling ration, defined as source/destination
1004 a
.full
= dfixed_const(mode
->clock
);
1005 b
.full
= dfixed_const(1000);
1006 a
.full
= dfixed_div(a
, b
);
1007 pclk
.full
= dfixed_div(b
, a
);
1008 if (crtc
->rmx_type
!= RMX_OFF
) {
1009 b
.full
= dfixed_const(2);
1010 if (crtc
->vsc
.full
> b
.full
)
1011 b
.full
= crtc
->vsc
.full
;
1012 b
.full
= dfixed_mul(b
, crtc
->hsc
);
1013 c
.full
= dfixed_const(2);
1014 b
.full
= dfixed_div(b
, c
);
1015 consumption_time
.full
= dfixed_div(pclk
, b
);
1017 consumption_time
.full
= pclk
.full
;
1019 a
.full
= dfixed_const(1);
1020 wm
->consumption_rate
.full
= dfixed_div(a
, consumption_time
);
1023 /* Determine line time
1024 * LineTime = total time for one line of displayhtotal
1025 * LineTime = total number of horizontal pixels
1026 * pclk = pixel clock period(ns)
1028 a
.full
= dfixed_const(crtc
->base
.mode
.crtc_htotal
);
1029 line_time
.full
= dfixed_mul(a
, pclk
);
1031 /* Determine active time
1032 * ActiveTime = time of active region of display within one line,
1033 * hactive = total number of horizontal active pixels
1034 * htotal = total number of horizontal pixels
1036 a
.full
= dfixed_const(crtc
->base
.mode
.crtc_htotal
);
1037 b
.full
= dfixed_const(crtc
->base
.mode
.crtc_hdisplay
);
1038 wm
->active_time
.full
= dfixed_mul(line_time
, b
);
1039 wm
->active_time
.full
= dfixed_div(wm
->active_time
, a
);
1041 /* Determine chunk time
1042 * ChunkTime = the time it takes the DCP to send one chunk of data
1043 * to the LB which consists of pipeline delay and inter chunk gap
1044 * sclk = system clock(Mhz)
1046 a
.full
= dfixed_const(600 * 1000);
1047 chunk_time
.full
= dfixed_div(a
, sclk
);
1048 read_delay_latency
.full
= dfixed_const(1000);
1050 /* Determine the worst case latency
1051 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1052 * WorstCaseLatency = worst case time from urgent to when the MC starts
1054 * READ_DELAY_IDLE_MAX = constant of 1us
1055 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1056 * which consists of pipeline delay and inter chunk gap
1058 if (dfixed_trunc(wm
->num_line_pair
) > 1) {
1059 a
.full
= dfixed_const(3);
1060 wm
->worst_case_latency
.full
= dfixed_mul(a
, chunk_time
);
1061 wm
->worst_case_latency
.full
+= read_delay_latency
.full
;
1063 wm
->worst_case_latency
.full
= chunk_time
.full
+ read_delay_latency
.full
;
1066 /* Determine the tolerable latency
1067 * TolerableLatency = Any given request has only 1 line time
1068 * for the data to be returned
1069 * LBRequestFifoDepth = Number of chunk requests the LB can
1070 * put into the request FIFO for a display
1071 * LineTime = total time for one line of display
1072 * ChunkTime = the time it takes the DCP to send one chunk
1073 * of data to the LB which consists of
1074 * pipeline delay and inter chunk gap
1076 if ((2+wm
->lb_request_fifo_depth
) >= dfixed_trunc(request_fifo_depth
)) {
1077 tolerable_latency
.full
= line_time
.full
;
1079 tolerable_latency
.full
= dfixed_const(wm
->lb_request_fifo_depth
- 2);
1080 tolerable_latency
.full
= request_fifo_depth
.full
- tolerable_latency
.full
;
1081 tolerable_latency
.full
= dfixed_mul(tolerable_latency
, chunk_time
);
1082 tolerable_latency
.full
= line_time
.full
- tolerable_latency
.full
;
1084 /* We assume worst case 32bits (4 bytes) */
1085 wm
->dbpp
.full
= dfixed_const(2 * 16);
1087 /* Determine the maximum priority mark
1088 * width = viewport width in pixels
1090 a
.full
= dfixed_const(16);
1091 wm
->priority_mark_max
.full
= dfixed_const(crtc
->base
.mode
.crtc_hdisplay
);
1092 wm
->priority_mark_max
.full
= dfixed_div(wm
->priority_mark_max
, a
);
1093 wm
->priority_mark_max
.full
= dfixed_ceil(wm
->priority_mark_max
);
1095 /* Determine estimated width */
1096 estimated_width
.full
= tolerable_latency
.full
- wm
->worst_case_latency
.full
;
1097 estimated_width
.full
= dfixed_div(estimated_width
, consumption_time
);
1098 if (dfixed_trunc(estimated_width
) > crtc
->base
.mode
.crtc_hdisplay
) {
1099 wm
->priority_mark
.full
= wm
->priority_mark_max
.full
;
1101 a
.full
= dfixed_const(16);
1102 wm
->priority_mark
.full
= dfixed_div(estimated_width
, a
);
1103 wm
->priority_mark
.full
= dfixed_ceil(wm
->priority_mark
);
1104 wm
->priority_mark
.full
= wm
->priority_mark_max
.full
- wm
->priority_mark
.full
;
1108 static void rv515_compute_mode_priority(struct radeon_device
*rdev
,
1109 struct rv515_watermark
*wm0
,
1110 struct rv515_watermark
*wm1
,
1111 struct drm_display_mode
*mode0
,
1112 struct drm_display_mode
*mode1
,
1113 u32
*d1mode_priority_a_cnt
,
1114 u32
*d2mode_priority_a_cnt
)
1116 fixed20_12 priority_mark02
, priority_mark12
, fill_rate
;
1119 *d1mode_priority_a_cnt
= MODE_PRIORITY_OFF
;
1120 *d2mode_priority_a_cnt
= MODE_PRIORITY_OFF
;
1122 if (mode0
&& mode1
) {
1123 if (dfixed_trunc(wm0
->dbpp
) > 64)
1124 a
.full
= dfixed_div(wm0
->dbpp
, wm0
->num_line_pair
);
1126 a
.full
= wm0
->num_line_pair
.full
;
1127 if (dfixed_trunc(wm1
->dbpp
) > 64)
1128 b
.full
= dfixed_div(wm1
->dbpp
, wm1
->num_line_pair
);
1130 b
.full
= wm1
->num_line_pair
.full
;
1132 fill_rate
.full
= dfixed_div(wm0
->sclk
, a
);
1133 if (wm0
->consumption_rate
.full
> fill_rate
.full
) {
1134 b
.full
= wm0
->consumption_rate
.full
- fill_rate
.full
;
1135 b
.full
= dfixed_mul(b
, wm0
->active_time
);
1136 a
.full
= dfixed_const(16);
1137 b
.full
= dfixed_div(b
, a
);
1138 a
.full
= dfixed_mul(wm0
->worst_case_latency
,
1139 wm0
->consumption_rate
);
1140 priority_mark02
.full
= a
.full
+ b
.full
;
1142 a
.full
= dfixed_mul(wm0
->worst_case_latency
,
1143 wm0
->consumption_rate
);
1144 b
.full
= dfixed_const(16 * 1000);
1145 priority_mark02
.full
= dfixed_div(a
, b
);
1147 if (wm1
->consumption_rate
.full
> fill_rate
.full
) {
1148 b
.full
= wm1
->consumption_rate
.full
- fill_rate
.full
;
1149 b
.full
= dfixed_mul(b
, wm1
->active_time
);
1150 a
.full
= dfixed_const(16);
1151 b
.full
= dfixed_div(b
, a
);
1152 a
.full
= dfixed_mul(wm1
->worst_case_latency
,
1153 wm1
->consumption_rate
);
1154 priority_mark12
.full
= a
.full
+ b
.full
;
1156 a
.full
= dfixed_mul(wm1
->worst_case_latency
,
1157 wm1
->consumption_rate
);
1158 b
.full
= dfixed_const(16 * 1000);
1159 priority_mark12
.full
= dfixed_div(a
, b
);
1161 if (wm0
->priority_mark
.full
> priority_mark02
.full
)
1162 priority_mark02
.full
= wm0
->priority_mark
.full
;
1163 if (wm0
->priority_mark_max
.full
> priority_mark02
.full
)
1164 priority_mark02
.full
= wm0
->priority_mark_max
.full
;
1165 if (wm1
->priority_mark
.full
> priority_mark12
.full
)
1166 priority_mark12
.full
= wm1
->priority_mark
.full
;
1167 if (wm1
->priority_mark_max
.full
> priority_mark12
.full
)
1168 priority_mark12
.full
= wm1
->priority_mark_max
.full
;
1169 *d1mode_priority_a_cnt
= dfixed_trunc(priority_mark02
);
1170 *d2mode_priority_a_cnt
= dfixed_trunc(priority_mark12
);
1171 if (rdev
->disp_priority
== 2) {
1172 *d1mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1173 *d2mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1176 if (dfixed_trunc(wm0
->dbpp
) > 64)
1177 a
.full
= dfixed_div(wm0
->dbpp
, wm0
->num_line_pair
);
1179 a
.full
= wm0
->num_line_pair
.full
;
1180 fill_rate
.full
= dfixed_div(wm0
->sclk
, a
);
1181 if (wm0
->consumption_rate
.full
> fill_rate
.full
) {
1182 b
.full
= wm0
->consumption_rate
.full
- fill_rate
.full
;
1183 b
.full
= dfixed_mul(b
, wm0
->active_time
);
1184 a
.full
= dfixed_const(16);
1185 b
.full
= dfixed_div(b
, a
);
1186 a
.full
= dfixed_mul(wm0
->worst_case_latency
,
1187 wm0
->consumption_rate
);
1188 priority_mark02
.full
= a
.full
+ b
.full
;
1190 a
.full
= dfixed_mul(wm0
->worst_case_latency
,
1191 wm0
->consumption_rate
);
1192 b
.full
= dfixed_const(16);
1193 priority_mark02
.full
= dfixed_div(a
, b
);
1195 if (wm0
->priority_mark
.full
> priority_mark02
.full
)
1196 priority_mark02
.full
= wm0
->priority_mark
.full
;
1197 if (wm0
->priority_mark_max
.full
> priority_mark02
.full
)
1198 priority_mark02
.full
= wm0
->priority_mark_max
.full
;
1199 *d1mode_priority_a_cnt
= dfixed_trunc(priority_mark02
);
1200 if (rdev
->disp_priority
== 2)
1201 *d1mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1203 if (dfixed_trunc(wm1
->dbpp
) > 64)
1204 a
.full
= dfixed_div(wm1
->dbpp
, wm1
->num_line_pair
);
1206 a
.full
= wm1
->num_line_pair
.full
;
1207 fill_rate
.full
= dfixed_div(wm1
->sclk
, a
);
1208 if (wm1
->consumption_rate
.full
> fill_rate
.full
) {
1209 b
.full
= wm1
->consumption_rate
.full
- fill_rate
.full
;
1210 b
.full
= dfixed_mul(b
, wm1
->active_time
);
1211 a
.full
= dfixed_const(16);
1212 b
.full
= dfixed_div(b
, a
);
1213 a
.full
= dfixed_mul(wm1
->worst_case_latency
,
1214 wm1
->consumption_rate
);
1215 priority_mark12
.full
= a
.full
+ b
.full
;
1217 a
.full
= dfixed_mul(wm1
->worst_case_latency
,
1218 wm1
->consumption_rate
);
1219 b
.full
= dfixed_const(16 * 1000);
1220 priority_mark12
.full
= dfixed_div(a
, b
);
1222 if (wm1
->priority_mark
.full
> priority_mark12
.full
)
1223 priority_mark12
.full
= wm1
->priority_mark
.full
;
1224 if (wm1
->priority_mark_max
.full
> priority_mark12
.full
)
1225 priority_mark12
.full
= wm1
->priority_mark_max
.full
;
1226 *d2mode_priority_a_cnt
= dfixed_trunc(priority_mark12
);
1227 if (rdev
->disp_priority
== 2)
1228 *d2mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1232 void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
)
1234 struct drm_display_mode
*mode0
= NULL
;
1235 struct drm_display_mode
*mode1
= NULL
;
1236 struct rv515_watermark wm0_high
, wm0_low
;
1237 struct rv515_watermark wm1_high
, wm1_low
;
1239 u32 d1mode_priority_a_cnt
, d1mode_priority_b_cnt
;
1240 u32 d2mode_priority_a_cnt
, d2mode_priority_b_cnt
;
1242 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
)
1243 mode0
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
1244 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
)
1245 mode1
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
1246 rs690_line_buffer_adjust(rdev
, mode0
, mode1
);
1248 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[0], &wm0_high
, false);
1249 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[1], &wm1_high
, false);
1251 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[0], &wm0_low
, false);
1252 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[1], &wm1_low
, false);
1254 tmp
= wm0_high
.lb_request_fifo_depth
;
1255 tmp
|= wm1_high
.lb_request_fifo_depth
<< 16;
1256 WREG32(LB_MAX_REQ_OUTSTANDING
, tmp
);
1258 rv515_compute_mode_priority(rdev
,
1259 &wm0_high
, &wm1_high
,
1261 &d1mode_priority_a_cnt
, &d2mode_priority_a_cnt
);
1262 rv515_compute_mode_priority(rdev
,
1265 &d1mode_priority_b_cnt
, &d2mode_priority_b_cnt
);
1267 WREG32(D1MODE_PRIORITY_A_CNT
, d1mode_priority_a_cnt
);
1268 WREG32(D1MODE_PRIORITY_B_CNT
, d1mode_priority_b_cnt
);
1269 WREG32(D2MODE_PRIORITY_A_CNT
, d2mode_priority_a_cnt
);
1270 WREG32(D2MODE_PRIORITY_B_CNT
, d2mode_priority_b_cnt
);
1273 void rv515_bandwidth_update(struct radeon_device
*rdev
)
1276 struct drm_display_mode
*mode0
= NULL
;
1277 struct drm_display_mode
*mode1
= NULL
;
1279 if (!rdev
->mode_info
.mode_config_initialized
)
1282 radeon_update_display_priority(rdev
);
1284 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
)
1285 mode0
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
1286 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
)
1287 mode1
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
1289 * Set display0/1 priority up in the memory controller for
1290 * modes if the user specifies HIGH for displaypriority
1293 if ((rdev
->disp_priority
== 2) &&
1294 (rdev
->family
== CHIP_RV515
)) {
1295 tmp
= RREG32_MC(MC_MISC_LAT_TIMER
);
1296 tmp
&= ~MC_DISP1R_INIT_LAT_MASK
;
1297 tmp
&= ~MC_DISP0R_INIT_LAT_MASK
;
1299 tmp
|= (1 << MC_DISP1R_INIT_LAT_SHIFT
);
1301 tmp
|= (1 << MC_DISP0R_INIT_LAT_SHIFT
);
1302 WREG32_MC(MC_MISC_LAT_TIMER
, tmp
);
1304 rv515_bandwidth_avivo_update(rdev
);