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Merge git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending
[deliverable/linux.git] / drivers / gpu / drm / radeon / si_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "radeon_asic.h"
27 #include "sid.h"
28 #include "r600_dpm.h"
29 #include "si_dpm.h"
30 #include "atom.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
33
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
38
39 #define SMC_RAM_END 0x20000
40
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
44 {
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106 };
107
108 static const struct si_cac_config_reg lcac_tahiti[] =
109 {
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198 };
199
200 static const struct si_cac_config_reg cac_override_tahiti[] =
201 {
202 { 0xFFFFFFFF }
203 };
204
205 static const struct si_powertune_data powertune_data_tahiti =
206 {
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234 };
235
236 static const struct si_dte_data dte_data_tahiti =
237 {
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252 };
253
254 static const struct si_dte_data dte_data_tahiti_le =
255 {
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270 };
271
272 static const struct si_dte_data dte_data_tahiti_pro =
273 {
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288 };
289
290 static const struct si_dte_data dte_data_new_zealand =
291 {
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306 };
307
308 static const struct si_dte_data dte_data_aruba_pro =
309 {
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324 };
325
326 static const struct si_dte_data dte_data_malta =
327 {
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342 };
343
344 struct si_cac_config_reg cac_weights_pitcairn[] =
345 {
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407 };
408
409 static const struct si_cac_config_reg lcac_pitcairn[] =
410 {
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498 };
499
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
501 {
502 { 0xFFFFFFFF }
503 };
504
505 static const struct si_powertune_data powertune_data_pitcairn =
506 {
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534 };
535
536 static const struct si_dte_data dte_data_pitcairn =
537 {
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552 };
553
554 static const struct si_dte_data dte_data_curacao_xt =
555 {
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570 };
571
572 static const struct si_dte_data dte_data_curacao_pro =
573 {
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588 };
589
590 static const struct si_dte_data dte_data_neptune_xt =
591 {
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606 };
607
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609 {
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671 };
672
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674 {
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736 };
737
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
739 {
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801 };
802
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804 {
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866 };
867
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
869 {
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931 };
932
933 static const struct si_cac_config_reg lcac_cape_verde[] =
934 {
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990 };
991
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
993 {
994 { 0xFFFFFFFF }
995 };
996
997 static const struct si_powertune_data powertune_data_cape_verde =
998 {
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521 { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 u32 engine_clock,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767 return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 s64 tmp;
1776
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1786
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1799 u16 v,
1800 s32 t,
1801 u32 i_leakage,
1802 u32 *leakage)
1803 {
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1810 {
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1827 const u32 fixed_kt,
1828 u16 v,
1829 u32 i_leakage,
1830 u32 *leakage)
1831 {
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1838 {
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1845 u32 i;
1846
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1849
1850 for (i = 0; i < k; i++) {
1851 dte_data->r[i] =
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1854 }
1855
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1860 }
1861 } else {
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1871
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1878
1879 switch (rdev->pdev->device) {
1880 case 0x6798:
1881 si_pi->dte_data.enable_dte_by_default = true;
1882 break;
1883 case 0x6799:
1884 si_pi->dte_data = dte_data_new_zealand;
1885 break;
1886 case 0x6790:
1887 case 0x6791:
1888 case 0x6792:
1889 case 0x679E:
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679B:
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1896 break;
1897 case 0x679A:
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1900 break;
1901 default:
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1904 break;
1905 }
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1908 case 0x6810:
1909 case 0x6818:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6819:
1918 case 0x6811:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1925 break;
1926 case 0x6800:
1927 case 0x6806:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1934 break;
1935 default:
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1941 break;
1942 }
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948 switch (rdev->pdev->device) {
1949 case 0x683B:
1950 case 0x683F:
1951 case 0x6829:
1952 case 0x6835:
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682C:
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 break;
1960 case 0x6825:
1961 case 0x6827:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6824:
1966 case 0x682D:
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1969 break;
1970 case 0x682F:
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1973 break;
1974 case 0x6820:
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1977 break;
1978 case 0x6821:
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1981 break;
1982 case 0x6823:
1983 case 0x682B:
1984 case 0x6822:
1985 case 0x682A:
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1988 break;
1989 default:
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1992 break;
1993 }
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
1996 case 0x6601:
1997 case 0x6621:
1998 case 0x6603:
1999 case 0x6605:
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x6600:
2008 case 0x6606:
2009 case 0x6620:
2010 case 0x6604:
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x6611:
2019 case 0x6613:
2020 case 0x6608:
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6610:
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2035 break;
2036 default:
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2042 break;
2043 }
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2051 } else {
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 return;
2054 }
2055
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2060
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069 }
2070 ni_pi->enable_sq_ramping = true;
2071 }
2072
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2075
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2082 } else {
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2086 }
2087
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093 return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098 u32 xclk;
2099 u32 wintime;
2100 u32 cac_window;
2101 u32 cac_window_size;
2102
2103 xclk = radeon_get_xclk(rdev);
2104
2105 if (xclk == 0)
2106 return 0;
2107
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111 wintime = (cac_window_size * 100) / xclk;
2112
2113 return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118 return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2123 u32 tdp_adjustment,
2124 u32 *tdp_limit,
2125 u32 *near_tdp_limit)
2126 {
2127 u32 adjustment_delta, max_tdp_limit;
2128
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 return -EINVAL;
2131
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 } else {
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 else
2143 *near_tdp_limit = 0;
2144 }
2145
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 return -EINVAL;
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 return -EINVAL;
2150
2151 return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2156 {
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 u32 tdp_limit;
2166 u32 near_tdp_limit;
2167 int ret;
2168
2169 if (scaling_factor == 0)
2170 return -EINVAL;
2171
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 false, /* ??? */
2176 rdev->pm.dpm.tdp_adjustment,
2177 &tdp_limit,
2178 &near_tdp_limit);
2179 if (ret)
2180 return ret;
2181
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 sizeof(u32) * 3,
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 (u8 *)papm_parm,
2210 sizeof(PP_SIslands_PAPMParameters),
2211 si_pi->sram_end);
2212 if (ret)
2213 return ret;
2214 }
2215 }
2216 return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2221 {
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 int ret;
2229
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 sizeof(u32) * 2,
2243 si_pi->sram_end);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2254 {
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2259
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2261 return 0;
2262
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2266
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 return 0;
2269
2270 return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2275 {
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2280 return true;
2281
2282 return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 u32 prev_sclk;
2294 u32 max_sclk;
2295 u32 min_sclk;
2296 u16 prev_std_vddc;
2297 u16 curr_std_vddc;
2298 int i;
2299 u16 pwr_efficiency_ratio;
2300 u8 max_ps_percent;
2301 bool disable_uvd_power_tune;
2302 int ret;
2303
2304 if (ni_pi->enable_power_containment == false)
2305 return 0;
2306
2307 if (state->performance_level_count == 0)
2308 return -EINVAL;
2309
2310 if (smc_state->levelCount != state->performance_level_count)
2311 return -EINVAL;
2312
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2324 if (i == 1)
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 else
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329 if (prev_sclk > max_sclk)
2330 return -EINVAL;
2331
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2338 } else {
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 }
2341
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2344
2345 if (min_sclk == 0)
2346 return -EINVAL;
2347
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2350 if (ret)
2351 return ret;
2352
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2359 if (ret)
2360 return ret;
2361
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 if (ret)
2364 return ret;
2365
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2368
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 }
2375
2376 return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 int i;
2388
2389 if (state->performance_level_count == 0)
2390 return -EINVAL;
2391
2392 if (smc_state->levelCount != state->performance_level_count)
2393 return -EINVAL;
2394
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 return -EINVAL;
2397
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2403
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2406
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2409
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2412
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2416
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 } else {
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 }
2428
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2438 bool enable)
2439 {
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2442 int ret = 0;
2443
2444 if (ni_pi->enable_power_containment) {
2445 if (enable) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2449 ret = -EINVAL;
2450 ni_pi->pc_enabled = false;
2451 } else {
2452 ni_pi->pc_enabled = true;
2453 }
2454 }
2455 } else {
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2458 ret = -EINVAL;
2459 ni_pi->pc_enabled = false;
2460 }
2461 }
2462
2463 return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2469 int ret = 0;
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 u32 table_size;
2473 u8 tdep_count;
2474 u32 i;
2475
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2478
2479 if (si_pi->enable_dte == false)
2480 return 0;
2481
2482 if (dte_data->k <= 0)
2483 return -EINVAL;
2484
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2488 return -ENOMEM;
2489 }
2490
2491 table_size = dte_data->k;
2492
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508 if (tdep_count > 0)
2509 table_size--;
2510
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2514 }
2515
2516 dte_tables->Tdep_count = tdep_count;
2517
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 }
2523
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 kfree(dte_tables);
2527
2528 return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 u16 *max, u16 *min)
2533 {
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 u32 i;
2538 u32 v0_loadline;
2539
2540
2541 if (table == NULL)
2542 return -EINVAL;
2543
2544 *max = 0;
2545 *min = 0xFFFF;
2546
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2552 }
2553
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 return -EINVAL;
2556
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559 if (v0_loadline > 0xFFFFUL)
2560 return -EINVAL;
2561
2562 *min = (u16)v0_loadline;
2563
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2565 return -EINVAL;
2566
2567 return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 u16 t0, u16 t_step)
2580 {
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2582 u32 leakage;
2583 unsigned int i, j;
2584 s32 t;
2585 u32 smc_leakage;
2586 u32 scaling_factor;
2587 u16 voltage;
2588
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2593
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2596
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2599 voltage,
2600 t,
2601 si_pi->dyn_powertune_data.cac_leakage,
2602 &leakage);
2603
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2608
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2611 }
2612 }
2613 return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2621 u32 leakage;
2622 unsigned int i, j;
2623 u32 smc_leakage;
2624 u32 scaling_factor;
2625 u16 voltage;
2626
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2631
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2635 voltage,
2636 si_pi->dyn_powertune_data.cac_leakage,
2637 &leakage);
2638
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2643
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2647 }
2648 return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2657 u16 t0, t_step;
2658 u32 load_line_slope, reg;
2659 int ret = 0;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662 if (ni_pi->enable_cac == false)
2663 return 0;
2664
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 if (!cac_tables)
2667 return -ENOMEM;
2668
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2672
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 if (ret)
2683 goto done_free;
2684
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 t_step = 4;
2688 t0 = 60;
2689
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2693 t0, t_step);
2694 else
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2697 if (ret)
2698 goto done_free;
2699
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719 if (ret)
2720 goto done_free;
2721
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725 if (ret) {
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2728 }
2729
2730 kfree(cac_tables);
2731
2732 return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2737 {
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2740
2741 if (!config_regs)
2742 return -EINVAL;
2743
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2750 break;
2751 default:
2752 data = RREG32(config_regs->offset << 2);
2753 break;
2754 }
2755
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2764 break;
2765 default:
2766 WREG32(config_regs->offset << 2, data);
2767 break;
2768 }
2769 config_regs++;
2770 }
2771 return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2778 int ret;
2779
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2782 return 0;
2783
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 if (ret)
2786 return ret;
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 if (ret)
2789 return ret;
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 if (ret)
2792 return ret;
2793
2794 return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2799 bool enable)
2800 {
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2804 int ret = 0;
2805
2806 if (ni_pi->enable_cac) {
2807 if (enable) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2813 }
2814
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2817 ret = -EINVAL;
2818 ni_pi->cac_enabled = false;
2819 } else {
2820 ni_pi->cac_enabled = true;
2821 }
2822
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2826 ret = -EINVAL;
2827 }
2828 }
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835 ni_pi->cac_enabled = false;
2836
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 }
2840 }
2841 return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 u32 fb_div, p_div;
2851 u32 clk_s, clk_v;
2852 u32 sclk = 0;
2853 int ret = 0;
2854 u32 tmp;
2855 int i;
2856
2857 if (si_pi->spll_table_start == 0)
2858 return -EINVAL;
2859
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2862 return -ENOMEM;
2863
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 if (ret)
2867 break;
2868
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874 fb_div &= ~0x00001FFF;
2875 fb_div >>= 1;
2876 clk_v >>= 6;
2877
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 ret = -EINVAL;
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 ret = -EINVAL;
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 ret = -EINVAL;
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 ret = -EINVAL;
2886
2887 if (ret)
2888 break;
2889
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898 sclk += 512;
2899 }
2900
2901
2902 if (!ret)
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 si_pi->sram_end);
2906
2907 if (ret)
2908 ni_pi->enable_power_containment = false;
2909
2910 kfree(spll_table);
2911
2912 return ret;
2913 }
2914
2915 struct si_dpm_quirk {
2916 u32 chip_vendor;
2917 u32 chip_device;
2918 u32 subsys_vendor;
2919 u32 subsys_device;
2920 u32 max_sclk;
2921 u32 max_mclk;
2922 };
2923
2924 /* cards with dpm stability problems */
2925 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2926 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2930 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2932 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2933 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2934 { 0, 0, 0, 0 },
2935 };
2936
2937 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2938 u16 vce_voltage)
2939 {
2940 u16 highest_leakage = 0;
2941 struct si_power_info *si_pi = si_get_pi(rdev);
2942 int i;
2943
2944 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2945 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2946 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2947 }
2948
2949 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2950 return highest_leakage;
2951
2952 return vce_voltage;
2953 }
2954
2955 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2956 u32 evclk, u32 ecclk, u16 *voltage)
2957 {
2958 u32 i;
2959 int ret = -EINVAL;
2960 struct radeon_vce_clock_voltage_dependency_table *table =
2961 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2962
2963 if (((evclk == 0) && (ecclk == 0)) ||
2964 (table && (table->count == 0))) {
2965 *voltage = 0;
2966 return 0;
2967 }
2968
2969 for (i = 0; i < table->count; i++) {
2970 if ((evclk <= table->entries[i].evclk) &&
2971 (ecclk <= table->entries[i].ecclk)) {
2972 *voltage = table->entries[i].v;
2973 ret = 0;
2974 break;
2975 }
2976 }
2977
2978 /* if no match return the highest voltage */
2979 if (ret)
2980 *voltage = table->entries[table->count - 1].v;
2981
2982 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2983
2984 return ret;
2985 }
2986
2987 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2988 struct radeon_ps *rps)
2989 {
2990 struct ni_ps *ps = ni_get_ps(rps);
2991 struct radeon_clock_and_voltage_limits *max_limits;
2992 bool disable_mclk_switching = false;
2993 bool disable_sclk_switching = false;
2994 u32 mclk, sclk;
2995 u16 vddc, vddci, min_vce_voltage = 0;
2996 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2997 u32 max_sclk = 0, max_mclk = 0;
2998 int i;
2999 struct si_dpm_quirk *p = si_dpm_quirk_list;
3000
3001 /* Apply dpm quirks */
3002 while (p && p->chip_device != 0) {
3003 if (rdev->pdev->vendor == p->chip_vendor &&
3004 rdev->pdev->device == p->chip_device &&
3005 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3006 rdev->pdev->subsystem_device == p->subsys_device) {
3007 max_sclk = p->max_sclk;
3008 max_mclk = p->max_mclk;
3009 break;
3010 }
3011 ++p;
3012 }
3013 /* limit mclk on all R7 370 parts for stability */
3014 if (rdev->pdev->device == 0x6811 &&
3015 rdev->pdev->revision == 0x81)
3016 max_mclk = 120000;
3017
3018 if (rps->vce_active) {
3019 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3020 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3021 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3022 &min_vce_voltage);
3023 } else {
3024 rps->evclk = 0;
3025 rps->ecclk = 0;
3026 }
3027
3028 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3029 ni_dpm_vblank_too_short(rdev))
3030 disable_mclk_switching = true;
3031
3032 if (rps->vclk || rps->dclk) {
3033 disable_mclk_switching = true;
3034 disable_sclk_switching = true;
3035 }
3036
3037 if (rdev->pm.dpm.ac_power)
3038 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3039 else
3040 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3041
3042 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3043 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3044 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3045 }
3046 if (rdev->pm.dpm.ac_power == false) {
3047 for (i = 0; i < ps->performance_level_count; i++) {
3048 if (ps->performance_levels[i].mclk > max_limits->mclk)
3049 ps->performance_levels[i].mclk = max_limits->mclk;
3050 if (ps->performance_levels[i].sclk > max_limits->sclk)
3051 ps->performance_levels[i].sclk = max_limits->sclk;
3052 if (ps->performance_levels[i].vddc > max_limits->vddc)
3053 ps->performance_levels[i].vddc = max_limits->vddc;
3054 if (ps->performance_levels[i].vddci > max_limits->vddci)
3055 ps->performance_levels[i].vddci = max_limits->vddci;
3056 }
3057 }
3058
3059 /* limit clocks to max supported clocks based on voltage dependency tables */
3060 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3061 &max_sclk_vddc);
3062 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3063 &max_mclk_vddci);
3064 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3065 &max_mclk_vddc);
3066
3067 for (i = 0; i < ps->performance_level_count; i++) {
3068 if (max_sclk_vddc) {
3069 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3070 ps->performance_levels[i].sclk = max_sclk_vddc;
3071 }
3072 if (max_mclk_vddci) {
3073 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3074 ps->performance_levels[i].mclk = max_mclk_vddci;
3075 }
3076 if (max_mclk_vddc) {
3077 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3078 ps->performance_levels[i].mclk = max_mclk_vddc;
3079 }
3080 if (max_mclk) {
3081 if (ps->performance_levels[i].mclk > max_mclk)
3082 ps->performance_levels[i].mclk = max_mclk;
3083 }
3084 if (max_sclk) {
3085 if (ps->performance_levels[i].sclk > max_sclk)
3086 ps->performance_levels[i].sclk = max_sclk;
3087 }
3088 }
3089
3090 /* XXX validate the min clocks required for display */
3091
3092 if (disable_mclk_switching) {
3093 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3094 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3095 } else {
3096 mclk = ps->performance_levels[0].mclk;
3097 vddci = ps->performance_levels[0].vddci;
3098 }
3099
3100 if (disable_sclk_switching) {
3101 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3102 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3103 } else {
3104 sclk = ps->performance_levels[0].sclk;
3105 vddc = ps->performance_levels[0].vddc;
3106 }
3107
3108 if (rps->vce_active) {
3109 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3110 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3111 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3112 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3113 }
3114
3115 /* adjusted low state */
3116 ps->performance_levels[0].sclk = sclk;
3117 ps->performance_levels[0].mclk = mclk;
3118 ps->performance_levels[0].vddc = vddc;
3119 ps->performance_levels[0].vddci = vddci;
3120
3121 if (disable_sclk_switching) {
3122 sclk = ps->performance_levels[0].sclk;
3123 for (i = 1; i < ps->performance_level_count; i++) {
3124 if (sclk < ps->performance_levels[i].sclk)
3125 sclk = ps->performance_levels[i].sclk;
3126 }
3127 for (i = 0; i < ps->performance_level_count; i++) {
3128 ps->performance_levels[i].sclk = sclk;
3129 ps->performance_levels[i].vddc = vddc;
3130 }
3131 } else {
3132 for (i = 1; i < ps->performance_level_count; i++) {
3133 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3134 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3135 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3136 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3137 }
3138 }
3139
3140 if (disable_mclk_switching) {
3141 mclk = ps->performance_levels[0].mclk;
3142 for (i = 1; i < ps->performance_level_count; i++) {
3143 if (mclk < ps->performance_levels[i].mclk)
3144 mclk = ps->performance_levels[i].mclk;
3145 }
3146 for (i = 0; i < ps->performance_level_count; i++) {
3147 ps->performance_levels[i].mclk = mclk;
3148 ps->performance_levels[i].vddci = vddci;
3149 }
3150 } else {
3151 for (i = 1; i < ps->performance_level_count; i++) {
3152 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3153 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3154 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3155 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3156 }
3157 }
3158
3159 for (i = 0; i < ps->performance_level_count; i++)
3160 btc_adjust_clock_combinations(rdev, max_limits,
3161 &ps->performance_levels[i]);
3162
3163 for (i = 0; i < ps->performance_level_count; i++) {
3164 if (ps->performance_levels[i].vddc < min_vce_voltage)
3165 ps->performance_levels[i].vddc = min_vce_voltage;
3166 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3167 ps->performance_levels[i].sclk,
3168 max_limits->vddc, &ps->performance_levels[i].vddc);
3169 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3170 ps->performance_levels[i].mclk,
3171 max_limits->vddci, &ps->performance_levels[i].vddci);
3172 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3173 ps->performance_levels[i].mclk,
3174 max_limits->vddc, &ps->performance_levels[i].vddc);
3175 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3176 rdev->clock.current_dispclk,
3177 max_limits->vddc, &ps->performance_levels[i].vddc);
3178 }
3179
3180 for (i = 0; i < ps->performance_level_count; i++) {
3181 btc_apply_voltage_delta_rules(rdev,
3182 max_limits->vddc, max_limits->vddci,
3183 &ps->performance_levels[i].vddc,
3184 &ps->performance_levels[i].vddci);
3185 }
3186
3187 ps->dc_compatible = true;
3188 for (i = 0; i < ps->performance_level_count; i++) {
3189 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3190 ps->dc_compatible = false;
3191 }
3192 }
3193
3194 #if 0
3195 static int si_read_smc_soft_register(struct radeon_device *rdev,
3196 u16 reg_offset, u32 *value)
3197 {
3198 struct si_power_info *si_pi = si_get_pi(rdev);
3199
3200 return si_read_smc_sram_dword(rdev,
3201 si_pi->soft_regs_start + reg_offset, value,
3202 si_pi->sram_end);
3203 }
3204 #endif
3205
3206 static int si_write_smc_soft_register(struct radeon_device *rdev,
3207 u16 reg_offset, u32 value)
3208 {
3209 struct si_power_info *si_pi = si_get_pi(rdev);
3210
3211 return si_write_smc_sram_dword(rdev,
3212 si_pi->soft_regs_start + reg_offset,
3213 value, si_pi->sram_end);
3214 }
3215
3216 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3217 {
3218 bool ret = false;
3219 u32 tmp, width, row, column, bank, density;
3220 bool is_memory_gddr5, is_special;
3221
3222 tmp = RREG32(MC_SEQ_MISC0);
3223 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3224 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3225 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3226
3227 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3228 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3229
3230 tmp = RREG32(MC_ARB_RAMCFG);
3231 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3232 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3233 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3234
3235 density = (1 << (row + column - 20 + bank)) * width;
3236
3237 if ((rdev->pdev->device == 0x6819) &&
3238 is_memory_gddr5 && is_special && (density == 0x400))
3239 ret = true;
3240
3241 return ret;
3242 }
3243
3244 static void si_get_leakage_vddc(struct radeon_device *rdev)
3245 {
3246 struct si_power_info *si_pi = si_get_pi(rdev);
3247 u16 vddc, count = 0;
3248 int i, ret;
3249
3250 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3251 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3252
3253 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3254 si_pi->leakage_voltage.entries[count].voltage = vddc;
3255 si_pi->leakage_voltage.entries[count].leakage_index =
3256 SISLANDS_LEAKAGE_INDEX0 + i;
3257 count++;
3258 }
3259 }
3260 si_pi->leakage_voltage.count = count;
3261 }
3262
3263 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3264 u32 index, u16 *leakage_voltage)
3265 {
3266 struct si_power_info *si_pi = si_get_pi(rdev);
3267 int i;
3268
3269 if (leakage_voltage == NULL)
3270 return -EINVAL;
3271
3272 if ((index & 0xff00) != 0xff00)
3273 return -EINVAL;
3274
3275 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3276 return -EINVAL;
3277
3278 if (index < SISLANDS_LEAKAGE_INDEX0)
3279 return -EINVAL;
3280
3281 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3282 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3283 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3284 return 0;
3285 }
3286 }
3287 return -EAGAIN;
3288 }
3289
3290 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3291 {
3292 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3293 bool want_thermal_protection;
3294 enum radeon_dpm_event_src dpm_event_src;
3295
3296 switch (sources) {
3297 case 0:
3298 default:
3299 want_thermal_protection = false;
3300 break;
3301 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3302 want_thermal_protection = true;
3303 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3304 break;
3305 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3306 want_thermal_protection = true;
3307 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3308 break;
3309 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3310 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3311 want_thermal_protection = true;
3312 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3313 break;
3314 }
3315
3316 if (want_thermal_protection) {
3317 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3318 if (pi->thermal_protection)
3319 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3320 } else {
3321 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3322 }
3323 }
3324
3325 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3326 enum radeon_dpm_auto_throttle_src source,
3327 bool enable)
3328 {
3329 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3330
3331 if (enable) {
3332 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3333 pi->active_auto_throttle_sources |= 1 << source;
3334 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3335 }
3336 } else {
3337 if (pi->active_auto_throttle_sources & (1 << source)) {
3338 pi->active_auto_throttle_sources &= ~(1 << source);
3339 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3340 }
3341 }
3342 }
3343
3344 static void si_start_dpm(struct radeon_device *rdev)
3345 {
3346 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3347 }
3348
3349 static void si_stop_dpm(struct radeon_device *rdev)
3350 {
3351 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3352 }
3353
3354 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3355 {
3356 if (enable)
3357 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3358 else
3359 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3360
3361 }
3362
3363 #if 0
3364 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3365 u32 thermal_level)
3366 {
3367 PPSMC_Result ret;
3368
3369 if (thermal_level == 0) {
3370 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3371 if (ret == PPSMC_Result_OK)
3372 return 0;
3373 else
3374 return -EINVAL;
3375 }
3376 return 0;
3377 }
3378
3379 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3380 {
3381 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3382 }
3383 #endif
3384
3385 #if 0
3386 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3387 {
3388 if (ac_power)
3389 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3390 0 : -EINVAL;
3391
3392 return 0;
3393 }
3394 #endif
3395
3396 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3397 PPSMC_Msg msg, u32 parameter)
3398 {
3399 WREG32(SMC_SCRATCH0, parameter);
3400 return si_send_msg_to_smc(rdev, msg);
3401 }
3402
3403 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3404 {
3405 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3406 return -EINVAL;
3407
3408 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3409 0 : -EINVAL;
3410 }
3411
3412 int si_dpm_force_performance_level(struct radeon_device *rdev,
3413 enum radeon_dpm_forced_level level)
3414 {
3415 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3416 struct ni_ps *ps = ni_get_ps(rps);
3417 u32 levels = ps->performance_level_count;
3418
3419 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3420 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3421 return -EINVAL;
3422
3423 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3424 return -EINVAL;
3425 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3426 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3427 return -EINVAL;
3428
3429 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3430 return -EINVAL;
3431 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3432 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3433 return -EINVAL;
3434
3435 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3436 return -EINVAL;
3437 }
3438
3439 rdev->pm.dpm.forced_level = level;
3440
3441 return 0;
3442 }
3443
3444 #if 0
3445 static int si_set_boot_state(struct radeon_device *rdev)
3446 {
3447 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3448 0 : -EINVAL;
3449 }
3450 #endif
3451
3452 static int si_set_sw_state(struct radeon_device *rdev)
3453 {
3454 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3455 0 : -EINVAL;
3456 }
3457
3458 static int si_halt_smc(struct radeon_device *rdev)
3459 {
3460 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3461 return -EINVAL;
3462
3463 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3464 0 : -EINVAL;
3465 }
3466
3467 static int si_resume_smc(struct radeon_device *rdev)
3468 {
3469 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3470 return -EINVAL;
3471
3472 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3473 0 : -EINVAL;
3474 }
3475
3476 static void si_dpm_start_smc(struct radeon_device *rdev)
3477 {
3478 si_program_jump_on_start(rdev);
3479 si_start_smc(rdev);
3480 si_start_smc_clock(rdev);
3481 }
3482
3483 static void si_dpm_stop_smc(struct radeon_device *rdev)
3484 {
3485 si_reset_smc(rdev);
3486 si_stop_smc_clock(rdev);
3487 }
3488
3489 static int si_process_firmware_header(struct radeon_device *rdev)
3490 {
3491 struct si_power_info *si_pi = si_get_pi(rdev);
3492 u32 tmp;
3493 int ret;
3494
3495 ret = si_read_smc_sram_dword(rdev,
3496 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3497 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3498 &tmp, si_pi->sram_end);
3499 if (ret)
3500 return ret;
3501
3502 si_pi->state_table_start = tmp;
3503
3504 ret = si_read_smc_sram_dword(rdev,
3505 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3506 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3507 &tmp, si_pi->sram_end);
3508 if (ret)
3509 return ret;
3510
3511 si_pi->soft_regs_start = tmp;
3512
3513 ret = si_read_smc_sram_dword(rdev,
3514 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3515 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3516 &tmp, si_pi->sram_end);
3517 if (ret)
3518 return ret;
3519
3520 si_pi->mc_reg_table_start = tmp;
3521
3522 ret = si_read_smc_sram_dword(rdev,
3523 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3524 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3525 &tmp, si_pi->sram_end);
3526 if (ret)
3527 return ret;
3528
3529 si_pi->fan_table_start = tmp;
3530
3531 ret = si_read_smc_sram_dword(rdev,
3532 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3533 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3534 &tmp, si_pi->sram_end);
3535 if (ret)
3536 return ret;
3537
3538 si_pi->arb_table_start = tmp;
3539
3540 ret = si_read_smc_sram_dword(rdev,
3541 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3542 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3543 &tmp, si_pi->sram_end);
3544 if (ret)
3545 return ret;
3546
3547 si_pi->cac_table_start = tmp;
3548
3549 ret = si_read_smc_sram_dword(rdev,
3550 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3551 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3552 &tmp, si_pi->sram_end);
3553 if (ret)
3554 return ret;
3555
3556 si_pi->dte_table_start = tmp;
3557
3558 ret = si_read_smc_sram_dword(rdev,
3559 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3560 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3561 &tmp, si_pi->sram_end);
3562 if (ret)
3563 return ret;
3564
3565 si_pi->spll_table_start = tmp;
3566
3567 ret = si_read_smc_sram_dword(rdev,
3568 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3569 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3570 &tmp, si_pi->sram_end);
3571 if (ret)
3572 return ret;
3573
3574 si_pi->papm_cfg_table_start = tmp;
3575
3576 return ret;
3577 }
3578
3579 static void si_read_clock_registers(struct radeon_device *rdev)
3580 {
3581 struct si_power_info *si_pi = si_get_pi(rdev);
3582
3583 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3584 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3585 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3586 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3587 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3588 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3589 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3590 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3591 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3592 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3593 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3594 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3595 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3596 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3597 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3598 }
3599
3600 static void si_enable_thermal_protection(struct radeon_device *rdev,
3601 bool enable)
3602 {
3603 if (enable)
3604 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3605 else
3606 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3607 }
3608
3609 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3610 {
3611 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3612 }
3613
3614 #if 0
3615 static int si_enter_ulp_state(struct radeon_device *rdev)
3616 {
3617 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3618
3619 udelay(25000);
3620
3621 return 0;
3622 }
3623
3624 static int si_exit_ulp_state(struct radeon_device *rdev)
3625 {
3626 int i;
3627
3628 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3629
3630 udelay(7000);
3631
3632 for (i = 0; i < rdev->usec_timeout; i++) {
3633 if (RREG32(SMC_RESP_0) == 1)
3634 break;
3635 udelay(1000);
3636 }
3637
3638 return 0;
3639 }
3640 #endif
3641
3642 static int si_notify_smc_display_change(struct radeon_device *rdev,
3643 bool has_display)
3644 {
3645 PPSMC_Msg msg = has_display ?
3646 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3647
3648 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3649 0 : -EINVAL;
3650 }
3651
3652 static void si_program_response_times(struct radeon_device *rdev)
3653 {
3654 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3655 u32 vddc_dly, acpi_dly, vbi_dly;
3656 u32 reference_clock;
3657
3658 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3659
3660 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3661 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3662
3663 if (voltage_response_time == 0)
3664 voltage_response_time = 1000;
3665
3666 acpi_delay_time = 15000;
3667 vbi_time_out = 100000;
3668
3669 reference_clock = radeon_get_xclk(rdev);
3670
3671 vddc_dly = (voltage_response_time * reference_clock) / 100;
3672 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3673 vbi_dly = (vbi_time_out * reference_clock) / 100;
3674
3675 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3676 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3677 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3679 }
3680
3681 static void si_program_ds_registers(struct radeon_device *rdev)
3682 {
3683 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3684 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3685
3686 if (eg_pi->sclk_deep_sleep) {
3687 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3688 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3689 ~AUTOSCALE_ON_SS_CLEAR);
3690 }
3691 }
3692
3693 static void si_program_display_gap(struct radeon_device *rdev)
3694 {
3695 u32 tmp, pipe;
3696 int i;
3697
3698 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3699 if (rdev->pm.dpm.new_active_crtc_count > 0)
3700 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3701 else
3702 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3703
3704 if (rdev->pm.dpm.new_active_crtc_count > 1)
3705 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3706 else
3707 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3708
3709 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3710
3711 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3712 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3713
3714 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3715 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3716 /* find the first active crtc */
3717 for (i = 0; i < rdev->num_crtc; i++) {
3718 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3719 break;
3720 }
3721 if (i == rdev->num_crtc)
3722 pipe = 0;
3723 else
3724 pipe = i;
3725
3726 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3727 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3728 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3729 }
3730
3731 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3732 * This can be a problem on PowerXpress systems or if you want to use the card
3733 * for offscreen rendering or compute if there are no crtcs enabled.
3734 */
3735 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3736 }
3737
3738 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3739 {
3740 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3741
3742 if (enable) {
3743 if (pi->sclk_ss)
3744 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3745 } else {
3746 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3747 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3748 }
3749 }
3750
3751 static void si_setup_bsp(struct radeon_device *rdev)
3752 {
3753 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3754 u32 xclk = radeon_get_xclk(rdev);
3755
3756 r600_calculate_u_and_p(pi->asi,
3757 xclk,
3758 16,
3759 &pi->bsp,
3760 &pi->bsu);
3761
3762 r600_calculate_u_and_p(pi->pasi,
3763 xclk,
3764 16,
3765 &pi->pbsp,
3766 &pi->pbsu);
3767
3768
3769 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3770 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3771
3772 WREG32(CG_BSP, pi->dsp);
3773 }
3774
3775 static void si_program_git(struct radeon_device *rdev)
3776 {
3777 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3778 }
3779
3780 static void si_program_tp(struct radeon_device *rdev)
3781 {
3782 int i;
3783 enum r600_td td = R600_TD_DFLT;
3784
3785 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3786 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3787
3788 if (td == R600_TD_AUTO)
3789 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3790 else
3791 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3792
3793 if (td == R600_TD_UP)
3794 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3795
3796 if (td == R600_TD_DOWN)
3797 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3798 }
3799
3800 static void si_program_tpp(struct radeon_device *rdev)
3801 {
3802 WREG32(CG_TPC, R600_TPC_DFLT);
3803 }
3804
3805 static void si_program_sstp(struct radeon_device *rdev)
3806 {
3807 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3808 }
3809
3810 static void si_enable_display_gap(struct radeon_device *rdev)
3811 {
3812 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3813
3814 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3815 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3816 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3817
3818 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3819 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3820 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3821 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3822 }
3823
3824 static void si_program_vc(struct radeon_device *rdev)
3825 {
3826 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3827
3828 WREG32(CG_FTV, pi->vrc);
3829 }
3830
3831 static void si_clear_vc(struct radeon_device *rdev)
3832 {
3833 WREG32(CG_FTV, 0);
3834 }
3835
3836 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3837 {
3838 u8 mc_para_index;
3839
3840 if (memory_clock < 10000)
3841 mc_para_index = 0;
3842 else if (memory_clock >= 80000)
3843 mc_para_index = 0x0f;
3844 else
3845 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3846 return mc_para_index;
3847 }
3848
3849 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3850 {
3851 u8 mc_para_index;
3852
3853 if (strobe_mode) {
3854 if (memory_clock < 12500)
3855 mc_para_index = 0x00;
3856 else if (memory_clock > 47500)
3857 mc_para_index = 0x0f;
3858 else
3859 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3860 } else {
3861 if (memory_clock < 65000)
3862 mc_para_index = 0x00;
3863 else if (memory_clock > 135000)
3864 mc_para_index = 0x0f;
3865 else
3866 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3867 }
3868 return mc_para_index;
3869 }
3870
3871 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3872 {
3873 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3874 bool strobe_mode = false;
3875 u8 result = 0;
3876
3877 if (mclk <= pi->mclk_strobe_mode_threshold)
3878 strobe_mode = true;
3879
3880 if (pi->mem_gddr5)
3881 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3882 else
3883 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3884
3885 if (strobe_mode)
3886 result |= SISLANDS_SMC_STROBE_ENABLE;
3887
3888 return result;
3889 }
3890
3891 static int si_upload_firmware(struct radeon_device *rdev)
3892 {
3893 struct si_power_info *si_pi = si_get_pi(rdev);
3894 int ret;
3895
3896 si_reset_smc(rdev);
3897 si_stop_smc_clock(rdev);
3898
3899 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3900
3901 return ret;
3902 }
3903
3904 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3905 const struct atom_voltage_table *table,
3906 const struct radeon_phase_shedding_limits_table *limits)
3907 {
3908 u32 data, num_bits, num_levels;
3909
3910 if ((table == NULL) || (limits == NULL))
3911 return false;
3912
3913 data = table->mask_low;
3914
3915 num_bits = hweight32(data);
3916
3917 if (num_bits == 0)
3918 return false;
3919
3920 num_levels = (1 << num_bits);
3921
3922 if (table->count != num_levels)
3923 return false;
3924
3925 if (limits->count != (num_levels - 1))
3926 return false;
3927
3928 return true;
3929 }
3930
3931 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3932 u32 max_voltage_steps,
3933 struct atom_voltage_table *voltage_table)
3934 {
3935 unsigned int i, diff;
3936
3937 if (voltage_table->count <= max_voltage_steps)
3938 return;
3939
3940 diff = voltage_table->count - max_voltage_steps;
3941
3942 for (i= 0; i < max_voltage_steps; i++)
3943 voltage_table->entries[i] = voltage_table->entries[i + diff];
3944
3945 voltage_table->count = max_voltage_steps;
3946 }
3947
3948 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3949 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3950 struct atom_voltage_table *voltage_table)
3951 {
3952 u32 i;
3953
3954 if (voltage_dependency_table == NULL)
3955 return -EINVAL;
3956
3957 voltage_table->mask_low = 0;
3958 voltage_table->phase_delay = 0;
3959
3960 voltage_table->count = voltage_dependency_table->count;
3961 for (i = 0; i < voltage_table->count; i++) {
3962 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3963 voltage_table->entries[i].smio_low = 0;
3964 }
3965
3966 return 0;
3967 }
3968
3969 static int si_construct_voltage_tables(struct radeon_device *rdev)
3970 {
3971 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3972 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3973 struct si_power_info *si_pi = si_get_pi(rdev);
3974 int ret;
3975
3976 if (pi->voltage_control) {
3977 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3978 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3979 if (ret)
3980 return ret;
3981
3982 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3983 si_trim_voltage_table_to_fit_state_table(rdev,
3984 SISLANDS_MAX_NO_VREG_STEPS,
3985 &eg_pi->vddc_voltage_table);
3986 } else if (si_pi->voltage_control_svi2) {
3987 ret = si_get_svi2_voltage_table(rdev,
3988 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3989 &eg_pi->vddc_voltage_table);
3990 if (ret)
3991 return ret;
3992 } else {
3993 return -EINVAL;
3994 }
3995
3996 if (eg_pi->vddci_control) {
3997 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3998 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3999 if (ret)
4000 return ret;
4001
4002 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4003 si_trim_voltage_table_to_fit_state_table(rdev,
4004 SISLANDS_MAX_NO_VREG_STEPS,
4005 &eg_pi->vddci_voltage_table);
4006 }
4007 if (si_pi->vddci_control_svi2) {
4008 ret = si_get_svi2_voltage_table(rdev,
4009 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4010 &eg_pi->vddci_voltage_table);
4011 if (ret)
4012 return ret;
4013 }
4014
4015 if (pi->mvdd_control) {
4016 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4017 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4018
4019 if (ret) {
4020 pi->mvdd_control = false;
4021 return ret;
4022 }
4023
4024 if (si_pi->mvdd_voltage_table.count == 0) {
4025 pi->mvdd_control = false;
4026 return -EINVAL;
4027 }
4028
4029 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4030 si_trim_voltage_table_to_fit_state_table(rdev,
4031 SISLANDS_MAX_NO_VREG_STEPS,
4032 &si_pi->mvdd_voltage_table);
4033 }
4034
4035 if (si_pi->vddc_phase_shed_control) {
4036 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4037 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4038 if (ret)
4039 si_pi->vddc_phase_shed_control = false;
4040
4041 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4042 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4043 si_pi->vddc_phase_shed_control = false;
4044 }
4045
4046 return 0;
4047 }
4048
4049 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4050 const struct atom_voltage_table *voltage_table,
4051 SISLANDS_SMC_STATETABLE *table)
4052 {
4053 unsigned int i;
4054
4055 for (i = 0; i < voltage_table->count; i++)
4056 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4057 }
4058
4059 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4060 SISLANDS_SMC_STATETABLE *table)
4061 {
4062 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4063 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4064 struct si_power_info *si_pi = si_get_pi(rdev);
4065 u8 i;
4066
4067 if (si_pi->voltage_control_svi2) {
4068 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4069 si_pi->svc_gpio_id);
4070 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4071 si_pi->svd_gpio_id);
4072 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4073 2);
4074 } else {
4075 if (eg_pi->vddc_voltage_table.count) {
4076 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4077 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4078 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4079
4080 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4081 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4082 table->maxVDDCIndexInPPTable = i;
4083 break;
4084 }
4085 }
4086 }
4087
4088 if (eg_pi->vddci_voltage_table.count) {
4089 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4090
4091 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4092 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4093 }
4094
4095
4096 if (si_pi->mvdd_voltage_table.count) {
4097 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4098
4099 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4100 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4101 }
4102
4103 if (si_pi->vddc_phase_shed_control) {
4104 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4105 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4106 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4107
4108 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4109 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4110
4111 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4112 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4113 } else {
4114 si_pi->vddc_phase_shed_control = false;
4115 }
4116 }
4117 }
4118
4119 return 0;
4120 }
4121
4122 static int si_populate_voltage_value(struct radeon_device *rdev,
4123 const struct atom_voltage_table *table,
4124 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4125 {
4126 unsigned int i;
4127
4128 for (i = 0; i < table->count; i++) {
4129 if (value <= table->entries[i].value) {
4130 voltage->index = (u8)i;
4131 voltage->value = cpu_to_be16(table->entries[i].value);
4132 break;
4133 }
4134 }
4135
4136 if (i >= table->count)
4137 return -EINVAL;
4138
4139 return 0;
4140 }
4141
4142 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4143 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4144 {
4145 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4146 struct si_power_info *si_pi = si_get_pi(rdev);
4147
4148 if (pi->mvdd_control) {
4149 if (mclk <= pi->mvdd_split_frequency)
4150 voltage->index = 0;
4151 else
4152 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4153
4154 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4155 }
4156 return 0;
4157 }
4158
4159 static int si_get_std_voltage_value(struct radeon_device *rdev,
4160 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4161 u16 *std_voltage)
4162 {
4163 u16 v_index;
4164 bool voltage_found = false;
4165 *std_voltage = be16_to_cpu(voltage->value);
4166
4167 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4168 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4169 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4170 return -EINVAL;
4171
4172 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4173 if (be16_to_cpu(voltage->value) ==
4174 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4175 voltage_found = true;
4176 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4177 *std_voltage =
4178 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4179 else
4180 *std_voltage =
4181 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4182 break;
4183 }
4184 }
4185
4186 if (!voltage_found) {
4187 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4188 if (be16_to_cpu(voltage->value) <=
4189 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4190 voltage_found = true;
4191 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4192 *std_voltage =
4193 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4194 else
4195 *std_voltage =
4196 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4197 break;
4198 }
4199 }
4200 }
4201 } else {
4202 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4203 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4204 }
4205 }
4206
4207 return 0;
4208 }
4209
4210 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4211 u16 value, u8 index,
4212 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4213 {
4214 voltage->index = index;
4215 voltage->value = cpu_to_be16(value);
4216
4217 return 0;
4218 }
4219
4220 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4221 const struct radeon_phase_shedding_limits_table *limits,
4222 u16 voltage, u32 sclk, u32 mclk,
4223 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4224 {
4225 unsigned int i;
4226
4227 for (i = 0; i < limits->count; i++) {
4228 if ((voltage <= limits->entries[i].voltage) &&
4229 (sclk <= limits->entries[i].sclk) &&
4230 (mclk <= limits->entries[i].mclk))
4231 break;
4232 }
4233
4234 smc_voltage->phase_settings = (u8)i;
4235
4236 return 0;
4237 }
4238
4239 static int si_init_arb_table_index(struct radeon_device *rdev)
4240 {
4241 struct si_power_info *si_pi = si_get_pi(rdev);
4242 u32 tmp;
4243 int ret;
4244
4245 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4246 if (ret)
4247 return ret;
4248
4249 tmp &= 0x00FFFFFF;
4250 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4251
4252 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4253 }
4254
4255 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4256 {
4257 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4258 }
4259
4260 static int si_reset_to_default(struct radeon_device *rdev)
4261 {
4262 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4263 0 : -EINVAL;
4264 }
4265
4266 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4267 {
4268 struct si_power_info *si_pi = si_get_pi(rdev);
4269 u32 tmp;
4270 int ret;
4271
4272 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4273 &tmp, si_pi->sram_end);
4274 if (ret)
4275 return ret;
4276
4277 tmp = (tmp >> 24) & 0xff;
4278
4279 if (tmp == MC_CG_ARB_FREQ_F0)
4280 return 0;
4281
4282 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4283 }
4284
4285 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4286 u32 engine_clock)
4287 {
4288 u32 dram_rows;
4289 u32 dram_refresh_rate;
4290 u32 mc_arb_rfsh_rate;
4291 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4292
4293 if (tmp >= 4)
4294 dram_rows = 16384;
4295 else
4296 dram_rows = 1 << (tmp + 10);
4297
4298 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4299 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4300
4301 return mc_arb_rfsh_rate;
4302 }
4303
4304 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4305 struct rv7xx_pl *pl,
4306 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4307 {
4308 u32 dram_timing;
4309 u32 dram_timing2;
4310 u32 burst_time;
4311
4312 arb_regs->mc_arb_rfsh_rate =
4313 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4314
4315 radeon_atom_set_engine_dram_timings(rdev,
4316 pl->sclk,
4317 pl->mclk);
4318
4319 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4320 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4321 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4322
4323 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4324 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4325 arb_regs->mc_arb_burst_time = (u8)burst_time;
4326
4327 return 0;
4328 }
4329
4330 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4331 struct radeon_ps *radeon_state,
4332 unsigned int first_arb_set)
4333 {
4334 struct si_power_info *si_pi = si_get_pi(rdev);
4335 struct ni_ps *state = ni_get_ps(radeon_state);
4336 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4337 int i, ret = 0;
4338
4339 for (i = 0; i < state->performance_level_count; i++) {
4340 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4341 if (ret)
4342 break;
4343 ret = si_copy_bytes_to_smc(rdev,
4344 si_pi->arb_table_start +
4345 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4346 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4347 (u8 *)&arb_regs,
4348 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4349 si_pi->sram_end);
4350 if (ret)
4351 break;
4352 }
4353
4354 return ret;
4355 }
4356
4357 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4358 struct radeon_ps *radeon_new_state)
4359 {
4360 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4361 SISLANDS_DRIVER_STATE_ARB_INDEX);
4362 }
4363
4364 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4365 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4366 {
4367 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4368 struct si_power_info *si_pi = si_get_pi(rdev);
4369
4370 if (pi->mvdd_control)
4371 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4372 si_pi->mvdd_bootup_value, voltage);
4373
4374 return 0;
4375 }
4376
4377 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4378 struct radeon_ps *radeon_initial_state,
4379 SISLANDS_SMC_STATETABLE *table)
4380 {
4381 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4382 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4383 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4384 struct si_power_info *si_pi = si_get_pi(rdev);
4385 u32 reg;
4386 int ret;
4387
4388 table->initialState.levels[0].mclk.vDLL_CNTL =
4389 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4390 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4391 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4392 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4393 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4394 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4395 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4396 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4397 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4398 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4399 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4400 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4401 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4402 table->initialState.levels[0].mclk.vMPLL_SS =
4403 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4404 table->initialState.levels[0].mclk.vMPLL_SS2 =
4405 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4406
4407 table->initialState.levels[0].mclk.mclk_value =
4408 cpu_to_be32(initial_state->performance_levels[0].mclk);
4409
4410 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4411 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4412 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4413 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4414 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4415 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4416 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4417 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4418 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4419 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4420 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4421 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4422
4423 table->initialState.levels[0].sclk.sclk_value =
4424 cpu_to_be32(initial_state->performance_levels[0].sclk);
4425
4426 table->initialState.levels[0].arbRefreshState =
4427 SISLANDS_INITIAL_STATE_ARB_INDEX;
4428
4429 table->initialState.levels[0].ACIndex = 0;
4430
4431 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4432 initial_state->performance_levels[0].vddc,
4433 &table->initialState.levels[0].vddc);
4434
4435 if (!ret) {
4436 u16 std_vddc;
4437
4438 ret = si_get_std_voltage_value(rdev,
4439 &table->initialState.levels[0].vddc,
4440 &std_vddc);
4441 if (!ret)
4442 si_populate_std_voltage_value(rdev, std_vddc,
4443 table->initialState.levels[0].vddc.index,
4444 &table->initialState.levels[0].std_vddc);
4445 }
4446
4447 if (eg_pi->vddci_control)
4448 si_populate_voltage_value(rdev,
4449 &eg_pi->vddci_voltage_table,
4450 initial_state->performance_levels[0].vddci,
4451 &table->initialState.levels[0].vddci);
4452
4453 if (si_pi->vddc_phase_shed_control)
4454 si_populate_phase_shedding_value(rdev,
4455 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4456 initial_state->performance_levels[0].vddc,
4457 initial_state->performance_levels[0].sclk,
4458 initial_state->performance_levels[0].mclk,
4459 &table->initialState.levels[0].vddc);
4460
4461 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4462
4463 reg = CG_R(0xffff) | CG_L(0);
4464 table->initialState.levels[0].aT = cpu_to_be32(reg);
4465
4466 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4467
4468 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4469
4470 if (pi->mem_gddr5) {
4471 table->initialState.levels[0].strobeMode =
4472 si_get_strobe_mode_settings(rdev,
4473 initial_state->performance_levels[0].mclk);
4474
4475 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4476 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4477 else
4478 table->initialState.levels[0].mcFlags = 0;
4479 }
4480
4481 table->initialState.levelCount = 1;
4482
4483 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4484
4485 table->initialState.levels[0].dpm2.MaxPS = 0;
4486 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4487 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4488 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4489 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4490
4491 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4492 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4493
4494 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4495 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4496
4497 return 0;
4498 }
4499
4500 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4501 SISLANDS_SMC_STATETABLE *table)
4502 {
4503 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4504 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4505 struct si_power_info *si_pi = si_get_pi(rdev);
4506 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4507 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4508 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4509 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4510 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4511 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4512 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4513 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4514 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4515 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4516 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4517 u32 reg;
4518 int ret;
4519
4520 table->ACPIState = table->initialState;
4521
4522 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4523
4524 if (pi->acpi_vddc) {
4525 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4526 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4527 if (!ret) {
4528 u16 std_vddc;
4529
4530 ret = si_get_std_voltage_value(rdev,
4531 &table->ACPIState.levels[0].vddc, &std_vddc);
4532 if (!ret)
4533 si_populate_std_voltage_value(rdev, std_vddc,
4534 table->ACPIState.levels[0].vddc.index,
4535 &table->ACPIState.levels[0].std_vddc);
4536 }
4537 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4538
4539 if (si_pi->vddc_phase_shed_control) {
4540 si_populate_phase_shedding_value(rdev,
4541 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4542 pi->acpi_vddc,
4543 0,
4544 0,
4545 &table->ACPIState.levels[0].vddc);
4546 }
4547 } else {
4548 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4549 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4550 if (!ret) {
4551 u16 std_vddc;
4552
4553 ret = si_get_std_voltage_value(rdev,
4554 &table->ACPIState.levels[0].vddc, &std_vddc);
4555
4556 if (!ret)
4557 si_populate_std_voltage_value(rdev, std_vddc,
4558 table->ACPIState.levels[0].vddc.index,
4559 &table->ACPIState.levels[0].std_vddc);
4560 }
4561 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4562 si_pi->sys_pcie_mask,
4563 si_pi->boot_pcie_gen,
4564 RADEON_PCIE_GEN1);
4565
4566 if (si_pi->vddc_phase_shed_control)
4567 si_populate_phase_shedding_value(rdev,
4568 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4569 pi->min_vddc_in_table,
4570 0,
4571 0,
4572 &table->ACPIState.levels[0].vddc);
4573 }
4574
4575 if (pi->acpi_vddc) {
4576 if (eg_pi->acpi_vddci)
4577 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4578 eg_pi->acpi_vddci,
4579 &table->ACPIState.levels[0].vddci);
4580 }
4581
4582 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4583 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4584
4585 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4586
4587 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4588 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4589
4590 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4591 cpu_to_be32(dll_cntl);
4592 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4593 cpu_to_be32(mclk_pwrmgt_cntl);
4594 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4595 cpu_to_be32(mpll_ad_func_cntl);
4596 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4597 cpu_to_be32(mpll_dq_func_cntl);
4598 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4599 cpu_to_be32(mpll_func_cntl);
4600 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4601 cpu_to_be32(mpll_func_cntl_1);
4602 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4603 cpu_to_be32(mpll_func_cntl_2);
4604 table->ACPIState.levels[0].mclk.vMPLL_SS =
4605 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4606 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4607 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4608
4609 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4610 cpu_to_be32(spll_func_cntl);
4611 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4612 cpu_to_be32(spll_func_cntl_2);
4613 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4614 cpu_to_be32(spll_func_cntl_3);
4615 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4616 cpu_to_be32(spll_func_cntl_4);
4617
4618 table->ACPIState.levels[0].mclk.mclk_value = 0;
4619 table->ACPIState.levels[0].sclk.sclk_value = 0;
4620
4621 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4622
4623 if (eg_pi->dynamic_ac_timing)
4624 table->ACPIState.levels[0].ACIndex = 0;
4625
4626 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4627 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4628 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4629 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4630 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4631
4632 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4633 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4634
4635 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4636 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4637
4638 return 0;
4639 }
4640
4641 static int si_populate_ulv_state(struct radeon_device *rdev,
4642 SISLANDS_SMC_SWSTATE *state)
4643 {
4644 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4645 struct si_power_info *si_pi = si_get_pi(rdev);
4646 struct si_ulv_param *ulv = &si_pi->ulv;
4647 u32 sclk_in_sr = 1350; /* ??? */
4648 int ret;
4649
4650 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4651 &state->levels[0]);
4652 if (!ret) {
4653 if (eg_pi->sclk_deep_sleep) {
4654 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4655 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4656 else
4657 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4658 }
4659 if (ulv->one_pcie_lane_in_ulv)
4660 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4661 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4662 state->levels[0].ACIndex = 1;
4663 state->levels[0].std_vddc = state->levels[0].vddc;
4664 state->levelCount = 1;
4665
4666 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4667 }
4668
4669 return ret;
4670 }
4671
4672 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4673 {
4674 struct si_power_info *si_pi = si_get_pi(rdev);
4675 struct si_ulv_param *ulv = &si_pi->ulv;
4676 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4677 int ret;
4678
4679 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4680 &arb_regs);
4681 if (ret)
4682 return ret;
4683
4684 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4685 ulv->volt_change_delay);
4686
4687 ret = si_copy_bytes_to_smc(rdev,
4688 si_pi->arb_table_start +
4689 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4690 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4691 (u8 *)&arb_regs,
4692 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4693 si_pi->sram_end);
4694
4695 return ret;
4696 }
4697
4698 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4699 {
4700 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4701
4702 pi->mvdd_split_frequency = 30000;
4703 }
4704
4705 static int si_init_smc_table(struct radeon_device *rdev)
4706 {
4707 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4708 struct si_power_info *si_pi = si_get_pi(rdev);
4709 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4710 const struct si_ulv_param *ulv = &si_pi->ulv;
4711 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4712 int ret;
4713 u32 lane_width;
4714 u32 vr_hot_gpio;
4715
4716 si_populate_smc_voltage_tables(rdev, table);
4717
4718 switch (rdev->pm.int_thermal_type) {
4719 case THERMAL_TYPE_SI:
4720 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4721 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4722 break;
4723 case THERMAL_TYPE_NONE:
4724 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4725 break;
4726 default:
4727 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4728 break;
4729 }
4730
4731 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4732 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4733
4734 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4735 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4736 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4737 }
4738
4739 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4740 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4741
4742 if (pi->mem_gddr5)
4743 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4744
4745 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4746 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4747
4748 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4749 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4750 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4751 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4752 vr_hot_gpio);
4753 }
4754
4755 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4756 if (ret)
4757 return ret;
4758
4759 ret = si_populate_smc_acpi_state(rdev, table);
4760 if (ret)
4761 return ret;
4762
4763 table->driverState = table->initialState;
4764
4765 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4766 SISLANDS_INITIAL_STATE_ARB_INDEX);
4767 if (ret)
4768 return ret;
4769
4770 if (ulv->supported && ulv->pl.vddc) {
4771 ret = si_populate_ulv_state(rdev, &table->ULVState);
4772 if (ret)
4773 return ret;
4774
4775 ret = si_program_ulv_memory_timing_parameters(rdev);
4776 if (ret)
4777 return ret;
4778
4779 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4780 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4781
4782 lane_width = radeon_get_pcie_lanes(rdev);
4783 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4784 } else {
4785 table->ULVState = table->initialState;
4786 }
4787
4788 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4789 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4790 si_pi->sram_end);
4791 }
4792
4793 static int si_calculate_sclk_params(struct radeon_device *rdev,
4794 u32 engine_clock,
4795 SISLANDS_SMC_SCLK_VALUE *sclk)
4796 {
4797 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4798 struct si_power_info *si_pi = si_get_pi(rdev);
4799 struct atom_clock_dividers dividers;
4800 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4801 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4802 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4803 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4804 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4805 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4806 u64 tmp;
4807 u32 reference_clock = rdev->clock.spll.reference_freq;
4808 u32 reference_divider;
4809 u32 fbdiv;
4810 int ret;
4811
4812 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4813 engine_clock, false, &dividers);
4814 if (ret)
4815 return ret;
4816
4817 reference_divider = 1 + dividers.ref_div;
4818
4819 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4820 do_div(tmp, reference_clock);
4821 fbdiv = (u32) tmp;
4822
4823 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4824 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4825 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4826
4827 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4828 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4829
4830 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4831 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4832 spll_func_cntl_3 |= SPLL_DITHEN;
4833
4834 if (pi->sclk_ss) {
4835 struct radeon_atom_ss ss;
4836 u32 vco_freq = engine_clock * dividers.post_div;
4837
4838 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4839 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4840 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4841 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4842
4843 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4844 cg_spll_spread_spectrum |= CLK_S(clk_s);
4845 cg_spll_spread_spectrum |= SSEN;
4846
4847 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4848 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4849 }
4850 }
4851
4852 sclk->sclk_value = engine_clock;
4853 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4854 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4855 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4856 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4857 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4858 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4859
4860 return 0;
4861 }
4862
4863 static int si_populate_sclk_value(struct radeon_device *rdev,
4864 u32 engine_clock,
4865 SISLANDS_SMC_SCLK_VALUE *sclk)
4866 {
4867 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4868 int ret;
4869
4870 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4871 if (!ret) {
4872 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4873 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4874 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4875 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4876 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4877 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4878 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4879 }
4880
4881 return ret;
4882 }
4883
4884 static int si_populate_mclk_value(struct radeon_device *rdev,
4885 u32 engine_clock,
4886 u32 memory_clock,
4887 SISLANDS_SMC_MCLK_VALUE *mclk,
4888 bool strobe_mode,
4889 bool dll_state_on)
4890 {
4891 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4892 struct si_power_info *si_pi = si_get_pi(rdev);
4893 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4894 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4895 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4896 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4897 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4898 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4899 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4900 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4901 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4902 struct atom_mpll_param mpll_param;
4903 int ret;
4904
4905 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4906 if (ret)
4907 return ret;
4908
4909 mpll_func_cntl &= ~BWCTRL_MASK;
4910 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4911
4912 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4913 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4914 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4915
4916 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4917 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4918
4919 if (pi->mem_gddr5) {
4920 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4921 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4922 YCLK_POST_DIV(mpll_param.post_div);
4923 }
4924
4925 if (pi->mclk_ss) {
4926 struct radeon_atom_ss ss;
4927 u32 freq_nom;
4928 u32 tmp;
4929 u32 reference_clock = rdev->clock.mpll.reference_freq;
4930
4931 if (pi->mem_gddr5)
4932 freq_nom = memory_clock * 4;
4933 else
4934 freq_nom = memory_clock * 2;
4935
4936 tmp = freq_nom / reference_clock;
4937 tmp = tmp * tmp;
4938 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4939 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4940 u32 clks = reference_clock * 5 / ss.rate;
4941 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4942
4943 mpll_ss1 &= ~CLKV_MASK;
4944 mpll_ss1 |= CLKV(clkv);
4945
4946 mpll_ss2 &= ~CLKS_MASK;
4947 mpll_ss2 |= CLKS(clks);
4948 }
4949 }
4950
4951 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4952 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4953
4954 if (dll_state_on)
4955 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4956 else
4957 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4958
4959 mclk->mclk_value = cpu_to_be32(memory_clock);
4960 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4961 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4962 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4963 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4964 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4965 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4966 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4967 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4968 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4969
4970 return 0;
4971 }
4972
4973 static void si_populate_smc_sp(struct radeon_device *rdev,
4974 struct radeon_ps *radeon_state,
4975 SISLANDS_SMC_SWSTATE *smc_state)
4976 {
4977 struct ni_ps *ps = ni_get_ps(radeon_state);
4978 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4979 int i;
4980
4981 for (i = 0; i < ps->performance_level_count - 1; i++)
4982 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4983
4984 smc_state->levels[ps->performance_level_count - 1].bSP =
4985 cpu_to_be32(pi->psp);
4986 }
4987
4988 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4989 struct rv7xx_pl *pl,
4990 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4991 {
4992 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4993 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4994 struct si_power_info *si_pi = si_get_pi(rdev);
4995 int ret;
4996 bool dll_state_on;
4997 u16 std_vddc;
4998 bool gmc_pg = false;
4999
5000 if (eg_pi->pcie_performance_request &&
5001 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5002 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5003 else
5004 level->gen2PCIE = (u8)pl->pcie_gen;
5005
5006 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5007 if (ret)
5008 return ret;
5009
5010 level->mcFlags = 0;
5011
5012 if (pi->mclk_stutter_mode_threshold &&
5013 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5014 !eg_pi->uvd_enabled &&
5015 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5016 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5017 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5018
5019 if (gmc_pg)
5020 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5021 }
5022
5023 if (pi->mem_gddr5) {
5024 if (pl->mclk > pi->mclk_edc_enable_threshold)
5025 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5026
5027 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5028 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5029
5030 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5031
5032 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5033 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5034 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5035 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5036 else
5037 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5038 } else {
5039 dll_state_on = false;
5040 }
5041 } else {
5042 level->strobeMode = si_get_strobe_mode_settings(rdev,
5043 pl->mclk);
5044
5045 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5046 }
5047
5048 ret = si_populate_mclk_value(rdev,
5049 pl->sclk,
5050 pl->mclk,
5051 &level->mclk,
5052 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5053 if (ret)
5054 return ret;
5055
5056 ret = si_populate_voltage_value(rdev,
5057 &eg_pi->vddc_voltage_table,
5058 pl->vddc, &level->vddc);
5059 if (ret)
5060 return ret;
5061
5062
5063 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5064 if (ret)
5065 return ret;
5066
5067 ret = si_populate_std_voltage_value(rdev, std_vddc,
5068 level->vddc.index, &level->std_vddc);
5069 if (ret)
5070 return ret;
5071
5072 if (eg_pi->vddci_control) {
5073 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5074 pl->vddci, &level->vddci);
5075 if (ret)
5076 return ret;
5077 }
5078
5079 if (si_pi->vddc_phase_shed_control) {
5080 ret = si_populate_phase_shedding_value(rdev,
5081 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5082 pl->vddc,
5083 pl->sclk,
5084 pl->mclk,
5085 &level->vddc);
5086 if (ret)
5087 return ret;
5088 }
5089
5090 level->MaxPoweredUpCU = si_pi->max_cu;
5091
5092 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5093
5094 return ret;
5095 }
5096
5097 static int si_populate_smc_t(struct radeon_device *rdev,
5098 struct radeon_ps *radeon_state,
5099 SISLANDS_SMC_SWSTATE *smc_state)
5100 {
5101 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5102 struct ni_ps *state = ni_get_ps(radeon_state);
5103 u32 a_t;
5104 u32 t_l, t_h;
5105 u32 high_bsp;
5106 int i, ret;
5107
5108 if (state->performance_level_count >= 9)
5109 return -EINVAL;
5110
5111 if (state->performance_level_count < 2) {
5112 a_t = CG_R(0xffff) | CG_L(0);
5113 smc_state->levels[0].aT = cpu_to_be32(a_t);
5114 return 0;
5115 }
5116
5117 smc_state->levels[0].aT = cpu_to_be32(0);
5118
5119 for (i = 0; i <= state->performance_level_count - 2; i++) {
5120 ret = r600_calculate_at(
5121 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5122 100 * R600_AH_DFLT,
5123 state->performance_levels[i + 1].sclk,
5124 state->performance_levels[i].sclk,
5125 &t_l,
5126 &t_h);
5127
5128 if (ret) {
5129 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5130 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5131 }
5132
5133 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5134 a_t |= CG_R(t_l * pi->bsp / 20000);
5135 smc_state->levels[i].aT = cpu_to_be32(a_t);
5136
5137 high_bsp = (i == state->performance_level_count - 2) ?
5138 pi->pbsp : pi->bsp;
5139 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5140 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5141 }
5142
5143 return 0;
5144 }
5145
5146 static int si_disable_ulv(struct radeon_device *rdev)
5147 {
5148 struct si_power_info *si_pi = si_get_pi(rdev);
5149 struct si_ulv_param *ulv = &si_pi->ulv;
5150
5151 if (ulv->supported)
5152 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5153 0 : -EINVAL;
5154
5155 return 0;
5156 }
5157
5158 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5159 struct radeon_ps *radeon_state)
5160 {
5161 const struct si_power_info *si_pi = si_get_pi(rdev);
5162 const struct si_ulv_param *ulv = &si_pi->ulv;
5163 const struct ni_ps *state = ni_get_ps(radeon_state);
5164 int i;
5165
5166 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5167 return false;
5168
5169 /* XXX validate against display requirements! */
5170
5171 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5172 if (rdev->clock.current_dispclk <=
5173 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5174 if (ulv->pl.vddc <
5175 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5176 return false;
5177 }
5178 }
5179
5180 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5181 return false;
5182
5183 return true;
5184 }
5185
5186 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5187 struct radeon_ps *radeon_new_state)
5188 {
5189 const struct si_power_info *si_pi = si_get_pi(rdev);
5190 const struct si_ulv_param *ulv = &si_pi->ulv;
5191
5192 if (ulv->supported) {
5193 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5194 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5195 0 : -EINVAL;
5196 }
5197 return 0;
5198 }
5199
5200 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5201 struct radeon_ps *radeon_state,
5202 SISLANDS_SMC_SWSTATE *smc_state)
5203 {
5204 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5205 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5206 struct si_power_info *si_pi = si_get_pi(rdev);
5207 struct ni_ps *state = ni_get_ps(radeon_state);
5208 int i, ret;
5209 u32 threshold;
5210 u32 sclk_in_sr = 1350; /* ??? */
5211
5212 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5213 return -EINVAL;
5214
5215 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5216
5217 if (radeon_state->vclk && radeon_state->dclk) {
5218 eg_pi->uvd_enabled = true;
5219 if (eg_pi->smu_uvd_hs)
5220 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5221 } else {
5222 eg_pi->uvd_enabled = false;
5223 }
5224
5225 if (state->dc_compatible)
5226 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5227
5228 smc_state->levelCount = 0;
5229 for (i = 0; i < state->performance_level_count; i++) {
5230 if (eg_pi->sclk_deep_sleep) {
5231 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5232 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5233 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5234 else
5235 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5236 }
5237 }
5238
5239 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5240 &smc_state->levels[i]);
5241 smc_state->levels[i].arbRefreshState =
5242 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5243
5244 if (ret)
5245 return ret;
5246
5247 if (ni_pi->enable_power_containment)
5248 smc_state->levels[i].displayWatermark =
5249 (state->performance_levels[i].sclk < threshold) ?
5250 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5251 else
5252 smc_state->levels[i].displayWatermark = (i < 2) ?
5253 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5254
5255 if (eg_pi->dynamic_ac_timing)
5256 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5257 else
5258 smc_state->levels[i].ACIndex = 0;
5259
5260 smc_state->levelCount++;
5261 }
5262
5263 si_write_smc_soft_register(rdev,
5264 SI_SMC_SOFT_REGISTER_watermark_threshold,
5265 threshold / 512);
5266
5267 si_populate_smc_sp(rdev, radeon_state, smc_state);
5268
5269 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5270 if (ret)
5271 ni_pi->enable_power_containment = false;
5272
5273 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5274 if (ret)
5275 ni_pi->enable_sq_ramping = false;
5276
5277 return si_populate_smc_t(rdev, radeon_state, smc_state);
5278 }
5279
5280 static int si_upload_sw_state(struct radeon_device *rdev,
5281 struct radeon_ps *radeon_new_state)
5282 {
5283 struct si_power_info *si_pi = si_get_pi(rdev);
5284 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5285 int ret;
5286 u32 address = si_pi->state_table_start +
5287 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5288 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5289 ((new_state->performance_level_count - 1) *
5290 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5291 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5292
5293 memset(smc_state, 0, state_size);
5294
5295 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5296 if (ret)
5297 return ret;
5298
5299 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5300 state_size, si_pi->sram_end);
5301
5302 return ret;
5303 }
5304
5305 static int si_upload_ulv_state(struct radeon_device *rdev)
5306 {
5307 struct si_power_info *si_pi = si_get_pi(rdev);
5308 struct si_ulv_param *ulv = &si_pi->ulv;
5309 int ret = 0;
5310
5311 if (ulv->supported && ulv->pl.vddc) {
5312 u32 address = si_pi->state_table_start +
5313 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5314 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5315 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5316
5317 memset(smc_state, 0, state_size);
5318
5319 ret = si_populate_ulv_state(rdev, smc_state);
5320 if (!ret)
5321 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5322 state_size, si_pi->sram_end);
5323 }
5324
5325 return ret;
5326 }
5327
5328 static int si_upload_smc_data(struct radeon_device *rdev)
5329 {
5330 struct radeon_crtc *radeon_crtc = NULL;
5331 int i;
5332
5333 if (rdev->pm.dpm.new_active_crtc_count == 0)
5334 return 0;
5335
5336 for (i = 0; i < rdev->num_crtc; i++) {
5337 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5338 radeon_crtc = rdev->mode_info.crtcs[i];
5339 break;
5340 }
5341 }
5342
5343 if (radeon_crtc == NULL)
5344 return 0;
5345
5346 if (radeon_crtc->line_time <= 0)
5347 return 0;
5348
5349 if (si_write_smc_soft_register(rdev,
5350 SI_SMC_SOFT_REGISTER_crtc_index,
5351 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5352 return 0;
5353
5354 if (si_write_smc_soft_register(rdev,
5355 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5356 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5357 return 0;
5358
5359 if (si_write_smc_soft_register(rdev,
5360 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5361 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5362 return 0;
5363
5364 return 0;
5365 }
5366
5367 static int si_set_mc_special_registers(struct radeon_device *rdev,
5368 struct si_mc_reg_table *table)
5369 {
5370 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5371 u8 i, j, k;
5372 u32 temp_reg;
5373
5374 for (i = 0, j = table->last; i < table->last; i++) {
5375 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5376 return -EINVAL;
5377 switch (table->mc_reg_address[i].s1 << 2) {
5378 case MC_SEQ_MISC1:
5379 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5380 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5381 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5382 for (k = 0; k < table->num_entries; k++)
5383 table->mc_reg_table_entry[k].mc_data[j] =
5384 ((temp_reg & 0xffff0000)) |
5385 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5386 j++;
5387 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5388 return -EINVAL;
5389
5390 temp_reg = RREG32(MC_PMG_CMD_MRS);
5391 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5392 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5393 for (k = 0; k < table->num_entries; k++) {
5394 table->mc_reg_table_entry[k].mc_data[j] =
5395 (temp_reg & 0xffff0000) |
5396 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5397 if (!pi->mem_gddr5)
5398 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5399 }
5400 j++;
5401 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5402 return -EINVAL;
5403
5404 if (!pi->mem_gddr5) {
5405 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5406 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5407 for (k = 0; k < table->num_entries; k++)
5408 table->mc_reg_table_entry[k].mc_data[j] =
5409 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5410 j++;
5411 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5412 return -EINVAL;
5413 }
5414 break;
5415 case MC_SEQ_RESERVE_M:
5416 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5417 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5418 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5419 for(k = 0; k < table->num_entries; k++)
5420 table->mc_reg_table_entry[k].mc_data[j] =
5421 (temp_reg & 0xffff0000) |
5422 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5423 j++;
5424 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5425 return -EINVAL;
5426 break;
5427 default:
5428 break;
5429 }
5430 }
5431
5432 table->last = j;
5433
5434 return 0;
5435 }
5436
5437 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5438 {
5439 bool result = true;
5440
5441 switch (in_reg) {
5442 case MC_SEQ_RAS_TIMING >> 2:
5443 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5444 break;
5445 case MC_SEQ_CAS_TIMING >> 2:
5446 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5447 break;
5448 case MC_SEQ_MISC_TIMING >> 2:
5449 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5450 break;
5451 case MC_SEQ_MISC_TIMING2 >> 2:
5452 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5453 break;
5454 case MC_SEQ_RD_CTL_D0 >> 2:
5455 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5456 break;
5457 case MC_SEQ_RD_CTL_D1 >> 2:
5458 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5459 break;
5460 case MC_SEQ_WR_CTL_D0 >> 2:
5461 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5462 break;
5463 case MC_SEQ_WR_CTL_D1 >> 2:
5464 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5465 break;
5466 case MC_PMG_CMD_EMRS >> 2:
5467 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5468 break;
5469 case MC_PMG_CMD_MRS >> 2:
5470 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5471 break;
5472 case MC_PMG_CMD_MRS1 >> 2:
5473 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5474 break;
5475 case MC_SEQ_PMG_TIMING >> 2:
5476 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5477 break;
5478 case MC_PMG_CMD_MRS2 >> 2:
5479 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5480 break;
5481 case MC_SEQ_WR_CTL_2 >> 2:
5482 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5483 break;
5484 default:
5485 result = false;
5486 break;
5487 }
5488
5489 return result;
5490 }
5491
5492 static void si_set_valid_flag(struct si_mc_reg_table *table)
5493 {
5494 u8 i, j;
5495
5496 for (i = 0; i < table->last; i++) {
5497 for (j = 1; j < table->num_entries; j++) {
5498 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5499 table->valid_flag |= 1 << i;
5500 break;
5501 }
5502 }
5503 }
5504 }
5505
5506 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5507 {
5508 u32 i;
5509 u16 address;
5510
5511 for (i = 0; i < table->last; i++)
5512 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5513 address : table->mc_reg_address[i].s1;
5514
5515 }
5516
5517 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5518 struct si_mc_reg_table *si_table)
5519 {
5520 u8 i, j;
5521
5522 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5523 return -EINVAL;
5524 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5525 return -EINVAL;
5526
5527 for (i = 0; i < table->last; i++)
5528 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5529 si_table->last = table->last;
5530
5531 for (i = 0; i < table->num_entries; i++) {
5532 si_table->mc_reg_table_entry[i].mclk_max =
5533 table->mc_reg_table_entry[i].mclk_max;
5534 for (j = 0; j < table->last; j++) {
5535 si_table->mc_reg_table_entry[i].mc_data[j] =
5536 table->mc_reg_table_entry[i].mc_data[j];
5537 }
5538 }
5539 si_table->num_entries = table->num_entries;
5540
5541 return 0;
5542 }
5543
5544 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5545 {
5546 struct si_power_info *si_pi = si_get_pi(rdev);
5547 struct atom_mc_reg_table *table;
5548 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5549 u8 module_index = rv770_get_memory_module_index(rdev);
5550 int ret;
5551
5552 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5553 if (!table)
5554 return -ENOMEM;
5555
5556 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5557 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5558 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5559 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5560 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5561 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5562 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5563 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5564 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5565 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5566 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5567 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5568 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5569 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5570
5571 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5572 if (ret)
5573 goto init_mc_done;
5574
5575 ret = si_copy_vbios_mc_reg_table(table, si_table);
5576 if (ret)
5577 goto init_mc_done;
5578
5579 si_set_s0_mc_reg_index(si_table);
5580
5581 ret = si_set_mc_special_registers(rdev, si_table);
5582 if (ret)
5583 goto init_mc_done;
5584
5585 si_set_valid_flag(si_table);
5586
5587 init_mc_done:
5588 kfree(table);
5589
5590 return ret;
5591
5592 }
5593
5594 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5595 SMC_SIslands_MCRegisters *mc_reg_table)
5596 {
5597 struct si_power_info *si_pi = si_get_pi(rdev);
5598 u32 i, j;
5599
5600 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5601 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5602 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5603 break;
5604 mc_reg_table->address[i].s0 =
5605 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5606 mc_reg_table->address[i].s1 =
5607 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5608 i++;
5609 }
5610 }
5611 mc_reg_table->last = (u8)i;
5612 }
5613
5614 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5615 SMC_SIslands_MCRegisterSet *data,
5616 u32 num_entries, u32 valid_flag)
5617 {
5618 u32 i, j;
5619
5620 for(i = 0, j = 0; j < num_entries; j++) {
5621 if (valid_flag & (1 << j)) {
5622 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5623 i++;
5624 }
5625 }
5626 }
5627
5628 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5629 struct rv7xx_pl *pl,
5630 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5631 {
5632 struct si_power_info *si_pi = si_get_pi(rdev);
5633 u32 i = 0;
5634
5635 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5636 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5637 break;
5638 }
5639
5640 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5641 --i;
5642
5643 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5644 mc_reg_table_data, si_pi->mc_reg_table.last,
5645 si_pi->mc_reg_table.valid_flag);
5646 }
5647
5648 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5649 struct radeon_ps *radeon_state,
5650 SMC_SIslands_MCRegisters *mc_reg_table)
5651 {
5652 struct ni_ps *state = ni_get_ps(radeon_state);
5653 int i;
5654
5655 for (i = 0; i < state->performance_level_count; i++) {
5656 si_convert_mc_reg_table_entry_to_smc(rdev,
5657 &state->performance_levels[i],
5658 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5659 }
5660 }
5661
5662 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5663 struct radeon_ps *radeon_boot_state)
5664 {
5665 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5666 struct si_power_info *si_pi = si_get_pi(rdev);
5667 struct si_ulv_param *ulv = &si_pi->ulv;
5668 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5669
5670 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5671
5672 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5673
5674 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5675
5676 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5677 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5678
5679 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5680 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5681 si_pi->mc_reg_table.last,
5682 si_pi->mc_reg_table.valid_flag);
5683
5684 if (ulv->supported && ulv->pl.vddc != 0)
5685 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5686 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5687 else
5688 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5689 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5690 si_pi->mc_reg_table.last,
5691 si_pi->mc_reg_table.valid_flag);
5692
5693 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5694
5695 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5696 (u8 *)smc_mc_reg_table,
5697 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5698 }
5699
5700 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5701 struct radeon_ps *radeon_new_state)
5702 {
5703 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5704 struct si_power_info *si_pi = si_get_pi(rdev);
5705 u32 address = si_pi->mc_reg_table_start +
5706 offsetof(SMC_SIslands_MCRegisters,
5707 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5708 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5709
5710 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5711
5712 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5713
5714
5715 return si_copy_bytes_to_smc(rdev, address,
5716 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5717 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5718 si_pi->sram_end);
5719
5720 }
5721
5722 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5723 {
5724 if (enable)
5725 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5726 else
5727 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5728 }
5729
5730 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5731 struct radeon_ps *radeon_state)
5732 {
5733 struct ni_ps *state = ni_get_ps(radeon_state);
5734 int i;
5735 u16 pcie_speed, max_speed = 0;
5736
5737 for (i = 0; i < state->performance_level_count; i++) {
5738 pcie_speed = state->performance_levels[i].pcie_gen;
5739 if (max_speed < pcie_speed)
5740 max_speed = pcie_speed;
5741 }
5742 return max_speed;
5743 }
5744
5745 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5746 {
5747 u32 speed_cntl;
5748
5749 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5750 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5751
5752 return (u16)speed_cntl;
5753 }
5754
5755 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5756 struct radeon_ps *radeon_new_state,
5757 struct radeon_ps *radeon_current_state)
5758 {
5759 struct si_power_info *si_pi = si_get_pi(rdev);
5760 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5761 enum radeon_pcie_gen current_link_speed;
5762
5763 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5764 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5765 else
5766 current_link_speed = si_pi->force_pcie_gen;
5767
5768 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5769 si_pi->pspp_notify_required = false;
5770 if (target_link_speed > current_link_speed) {
5771 switch (target_link_speed) {
5772 #if defined(CONFIG_ACPI)
5773 case RADEON_PCIE_GEN3:
5774 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5775 break;
5776 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5777 if (current_link_speed == RADEON_PCIE_GEN2)
5778 break;
5779 case RADEON_PCIE_GEN2:
5780 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5781 break;
5782 #endif
5783 default:
5784 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5785 break;
5786 }
5787 } else {
5788 if (target_link_speed < current_link_speed)
5789 si_pi->pspp_notify_required = true;
5790 }
5791 }
5792
5793 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5794 struct radeon_ps *radeon_new_state,
5795 struct radeon_ps *radeon_current_state)
5796 {
5797 struct si_power_info *si_pi = si_get_pi(rdev);
5798 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5799 u8 request;
5800
5801 if (si_pi->pspp_notify_required) {
5802 if (target_link_speed == RADEON_PCIE_GEN3)
5803 request = PCIE_PERF_REQ_PECI_GEN3;
5804 else if (target_link_speed == RADEON_PCIE_GEN2)
5805 request = PCIE_PERF_REQ_PECI_GEN2;
5806 else
5807 request = PCIE_PERF_REQ_PECI_GEN1;
5808
5809 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5810 (si_get_current_pcie_speed(rdev) > 0))
5811 return;
5812
5813 #if defined(CONFIG_ACPI)
5814 radeon_acpi_pcie_performance_request(rdev, request, false);
5815 #endif
5816 }
5817 }
5818
5819 #if 0
5820 static int si_ds_request(struct radeon_device *rdev,
5821 bool ds_status_on, u32 count_write)
5822 {
5823 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5824
5825 if (eg_pi->sclk_deep_sleep) {
5826 if (ds_status_on)
5827 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5828 PPSMC_Result_OK) ?
5829 0 : -EINVAL;
5830 else
5831 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5832 PPSMC_Result_OK) ? 0 : -EINVAL;
5833 }
5834 return 0;
5835 }
5836 #endif
5837
5838 static void si_set_max_cu_value(struct radeon_device *rdev)
5839 {
5840 struct si_power_info *si_pi = si_get_pi(rdev);
5841
5842 if (rdev->family == CHIP_VERDE) {
5843 switch (rdev->pdev->device) {
5844 case 0x6820:
5845 case 0x6825:
5846 case 0x6821:
5847 case 0x6823:
5848 case 0x6827:
5849 si_pi->max_cu = 10;
5850 break;
5851 case 0x682D:
5852 case 0x6824:
5853 case 0x682F:
5854 case 0x6826:
5855 si_pi->max_cu = 8;
5856 break;
5857 case 0x6828:
5858 case 0x6830:
5859 case 0x6831:
5860 case 0x6838:
5861 case 0x6839:
5862 case 0x683D:
5863 si_pi->max_cu = 10;
5864 break;
5865 case 0x683B:
5866 case 0x683F:
5867 case 0x6829:
5868 si_pi->max_cu = 8;
5869 break;
5870 default:
5871 si_pi->max_cu = 0;
5872 break;
5873 }
5874 } else {
5875 si_pi->max_cu = 0;
5876 }
5877 }
5878
5879 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5880 struct radeon_clock_voltage_dependency_table *table)
5881 {
5882 u32 i;
5883 int j;
5884 u16 leakage_voltage;
5885
5886 if (table) {
5887 for (i = 0; i < table->count; i++) {
5888 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5889 table->entries[i].v,
5890 &leakage_voltage)) {
5891 case 0:
5892 table->entries[i].v = leakage_voltage;
5893 break;
5894 case -EAGAIN:
5895 return -EINVAL;
5896 case -EINVAL:
5897 default:
5898 break;
5899 }
5900 }
5901
5902 for (j = (table->count - 2); j >= 0; j--) {
5903 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5904 table->entries[j].v : table->entries[j + 1].v;
5905 }
5906 }
5907 return 0;
5908 }
5909
5910 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5911 {
5912 int ret = 0;
5913
5914 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5915 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5916 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5917 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5918 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5919 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5920 return ret;
5921 }
5922
5923 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5924 struct radeon_ps *radeon_new_state,
5925 struct radeon_ps *radeon_current_state)
5926 {
5927 u32 lane_width;
5928 u32 new_lane_width =
5929 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5930 u32 current_lane_width =
5931 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5932
5933 if (new_lane_width != current_lane_width) {
5934 radeon_set_pcie_lanes(rdev, new_lane_width);
5935 lane_width = radeon_get_pcie_lanes(rdev);
5936 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5937 }
5938 }
5939
5940 static void si_set_vce_clock(struct radeon_device *rdev,
5941 struct radeon_ps *new_rps,
5942 struct radeon_ps *old_rps)
5943 {
5944 if ((old_rps->evclk != new_rps->evclk) ||
5945 (old_rps->ecclk != new_rps->ecclk)) {
5946 /* turn the clocks on when encoding, off otherwise */
5947 if (new_rps->evclk || new_rps->ecclk)
5948 vce_v1_0_enable_mgcg(rdev, false);
5949 else
5950 vce_v1_0_enable_mgcg(rdev, true);
5951 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5952 }
5953 }
5954
5955 void si_dpm_setup_asic(struct radeon_device *rdev)
5956 {
5957 int r;
5958
5959 r = si_mc_load_microcode(rdev);
5960 if (r)
5961 DRM_ERROR("Failed to load MC firmware!\n");
5962 rv770_get_memory_type(rdev);
5963 si_read_clock_registers(rdev);
5964 si_enable_acpi_power_management(rdev);
5965 }
5966
5967 static int si_thermal_enable_alert(struct radeon_device *rdev,
5968 bool enable)
5969 {
5970 u32 thermal_int = RREG32(CG_THERMAL_INT);
5971
5972 if (enable) {
5973 PPSMC_Result result;
5974
5975 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5976 WREG32(CG_THERMAL_INT, thermal_int);
5977 rdev->irq.dpm_thermal = false;
5978 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5979 if (result != PPSMC_Result_OK) {
5980 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5981 return -EINVAL;
5982 }
5983 } else {
5984 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5985 WREG32(CG_THERMAL_INT, thermal_int);
5986 rdev->irq.dpm_thermal = true;
5987 }
5988
5989 return 0;
5990 }
5991
5992 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5993 int min_temp, int max_temp)
5994 {
5995 int low_temp = 0 * 1000;
5996 int high_temp = 255 * 1000;
5997
5998 if (low_temp < min_temp)
5999 low_temp = min_temp;
6000 if (high_temp > max_temp)
6001 high_temp = max_temp;
6002 if (high_temp < low_temp) {
6003 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6004 return -EINVAL;
6005 }
6006
6007 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6008 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6009 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6010
6011 rdev->pm.dpm.thermal.min_temp = low_temp;
6012 rdev->pm.dpm.thermal.max_temp = high_temp;
6013
6014 return 0;
6015 }
6016
6017 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6018 {
6019 struct si_power_info *si_pi = si_get_pi(rdev);
6020 u32 tmp;
6021
6022 if (si_pi->fan_ctrl_is_in_default_mode) {
6023 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6024 si_pi->fan_ctrl_default_mode = tmp;
6025 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6026 si_pi->t_min = tmp;
6027 si_pi->fan_ctrl_is_in_default_mode = false;
6028 }
6029
6030 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6031 tmp |= TMIN(0);
6032 WREG32(CG_FDO_CTRL2, tmp);
6033
6034 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6035 tmp |= FDO_PWM_MODE(mode);
6036 WREG32(CG_FDO_CTRL2, tmp);
6037 }
6038
6039 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6040 {
6041 struct si_power_info *si_pi = si_get_pi(rdev);
6042 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6043 u32 duty100;
6044 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6045 u16 fdo_min, slope1, slope2;
6046 u32 reference_clock, tmp;
6047 int ret;
6048 u64 tmp64;
6049
6050 if (!si_pi->fan_table_start) {
6051 rdev->pm.dpm.fan.ucode_fan_control = false;
6052 return 0;
6053 }
6054
6055 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6056
6057 if (duty100 == 0) {
6058 rdev->pm.dpm.fan.ucode_fan_control = false;
6059 return 0;
6060 }
6061
6062 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6063 do_div(tmp64, 10000);
6064 fdo_min = (u16)tmp64;
6065
6066 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6067 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6068
6069 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6070 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6071
6072 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6073 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6074
6075 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6076 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6077 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6078
6079 fan_table.slope1 = cpu_to_be16(slope1);
6080 fan_table.slope2 = cpu_to_be16(slope2);
6081
6082 fan_table.fdo_min = cpu_to_be16(fdo_min);
6083
6084 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6085
6086 fan_table.hys_up = cpu_to_be16(1);
6087
6088 fan_table.hys_slope = cpu_to_be16(1);
6089
6090 fan_table.temp_resp_lim = cpu_to_be16(5);
6091
6092 reference_clock = radeon_get_xclk(rdev);
6093
6094 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6095 reference_clock) / 1600);
6096
6097 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6098
6099 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6100 fan_table.temp_src = (uint8_t)tmp;
6101
6102 ret = si_copy_bytes_to_smc(rdev,
6103 si_pi->fan_table_start,
6104 (u8 *)(&fan_table),
6105 sizeof(fan_table),
6106 si_pi->sram_end);
6107
6108 if (ret) {
6109 DRM_ERROR("Failed to load fan table to the SMC.");
6110 rdev->pm.dpm.fan.ucode_fan_control = false;
6111 }
6112
6113 return 0;
6114 }
6115
6116 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6117 {
6118 struct si_power_info *si_pi = si_get_pi(rdev);
6119 PPSMC_Result ret;
6120
6121 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6122 if (ret == PPSMC_Result_OK) {
6123 si_pi->fan_is_controlled_by_smc = true;
6124 return 0;
6125 } else {
6126 return -EINVAL;
6127 }
6128 }
6129
6130 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6131 {
6132 struct si_power_info *si_pi = si_get_pi(rdev);
6133 PPSMC_Result ret;
6134
6135 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6136
6137 if (ret == PPSMC_Result_OK) {
6138 si_pi->fan_is_controlled_by_smc = false;
6139 return 0;
6140 } else {
6141 return -EINVAL;
6142 }
6143 }
6144
6145 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6146 u32 *speed)
6147 {
6148 u32 duty, duty100;
6149 u64 tmp64;
6150
6151 if (rdev->pm.no_fan)
6152 return -ENOENT;
6153
6154 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6155 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6156
6157 if (duty100 == 0)
6158 return -EINVAL;
6159
6160 tmp64 = (u64)duty * 100;
6161 do_div(tmp64, duty100);
6162 *speed = (u32)tmp64;
6163
6164 if (*speed > 100)
6165 *speed = 100;
6166
6167 return 0;
6168 }
6169
6170 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6171 u32 speed)
6172 {
6173 struct si_power_info *si_pi = si_get_pi(rdev);
6174 u32 tmp;
6175 u32 duty, duty100;
6176 u64 tmp64;
6177
6178 if (rdev->pm.no_fan)
6179 return -ENOENT;
6180
6181 if (si_pi->fan_is_controlled_by_smc)
6182 return -EINVAL;
6183
6184 if (speed > 100)
6185 return -EINVAL;
6186
6187 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6188
6189 if (duty100 == 0)
6190 return -EINVAL;
6191
6192 tmp64 = (u64)speed * duty100;
6193 do_div(tmp64, 100);
6194 duty = (u32)tmp64;
6195
6196 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6197 tmp |= FDO_STATIC_DUTY(duty);
6198 WREG32(CG_FDO_CTRL0, tmp);
6199
6200 return 0;
6201 }
6202
6203 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6204 {
6205 if (mode) {
6206 /* stop auto-manage */
6207 if (rdev->pm.dpm.fan.ucode_fan_control)
6208 si_fan_ctrl_stop_smc_fan_control(rdev);
6209 si_fan_ctrl_set_static_mode(rdev, mode);
6210 } else {
6211 /* restart auto-manage */
6212 if (rdev->pm.dpm.fan.ucode_fan_control)
6213 si_thermal_start_smc_fan_control(rdev);
6214 else
6215 si_fan_ctrl_set_default_mode(rdev);
6216 }
6217 }
6218
6219 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6220 {
6221 struct si_power_info *si_pi = si_get_pi(rdev);
6222 u32 tmp;
6223
6224 if (si_pi->fan_is_controlled_by_smc)
6225 return 0;
6226
6227 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6228 return (tmp >> FDO_PWM_MODE_SHIFT);
6229 }
6230
6231 #if 0
6232 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6233 u32 *speed)
6234 {
6235 u32 tach_period;
6236 u32 xclk = radeon_get_xclk(rdev);
6237
6238 if (rdev->pm.no_fan)
6239 return -ENOENT;
6240
6241 if (rdev->pm.fan_pulses_per_revolution == 0)
6242 return -ENOENT;
6243
6244 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6245 if (tach_period == 0)
6246 return -ENOENT;
6247
6248 *speed = 60 * xclk * 10000 / tach_period;
6249
6250 return 0;
6251 }
6252
6253 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6254 u32 speed)
6255 {
6256 u32 tach_period, tmp;
6257 u32 xclk = radeon_get_xclk(rdev);
6258
6259 if (rdev->pm.no_fan)
6260 return -ENOENT;
6261
6262 if (rdev->pm.fan_pulses_per_revolution == 0)
6263 return -ENOENT;
6264
6265 if ((speed < rdev->pm.fan_min_rpm) ||
6266 (speed > rdev->pm.fan_max_rpm))
6267 return -EINVAL;
6268
6269 if (rdev->pm.dpm.fan.ucode_fan_control)
6270 si_fan_ctrl_stop_smc_fan_control(rdev);
6271
6272 tach_period = 60 * xclk * 10000 / (8 * speed);
6273 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6274 tmp |= TARGET_PERIOD(tach_period);
6275 WREG32(CG_TACH_CTRL, tmp);
6276
6277 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6278
6279 return 0;
6280 }
6281 #endif
6282
6283 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6284 {
6285 struct si_power_info *si_pi = si_get_pi(rdev);
6286 u32 tmp;
6287
6288 if (!si_pi->fan_ctrl_is_in_default_mode) {
6289 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6290 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6291 WREG32(CG_FDO_CTRL2, tmp);
6292
6293 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6294 tmp |= TMIN(si_pi->t_min);
6295 WREG32(CG_FDO_CTRL2, tmp);
6296 si_pi->fan_ctrl_is_in_default_mode = true;
6297 }
6298 }
6299
6300 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6301 {
6302 if (rdev->pm.dpm.fan.ucode_fan_control) {
6303 si_fan_ctrl_start_smc_fan_control(rdev);
6304 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6305 }
6306 }
6307
6308 static void si_thermal_initialize(struct radeon_device *rdev)
6309 {
6310 u32 tmp;
6311
6312 if (rdev->pm.fan_pulses_per_revolution) {
6313 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6314 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6315 WREG32(CG_TACH_CTRL, tmp);
6316 }
6317
6318 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6319 tmp |= TACH_PWM_RESP_RATE(0x28);
6320 WREG32(CG_FDO_CTRL2, tmp);
6321 }
6322
6323 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6324 {
6325 int ret;
6326
6327 si_thermal_initialize(rdev);
6328 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6329 if (ret)
6330 return ret;
6331 ret = si_thermal_enable_alert(rdev, true);
6332 if (ret)
6333 return ret;
6334 if (rdev->pm.dpm.fan.ucode_fan_control) {
6335 ret = si_halt_smc(rdev);
6336 if (ret)
6337 return ret;
6338 ret = si_thermal_setup_fan_table(rdev);
6339 if (ret)
6340 return ret;
6341 ret = si_resume_smc(rdev);
6342 if (ret)
6343 return ret;
6344 si_thermal_start_smc_fan_control(rdev);
6345 }
6346
6347 return 0;
6348 }
6349
6350 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6351 {
6352 if (!rdev->pm.no_fan) {
6353 si_fan_ctrl_set_default_mode(rdev);
6354 si_fan_ctrl_stop_smc_fan_control(rdev);
6355 }
6356 }
6357
6358 int si_dpm_enable(struct radeon_device *rdev)
6359 {
6360 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6361 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6362 struct si_power_info *si_pi = si_get_pi(rdev);
6363 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6364 int ret;
6365
6366 if (si_is_smc_running(rdev))
6367 return -EINVAL;
6368 if (pi->voltage_control || si_pi->voltage_control_svi2)
6369 si_enable_voltage_control(rdev, true);
6370 if (pi->mvdd_control)
6371 si_get_mvdd_configuration(rdev);
6372 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6373 ret = si_construct_voltage_tables(rdev);
6374 if (ret) {
6375 DRM_ERROR("si_construct_voltage_tables failed\n");
6376 return ret;
6377 }
6378 }
6379 if (eg_pi->dynamic_ac_timing) {
6380 ret = si_initialize_mc_reg_table(rdev);
6381 if (ret)
6382 eg_pi->dynamic_ac_timing = false;
6383 }
6384 if (pi->dynamic_ss)
6385 si_enable_spread_spectrum(rdev, true);
6386 if (pi->thermal_protection)
6387 si_enable_thermal_protection(rdev, true);
6388 si_setup_bsp(rdev);
6389 si_program_git(rdev);
6390 si_program_tp(rdev);
6391 si_program_tpp(rdev);
6392 si_program_sstp(rdev);
6393 si_enable_display_gap(rdev);
6394 si_program_vc(rdev);
6395 ret = si_upload_firmware(rdev);
6396 if (ret) {
6397 DRM_ERROR("si_upload_firmware failed\n");
6398 return ret;
6399 }
6400 ret = si_process_firmware_header(rdev);
6401 if (ret) {
6402 DRM_ERROR("si_process_firmware_header failed\n");
6403 return ret;
6404 }
6405 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6406 if (ret) {
6407 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6408 return ret;
6409 }
6410 ret = si_init_smc_table(rdev);
6411 if (ret) {
6412 DRM_ERROR("si_init_smc_table failed\n");
6413 return ret;
6414 }
6415 ret = si_init_smc_spll_table(rdev);
6416 if (ret) {
6417 DRM_ERROR("si_init_smc_spll_table failed\n");
6418 return ret;
6419 }
6420 ret = si_init_arb_table_index(rdev);
6421 if (ret) {
6422 DRM_ERROR("si_init_arb_table_index failed\n");
6423 return ret;
6424 }
6425 if (eg_pi->dynamic_ac_timing) {
6426 ret = si_populate_mc_reg_table(rdev, boot_ps);
6427 if (ret) {
6428 DRM_ERROR("si_populate_mc_reg_table failed\n");
6429 return ret;
6430 }
6431 }
6432 ret = si_initialize_smc_cac_tables(rdev);
6433 if (ret) {
6434 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6435 return ret;
6436 }
6437 ret = si_initialize_hardware_cac_manager(rdev);
6438 if (ret) {
6439 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6440 return ret;
6441 }
6442 ret = si_initialize_smc_dte_tables(rdev);
6443 if (ret) {
6444 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6445 return ret;
6446 }
6447 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6448 if (ret) {
6449 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6450 return ret;
6451 }
6452 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6453 if (ret) {
6454 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6455 return ret;
6456 }
6457 si_program_response_times(rdev);
6458 si_program_ds_registers(rdev);
6459 si_dpm_start_smc(rdev);
6460 ret = si_notify_smc_display_change(rdev, false);
6461 if (ret) {
6462 DRM_ERROR("si_notify_smc_display_change failed\n");
6463 return ret;
6464 }
6465 si_enable_sclk_control(rdev, true);
6466 si_start_dpm(rdev);
6467
6468 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6469
6470 si_thermal_start_thermal_controller(rdev);
6471
6472 ni_update_current_ps(rdev, boot_ps);
6473
6474 return 0;
6475 }
6476
6477 static int si_set_temperature_range(struct radeon_device *rdev)
6478 {
6479 int ret;
6480
6481 ret = si_thermal_enable_alert(rdev, false);
6482 if (ret)
6483 return ret;
6484 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6485 if (ret)
6486 return ret;
6487 ret = si_thermal_enable_alert(rdev, true);
6488 if (ret)
6489 return ret;
6490
6491 return ret;
6492 }
6493
6494 int si_dpm_late_enable(struct radeon_device *rdev)
6495 {
6496 int ret;
6497
6498 ret = si_set_temperature_range(rdev);
6499 if (ret)
6500 return ret;
6501
6502 return ret;
6503 }
6504
6505 void si_dpm_disable(struct radeon_device *rdev)
6506 {
6507 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6508 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6509
6510 if (!si_is_smc_running(rdev))
6511 return;
6512 si_thermal_stop_thermal_controller(rdev);
6513 si_disable_ulv(rdev);
6514 si_clear_vc(rdev);
6515 if (pi->thermal_protection)
6516 si_enable_thermal_protection(rdev, false);
6517 si_enable_power_containment(rdev, boot_ps, false);
6518 si_enable_smc_cac(rdev, boot_ps, false);
6519 si_enable_spread_spectrum(rdev, false);
6520 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6521 si_stop_dpm(rdev);
6522 si_reset_to_default(rdev);
6523 si_dpm_stop_smc(rdev);
6524 si_force_switch_to_arb_f0(rdev);
6525
6526 ni_update_current_ps(rdev, boot_ps);
6527 }
6528
6529 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6530 {
6531 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6532 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6533 struct radeon_ps *new_ps = &requested_ps;
6534
6535 ni_update_requested_ps(rdev, new_ps);
6536
6537 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6538
6539 return 0;
6540 }
6541
6542 static int si_power_control_set_level(struct radeon_device *rdev)
6543 {
6544 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6545 int ret;
6546
6547 ret = si_restrict_performance_levels_before_switch(rdev);
6548 if (ret)
6549 return ret;
6550 ret = si_halt_smc(rdev);
6551 if (ret)
6552 return ret;
6553 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6554 if (ret)
6555 return ret;
6556 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6557 if (ret)
6558 return ret;
6559 ret = si_resume_smc(rdev);
6560 if (ret)
6561 return ret;
6562 ret = si_set_sw_state(rdev);
6563 if (ret)
6564 return ret;
6565 return 0;
6566 }
6567
6568 int si_dpm_set_power_state(struct radeon_device *rdev)
6569 {
6570 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6571 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6572 struct radeon_ps *old_ps = &eg_pi->current_rps;
6573 int ret;
6574
6575 ret = si_disable_ulv(rdev);
6576 if (ret) {
6577 DRM_ERROR("si_disable_ulv failed\n");
6578 return ret;
6579 }
6580 ret = si_restrict_performance_levels_before_switch(rdev);
6581 if (ret) {
6582 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6583 return ret;
6584 }
6585 if (eg_pi->pcie_performance_request)
6586 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6587 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6588 ret = si_enable_power_containment(rdev, new_ps, false);
6589 if (ret) {
6590 DRM_ERROR("si_enable_power_containment failed\n");
6591 return ret;
6592 }
6593 ret = si_enable_smc_cac(rdev, new_ps, false);
6594 if (ret) {
6595 DRM_ERROR("si_enable_smc_cac failed\n");
6596 return ret;
6597 }
6598 ret = si_halt_smc(rdev);
6599 if (ret) {
6600 DRM_ERROR("si_halt_smc failed\n");
6601 return ret;
6602 }
6603 ret = si_upload_sw_state(rdev, new_ps);
6604 if (ret) {
6605 DRM_ERROR("si_upload_sw_state failed\n");
6606 return ret;
6607 }
6608 ret = si_upload_smc_data(rdev);
6609 if (ret) {
6610 DRM_ERROR("si_upload_smc_data failed\n");
6611 return ret;
6612 }
6613 ret = si_upload_ulv_state(rdev);
6614 if (ret) {
6615 DRM_ERROR("si_upload_ulv_state failed\n");
6616 return ret;
6617 }
6618 if (eg_pi->dynamic_ac_timing) {
6619 ret = si_upload_mc_reg_table(rdev, new_ps);
6620 if (ret) {
6621 DRM_ERROR("si_upload_mc_reg_table failed\n");
6622 return ret;
6623 }
6624 }
6625 ret = si_program_memory_timing_parameters(rdev, new_ps);
6626 if (ret) {
6627 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6628 return ret;
6629 }
6630 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6631
6632 ret = si_resume_smc(rdev);
6633 if (ret) {
6634 DRM_ERROR("si_resume_smc failed\n");
6635 return ret;
6636 }
6637 ret = si_set_sw_state(rdev);
6638 if (ret) {
6639 DRM_ERROR("si_set_sw_state failed\n");
6640 return ret;
6641 }
6642 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6643 si_set_vce_clock(rdev, new_ps, old_ps);
6644 if (eg_pi->pcie_performance_request)
6645 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6646 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6647 if (ret) {
6648 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6649 return ret;
6650 }
6651 ret = si_enable_smc_cac(rdev, new_ps, true);
6652 if (ret) {
6653 DRM_ERROR("si_enable_smc_cac failed\n");
6654 return ret;
6655 }
6656 ret = si_enable_power_containment(rdev, new_ps, true);
6657 if (ret) {
6658 DRM_ERROR("si_enable_power_containment failed\n");
6659 return ret;
6660 }
6661
6662 ret = si_power_control_set_level(rdev);
6663 if (ret) {
6664 DRM_ERROR("si_power_control_set_level failed\n");
6665 return ret;
6666 }
6667
6668 return 0;
6669 }
6670
6671 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6672 {
6673 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6674 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6675
6676 ni_update_current_ps(rdev, new_ps);
6677 }
6678
6679 #if 0
6680 void si_dpm_reset_asic(struct radeon_device *rdev)
6681 {
6682 si_restrict_performance_levels_before_switch(rdev);
6683 si_disable_ulv(rdev);
6684 si_set_boot_state(rdev);
6685 }
6686 #endif
6687
6688 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6689 {
6690 si_program_display_gap(rdev);
6691 }
6692
6693 union power_info {
6694 struct _ATOM_POWERPLAY_INFO info;
6695 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6696 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6697 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6698 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6699 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6700 };
6701
6702 union pplib_clock_info {
6703 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6704 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6705 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6706 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6707 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6708 };
6709
6710 union pplib_power_state {
6711 struct _ATOM_PPLIB_STATE v1;
6712 struct _ATOM_PPLIB_STATE_V2 v2;
6713 };
6714
6715 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6716 struct radeon_ps *rps,
6717 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6718 u8 table_rev)
6719 {
6720 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6721 rps->class = le16_to_cpu(non_clock_info->usClassification);
6722 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6723
6724 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6725 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6726 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6727 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6728 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6729 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6730 } else {
6731 rps->vclk = 0;
6732 rps->dclk = 0;
6733 }
6734
6735 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6736 rdev->pm.dpm.boot_ps = rps;
6737 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6738 rdev->pm.dpm.uvd_ps = rps;
6739 }
6740
6741 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6742 struct radeon_ps *rps, int index,
6743 union pplib_clock_info *clock_info)
6744 {
6745 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6746 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6747 struct si_power_info *si_pi = si_get_pi(rdev);
6748 struct ni_ps *ps = ni_get_ps(rps);
6749 u16 leakage_voltage;
6750 struct rv7xx_pl *pl = &ps->performance_levels[index];
6751 int ret;
6752
6753 ps->performance_level_count = index + 1;
6754
6755 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6756 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6757 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6758 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6759
6760 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6761 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6762 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6763 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6764 si_pi->sys_pcie_mask,
6765 si_pi->boot_pcie_gen,
6766 clock_info->si.ucPCIEGen);
6767
6768 /* patch up vddc if necessary */
6769 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6770 &leakage_voltage);
6771 if (ret == 0)
6772 pl->vddc = leakage_voltage;
6773
6774 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6775 pi->acpi_vddc = pl->vddc;
6776 eg_pi->acpi_vddci = pl->vddci;
6777 si_pi->acpi_pcie_gen = pl->pcie_gen;
6778 }
6779
6780 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6781 index == 0) {
6782 /* XXX disable for A0 tahiti */
6783 si_pi->ulv.supported = false;
6784 si_pi->ulv.pl = *pl;
6785 si_pi->ulv.one_pcie_lane_in_ulv = false;
6786 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6787 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6788 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6789 }
6790
6791 if (pi->min_vddc_in_table > pl->vddc)
6792 pi->min_vddc_in_table = pl->vddc;
6793
6794 if (pi->max_vddc_in_table < pl->vddc)
6795 pi->max_vddc_in_table = pl->vddc;
6796
6797 /* patch up boot state */
6798 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6799 u16 vddc, vddci, mvdd;
6800 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6801 pl->mclk = rdev->clock.default_mclk;
6802 pl->sclk = rdev->clock.default_sclk;
6803 pl->vddc = vddc;
6804 pl->vddci = vddci;
6805 si_pi->mvdd_bootup_value = mvdd;
6806 }
6807
6808 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6809 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6810 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6811 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6812 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6813 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6814 }
6815 }
6816
6817 static int si_parse_power_table(struct radeon_device *rdev)
6818 {
6819 struct radeon_mode_info *mode_info = &rdev->mode_info;
6820 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6821 union pplib_power_state *power_state;
6822 int i, j, k, non_clock_array_index, clock_array_index;
6823 union pplib_clock_info *clock_info;
6824 struct _StateArray *state_array;
6825 struct _ClockInfoArray *clock_info_array;
6826 struct _NonClockInfoArray *non_clock_info_array;
6827 union power_info *power_info;
6828 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6829 u16 data_offset;
6830 u8 frev, crev;
6831 u8 *power_state_offset;
6832 struct ni_ps *ps;
6833
6834 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6835 &frev, &crev, &data_offset))
6836 return -EINVAL;
6837 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6838
6839 state_array = (struct _StateArray *)
6840 (mode_info->atom_context->bios + data_offset +
6841 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6842 clock_info_array = (struct _ClockInfoArray *)
6843 (mode_info->atom_context->bios + data_offset +
6844 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6845 non_clock_info_array = (struct _NonClockInfoArray *)
6846 (mode_info->atom_context->bios + data_offset +
6847 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6848
6849 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6850 state_array->ucNumEntries, GFP_KERNEL);
6851 if (!rdev->pm.dpm.ps)
6852 return -ENOMEM;
6853 power_state_offset = (u8 *)state_array->states;
6854 for (i = 0; i < state_array->ucNumEntries; i++) {
6855 u8 *idx;
6856 power_state = (union pplib_power_state *)power_state_offset;
6857 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6858 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6859 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6860 if (!rdev->pm.power_state[i].clock_info)
6861 return -EINVAL;
6862 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6863 if (ps == NULL) {
6864 kfree(rdev->pm.dpm.ps);
6865 return -ENOMEM;
6866 }
6867 rdev->pm.dpm.ps[i].ps_priv = ps;
6868 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6869 non_clock_info,
6870 non_clock_info_array->ucEntrySize);
6871 k = 0;
6872 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6873 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6874 clock_array_index = idx[j];
6875 if (clock_array_index >= clock_info_array->ucNumEntries)
6876 continue;
6877 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6878 break;
6879 clock_info = (union pplib_clock_info *)
6880 ((u8 *)&clock_info_array->clockInfo[0] +
6881 (clock_array_index * clock_info_array->ucEntrySize));
6882 si_parse_pplib_clock_info(rdev,
6883 &rdev->pm.dpm.ps[i], k,
6884 clock_info);
6885 k++;
6886 }
6887 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6888 }
6889 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6890
6891 /* fill in the vce power states */
6892 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6893 u32 sclk, mclk;
6894 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6895 clock_info = (union pplib_clock_info *)
6896 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6897 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6898 sclk |= clock_info->si.ucEngineClockHigh << 16;
6899 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6900 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6901 rdev->pm.dpm.vce_states[i].sclk = sclk;
6902 rdev->pm.dpm.vce_states[i].mclk = mclk;
6903 }
6904
6905 return 0;
6906 }
6907
6908 int si_dpm_init(struct radeon_device *rdev)
6909 {
6910 struct rv7xx_power_info *pi;
6911 struct evergreen_power_info *eg_pi;
6912 struct ni_power_info *ni_pi;
6913 struct si_power_info *si_pi;
6914 struct atom_clock_dividers dividers;
6915 int ret;
6916 u32 mask;
6917
6918 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6919 if (si_pi == NULL)
6920 return -ENOMEM;
6921 rdev->pm.dpm.priv = si_pi;
6922 ni_pi = &si_pi->ni;
6923 eg_pi = &ni_pi->eg;
6924 pi = &eg_pi->rv7xx;
6925
6926 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6927 if (ret)
6928 si_pi->sys_pcie_mask = 0;
6929 else
6930 si_pi->sys_pcie_mask = mask;
6931 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6932 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6933
6934 si_set_max_cu_value(rdev);
6935
6936 rv770_get_max_vddc(rdev);
6937 si_get_leakage_vddc(rdev);
6938 si_patch_dependency_tables_based_on_leakage(rdev);
6939
6940 pi->acpi_vddc = 0;
6941 eg_pi->acpi_vddci = 0;
6942 pi->min_vddc_in_table = 0;
6943 pi->max_vddc_in_table = 0;
6944
6945 ret = r600_get_platform_caps(rdev);
6946 if (ret)
6947 return ret;
6948
6949 ret = r600_parse_extended_power_table(rdev);
6950 if (ret)
6951 return ret;
6952
6953 ret = si_parse_power_table(rdev);
6954 if (ret)
6955 return ret;
6956
6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6958 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6959 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6960 r600_free_extended_power_table(rdev);
6961 return -ENOMEM;
6962 }
6963 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6964 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6965 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6966 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6967 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6972
6973 if (rdev->pm.dpm.voltage_response_time == 0)
6974 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6975 if (rdev->pm.dpm.backbias_response_time == 0)
6976 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6977
6978 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6979 0, false, &dividers);
6980 if (ret)
6981 pi->ref_div = dividers.ref_div + 1;
6982 else
6983 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6984
6985 eg_pi->smu_uvd_hs = false;
6986
6987 pi->mclk_strobe_mode_threshold = 40000;
6988 if (si_is_special_1gb_platform(rdev))
6989 pi->mclk_stutter_mode_threshold = 0;
6990 else
6991 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6992 pi->mclk_edc_enable_threshold = 40000;
6993 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6994
6995 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6996
6997 pi->voltage_control =
6998 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6999 VOLTAGE_OBJ_GPIO_LUT);
7000 if (!pi->voltage_control) {
7001 si_pi->voltage_control_svi2 =
7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7003 VOLTAGE_OBJ_SVID2);
7004 if (si_pi->voltage_control_svi2)
7005 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7006 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7007 }
7008
7009 pi->mvdd_control =
7010 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7011 VOLTAGE_OBJ_GPIO_LUT);
7012
7013 eg_pi->vddci_control =
7014 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7015 VOLTAGE_OBJ_GPIO_LUT);
7016 if (!eg_pi->vddci_control)
7017 si_pi->vddci_control_svi2 =
7018 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7019 VOLTAGE_OBJ_SVID2);
7020
7021 si_pi->vddc_phase_shed_control =
7022 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7023 VOLTAGE_OBJ_PHASE_LUT);
7024
7025 rv770_get_engine_memory_ss(rdev);
7026
7027 pi->asi = RV770_ASI_DFLT;
7028 pi->pasi = CYPRESS_HASI_DFLT;
7029 pi->vrc = SISLANDS_VRC_DFLT;
7030
7031 pi->gfx_clock_gating = true;
7032
7033 eg_pi->sclk_deep_sleep = true;
7034 si_pi->sclk_deep_sleep_above_low = false;
7035
7036 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7037 pi->thermal_protection = true;
7038 else
7039 pi->thermal_protection = false;
7040
7041 eg_pi->dynamic_ac_timing = true;
7042
7043 eg_pi->light_sleep = true;
7044 #if defined(CONFIG_ACPI)
7045 eg_pi->pcie_performance_request =
7046 radeon_acpi_is_pcie_performance_request_supported(rdev);
7047 #else
7048 eg_pi->pcie_performance_request = false;
7049 #endif
7050
7051 si_pi->sram_end = SMC_RAM_END;
7052
7053 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7054 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7055 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7056 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7057 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7058 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7059 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7060
7061 si_initialize_powertune_defaults(rdev);
7062
7063 /* make sure dc limits are valid */
7064 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7065 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7066 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7067 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7068
7069 si_pi->fan_ctrl_is_in_default_mode = true;
7070
7071 return 0;
7072 }
7073
7074 void si_dpm_fini(struct radeon_device *rdev)
7075 {
7076 int i;
7077
7078 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7079 kfree(rdev->pm.dpm.ps[i].ps_priv);
7080 }
7081 kfree(rdev->pm.dpm.ps);
7082 kfree(rdev->pm.dpm.priv);
7083 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7084 r600_free_extended_power_table(rdev);
7085 }
7086
7087 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7088 struct seq_file *m)
7089 {
7090 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7091 struct radeon_ps *rps = &eg_pi->current_rps;
7092 struct ni_ps *ps = ni_get_ps(rps);
7093 struct rv7xx_pl *pl;
7094 u32 current_index =
7095 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7096 CURRENT_STATE_INDEX_SHIFT;
7097
7098 if (current_index >= ps->performance_level_count) {
7099 seq_printf(m, "invalid dpm profile %d\n", current_index);
7100 } else {
7101 pl = &ps->performance_levels[current_index];
7102 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7103 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7104 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7105 }
7106 }
7107
7108 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7109 {
7110 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7111 struct radeon_ps *rps = &eg_pi->current_rps;
7112 struct ni_ps *ps = ni_get_ps(rps);
7113 struct rv7xx_pl *pl;
7114 u32 current_index =
7115 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7116 CURRENT_STATE_INDEX_SHIFT;
7117
7118 if (current_index >= ps->performance_level_count) {
7119 return 0;
7120 } else {
7121 pl = &ps->performance_levels[current_index];
7122 return pl->sclk;
7123 }
7124 }
7125
7126 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7127 {
7128 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7129 struct radeon_ps *rps = &eg_pi->current_rps;
7130 struct ni_ps *ps = ni_get_ps(rps);
7131 struct rv7xx_pl *pl;
7132 u32 current_index =
7133 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7134 CURRENT_STATE_INDEX_SHIFT;
7135
7136 if (current_index >= ps->performance_level_count) {
7137 return 0;
7138 } else {
7139 pl = &ps->performance_levels[current_index];
7140 return pl->mclk;
7141 }
7142 }
Linux kernel - Deliverables
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