Merge tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / rockchip / inno_hdmi.h
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Zheng Yang <zhengyang@rock-chips.com>
4 * Yakir Yang <ykk@rock-chips.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef __INNO_HDMI_H__
17 #define __INNO_HDMI_H__
18
19 #define DDC_SEGMENT_ADDR 0x30
20
21 enum PWR_MODE {
22 NORMAL,
23 LOWER_PWR,
24 };
25
26 #define HDMI_SCL_RATE (100*1000)
27 #define DDC_BUS_FREQ_L 0x4b
28 #define DDC_BUS_FREQ_H 0x4c
29
30 #define HDMI_SYS_CTRL 0x00
31 #define m_RST_ANALOG (1 << 6)
32 #define v_RST_ANALOG (0 << 6)
33 #define v_NOT_RST_ANALOG (1 << 6)
34 #define m_RST_DIGITAL (1 << 5)
35 #define v_RST_DIGITAL (0 << 5)
36 #define v_NOT_RST_DIGITAL (1 << 5)
37 #define m_REG_CLK_INV (1 << 4)
38 #define v_REG_CLK_NOT_INV (0 << 4)
39 #define v_REG_CLK_INV (1 << 4)
40 #define m_VCLK_INV (1 << 3)
41 #define v_VCLK_NOT_INV (0 << 3)
42 #define v_VCLK_INV (1 << 3)
43 #define m_REG_CLK_SOURCE (1 << 2)
44 #define v_REG_CLK_SOURCE_TMDS (0 << 2)
45 #define v_REG_CLK_SOURCE_SYS (1 << 2)
46 #define m_POWER (1 << 1)
47 #define v_PWR_ON (0 << 1)
48 #define v_PWR_OFF (1 << 1)
49 #define m_INT_POL (1 << 0)
50 #define v_INT_POL_HIGH 1
51 #define v_INT_POL_LOW 0
52
53 #define HDMI_VIDEO_CONTRL1 0x01
54 #define m_VIDEO_INPUT_FORMAT (7 << 1)
55 #define m_DE_SOURCE (1 << 0)
56 #define v_VIDEO_INPUT_FORMAT(n) (n << 1)
57 #define v_DE_EXTERNAL 1
58 #define v_DE_INTERNAL 0
59 enum {
60 VIDEO_INPUT_SDR_RGB444 = 0,
61 VIDEO_INPUT_DDR_RGB444 = 5,
62 VIDEO_INPUT_DDR_YCBCR422 = 6
63 };
64
65 #define HDMI_VIDEO_CONTRL2 0x02
66 #define m_VIDEO_OUTPUT_COLOR (3 << 6)
67 #define m_VIDEO_INPUT_BITS (3 << 4)
68 #define m_VIDEO_INPUT_CSP (1 << 0)
69 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
70 #define v_VIDEO_INPUT_BITS(n) (n << 4)
71 #define v_VIDEO_INPUT_CSP(n) (n << 0)
72 enum {
73 VIDEO_INPUT_12BITS = 0,
74 VIDEO_INPUT_10BITS = 1,
75 VIDEO_INPUT_REVERT = 2,
76 VIDEO_INPUT_8BITS = 3,
77 };
78
79 #define HDMI_VIDEO_CONTRL 0x03
80 #define m_VIDEO_AUTO_CSC (1 << 7)
81 #define v_VIDEO_AUTO_CSC(n) (n << 7)
82 #define m_VIDEO_C0_C2_SWAP (1 << 0)
83 #define v_VIDEO_C0_C2_SWAP(n) (n << 0)
84 enum {
85 C0_C2_CHANGE_ENABLE = 0,
86 C0_C2_CHANGE_DISABLE = 1,
87 AUTO_CSC_DISABLE = 0,
88 AUTO_CSC_ENABLE = 1,
89 };
90
91 #define HDMI_VIDEO_CONTRL3 0x04
92 #define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
93 #define m_SOF (1 << 3)
94 #define m_COLOR_RANGE (1 << 2)
95 #define m_CSC (1 << 0)
96 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
97 #define v_SOF_ENABLE (0 << 3)
98 #define v_SOF_DISABLE (1 << 3)
99 #define v_COLOR_RANGE_FULL (1 << 2)
100 #define v_COLOR_RANGE_LIMITED (0 << 2)
101 #define v_CSC_ENABLE 1
102 #define v_CSC_DISABLE 0
103
104 #define HDMI_AV_MUTE 0x05
105 #define m_AVMUTE_CLEAR (1 << 7)
106 #define m_AVMUTE_ENABLE (1 << 6)
107 #define m_AUDIO_MUTE (1 << 1)
108 #define m_VIDEO_BLACK (1 << 0)
109 #define v_AVMUTE_CLEAR(n) (n << 7)
110 #define v_AVMUTE_ENABLE(n) (n << 6)
111 #define v_AUDIO_MUTE(n) (n << 1)
112 #define v_VIDEO_MUTE(n) (n << 0)
113
114 #define HDMI_VIDEO_TIMING_CTL 0x08
115 #define v_HSYNC_POLARITY(n) (n << 3)
116 #define v_VSYNC_POLARITY(n) (n << 2)
117 #define v_INETLACE(n) (n << 1)
118 #define v_EXTERANL_VIDEO(n) (n << 0)
119
120 #define HDMI_VIDEO_EXT_HTOTAL_L 0x09
121 #define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
122 #define HDMI_VIDEO_EXT_HBLANK_L 0x0b
123 #define HDMI_VIDEO_EXT_HBLANK_H 0x0c
124 #define HDMI_VIDEO_EXT_HDELAY_L 0x0d
125 #define HDMI_VIDEO_EXT_HDELAY_H 0x0e
126 #define HDMI_VIDEO_EXT_HDURATION_L 0x0f
127 #define HDMI_VIDEO_EXT_HDURATION_H 0x10
128 #define HDMI_VIDEO_EXT_VTOTAL_L 0x11
129 #define HDMI_VIDEO_EXT_VTOTAL_H 0x12
130 #define HDMI_VIDEO_EXT_VBLANK 0x13
131 #define HDMI_VIDEO_EXT_VDELAY 0x14
132 #define HDMI_VIDEO_EXT_VDURATION 0x15
133
134 #define HDMI_VIDEO_CSC_COEF 0x18
135
136 #define HDMI_AUDIO_CTRL1 0x35
137 enum {
138 CTS_SOURCE_INTERNAL = 0,
139 CTS_SOURCE_EXTERNAL = 1,
140 };
141 #define v_CTS_SOURCE(n) (n << 7)
142
143 enum {
144 DOWNSAMPLE_DISABLE = 0,
145 DOWNSAMPLE_1_2 = 1,
146 DOWNSAMPLE_1_4 = 2,
147 };
148 #define v_DOWN_SAMPLE(n) (n << 5)
149
150 enum {
151 AUDIO_SOURCE_IIS = 0,
152 AUDIO_SOURCE_SPDIF = 1,
153 };
154 #define v_AUDIO_SOURCE(n) (n << 3)
155
156 #define v_MCLK_ENABLE(n) (n << 2)
157 enum {
158 MCLK_128FS = 0,
159 MCLK_256FS = 1,
160 MCLK_384FS = 2,
161 MCLK_512FS = 3,
162 };
163 #define v_MCLK_RATIO(n) (n)
164
165 #define AUDIO_SAMPLE_RATE 0x37
166 enum {
167 AUDIO_32K = 0x3,
168 AUDIO_441K = 0x0,
169 AUDIO_48K = 0x2,
170 AUDIO_882K = 0x8,
171 AUDIO_96K = 0xa,
172 AUDIO_1764K = 0xc,
173 AUDIO_192K = 0xe,
174 };
175
176 #define AUDIO_I2S_MODE 0x38
177 enum {
178 I2S_CHANNEL_1_2 = 1,
179 I2S_CHANNEL_3_4 = 3,
180 I2S_CHANNEL_5_6 = 7,
181 I2S_CHANNEL_7_8 = 0xf
182 };
183 #define v_I2S_CHANNEL(n) ((n) << 2)
184 enum {
185 I2S_STANDARD = 0,
186 I2S_LEFT_JUSTIFIED = 1,
187 I2S_RIGHT_JUSTIFIED = 2,
188 };
189 #define v_I2S_MODE(n) (n)
190
191 #define AUDIO_I2S_MAP 0x39
192 #define AUDIO_I2S_SWAPS_SPDIF 0x3a
193 #define v_SPIDF_FREQ(n) (n)
194
195 #define N_32K 0x1000
196 #define N_441K 0x1880
197 #define N_882K 0x3100
198 #define N_1764K 0x6200
199 #define N_48K 0x1800
200 #define N_96K 0x3000
201 #define N_192K 0x6000
202
203 #define HDMI_AUDIO_CHANNEL_STATUS 0x3e
204 #define m_AUDIO_STATUS_NLPCM (1 << 7)
205 #define m_AUDIO_STATUS_USE (1 << 6)
206 #define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
207 #define m_AUDIO_STATUS_ADDITION (3 << 2)
208 #define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
209 #define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
210 #define AUDIO_N_H 0x3f
211 #define AUDIO_N_M 0x40
212 #define AUDIO_N_L 0x41
213
214 #define HDMI_AUDIO_CTS_H 0x45
215 #define HDMI_AUDIO_CTS_M 0x46
216 #define HDMI_AUDIO_CTS_L 0x47
217
218 #define HDMI_DDC_CLK_L 0x4b
219 #define HDMI_DDC_CLK_H 0x4c
220
221 #define HDMI_EDID_SEGMENT_POINTER 0x4d
222 #define HDMI_EDID_WORD_ADDR 0x4e
223 #define HDMI_EDID_FIFO_OFFSET 0x4f
224 #define HDMI_EDID_FIFO_ADDR 0x50
225
226 #define HDMI_PACKET_SEND_MANUAL 0x9c
227 #define HDMI_PACKET_SEND_AUTO 0x9d
228 #define m_PACKET_GCP_EN (1 << 7)
229 #define m_PACKET_MSI_EN (1 << 6)
230 #define m_PACKET_SDI_EN (1 << 5)
231 #define m_PACKET_VSI_EN (1 << 4)
232 #define v_PACKET_GCP_EN(n) ((n & 1) << 7)
233 #define v_PACKET_MSI_EN(n) ((n & 1) << 6)
234 #define v_PACKET_SDI_EN(n) ((n & 1) << 5)
235 #define v_PACKET_VSI_EN(n) ((n & 1) << 4)
236
237 #define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
238 enum {
239 INFOFRAME_VSI = 0x05,
240 INFOFRAME_AVI = 0x06,
241 INFOFRAME_AAI = 0x08,
242 };
243
244 #define HDMI_CONTROL_PACKET_ADDR 0xa0
245 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
246 enum {
247 AVI_COLOR_MODE_RGB = 0,
248 AVI_COLOR_MODE_YCBCR422 = 1,
249 AVI_COLOR_MODE_YCBCR444 = 2,
250 AVI_COLORIMETRY_NO_DATA = 0,
251
252 AVI_COLORIMETRY_SMPTE_170M = 1,
253 AVI_COLORIMETRY_ITU709 = 2,
254 AVI_COLORIMETRY_EXTENDED = 3,
255
256 AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
257 AVI_CODED_FRAME_ASPECT_4_3 = 1,
258 AVI_CODED_FRAME_ASPECT_16_9 = 2,
259
260 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
261 ACTIVE_ASPECT_RATE_4_3 = 0x09,
262 ACTIVE_ASPECT_RATE_16_9 = 0x0A,
263 ACTIVE_ASPECT_RATE_14_9 = 0x0B,
264 };
265
266 #define HDMI_HDCP_CTRL 0x52
267 #define m_HDMI_DVI (1 << 1)
268 #define v_HDMI_DVI(n) (n << 1)
269
270 #define HDMI_INTERRUPT_MASK1 0xc0
271 #define HDMI_INTERRUPT_STATUS1 0xc1
272 #define m_INT_ACTIVE_VSYNC (1 << 5)
273 #define m_INT_EDID_READY (1 << 2)
274
275 #define HDMI_INTERRUPT_MASK2 0xc2
276 #define HDMI_INTERRUPT_STATUS2 0xc3
277 #define m_INT_HDCP_ERR (1 << 7)
278 #define m_INT_BKSV_FLAG (1 << 6)
279 #define m_INT_HDCP_OK (1 << 4)
280
281 #define HDMI_STATUS 0xc8
282 #define m_HOTPLUG (1 << 7)
283 #define m_MASK_INT_HOTPLUG (1 << 5)
284 #define m_INT_HOTPLUG (1 << 1)
285 #define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
286
287 #define HDMI_COLORBAR 0xc9
288
289 #define HDMI_PHY_SYNC 0xce
290 #define HDMI_PHY_SYS_CTL 0xe0
291 #define m_TMDS_CLK_SOURCE (1 << 5)
292 #define v_TMDS_FROM_PLL (0 << 5)
293 #define v_TMDS_FROM_GEN (1 << 5)
294 #define m_PHASE_CLK (1 << 4)
295 #define v_DEFAULT_PHASE (0 << 4)
296 #define v_SYNC_PHASE (1 << 4)
297 #define m_TMDS_CURRENT_PWR (1 << 3)
298 #define v_TURN_ON_CURRENT (0 << 3)
299 #define v_CAT_OFF_CURRENT (1 << 3)
300 #define m_BANDGAP_PWR (1 << 2)
301 #define v_BANDGAP_PWR_UP (0 << 2)
302 #define v_BANDGAP_PWR_DOWN (1 << 2)
303 #define m_PLL_PWR (1 << 1)
304 #define v_PLL_PWR_UP (0 << 1)
305 #define v_PLL_PWR_DOWN (1 << 1)
306 #define m_TMDS_CHG_PWR (1 << 0)
307 #define v_TMDS_CHG_PWR_UP (0 << 0)
308 #define v_TMDS_CHG_PWR_DOWN (1 << 0)
309
310 #define HDMI_PHY_CHG_PWR 0xe1
311 #define v_CLK_CHG_PWR(n) ((n & 1) << 3)
312 #define v_DATA_CHG_PWR(n) ((n & 7) << 0)
313
314 #define HDMI_PHY_DRIVER 0xe2
315 #define v_CLK_MAIN_DRIVER(n) (n << 4)
316 #define v_DATA_MAIN_DRIVER(n) (n << 0)
317
318 #define HDMI_PHY_PRE_EMPHASIS 0xe3
319 #define v_PRE_EMPHASIS(n) ((n & 7) << 4)
320 #define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
321 #define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
322
323 #define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
324 #define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
325 #define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
326 #define v_FEEDBACK_DIV_HIGH(n) (n & 1)
327
328 #define HDMI_PHY_PRE_DIV_RATIO 0xed
329 #define v_PRE_DIV_RATIO(n) (n & 0x1f)
330
331 #define HDMI_CEC_CTRL 0xd0
332 #define m_ADJUST_FOR_HISENSE (1 << 6)
333 #define m_REJECT_RX_BROADCAST (1 << 5)
334 #define m_BUSFREETIME_ENABLE (1 << 2)
335 #define m_REJECT_RX (1 << 1)
336 #define m_START_TX (1 << 0)
337
338 #define HDMI_CEC_DATA 0xd1
339 #define HDMI_CEC_TX_OFFSET 0xd2
340 #define HDMI_CEC_RX_OFFSET 0xd3
341 #define HDMI_CEC_CLK_H 0xd4
342 #define HDMI_CEC_CLK_L 0xd5
343 #define HDMI_CEC_TX_LENGTH 0xd6
344 #define HDMI_CEC_RX_LENGTH 0xd7
345 #define HDMI_CEC_TX_INT_MASK 0xd8
346 #define m_TX_DONE (1 << 3)
347 #define m_TX_NOACK (1 << 2)
348 #define m_TX_BROADCAST_REJ (1 << 1)
349 #define m_TX_BUSNOTFREE (1 << 0)
350
351 #define HDMI_CEC_RX_INT_MASK 0xd9
352 #define m_RX_LA_ERR (1 << 4)
353 #define m_RX_GLITCH (1 << 3)
354 #define m_RX_DONE (1 << 0)
355
356 #define HDMI_CEC_TX_INT 0xda
357 #define HDMI_CEC_RX_INT 0xdb
358 #define HDMI_CEC_BUSFREETIME_L 0xdc
359 #define HDMI_CEC_BUSFREETIME_H 0xdd
360 #define HDMI_CEC_LOGICADDR 0xde
361
362 #endif /* __INNO_HDMI_H__ */
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