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Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
30
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_psr.h"
38 #include "rockchip_drm_vop.h"
39
40 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
41 vop_mask_write(x, off, mask, shift, v, write_mask, true)
42
43 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
44 vop_mask_write(x, off, mask, shift, v, write_mask, false)
45
46 #define REG_SET(x, base, reg, v, mode) \
47 __REG_SET_##mode(x, base + reg.offset, \
48 reg.mask, reg.shift, v, reg.write_mask)
49 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
50 __REG_SET_##mode(x, base + reg.offset, \
51 mask, reg.shift, v, reg.write_mask)
52
53 #define VOP_WIN_SET(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->name, v, RELAXED)
55 #define VOP_SCL_SET(x, win, name, v) \
56 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
57 #define VOP_SCL_SET_EXT(x, win, name, v) \
58 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
59 #define VOP_CTRL_SET(x, name, v) \
60 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
61
62 #define VOP_INTR_GET(vop, name) \
63 vop_read_reg(vop, 0, &vop->data->ctrl->name)
64
65 #define VOP_INTR_SET(vop, name, mask, v) \
66 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
67 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
68 do { \
69 int i, reg = 0, mask = 0; \
70 for (i = 0; i < vop->data->intr->nintrs; i++) { \
71 if (vop->data->intr->intrs[i] & type) { \
72 reg |= (v) << i; \
73 mask |= 1 << i; \
74 } \
75 } \
76 VOP_INTR_SET(vop, name, mask, reg); \
77 } while (0)
78 #define VOP_INTR_GET_TYPE(vop, name, type) \
79 vop_get_intr_type(vop, &vop->data->intr->name, type)
80
81 #define VOP_WIN_GET(x, win, name) \
82 vop_read_reg(x, win->base, &win->phy->name)
83
84 #define VOP_WIN_GET_YRGBADDR(vop, win) \
85 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
86
87 #define to_vop(x) container_of(x, struct vop, crtc)
88 #define to_vop_win(x) container_of(x, struct vop_win, base)
89 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
90
91 struct vop_plane_state {
92 struct drm_plane_state base;
93 int format;
94 dma_addr_t yrgb_mst;
95 bool enable;
96 };
97
98 struct vop_win {
99 struct drm_plane base;
100 const struct vop_win_data *data;
101 struct vop *vop;
102
103 /* protected by dev->event_lock */
104 bool enable;
105 dma_addr_t yrgb_mst;
106 };
107
108 struct vop {
109 struct drm_crtc crtc;
110 struct device *dev;
111 struct drm_device *drm_dev;
112 bool is_enabled;
113 bool vblank_active;
114
115 /* mutex vsync_ work */
116 struct mutex vsync_mutex;
117 bool vsync_work_pending;
118 struct completion dsp_hold_completion;
119 struct completion wait_update_complete;
120
121 /* protected by dev->event_lock */
122 struct drm_pending_vblank_event *event;
123
124 struct completion line_flag_completion;
125
126 const struct vop_data *data;
127
128 uint32_t *regsbak;
129 void __iomem *regs;
130
131 /* physical map length of vop register */
132 uint32_t len;
133
134 /* one time only one process allowed to config the register */
135 spinlock_t reg_lock;
136 /* lock vop irq reg */
137 spinlock_t irq_lock;
138
139 unsigned int irq;
140
141 /* vop AHP clk */
142 struct clk *hclk;
143 /* vop dclk */
144 struct clk *dclk;
145 /* vop share memory frequency */
146 struct clk *aclk;
147
148 /* vop dclk reset */
149 struct reset_control *dclk_rst;
150
151 struct vop_win win[];
152 };
153
154 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
155 {
156 writel(v, vop->regs + offset);
157 vop->regsbak[offset >> 2] = v;
158 }
159
160 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
161 {
162 return readl(vop->regs + offset);
163 }
164
165 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
166 const struct vop_reg *reg)
167 {
168 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
169 }
170
171 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
172 uint32_t mask, uint32_t shift, uint32_t v,
173 bool write_mask, bool relaxed)
174 {
175 if (!mask)
176 return;
177
178 if (write_mask) {
179 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
180 } else {
181 uint32_t cached_val = vop->regsbak[offset >> 2];
182
183 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
184 vop->regsbak[offset >> 2] = v;
185 }
186
187 if (relaxed)
188 writel_relaxed(v, vop->regs + offset);
189 else
190 writel(v, vop->regs + offset);
191 }
192
193 static inline uint32_t vop_get_intr_type(struct vop *vop,
194 const struct vop_reg *reg, int type)
195 {
196 uint32_t i, ret = 0;
197 uint32_t regs = vop_read_reg(vop, 0, reg);
198
199 for (i = 0; i < vop->data->intr->nintrs; i++) {
200 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
201 ret |= vop->data->intr->intrs[i];
202 }
203
204 return ret;
205 }
206
207 static inline void vop_cfg_done(struct vop *vop)
208 {
209 VOP_CTRL_SET(vop, cfg_done, 1);
210 }
211
212 static bool has_rb_swapped(uint32_t format)
213 {
214 switch (format) {
215 case DRM_FORMAT_XBGR8888:
216 case DRM_FORMAT_ABGR8888:
217 case DRM_FORMAT_BGR888:
218 case DRM_FORMAT_BGR565:
219 return true;
220 default:
221 return false;
222 }
223 }
224
225 static enum vop_data_format vop_convert_format(uint32_t format)
226 {
227 switch (format) {
228 case DRM_FORMAT_XRGB8888:
229 case DRM_FORMAT_ARGB8888:
230 case DRM_FORMAT_XBGR8888:
231 case DRM_FORMAT_ABGR8888:
232 return VOP_FMT_ARGB8888;
233 case DRM_FORMAT_RGB888:
234 case DRM_FORMAT_BGR888:
235 return VOP_FMT_RGB888;
236 case DRM_FORMAT_RGB565:
237 case DRM_FORMAT_BGR565:
238 return VOP_FMT_RGB565;
239 case DRM_FORMAT_NV12:
240 return VOP_FMT_YUV420SP;
241 case DRM_FORMAT_NV16:
242 return VOP_FMT_YUV422SP;
243 case DRM_FORMAT_NV24:
244 return VOP_FMT_YUV444SP;
245 default:
246 DRM_ERROR("unsupported format[%08x]\n", format);
247 return -EINVAL;
248 }
249 }
250
251 static bool is_yuv_support(uint32_t format)
252 {
253 switch (format) {
254 case DRM_FORMAT_NV12:
255 case DRM_FORMAT_NV16:
256 case DRM_FORMAT_NV24:
257 return true;
258 default:
259 return false;
260 }
261 }
262
263 static bool is_alpha_support(uint32_t format)
264 {
265 switch (format) {
266 case DRM_FORMAT_ARGB8888:
267 case DRM_FORMAT_ABGR8888:
268 return true;
269 default:
270 return false;
271 }
272 }
273
274 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
275 uint32_t dst, bool is_horizontal,
276 int vsu_mode, int *vskiplines)
277 {
278 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279
280 if (is_horizontal) {
281 if (mode == SCALE_UP)
282 val = GET_SCL_FT_BIC(src, dst);
283 else if (mode == SCALE_DOWN)
284 val = GET_SCL_FT_BILI_DN(src, dst);
285 } else {
286 if (mode == SCALE_UP) {
287 if (vsu_mode == SCALE_UP_BIL)
288 val = GET_SCL_FT_BILI_UP(src, dst);
289 else
290 val = GET_SCL_FT_BIC(src, dst);
291 } else if (mode == SCALE_DOWN) {
292 if (vskiplines) {
293 *vskiplines = scl_get_vskiplines(src, dst);
294 val = scl_get_bili_dn_vskip(src, dst,
295 *vskiplines);
296 } else {
297 val = GET_SCL_FT_BILI_DN(src, dst);
298 }
299 }
300 }
301
302 return val;
303 }
304
305 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
306 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
307 uint32_t dst_h, uint32_t pixel_format)
308 {
309 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
310 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
311 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
312 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
313 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
314 bool is_yuv = is_yuv_support(pixel_format);
315 uint16_t cbcr_src_w = src_w / hsub;
316 uint16_t cbcr_src_h = src_h / vsub;
317 uint16_t vsu_mode;
318 uint16_t lb_mode;
319 uint32_t val;
320 int vskiplines = 0;
321
322 if (dst_w > 3840) {
323 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
324 return;
325 }
326
327 if (!win->phy->scl->ext) {
328 VOP_SCL_SET(vop, win, scale_yrgb_x,
329 scl_cal_scale2(src_w, dst_w));
330 VOP_SCL_SET(vop, win, scale_yrgb_y,
331 scl_cal_scale2(src_h, dst_h));
332 if (is_yuv) {
333 VOP_SCL_SET(vop, win, scale_cbcr_x,
334 scl_cal_scale2(cbcr_src_w, dst_w));
335 VOP_SCL_SET(vop, win, scale_cbcr_y,
336 scl_cal_scale2(cbcr_src_h, dst_h));
337 }
338 return;
339 }
340
341 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
342 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
343
344 if (is_yuv) {
345 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
346 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
347 if (cbcr_hor_scl_mode == SCALE_DOWN)
348 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
349 else
350 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
351 } else {
352 if (yrgb_hor_scl_mode == SCALE_DOWN)
353 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
354 else
355 lb_mode = scl_vop_cal_lb_mode(src_w, false);
356 }
357
358 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
359 if (lb_mode == LB_RGB_3840X2) {
360 if (yrgb_ver_scl_mode != SCALE_NONE) {
361 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
362 return;
363 }
364 if (cbcr_ver_scl_mode != SCALE_NONE) {
365 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
366 return;
367 }
368 vsu_mode = SCALE_UP_BIL;
369 } else if (lb_mode == LB_RGB_2560X4) {
370 vsu_mode = SCALE_UP_BIL;
371 } else {
372 vsu_mode = SCALE_UP_BIC;
373 }
374
375 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
376 true, 0, NULL);
377 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
378 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
379 false, vsu_mode, &vskiplines);
380 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
381
382 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
383 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
384
385 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
386 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
387 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
388 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
389 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
390 if (is_yuv) {
391 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
392 dst_w, true, 0, NULL);
393 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
394 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
395 dst_h, false, vsu_mode, &vskiplines);
396 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
397
398 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
399 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
400 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
401 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
402 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
403 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
404 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
405 }
406 }
407
408 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
409 {
410 unsigned long flags;
411
412 if (WARN_ON(!vop->is_enabled))
413 return;
414
415 spin_lock_irqsave(&vop->irq_lock, flags);
416
417 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
418
419 spin_unlock_irqrestore(&vop->irq_lock, flags);
420 }
421
422 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
423 {
424 unsigned long flags;
425
426 if (WARN_ON(!vop->is_enabled))
427 return;
428
429 spin_lock_irqsave(&vop->irq_lock, flags);
430
431 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
432
433 spin_unlock_irqrestore(&vop->irq_lock, flags);
434 }
435
436 /*
437 * (1) each frame starts at the start of the Vsync pulse which is signaled by
438 * the "FRAME_SYNC" interrupt.
439 * (2) the active data region of each frame ends at dsp_vact_end
440 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
441 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
442 *
443 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
444 * Interrupts
445 * LINE_FLAG -------------------------------+
446 * FRAME_SYNC ----+ |
447 * | |
448 * v v
449 * | Vsync | Vbp | Vactive | Vfp |
450 * ^ ^ ^ ^
451 * | | | |
452 * | | | |
453 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
454 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
455 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
456 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
457 */
458 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
459 {
460 uint32_t line_flag_irq;
461 unsigned long flags;
462
463 spin_lock_irqsave(&vop->irq_lock, flags);
464
465 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
466
467 spin_unlock_irqrestore(&vop->irq_lock, flags);
468
469 return !!line_flag_irq;
470 }
471
472 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
473 {
474 unsigned long flags;
475
476 if (WARN_ON(!vop->is_enabled))
477 return;
478
479 spin_lock_irqsave(&vop->irq_lock, flags);
480
481 VOP_CTRL_SET(vop, line_flag_num[0], line_num);
482 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
483
484 spin_unlock_irqrestore(&vop->irq_lock, flags);
485 }
486
487 static void vop_line_flag_irq_disable(struct vop *vop)
488 {
489 unsigned long flags;
490
491 if (WARN_ON(!vop->is_enabled))
492 return;
493
494 spin_lock_irqsave(&vop->irq_lock, flags);
495
496 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
497
498 spin_unlock_irqrestore(&vop->irq_lock, flags);
499 }
500
501 static int vop_enable(struct drm_crtc *crtc)
502 {
503 struct vop *vop = to_vop(crtc);
504 int ret;
505
506 ret = pm_runtime_get_sync(vop->dev);
507 if (ret < 0) {
508 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
509 goto err_put_pm_runtime;
510 }
511
512 ret = clk_enable(vop->hclk);
513 if (WARN_ON(ret < 0))
514 goto err_put_pm_runtime;
515
516 ret = clk_enable(vop->dclk);
517 if (WARN_ON(ret < 0))
518 goto err_disable_hclk;
519
520 ret = clk_enable(vop->aclk);
521 if (WARN_ON(ret < 0))
522 goto err_disable_dclk;
523
524 /*
525 * Slave iommu shares power, irq and clock with vop. It was associated
526 * automatically with this master device via common driver code.
527 * Now that we have enabled the clock we attach it to the shared drm
528 * mapping.
529 */
530 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
531 if (ret) {
532 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
533 goto err_disable_aclk;
534 }
535
536 memcpy(vop->regs, vop->regsbak, vop->len);
537 /*
538 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
539 */
540 vop->is_enabled = true;
541
542 spin_lock(&vop->reg_lock);
543
544 VOP_CTRL_SET(vop, standby, 0);
545
546 spin_unlock(&vop->reg_lock);
547
548 enable_irq(vop->irq);
549
550 drm_crtc_vblank_on(crtc);
551
552 return 0;
553
554 err_disable_aclk:
555 clk_disable(vop->aclk);
556 err_disable_dclk:
557 clk_disable(vop->dclk);
558 err_disable_hclk:
559 clk_disable(vop->hclk);
560 err_put_pm_runtime:
561 pm_runtime_put_sync(vop->dev);
562 return ret;
563 }
564
565 static void vop_crtc_disable(struct drm_crtc *crtc)
566 {
567 struct vop *vop = to_vop(crtc);
568 int i;
569
570 WARN_ON(vop->event);
571
572 /*
573 * We need to make sure that all windows are disabled before we
574 * disable that crtc. Otherwise we might try to scan from a destroyed
575 * buffer later.
576 */
577 for (i = 0; i < vop->data->win_size; i++) {
578 struct vop_win *vop_win = &vop->win[i];
579 const struct vop_win_data *win = vop_win->data;
580
581 spin_lock(&vop->reg_lock);
582 VOP_WIN_SET(vop, win, enable, 0);
583 spin_unlock(&vop->reg_lock);
584 }
585
586 drm_crtc_vblank_off(crtc);
587
588 /*
589 * Vop standby will take effect at end of current frame,
590 * if dsp hold valid irq happen, it means standby complete.
591 *
592 * we must wait standby complete when we want to disable aclk,
593 * if not, memory bus maybe dead.
594 */
595 reinit_completion(&vop->dsp_hold_completion);
596 vop_dsp_hold_valid_irq_enable(vop);
597
598 spin_lock(&vop->reg_lock);
599
600 VOP_CTRL_SET(vop, standby, 1);
601
602 spin_unlock(&vop->reg_lock);
603
604 wait_for_completion(&vop->dsp_hold_completion);
605
606 vop_dsp_hold_valid_irq_disable(vop);
607
608 disable_irq(vop->irq);
609
610 vop->is_enabled = false;
611
612 /*
613 * vop standby complete, so iommu detach is safe.
614 */
615 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
616
617 clk_disable(vop->dclk);
618 clk_disable(vop->aclk);
619 clk_disable(vop->hclk);
620 pm_runtime_put(vop->dev);
621
622 if (crtc->state->event && !crtc->state->active) {
623 spin_lock_irq(&crtc->dev->event_lock);
624 drm_crtc_send_vblank_event(crtc, crtc->state->event);
625 spin_unlock_irq(&crtc->dev->event_lock);
626
627 crtc->state->event = NULL;
628 }
629 }
630
631 static void vop_plane_destroy(struct drm_plane *plane)
632 {
633 drm_plane_cleanup(plane);
634 }
635
636 static int vop_plane_prepare_fb(struct drm_plane *plane,
637 struct drm_plane_state *new_state)
638 {
639 if (plane->state->fb)
640 drm_framebuffer_reference(plane->state->fb);
641
642 return 0;
643 }
644
645 static void vop_plane_cleanup_fb(struct drm_plane *plane,
646 struct drm_plane_state *old_state)
647 {
648 if (old_state->fb)
649 drm_framebuffer_unreference(old_state->fb);
650 }
651
652 static int vop_plane_atomic_check(struct drm_plane *plane,
653 struct drm_plane_state *state)
654 {
655 struct drm_crtc *crtc = state->crtc;
656 struct drm_crtc_state *crtc_state;
657 struct drm_framebuffer *fb = state->fb;
658 struct vop_win *vop_win = to_vop_win(plane);
659 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
660 const struct vop_win_data *win = vop_win->data;
661 int ret;
662 struct drm_rect clip;
663 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
664 DRM_PLANE_HELPER_NO_SCALING;
665 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
666 DRM_PLANE_HELPER_NO_SCALING;
667
668 if (!crtc || !fb)
669 goto out_disable;
670
671 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
672 if (WARN_ON(!crtc_state))
673 return -EINVAL;
674
675 clip.x1 = 0;
676 clip.y1 = 0;
677 clip.x2 = crtc_state->adjusted_mode.hdisplay;
678 clip.y2 = crtc_state->adjusted_mode.vdisplay;
679
680 ret = drm_plane_helper_check_state(state, &clip,
681 min_scale, max_scale,
682 true, true);
683 if (ret)
684 return ret;
685
686 if (!state->visible)
687 goto out_disable;
688
689 vop_plane_state->format = vop_convert_format(fb->pixel_format);
690 if (vop_plane_state->format < 0)
691 return vop_plane_state->format;
692
693 /*
694 * Src.x1 can be odd when do clip, but yuv plane start point
695 * need align with 2 pixel.
696 */
697 if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2))
698 return -EINVAL;
699
700 vop_plane_state->enable = true;
701
702 return 0;
703
704 out_disable:
705 vop_plane_state->enable = false;
706 return 0;
707 }
708
709 static void vop_plane_atomic_disable(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
711 {
712 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
713 struct vop_win *vop_win = to_vop_win(plane);
714 const struct vop_win_data *win = vop_win->data;
715 struct vop *vop = to_vop(old_state->crtc);
716
717 if (!old_state->crtc)
718 return;
719
720 spin_lock_irq(&plane->dev->event_lock);
721 vop_win->enable = false;
722 vop_win->yrgb_mst = 0;
723 spin_unlock_irq(&plane->dev->event_lock);
724
725 spin_lock(&vop->reg_lock);
726
727 VOP_WIN_SET(vop, win, enable, 0);
728
729 spin_unlock(&vop->reg_lock);
730
731 vop_plane_state->enable = false;
732 }
733
734 static void vop_plane_atomic_update(struct drm_plane *plane,
735 struct drm_plane_state *old_state)
736 {
737 struct drm_plane_state *state = plane->state;
738 struct drm_crtc *crtc = state->crtc;
739 struct vop_win *vop_win = to_vop_win(plane);
740 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
741 const struct vop_win_data *win = vop_win->data;
742 struct vop *vop = to_vop(state->crtc);
743 struct drm_framebuffer *fb = state->fb;
744 unsigned int actual_w, actual_h;
745 unsigned int dsp_stx, dsp_sty;
746 uint32_t act_info, dsp_info, dsp_st;
747 struct drm_rect *src = &state->src;
748 struct drm_rect *dest = &state->dst;
749 struct drm_gem_object *obj, *uv_obj;
750 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
751 unsigned long offset;
752 dma_addr_t dma_addr;
753 uint32_t val;
754 bool rb_swap;
755
756 /*
757 * can't update plane when vop is disabled.
758 */
759 if (WARN_ON(!crtc))
760 return;
761
762 if (WARN_ON(!vop->is_enabled))
763 return;
764
765 if (!vop_plane_state->enable) {
766 vop_plane_atomic_disable(plane, old_state);
767 return;
768 }
769
770 obj = rockchip_fb_get_gem_obj(fb, 0);
771 rk_obj = to_rockchip_obj(obj);
772
773 actual_w = drm_rect_width(src) >> 16;
774 actual_h = drm_rect_height(src) >> 16;
775 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
776
777 dsp_info = (drm_rect_height(dest) - 1) << 16;
778 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
779
780 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
781 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
782 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
783
784 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
785 offset += (src->y1 >> 16) * fb->pitches[0];
786 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
787
788 spin_lock_irq(&plane->dev->event_lock);
789 vop_win->enable = true;
790 vop_win->yrgb_mst = vop_plane_state->yrgb_mst;
791 spin_unlock_irq(&plane->dev->event_lock);
792
793 spin_lock(&vop->reg_lock);
794
795 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
796 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
797 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
798 if (is_yuv_support(fb->pixel_format)) {
799 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
800 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
801 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
802
803 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
804 rk_uv_obj = to_rockchip_obj(uv_obj);
805
806 offset = (src->x1 >> 16) * bpp / hsub;
807 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
808
809 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
810 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
811 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
812 }
813
814 if (win->phy->scl)
815 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
816 drm_rect_width(dest), drm_rect_height(dest),
817 fb->pixel_format);
818
819 VOP_WIN_SET(vop, win, act_info, act_info);
820 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
821 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
822
823 rb_swap = has_rb_swapped(fb->pixel_format);
824 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
825
826 if (is_alpha_support(fb->pixel_format)) {
827 VOP_WIN_SET(vop, win, dst_alpha_ctl,
828 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
829 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
830 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
831 SRC_BLEND_M0(ALPHA_PER_PIX) |
832 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
833 SRC_FACTOR_M0(ALPHA_ONE);
834 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
835 } else {
836 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
837 }
838
839 VOP_WIN_SET(vop, win, enable, 1);
840 spin_unlock(&vop->reg_lock);
841 }
842
843 static const struct drm_plane_helper_funcs plane_helper_funcs = {
844 .prepare_fb = vop_plane_prepare_fb,
845 .cleanup_fb = vop_plane_cleanup_fb,
846 .atomic_check = vop_plane_atomic_check,
847 .atomic_update = vop_plane_atomic_update,
848 .atomic_disable = vop_plane_atomic_disable,
849 };
850
851 static void vop_atomic_plane_reset(struct drm_plane *plane)
852 {
853 struct vop_plane_state *vop_plane_state =
854 to_vop_plane_state(plane->state);
855
856 if (plane->state && plane->state->fb)
857 drm_framebuffer_unreference(plane->state->fb);
858
859 kfree(vop_plane_state);
860 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
861 if (!vop_plane_state)
862 return;
863
864 plane->state = &vop_plane_state->base;
865 plane->state->plane = plane;
866 }
867
868 static struct drm_plane_state *
869 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
870 {
871 struct vop_plane_state *old_vop_plane_state;
872 struct vop_plane_state *vop_plane_state;
873
874 if (WARN_ON(!plane->state))
875 return NULL;
876
877 old_vop_plane_state = to_vop_plane_state(plane->state);
878 vop_plane_state = kmemdup(old_vop_plane_state,
879 sizeof(*vop_plane_state), GFP_KERNEL);
880 if (!vop_plane_state)
881 return NULL;
882
883 __drm_atomic_helper_plane_duplicate_state(plane,
884 &vop_plane_state->base);
885
886 return &vop_plane_state->base;
887 }
888
889 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
890 struct drm_plane_state *state)
891 {
892 struct vop_plane_state *vop_state = to_vop_plane_state(state);
893
894 __drm_atomic_helper_plane_destroy_state(state);
895
896 kfree(vop_state);
897 }
898
899 static const struct drm_plane_funcs vop_plane_funcs = {
900 .update_plane = drm_atomic_helper_update_plane,
901 .disable_plane = drm_atomic_helper_disable_plane,
902 .destroy = vop_plane_destroy,
903 .reset = vop_atomic_plane_reset,
904 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
905 .atomic_destroy_state = vop_atomic_plane_destroy_state,
906 };
907
908 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
909 {
910 struct vop *vop = to_vop(crtc);
911 unsigned long flags;
912
913 if (WARN_ON(!vop->is_enabled))
914 return -EPERM;
915
916 spin_lock_irqsave(&vop->irq_lock, flags);
917
918 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
919
920 spin_unlock_irqrestore(&vop->irq_lock, flags);
921
922 rockchip_drm_psr_disable(&vop->crtc);
923
924 return 0;
925 }
926
927 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
928 {
929 struct vop *vop = to_vop(crtc);
930 unsigned long flags;
931
932 if (WARN_ON(!vop->is_enabled))
933 return;
934
935 spin_lock_irqsave(&vop->irq_lock, flags);
936
937 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
938
939 spin_unlock_irqrestore(&vop->irq_lock, flags);
940
941 rockchip_drm_psr_enable(&vop->crtc);
942 }
943
944 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
945 {
946 struct vop *vop = to_vop(crtc);
947
948 reinit_completion(&vop->wait_update_complete);
949 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
950 }
951
952 static const struct rockchip_crtc_funcs private_crtc_funcs = {
953 .enable_vblank = vop_crtc_enable_vblank,
954 .disable_vblank = vop_crtc_disable_vblank,
955 .wait_for_update = vop_crtc_wait_for_update,
956 };
957
958 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
959 const struct drm_display_mode *mode,
960 struct drm_display_mode *adjusted_mode)
961 {
962 struct vop *vop = to_vop(crtc);
963
964 adjusted_mode->clock =
965 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
966
967 return true;
968 }
969
970 static void vop_crtc_enable(struct drm_crtc *crtc)
971 {
972 struct vop *vop = to_vop(crtc);
973 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
974 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
975 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
976 u16 hdisplay = adjusted_mode->hdisplay;
977 u16 htotal = adjusted_mode->htotal;
978 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
979 u16 hact_end = hact_st + hdisplay;
980 u16 vdisplay = adjusted_mode->vdisplay;
981 u16 vtotal = adjusted_mode->vtotal;
982 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
983 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
984 u16 vact_end = vact_st + vdisplay;
985 uint32_t pin_pol, val;
986 int ret;
987
988 WARN_ON(vop->event);
989
990 ret = vop_enable(crtc);
991 if (ret) {
992 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
993 return;
994 }
995
996 /*
997 * If dclk rate is zero, mean that scanout is stop,
998 * we don't need wait any more.
999 */
1000 if (clk_get_rate(vop->dclk)) {
1001 /*
1002 * Rk3288 vop timing register is immediately, when configure
1003 * display timing on display time, may cause tearing.
1004 *
1005 * Vop standby will take effect at end of current frame,
1006 * if dsp hold valid irq happen, it means standby complete.
1007 *
1008 * mode set:
1009 * standby and wait complete --> |----
1010 * | display time
1011 * |----
1012 * |---> dsp hold irq
1013 * configure display timing --> |
1014 * standby exit |
1015 * | new frame start.
1016 */
1017
1018 reinit_completion(&vop->dsp_hold_completion);
1019 vop_dsp_hold_valid_irq_enable(vop);
1020
1021 spin_lock(&vop->reg_lock);
1022
1023 VOP_CTRL_SET(vop, standby, 1);
1024
1025 spin_unlock(&vop->reg_lock);
1026
1027 wait_for_completion(&vop->dsp_hold_completion);
1028
1029 vop_dsp_hold_valid_irq_disable(vop);
1030 }
1031
1032 pin_pol = 0x8;
1033 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1034 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1035 VOP_CTRL_SET(vop, pin_pol, pin_pol);
1036
1037 switch (s->output_type) {
1038 case DRM_MODE_CONNECTOR_LVDS:
1039 VOP_CTRL_SET(vop, rgb_en, 1);
1040 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
1041 break;
1042 case DRM_MODE_CONNECTOR_eDP:
1043 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
1044 VOP_CTRL_SET(vop, edp_en, 1);
1045 break;
1046 case DRM_MODE_CONNECTOR_HDMIA:
1047 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
1048 VOP_CTRL_SET(vop, hdmi_en, 1);
1049 break;
1050 case DRM_MODE_CONNECTOR_DSI:
1051 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
1052 VOP_CTRL_SET(vop, mipi_en, 1);
1053 break;
1054 default:
1055 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1056 s->output_type);
1057 }
1058 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1059
1060 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1061 val = hact_st << 16;
1062 val |= hact_end;
1063 VOP_CTRL_SET(vop, hact_st_end, val);
1064 VOP_CTRL_SET(vop, hpost_st_end, val);
1065
1066 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1067 val = vact_st << 16;
1068 val |= vact_end;
1069 VOP_CTRL_SET(vop, vact_st_end, val);
1070 VOP_CTRL_SET(vop, vpost_st_end, val);
1071
1072 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1073
1074 VOP_CTRL_SET(vop, standby, 0);
1075 }
1076
1077 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1078 struct drm_crtc_state *old_crtc_state)
1079 {
1080 struct vop *vop = to_vop(crtc);
1081
1082 if (WARN_ON(!vop->is_enabled))
1083 return;
1084
1085 spin_lock(&vop->reg_lock);
1086
1087 vop_cfg_done(vop);
1088
1089 spin_unlock(&vop->reg_lock);
1090 }
1091
1092 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1093 struct drm_crtc_state *old_crtc_state)
1094 {
1095 struct vop *vop = to_vop(crtc);
1096
1097 spin_lock_irq(&crtc->dev->event_lock);
1098 vop->vblank_active = true;
1099 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1100 WARN_ON(vop->event);
1101
1102 if (crtc->state->event) {
1103 vop->event = crtc->state->event;
1104 crtc->state->event = NULL;
1105 }
1106 spin_unlock_irq(&crtc->dev->event_lock);
1107 }
1108
1109 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1110 .enable = vop_crtc_enable,
1111 .disable = vop_crtc_disable,
1112 .mode_fixup = vop_crtc_mode_fixup,
1113 .atomic_flush = vop_crtc_atomic_flush,
1114 .atomic_begin = vop_crtc_atomic_begin,
1115 };
1116
1117 static void vop_crtc_destroy(struct drm_crtc *crtc)
1118 {
1119 drm_crtc_cleanup(crtc);
1120 }
1121
1122 static void vop_crtc_reset(struct drm_crtc *crtc)
1123 {
1124 if (crtc->state)
1125 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1126 kfree(crtc->state);
1127
1128 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1129 if (crtc->state)
1130 crtc->state->crtc = crtc;
1131 }
1132
1133 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1134 {
1135 struct rockchip_crtc_state *rockchip_state;
1136
1137 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1138 if (!rockchip_state)
1139 return NULL;
1140
1141 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1142 return &rockchip_state->base;
1143 }
1144
1145 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1146 struct drm_crtc_state *state)
1147 {
1148 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1149
1150 __drm_atomic_helper_crtc_destroy_state(&s->base);
1151 kfree(s);
1152 }
1153
1154 static const struct drm_crtc_funcs vop_crtc_funcs = {
1155 .set_config = drm_atomic_helper_set_config,
1156 .page_flip = drm_atomic_helper_page_flip,
1157 .destroy = vop_crtc_destroy,
1158 .reset = vop_crtc_reset,
1159 .atomic_duplicate_state = vop_crtc_duplicate_state,
1160 .atomic_destroy_state = vop_crtc_destroy_state,
1161 };
1162
1163 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1164 {
1165 dma_addr_t yrgb_mst;
1166
1167 if (!vop_win->enable)
1168 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
1169
1170 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1171
1172 return yrgb_mst == vop_win->yrgb_mst;
1173 }
1174
1175 static void vop_handle_vblank(struct vop *vop)
1176 {
1177 struct drm_device *drm = vop->drm_dev;
1178 struct drm_crtc *crtc = &vop->crtc;
1179 unsigned long flags;
1180 int i;
1181
1182 for (i = 0; i < vop->data->win_size; i++) {
1183 if (!vop_win_pending_is_complete(&vop->win[i]))
1184 return;
1185 }
1186
1187 spin_lock_irqsave(&drm->event_lock, flags);
1188 if (vop->event) {
1189 drm_crtc_send_vblank_event(crtc, vop->event);
1190 vop->event = NULL;
1191
1192 }
1193 if (vop->vblank_active) {
1194 vop->vblank_active = false;
1195 drm_crtc_vblank_put(crtc);
1196 }
1197 spin_unlock_irqrestore(&drm->event_lock, flags);
1198
1199 if (!completion_done(&vop->wait_update_complete))
1200 complete(&vop->wait_update_complete);
1201 }
1202
1203 static irqreturn_t vop_isr(int irq, void *data)
1204 {
1205 struct vop *vop = data;
1206 struct drm_crtc *crtc = &vop->crtc;
1207 uint32_t active_irqs;
1208 unsigned long flags;
1209 int ret = IRQ_NONE;
1210
1211 /*
1212 * interrupt register has interrupt status, enable and clear bits, we
1213 * must hold irq_lock to avoid a race with enable/disable_vblank().
1214 */
1215 spin_lock_irqsave(&vop->irq_lock, flags);
1216
1217 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1218 /* Clear all active interrupt sources */
1219 if (active_irqs)
1220 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1221
1222 spin_unlock_irqrestore(&vop->irq_lock, flags);
1223
1224 /* This is expected for vop iommu irqs, since the irq is shared */
1225 if (!active_irqs)
1226 return IRQ_NONE;
1227
1228 if (active_irqs & DSP_HOLD_VALID_INTR) {
1229 complete(&vop->dsp_hold_completion);
1230 active_irqs &= ~DSP_HOLD_VALID_INTR;
1231 ret = IRQ_HANDLED;
1232 }
1233
1234 if (active_irqs & LINE_FLAG_INTR) {
1235 complete(&vop->line_flag_completion);
1236 active_irqs &= ~LINE_FLAG_INTR;
1237 ret = IRQ_HANDLED;
1238 }
1239
1240 if (active_irqs & FS_INTR) {
1241 drm_crtc_handle_vblank(crtc);
1242 vop_handle_vblank(vop);
1243 active_irqs &= ~FS_INTR;
1244 ret = IRQ_HANDLED;
1245 }
1246
1247 /* Unhandled irqs are spurious. */
1248 if (active_irqs)
1249 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1250 active_irqs);
1251
1252 return ret;
1253 }
1254
1255 static int vop_create_crtc(struct vop *vop)
1256 {
1257 const struct vop_data *vop_data = vop->data;
1258 struct device *dev = vop->dev;
1259 struct drm_device *drm_dev = vop->drm_dev;
1260 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1261 struct drm_crtc *crtc = &vop->crtc;
1262 struct device_node *port;
1263 int ret;
1264 int i;
1265
1266 /*
1267 * Create drm_plane for primary and cursor planes first, since we need
1268 * to pass them to drm_crtc_init_with_planes, which sets the
1269 * "possible_crtcs" to the newly initialized crtc.
1270 */
1271 for (i = 0; i < vop_data->win_size; i++) {
1272 struct vop_win *vop_win = &vop->win[i];
1273 const struct vop_win_data *win_data = vop_win->data;
1274
1275 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1276 win_data->type != DRM_PLANE_TYPE_CURSOR)
1277 continue;
1278
1279 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1280 0, &vop_plane_funcs,
1281 win_data->phy->data_formats,
1282 win_data->phy->nformats,
1283 win_data->type, NULL);
1284 if (ret) {
1285 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1286 ret);
1287 goto err_cleanup_planes;
1288 }
1289
1290 plane = &vop_win->base;
1291 drm_plane_helper_add(plane, &plane_helper_funcs);
1292 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1293 primary = plane;
1294 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1295 cursor = plane;
1296 }
1297
1298 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1299 &vop_crtc_funcs, NULL);
1300 if (ret)
1301 goto err_cleanup_planes;
1302
1303 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1304
1305 /*
1306 * Create drm_planes for overlay windows with possible_crtcs restricted
1307 * to the newly created crtc.
1308 */
1309 for (i = 0; i < vop_data->win_size; i++) {
1310 struct vop_win *vop_win = &vop->win[i];
1311 const struct vop_win_data *win_data = vop_win->data;
1312 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1313
1314 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1315 continue;
1316
1317 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1318 possible_crtcs,
1319 &vop_plane_funcs,
1320 win_data->phy->data_formats,
1321 win_data->phy->nformats,
1322 win_data->type, NULL);
1323 if (ret) {
1324 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1325 ret);
1326 goto err_cleanup_crtc;
1327 }
1328 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1329 }
1330
1331 port = of_get_child_by_name(dev->of_node, "port");
1332 if (!port) {
1333 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1334 dev->of_node->full_name);
1335 ret = -ENOENT;
1336 goto err_cleanup_crtc;
1337 }
1338
1339 init_completion(&vop->dsp_hold_completion);
1340 init_completion(&vop->wait_update_complete);
1341 init_completion(&vop->line_flag_completion);
1342 crtc->port = port;
1343 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1344
1345 return 0;
1346
1347 err_cleanup_crtc:
1348 drm_crtc_cleanup(crtc);
1349 err_cleanup_planes:
1350 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1351 head)
1352 drm_plane_cleanup(plane);
1353 return ret;
1354 }
1355
1356 static void vop_destroy_crtc(struct vop *vop)
1357 {
1358 struct drm_crtc *crtc = &vop->crtc;
1359 struct drm_device *drm_dev = vop->drm_dev;
1360 struct drm_plane *plane, *tmp;
1361
1362 rockchip_unregister_crtc_funcs(crtc);
1363 of_node_put(crtc->port);
1364
1365 /*
1366 * We need to cleanup the planes now. Why?
1367 *
1368 * The planes are "&vop->win[i].base". That means the memory is
1369 * all part of the big "struct vop" chunk of memory. That memory
1370 * was devm allocated and associated with this component. We need to
1371 * free it ourselves before vop_unbind() finishes.
1372 */
1373 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1374 head)
1375 vop_plane_destroy(plane);
1376
1377 /*
1378 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1379 * references the CRTC.
1380 */
1381 drm_crtc_cleanup(crtc);
1382 }
1383
1384 static int vop_initial(struct vop *vop)
1385 {
1386 const struct vop_data *vop_data = vop->data;
1387 const struct vop_reg_data *init_table = vop_data->init_table;
1388 struct reset_control *ahb_rst;
1389 int i, ret;
1390
1391 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1392 if (IS_ERR(vop->hclk)) {
1393 dev_err(vop->dev, "failed to get hclk source\n");
1394 return PTR_ERR(vop->hclk);
1395 }
1396 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1397 if (IS_ERR(vop->aclk)) {
1398 dev_err(vop->dev, "failed to get aclk source\n");
1399 return PTR_ERR(vop->aclk);
1400 }
1401 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1402 if (IS_ERR(vop->dclk)) {
1403 dev_err(vop->dev, "failed to get dclk source\n");
1404 return PTR_ERR(vop->dclk);
1405 }
1406
1407 ret = clk_prepare(vop->dclk);
1408 if (ret < 0) {
1409 dev_err(vop->dev, "failed to prepare dclk\n");
1410 return ret;
1411 }
1412
1413 /* Enable both the hclk and aclk to setup the vop */
1414 ret = clk_prepare_enable(vop->hclk);
1415 if (ret < 0) {
1416 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1417 goto err_unprepare_dclk;
1418 }
1419
1420 ret = clk_prepare_enable(vop->aclk);
1421 if (ret < 0) {
1422 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1423 goto err_disable_hclk;
1424 }
1425
1426 /*
1427 * do hclk_reset, reset all vop registers.
1428 */
1429 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1430 if (IS_ERR(ahb_rst)) {
1431 dev_err(vop->dev, "failed to get ahb reset\n");
1432 ret = PTR_ERR(ahb_rst);
1433 goto err_disable_aclk;
1434 }
1435 reset_control_assert(ahb_rst);
1436 usleep_range(10, 20);
1437 reset_control_deassert(ahb_rst);
1438
1439 memcpy(vop->regsbak, vop->regs, vop->len);
1440
1441 for (i = 0; i < vop_data->table_size; i++)
1442 vop_writel(vop, init_table[i].offset, init_table[i].value);
1443
1444 for (i = 0; i < vop_data->win_size; i++) {
1445 const struct vop_win_data *win = &vop_data->win[i];
1446
1447 VOP_WIN_SET(vop, win, enable, 0);
1448 }
1449
1450 vop_cfg_done(vop);
1451
1452 /*
1453 * do dclk_reset, let all config take affect.
1454 */
1455 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1456 if (IS_ERR(vop->dclk_rst)) {
1457 dev_err(vop->dev, "failed to get dclk reset\n");
1458 ret = PTR_ERR(vop->dclk_rst);
1459 goto err_disable_aclk;
1460 }
1461 reset_control_assert(vop->dclk_rst);
1462 usleep_range(10, 20);
1463 reset_control_deassert(vop->dclk_rst);
1464
1465 clk_disable(vop->hclk);
1466 clk_disable(vop->aclk);
1467
1468 vop->is_enabled = false;
1469 vop->vblank_active = false;
1470
1471 return 0;
1472
1473 err_disable_aclk:
1474 clk_disable_unprepare(vop->aclk);
1475 err_disable_hclk:
1476 clk_disable_unprepare(vop->hclk);
1477 err_unprepare_dclk:
1478 clk_unprepare(vop->dclk);
1479 return ret;
1480 }
1481
1482 /*
1483 * Initialize the vop->win array elements.
1484 */
1485 static void vop_win_init(struct vop *vop)
1486 {
1487 const struct vop_data *vop_data = vop->data;
1488 unsigned int i;
1489
1490 for (i = 0; i < vop_data->win_size; i++) {
1491 struct vop_win *vop_win = &vop->win[i];
1492 const struct vop_win_data *win_data = &vop_data->win[i];
1493
1494 vop_win->data = win_data;
1495 vop_win->vop = vop;
1496 }
1497 }
1498
1499 /**
1500 * rockchip_drm_wait_line_flag - acqiure the give line flag event
1501 * @crtc: CRTC to enable line flag
1502 * @line_num: interested line number
1503 * @mstimeout: millisecond for timeout
1504 *
1505 * Driver would hold here until the interested line flag interrupt have
1506 * happened or timeout to wait.
1507 *
1508 * Returns:
1509 * Zero on success, negative errno on failure.
1510 */
1511 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
1512 unsigned int mstimeout)
1513 {
1514 struct vop *vop = to_vop(crtc);
1515 unsigned long jiffies_left;
1516
1517 if (!crtc || !vop->is_enabled)
1518 return -ENODEV;
1519
1520 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
1521 return -EINVAL;
1522
1523 if (vop_line_flag_irq_is_enabled(vop))
1524 return -EBUSY;
1525
1526 reinit_completion(&vop->line_flag_completion);
1527 vop_line_flag_irq_enable(vop, line_num);
1528
1529 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1530 msecs_to_jiffies(mstimeout));
1531 vop_line_flag_irq_disable(vop);
1532
1533 if (jiffies_left == 0) {
1534 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1535 return -ETIMEDOUT;
1536 }
1537
1538 return 0;
1539 }
1540 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
1541
1542 static int vop_bind(struct device *dev, struct device *master, void *data)
1543 {
1544 struct platform_device *pdev = to_platform_device(dev);
1545 const struct vop_data *vop_data;
1546 struct drm_device *drm_dev = data;
1547 struct vop *vop;
1548 struct resource *res;
1549 size_t alloc_size;
1550 int ret, irq;
1551
1552 vop_data = of_device_get_match_data(dev);
1553 if (!vop_data)
1554 return -ENODEV;
1555
1556 /* Allocate vop struct and its vop_win array */
1557 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1558 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1559 if (!vop)
1560 return -ENOMEM;
1561
1562 vop->dev = dev;
1563 vop->data = vop_data;
1564 vop->drm_dev = drm_dev;
1565 dev_set_drvdata(dev, vop);
1566
1567 vop_win_init(vop);
1568
1569 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1570 vop->len = resource_size(res);
1571 vop->regs = devm_ioremap_resource(dev, res);
1572 if (IS_ERR(vop->regs))
1573 return PTR_ERR(vop->regs);
1574
1575 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1576 if (!vop->regsbak)
1577 return -ENOMEM;
1578
1579 ret = vop_initial(vop);
1580 if (ret < 0) {
1581 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1582 return ret;
1583 }
1584
1585 irq = platform_get_irq(pdev, 0);
1586 if (irq < 0) {
1587 dev_err(dev, "cannot find irq for vop\n");
1588 return irq;
1589 }
1590 vop->irq = (unsigned int)irq;
1591
1592 spin_lock_init(&vop->reg_lock);
1593 spin_lock_init(&vop->irq_lock);
1594
1595 mutex_init(&vop->vsync_mutex);
1596
1597 ret = devm_request_irq(dev, vop->irq, vop_isr,
1598 IRQF_SHARED, dev_name(dev), vop);
1599 if (ret)
1600 return ret;
1601
1602 /* IRQ is initially disabled; it gets enabled in power_on */
1603 disable_irq(vop->irq);
1604
1605 ret = vop_create_crtc(vop);
1606 if (ret)
1607 return ret;
1608
1609 pm_runtime_enable(&pdev->dev);
1610
1611 return 0;
1612 }
1613
1614 static void vop_unbind(struct device *dev, struct device *master, void *data)
1615 {
1616 struct vop *vop = dev_get_drvdata(dev);
1617
1618 pm_runtime_disable(dev);
1619 vop_destroy_crtc(vop);
1620 }
1621
1622 const struct component_ops vop_component_ops = {
1623 .bind = vop_bind,
1624 .unbind = vop_unbind,
1625 };
1626 EXPORT_SYMBOL_GPL(vop_component_ops);
Linux kernel - Deliverables
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