2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include "drm_flip_work.h"
19 #include <drm/drm_plane_helper.h>
20 #include <drm/drm_atomic_helper.h>
22 #include "tilcdc_drv.h"
23 #include "tilcdc_regs.h"
25 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
30 struct drm_plane primary
;
31 const struct tilcdc_panel_info
*info
;
32 struct drm_pending_vblank_event
*event
;
34 wait_queue_head_t frame_done_wq
;
40 struct drm_framebuffer
*curr_fb
;
41 struct drm_framebuffer
*next_fb
;
43 /* for deferred fb unref's: */
44 struct drm_flip_work unref_work
;
46 /* Only set if an external encoder is connected */
47 bool simulate_vesa_sync
;
52 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
54 static void unref_worker(struct drm_flip_work
*work
, void *val
)
56 struct tilcdc_crtc
*tilcdc_crtc
=
57 container_of(work
, struct tilcdc_crtc
, unref_work
);
58 struct drm_device
*dev
= tilcdc_crtc
->base
.dev
;
60 mutex_lock(&dev
->mode_config
.mutex
);
61 drm_framebuffer_unreference(val
);
62 mutex_unlock(&dev
->mode_config
.mutex
);
65 static void set_scanout(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
)
67 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
68 struct drm_device
*dev
= crtc
->dev
;
69 struct drm_gem_cma_object
*gem
;
70 unsigned int depth
, bpp
;
71 dma_addr_t start
, end
;
72 u64 dma_base_and_ceiling
;
74 drm_fb_get_bpp_depth(fb
->pixel_format
, &depth
, &bpp
);
75 gem
= drm_fb_cma_get_gem_obj(fb
, 0);
77 start
= gem
->paddr
+ fb
->offsets
[0] +
78 crtc
->y
* fb
->pitches
[0] +
81 end
= start
+ (crtc
->mode
.vdisplay
* fb
->pitches
[0]);
83 /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
84 * with a single insruction, if available. This should make it more
85 * unlikely that LCDC would fetch the DMA addresses in the middle of
88 dma_base_and_ceiling
= (u64
)(end
- 1) << 32 | start
;
89 tilcdc_write64(dev
, LCDC_DMA_FB_BASE_ADDR_0_REG
, dma_base_and_ceiling
);
91 if (tilcdc_crtc
->curr_fb
)
92 drm_flip_work_queue(&tilcdc_crtc
->unref_work
,
93 tilcdc_crtc
->curr_fb
);
95 tilcdc_crtc
->curr_fb
= fb
;
98 static void tilcdc_crtc_enable_irqs(struct drm_device
*dev
)
100 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
102 tilcdc_clear_irqstatus(dev
, 0xffffffff);
104 if (priv
->rev
== 1) {
105 tilcdc_set(dev
, LCDC_RASTER_CTRL_REG
,
106 LCDC_V1_UNDERFLOW_INT_ENA
);
107 tilcdc_set(dev
, LCDC_DMA_CTRL_REG
,
108 LCDC_V1_END_OF_FRAME_INT_ENA
);
110 tilcdc_write(dev
, LCDC_INT_ENABLE_SET_REG
,
111 LCDC_V2_UNDERFLOW_INT_ENA
|
112 LCDC_V2_END_OF_FRAME0_INT_ENA
|
113 LCDC_FRAME_DONE
| LCDC_SYNC_LOST
);
117 static void tilcdc_crtc_disable_irqs(struct drm_device
*dev
)
119 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
121 /* disable irqs that we might have enabled: */
122 if (priv
->rev
== 1) {
123 tilcdc_clear(dev
, LCDC_RASTER_CTRL_REG
,
124 LCDC_V1_UNDERFLOW_INT_ENA
| LCDC_V1_PL_INT_ENA
);
125 tilcdc_clear(dev
, LCDC_DMA_CTRL_REG
,
126 LCDC_V1_END_OF_FRAME_INT_ENA
);
128 tilcdc_write(dev
, LCDC_INT_ENABLE_CLR_REG
,
129 LCDC_V2_UNDERFLOW_INT_ENA
| LCDC_V2_PL_INT_ENA
|
130 LCDC_V2_END_OF_FRAME0_INT_ENA
|
131 LCDC_FRAME_DONE
| LCDC_SYNC_LOST
);
135 static void reset(struct drm_crtc
*crtc
)
137 struct drm_device
*dev
= crtc
->dev
;
138 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
143 tilcdc_set(dev
, LCDC_CLK_RESET_REG
, LCDC_CLK_MAIN_RESET
);
144 usleep_range(250, 1000);
145 tilcdc_clear(dev
, LCDC_CLK_RESET_REG
, LCDC_CLK_MAIN_RESET
);
148 static void tilcdc_crtc_enable(struct drm_crtc
*crtc
)
150 struct drm_device
*dev
= crtc
->dev
;
151 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
153 if (tilcdc_crtc
->enabled
)
156 pm_runtime_get_sync(dev
->dev
);
160 tilcdc_crtc_enable_irqs(dev
);
162 tilcdc_clear(dev
, LCDC_DMA_CTRL_REG
, LCDC_DUAL_FRAME_BUFFER_ENABLE
);
163 tilcdc_set(dev
, LCDC_RASTER_CTRL_REG
, LCDC_PALETTE_LOAD_MODE(DATA_ONLY
));
164 tilcdc_set(dev
, LCDC_RASTER_CTRL_REG
, LCDC_RASTER_ENABLE
);
166 drm_crtc_vblank_on(crtc
);
168 tilcdc_crtc
->enabled
= true;
171 void tilcdc_crtc_disable(struct drm_crtc
*crtc
)
173 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
174 struct drm_device
*dev
= crtc
->dev
;
175 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
177 if (!tilcdc_crtc
->enabled
)
180 tilcdc_crtc
->frame_done
= false;
181 tilcdc_clear(dev
, LCDC_RASTER_CTRL_REG
, LCDC_RASTER_ENABLE
);
184 * if necessary wait for framedone irq which will still come
185 * before putting things to sleep..
187 if (priv
->rev
== 2) {
188 int ret
= wait_event_timeout(tilcdc_crtc
->frame_done_wq
,
189 tilcdc_crtc
->frame_done
,
190 msecs_to_jiffies(500));
192 dev_err(dev
->dev
, "%s: timeout waiting for framedone\n",
196 drm_crtc_vblank_off(crtc
);
198 tilcdc_crtc_disable_irqs(dev
);
200 pm_runtime_put_sync(dev
->dev
);
202 if (tilcdc_crtc
->next_fb
) {
203 drm_flip_work_queue(&tilcdc_crtc
->unref_work
,
204 tilcdc_crtc
->next_fb
);
205 tilcdc_crtc
->next_fb
= NULL
;
208 if (tilcdc_crtc
->curr_fb
) {
209 drm_flip_work_queue(&tilcdc_crtc
->unref_work
,
210 tilcdc_crtc
->curr_fb
);
211 tilcdc_crtc
->curr_fb
= NULL
;
214 drm_flip_work_commit(&tilcdc_crtc
->unref_work
, priv
->wq
);
215 tilcdc_crtc
->last_vblank
= ktime_set(0, 0);
217 tilcdc_crtc
->enabled
= false;
220 static bool tilcdc_crtc_is_on(struct drm_crtc
*crtc
)
222 return crtc
->state
&& crtc
->state
->enable
&& crtc
->state
->active
;
225 static void tilcdc_crtc_destroy(struct drm_crtc
*crtc
)
227 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
229 tilcdc_crtc_disable(crtc
);
231 of_node_put(crtc
->port
);
232 drm_crtc_cleanup(crtc
);
233 drm_flip_work_cleanup(&tilcdc_crtc
->unref_work
);
236 int tilcdc_crtc_update_fb(struct drm_crtc
*crtc
,
237 struct drm_framebuffer
*fb
,
238 struct drm_pending_vblank_event
*event
)
240 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
241 struct drm_device
*dev
= crtc
->dev
;
244 if (tilcdc_crtc
->event
) {
245 dev_err(dev
->dev
, "already pending page flip!\n");
249 drm_framebuffer_reference(fb
);
251 crtc
->primary
->fb
= fb
;
253 spin_lock_irqsave(&tilcdc_crtc
->irq_lock
, flags
);
255 if (crtc
->hwmode
.vrefresh
&& ktime_to_ns(tilcdc_crtc
->last_vblank
)) {
259 next_vblank
= ktime_add_us(tilcdc_crtc
->last_vblank
,
260 1000000 / crtc
->hwmode
.vrefresh
);
262 tdiff
= ktime_to_us(ktime_sub(next_vblank
, ktime_get()));
264 if (tdiff
< TILCDC_VBLANK_SAFETY_THRESHOLD_US
)
265 tilcdc_crtc
->next_fb
= fb
;
268 if (tilcdc_crtc
->next_fb
!= fb
)
269 set_scanout(crtc
, fb
);
271 tilcdc_crtc
->event
= event
;
273 spin_unlock_irqrestore(&tilcdc_crtc
->irq_lock
, flags
);
278 static bool tilcdc_crtc_mode_fixup(struct drm_crtc
*crtc
,
279 const struct drm_display_mode
*mode
,
280 struct drm_display_mode
*adjusted_mode
)
282 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
284 if (!tilcdc_crtc
->simulate_vesa_sync
)
288 * tilcdc does not generate VESA-compliant sync but aligns
289 * VS on the second edge of HS instead of first edge.
290 * We use adjusted_mode, to fixup sync by aligning both rising
291 * edges and add HSKEW offset to fix the sync.
293 adjusted_mode
->hskew
= mode
->hsync_end
- mode
->hsync_start
;
294 adjusted_mode
->flags
|= DRM_MODE_FLAG_HSKEW
;
296 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
) {
297 adjusted_mode
->flags
|= DRM_MODE_FLAG_PHSYNC
;
298 adjusted_mode
->flags
&= ~DRM_MODE_FLAG_NHSYNC
;
300 adjusted_mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
301 adjusted_mode
->flags
&= ~DRM_MODE_FLAG_PHSYNC
;
307 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
309 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
310 struct drm_device
*dev
= crtc
->dev
;
311 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
312 const struct tilcdc_panel_info
*info
= tilcdc_crtc
->info
;
313 uint32_t reg
, hbp
, hfp
, hsw
, vbp
, vfp
, vsw
;
314 struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
315 struct drm_framebuffer
*fb
= crtc
->primary
->state
->fb
;
323 /* Configure the Burst Size and fifo threshold of DMA: */
324 reg
= tilcdc_read(dev
, LCDC_DMA_CTRL_REG
) & ~0x00000770;
325 switch (info
->dma_burst_sz
) {
327 reg
|= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1
);
330 reg
|= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2
);
333 reg
|= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4
);
336 reg
|= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8
);
339 reg
|= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16
);
342 dev_err(dev
->dev
, "invalid burst size\n");
345 reg
|= (info
->fifo_th
<< 8);
346 tilcdc_write(dev
, LCDC_DMA_CTRL_REG
, reg
);
348 /* Configure timings: */
349 hbp
= mode
->htotal
- mode
->hsync_end
;
350 hfp
= mode
->hsync_start
- mode
->hdisplay
;
351 hsw
= mode
->hsync_end
- mode
->hsync_start
;
352 vbp
= mode
->vtotal
- mode
->vsync_end
;
353 vfp
= mode
->vsync_start
- mode
->vdisplay
;
354 vsw
= mode
->vsync_end
- mode
->vsync_start
;
356 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
357 mode
->hdisplay
, mode
->vdisplay
, hbp
, hfp
, hsw
, vbp
, vfp
, vsw
);
359 /* Set AC Bias Period and Number of Transitions per Interrupt: */
360 reg
= tilcdc_read(dev
, LCDC_RASTER_TIMING_2_REG
) & ~0x000fff00;
361 reg
|= LCDC_AC_BIAS_FREQUENCY(info
->ac_bias
) |
362 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info
->ac_bias_intrpt
);
365 * subtract one from hfp, hbp, hsw because the hardware uses
368 if (priv
->rev
== 2) {
369 /* clear bits we're going to set */
371 reg
|= ((hfp
-1) & 0x300) >> 8;
372 reg
|= ((hbp
-1) & 0x300) >> 4;
373 reg
|= ((hsw
-1) & 0x3c0) << 21;
375 tilcdc_write(dev
, LCDC_RASTER_TIMING_2_REG
, reg
);
377 reg
= (((mode
->hdisplay
>> 4) - 1) << 4) |
378 (((hbp
-1) & 0xff) << 24) |
379 (((hfp
-1) & 0xff) << 16) |
380 (((hsw
-1) & 0x3f) << 10);
382 reg
|= (((mode
->hdisplay
>> 4) - 1) & 0x40) >> 3;
383 tilcdc_write(dev
, LCDC_RASTER_TIMING_0_REG
, reg
);
385 reg
= ((mode
->vdisplay
- 1) & 0x3ff) |
386 ((vbp
& 0xff) << 24) |
387 ((vfp
& 0xff) << 16) |
388 (((vsw
-1) & 0x3f) << 10);
389 tilcdc_write(dev
, LCDC_RASTER_TIMING_1_REG
, reg
);
392 * be sure to set Bit 10 for the V2 LCDC controller,
393 * otherwise limited to 1024 pixels width, stopping
394 * 1920x1080 being supported.
396 if (priv
->rev
== 2) {
397 if ((mode
->vdisplay
- 1) & 0x400) {
398 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
,
401 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
,
406 /* Configure display type: */
407 reg
= tilcdc_read(dev
, LCDC_RASTER_CTRL_REG
) &
408 ~(LCDC_TFT_MODE
| LCDC_MONO_8BIT_MODE
| LCDC_MONOCHROME_MODE
|
409 LCDC_V2_TFT_24BPP_MODE
| LCDC_V2_TFT_24BPP_UNPACK
|
410 0x000ff000 /* Palette Loading Delay bits */);
411 reg
|= LCDC_TFT_MODE
; /* no monochrome/passive support */
412 if (info
->tft_alt_mode
)
413 reg
|= LCDC_TFT_ALT_ENABLE
;
414 if (priv
->rev
== 2) {
415 unsigned int depth
, bpp
;
417 drm_fb_get_bpp_depth(fb
->pixel_format
, &depth
, &bpp
);
422 reg
|= LCDC_V2_TFT_24BPP_UNPACK
;
425 reg
|= LCDC_V2_TFT_24BPP_MODE
;
428 dev_err(dev
->dev
, "invalid pixel format\n");
432 reg
|= info
->fdd
< 12;
433 tilcdc_write(dev
, LCDC_RASTER_CTRL_REG
, reg
);
435 if (info
->invert_pxl_clk
)
436 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_PIXEL_CLOCK
);
438 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_PIXEL_CLOCK
);
441 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_SYNC_CTRL
);
443 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_SYNC_CTRL
);
446 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_SYNC_EDGE
);
448 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_SYNC_EDGE
);
450 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
451 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_HSYNC
);
453 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_HSYNC
);
455 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
456 tilcdc_set(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_VSYNC
);
458 tilcdc_clear(dev
, LCDC_RASTER_TIMING_2_REG
, LCDC_INVERT_VSYNC
);
460 if (info
->raster_order
)
461 tilcdc_set(dev
, LCDC_RASTER_CTRL_REG
, LCDC_RASTER_ORDER
);
463 tilcdc_clear(dev
, LCDC_RASTER_CTRL_REG
, LCDC_RASTER_ORDER
);
465 drm_framebuffer_reference(fb
);
467 set_scanout(crtc
, fb
);
469 tilcdc_crtc_update_clk(crtc
);
471 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
474 static int tilcdc_crtc_atomic_check(struct drm_crtc
*crtc
,
475 struct drm_crtc_state
*state
)
477 struct drm_display_mode
*mode
= &state
->mode
;
480 /* If we are not active we don't care */
484 if (state
->state
->planes
[0].ptr
!= crtc
->primary
||
485 state
->state
->planes
[0].state
== NULL
||
486 state
->state
->planes
[0].state
->crtc
!= crtc
) {
487 dev_dbg(crtc
->dev
->dev
, "CRTC primary plane must be present");
491 ret
= tilcdc_crtc_mode_valid(crtc
, mode
);
493 dev_dbg(crtc
->dev
->dev
, "Mode \"%s\" not valid", mode
->name
);
500 static const struct drm_crtc_funcs tilcdc_crtc_funcs
= {
501 .destroy
= tilcdc_crtc_destroy
,
502 .set_config
= drm_atomic_helper_set_config
,
503 .page_flip
= drm_atomic_helper_page_flip
,
504 .reset
= drm_atomic_helper_crtc_reset
,
505 .atomic_duplicate_state
= drm_atomic_helper_crtc_duplicate_state
,
506 .atomic_destroy_state
= drm_atomic_helper_crtc_destroy_state
,
509 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs
= {
510 .mode_fixup
= tilcdc_crtc_mode_fixup
,
511 .enable
= tilcdc_crtc_enable
,
512 .disable
= tilcdc_crtc_disable
,
513 .atomic_check
= tilcdc_crtc_atomic_check
,
514 .mode_set_nofb
= tilcdc_crtc_mode_set_nofb
,
517 int tilcdc_crtc_max_width(struct drm_crtc
*crtc
)
519 struct drm_device
*dev
= crtc
->dev
;
520 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
525 else if (priv
->rev
== 2)
531 int tilcdc_crtc_mode_valid(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
)
533 struct tilcdc_drm_private
*priv
= crtc
->dev
->dev_private
;
534 unsigned int bandwidth
;
535 uint32_t hbp
, hfp
, hsw
, vbp
, vfp
, vsw
;
538 * check to see if the width is within the range that
539 * the LCD Controller physically supports
541 if (mode
->hdisplay
> tilcdc_crtc_max_width(crtc
))
542 return MODE_VIRTUAL_X
;
544 /* width must be multiple of 16 */
545 if (mode
->hdisplay
& 0xf)
546 return MODE_VIRTUAL_X
;
548 if (mode
->vdisplay
> 2048)
549 return MODE_VIRTUAL_Y
;
551 DBG("Processing mode %dx%d@%d with pixel clock %d",
552 mode
->hdisplay
, mode
->vdisplay
,
553 drm_mode_vrefresh(mode
), mode
->clock
);
555 hbp
= mode
->htotal
- mode
->hsync_end
;
556 hfp
= mode
->hsync_start
- mode
->hdisplay
;
557 hsw
= mode
->hsync_end
- mode
->hsync_start
;
558 vbp
= mode
->vtotal
- mode
->vsync_end
;
559 vfp
= mode
->vsync_start
- mode
->vdisplay
;
560 vsw
= mode
->vsync_end
- mode
->vsync_start
;
562 if ((hbp
-1) & ~0x3ff) {
563 DBG("Pruning mode: Horizontal Back Porch out of range");
564 return MODE_HBLANK_WIDE
;
567 if ((hfp
-1) & ~0x3ff) {
568 DBG("Pruning mode: Horizontal Front Porch out of range");
569 return MODE_HBLANK_WIDE
;
572 if ((hsw
-1) & ~0x3ff) {
573 DBG("Pruning mode: Horizontal Sync Width out of range");
574 return MODE_HSYNC_WIDE
;
578 DBG("Pruning mode: Vertical Back Porch out of range");
579 return MODE_VBLANK_WIDE
;
583 DBG("Pruning mode: Vertical Front Porch out of range");
584 return MODE_VBLANK_WIDE
;
587 if ((vsw
-1) & ~0x3f) {
588 DBG("Pruning mode: Vertical Sync Width out of range");
589 return MODE_VSYNC_WIDE
;
593 * some devices have a maximum allowed pixel clock
594 * configured from the DT
596 if (mode
->clock
> priv
->max_pixelclock
) {
597 DBG("Pruning mode: pixel clock too high");
598 return MODE_CLOCK_HIGH
;
602 * some devices further limit the max horizontal resolution
603 * configured from the DT
605 if (mode
->hdisplay
> priv
->max_width
)
606 return MODE_BAD_WIDTH
;
608 /* filter out modes that would require too much memory bandwidth: */
609 bandwidth
= mode
->hdisplay
* mode
->vdisplay
*
610 drm_mode_vrefresh(mode
);
611 if (bandwidth
> priv
->max_bandwidth
) {
612 DBG("Pruning mode: exceeds defined bandwidth limit");
619 void tilcdc_crtc_set_panel_info(struct drm_crtc
*crtc
,
620 const struct tilcdc_panel_info
*info
)
622 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
623 tilcdc_crtc
->info
= info
;
626 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc
*crtc
,
627 bool simulate_vesa_sync
)
629 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
631 tilcdc_crtc
->simulate_vesa_sync
= simulate_vesa_sync
;
634 void tilcdc_crtc_update_clk(struct drm_crtc
*crtc
)
636 struct drm_device
*dev
= crtc
->dev
;
637 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
638 unsigned long lcd_clk
;
639 const unsigned clkdiv
= 2; /* using a fixed divider of 2 */
642 pm_runtime_get_sync(dev
->dev
);
644 tilcdc_crtc_disable(crtc
);
646 /* mode.clock is in KHz, set_rate wants parameter in Hz */
647 ret
= clk_set_rate(priv
->clk
, crtc
->mode
.clock
* 1000 * clkdiv
);
649 dev_err(dev
->dev
, "failed to set display clock rate to: %d\n",
654 lcd_clk
= clk_get_rate(priv
->clk
);
656 DBG("lcd_clk=%lu, mode clock=%d, div=%u",
657 lcd_clk
, crtc
->mode
.clock
, clkdiv
);
659 /* Configure the LCD clock divisor. */
660 tilcdc_write(dev
, LCDC_CTRL_REG
, LCDC_CLK_DIVISOR(clkdiv
) |
664 tilcdc_set(dev
, LCDC_CLK_ENABLE_REG
,
665 LCDC_V2_DMA_CLK_EN
| LCDC_V2_LIDD_CLK_EN
|
666 LCDC_V2_CORE_CLK_EN
);
668 if (tilcdc_crtc_is_on(crtc
))
669 tilcdc_crtc_enable(crtc
);
672 pm_runtime_put_sync(dev
->dev
);
675 #define SYNC_LOST_COUNT_LIMIT 50
677 irqreturn_t
tilcdc_crtc_irq(struct drm_crtc
*crtc
)
679 struct tilcdc_crtc
*tilcdc_crtc
= to_tilcdc_crtc(crtc
);
680 struct drm_device
*dev
= crtc
->dev
;
681 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
684 stat
= tilcdc_read_irqstatus(dev
);
685 tilcdc_clear_irqstatus(dev
, stat
);
687 if (stat
& LCDC_END_OF_FRAME0
) {
689 bool skip_event
= false;
694 drm_flip_work_commit(&tilcdc_crtc
->unref_work
, priv
->wq
);
696 spin_lock_irqsave(&tilcdc_crtc
->irq_lock
, flags
);
698 tilcdc_crtc
->last_vblank
= now
;
700 if (tilcdc_crtc
->next_fb
) {
701 set_scanout(crtc
, tilcdc_crtc
->next_fb
);
702 tilcdc_crtc
->next_fb
= NULL
;
706 spin_unlock_irqrestore(&tilcdc_crtc
->irq_lock
, flags
);
708 drm_crtc_handle_vblank(crtc
);
711 struct drm_pending_vblank_event
*event
;
713 spin_lock_irqsave(&dev
->event_lock
, flags
);
715 event
= tilcdc_crtc
->event
;
716 tilcdc_crtc
->event
= NULL
;
718 drm_crtc_send_vblank_event(crtc
, event
);
720 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
723 if (tilcdc_crtc
->frame_intact
)
724 tilcdc_crtc
->sync_lost_count
= 0;
726 tilcdc_crtc
->frame_intact
= true;
729 if (stat
& LCDC_FIFO_UNDERFLOW
)
730 dev_err_ratelimited(dev
->dev
, "%s(0x%08x): FIFO underfow",
733 /* For revision 2 only */
734 if (priv
->rev
== 2) {
735 if (stat
& LCDC_FRAME_DONE
) {
736 tilcdc_crtc
->frame_done
= true;
737 wake_up(&tilcdc_crtc
->frame_done_wq
);
740 if (stat
& LCDC_SYNC_LOST
) {
741 dev_err_ratelimited(dev
->dev
, "%s(0x%08x): Sync lost",
743 tilcdc_crtc
->frame_intact
= false;
744 if (tilcdc_crtc
->sync_lost_count
++ >
745 SYNC_LOST_COUNT_LIMIT
) {
746 dev_err(dev
->dev
, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__
, stat
);
747 tilcdc_write(dev
, LCDC_INT_ENABLE_CLR_REG
,
752 /* Indicate to LCDC that the interrupt service routine has
753 * completed, see 13.3.6.1.6 in AM335x TRM.
755 tilcdc_write(dev
, LCDC_END_OF_INT_IND_REG
, 0);
761 struct drm_crtc
*tilcdc_crtc_create(struct drm_device
*dev
)
763 struct tilcdc_drm_private
*priv
= dev
->dev_private
;
764 struct tilcdc_crtc
*tilcdc_crtc
;
765 struct drm_crtc
*crtc
;
768 tilcdc_crtc
= devm_kzalloc(dev
->dev
, sizeof(*tilcdc_crtc
), GFP_KERNEL
);
770 dev_err(dev
->dev
, "allocation failed\n");
774 crtc
= &tilcdc_crtc
->base
;
776 ret
= tilcdc_plane_init(dev
, &tilcdc_crtc
->primary
);
780 init_waitqueue_head(&tilcdc_crtc
->frame_done_wq
);
782 drm_flip_work_init(&tilcdc_crtc
->unref_work
,
783 "unref", unref_worker
);
785 spin_lock_init(&tilcdc_crtc
->irq_lock
);
787 ret
= drm_crtc_init_with_planes(dev
, crtc
,
788 &tilcdc_crtc
->primary
,
795 drm_crtc_helper_add(crtc
, &tilcdc_crtc_helper_funcs
);
797 if (priv
->is_componentized
) {
798 struct device_node
*ports
=
799 of_get_child_by_name(dev
->dev
->of_node
, "ports");
802 crtc
->port
= of_get_child_by_name(ports
, "port");
806 of_get_child_by_name(dev
->dev
->of_node
, "port");
808 if (!crtc
->port
) { /* This should never happen */
809 dev_err(dev
->dev
, "Port node not found in %s\n",
810 dev
->dev
->of_node
->full_name
);
818 tilcdc_crtc_destroy(crtc
);